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cvdp_problems.json

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+[
+  {
+    "source": "cvdp",
+    "file": "cvdp_v1.0.1_example_nonagentic_code_generation_commercial_with_solutions.jsonl",
+    "line": 1,
+    "id": "cvdp_copilot_gf_multiplier_0039",
+    "categories": [
+      "cid012",
+      "easy"
+    ],
+    "input": {
+      "prompt": "Develop a testbench to generate stimuli for the gf_multiplier module, which performs polynomial multiplication in GF(2<sup>4</sup>) for two 4-bit inputs (`A` and `B`).\n\n---\n## Description\n\n---\n## Inputs\n\n- **Registers**: `A` and `B` are 4-bit registers that provide binary inputs to the module.\n\n---\n## Outputs\n\n- **GF(2<sup>4</sup>) Product Output**: A 4-bit register, `result`, which indicates the polynomial multiplication result over GF(2<sup>4</sup>).\n\n---\n## Instantiation\n\n- **Module Instance**: The `gf_multiplier` module is instantiated as `uut`, with the input and output signals connected for testing.\n\n---\n## Input Generation and Validation\n\n- **Random Input Generation**: The testbench must generate pairs of 4-bit binary values for `A` and `B` to cover all possibilities, including corner cases.\n- **Stabilization Period**: After setting each pair of inputs, the testbench waits 10 time units to ensure the outputs have stabilized before applying new values.\n\n---\n\nFollows the specification for building the RTL of the module, use it as reference for the verification environment too:\n\n### Module interface\n\n1. **Inputs**:\n   - `A [3:0]` and `B [3:0]`: These are the 4-bit data inputs for the GF(2<sup>4</sup>) multiplication.\n\n2. **Output**:\n   - `result [3:0]`: This 4-bit output holds the product of `A` and `B` under GF(2<sup>4</sup>) using the irreducible polynomial \\( x<sup>4</sup> + x + 1 \\).\n\n3. **Module Functionality**:\n   - **Polynomial Multiplication**: For each bit of `B`, the partial product is formed by `A` and reduced modulo the irreducible polynomial if overflow occurs. The final XOR-based accumulation provides the 4-bit `result`.",
+      "context": {}
+    },
+    "output": {
+      "response": "",
+      "context": {
+        "verif/gf_multiplier_tb.sv": "`timescale 1ns/1ps\n\nmodule gf_multiplier_tb;\n    reg  [3:0] A, B;\n    wire [3:0] result;\n    \n    // Instantiate the gf_multiplier module\n    gf_multiplier uut (\n        .A(A),\n        .B(B),\n        .result(result)\n    );\n    \n    initial begin\n        // Optional: create a VCD file for waveform viewing\n        $dumpfile(\"gf_multiplier_tb.vcd\");\n        $dumpvars(0, gf_multiplier_tb);\n        \n        // Testcase 1\n        A = 4'h0; B = 4'h0;\n        #5;\n        $display(\"TC1  : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 2\n        A = 4'h0; B = 4'h1;\n        #5;\n        $display(\"TC2  : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 3\n        A = 4'h1; B = 4'h0;\n        #5;\n        $display(\"TC3  : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 4\n        A = 4'h1; B = 4'h1;\n        #5;\n        $display(\"TC4  : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 5\n        A = 4'h3; B = 4'h4;\n        #5;\n        $display(\"TC5  : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 6\n        A = 4'h7; B = 4'h9;\n        #5;\n        $display(\"TC6  : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 7\n        A = 4'ha; B = 4'h5;\n        #5;\n        $display(\"TC7  : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 8\n        A = 4'hf; B = 4'hf;\n        #5;\n        $display(\"TC8  : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 9\n        A = 4'hc; B = 4'h3;\n        #5;\n        $display(\"TC9  : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 10\n        A = 4'h8; B = 4'h8;\n        #5;\n        $display(\"TC10 : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 11\n        A = 4'hd; B = 4'h2;\n        #5;\n        $display(\"TC11 : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 12\n        A = 4'h2; B = 4'hf;\n        #5;\n        $display(\"TC12 : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 13\n        A = 4'h9; B = 4'h9;\n        #5;\n        $display(\"TC13 : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 14\n        A = 4'h6; B = 4'ha;\n        #5;\n        $display(\"TC14 : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Testcase 15\n        A = 4'h5; B = 4'h7;\n        #5;\n        $display(\"TC15 : A=%h, B=%h -> result=%h\", A, B, result);\n\n        // Finish simulation\n        $finish;\n    end\nendmodule"
+      }
+    },
+    "harness": {
+      "files": {
+        "docker-compose.yml": "services:\n\n  xrun:\n    image: __VERIF_EDA_IMAGE__\n    volumes:\n      - ./src/:/src/:ro # Infrastructure location\n    env_file : ./src/.env\n    command: pytest /src/process.py -v -s\n    networks:\n      - licnetwork\n\nnetworks:\n  licnetwork:\n      name: licnetwork\n      external: true\n",
+        "src/.env": "HASH   = 6eab1a31b4e8dee548340ce2e4b751d4d07e0271\nTARGET = 90",
+        "src/coverage.cmd": "report -metrics overall -out coverage.log",
+        "src/gf_multiplier.sv": "`timescale 1ns/1ps\n\nmodule gf_multiplier (\n    input [3:0] A,     // Multiplicand\n    input [3:0] B,     // Multiplier\n    output reg [3:0] result // Result\n);\n    reg [3:0] temp_result;\n    reg [4:0] multiplicand;\n    reg [4:0] irreducible_poly = 5'b10011; // Irreducible polynomial x^4 + x + 1\n\n    integer i;\n\n    always @(*) begin\n        temp_result = 4'b0000; // Initialize result to zero\n        multiplicand = {1'b0, A}; // Initialize multiplicand, adding an extra bit to handle overflow\n\n        // Perform multiplication using shift-and-add algorithm\n        for (i = 0; i < 4; i = i + 1) begin\n            if (B[i]) begin\n                temp_result = temp_result ^ multiplicand[3:0]; // XOR the multiplicand with result\n            end\n            multiplicand = multiplicand << 1; // Shift the multiplicand left by 1\n            if (multiplicand[4]) begin\n                multiplicand = multiplicand ^ irreducible_poly; // Polynomial reduction if overflow occurs\n            end\n        end\n\n        result = temp_result; // Output the final result\n    end\nendmodule\n",
+        "src/process.py": "import os\nimport re\nimport subprocess\nimport pytest\n\n# ----------------------------------------\n# - Simulate\n# ----------------------------------------\n\[email protected](scope='session')\ndef test_simulate():\n\n    cmd = \"xrun -coverage all /src/gf_multiplier.sv /code/verif/gf_multiplier_tb.sv -covtest test -seed random -covoverwrite\"\n    assert(subprocess.run(cmd, shell=True)), \"Simulation didn't ran correctly.\"\n\n# ----------------------------------------\n# - Generate Coverage\n# ----------------------------------------\n\[email protected](scope='test_simulate')\ndef test_coverage():\n\n    cmd = \"imc -load /code/rundir/cov_work/scope/test -exec /src/coverage.cmd\"\n    assert(subprocess.run(cmd, shell=True)), \"Coverage merge didn't ran correctly.\"\n\n# ----------------------------------------\n# - Report\n# ----------------------------------------\n\[email protected](scope='test_coverage')\ndef test_report():\n\n    metrics = {}\n\n    with open(\"/code/rundir/coverage.log\") as f:\n        lines = f.readlines()\n\n    # ----------------------------------------\n    # - Evaluate Report\n    # ----------------------------------------\n\n    for line in lines[2:]:\n        info = line.split()\n\n        inst = info [0]\n        avg  = info [1]\n        cov  = info [2]\n\n        inst = re.sub(r'[\\W]', '', inst)\n\n        metrics [inst] = {\n            \"Average\" : float(avg[:-1]),\n            \"Covered\" : float(cov[:-1])\n        }\n\n    assert metrics [\"uut\"][\"Average\"] >= float(os.getenv(\"TARGET\")), \"Didn't achieved the required coverage result.\"\n"
+      }
+    },
+    "task_type": "code_generation",
+    "metadata": {
+      "commercial": true,
+      "agentic": true,
+      "has_prompt": true,
+      "has_solution": true,
+      "has_harness": true,
+      "file_size": 7703
+    }
+  },
+  {
+    "source": "cvdp",
+    "file": "cvdp_v1.0.1_example_nonagentic_code_comprehension_with_solutions.jsonl",
+    "line": 1,
+    "id": "cvdp_copilot_barrel_shifter_0031",
+    "categories": [
+      "cid010",
+      "easy"
+    ],
+    "input": {
+      "prompt": "Explain in four sentences why testing circular shifts with `shift_bits = DATA_WIDTH` is critical for ensuring the barrel shifter correctly handles edge cases without introducing unintended behavior or corrupting data integrity.",
+      "context": {
+        "verif/tb.sv": "`timescale 1ns / 1ps\n\nmodule barrel_shifter_tb;\n\n    // Parameters\n    parameter DATA_WIDTH = 16;\n    parameter SHIFT_BITS_WIDTH = 4;\n\n    // DUT Inputs\n    reg [DATA_WIDTH-1:0] data_in;\n    reg [SHIFT_BITS_WIDTH-1:0] shift_bits;\n    reg [2:0] mode;\n    reg left_right;\n    reg [DATA_WIDTH-1:0] mask;\n    reg enable;\n    reg enable_parity;\n\n    // DUT Outputs\n    wire [DATA_WIDTH-1:0] data_out;\n    wire parity_out;\n    wire error;\n\n    // Expected Values\n    reg [DATA_WIDTH-1:0] expected_data_out;\n    reg expected_parity_out;\n    reg expected_error;\n\n    // Instantiate the DUT\n    barrel_shifter #(\n        .data_width(DATA_WIDTH),\n        .shift_bits_width(SHIFT_BITS_WIDTH)\n    ) dut (\n        .data_in(data_in),\n        .shift_bits(shift_bits),\n        .mode(mode),\n        .left_right(left_right),\n        .mask(mask),\n        .enable(enable),\n        .enable_parity(enable_parity),\n        .data_out(data_out),\n        .parity_out(parity_out),\n        .error(error)\n    );\n\n    // Task for analyzing and comparing outputs\n    task analyze_output;\n        input string test_case;\n        begin\n            $display(\"\\n%s\", test_case);\n            $display(\"Inputs: data_in=%h, shift_bits=%d, mode=%b, left_right=%b, mask=%h\", \n                      data_in, shift_bits, mode, left_right, mask);\n            $display(\"Expected: data_out=%h, parity_out=%b, error=%b\", \n                      expected_data_out, expected_parity_out, expected_error);\n            $display(\"Actual:   data_out=%h, parity_out=%b, error=%b\", \n                      data_out, parity_out, error);\n\n            if ((data_out === expected_data_out) && \n                (parity_out === expected_parity_out) && \n                (error === expected_error)) begin\n                $display(\"Result: PASS\");\n            end else begin\n                $display(\"Result: FAIL\");\n            end\n        end\n    endtask\n\n    // Test procedure\n    initial begin\n        $display(\"Starting Barrel Shifter Testbench...\");\n\n        enable = 0;\n        enable_parity = 0;\n\n        // Test 1\n        enable = 1;\n        mode = 3'b000;\n        data_in = 16'h1234;\n        shift_bits = 4;\n\n        left_right = 1;\n        #10;\n        expected_data_out = data_in << shift_bits;\n        expected_parity_out = 0;\n        expected_error = 0;\n        analyze_output(\"Test 1.1\");\n\n        left_right = 0;\n        #10;\n        expected_data_out = data_in >> shift_bits;\n        expected_parity_out = 0;\n        expected_error = 0;\n        analyze_output(\"Test 1.2\");\n\n        // Test 2\n        mode = 3'b001;\n        data_in = 16'hF234; \n        shift_bits = 3;\n\n        left_right = 1;\n        #10;\n        expected_data_out = data_in << shift_bits;\n        expected_parity_out = 0;\n        expected_error = 0;\n        analyze_output(\"Test 2.1\");\n\n        left_right = 0;\n        #10;\n        expected_data_out = $signed(data_in) >>> shift_bits;\n        expected_parity_out = 0;\n        expected_error = 0;\n        analyze_output(\"Test 2.2\");\n\n        // Test 3\n        mode = 3'b010;\n        data_in = 16'h89AB;\n        shift_bits = 4;\n\n        // Left rotate\n        left_right = 1;\n        #10;\n        expected_data_out = (data_in << shift_bits) | (data_in >> (DATA_WIDTH - shift_bits));\n        expected_parity_out = 0;\n        expected_error = 0;\n        analyze_output(\"Test 3.1\");\n\n        // Right rotate\n        left_right = 0;\n        #10;\n        expected_data_out = (data_in >> shift_bits) | (data_in << (DATA_WIDTH - shift_bits));\n        expected_parity_out = 0;\n        expected_error = 0;\n        analyze_output(\"Test 3.2\");\n\n        // Test 4\n        mode = 3'b011;\n        mask = 16'hFF00;\n        data_in = 16'h1234;\n        shift_bits = 8;\n\n        left_right = 1;\n        #10;\n        expected_data_out = (data_in << shift_bits) & mask;\n        expected_parity_out = 0;\n        expected_error = 0;\n        analyze_output(\"Test 4.1\");\n\n        left_right = 0;\n        #10;\n        expected_data_out = (data_in >> shift_bits) & mask;\n        expected_parity_out = 0;\n        expected_error = 0;\n        analyze_output(\"Test 4.2\");\n\n        // Test 5\n        mode = 3'b100;\n        data_in = 16'h0010;\n        shift_bits = 8;\n\n        left_right = 1;\n        #10;\n        expected_data_out = data_in + shift_bits;\n        expected_parity_out = 0;\n        expected_error = 0;\n        analyze_output(\"Test 5.1\");\n\n        left_right = 0;\n        #10;\n        expected_data_out = data_in - shift_bits;\n        expected_parity_out = 0;\n        expected_error = 0;\n        analyze_output(\"Test 5.2\");\n\n        // Test 6\n        mode = 3'b101;\n        data_in = 16'h0840;\n        #10;\n        expected_data_out = 11;  \n        expected_parity_out = 0;\n        expected_error = 0;\n        analyze_output(\"Test 6\");\n\n        // Test 7\n        mode = 3'b110;\n        data_in = 16'h0010;\n        shift_bits = 5;\n\n        left_right = 1;\n        #10;\n        expected_data_out = (data_in + shift_bits) % DATA_WIDTH;\n        expected_parity_out = 0;\n        expected_error = 0;\n        analyze_output(\"Test 7.1\");\n\n        left_right = 0;\n        #10;\n        expected_data_out = (data_in - shift_bits) % DATA_WIDTH;\n        expected_parity_out = 0;\n        expected_error = 0;\n        analyze_output(\"Test 7.2\");\n\n        // Test 8\n        enable_parity = 1;\n        data_in = 16'h1234;\n        mode = 3'b000;\n        shift_bits = 4;\n        left_right = 1;\n        #10;\n        expected_parity_out = ^data_out;\n        expected_data_out = data_in << shift_bits;\n        expected_error = 0;\n        analyze_output(\"Test 8\");\n\n        // Test 9\n        enable_parity = 1;\n        data_in = 16'h1234;\n        mode = 3'b111;\n        shift_bits = 4;\n        left_right = 1;\n        #10;\n        expected_parity_out = ^data_out;\n        expected_data_out = 0;\n        expected_error = 1;\n        analyze_output(\"Test 9\");\n\n        // End of test\n        $display(\"\\nBarrel Shifter Testbench Completed.\");\n        $finish;\n    end\nendmodule",
+        "rtl/barrel_shifter.sv": "module barrel_shifter #(\n    parameter data_width = 16,     \n    parameter shift_bits_width = 4  \n)(\n    input [data_width-1:0] data_in,\n    input [shift_bits_width-1:0] shift_bits,\n    input [2:0] mode,             \n    input left_right,              \n    input [data_width-1:0] mask,   \n    input enable,                  \n    input enable_parity,           \n    output reg [data_width-1:0] data_out,\n    output reg parity_out,        \n    output reg error               \n);\n\nalways @(*) begin\n    if (!enable) begin\n        data_out = data_out;  \n        error = 0;      \n        parity_out = 0;      \n    end else begin\n        error = 0;  \n        case (mode)\n            3'b000: begin  \n                if (shift_bits >= data_width) begin\n                    error = 1;  \n                    data_out = {data_width{1'b0}};\n                end else if (left_right) begin\n                    data_out = data_in << shift_bits;  \n                end else begin\n                    data_out = data_in >> shift_bits;  \n                end\n            end\n            3'b001: begin  \n                if (shift_bits >= data_width) begin\n                    error = 1;  \n                    data_out = {data_width{1'b0}};\n                end else if (left_right) begin\n                    data_out = data_in << shift_bits;  \n                end else begin\n                    data_out = $signed(data_in) >>> shift_bits; \n                end\n            end\n            3'b010: begin \n                if (shift_bits >= data_width) begin\n                    error = 1;  \n                    data_out = {data_width{1'b0}};\n                end else if (left_right) begin\n                    data_out = (data_in << shift_bits) | (data_in >> (data_width - shift_bits)); \n                end else begin\n                    data_out = (data_in >> shift_bits) | (data_in << (data_width - shift_bits));  \n                end\n            end\n            3'b011: begin  \n                if (shift_bits >= data_width) begin\n                    error = 1;  \n                    data_out = {data_width{1'b0}};\n                end else if (left_right) begin\n                    data_out = (data_in << shift_bits) & mask;  \n                end else begin\n                    data_out = (data_in >> shift_bits) & mask;  \n                end\n            end\n            3'b100: begin \n                if (left_right) begin\n                    data_out = data_in + shift_bits;  \n                end else begin\n                    data_out = data_in - shift_bits;  \n                end\n            end\n            3'b101: begin  \n                data_out = 0;\n                for (int i = data_width-1; i >= 0; i = i - 1) begin\n                    if (data_in[i] == 1 && data_out == 0) begin\n                        data_out = i;  \n                    end\n                end\n            end\n            3'b110: begin \n                if (left_right) begin\n                    data_out = (data_in + shift_bits) % data_width; \n                end else begin\n                    data_out = (data_in - shift_bits) % data_width; \n                end\n            end\n            default: begin\n                data_out = {data_width{1'b0}}; \n                error = 1;  \n            end\n        endcase\n    end\n\n    if (enable_parity) begin\n        parity_out = ^data_out; \n    end else begin\n        parity_out = 0;        \n    end\nend\n\nendmodule"
+      }
+    },
+    "output": {
+      "response": "Testing circular shifts with `shift_bits = DATA_WIDTH` checks if the barrel shifter wraps the bits correctly when the shift amount matches the data width. In this case, the output should stay exactly the same as the input since all bits return to their original position. This test helps find bugs like incorrect bit wrapping or shifting errors. Ensuring this works properly is important for systems like encryption or error checking, where bit manipulation must be precise.\n",
+      "context": {}
+    },
+    "harness": {},
+    "task_type": "code_comprehension",
+    "metadata": {
+      "commercial": false,
+      "agentic": true,
+      "has_prompt": true,
+      "has_solution": false,
+      "has_harness": false,
+      "file_size": 10690
+    }
+  },
+  {
+    "source": "cvdp",
+    "file": "cvdp_v1.0.1_example_nonagentic_code_generation_no_commercial_with_solutions.jsonl",
+    "line": 1,
+    "id": "cvdp_copilot_lfsr_0001",
+    "categories": [
+      "cid003",
+      "easy"
+    ],
+    "input": {
+      "prompt": "Design the RTL for an 8-bit Linear Feedback Shift Register (LFSR) by utilizing the primitive polynomial **x<sup>8</sup>+x<sup>6</sup>+x<sup>5</sup>+x+1** under Galois configuration to construct maximal length pseudo-random sequences.\n\n## Design Specification:\n\n- LFSRs configured in the Galois style operate using an internal feedback system. \n- In this arrangement, the feedback taps directly impact specific bits within the shift register.\n- A distinctive characteristic of Galois LFSRs is that only one bit is shifted per clock cycle, with the feedback bit selectively toggling the bits at the designated tap positions.\n- In this setup, the output from the final register undergoes an XOR operation with the outputs of selected register bits, which are determined by the coefficients of the primitive polynomial. For a polynomial of degree n, the positions of non-zero coefficients, excluding the nth and zeroth, are considered when performing the XOR operations.\n\n#### Structure of Galois configuration\n- Registers: A set of flip-flops connected in series, each holding a single bit\n- Feedback mechanism: Feedback is taken from the output of the last flip-flop and applied to various taps (which are bits in the register) using XOR gates\n- Shift: On each clock cycle, the bits are shifted to the right, and the feedback bit is XORed with some of the bits in the registers before shifting\n\n#### Working example\n\nLet `lfsr_out [7:0]` be the 8-bit output of LFSR. Assume `lfsr_out[7]` and `lfsr_out[0]` as MSB and LSBs of the output of 8-bit LFSR under Galois configuration with the polynomial **x<sup>8</sup>+x<sup>6</sup>+x <sup>5</sup>+x+1**\n\nExpanding the coefficients of the polynomial,\n\n**1 . x<sup>8</sup> + 0 . x<sup>7</sup> + 1 . x<sup>6</sup> + 1 . x<sup>5</sup> + 0 . x<sup>4</sup> + 0 . x<sup>3</sup> + 0 . x<sup>2</sup> + 1 . x<sup>1</sup> + 1 . x<sup>0</sup>**\n\nIn this n-degree polynomial, 'n' represents the number of registers and the presence of non-zero coefficients in terms except the n-th term and zeroth term represent the tap positions in the 8-bit LFSR based on Galois configuration. The tap positions define the XOR operation with the final register value. As per the above primitive polynomial, 8 registers are needed to construct the LFSR with 3 XOR operations.\n\nHere, \n`1 . x^6` represents the XOR operation between `lfsr_out[6]` XOR `lfsr_out[0]`\\\n `1 . x^5` represents the XOR operation between `lfsr_out[5]` XOR `lfsr_out[0]`\\\n `1 . x^1` represents the XOR operation between `lfsr_out[1]` XOR `lfsr_out[0]`\\\n\n The LFSR shifts the bits in the following way during every clock cycle. \n\nlfsr_out[7] = lfsr_out[0]\\\nlfsr_out[6] = lfsr_out[7]\\\nlfsr_out[5] = lfsr_out[6] XOR lfsr_out[0]\\\nlfsr_out[4] = lfsr_out[5] XOR lfsr_out[0]\\\nlfsr_out[3] = lfsr_out[4]\\\nlfsr_out[2] = lfsr_out[3]\\\nlfsr_out[1] = lfsr_out[2]\\\nlfsr_out[0] = lfsr_out[1] XOR lfsr_out[0]\n\nWhen the reset is HIGH with the LFSR seed as 8'b10011001 , the `lfsr_out` for a few clock cycles will be as follows:\n\nclk #1 -> lfsr_out = 8'b11111101\\\nclk #2 -> lfsr_out = 8'b11001111\\\nclk #3 -> lfsr_out = 8'b11010110\\\nclk #4 -> lfsr_out = 8'b01101011\\\nclk #5 -> lfsr_out = 8'b10000100\n\n#### Functional requirements:\n- The constructed 8-bit LFSR based on Galois configuration has to generate a maximal length sequence of (2<sup>8</sup> - 1) pseudo-random 8-bit sequences without supporting all-zero seed. In this case, the pseudo-random sequences fall in the range of values between 0000_0001 and 1111_1111\n\n- Following should be the interface of the RTL design of 8-bit LFSR module named `lfsr_8bit`\n\n#### Inputs:\n- `clock (1-bit)`: A single-bit input clock essential for the operation of the 8-bit LFSR, controlling data movement on the positive clock edge. Normally, the clock operates with a 50:50 duty cycle.\n- `reset (1-bit)`: A control signal that asynchronously resets the LFSR output to the initial seed when active LOW.\n- `lfsr_seed (8-bit, array index [7:0])`: An 8-bit initial seed that initializes the LFSR to trigger the pseudo-random sequence generation upon an asynchronous active LOW reset.\n\n#### Output:\n- `lfsr_out (8-bit, array index [7:0])`: Represents the output from the 8-bit LFSR. A new random value is output at each positive clock edge when the value of `reset` is HIGH.",
+      "context": {}
+    },
+    "output": {
+      "response": "",
+      "context": {
+        "rtl/lfsr_8bit.sv": "module lfsr_8bit(input clock,reset,input [7:0] lfsr_seed, output reg [7:0] lfsr_out);\n\tlogic q1,q2,q3;\n\t//Primitive polynomial considered for 8-bit Linear Feedback Shift Register (LFSR) with Galois configuration is x^8+x^6+x^5+x+1 \n\t\n\t//Internal XORing based on primitive polynomial\n\tassign q1 = lfsr_out[6] ^ lfsr_out[0];\n\tassign q2 = lfsr_out[5] ^ lfsr_out[0];\n\tassign q3 = lfsr_out[1] ^ lfsr_out[0];\n\n\talways_ff @(posedge clock or negedge reset)\n\tbegin\n\t\tif (!reset)\n\t\t\tlfsr_out <= lfsr_seed;//If reset is at logic LOW, the initial seed will be loaded into LFSR's 8-bit output\n\t\telse\n\t\t\tlfsr_out <= {lfsr_out[0],lfsr_out[7],q1,q2,lfsr_out[4],lfsr_out[3],lfsr_out[2],q3};//Shift register based on the primitive polynomial\n\tend\nendmodule"
+      }
+    },
+    "harness": {
+      "files": {
+        "Dockerfile": "FROM __OSS_SIM_IMAGE__\nRUN pip install cocotb-bus",
+        "docker-compose.yml": "services:\n\n  direct:\n    build: .\n    volumes:\n      - ./src/:/src/:ro # Infrastructure location\n    env_file    : ./src/.env\n    command     : pytest -s --log-cli-level=INFO -o cache_dir=/rundir/harness/.cache /src/test_runner.py -v\n    # command     : python3 /src/test_runner.py",
+        "src/.env": "SIM             = icarus\nTOPLEVEL_LANG   = verilog\nVERILOG_SOURCES = /code/rtl/lfsr_8bit.sv\nTOPLEVEL        = lfsr_8bit\nMODULE          = test_lfsr\nPYTHONPATH      = /src\nHASH            = d1acc6a3c4a0c29ba7e4695e76d1a864f1c84458",
+        "src/test_lfsr.py": "import cocotb\nimport os\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import FallingEdge, RisingEdge, ClockCycles, Timer, Join\nimport random\n\n# ----------------------------------------\n# - Tests\n# ----------------------------------------\n\nasync def assert_seed(dut, value : int = 0):\n\n    # Assert seed value\n    dut.reset.value = 0\n    dut.lfsr_seed.value = value\n\n    # Synchronize with Falling Edge again\n    await FallingEdge(dut.clock)\n\n    for _ in range(2):\n        await RisingEdge(dut.clock)\n\n    dut.reset.value = 1\n\n    for i in range(256):\n        await RisingEdge(dut.clock)\n        if ((i == 0) or (i == 255)):\n            print(dut.lfsr_out)\n        if (i == 0):\n            first_value = dut.lfsr_out;\n        if (i == 0):\n            q1 = int(dut.lfsr_out[6]) ^ int(dut.lfsr_out[0])\n            q2 = int(dut.lfsr_out[5]) ^ int(dut.lfsr_out[0])\n            q3 = int(dut.lfsr_out[1]) ^ int(dut.lfsr_out[0])\n            lfsr_out =  (int(dut.lfsr_out[0]) << 7) | (int(dut.lfsr_out[7]) << 6) | (q1 << 5) | (q2 << 4) | (int(dut.lfsr_out[4]) << 3) | (int(dut.lfsr_out[3]) << 2) | (int(dut.lfsr_out[2]) << 1) | q3\n            print(\"lfsr_out \",lfsr_out)\n        if (i == 1):\n            second_value = int(dut.lfsr_out.value);\n            print(\"second_value \",second_value)\n        if (i == 255):\n            last_value = dut.lfsr_out;\n    if (first_value == last_value):\n        print(\"Max.length sequence\");\n    if (second_value == lfsr_out):\n        print(\"PRBS next sequence has been checked\")\n    assert second_value == lfsr_out, f\"The computed and DUT 8-bit LFSR sequences are not matching\"\n    assert first_value == last_value, f\"8-bit LFSR doesn't support maximal length sequence\"\n  \n\[email protected]()\nasync def test_non_zero_1(dut):\n\n    # Start clock thread\n    cocotb.start_soon(Clock(dut.clock, 10, units='ns').start())\n\n    # Assert seed and wait\n    seed = int((1.0 - random.random()) * 2 ** 8);\n    print(\"seed_1 \",seed)\n    await assert_seed(dut, seed)\n\[email protected]()\nasync def test_non_zero_2(dut):\n\n    # Start clock thread\n    cocotb.start_soon(Clock(dut.clock, 10, units='ns').start())\n\n  # Assert seed and wait\n    seed = int((1.0 - random.random()) * 2 ** 8)\n    print(\"seed_2 \",seed)\n    await assert_seed(dut, seed)\n    \[email protected]()\nasync def test_non_zero_3(dut):\n\n    # Start clock thread\n    cocotb.start_soon(Clock(dut.clock, 10, units='ns').start())\n\n  # Assert seed and wait\n    seed = int((1.0 - random.random()) * 2 ** 8)\n    print(\"seed_3 \",seed)\n    await assert_seed(dut, seed)\n\n",
+        "src/test_runner.py": "import os\nfrom pathlib import Path\nfrom cocotb.runner import get_runner\nimport re\nimport logging\n\nverilog_sources = os.getenv(\"VERILOG_SOURCES\").split()\ntoplevel_lang   = os.getenv(\"TOPLEVEL_LANG\")\nsim             = os.getenv(\"SIM\", \"icarus\")\ntoplevel        = os.getenv(\"TOPLEVEL\")\nmodule          = os.getenv(\"MODULE\")\nwave            = os.getenv(\"WAVE\")\n\ndef test_runner():\n\n    runner = get_runner(sim)\n    runner.build(\n        sources=verilog_sources,\n        hdl_toplevel=toplevel,\n        # Arguments\n        always=True,\n        clean=True,\n        waves=True,\n        verbose=True,\n        timescale=(\"1ns\", \"1ns\"),\n        log_file=\"build.log\")\n\n    runner.test(hdl_toplevel=toplevel, test_module=module, waves=True)\n\n\nif __name__ == \"__main__\":\n    test_runner()"
+      }
+    },
+    "task_type": "code_generation",
+    "metadata": {
+      "commercial": true,
+      "agentic": true,
+      "has_prompt": true,
+      "has_solution": true,
+      "has_harness": true,
+      "file_size": 9431
+    }
+  },
+  {
+    "source": "cvdp",
+    "file": "cvdp_v1.0.1_example_agentic_code_generation_no_commercial_with_solutions.jsonl",
+    "line": 1,
+    "id": "cvdp_agentic_fixed_arbiter_0001",
+    "categories": [
+      "cid003",
+      "easy"
+    ],
+    "input": {
+      "prompt": "",
+      "context": {}
+    },
+    "output": {
+      "response": "",
+      "context": {}
+    },
+    "harness": {
+      "docker-compose.yml": "services:\n\n  direct:\n    #image: __OSS_SIM_IMAGE__\n    image: __OSS_SIM_IMAGE__\n\n    volumes:\n      - ./src/:/src/:ro # Infrastructure location\n    env_file    : ./src/.env\n    command     : pytest -s --log-cli-level=INFO -o cache_dir=/rundir/harness/.cache /src/test_runner.py -v\n    # command     : python3 /src/test_runner.py\n",
+      "src/.env": "SIM             = icarus\nWAVE            = True\nTOPLEVEL_LANG   = verilog\nVERILOG_SOURCES = /code/rtl/fixed_priority_arbiter.sv\nTOPLEVEL        = fixed_priority_arbiter\nMODULE          = test_fixed_priority_arbiter\nPYTHONPATH      = /src\nHASH            = 0c5518b3c14bf4d0439841379b58e8120707a637",
+      "src/harness_library.py": "from cocotb.triggers import FallingEdge, RisingEdge, Timer\nimport random\nasync def reset_dut(reset_n, duration_ns = 2, active:bool = False):\n    # Restart Interface\n    reset_n.value = 0 if active else 1\n    await Timer(duration_ns, units=\"ns\")\n    reset_n.value = 1 if active else 0\n    await Timer(duration_ns, units='ns')\n    reset_n._log.debug(\"Reset complete\")\n\nasync def duty_cycle(pwm_signal, clock, period):\n    # 0-> time_period, 1-> high_time, 2-> low_time = full_time = high_time\n    pwm = {\"time_period\": period, \"on_time\": 0, \"off_time\": 0}\n    pwm_signal._log.debug(\"Pulse started\")\n    for i in range(period):\n        if pwm_signal.value == 1:\n            pwm[\"on_time\"] += 1\n        await RisingEdge(clock)\n\n    pwm[\"off_time\"] = pwm[\"time_period\"] - pwm[\"on_time\"]\n    pwm_signal._log.debug(\"Time period completed\")\n    return pwm\n\nasync def dut_init(dut):\n    # iterate all the input signals and initialize with 0\n    for signal in dut:\n        if signal._type == \"GPI_NET\":\n            signal.value = 0\n\n# all the element of array dump in to one verable\ndef ary_2_int(arry: list) -> int:\n    if arry is not None:\n        ary = arry.copy()\n        ary.reverse()\n        ary_byt = int(''.join(format(num, '08b') for num in ary), 2)\n        return ary_byt\n    else:\n        raise ValueError\n    \nasync def rnd_clk_dly (clock, low: int = 50, high: int = 100):\n    for i in range(random.randint(50,100)):\n            await RisingEdge(clock)",
+      "src/test_fixed_priority_arbiter.py": "import cocotb\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import RisingEdge, Timer\nimport harness_library as hrs_lb  \n\[email protected]()\nasync def test_fixed_priority_arbiter(dut):\n    \"\"\"Test the fixed_priority_arbiter module.\"\"\"\n\n    # Start the clock with a period of 10ns\n    cocotb.start_soon(Clock(dut.clk, 10, units='ns').start())\n\n    # Initialize the DUT signals\n    await hrs_lb.dut_init(dut)\n\n    # Task: Apply reset (Active High)\n    async def reset_dut(active=True, duration_ns=10):\n        dut.reset.value = active\n        await Timer(duration_ns, units=\"ns\")\n        dut.reset.value = not active\n        await RisingEdge(dut.clk)  # Wait for one clock edge after reset is de-asserted\n\n    # Task: Drive request and optional priority override\n    async def drive_request(request, priority_override=0):\n        dut.req.value = request\n        dut.priority_override.value = priority_override\n        await RisingEdge(dut.clk)\n        await Timer(10, units=\"ns\")  # Wait to observe the output\n\n    # Monitor the signals\n    cocotb.log.info(\"Starting simulation\")\n\n    # Apply a reset to the DUT before starting the test cases\n    await reset_dut(active=True, duration_ns=25)\n\n    # ---------------- Test Case 1: Single Request ----------------\n    await drive_request(0b00001000)  \n    assert dut.grant.value == 0b00001000, f\"Test Case 1 Failed: Expected grant=0b00001000, got grant={dut.grant.value}\"\n    assert dut.grant_index.value == 3, f\"Test Case 1 Failed: Expected grant_index=3, got grant_index={dut.grant_index.value}\"\n    assert dut.valid.value == 1, f\"Test Case 1 Failed: Expected valid=1, got valid={dut.valid.value}\"\n    cocotb.log.info(\"Test Case 1 Passed: Single request granted correctly.\")\n\n    # ---------------- Test Case 2: Multiple Requests (Fixed Priority) ----------------\n    await drive_request(0b00111000)  \n    assert dut.grant.value == 0b00001000, \"Test Case 2 Failed: Incorrect priority handling.\"\n    cocotb.log.info(\"Test Case 2 Passed: Multiple requests handled with fixed priority.\")\n\n    # ---------------- Test Case 3: Priority Override ----------------\n    await drive_request(0b00010010, priority_override=0b00010000)  \n    assert dut.grant.value == 0b00010000, \"Test Case 3 Failed: Priority override did not work.\"\n    cocotb.log.info(\"Test Case 3 Passed: Priority override successful.\")\n\n    # ---------------- Test Case 4: No Requests (Grant Should be Zero) ----------------\n    await drive_request(0b00000000)  \n    assert dut.grant.value == 0b00000000, \"Test Case 4 Failed: Incorrect handling of no requests.\"\n    assert dut.valid.value == 0, \"Test Case 4 Failed: Valid signal should be low when no requests.\"\n    cocotb.log.info(\"Test Case 4 Passed: No requests scenario handled correctly.\")\n\n    # ---------------- Test Case 5: Highest Priority Request Wins ----------------\n    await drive_request(0b10000001)  \n    assert dut.grant.value == 0b00000001, \"Test Case 5 Failed: Incorrect priority decision.\"\n    cocotb.log.info(\"Test Case 5 Passed: Highest priority request wins correctly.\")\n\n    # ---------------- Test Case 6: Changing Requests Dynamically ----------------\n    await drive_request(0b00000010)  \n    assert dut.grant.value == 0b00000010, \"Test Case 6 Failed: Grant did not update correctly.\"\n    cocotb.log.info(\"Test Case 6 Passed: Grant updates dynamically.\")\n\n    await drive_request(0b00000100)  \n    assert dut.grant.value == 0b00000100, \"Test Case 6 Failed: Dynamic request update failed.\"\n    cocotb.log.info(\"Test Case 6 Passed: Dynamic request update confirmed.\")\n\n    # ---------------- Test Case 7: Priority Override While Requests Change ----------------\n    await drive_request(0b00000010, priority_override=0b00100000)  \n    assert dut.grant.value == 0b00100000, \"Test Case 7 Failed: Priority override not applied correctly.\"\n    cocotb.log.info(\"Test Case 7 Passed: Priority override worked dynamically.\")\n\n    await drive_request(0b00010010, priority_override=0b00010000)  \n    assert dut.grant.value == 0b00010000, \"Test Case 7 Failed: Priority override did not take effect.\"\n    cocotb.log.info(\"Test Case 7 Passed: Priority override successfully applied during active requests.\")\n\n    # ---------------- Test Case 8: Reset During Operation ----------------\n    await drive_request(0b00011000)  \n    assert dut.grant.value == 0b00001000, \"Test Case 8 Failed: Incorrect grant before reset.\"\n\n    # Apply reset during active requests\n    await reset_dut(active=False, duration_ns=25)  \n    assert dut.grant.value == 0b00000000, \"Test Case 8 Failed: Grant should be zero after reset.\"\n    assert dut.valid.value == 0, \"Test Case 8 Failed: Valid should be low after reset.\"\n    cocotb.log.info(\"Test Case 8 Passed: Reset handled correctly.\")\n\n    # Log the successful completion of the simulation\n    cocotb.log.info(\"Simulation completed successfully\")\n",
+      "src/test_runner.py": "import os\nfrom cocotb_tools.runner import get_runner\nimport pytest\n\nverilog_sources = os.getenv(\"VERILOG_SOURCES\").split()\nsim             = os.getenv(\"SIM\", \"icarus\")\ntoplevel        = os.getenv(\"TOPLEVEL\")\nmodule          = os.getenv(\"MODULE\")\nwave            = bool(os.getenv(\"WAVE\"))\n\ndef runner(plusargs=[], parameter={}):\n    runner = get_runner(sim)\n    runner.build(\n        sources=verilog_sources,\n        hdl_toplevel=toplevel,\n        # Arguments\n        parameters=parameter,\n        always=True,\n        clean=True,\n        waves=wave,\n        verbose=True,\n        timescale=(\"1ns\", \"1ns\"),\n        log_file=\"sim.log\")\n    runner.test(hdl_toplevel=toplevel, test_module=module, waves=wave, plusargs=plusargs)\n\n\[email protected](\"test\", range(1))\ndef test_areg_param(test):\n        runner()"
+    },
+    "task_type": "code_generation",
+    "metadata": {
+      "commercial": true,
+      "agentic": true,
+      "has_prompt": false,
+      "has_solution": false,
+      "has_harness": true,
+      "file_size": 21413
+    }
+  },
+  {
+    "source": "cvdp",
+    "file": "cvdp_v1.0.1_example_agentic_code_generation_commercial_with_solutions.jsonl",
+    "line": 1,
+    "id": "cvdp_agentic_8x3_priority_encoder_0003",
+    "categories": [
+      "cid014",
+      "easy"
+    ],
+    "input": {
+      "prompt": "",
+      "context": {}
+    },
+    "output": {
+      "response": "",
+      "context": {}
+    },
+    "harness": {
+      "Dockerfile": "FROM __VERIF_EDA_IMAGE__\nRUN pip3 install cocotb",
+      "docker-compose.yml": "services:\n\n  xrun:\n    build: .\n    volumes:\n      - ./src/:/src/:ro\n    env_file : ./src/.env\n    working_dir: /code/rundir\n    command: pytest -s --log-cli-level=INFO -o cache_dir=/rundir/harness/.cache /src/test_runner.py -v\n    networks:\n      - licnetwork\n\nnetworks:\n  licnetwork:\n      name: licnetwork\n      external: true",
+      "src/.env": "INST            = dut\nTARGET          = 100\nSIM             = xcelium\nWAVE            = 1\nTOPLEVEL_LANG   = verilog\nVERILOG_SOURCES = /code/rtl/priority_encoder.sv\nTOPLEVEL        = priority_encoder_8x3\nMODULE          = test_pri_enc_8x3\nPYTHONPATH      = /src\nHASH            = 9fd60da03ffcaf62368a25f0af15eff46b511dba",
+      "src/harness_library.py": "\nfrom cocotb.triggers import FallingEdge, RisingEdge, Timer\nfrom cocotb.runner import get_runner\nimport random\nimport struct\nimport os\nimport subprocess\nimport re\n\ndef runner(module, toplevel, src:str, plusargs:list =[], args:tuple = (), parameter:dict={}, wave:bool = False, sim:str = \"icarus\"):\n    runner = get_runner(sim)\n    runner.build(\n        sources=src,\n        hdl_toplevel=toplevel,\n        # Arguments\n        parameters=parameter,\n        # compiler args\n        build_args=args,\n        always=True,\n        clean=True,\n        waves=wave,\n        verbose=True,\n        timescale=(\"1ns\", \"1ns\"),\n        log_file=\"build.log\")\n    runner.test(hdl_toplevel=toplevel, test_module=module, waves=wave, plusargs=plusargs, log_file=\"sim.log\")\n\ndef coverage_report(asrt_type:str):\n    '''asrt_type: assertion, toggle, overall'''\n    cmd = f\"imc -load /code/rundir/sim_build/cov_work/scope/test -execcmd \\\"report -metrics {asrt_type} -all -aspect sim -assertionStatus -overwrite -text -out coverage.log\\\"\"\n    assert(subprocess.run(cmd, shell=True)), \"Coverage merge didn't ran correctly.\"\n\ndef covt_report_check():\n\n    metrics = {}\n\n    with open(\"/code/rundir/coverage.log\") as f:\n        lines = f.readlines()\n\n    # ----------------------------------------\n    # - Evaluate Report\n    # ----------------------------------------\n    column = re.split(r'\\s{2,}', lines[0].strip())\n    for line in lines[2:]:\n        info = re.split(r'\\s{2,}', line.strip())\n        inst = info[0].lstrip('|-')\n        metrics [inst] = {column[i]: info[i].split('%')[0] for i in range(1, len(column))}\n\n    print(\"Metrics:\")\n    print(metrics)\n\n    if \"Overall Average\" in metrics[os.getenv(\"TOPLEVEL\")]:\n        assert float(metrics[os.getenv(\"TOPLEVEL\")][\"Overall Average\"]) >= float(os.getenv(\"TARGET\")), \"Didn't achieved the required coverage result.\"\n    elif \"Assertion\" in metrics[os.getenv(\"TOPLEVEL\")]:\n        assert float(metrics[os.getenv(\"TOPLEVEL\")][\"Assertion\"]) >= 100.00, \"Didn't achieved the required coverage result.\"\n    elif \"Toggle\" in metrics[os.getenv(\"TOPLEVEL\")]:\n        assert float(metrics[os.getenv(\"TOPLEVEL\")][\"Toggle\"]) >= float(os.getenv(\"TARGET\")), \"Didn't achieved the required coverage result.\"\n    elif \"Block\" in metrics[os.getenv(\"TOPLEVEL\")]:\n        assert float(metrics[os.getenv(\"TOPLEVEL\")][\"Block\"]) >= float(os.getenv(\"TARGET\")), \"Didn't achieved the required coverage result.\"\n    else:\n        assert False, \"Couldn't find the required coverage result.\"\n\ndef save_vcd(wave:bool, toplevel:str, new_name:str):\n    if wave:\n        os.makedirs(\"vcd\", exist_ok=True)\n        os.rename(f'./sim_build/{toplevel}.fst', f'./vcd/{new_name}.fst')\n\nasync def reset_dut(reset_n, duration_ns = 10, active:bool = False):\n    # Restart Interface\n    reset_n.value = 1 if active else 0\n    await Timer(duration_ns, units=\"ns\")\n    reset_n.value = 0 if active else 1\n    await Timer(duration_ns, units='ns')\n    reset_n._log.debug(\"Reset complete\")\n\nasync def duty_cycle(pwm_signal, clock, period):\n    # 0-> time_period, 1-> high_time, 2-> low_time = full_time = high_time\n    pwm = {\"time_period\": period, \"on_time\": 0, \"off_time\": 0}\n    pwm_signal._log.debug(\"Pulse started\")\n    for i in range(period):\n        if pwm_signal.value == 1:\n            pwm[\"on_time\"] += 1\n        await RisingEdge(clock)\n\n    pwm[\"off_time\"] = pwm[\"time_period\"] - pwm[\"on_time\"]\n    pwm_signal._log.debug(\"Time period completed\")\n    return pwm\n\nasync def dut_init(dut):\n    # iterate all the input signals and initialize with 0\n    for signal in dut:\n        if signal._type == \"GPI_NET\":\n            signal.value = 0\n\n# all the element of array dump in to one verable\ndef ary_2_int(arry: list, ewdth: int=8) -> int:\n    if arry is not None:\n        ary = arry.copy()\n        ary.reverse()\n        ary_byt = int(''.join(format(num, f'0{ewdth}b') for num in ary), 2)\n        return ary_byt\n    else:\n        raise ValueError\n    \nasync def rnd_clk_dly (clock, low: int = 50, high: int = 100):\n    for i in range(random.randint(50,100)):\n            await RisingEdge(clock)\n\n# converitng floating point number in scientific notation binary format\ndef float_to_binary(num: float):\n    # Convert float to 32-bit binary representation\n    packed_num = struct.pack('!f', num)  # Packs the float into 32 bits using IEEE 754\n    binary_representation = ''.join(f'{byte:08b}' for byte in packed_num)\n\n    sign = binary_representation[0]\n    exponent = binary_representation[1:9]\n    mantissa = binary_representation[9:]\n\n    return sign, exponent, mantissa\n\ndef highbit_number(number: int, length=8,  msb=True) -> int:\n    str_num = bin(number)[2:].zfill(length)\n    print(str_num)\n    if str_num.count('1') == 0:\n        return 0\n    elif msb:\n        return length - str_num.index('1') - 1\n    else:\n        return str_num[::-1].index('1')",
+      "src/test_pri_enc_8x3.py": "import cocotb\nfrom cocotb.triggers import Timer\nimport harness_library as hrs_lb\nfrom math import ceil, log2\n\n# ----------------------------------------\n# - Tests\n# ----------------------------------------\n\[email protected]()\nasync def test_penc(dut):\n    # initialize the DUT and wait for a short time\n    await hrs_lb.dut_init(dut)\n    await Timer(10, units=\"ns\")\n\n    for index in range(256):\n        print(\"input value =\", bin(index))\n        dut._id(\"in\", extended=False).value = index\n        await Timer(10, units=\"ns\")\n        msb_1_bit_num = hrs_lb.highbit_number(index, msb=True, length=8)\n\n        # ----------------------------------------\n        # - Check No Operation\n        # ----------------------------------------\n        assert (dut.out.value == msb_1_bit_num), f\"encoder input = {index} and output is {dut.out.value} expecting {msb_1_bit_num}\"",
+      "src/test_runner.py": "import os\nimport harness_library as hrs_lb\nimport random\nimport pytest\n\n# Fetch environment variables for Verilog source setup\nverilog_sources = os.getenv(\"VERILOG_SOURCES\").split()\ntoplevel_lang   = os.getenv(\"TOPLEVEL_LANG\")\nsim             = os.getenv(\"SIM\", \"icarus\")\ntoplevel        = os.getenv(\"TOPLEVEL\")\nmodule          = os.getenv(\"MODULE\")\nwave            = os.getenv(\"WAVE\")\n\[email protected](\"test\", range(1))\ndef test_pri_enc(test):\n    encoder_in = random.randint(0, 255)\n    plusargs=[f'+encoder_in={encoder_in}']\n    try:\n        args = []\n        if sim == \"xcelium\":\n            args=(\"-coverage all\",\" -covoverwrite\", \"-sv\", \"-covtest test\", \"-svseed random\")\n        \n        hrs_lb.runner(wave = wave, toplevel = toplevel, plusargs=plusargs, module = module, src=verilog_sources, sim=sim, args=args)\n        hrs_lb.coverage_report(\"assertion\")\n        hrs_lb.covt_report_check()\n    except SystemExit:\n        # hrs_lb.save_vcd(wave, toplevel, new_name=f\"prioroty_encoder_{tst_seq}_test\")\n        raise SystemError(\"simulation failed due to assertion failed in your test\")\n\n# if __name__ == \"__main__\":\n#     test_simulate()"
+    },
+    "task_type": "code_generation",
+    "metadata": {
+      "commercial": true,
+      "agentic": true,
+      "has_prompt": false,
+      "has_solution": false,
+      "has_harness": true,
+      "file_size": 14732
+    }
+  }
+]