uploaded from leia
Browse files- .gitattributes +12 -0
- VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf +3 -0
- VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q2_K.gguf +3 -0
- VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_L.gguf +3 -0
- VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_M.gguf +3 -0
- VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_S.gguf +3 -0
- VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_M.gguf +3 -0
- VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_S.gguf +3 -0
- VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_M.gguf +3 -0
- VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_S.gguf +3 -0
- VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q6_K.gguf +3 -0
- VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q8_0.gguf +3 -0
- VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.f16.gguf +3 -0
.gitattributes
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*.zip filter=lfs diff=lfs merge=lfs -text
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*.zst filter=lfs diff=lfs merge=lfs -text
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*tfevents* filter=lfs diff=lfs merge=lfs -text
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VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf filter=lfs diff=lfs merge=lfs -text
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VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q2_K.gguf filter=lfs diff=lfs merge=lfs -text
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VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_L.gguf filter=lfs diff=lfs merge=lfs -text
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VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_M.gguf filter=lfs diff=lfs merge=lfs -text
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