sonyashijin commited on
Commit
ab73327
·
verified ·
1 Parent(s): 901b049

Add LoRA adapter configuration

Browse files
Files changed (1) hide show
  1. adapter_config.json +14 -15
adapter_config.json CHANGED
@@ -1,19 +1,19 @@
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  {
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- "task_type": "text-generation",
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  "peft_type": "LORA",
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  "auto_mapping": null,
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  "base_model_name_or_path": "Qwen/Qwen3-32B",
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  "revision": null,
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- "inference_mode": "vllm-adapter",
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  "r": 32,
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  "target_modules": [
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- "gate_proj",
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- "v_proj",
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- "down_proj",
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- "up_proj",
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  "k_proj",
 
 
 
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  "q_proj",
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- "o_proj"
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  ],
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  "exclude_modules": null,
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  "lora_alpha": 32,
@@ -39,12 +39,11 @@
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  "ephemeral_gpu_offload": false
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  },
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  "lora_bias": false,
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- "library_name": "vllm",
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- "tags": [
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- "verilog",
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- "hardware-design",
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- "code-generation",
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- "lora"
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- ],
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- "license": "apache-2.0"
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  }
 
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  {
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+ "task_type": "CAUSAL_LM",
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  "peft_type": "LORA",
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  "auto_mapping": null,
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  "base_model_name_or_path": "Qwen/Qwen3-32B",
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  "revision": null,
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+ "inference_mode": false,
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  "r": 32,
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  "target_modules": [
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+ "o_proj",
 
 
 
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  "k_proj",
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+ "up_proj",
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+ "v_proj",
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+ "gate_proj",
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  "q_proj",
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+ "down_proj"
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  ],
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  "exclude_modules": null,
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  "lora_alpha": 32,
 
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  "ephemeral_gpu_offload": false
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  },
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  "lora_bias": false,
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+ "_verl_training_info": {
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+ "algorithm": "GRPO",
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+ "task": "verilog_code_generation",
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+ "original_base_model_path": "/dev/shm/verl-cache/49dc1026f3bd52528db07ca11dcb8ffe/Qwen3-32B",
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+ "lora_rank": 32,
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+ "lora_alpha": 32
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+ }
 
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  }