Spaces:
Running
Running
[ | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 96.15, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 86.12, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 81.54, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 64.9, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 81.28, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 64.49, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 79.15, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 73.33, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 78.09, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 65.64, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 79.28, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 71.15, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": -1.0, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 95.38, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 91.76, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 81.54, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 62.35, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 81.41, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 62.35, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 80.27, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 52.12, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 78.69, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 62.25, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 79.99, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1-0528", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 65.32, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-0528", | |
"Params": 685, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 97.18, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 89.8, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 79.74, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 65.71, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 79.62, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 63.27, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 78.33, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 71.34, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 76.49, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 64.06, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 78.19, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 70.08, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": -1.0, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 97.44, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 96.47, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 79.49, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 60.0, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 79.49, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 60.0, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 78.27, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 50.25, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 76.43, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 60.15, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 77.96, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 63.07, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1", | |
"Params": 685, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 87.44, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 77.14, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 58.97, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 45.71, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 58.85, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 41.63, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 57.58, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 50.88, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 55.93, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 32.44, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 56.13, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 43.45, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 34.62, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 88.59, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 95.29, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 56.15, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 52.94, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 55.9, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 52.94, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 55.13, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 49.22, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 53.45, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 52.52, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 54.48, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.1 405B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 55.31, | |
"Model URL": "https://huggingface.co/RedHatAI/Meta-Llama-3.1-405B-FP8", | |
"Params": 406, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 91.28, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 73.88, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 76.92, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 51.43, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 76.79, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 48.57, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 75.25, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 54.61, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 73.56, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 46.37, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 75.67, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 50.47, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 41.94, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 82.18, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 87.06, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 69.62, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 49.41, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 69.62, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 49.41, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 69.04, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 41.82, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 66.89, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 49.64, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 69.15, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen3 236B A22B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 49.99, | |
"Model URL": "https://huggingface.co/Qwen/Qwen3-235B-A22B", | |
"Params": 235, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 66.15, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 73.88, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 40.64, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 42.45, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 40.64, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 39.18, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 40.46, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 40.81, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 38.08, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 38.14, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 39.86, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 39.65, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 28.72, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 84.74, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 89.41, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 41.67, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 51.76, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 41.67, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 51.76, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 41.38, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 50.61, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 39.75, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 51.76, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 41.36, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Llama 3.(1-3) 70B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 51.88, | |
"Model URL": "https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct", | |
"Params": 70.6, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 82.18, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 79.59, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 52.44, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 45.31, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 51.92, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 44.08, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 51.83, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 46.47, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 48.75, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 45.4, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 50.09, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 47.65, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 37.44, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 80.9, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 84.71, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 52.95, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 35.29, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 52.69, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 35.29, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 51.66, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 35.82, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 49.37, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 35.2, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 51.18, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 72B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 35.94, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-72B-Instruct", | |
"Params": 72.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 87.95, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 82.45, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 66.41, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 56.73, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 66.41, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 52.24, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 66.15, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 55.83, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 63.8, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 51.91, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 65.12, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 56.07, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": -1.0, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 58.97, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 68.24, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 40.0, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 42.35, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 39.62, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 42.35, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 39.4, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 40.9, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 37.53, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 42.31, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 39.1, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwQ 32B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 42.87, | |
"Model URL": "https://huggingface.co/Qwen/QwQ-32B", | |
"Params": 32.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 88.59, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 84.08, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 52.56, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 50.2, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 52.18, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 46.12, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 52.32, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 49.73, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 49.43, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 46.43, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 50.82, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 50.43, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 28.93, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 93.21, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 85.88, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 41.54, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 32.94, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 41.54, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 32.94, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 41.31, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 30.65, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 40.48, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 33.11, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 41.23, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "Qwen2.5 32B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 32.5, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-32B", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 88.46, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 84.9, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 37.95, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 44.49, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 37.95, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 44.08, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 37.56, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 46.95, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 35.3, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 43.22, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 37.19, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 46.65, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 13.42, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 79.74, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 92.94, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 36.41, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 51.76, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 36.03, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 51.76, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 36.08, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 46.3, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 34.91, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 51.49, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 35.76, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "StarChat2 15B v0.1", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 52.8, | |
"Model URL": "https://huggingface.co/HuggingFaceH4/starchat2-15b-v0.1", | |
"Params": 16, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 42.18, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 34.69, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 25.51, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 18.37, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 25.51, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 16.33, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 25.36, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 17.86, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 24.19, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 16.48, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 25.27, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 17.33, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": -1.0, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 45.0, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 44.71, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 25.64, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 21.18, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 25.26, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 21.18, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 24.79, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 17.65, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 23.48, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 21.08, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 24.63, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek R1 Distill Qwen 14B", | |
"Model Type": "General", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 21.29, | |
"Model URL": "https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Qwen-14B", | |
"Params": 14.8, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 67.05, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 69.8, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 33.08, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 36.33, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 33.08, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 34.29, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 32.69, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 37.19, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 31.46, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 34.29, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 32.44, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 35.95, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 24.33, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 90.77, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 88.24, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 33.33, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 35.29, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 33.33, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 35.29, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 33.02, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 34.03, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 30.8, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 35.15, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 32.99, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeLlama 70B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 35.21, | |
"Model URL": "https://huggingface.co/codellama/CodeLlama-70b-hf", | |
"Params": 69, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 62.82, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 83.67, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 23.33, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 42.45, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 23.08, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 42.04, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 22.86, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 42.29, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 22.81, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 39.42, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 22.29, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 42.71, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 24.58, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 75.26, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 88.24, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 39.62, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 31.76, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 39.36, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 31.76, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 38.23, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 32.16, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 36.79, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 31.46, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 37.9, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 33B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 32.12, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-33b-instruct", | |
"Params": 33.3, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 87.18, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 77.96, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 45.0, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 43.27, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 44.87, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 43.27, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 44.25, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 46.82, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 43.03, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 43.2, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 43.76, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 45.42, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 31.07, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 83.72, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 87.06, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 45.64, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 42.35, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 45.13, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 42.35, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 44.59, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 42.79, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 43.01, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 42.24, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 44.55, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 32B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 43.25, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-32B-Instruct", | |
"Params": 32.5, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 78.97, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 81.63, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 37.82, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 46.12, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 37.44, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 45.31, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 35.94, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 45.82, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 34.83, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 44.64, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 35.18, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 46.05, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 37.53, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 80.0, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 83.53, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 41.67, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 35.29, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 41.15, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 35.29, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 40.74, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 34.17, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 39.2, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 35.32, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 40.83, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 34.67, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-14B-Instruct", | |
"Params": 14.7, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 43.85, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 39.59, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 28.08, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 23.67, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 28.08, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 22.04, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 27.94, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 25.0, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 26.26, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 22.0, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 27.77, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 23.15, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": -1.0, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 61.92, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 48.24, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 34.1, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 23.53, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 33.72, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 23.53, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 33.7, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 21.18, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 32.17, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 23.43, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 33.67, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "DeepCoder 14B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 23.65, | |
"Model URL": "https://huggingface.co/agentica-org/DeepCoder-14B-Preview", | |
"Params": 14.8, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 78.21, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 75.92, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 28.46, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 42.86, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 27.82, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 40.82, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 27.34, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 41.36, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 25.95, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 39.77, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 27.11, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 41.36, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 16.17, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 80.0, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 95.29, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 35.64, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 41.18, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 35.38, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 41.18, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 35.12, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 37.69, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 33.47, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 41.05, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 35.13, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OpenCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 41.55, | |
"Model URL": "https://huggingface.co/infly/OpenCoder-8B-Instruct", | |
"Params": 7.77, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 91.41, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 85.31, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 53.46, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 47.35, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 53.33, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 46.53, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 52.86, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 49.42, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 50.62, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 45.6, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 51.65, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 49.59, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 28.23, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 77.44, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 94.12, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 37.31, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 30.59, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 37.31, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 27.06, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 37.32, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 23.53, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 35.35, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 26.92, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 36.89, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 27.23, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Instruct", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 67.82, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 53.47, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 49.23, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 30.2, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 49.23, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 29.39, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 48.92, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 32.04, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 46.76, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 28.64, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 47.87, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 29.99, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": -1.0, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 83.33, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 78.82, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 48.21, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 50.59, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 48.08, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 50.59, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 47.78, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 41.74, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 45.44, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 50.02, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 47.06, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "SeedCoder 8B Reasoning", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 52.92, | |
"Model URL": "https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Reasoning-bf16", | |
"Params": 8.25, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 20.13, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 76.33, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 6.92, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 38.78, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 6.67, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 37.14, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 6.51, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 40.65, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 6.63, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 37.25, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 6.56, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 39.58, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 28.33, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 74.1, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 90.59, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 33.72, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 32.94, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 33.72, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 32.94, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 33.59, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 30.67, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 31.78, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 33.01, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 33.62, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "QwenCoder 2.5 7B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 33.51, | |
"Model URL": "https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct", | |
"Params": 7.61, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 82.05, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 78.78, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 29.62, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 41.22, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 29.49, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 38.78, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 29.51, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 42.62, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 27.73, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 39.33, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 29.41, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 43.3, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 24.63, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 67.18, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 84.71, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 31.67, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 24.71, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 29.87, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 24.71, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 29.78, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 23.53, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 27.98, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 24.5, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 29.21, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "DeepSeek Coder 6,7B", | |
"Model Type": "Coding", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 24.79, | |
"Model URL": "https://huggingface.co/deepseek-ai/deepseek-coder-6.7b-instruct", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 54.87, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 32.24, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 24.62, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 16.33, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 24.62, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 15.92, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 24.28, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 16.03, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 22.78, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 14.71, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 24.06, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 16.0, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 14.77, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 60.51, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 85.88, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 27.05, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 36.47, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 27.05, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 36.47, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 26.94, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 34.63, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 25.22, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 36.55, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 26.87, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder Mistral", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 37.64, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-v1.1", | |
"Params": 7.24, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 84.62, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 73.06, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 39.49, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 37.14, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 39.49, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 34.69, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 38.91, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 34.3, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 37.52, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 32.76, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 38.55, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 33.69, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 19.35, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 77.31, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 85.88, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 36.92, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 40.0, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 36.79, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 40.0, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 36.94, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 35.57, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 34.84, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 39.83, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 36.62, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "RTLCoder DeepSeek", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 39.6, | |
"Model URL": "https://huggingface.co/ishorn5/RTLCoder-Deepseek-v1.1", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 96.15, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 81.63, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 54.23, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 50.61, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 54.23, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 50.61, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 54.29, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 53.1, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 51.57, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 50.86, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 53.15, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 53.44, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 17.07, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 92.44, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 98.82, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 50.77, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 58.82, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 50.77, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 58.82, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 50.95, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 54.14, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 48.53, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 58.81, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 50.51, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "OriGen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 61.4, | |
"Model URL": "https://huggingface.co/henryen/OriGen", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 56.92, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 73.06, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 33.33, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 49.8, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 33.33, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 47.35, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 32.58, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 49.25, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 32.01, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 47.45, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 32.45, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 49.01, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": -1.0, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 92.69, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 89.41, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 21.28, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 49.41, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 21.28, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 49.41, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 21.04, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 43.68, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 19.59, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 49.06, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 21.05, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "CodeV R1 Distill Qwen 7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 49.91, | |
"Model URL": "https://huggingface.co/zhuyaoyu/CodeV-R1-Distill-Qwen-7B", | |
"Params": 7.62, | |
"Release": "V2" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 93.33, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 80.41, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 47.31, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 42.86, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 46.15, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 41.22, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 45.08, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 40.59, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 44.26, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 38.83, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 44.68, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 40.53, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 25.14, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 93.59, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 100.0, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 50.13, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 47.06, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 49.49, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 47.06, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 47.55, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 46.6, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 47.05, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 47.14, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 47.09, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "HaVen-CodeQwen", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 46.67, | |
"Model URL": "https://huggingface.co/yangyiyao/HaVen-CodeQwen", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 32.18, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 48.16, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 13.08, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 24.49, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 12.95, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 21.63, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 12.8, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 22.25, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 12.51, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 20.59, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 12.82, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 21.29, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 12.27, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 92.05, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 98.82, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 31.79, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 43.53, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 31.79, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 43.53, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 31.74, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 42.25, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 29.45, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 43.46, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 31.61, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-CL-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 43.2, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-CL-7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 45.38, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 68.16, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 19.62, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 34.29, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 18.97, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 26.53, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 18.91, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 28.14, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 18.71, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 21.8, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 18.85, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 26.5, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 20.94, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 93.33, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 100.0, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 52.31, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 48.24, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 51.54, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 48.24, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 51.69, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 48.14, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 48.79, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 48.18, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 51.45, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-QW-7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 48.81, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-QW-7B", | |
"Params": 7.25, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Syntax (STX)", | |
"Result": 33.59, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Syntax (STX)", | |
"Result": 67.35, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Functionality (FNC)", | |
"Result": 15.0, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Functionality (FNC)", | |
"Result": 38.78, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Synthesis (SYN)", | |
"Result": 15.0, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Synthesis (SYN)", | |
"Result": 37.14, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Power", | |
"Result": 15.1, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Power", | |
"Result": 35.56, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Performance", | |
"Result": 14.46, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Performance", | |
"Result": 35.13, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval S2R", | |
"Task": "Area", | |
"Result": 14.85, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTLLM", | |
"Task": "Area", | |
"Result": 35.88, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "RTL-Repo", | |
"Task": "Exact Matching (EM)", | |
"Result": 21.26, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Syntax (STX)", | |
"Result": 95.51, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Syntax (STX)", | |
"Result": 100.0, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Functionality (FNC)", | |
"Result": 47.05, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Functionality (FNC)", | |
"Result": 50.59, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Synthesis (SYN)", | |
"Result": 47.05, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Synthesis (SYN)", | |
"Result": 50.59, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Power", | |
"Result": 47.37, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Power", | |
"Result": 50.47, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Performance", | |
"Result": 44.35, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Performance", | |
"Result": 50.54, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VerilogEval MC", | |
"Task": "Area", | |
"Result": 46.52, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
}, | |
{ | |
"Model": "CodeV-DS-6.7B", | |
"Model Type": "RTL-Specific", | |
"Benchmark": "VeriGen", | |
"Task": "Area", | |
"Result": 50.36, | |
"Model URL": "https://huggingface.co/yang-z/CodeV-DS-6.7B", | |
"Params": 6.74, | |
"Release": "V1" | |
} | |
] |