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.gitattributes CHANGED
@@ -33,3 +33,15 @@ saved_model/**/* filter=lfs diff=lfs merge=lfs -text
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  *.zip filter=lfs diff=lfs merge=lfs -text
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  *.zst filter=lfs diff=lfs merge=lfs -text
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  *.zip filter=lfs diff=lfs merge=lfs -text
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  *.zst filter=lfs diff=lfs merge=lfs -text
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  *tfevents* filter=lfs diff=lfs merge=lfs -text
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+ VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q2_K.gguf filter=lfs diff=lfs merge=lfs -text
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+ VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q3_K_L.gguf filter=lfs diff=lfs merge=lfs -text
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+ VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q3_K_M.gguf filter=lfs diff=lfs merge=lfs -text
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+ VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q3_K_S.gguf filter=lfs diff=lfs merge=lfs -text
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+ VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q4_0.gguf filter=lfs diff=lfs merge=lfs -text
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+ VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q4_K_M.gguf filter=lfs diff=lfs merge=lfs -text
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+ VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q4_K_S.gguf filter=lfs diff=lfs merge=lfs -text
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+ VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q5_0.gguf filter=lfs diff=lfs merge=lfs -text
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+ VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q5_K_M.gguf filter=lfs diff=lfs merge=lfs -text
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+ VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q5_K_S.gguf filter=lfs diff=lfs merge=lfs -text
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+ VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q6_K.gguf filter=lfs diff=lfs merge=lfs -text
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+ VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q8_0.gguf filter=lfs diff=lfs merge=lfs -text
README.md ADDED
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+ ---
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+ library_name: transformers
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+ tags:
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+ - verilog
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+ - reasoning
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+ - reinforcement-learning
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+ - rtl
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+ - TensorBlock
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+ - GGUF
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+ base_model: Nellyw888/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb
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+ ---
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+
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+ <div style="width: auto; margin-left: auto; margin-right: auto">
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+ <img src="https://i.imgur.com/jC7kdl8.jpeg" alt="TensorBlock" style="width: 100%; min-width: 400px; display: block; margin: auto;">
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+ </div>
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+
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+ [![Website](https://img.shields.io/badge/Website-tensorblock.co-blue?logo=google-chrome&logoColor=white)](https://tensorblock.co)
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+ [![Twitter](https://img.shields.io/twitter/follow/tensorblock_aoi?style=social)](https://twitter.com/tensorblock_aoi)
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+ [![Discord](https://img.shields.io/badge/Discord-Join%20Us-5865F2?logo=discord&logoColor=white)](https://discord.gg/Ej5NmeHFf2)
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+ [![GitHub](https://img.shields.io/badge/GitHub-TensorBlock-black?logo=github&logoColor=white)](https://github.com/TensorBlock)
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+ [![Telegram](https://img.shields.io/badge/Telegram-Group-blue?logo=telegram)](https://t.me/TensorBlock)
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+
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+
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+ ## Nellyw888/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb - GGUF
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+
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+ <div style="text-align: left; margin: 20px 0;">
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+ <a href="https://discord.com/invite/Ej5NmeHFf2" style="display: inline-block; padding: 10px 20px; background-color: #5865F2; color: white; text-decoration: none; border-radius: 5px; font-weight: bold;">
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+ Join our Discord to learn more about what we're building ↗
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+ </a>
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+ </div>
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+
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+ This repo contains GGUF format model files for [Nellyw888/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb](https://huggingface.co/Nellyw888/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb).
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+
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+ The files were quantized using machines provided by [TensorBlock](https://tensorblock.co/), and they are compatible with llama.cpp as of [commit b5753](https://github.com/ggml-org/llama.cpp/commit/73e53dc834c0a2336cd104473af6897197b96277).
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+
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+ ## Our projects
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+ <table border="1" cellspacing="0" cellpadding="10">
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+ <tr>
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+ <th colspan="2" style="font-size: 25px;">Forge</th>
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+ </tr>
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+ <tr>
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+ <th colspan="2">
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+ <img src="https://imgur.com/faI5UKh.jpeg" alt="Forge Project" width="900"/>
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+ </th>
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+ </tr>
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+ <tr>
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+ <th colspan="2">An OpenAI-compatible multi-provider routing layer.</th>
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+ </tr>
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+ <tr>
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+ <th colspan="2">
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+ <a href="https://github.com/TensorBlock/forge" target="_blank" style="
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+ display: inline-block;
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+ padding: 8px 16px;
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+ background-color: #FF7F50;
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+ color: white;
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+ text-decoration: none;
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+ border-radius: 6px;
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+ font-weight: bold;
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+ font-family: sans-serif;
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+ ">🚀 Try it now! 🚀</a>
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+ </th>
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+ </tr>
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+
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+ <tr>
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+ <th style="font-size: 25px;">Awesome MCP Servers</th>
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+ <th style="font-size: 25px;">TensorBlock Studio</th>
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+ </tr>
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+ <tr>
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+ <th><img src="https://imgur.com/2Xov7B7.jpeg" alt="MCP Servers" width="450"/></th>
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+ <th><img src="https://imgur.com/pJcmF5u.jpeg" alt="Studio" width="450"/></th>
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+ </tr>
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+ <tr>
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+ <th>A comprehensive collection of Model Context Protocol (MCP) servers.</th>
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+ <th>A lightweight, open, and extensible multi-LLM interaction studio.</th>
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+ </tr>
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+ <tr>
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+ <th>
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+ <a href="https://github.com/TensorBlock/awesome-mcp-servers" target="_blank" style="
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+ display: inline-block;
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+ padding: 8px 16px;
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+ background-color: #FF7F50;
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+ color: white;
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+ text-decoration: none;
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+ border-radius: 6px;
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+ font-weight: bold;
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+ font-family: sans-serif;
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+ ">👀 See what we built 👀</a>
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+ </th>
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+ <th>
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+ <a href="https://github.com/TensorBlock/TensorBlock-Studio" target="_blank" style="
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+ display: inline-block;
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+ padding: 8px 16px;
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+ background-color: #FF7F50;
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+ color: white;
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+ text-decoration: none;
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+ border-radius: 6px;
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+ font-weight: bold;
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+ font-family: sans-serif;
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+ ">👀 See what we built 👀</a>
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+ </th>
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+ </tr>
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+ </table>
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+
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+ ## Prompt template
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+
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+ ```
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+ <s>[INST] <<SYS>>
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+ {system_prompt}
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+ <</SYS>>
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+
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+ {prompt} [/INST]
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+ ```
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+
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+ ## Model file specification
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+
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+ | Filename | Quant type | File Size | Description |
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+ | -------- | ---------- | --------- | ----------- |
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+ | [VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q2_K.gguf](https://huggingface.co/tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/blob/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q2_K.gguf) | Q2_K | 2.533 GB | smallest, significant quality loss - not recommended for most purposes |
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+ | [VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q3_K_S.gguf](https://huggingface.co/tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/blob/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q3_K_S.gguf) | Q3_K_S | 2.948 GB | very small, high quality loss |
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+ | [VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q3_K_M.gguf](https://huggingface.co/tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/blob/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q3_K_M.gguf) | Q3_K_M | 3.298 GB | very small, high quality loss |
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+ | [VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q3_K_L.gguf](https://huggingface.co/tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/blob/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q3_K_L.gguf) | Q3_K_L | 3.597 GB | small, substantial quality loss |
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+ | [VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q4_0.gguf](https://huggingface.co/tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/blob/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q4_0.gguf) | Q4_0 | 3.826 GB | legacy; small, very high quality loss - prefer using Q3_K_M |
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+ | [VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q4_K_S.gguf](https://huggingface.co/tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/blob/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q4_K_S.gguf) | Q4_K_S | 3.857 GB | small, greater quality loss |
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+ | [VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q4_K_M.gguf](https://huggingface.co/tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/blob/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q4_K_M.gguf) | Q4_K_M | 4.081 GB | medium, balanced quality - recommended |
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+ | [VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q5_0.gguf](https://huggingface.co/tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/blob/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q5_0.gguf) | Q5_0 | 4.652 GB | legacy; medium, balanced quality - prefer using Q4_K_M |
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+ | [VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q5_K_S.gguf](https://huggingface.co/tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/blob/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q5_K_S.gguf) | Q5_K_S | 4.652 GB | large, low quality loss - recommended |
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+ | [VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q5_K_M.gguf](https://huggingface.co/tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/blob/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q5_K_M.gguf) | Q5_K_M | 4.783 GB | large, very low quality loss - recommended |
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+ | [VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q6_K.gguf](https://huggingface.co/tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/blob/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q6_K.gguf) | Q6_K | 5.529 GB | very large, extremely low quality loss |
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+ | [VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q8_0.gguf](https://huggingface.co/tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/blob/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q8_0.gguf) | Q8_0 | 7.161 GB | very large, extremely low quality loss - not recommended |
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+
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+
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+ ## Downloading instruction
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+
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+ ### Command line
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+
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+ Firstly, install Huggingface Client
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+
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+ ```shell
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+ pip install -U "huggingface_hub[cli]"
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+ ```
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+
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+ Then, downoad the individual model file the a local directory
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+
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+ ```shell
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+ huggingface-cli download tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF --include "VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-Q2_K.gguf" --local-dir MY_LOCAL_DIR
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+ ```
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+
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+ If you wanna download multiple model files with a pattern (e.g., `*Q4_K*gguf`), you can try:
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+
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+ ```shell
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+ huggingface-cli download tensorblock/Nellyw888_VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF --local-dir MY_LOCAL_DIR --local-dir-use-symlinks False --include='*Q4_K*gguf'
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+ ```
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