Commit
·
a3c7b4a
1
Parent(s):
7e94263
Fix hacky ldrd instruction in ARM32
Browse files- pyproject.toml +1 -1
- remend/disassemble.py +11 -15
pyproject.toml
CHANGED
@@ -15,7 +15,7 @@ classifiers = [
|
|
15 |
requires-python = ">=3.9"
|
16 |
dependencies = [
|
17 |
"networkx",
|
18 |
-
"capstone",
|
19 |
"Levenshtein",
|
20 |
"tqdm",
|
21 |
"numpy",
|
|
|
15 |
requires-python = ">=3.9"
|
16 |
dependencies = [
|
17 |
"networkx",
|
18 |
+
"capstone==5.0.3",
|
19 |
"Levenshtein",
|
20 |
"tqdm",
|
21 |
"numpy",
|
remend/disassemble.py
CHANGED
@@ -142,25 +142,21 @@ class DisassemblerARM32(DisassemblerBase):
|
|
142 |
def check_ldrd(self, insn):
|
143 |
if insn.id != ARM_INS_LDRD:
|
144 |
return False
|
145 |
-
ops = insn.
|
146 |
if len(ops) != 3:
|
147 |
return False
|
148 |
-
|
149 |
-
if mem[0] != "[" or mem[-1] != "]":
|
150 |
return False
|
151 |
-
|
152 |
-
if
|
153 |
-
|
154 |
-
|
155 |
-
|
156 |
-
if basereg not in self.reg_values:
|
157 |
-
return False
|
158 |
-
base = align4(self.reg_values[basereg])
|
159 |
-
if len(memcomps) == 3:
|
160 |
-
offset = int(memcomps[2][1:])
|
161 |
else:
|
162 |
-
|
163 |
-
addr
|
|
|
|
|
164 |
fhex = self.loader.memory.load(addr, 8)
|
165 |
fval = struct.unpack("d", fhex)[0]
|
166 |
return fval, addr, 8
|
|
|
142 |
def check_ldrd(self, insn):
|
143 |
if insn.id != ARM_INS_LDRD:
|
144 |
return False
|
145 |
+
ops = list(insn.operands)
|
146 |
if len(ops) != 3:
|
147 |
return False
|
148 |
+
if ops[2].type != ARM_OP_MEM:
|
|
|
149 |
return False
|
150 |
+
mem = ops[2].value.mem
|
151 |
+
if mem.base == ARM_REG_PC:
|
152 |
+
addr = align4(insn.address + 4) + mem.disp
|
153 |
+
elif mem.base in self.reg_values:
|
154 |
+
addr = align4(self.reg_values[mem.base]) + mem.disp
|
|
|
|
|
|
|
|
|
|
|
155 |
else:
|
156 |
+
return False
|
157 |
+
if addr < self.loader.min_addr or addr + 8 > self.loader.max_addr:
|
158 |
+
# Out of bounds
|
159 |
+
return False
|
160 |
fhex = self.loader.memory.load(addr, 8)
|
161 |
fval = struct.unpack("d", fhex)[0]
|
162 |
return fval, addr, 8
|