Add pipeline tag, link to project page (#1)

- Add pipeline tag, link to project page (777f6fa55cd8aac371d4de321e683e6befa788f6)


Co-authored-by: Niels Rogge <[email protected]>

README.md

@@ -4,9 +4,12 @@ base_model:
 library_name: transformers
 tags:
 - verilog
+pipeline_tag: text-generation
 ---
+
 ## CodeV-R1-Qwen-7B
 
+[Project page](https://iprc-dip.github.io/CodeV-R1)
 
 ### 1. Introduction
 
@@ -78,7 +81,9 @@ vllm serve zhuyaoyu/CodeV-R1-Distill-Qwen-7B --tensor-parallel-size 2 --max-mode
 During training and evaluation, we use a system prompt
 
 ```
-You are a helpful assistant. The assistant first thinks about the reasoning process in the mind and then provides the user with the answer. The reasoning process and answer are enclosed within <think> </think> and<answer> </answer> tags, respectively, i.e., <think> reasoning process here </think><answer> answer here </answer>.  Now the user asks you to write verilog code. After thinking, when you finally reach a conclusion, enclose the final verilog code in ```verilog ``` within <answer> </answer> tags. i.e., <answer> ```verilog\n module top_module(in, out, ...) ... ``` </answer>.\n
+You are a helpful assistant. The assistant first thinks about the reasoning process in the mind and then provides the user with the answer. The reasoning process and answer are enclosed within <think> </think> and<answer> </answer> tags, respectively, i.e., <think> reasoning process here </think><answer> answer here </answer>.  Now the user asks you to write verilog code. After thinking, when you finally reach a conclusion, enclose the final verilog code in ```verilog ``` within <answer> </answer> tags. i.e., <answer> ```verilog
+ module top_module(in, out, ...) ... ``` </answer>.
+
 ```
 
 It is recommended to use this prompt during inference.