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ahmedheakl
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asm_cuda_to_amd

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uid
int64
0
19.8k
cuda_device
stringlengths
17
263M
cuda_host
stringlengths
1.59k
4.6M
amd_device
stringlengths
650
65M
amd_host
stringlengths
462
5.8M
num_cuda_device_tokens
int64
8
32.9M
num_cuda_host_tokens
int64
734
2.6M
num_amd_device_tokens
int64
301
33.8M
num_amd_host_tokens
int64
194
3.12M
100
code for sm_80 Function : _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R5, SR_CTAID.X ; ULDC UR4, c[0x0][0x1ac] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1b0] ; UIADD3 UR4, UR4, -0x1, URZ ; S2R R2, SR_TID.X ; ISETP.NE.AND P0, PT, R5, UR4, PT ; SEL R0, R0, c[0x0][0x1a8], !P0 ; ISETP.GE.AND P0, PT, R2, R0, PT ; @P0 EXIT ; IMAD.MOV.U32 R0, RZ, RZ, 0x8 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD R5, R5, c[0x0][0x1a8], R2 ; IMAD.WIDE R2, R5, R0, c[0x0][0x170] ; LDG.E.64 R2, [R2.64] ; F2I.F64.TRUNC R4, R2 ; ISETP.NE.AND P0, PT, R4, 0x1, PT ; @P0 EXIT ; IMAD.SHL.U32 R8, R5, 0x8, RZ ; SHF.R.S32.HI R2, RZ, 0x1f, R5 ; SHF.L.U64.HI R6, R5, 0x3, R2 ; IADD3 R12, P0, R8, c[0x0][0x1a0], RZ ; IADD3.X R13, R6, c[0x0][0x1a4], RZ, P0, !PT ; IADD3 R10, P0, R8, c[0x0][0x198], RZ ; LDG.E.64 R2, [R12.64] ; IADD3.X R11, R6, c[0x0][0x19c], RZ, P0, !PT ; LDG.E.64 R4, [R10.64] ; IADD3 R8, P0, R8, c[0x0][0x168], RZ ; IADD3.X R9, R6, c[0x0][0x16c], RZ, P0, !PT ; LDG.E.64 R6, [R8.64] ; BSSY B0, 0xd60 ; CS2R R12, SRZ ; F2I.F64.TRUNC R3, R2 ; F2I.F64.TRUNC R5, R4 ; ISETP.NE.AND P0, PT, R3, 0x1, PT ; F2I.F64.TRUNC R6, R6 ; SEL R30, RZ, 0x1, P0 ; ISETP.GT.AND P0, PT, R5, R30, PT ; @!P0 BRA 0xd50 ; IMAD.IADD R2, R5, 0x1, -R30.reuse ; BSSY B1, 0x5f0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x190] ; CS2R R12, SRZ ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x194] ; LOP3.LUT P0, R29, R2, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x188] ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x18c] ; IMAD.MOV.U32 R7, RZ, RZ, R30 ; @!P0 BRA 0x5e0 ; IMAD.IADD R13, R6, 0x1, R30.reuse ; IMAD.MOV.U32 R7, RZ, RZ, R30 ; IMAD.WIDE R32, R13, R0, c[0x0][0x190] ; IMAD.WIDE R34, R13, R0, c[0x0][0x188] ; IMAD.WIDE R12, R13, R0, c[0x0][0x160] ; IMAD.MOV.U32 R0, RZ, RZ, R12 ; IMAD.MOV.U32 R17, RZ, RZ, R13 ; CS2R R12, SRZ ; LDG.E.64 R18, [R34.64] ; IMAD.MOV.U32 R24, RZ, RZ, R0 ; IMAD.MOV.U32 R25, RZ, RZ, R17 ; LDG.E.64 R14, [R24.64] ; IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; BSSY B2, 0x4f0 ; MUFU.RCP64H R21, R19 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R16, -R18, R20, 1 ; DFMA R16, R16, R16, R16 ; DFMA R16, R20, R16, R20 ; DFMA R22, -R18, R16, 1 ; DFMA R22, R16, R22, R16 ; DMUL R20, R14, R22 ; DFMA R16, -R18, R20, R14 ; DFMA R36, R22, R16, R20 ; FFMA R0, RZ, R19, R37 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x4e0 ; MOV R4, 0x4e0 ; CALL.REL.NOINC 0xde0 ; BSYNC B2 ; IMAD.MOV.U32 R14, RZ, RZ, R32 ; STG.E.64 [R24.64], R36 ; IMAD.MOV.U32 R15, RZ, RZ, R33 ; LDG.E.64 R14, [R14.64] ; IADD3 R29, R29, -0x1, RZ ; IADD3 R34, P2, R34, 0x8, RZ ; ISETP.NE.AND P0, PT, R29, RZ, PT ; IADD3 R0, P3, R24, 0x8, RZ ; IMAD.X R35, RZ, RZ, R35, P2 ; IADD3 R32, P1, R32, 0x8, RZ ; IADD3 R7, R7, 0x1, RZ ; IMAD.X R17, RZ, RZ, R25, P3 ; IMAD.X R33, RZ, RZ, R33, P1 ; DFMA R12, R14, R36, R12 ; @P0 BRA 0x390 ; BSYNC B1 ; LOP3.LUT R0, RZ, R30, RZ, 0x33, !PT ; IMAD.IADD R0, R5, 0x1, R0 ; ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; @!P0 BRA 0xd50 ; IMAD.IADD R31, R6, 0x1, R7 ; IMAD.MOV.U32 R30, RZ, RZ, c[0x0][0x160] ; IMAD.MOV.U32 R29, RZ, RZ, c[0x0][0x164] ; IMAD.WIDE R32, R31, 0x8, R10 ; LDG.E.64 R18, [R32.64] ; IMAD.MOV.U32 R28, RZ, RZ, R30 ; IMAD.WIDE R34, R31, 0x8, R28 ; LDG.E.64 R14, [R34.64] ; IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; BSSY B1, 0x7f0 ; MUFU.RCP64H R17, R19 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R20, -R18, R16, 1 ; DFMA R20, R20, R20, R20 ; DFMA R20, R16, R20, R16 ; DFMA R22, -R18, R20, 1 ; DFMA R22, R20, R22, R20 ; DMUL R20, R14, R22 ; DFMA R16, -R18, R20, R14 ; DFMA R20, R22, R16, R20 ; FFMA R0, RZ, R19, R21 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7e0 ; MOV R4, 0x7c0 ; CALL.REL.NOINC 0xde0 ; IMAD.MOV.U32 R20, RZ, RZ, R36 ; IMAD.MOV.U32 R21, RZ, RZ, R37 ; BSYNC B1 ; STG.E.64 [R34.64], R20 ; LDG.E.64 R18, [R32.64+0x8] ; LDG.E.64 R14, [R34.64+0x8] ; IMAD.WIDE R24, R31, 0x8, R8 ; LDG.E.64 R16, [R24.64] ; IMAD.MOV.U32 R26, RZ, RZ, 0x1 ; BSSY B1, 0x970 ; MUFU.RCP64H R27, R19 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R12, R16, R20, R12 ; DFMA R22, -R18, R26, 1 ; DFMA R22, R22, R22, R22 ; DFMA R22, R26, R22, R26 ; DFMA R26, -R18, R22, 1 ; DFMA R26, R22, R26, R22 ; DMUL R22, R14, R26 ; DFMA R36, -R18, R22, R14 ; DFMA R36, R26, R36, R22 ; FFMA R0, RZ, R19, R37 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x960 ; MOV R4, 0x960 ; CALL.REL.NOINC 0xde0 ; BSYNC B1 ; STG.E.64 [R34.64+0x8], R36 ; LDG.E.64 R18, [R32.64+0x10] ; LDG.E.64 R14, [R34.64+0x10] ; LDG.E.64 R26, [R24.64+0x8] ; IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; BSSY B1, 0xb00 ; MUFU.RCP64H R21, R19 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R12, R26, R36, R12 ; DFMA R16, -R18, R20, 1 ; DFMA R16, R16, R16, R16 ; DFMA R16, R20, R16, R20 ; DFMA R22, -R18, R16, 1 ; DFMA R22, R16, R22, R16 ; DMUL R20, R14, R22 ; DFMA R16, -R18, R20, R14 ; DFMA R16, R22, R16, R20 ; FFMA R0, RZ, R19, R17 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xaf0 ; MOV R4, 0xad0 ; CALL.REL.NOINC 0xde0 ; IMAD.MOV.U32 R16, RZ, RZ, R36 ; IMAD.MOV.U32 R17, RZ, RZ, R37 ; BSYNC B1 ; STG.E.64 [R34.64+0x10], R16 ; LDG.E.64 R18, [R32.64+0x18] ; LDG.E.64 R14, [R34.64+0x18] ; LDG.E.64 R36, [R24.64+0x10] ; IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; BSSY B1, 0xc90 ; MUFU.RCP64H R23, R19 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R12, R36, R16, R12 ; DFMA R20, -R18, R22, 1 ; DFMA R20, R20, R20, R20 ; DFMA R20, R22, R20, R22 ; DFMA R26, -R18, R20, 1 ; DFMA R26, R20, R26, R20 ; DMUL R22, R14, R26 ; DFMA R20, -R18, R22, R14 ; DFMA R20, R26, R20, R22 ; FFMA R0, RZ, R19, R21 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xc80 ; MOV R4, 0xc60 ; CALL.REL.NOINC 0xde0 ; IMAD.MOV.U32 R20, RZ, RZ, R36 ; IMAD.MOV.U32 R21, RZ, RZ, R37 ; BSYNC B1 ; STG.E.64 [R34.64+0x18], R20 ; LDG.E.64 R24, [R24.64+0x18] ; IADD3 R7, R7, 0x4, RZ ; IADD3 R8, P1, R8, 0x20, RZ ; ISETP.GE.AND P0, PT, R7, R5, PT ; IADD3 R10, P2, R10, 0x20, RZ ; IMAD.X R9, RZ, RZ, R9, P1 ; IADD3 R30, P3, R30, 0x20, RZ ; IMAD.X R11, RZ, RZ, R11, P2 ; IMAD.X R29, RZ, RZ, R29, P3 ; DFMA R12, R24, R20, R12 ; @!P0 BRA 0x660 ; BSYNC B0 ; ISETP.NE.AND P0, PT, R3, 0x1, PT ; @P0 EXIT ; IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; LDG.E.64 R2, [R6.64] ; DADD R2, R2, -R12 ; STG.E.64 [R6.64], R2 ; EXIT ; FSETP.GEU.AND P2, PT, |R15|, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R2, RZ, RZ, 0x1ca00000 ; FSETP.GEU.AND P0, PT, |R19|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R20, RZ, RZ, R14 ; LOP3.LUT R16, R19, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R36, RZ, RZ, 0x1 ; LOP3.LUT R26, R15, 0x7ff00000, RZ, 0xc0, !PT ; BSSY B3, 0x1380 ; LOP3.LUT R17, R16, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R16, RZ, RZ, R18 ; LOP3.LUT R27, R19, 0x7ff00000, RZ, 0xc0, !PT ; @!P2 LOP3.LUT R21, R19, 0x7ff00000, RZ, 0xc0, !PT ; @!P2 IMAD.MOV.U32 R22, RZ, RZ, RZ ; @!P0 DMUL R16, R18, 8.98846567431157953865e+307 ; ISETP.GE.U32.AND P1, PT, R26.reuse, R27, PT ; @!P2 ISETP.GE.U32.AND P3, PT, R26, R21, PT ; SEL R21, R2.reuse, 0x63400000, !P1 ; MUFU.RCP64H R37, R17 ; @!P2 SEL R23, R2, 0x63400000, !P3 ; LOP3.LUT R21, R21, 0x800fffff, R15, 0xf8, !PT ; @!P2 LOP3.LUT R0, R23, 0x80000000, R15, 0xf8, !PT ; @!P0 LOP3.LUT R27, R17, 0x7ff00000, RZ, 0xc0, !PT ; @!P2 LOP3.LUT R23, R0, 0x100000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R0, RZ, RZ, R26 ; @!P2 DFMA R20, R20, 2, -R22 ; DFMA R22, R36, -R16, 1 ; DFMA R22, R22, R22, R22 ; @!P2 LOP3.LUT R0, R21, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R28, R0, -0x1, RZ ; DFMA R36, R36, R22, R36 ; ISETP.GT.U32.AND P0, PT, R28, 0x7feffffe, PT ; IADD3 R28, R27, -0x1, RZ ; DFMA R38, R36, -R16, 1 ; ISETP.GT.U32.OR P0, PT, R28, 0x7feffffe, P0 ; DFMA R38, R36, R38, R36 ; DMUL R36, R38, R20 ; DFMA R22, R36, -R16, R20 ; DFMA R22, R38, R22, R36 ; @P0 BRA 0x1220 ; LOP3.LUT R15, R19, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; ISETP.GE.U32.AND P0, PT, R26.reuse, R15, PT ; IMAD.IADD R0, R26, 0x1, -R15 ; SEL R2, R2, 0x63400000, !P0 ; IMNMX R0, R0, -0x46a00000, !PT ; IMNMX R15, R0, 0x46a00000, PT ; IMAD.IADD R2, R15, 0x1, -R2 ; IADD3 R15, R2, 0x7fe00000, RZ ; DMUL R36, R22, R14 ; FSETP.GTU.AND P0, PT, |R37|, 1.469367938527859385e-39, PT ; @P0 BRA 0x1370 ; DFMA R16, R22, -R16, R20 ; IMAD.MOV.U32 R16, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R17.reuse, RZ, PT ; LOP3.LUT R18, R17, 0x80000000, R19, 0x48, !PT ; LOP3.LUT R17, R18, R15, RZ, 0xfc, !PT ; @!P0 BRA 0x1370 ; IMAD.MOV R15, RZ, RZ, -R2 ; IADD3 R2, -R2, -0x43300000, RZ ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; DFMA R14, R36, -R14, R22 ; DMUL.RP R22, R22, R16 ; FSETP.NEU.AND P0, PT, |R15|, R2, PT ; FSEL R0, R22, R36, !P0 ; LOP3.LUT R18, R23, R18, RZ, 0x3c, !PT ; IMAD.MOV.U32 R36, RZ, RZ, R0 ; FSEL R37, R18, R37, !P0 ; BRA 0x1370 ; DSETP.NAN.AND P0, PT, R14, R14, PT ; @P0 BRA 0x1350 ; DSETP.NAN.AND P0, PT, R18, R18, PT ; @P0 BRA 0x1320 ; ISETP.NE.AND P0, PT, R0, R27, PT ; IMAD.MOV.U32 R36, RZ, RZ, 0x0 ; IMAD.MOV.U32 R37, RZ, RZ, -0x80000 ; @!P0 BRA 0x1370 ; ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; LOP3.LUT R37, R15, 0x80000000, R19, 0x48, !PT ; ISETP.EQ.OR P0, PT, R27, RZ, !P0 ; @P0 LOP3.LUT R0, R37, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R36, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R36, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R37, RZ, RZ, R0 ; BRA 0x1370 ; LOP3.LUT R37, R19, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R36, RZ, RZ, R18 ; BRA 0x1370 ; LOP3.LUT R37, R15, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R36, RZ, RZ, R14 ; BSYNC B3 ; IMAD.MOV.U32 R14, RZ, RZ, R4 ; IMAD.MOV.U32 R15, RZ, RZ, 0x0 ; RET.REL.NODEC R14 0x0 ; BRA 0x13b0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R5, SR_CTAID.X ; ULDC UR4, c[0x0][0x1a4] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1a8] ; UIADD3 UR4, UR4, -0x1, URZ ; S2R R2, SR_TID.X ; ISETP.NE.AND P0, PT, R5, UR4, PT ; SEL R0, R0, c[0x0][0x1a0], !P0 ; ISETP.GE.AND P0, PT, R2, R0, PT ; @P0 EXIT ; IMAD.MOV.U32 R6, RZ, RZ, 0x8 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD R5, R5, c[0x0][0x1a0], R2 ; IMAD.WIDE R2, R5, R6, c[0x0][0x170] ; LDG.E.64 R2, [R2.64] ; F2I.F64.TRUNC R0, R2 ; ISETP.NE.AND P0, PT, R0, 0x1, PT ; @P0 EXIT ; IMAD.SHL.U32 R8, R5, 0x8, RZ ; SHF.R.S32.HI R0, RZ, 0x1f, R5 ; SHF.L.U64.HI R9, R5, 0x3, R0 ; IADD3 R4, P0, R8, c[0x0][0x198], RZ ; IADD3.X R5, R9, c[0x0][0x19c], RZ, P0, !PT ; IADD3 R2, P0, R8, c[0x0][0x190], RZ ; LDG.E.64 R4, [R4.64] ; IADD3.X R3, R9, c[0x0][0x194], RZ, P0, !PT ; LDG.E.64 R2, [R2.64] ; IADD3 R8, P1, R8, c[0x0][0x168], RZ ; IADD3.X R9, R9, c[0x0][0x16c], RZ, P1, !PT ; F2I.F64.TRUNC R0, R4 ; F2I.F64.TRUNC R7, R2 ; ISETP.NE.AND P0, PT, R0, 0x1, PT ; SEL R26, RZ, 0x1, P0 ; ISETP.GT.AND P0, PT, R7, R26, PT ; @!P0 EXIT ; LDG.E.64 R8, [R8.64] ; IMAD.IADD R0, R7, 0x1, -R26.reuse ; BSSY B0, 0x550 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x188] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x18c] ; LOP3.LUT P0, R29, R0, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; IMAD.MOV.U32 R0, RZ, RZ, R26 ; F2I.F64.TRUNC R27, R8 ; @!P0 BRA 0x540 ; IMAD.IADD R9, R27, 0x1, R26.reuse ; IMAD.MOV.U32 R0, RZ, RZ, R26 ; IMAD.WIDE R30, R9, R6, c[0x0][0x188] ; IMAD.WIDE R8, R9, R6, c[0x0][0x160] ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; IMAD.MOV.U32 R13, RZ, RZ, R9 ; LDG.E.64 R8, [R30.64] ; IMAD.MOV.U32 R24, RZ, RZ, R6 ; IMAD.MOV.U32 R25, RZ, RZ, R13 ; LDG.E.64 R14, [R24.64] ; IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; BSSY B1, 0x4b0 ; MUFU.RCP64H R11, R9 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R12, -R8, R10, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R10, R12, R10 ; DFMA R10, -R8, R12, 1 ; DFMA R10, R12, R10, R12 ; DMUL R12, R14, R10 ; DFMA R16, -R8, R12, R14 ; DFMA R10, R10, R16, R12 ; FFMA R6, RZ, R9, R11 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x4a0 ; IMAD.MOV.U32 R13, RZ, RZ, R9 ; MOV R6, 0x4a0 ; CALL.REL.NOINC 0xbf0 ; BSYNC B1 ; STG.E.64 [R24.64], R10 ; IADD3 R29, R29, -0x1, RZ ; IADD3 R30, P1, R30, 0x8, RZ ; ISETP.NE.AND P0, PT, R29, RZ, PT ; IADD3 R6, P2, R24, 0x8, RZ ; IMAD.X R31, RZ, RZ, R31, P1 ; IADD3 R0, R0, 0x1, RZ ; IMAD.X R13, RZ, RZ, R25, P2 ; @P0 BRA 0x340 ; BSYNC B0 ; LOP3.LUT R6, RZ, R26, RZ, 0x33, !PT ; IMAD.IADD R6, R7, 0x1, R6 ; ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; @!P0 EXIT ; IMAD.IADD R29, R27, 0x1, R0 ; IMAD.WIDE R24, R29, 0x8, R4 ; LDG.E.64 R8, [R24.64] ; IMAD.WIDE R26, R29, 0x8, R2 ; LDG.E.64 R14, [R26.64] ; IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; BSSY B0, 0x710 ; MUFU.RCP64H R11, R9 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R12, -R8, R10, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R10, R12, R10 ; DFMA R10, -R8, R12, 1 ; DFMA R10, R12, R10, R12 ; DMUL R12, R14, R10 ; DFMA R16, -R8, R12, R14 ; DFMA R10, R10, R16, R12 ; FFMA R6, RZ, R9, R11 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x700 ; IMAD.MOV.U32 R13, RZ, RZ, R9 ; MOV R6, 0x700 ; CALL.REL.NOINC 0xbf0 ; BSYNC B0 ; STG.E.64 [R26.64], R10 ; LDG.E.64 R8, [R24.64+0x8] ; LDG.E.64 R14, [R26.64+0x8] ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; BSSY B0, 0x870 ; MUFU.RCP64H R13, R9 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R16, -R8, R12, 1 ; DFMA R16, R16, R16, R16 ; DFMA R16, R12, R16, R12 ; DFMA R12, -R8, R16, 1 ; DFMA R12, R16, R12, R16 ; DMUL R16, R14, R12 ; DFMA R10, -R8, R16, R14 ; DFMA R10, R12, R10, R16 ; FFMA R6, RZ, R9, R11 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x860 ; IMAD.MOV.U32 R13, RZ, RZ, R9 ; MOV R6, 0x860 ; CALL.REL.NOINC 0xbf0 ; BSYNC B0 ; STG.E.64 [R26.64+0x8], R10 ; LDG.E.64 R8, [R24.64+0x10] ; LDG.E.64 R14, [R26.64+0x10] ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; BSSY B0, 0x9d0 ; MUFU.RCP64H R13, R9 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R16, -R8, R12, 1 ; DFMA R16, R16, R16, R16 ; DFMA R16, R12, R16, R12 ; DFMA R12, -R8, R16, 1 ; DFMA R12, R16, R12, R16 ; DMUL R16, R14, R12 ; DFMA R10, -R8, R16, R14 ; DFMA R10, R12, R10, R16 ; FFMA R6, RZ, R9, R11 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x9c0 ; IMAD.MOV.U32 R13, RZ, RZ, R9 ; MOV R6, 0x9c0 ; CALL.REL.NOINC 0xbf0 ; BSYNC B0 ; STG.E.64 [R26.64+0x10], R10 ; LDG.E.64 R24, [R24.64+0x18] ; LDG.E.64 R14, [R26.64+0x18] ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B0, 0xb60 ; MUFU.RCP64H R9, R25 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R12, -R24, R8, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R8, R12, R8 ; DFMA R8, -R24, R12, 1 ; DFMA R8, R12, R8, R12 ; DMUL R12, R14, R8 ; DFMA R10, -R24, R12, R14 ; DFMA R8, R8, R10, R12 ; FFMA R6, RZ, R25, R9 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xb50 ; IMAD.MOV.U32 R8, RZ, RZ, R24 ; MOV R6, 0xb30 ; IMAD.MOV.U32 R13, RZ, RZ, R25 ; CALL.REL.NOINC 0xbf0 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; IMAD.MOV.U32 R9, RZ, RZ, R11 ; BSYNC B0 ; STG.E.64 [R26.64+0x18], R8 ; IADD3 R0, R0, 0x4, RZ ; IADD3 R4, P1, R4, 0x20, RZ ; ISETP.GE.AND P0, PT, R0, R7, PT ; IADD3 R2, P2, R2, 0x20, RZ ; IMAD.X R5, RZ, RZ, R5, P1 ; IMAD.X R3, RZ, RZ, R3, P2 ; @!P0 BRA 0x5a0 ; EXIT ; FSETP.GEU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R12, RZ, RZ, R8 ; FSETP.GEU.AND P2, PT, |R15|, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; LOP3.LUT R10, R13.reuse, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R16, RZ, RZ, R14 ; LOP3.LUT R33, R13, 0x7ff00000, RZ, 0xc0, !PT ; BSSY B2, 0x1190 ; LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R10, RZ, RZ, R8 ; LOP3.LUT R8, R15, 0x7ff00000, RZ, 0xc0, !PT ; @!P0 DMUL R10, R12, 8.98846567431157953865e+307 ; ISETP.GE.U32.AND P1, PT, R8.reuse, R33, PT ; @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; @!P2 LOP3.LUT R9, R13, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R28, RZ, RZ, R8 ; MUFU.RCP64H R23, R11 ; @!P2 ISETP.GE.U32.AND P3, PT, R8, R9, PT ; IMAD.MOV.U32 R9, RZ, RZ, 0x1ca00000 ; @!P0 LOP3.LUT R33, R11, 0x7ff00000, RZ, 0xc0, !PT ; @!P2 SEL R21, R9.reuse, 0x63400000, !P3 ; SEL R17, R9, 0x63400000, !P1 ; @!P2 LOP3.LUT R21, R21, 0x80000000, R15.reuse, 0xf8, !PT ; LOP3.LUT R17, R17, 0x800fffff, R15, 0xf8, !PT ; @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; DFMA R18, R22, -R10, 1 ; IADD3 R32, R33, -0x1, RZ ; @!P2 DFMA R16, R16, 2, -R20 ; DFMA R18, R18, R18, R18 ; DFMA R18, R22, R18, R22 ; @!P2 LOP3.LUT R28, R17, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R22, R28, -0x1, RZ ; DFMA R20, R18, -R10, 1 ; ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ; DFMA R18, R18, R20, R18 ; ISETP.GT.U32.OR P0, PT, R32, 0x7feffffe, P0 ; DMUL R20, R18, R16 ; DFMA R22, R20, -R10, R16 ; DFMA R22, R18, R22, R20 ; @P0 BRA 0x1030 ; LOP3.LUT R15, R13, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R8.reuse, R15, PT ; IMAD.IADD R14, R8, 0x1, -R15 ; SEL R9, R9, 0x63400000, !P0 ; IMNMX R14, R14, -0x46a00000, !PT ; IMNMX R14, R14, 0x46a00000, PT ; IMAD.IADD R18, R14, 0x1, -R9 ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; IADD3 R15, R18, 0x7fe00000, RZ ; DMUL R8, R22, R14 ; FSETP.GTU.AND P0, PT, |R9|, 1.469367938527859385e-39, PT ; @P0 BRA 0x1180 ; DFMA R10, R22, -R10, R16 ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R11.reuse, RZ, PT ; LOP3.LUT R13, R11, 0x80000000, R13, 0x48, !PT ; LOP3.LUT R15, R13, R15, RZ, 0xfc, !PT ; @!P0 BRA 0x1180 ; IMAD.MOV R11, RZ, RZ, -R18 ; DMUL.RP R14, R22, R14 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; DFMA R10, R8, -R10, R22 ; LOP3.LUT R13, R15, R13, RZ, 0x3c, !PT ; IADD3 R10, -R18, -0x43300000, RZ ; FSETP.NEU.AND P0, PT, |R11|, R10, PT ; FSEL R8, R14, R8, !P0 ; FSEL R9, R13, R9, !P0 ; BRA 0x1180 ; DSETP.NAN.AND P0, PT, R14, R14, PT ; @P0 BRA 0x1160 ; DSETP.NAN.AND P0, PT, R12, R12, PT ; @P0 BRA 0x1130 ; ISETP.NE.AND P0, PT, R28, R33, PT ; IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; IMAD.MOV.U32 R9, RZ, RZ, -0x80000 ; @!P0 BRA 0x1180 ; ISETP.NE.AND P0, PT, R28, 0x7ff00000, PT ; LOP3.LUT R9, R15, 0x80000000, R13, 0x48, !PT ; ISETP.EQ.OR P0, PT, R33, RZ, !P0 ; @P0 LOP3.LUT R10, R9, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R9, RZ, RZ, R10 ; BRA 0x1180 ; LOP3.LUT R9, R13, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R8, RZ, RZ, R12 ; BRA 0x1180 ; LOP3.LUT R9, R15, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R8, RZ, RZ, R14 ; BSYNC B2 ; IMAD.MOV.U32 R10, RZ, RZ, R8 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; RET.REL.NODEC R8 0x0 ; BRA 0x11e0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R9, SR_CTAID.X ; ULDC UR4, c[0x0][0x1e0] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1e4] ; UIADD3 UR4, UR4, -0x1, URZ ; S2R R2, SR_TID.X ; ISETP.NE.AND P0, PT, R9, UR4, PT ; SEL R3, R3, c[0x0][0x1dc], !P0 ; ISETP.GE.AND P0, PT, R2, R3, PT ; @P0 EXIT ; HFMA2.MMA R0, -RZ, RZ, 0, 4.76837158203125e-07 ; IMAD R9, R9, c[0x0][0x1dc], R2 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R4, R9, R0, c[0x0][0x170] ; LDG.E.64 R4, [R4.64] ; F2I.F64.TRUNC R3, R4 ; ISETP.NE.AND P0, PT, R3, 0x1, PT ; @P0 EXIT ; IMAD.SHL.U32 R10, R9, 0x8, RZ ; SHF.R.S32.HI R4, RZ, 0x1f, R9 ; SHF.L.U64.HI R9, R9, 0x3, R4 ; IADD3 R24, P3, R10.reuse, c[0x0][0x1a8], RZ ; IADD3 R12, P0, R10.reuse, c[0x0][0x168], RZ ; IADD3.X R25, R9, c[0x0][0x1ac], RZ, P3, !PT ; IADD3 R18, P1, R10.reuse, c[0x0][0x180], RZ ; IADD3 R22, P2, R10, c[0x0][0x1c8], RZ ; LDG.E.64 R24, [R24.64] ; IADD3 R26, P3, R10.reuse, c[0x0][0x1b0], RZ ; IADD3 R28, P4, R10, c[0x0][0x1d0], RZ ; IADD3.X R13, R9.reuse, c[0x0][0x16c], RZ, P0, !PT ; IADD3.X R19, R9.reuse, c[0x0][0x184], RZ, P1, !PT ; IADD3.X R23, R9.reuse, c[0x0][0x1cc], RZ, P2, !PT ; IADD3.X R27, R9.reuse, c[0x0][0x1b4], RZ, P3, !PT ; LDG.E.64 R12, [R12.64] ; IADD3.X R29, R9, c[0x0][0x1d4], RZ, P4, !PT ; LDG.E.64 R18, [R18.64] ; LDG.E.64 R22, [R22.64] ; LDG.E.64 R26, [R26.64] ; LDG.E.64 R28, [R28.64] ; IADD3 R16, P0, R10, c[0x0][0x1b8], RZ ; IADD3 R14, P1, R10.reuse, c[0x0][0x1a0], RZ ; IADD3 R20, P2, R10.reuse, c[0x0][0x1c0], RZ ; IADD3.X R17, R9.reuse, c[0x0][0x1bc], RZ, P0, !PT ; IADD3.X R15, R9.reuse, c[0x0][0x1a4], RZ, P1, !PT ; IADD3.X R21, R9.reuse, c[0x0][0x1c4], RZ, P2, !PT ; LDG.E.64 R16, [R16.64] ; LDG.E.64 R14, [R14.64] ; LDG.E.64 R20, [R20.64] ; IADD3 R10, P0, R10, c[0x0][0x188], RZ ; BSSY B0, 0xd10 ; IADD3.X R11, R9, c[0x0][0x18c], RZ, P0, !PT ; F2I.F64.TRUNC R3, R24 ; F2I.F64.TRUNC R4, R12 ; ISETP.GE.AND P1, PT, R3, 0x1, PT ; F2I.F64.TRUNC R6, R18 ; F2I.F64.TRUNC R5, R22 ; F2I.F64.TRUNC R7, R26 ; F2I.F64.TRUNC R8, R28 ; @!P1 BRA 0xd00 ; LDG.E.64 R10, [R10.64] ; IADD3 R12, R3.reuse, -0x1, RZ ; BSSY B1, 0xc50 ; LOP3.LUT R40, R3, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R42, RZ, RZ, RZ ; ISETP.GE.U32.AND P0, PT, R12, 0x3, PT ; F2I.F64.TRUNC R9, R10 ; @!P0 BRA 0xc40 ; IADD3 R41, R3, -R40, RZ ; BSSY B2, 0xb20 ; IMAD.SHL.U32 R37, R2, 0x8, RZ ; ISETP.GT.AND P0, PT, R41, RZ, PT ; IMAD.MOV.U32 R42, RZ, RZ, RZ ; @!P0 BRA 0xb10 ; ISETP.GT.AND P2, PT, R41, 0xc, PT ; BSSY B3, 0x8b0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0x8a0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R29, R9.reuse, R42, RZ ; IADD3 R31, R9, 0x4, R42 ; IMAD.WIDE R28, R29, R0, c[0x0][0x190] ; LDG.E.64 R26, [R28.64] ; IMAD.WIDE R30, R31, R0, c[0x0][0x190] ; LDG.E.64 R22, [R28.64+0x8] ; LDG.E.64 R38, [R28.64+0x10] ; LDG.E.64 R10, [R28.64+0x18] ; LDG.E.64 R12, [R30.64] ; LDG.E.64 R34, [R30.64+0x8] ; LDG.E.64 R24, [R30.64+0x10] ; IMAD R33, R0, c[0x0][0x1dc], R37 ; LDG.E.64 R18, [R30.64+0x18] ; IADD3 R45, R9.reuse, 0x8, R42.reuse ; IMAD R43, R0, c[0x0][0x1dc], R33 ; IADD3 R36, R9, 0xc, R42 ; IMAD.WIDE R44, R45, R0, c[0x0][0x190] ; IMAD R32, R0, c[0x0][0x1dc], R43 ; LDG.E.64 R28, [R44.64] ; LDG.E.64 R30, [R44.64+0x18] ; STS.64 [R37], R26 ; STS.64 [R33], R22 ; STS.64 [R43], R38 ; IMAD.WIDE R36, R36, R0, c[0x0][0x190] ; STS.64 [R32], R10 ; LDG.E.64 R26, [R36.64] ; IMAD R43, R0, c[0x0][0x1dc], R32 ; LDG.E.64 R22, [R36.64+0x8] ; LDG.E.64 R10, [R44.64+0x8] ; LDG.E.64 R32, [R44.64+0x10] ; STS.64 [R43], R12 ; LDG.E.64 R38, [R36.64+0x18] ; LDG.E.64 R12, [R36.64+0x10] ; IMAD R43, R0, c[0x0][0x1dc], R43 ; STS.64 [R43], R34 ; IMAD R35, R0, c[0x0][0x1dc], R43 ; IMAD R34, R0, c[0x0][0x1dc], R35 ; IMAD R45, R0.reuse, c[0x0][0x1dc], R34 ; STS.64 [R35], R24 ; IMAD R44, R0.reuse, c[0x0][0x1dc], R45 ; STS.64 [R34], R18 ; IMAD R25, R0, c[0x0][0x1dc], R44 ; IMAD R19, R0, c[0x0][0x1dc], R25 ; IMAD R36, R0, c[0x0][0x1dc], R19 ; IMAD R37, R0.reuse, c[0x0][0x1dc], R36 ; STS.64 [R45], R28 ; IMAD R43, R0, c[0x0][0x1dc], R37 ; IMAD R35, R0, c[0x0][0x1dc], R43 ; IADD3 R41, R41, -0x10, RZ ; ISETP.GT.AND P2, PT, R41, 0xc, PT ; IADD3 R42, R42, 0x10, RZ ; STS.64 [R44], R10 ; STS.64 [R25], R32 ; STS.64 [R19], R30 ; STS.64 [R36], R26 ; STS.64 [R37], R22 ; STS.64 [R43], R12 ; STS.64 [R35], R38 ; IMAD R37, R0, c[0x0][0x1dc], R35 ; @P2 BRA 0x4e0 ; BSYNC B3 ; ISETP.GT.AND P2, PT, R41, 0x4, PT ; BSSY B3, 0xae0 ; @!P2 BRA 0xad0 ; IMAD.IADD R35, R9.reuse, 0x1, R42.reuse ; IADD3 R33, R9, 0x4, R42 ; IMAD.WIDE R34, R35, R0, c[0x0][0x190] ; IMAD.WIDE R32, R33, R0, c[0x0][0x190] ; LDG.E.64 R30, [R34.64] ; LDG.E.64 R10, [R34.64+0x8] ; LDG.E.64 R12, [R34.64+0x10] ; LDG.E.64 R18, [R34.64+0x18] ; LDG.E.64 R22, [R32.64] ; LDG.E.64 R24, [R32.64+0x8] ; LDG.E.64 R26, [R32.64+0x10] ; LDG.E.64 R28, [R32.64+0x18] ; IMAD R39, R0, c[0x0][0x1dc], R37 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R41, R41, -0x8, RZ ; IMAD R43, R0, c[0x0][0x1dc], R39 ; IADD3 R42, R42, 0x8, RZ ; IMAD R45, R0, c[0x0][0x1dc], R43 ; IMAD R36, R0, c[0x0][0x1dc], R45 ; IMAD R38, R0, c[0x0][0x1dc], R36 ; IMAD R35, R0, c[0x0][0x1dc], R38 ; IMAD R34, R0.reuse, c[0x0][0x1dc], R35 ; STS.64 [R37], R30 ; STS.64 [R39], R10 ; STS.64 [R43], R12 ; STS.64 [R45], R18 ; IMAD R37, R0, c[0x0][0x1dc], R34 ; STS.64 [R36], R22 ; STS.64 [R38], R24 ; STS.64 [R35], R26 ; STS.64 [R34], R28 ; BSYNC B3 ; ISETP.NE.OR P0, PT, R41, RZ, P0 ; @!P0 BREAK B2 ; @!P0 BRA 0xc40 ; BSYNC B2 ; IMAD.IADD R25, R9, 0x1, R42 ; IMAD.WIDE R24, R25, R0, c[0x0][0x190] ; LDG.E.64 R18, [R24.64] ; LDG.E.64 R12, [R24.64+0x8] ; LDG.E.64 R10, [R24.64+0x10] ; LDG.E.64 R22, [R24.64+0x18] ; IMAD R27, R0, c[0x0][0x1dc], R37 ; IADD3 R41, R41, -0x4, RZ ; IADD3 R42, R42, 0x4, RZ ; IMAD R29, R0, c[0x0][0x1dc], R27 ; ISETP.NE.AND P0, PT, R41, RZ, PT ; IMAD R31, R0.reuse, c[0x0][0x1dc], R29 ; STS.64 [R37], R18 ; STS.64 [R27], R12 ; STS.64 [R29], R10 ; STS.64 [R31], R22 ; IMAD R37, R0, c[0x0][0x1dc], R31 ; @P0 BRA 0xb20 ; BSYNC B1 ; ISETP.NE.AND P0, PT, R40, RZ, PT ; @!P0 BRA 0xd00 ; IADD3 R11, R9, R42, RZ ; IMAD.WIDE R10, R11, R0, c[0x0][0x190] ; LDG.E.64 R10, [R10.64] ; IMAD R13, R42, c[0x0][0x1dc], R2 ; IADD3 R40, R40, -0x1, RZ ; IADD3 R42, R42, 0x1, RZ ; ISETP.NE.AND P0, PT, R40, RZ, PT ; STS.64 [R13.X8], R10 ; @P0 BRA 0xc70 ; BSYNC B0 ; WARPSYNC 0xffffffff ; ISETP.GE.AND P0, PT, R5, 0x1, PT ; BSSY B0, 0x6ad0 ; DSETP.GTU.OR P0, PT, R20, c[0x2][0x0], !P0 ; @P0 BRA 0x6ac0 ; I2F.F64 R10, R3 ; BSSY B1, 0xe60 ; MUFU.RCP64H R13, R11 ; IADD3 R12, R11, 0x300402, RZ ; FSETP.GEU.AND P0, PT, |R12|, 5.8789094863358348022e-39, PT ; DFMA R18, -R10, R12, 1 ; DFMA R18, R18, R18, R18 ; DFMA R18, R12, R18, R12 ; DFMA R22, -R10, R18, 1 ; DFMA R18, R18, R22, R18 ; @P0 BRA 0xe50 ; LOP3.LUT R0, R11, 0x7fffffff, RZ, 0xc0, !PT ; IADD3 R18, R0, -0x100000, RZ ; MOV R0, 0xe50 ; CALL.REL.NOINC 0x6e40 ; BSYNC B1 ; DADD R12, -R16.reuse, 1 ; LOP3.LUT R10, R3.reuse, 0x3, RZ, 0xc0, !PT ; IMAD.SHL.U32 R11, R2, 0x8, RZ ; IADD3 R9, R3.reuse, -0x1, RZ ; DMUL R16, R16, R14 ; IMAD.MOV.U32 R38, RZ, RZ, RZ ; IADD3 R39, R3, -R10, RZ ; DMUL R14, R14, R12 ; ISETP.GE.AND P0, PT, R7, 0x1, PT ; BSSY B1, 0x6a80 ; CS2R R12, SRZ ; @!P0 BRA 0x6a70 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1d8] ; CS2R R12, SRZ ; LOP3.LUT R0, R0, 0x2, RZ, 0xfc, !PT ; ISETP.NE.AND P0, PT, R0, 0x3, PT ; @!P0 BRA 0x3cf0 ; IMAD.MOV.U32 R45, RZ, RZ, RZ ; IADD3 R37, R4, R45, RZ ; IMAD.MOV.U32 R0, RZ, RZ, 0x8 ; IMAD.WIDE R36, R37, R0, c[0x0][0x160] ; LDG.E.64 R36, [R36.64] ; BSSY B2, 0x2ae0 ; CS2R R34, SRZ ; DSETP.NEU.AND P0, PT, R36, RZ, PT ; @P0 BRA 0x1b50 ; @!P1 BRA 0x2ad0 ; ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; BSSY B3, 0x19f0 ; IMAD R41, R3, R45, R6 ; CS2R R34, SRZ ; IMAD.MOV.U32 R40, RZ, RZ, RZ ; @!P0 BRA 0x19e0 ; ISETP.GT.AND P0, PT, R39, RZ, PT ; BSSY B4, 0x1880 ; MOV R40, RZ ; IMAD.MOV.U32 R43, RZ, RZ, R11 ; CS2R R34, SRZ ; IMAD.MOV.U32 R42, RZ, RZ, R39 ; IMAD.WIDE R32, R41, R0, c[0x0][0x178] ; @!P0 BRA 0x1870 ; ISETP.GT.AND P2, PT, R42, 0xc, PT ; BSSY B5, 0x15b0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0x15a0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E.64 R28, [R32.64] ; LDG.E.64 R26, [R32.64+0x8] ; LDG.E.64 R24, [R32.64+0x10] ; LDG.E.64 R22, [R32.64+0x18] ; LDS.64 R30, [R43] ; DFMA R30, R30, R28, R34 ; IMAD R35, R0, c[0x0][0x1dc], R43 ; IMAD R44, R0, c[0x0][0x1dc], R35 ; LDS.64 R28, [R35] ; LDG.E.64 R34, [R32.64+0x38] ; DFMA R30, R28, R26, R30 ; LDG.E.64 R26, [R32.64+0x20] ; LDS.64 R28, [R44] ; IMAD R44, R0, c[0x0][0x1dc], R44 ; DFMA R28, R28, R24, R30 ; LDG.E.64 R24, [R32.64+0x28] ; LDS.64 R30, [R44] ; DFMA R30, R30, R22, R28 ; LDG.E.64 R28, [R32.64+0x30] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; LDS.64 R22, [R43] ; DFMA R26, R22, R26, R30 ; IMAD R31, R0, c[0x0][0x1dc], R43 ; LDS.64 R22, [R31] ; IMAD R30, R0.reuse, c[0x0][0x1dc], R31 ; DFMA R26, R22, R24, R26 ; LDG.E.64 R24, [R32.64+0x40] ; LDS.64 R22, [R30] ; IMAD R43, R0, c[0x0][0x1dc], R30 ; LDG.E.64 R30, [R32.64+0x58] ; DFMA R28, R22, R28, R26 ; LDG.E.64 R22, [R32.64+0x48] ; LDS.64 R26, [R43] ; DFMA R34, R26, R34, R28 ; LDG.E.64 R28, [R32.64+0x50] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; LDS.64 R26, [R44] ; DFMA R24, R26, R24, R34 ; IMAD R35, R0, c[0x0][0x1dc], R44 ; LDS.64 R26, [R35] ; IMAD R34, R0.reuse, c[0x0][0x1dc], R35 ; DFMA R24, R26, R22, R24 ; LDG.E.64 R26, [R32.64+0x60] ; LDS.64 R22, [R34] ; IMAD R43, R0, c[0x0][0x1dc], R34 ; LDG.E.64 R34, [R32.64+0x78] ; DFMA R28, R22, R28, R24 ; LDG.E.64 R24, [R32.64+0x68] ; LDS.64 R22, [R43] ; DFMA R30, R22, R30, R28 ; LDG.E.64 R22, [R32.64+0x70] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; LDS.64 R28, [R44] ; IADD3 R42, R42, -0x10, RZ ; ISETP.GT.AND P2, PT, R42, 0xc, PT ; IADD3 R32, P3, R32, 0x80, RZ ; IADD3 R40, R40, 0x10, RZ ; IADD3.X R33, RZ, R33, RZ, P3, !PT ; DFMA R28, R28, R26, R30 ; IMAD R30, R0, c[0x0][0x1dc], R44 ; LDS.64 R26, [R30] ; IMAD R31, R0, c[0x0][0x1dc], R30 ; DFMA R28, R26, R24, R28 ; LDS.64 R26, [R31] ; IMAD R31, R0, c[0x0][0x1dc], R31 ; LDS.64 R24, [R31] ; IMAD R43, R0, c[0x0][0x1dc], R31 ; DFMA R22, R26, R22, R28 ; DFMA R34, R24, R34, R22 ; @P2 BRA 0x1140 ; BSYNC B5 ; ISETP.GT.AND P2, PT, R42, 0x4, PT ; BSSY B5, 0x1840 ; @!P2 BRA 0x1830 ; LDG.E.64 R28, [R32.64] ; LDG.E.64 R22, [R32.64+0x8] ; LDG.E.64 R24, [R32.64+0x10] ; LDG.E.64 R26, [R32.64+0x18] ; LDS.64 R30, [R43] ; DFMA R30, R30, R28, R34 ; IMAD R35, R0, c[0x0][0x1dc], R43 ; IMAD R44, R0, c[0x0][0x1dc], R35 ; LDS.64 R28, [R35] ; LDG.E.64 R34, [R32.64+0x38] ; DFMA R30, R28, R22, R30 ; LDG.E.64 R22, [R32.64+0x20] ; LDS.64 R28, [R44] ; IMAD R44, R0, c[0x0][0x1dc], R44 ; DFMA R28, R28, R24, R30 ; LDG.E.64 R24, [R32.64+0x28] ; LDS.64 R30, [R44] ; DFMA R30, R30, R26, R28 ; LDG.E.64 R26, [R32.64+0x30] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; LDS.64 R28, [R43] ; IADD3 R32, P2, R32, 0x40, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R40, R40, 0x8, RZ ; IMAD.X R33, RZ, RZ, R33, P2 ; IADD3 R42, R42, -0x8, RZ ; DFMA R28, R28, R22, R30 ; IMAD R30, R0, c[0x0][0x1dc], R43 ; LDS.64 R22, [R30] ; IMAD R31, R0, c[0x0][0x1dc], R30 ; DFMA R28, R22, R24, R28 ; LDS.64 R24, [R31] ; IMAD R31, R0, c[0x0][0x1dc], R31 ; LDS.64 R22, [R31] ; IMAD R43, R0, c[0x0][0x1dc], R31 ; DFMA R24, R24, R26, R28 ; DFMA R34, R22, R34, R24 ; BSYNC B5 ; ISETP.NE.OR P0, PT, R42, RZ, P0 ; @!P0 BREAK B4 ; @!P0 BRA 0x19e0 ; BSYNC B4 ; LDG.E.64 R28, [R32.64] ; LDG.E.64 R26, [R32.64+0x8] ; LDG.E.64 R24, [R32.64+0x10] ; LDG.E.64 R22, [R32.64+0x18] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; IADD3 R42, R42, -0x4, RZ ; LDS.64 R30, [R43] ; IADD3 R40, R40, 0x4, RZ ; ISETP.NE.AND P0, PT, R42, RZ, PT ; IADD3 R32, P2, R32, 0x20, RZ ; IMAD.X R33, RZ, RZ, R33, P2 ; DFMA R28, R30, R28, R34 ; LDS.64 R30, [R44] ; DFMA R28, R30, R26, R28 ; IMAD R30, R0, c[0x0][0x1dc], R44 ; IMAD R31, R0.reuse, c[0x0][0x1dc], R30 ; LDS.64 R26, [R30] ; IMAD R43, R0, c[0x0][0x1dc], R31 ; LDS.64 R34, [R31] ; DFMA R24, R26, R24, R28 ; DFMA R34, R34, R22, R24 ; @P0 BRA 0x1880 ; BSYNC B3 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x2ad0 ; IADD3 R23, R41, R40, RZ ; IMAD.WIDE R22, R23, R0, c[0x0][0x178] ; LDG.E.64 R24, [R22.64] ; IMAD R40, R40, c[0x0][0x1dc], R2 ; ISETP.NE.AND P0, PT, R10, 0x1, PT ; IMAD.SHL.U32 R29, R40, 0x8, RZ ; LDS.64 R26, [R29] ; DFMA R34, R26, R24, R34 ; @!P0 BRA 0x2ad0 ; LDG.E.64 R24, [R22.64+0x8] ; IMAD R29, R0, c[0x0][0x1dc], R29 ; ISETP.NE.AND P0, PT, R10, 0x2, PT ; LDS.64 R26, [R29] ; DFMA R34, R26, R24, R34 ; @!P0 BRA 0x2ad0 ; LDG.E.64 R22, [R22.64+0x10] ; IMAD R24, R0, c[0x0][0x1dc], R29 ; LDS.64 R24, [R24] ; DFMA R34, R24, R22, R34 ; BRA 0x2ad0 ; @!P1 BRA 0x2ad0 ; ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; BSSY B3, 0x2930 ; IMAD R41, R3, R45, R6 ; CS2R R34, SRZ ; IMAD.MOV.U32 R42, RZ, RZ, RZ ; @!P0 BRA 0x2920 ; ISETP.GT.AND P0, PT, R39, RZ, PT ; BSSY B4, 0x2740 ; MOV R42, RZ ; IMAD.MOV.U32 R40, RZ, RZ, R39 ; CS2R R34, SRZ ; IMAD.MOV.U32 R44, RZ, RZ, R11 ; @!P0 BRA 0x2730 ; ISETP.GT.AND P2, PT, R40, 0xc, PT ; BSSY B5, 0x2350 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0x2340 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R23, R41, R42, RZ ; LDS.64 R28, [R44] ; IMAD.WIDE R22, R23, R0, c[0x0][0x178] ; LDG.E.64 R30, [R22.64] ; LDG.E.64 R26, [R22.64+0x8] ; LDG.E.64 R24, [R22.64+0x10] ; LDG.E.64 R22, [R22.64+0x18] ; IMAD R33, R0, c[0x0][0x1dc], R44 ; IADD3 R43, R41, 0x4, R42 ; DFMA R28, R36, R30, R28 ; DFMA R34, R30, R28, R34 ; STS.64 [R44], R28 ; LDS.64 R30, [R33] ; DFMA R30, R36, R26, R30 ; DFMA R34, R26, R30, R34 ; STS.64 [R33], R30 ; IMAD.WIDE R26, R43, R0, c[0x0][0x178] ; IMAD R43, R0.reuse, c[0x0][0x1dc], R33 ; LDG.E.64 R28, [R26.64] ; LDS.64 R30, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R30, R36, R24, R30 ; DFMA R34, R24, R30, R34 ; STS.64 [R43], R30 ; LDG.E.64 R24, [R26.64+0x8] ; LDS.64 R32, [R44] ; LDG.E.64 R30, [R26.64+0x18] ; DFMA R32, R36, R22, R32 ; DFMA R34, R22, R32, R34 ; LDG.E.64 R22, [R26.64+0x10] ; STS.64 [R44], R32 ; IMAD R44, R0, c[0x0][0x1dc], R44 ; LDS.64 R32, [R44] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; DFMA R32, R36, R28, R32 ; DFMA R28, R28, R32, R34 ; STS.64 [R44], R32 ; LDS.64 R34, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R32, R36, R24, R34 ; IADD3 R35, R41, 0x8, R42 ; IMAD.WIDE R26, R35, R0, c[0x0][0x178] ; DFMA R28, R24, R32, R28 ; STS.64 [R43], R32 ; LDG.E.64 R24, [R26.64] ; LDS.64 R34, [R44] ; DFMA R34, R36, R22, R34 ; DFMA R32, R22, R34, R28 ; LDG.E.64 R22, [R26.64+0x8] ; STS.64 [R44], R34 ; IMAD R35, R0, c[0x0][0x1dc], R44 ; LDS.64 R28, [R35] ; DFMA R28, R36, R30, R28 ; DFMA R32, R30, R28, R32 ; LDG.E.64 R30, [R26.64+0x10] ; LDG.E.64 R26, [R26.64+0x18] ; IMAD R43, R0, c[0x0][0x1dc], R35 ; STS.64 [R35], R28 ; LDS.64 R28, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R34, R36, R24, R28 ; DFMA R32, R24, R34, R32 ; STS.64 [R43], R34 ; LDS.64 R24, [R44] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; DFMA R24, R36, R22, R24 ; DFMA R32, R22, R24, R32 ; IADD3 R23, R41, 0xc, R42 ; STS.64 [R44], R24 ; LDS.64 R28, [R43] ; IMAD.WIDE R24, R23, R0, c[0x0][0x178] ; LDG.E.64 R22, [R24.64] ; IMAD R35, R0, c[0x0][0x1dc], R43 ; DFMA R28, R36, R30, R28 ; DFMA R32, R30, R28, R32 ; STS.64 [R43], R28 ; LDS.64 R30, [R35] ; LDG.E.64 R28, [R24.64+0x8] ; DFMA R30, R36, R26, R30 ; DFMA R32, R26, R30, R32 ; LDG.E.64 R26, [R24.64+0x10] ; LDG.E.64 R24, [R24.64+0x18] ; IMAD R34, R0, c[0x0][0x1dc], R35 ; STS.64 [R35], R30 ; LDS.64 R30, [R34] ; IMAD R43, R0, c[0x0][0x1dc], R34 ; IMAD R44, R0, c[0x0][0x1dc], R43 ; IADD3 R40, R40, -0x10, RZ ; ISETP.GT.AND P2, PT, R40, 0xc, PT ; DFMA R30, R36, R22, R30 ; DFMA R32, R22, R30, R32 ; STS.64 [R34], R30 ; LDS.64 R22, [R43] ; DFMA R30, R36, R28, R22 ; STS.64 [R43], R30 ; LDS.64 R22, [R44] ; DFMA R32, R28, R30, R32 ; IMAD R43, R0, c[0x0][0x1dc], R44 ; DFMA R22, R36, R26, R22 ; STS.64 [R44], R22 ; LDS.64 R28, [R43] ; DFMA R32, R26, R22, R32 ; IADD3 R42, R42, 0x10, RZ ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R28, R36, R24, R28 ; STS.64 [R43], R28 ; DFMA R34, R24, R28, R32 ; @P2 BRA 0x1c80 ; BSYNC B5 ; ISETP.GT.AND P2, PT, R40, 0x4, PT ; BSSY B5, 0x2700 ; @!P2 BRA 0x26f0 ; IMAD.IADD R33, R41, 0x1, R42 ; LDS.64 R26, [R44] ; IMAD.WIDE R32, R33, R0, c[0x0][0x178] ; LDG.E.64 R24, [R32.64] ; LDG.E.64 R30, [R32.64+0x8] ; LDG.E.64 R22, [R32.64+0x10] ; LDG.E.64 R28, [R32.64+0x18] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; DFMA R26, R36, R24, R26 ; DFMA R24, R24, R26, R34 ; STS.64 [R44], R26 ; LDS.64 R34, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R34, R36, R30, R34 ; DFMA R30, R30, R34, R24 ; STS.64 [R43], R34 ; IADD3 R25, R41, 0x4, R42 ; IMAD.WIDE R32, R25, R0, c[0x0][0x178] ; LDS.64 R24, [R44] ; LDG.E.64 R26, [R32.64] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; LDG.E.64 R34, [R32.64+0x18] ; DFMA R24, R36, R22, R24 ; DFMA R22, R22, R24, R30 ; STS.64 [R44], R24 ; LDS.64 R30, [R43] ; LDG.E.64 R24, [R32.64+0x8] ; DFMA R30, R36, R28, R30 ; DFMA R28, R28, R30, R22 ; LDG.E.64 R22, [R32.64+0x10] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; STS.64 [R43], R30 ; LDS.64 R30, [R44] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R40, R40, -0x8, RZ ; IADD3 R42, R42, 0x8, RZ ; DFMA R30, R36, R26, R30 ; DFMA R28, R26, R30, R28 ; STS.64 [R44], R30 ; LDS.64 R26, [R43] ; IMAD R31, R0, c[0x0][0x1dc], R43 ; DFMA R32, R36, R24, R26 ; STS.64 [R43], R32 ; LDS.64 R26, [R31] ; DFMA R28, R24, R32, R28 ; IMAD R33, R0, c[0x0][0x1dc], R31 ; DFMA R26, R36, R22, R26 ; STS.64 [R31], R26 ; LDS.64 R24, [R33] ; DFMA R28, R22, R26, R28 ; IMAD R44, R0, c[0x0][0x1dc], R33 ; DFMA R24, R36, R34, R24 ; STS.64 [R33], R24 ; DFMA R34, R34, R24, R28 ; BSYNC B5 ; ISETP.NE.OR P0, PT, R40, RZ, P0 ; @!P0 BREAK B4 ; @!P0 BRA 0x2920 ; BSYNC B4 ; IMAD.IADD R33, R41, 0x1, R42 ; LDS.64 R28, [R44] ; IMAD.WIDE R32, R33, R0, c[0x0][0x178] ; LDG.E.64 R30, [R32.64] ; LDG.E.64 R26, [R32.64+0x8] ; LDG.E.64 R24, [R32.64+0x10] ; LDG.E.64 R22, [R32.64+0x18] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; IADD3 R40, R40, -0x4, RZ ; IADD3 R42, R42, 0x4, RZ ; ISETP.NE.AND P0, PT, R40, RZ, PT ; IMAD R33, R0, c[0x0][0x1dc], R43 ; IMAD R32, R0, c[0x0][0x1dc], R33 ; DFMA R28, R36, R30, R28 ; DFMA R30, R30, R28, R34 ; STS.64 [R44], R28 ; LDS.64 R34, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R32 ; DFMA R28, R36, R26, R34 ; DFMA R30, R26, R28, R30 ; STS.64 [R43], R28 ; LDS.64 R34, [R33] ; DFMA R26, R36, R24, R34 ; DFMA R30, R24, R26, R30 ; STS.64 [R33], R26 ; LDS.64 R34, [R32] ; DFMA R34, R36, R22, R34 ; STS.64 [R32], R34 ; DFMA R34, R22, R34, R30 ; @P0 BRA 0x2740 ; BSYNC B3 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x2ad0 ; IADD3 R23, R41, R42, RZ ; IMAD.WIDE R22, R23, R0, c[0x0][0x178] ; LDG.E.64 R24, [R22.64] ; IMAD R42, R42, c[0x0][0x1dc], R2 ; ISETP.NE.AND P0, PT, R10, 0x1, PT ; IMAD.SHL.U32 R29, R42, 0x8, RZ ; LDS.64 R26, [R29] ; DFMA R26, R36, R24, R26 ; DFMA R34, R24, R26, R34 ; STS.64 [R29], R26 ; @!P0 BRA 0x2ad0 ; LDG.E.64 R24, [R22.64+0x8] ; ISETP.NE.AND P0, PT, R10, 0x2, PT ; @P0 LDG.E.64 R26, [R22.64+0x10] ; IMAD R41, R0, c[0x0][0x1dc], R29 ; @P0 IMAD R33, R0, c[0x0][0x1dc], R41 ; LDS.64 R28, [R41] ; DFMA R28, R36, R24, R28 ; DFMA R34, R24, R28, R34 ; STS.64 [R41], R28 ; @P0 LDS.64 R30, [R33] ; @P0 DFMA R30, R36, R26, R30 ; @P0 DFMA R34, R26, R30, R34 ; @P0 STS.64 [R33], R30 ; BSYNC B2 ; DMUL R34, R34, R18 ; BSSY B2, 0x2bb0 ; DSETP.GEU.AND P0, PT, R16, |R34|, PT ; DSETP.GT.AND P2, PT, R34, RZ, PT ; @!P0 BRA P2, 0x2b90 ; DSETP.GEU.AND P0, PT, R16, |R34|, PT ; CS2R R22, SRZ ; DSETP.GEU.OR P0, PT, R34, RZ, P0 ; @P0 BRA 0x2ba0 ; DADD R22, R16, R34 ; BRA 0x2ba0 ; DADD R22, -R16, R34 ; BSYNC B2 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1d8] ; ISETP.NE.AND P2, PT, R8, 0x1, PT ; BSSY B2, 0x2dd0 ; ISETP.EQ.AND P3, PT, R45, RZ, PT ; CS2R R24, SRZ ; ISETP.NE.AND P0, PT, R0, 0x2, PT ; ISETP.NE.AND P0, PT, R0, 0x4, P0 ; @!P0 MOV R24, R18 ; @!P0 IMAD.MOV.U32 R25, RZ, RZ, R19 ; @!P2 BRA P3, 0x2dc0 ; DADD R24, R14, R24 ; IMAD.MOV.U32 R28, RZ, RZ, 0x1 ; FSETP.GEU.AND P3, PT, |R23|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x2dc0 ; MUFU.RCP64H R29, R25 ; DFMA R26, -R24, R28, 1 ; DFMA R26, R26, R26, R26 ; DFMA R26, R28, R26, R28 ; DFMA R30, -R24, R26, 1 ; DFMA R30, R26, R30, R26 ; DMUL R28, R30, R22 ; DFMA R26, -R24, R28, R22 ; DFMA R34, R30, R26, R28 ; FFMA R0, RZ, R25, R35 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P3, 0x2db0 ; MOV R26, R22 ; IMAD.MOV.U32 R27, RZ, RZ, R23 ; MOV R0, 0x2d90 ; CALL.REL.NOINC 0x70e0 ; MOV R34, R32 ; IMAD.MOV.U32 R35, RZ, RZ, R33 ; BSYNC B3 ; BSYNC B2 ; IADD3 R23, R4, R45, RZ ; IMAD.MOV.U32 R0, RZ, RZ, 0x8 ; DSETP.EQ.OR P0, PT, R34, RZ, !P1 ; BSSY B2, 0x3bb0 ; IMAD.WIDE R22, R23, R0, c[0x0][0x160] ; STG.E.64 [R22.64], R34 ; @P0 BRA 0x3ba0 ; ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; BSSY B3, 0x3a30 ; IMAD R40, R3, R45, R6 ; MOV R41, RZ ; @!P0 BRA 0x3a20 ; ISETP.GT.AND P0, PT, R39, RZ, PT ; BSSY B4, 0x3880 ; IMAD.MOV.U32 R41, RZ, RZ, RZ ; MOV R42, R39 ; IMAD.MOV.U32 R43, RZ, RZ, R11 ; @!P0 BRA 0x3870 ; ISETP.GT.AND P3, PT, R42, 0xc, PT ; BSSY B5, 0x3510 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P3 BRA 0x3500 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R23, R40, R41, RZ ; LDS.64 R28, [R43] ; IMAD.WIDE R22, R23, R0, c[0x0][0x178] ; LDG.E.64 R30, [R22.64] ; LDG.E.64 R24, [R22.64+0x8] ; LDG.E.64 R26, [R22.64+0x10] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; LDG.E.64 R22, [R22.64+0x18] ; IADD3 R33, R40, 0x4, R41 ; IMAD.WIDE R32, R33, R0, c[0x0][0x178] ; DFMA R30, R30, -R34, R28 ; STS.64 [R43], R30 ; LDS.64 R28, [R44] ; DFMA R28, R24, -R34, R28 ; STS.64 [R44], R28 ; LDG.E.64 R28, [R32.64] ; IMAD R44, R0, c[0x0][0x1dc], R44 ; LDS.64 R24, [R44] ; DFMA R26, R26, -R34, R24 ; LDG.E.64 R24, [R32.64+0x8] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; STS.64 [R44], R26 ; LDS.64 R30, [R43] ; LDG.E.64 R26, [R32.64+0x10] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R30, R22, -R34, R30 ; LDG.E.64 R22, [R32.64+0x18] ; STS.64 [R43], R30 ; LDS.64 R30, [R44] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; DFMA R30, R28, -R34, R30 ; STS.64 [R44], R30 ; LDS.64 R28, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R28, R24, -R34, R28 ; IADD3 R25, R40, 0x8, R41 ; IMAD.WIDE R32, R25, R0, c[0x0][0x178] ; STS.64 [R43], R28 ; LDS.64 R24, [R44] ; LDG.E.64 R28, [R32.64] ; DFMA R24, R26, -R34, R24 ; LDG.E.64 R26, [R32.64+0x8] ; STS.64 [R44], R24 ; LDG.E.64 R24, [R32.64+0x10] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; LDS.64 R30, [R43] ; DFMA R30, R22, -R34, R30 ; LDG.E.64 R22, [R32.64+0x18] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; STS.64 [R43], R30 ; LDS.64 R30, [R44] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; DFMA R30, R28, -R34, R30 ; STS.64 [R44], R30 ; LDS.64 R28, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R28, R26, -R34, R28 ; IADD3 R27, R40, 0xc, R41 ; IMAD.WIDE R32, R27, R0, c[0x0][0x178] ; STS.64 [R43], R28 ; LDS.64 R26, [R44] ; LDG.E.64 R28, [R32.64] ; DFMA R24, R24, -R34, R26 ; LDG.E.64 R26, [R32.64+0x8] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; STS.64 [R44], R24 ; LDS.64 R30, [R43] ; LDG.E.64 R24, [R32.64+0x10] ; DFMA R30, R22, -R34, R30 ; LDG.E.64 R22, [R32.64+0x18] ; STS.64 [R43], R30 ; IMAD R43, R0, c[0x0][0x1dc], R43 ; LDS.64 R30, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; IADD3 R42, R42, -0x10, RZ ; ISETP.GT.AND P3, PT, R42, 0xc, PT ; IADD3 R41, R41, 0x10, RZ ; DFMA R28, R28, -R34, R30 ; STS.64 [R43], R28 ; LDS.64 R28, [R44] ; DFMA R26, R26, -R34, R28 ; IMAD R29, R0, c[0x0][0x1dc], R44 ; STS.64 [R44], R26 ; LDS.64 R26, [R29] ; IMAD R33, R0, c[0x0][0x1dc], R29 ; DFMA R30, R24, -R34, R26 ; STS.64 [R29], R30 ; LDS.64 R24, [R33] ; IMAD R43, R0, c[0x0][0x1dc], R33 ; DFMA R22, R22, -R34, R24 ; STS.64 [R33], R22 ; @P3 BRA 0x2f40 ; BSYNC B5 ; ISETP.GT.AND P3, PT, R42, 0x4, PT ; BSSY B5, 0x3840 ; @!P3 BRA 0x3830 ; IMAD.IADD R33, R40, 0x1, R41 ; LDS.64 R28, [R43] ; IMAD.WIDE R32, R33, R0, c[0x0][0x178] ; LDG.E.64 R30, [R32.64] ; LDG.E.64 R26, [R32.64+0x8] ; LDG.E.64 R22, [R32.64+0x10] ; LDG.E.64 R24, [R32.64+0x18] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R30, R30, -R34, R28 ; STS.64 [R43], R30 ; LDS.64 R28, [R44] ; DFMA R26, R26, -R34, R28 ; IADD3 R29, R40, 0x4, R41 ; STS.64 [R44], R26 ; IMAD.WIDE R32, R29, R0, c[0x0][0x178] ; LDG.E.64 R28, [R32.64] ; IMAD R44, R0, c[0x0][0x1dc], R44 ; LDS.64 R26, [R44] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; DFMA R22, R22, -R34.reuse, R26 ; LDG.E.64 R26, [R32.64+0x18] ; STS.64 [R44], R22 ; LDS.64 R30, [R43] ; LDG.E.64 R22, [R32.64+0x8] ; DFMA R30, R24, -R34, R30 ; LDG.E.64 R24, [R32.64+0x10] ; STS.64 [R43], R30 ; IMAD R43, R0, c[0x0][0x1dc], R43 ; LDS.64 R30, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R28, R28, -R34, R30 ; STS.64 [R43], R28 ; LDS.64 R28, [R44] ; DFMA R22, R22, -R34, R28 ; IMAD R29, R0, c[0x0][0x1dc], R44 ; STS.64 [R44], R22 ; LDS.64 R22, [R29] ; IMAD R33, R0, c[0x0][0x1dc], R29 ; DFMA R30, R24, -R34, R22 ; STS.64 [R29], R30 ; LDS.64 R24, [R33] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD R43, R0, c[0x0][0x1dc], R33 ; IADD3 R42, R42, -0x8, RZ ; IADD3 R41, R41, 0x8, RZ ; DFMA R24, R26, -R34, R24 ; STS.64 [R33], R24 ; BSYNC B5 ; ISETP.NE.OR P0, PT, R42, RZ, P0 ; @!P0 BREAK B4 ; @!P0 BRA 0x3a20 ; BSYNC B4 ; IADD3 R33, R40, R41, RZ ; LDS.64 R28, [R43] ; IMAD.WIDE R32, R33, R0, c[0x0][0x178] ; LDG.E.64 R30, [R32.64] ; LDG.E.64 R26, [R32.64+0x8] ; LDG.E.64 R24, [R32.64+0x10] ; LDG.E.64 R22, [R32.64+0x18] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; IADD3 R42, R42, -0x4, RZ ; IADD3 R41, R41, 0x4, RZ ; ISETP.NE.AND P0, PT, R42, RZ, PT ; DFMA R28, R30, -R34, R28 ; STS.64 [R43], R28 ; LDS.64 R30, [R44] ; IMAD R29, R0, c[0x0][0x1dc], R44 ; IMAD R33, R0, c[0x0][0x1dc], R29 ; IMAD R43, R0, c[0x0][0x1dc], R33 ; DFMA R30, R26, -R34, R30 ; STS.64 [R44], R30 ; LDS.64 R26, [R29] ; DFMA R26, R24, -R34, R26 ; STS.64 [R29], R26 ; LDS.64 R24, [R33] ; DFMA R22, R22, -R34, R24 ; STS.64 [R33], R22 ; @P0 BRA 0x3880 ; BSYNC B3 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x3ba0 ; IMAD.IADD R23, R40, 0x1, R41 ; IMAD.WIDE R22, R23, R0, c[0x0][0x178] ; LDG.E.64 R24, [R22.64] ; IMAD R41, R41, c[0x0][0x1dc], R2 ; ISETP.NE.AND P0, PT, R10, 0x1, PT ; SHF.L.U32 R41, R41, 0x3, RZ ; LDS.64 R26, [R41] ; DFMA R24, R24, -R34, R26 ; STS.64 [R41], R24 ; @!P0 BRA 0x3ba0 ; LDG.E.64 R24, [R22.64+0x8] ; ISETP.NE.AND P0, PT, R10, 0x2, PT ; @P0 LDG.E.64 R26, [R22.64+0x10] ; IMAD R41, R0, c[0x0][0x1dc], R41 ; @P0 IMAD R31, R0, c[0x0][0x1dc], R41 ; LDS.64 R28, [R41] ; DFMA R24, R24, -R34, R28 ; STS.64 [R41], R24 ; @P0 LDS.64 R28, [R31] ; @P0 DFMA R26, R26, -R34, R28 ; @P0 STS.64 [R31], R26 ; BSYNC B2 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1d8] ; DADD R22, R36, -R34 ; ISETP.NE.AND P0, PT, R0.reuse, 0x2, PT ; DMUL R22, R22, R22 ; ISETP.NE.AND P0, PT, R0, 0x4, P0 ; @!P0 DMUL R24, R22, R18 ; @!P0 ISETP.NE.AND P2, PT, R45.reuse, RZ, !P2 ; IADD3 R45, R45, 0x1, RZ ; @!P0 ISETP.EQ.OR P2, PT, R8, RZ, P2 ; @!P0 FSEL R25, R25, R23, P2 ; @!P0 FSEL R0, R24, R22, P2 ; ISETP.GE.AND P2, PT, R45, R7, PT ; @!P0 IMAD.MOV.U32 R23, RZ, RZ, R25 ; @!P0 MOV R22, R0 ; DSETP.GT.AND P0, PT, R22, R12, PT ; FSEL R12, R22, R12, P0 ; FSEL R13, R23, R13, P0 ; @P2 CALL.REL.NOINC 0x3ce0 ; BRA 0xf80 ; BRA 0x6a70 ; MOV R45, RZ ; HFMA2.MMA R0, -RZ, RZ, 0, 4.76837158203125e-07 ; IMAD.IADD R37, R4, 0x1, R45 ; IMAD.WIDE R36, R37, R0, c[0x0][0x160] ; LDG.E.64 R36, [R36.64] ; BSSY B2, 0x58d0 ; CS2R R32, SRZ ; DSETP.NEU.AND P0, PT, R36, RZ, PT ; @P0 BRA 0x4940 ; @!P1 BRA 0x58c0 ; ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; BSSY B3, 0x47e0 ; IMAD R34, R3, R45, R6 ; CS2R R32, SRZ ; IMAD.MOV.U32 R35, RZ, RZ, RZ ; @!P0 BRA 0x47d0 ; ISETP.GT.AND P0, PT, R39, RZ, PT ; BSSY B4, 0x4670 ; MOV R35, RZ ; IMAD.MOV.U32 R40, RZ, RZ, R39 ; MOV R41, R11 ; CS2R R32, SRZ ; @!P0 BRA 0x4660 ; ISETP.GT.AND P2, PT, R40, 0xc, PT ; BSSY B5, 0x4380 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0x4370 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.IADD R23, R34, 0x1, R35 ; LDS.64 R30, [R41] ; IMAD.WIDE R22, R23, R0, c[0x0][0x178] ; LDG.E.64 R28, [R22.64] ; LDG.E.64 R26, [R22.64+0x8] ; LDG.E.64 R24, [R22.64+0x10] ; LDG.E.64 R22, [R22.64+0x18] ; IMAD R42, R0, c[0x0][0x1dc], R41 ; IMAD R43, R0, c[0x0][0x1dc], R42 ; IMAD R41, R0, c[0x0][0x1dc], R43 ; DFMA R32, R30, R28, R32 ; LDS.64 R28, [R42] ; IADD3 R31, R34, 0x4, R35 ; DFMA R32, R28, R26, R32 ; IMAD.WIDE R28, R31, R0, c[0x0][0x178] ; LDS.64 R30, [R43] ; LDG.E.64 R26, [R28.64] ; DFMA R30, R30, R24, R32 ; LDG.E.64 R24, [R28.64+0x8] ; LDS.64 R32, [R41] ; DFMA R30, R32, R22, R30 ; LDG.E.64 R22, [R28.64+0x10] ; LDG.E.64 R32, [R28.64+0x18] ; IMAD R44, R0, c[0x0][0x1dc], R41 ; LDS.64 R42, [R44] ; DFMA R26, R42, R26, R30 ; IMAD R42, R0, c[0x0][0x1dc], R44 ; IADD3 R43, R34, 0x8, R35 ; IMAD R41, R0, c[0x0][0x1dc], R42 ; LDS.64 R30, [R42] ; LDS.64 R28, [R41] ; DFMA R30, R30, R24, R26 ; IMAD.WIDE R26, R43, R0, c[0x0][0x178] ; LDG.E.64 R24, [R26.64] ; IMAD R43, R0, c[0x0][0x1dc], R41 ; DFMA R28, R28, R22, R30 ; LDG.E.64 R22, [R26.64+0x8] ; LDS.64 R30, [R43] ; DFMA R30, R30, R32, R28 ; LDG.E.64 R28, [R26.64+0x10] ; LDG.E.64 R32, [R26.64+0x18] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; IMAD R41, R0, c[0x0][0x1dc], R44 ; LDS.64 R42, [R44] ; IADD3 R44, R34, 0xc, R35 ; DFMA R30, R42, R24, R30 ; LDS.64 R24, [R41] ; DFMA R42, R24, R22, R30 ; IMAD.WIDE R24, R44, R0, c[0x0][0x178] ; IMAD R44, R0.reuse, c[0x0][0x1dc], R41 ; LDG.E.64 R22, [R24.64] ; IMAD R41, R0, c[0x0][0x1dc], R44 ; LDS.64 R30, [R44] ; LDG.E.64 R26, [R24.64+0x8] ; DFMA R30, R30, R28, R42 ; LDS.64 R28, [R41] ; DFMA R30, R28, R32, R30 ; LDG.E.64 R28, [R24.64+0x10] ; LDG.E.64 R32, [R24.64+0x18] ; IMAD R41, R0, c[0x0][0x1dc], R41 ; LDS.64 R42, [R41] ; IADD3 R40, R40, -0x10, RZ ; ISETP.GT.AND P2, PT, R40, 0xc, PT ; IADD3 R35, R35, 0x10, RZ ; DFMA R22, R42, R22, R30 ; IMAD R43, R0, c[0x0][0x1dc], R41 ; LDS.64 R30, [R43] ; IMAD R42, R0, c[0x0][0x1dc], R43 ; IMAD R44, R0.reuse, c[0x0][0x1dc], R42 ; DFMA R30, R30, R26, R22 ; LDS.64 R26, [R42] ; LDS.64 R22, [R44] ; IMAD R41, R0, c[0x0][0x1dc], R44 ; DFMA R26, R26, R28, R30 ; DFMA R32, R22, R32, R26 ; @P2 BRA 0x3eb0 ; BSYNC B5 ; ISETP.GT.AND P2, PT, R40, 0x4, PT ; BSSY B5, 0x4630 ; @!P2 BRA 0x4620 ; IADD3 R43, R34, R35, RZ ; LDS.64 R30, [R41] ; IMAD.WIDE R42, R43, R0, c[0x0][0x178] ; LDG.E.64 R28, [R42.64] ; LDG.E.64 R22, [R42.64+0x8] ; LDG.E.64 R24, [R42.64+0x10] ; LDG.E.64 R26, [R42.64+0x18] ; IMAD R44, R0, c[0x0][0x1dc], R41 ; DFMA R30, R30, R28, R32 ; LDS.64 R28, [R44] ; IMAD R44, R0, c[0x0][0x1dc], R44 ; LDS.64 R32, [R44] ; DFMA R30, R28, R22, R30 ; IADD3 R29, R34, 0x4, R35 ; IMAD.WIDE R28, R29, R0, c[0x0][0x178] ; LDG.E.64 R22, [R28.64] ; IMAD R41, R0, c[0x0][0x1dc], R44 ; DFMA R32, R32, R24, R30 ; LDG.E.64 R24, [R28.64+0x8] ; LDS.64 R30, [R41] ; DFMA R30, R30, R26, R32 ; LDG.E.64 R26, [R28.64+0x10] ; LDG.E.64 R32, [R28.64+0x18] ; IMAD R41, R0, c[0x0][0x1dc], R41 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R40, R40, -0x8, RZ ; LDS.64 R42, [R41] ; IADD3 R35, R35, 0x8, RZ ; DFMA R22, R42, R22, R30 ; IMAD R43, R0, c[0x0][0x1dc], R41 ; IMAD R42, R0.reuse, c[0x0][0x1dc], R43 ; LDS.64 R30, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R42 ; IMAD R41, R0, c[0x0][0x1dc], R44 ; DFMA R30, R30, R24, R22 ; LDS.64 R24, [R42] ; LDS.64 R22, [R44] ; DFMA R24, R24, R26, R30 ; DFMA R32, R22, R32, R24 ; BSYNC B5 ; ISETP.NE.OR P0, PT, R40, RZ, P0 ; @!P0 BREAK B4 ; @!P0 BRA 0x47d0 ; BSYNC B4 ; IMAD.IADD R43, R34, 0x1, R35 ; LDS.64 R30, [R41] ; IMAD.WIDE R42, R43, R0, c[0x0][0x178] ; LDG.E.64 R28, [R42.64] ; LDG.E.64 R26, [R42.64+0x8] ; LDG.E.64 R24, [R42.64+0x10] ; LDG.E.64 R22, [R42.64+0x18] ; IMAD R44, R0, c[0x0][0x1dc], R41 ; IADD3 R40, R40, -0x4, RZ ; IADD3 R35, R35, 0x4, RZ ; ISETP.NE.AND P0, PT, R40, RZ, PT ; DFMA R28, R30, R28, R32 ; LDS.64 R30, [R44] ; IMAD R44, R0, c[0x0][0x1dc], R44 ; DFMA R28, R30, R26, R28 ; LDS.64 R26, [R44] ; IMAD R31, R0, c[0x0][0x1dc], R44 ; IMAD R41, R0, c[0x0][0x1dc], R31 ; LDS.64 R32, [R31] ; DFMA R24, R26, R24, R28 ; DFMA R32, R32, R22, R24 ; @P0 BRA 0x4670 ; BSYNC B3 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x58c0 ; IADD3 R23, R34, R35, RZ ; IMAD.WIDE R22, R23, R0, c[0x0][0x178] ; LDG.E.64 R24, [R22.64] ; IMAD R35, R35, c[0x0][0x1dc], R2 ; ISETP.NE.AND P0, PT, R10, 0x1, PT ; IMAD.SHL.U32 R35, R35, 0x8, RZ ; LDS.64 R26, [R35] ; DFMA R32, R26, R24, R32 ; @!P0 BRA 0x58c0 ; LDG.E.64 R24, [R22.64+0x8] ; IMAD R35, R0, c[0x0][0x1dc], R35 ; ISETP.NE.AND P0, PT, R10, 0x2, PT ; LDS.64 R26, [R35] ; DFMA R32, R26, R24, R32 ; @!P0 BRA 0x58c0 ; LDG.E.64 R22, [R22.64+0x10] ; IMAD R24, R0, c[0x0][0x1dc], R35 ; LDS.64 R24, [R24] ; DFMA R32, R24, R22, R32 ; BRA 0x58c0 ; @!P1 BRA 0x58c0 ; ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; BSSY B3, 0x5720 ; IMAD R41, R3, R45, R6 ; MOV R42, RZ ; CS2R R32, SRZ ; @!P0 BRA 0x5710 ; ISETP.GT.AND P0, PT, R39, RZ, PT ; BSSY B4, 0x5530 ; IMAD.MOV.U32 R42, RZ, RZ, RZ ; MOV R40, R39 ; IMAD.MOV.U32 R44, RZ, RZ, R11 ; CS2R R32, SRZ ; @!P0 BRA 0x5520 ; ISETP.GT.AND P2, PT, R40, 0xc, PT ; BSSY B5, 0x5140 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0x5130 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R23, R41, R42, RZ ; LDS.64 R28, [R44] ; IMAD.WIDE R22, R23, R0, c[0x0][0x178] ; LDG.E.64 R30, [R22.64] ; LDG.E.64 R26, [R22.64+0x8] ; LDG.E.64 R24, [R22.64+0x10] ; LDG.E.64 R22, [R22.64+0x18] ; IMAD R35, R0, c[0x0][0x1dc], R44 ; IADD3 R43, R41, 0x4, R42 ; DFMA R28, R36, R30, R28 ; DFMA R32, R30, R28, R32 ; STS.64 [R44], R28 ; LDS.64 R30, [R35] ; DFMA R30, R36, R26, R30 ; DFMA R32, R26, R30, R32 ; STS.64 [R35], R30 ; IMAD.WIDE R26, R43, R0, c[0x0][0x178] ; IMAD R43, R0.reuse, c[0x0][0x1dc], R35 ; LDG.E.64 R28, [R26.64] ; LDS.64 R30, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R30, R36, R24, R30 ; DFMA R32, R24, R30, R32 ; STS.64 [R43], R30 ; LDG.E.64 R24, [R26.64+0x8] ; LDS.64 R34, [R44] ; LDG.E.64 R30, [R26.64+0x18] ; DFMA R34, R36, R22, R34 ; DFMA R32, R22, R34, R32 ; LDG.E.64 R22, [R26.64+0x10] ; STS.64 [R44], R34 ; IMAD R44, R0, c[0x0][0x1dc], R44 ; LDS.64 R34, [R44] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; IADD3 R27, R41, 0x8, R42 ; IMAD.WIDE R26, R27, R0, c[0x0][0x178] ; DFMA R34, R36, R28, R34 ; DFMA R32, R28, R34, R32 ; STS.64 [R44], R34 ; LDS.64 R28, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R28, R36, R24, R28 ; DFMA R32, R24, R28, R32 ; STS.64 [R43], R28 ; LDG.E.64 R24, [R26.64] ; LDS.64 R34, [R44] ; DFMA R34, R36, R22, R34 ; DFMA R32, R22, R34, R32 ; LDG.E.64 R22, [R26.64+0x8] ; STS.64 [R44], R34 ; IMAD R35, R0, c[0x0][0x1dc], R44 ; LDS.64 R28, [R35] ; DFMA R28, R36, R30, R28 ; DFMA R32, R30, R28, R32 ; LDG.E.64 R30, [R26.64+0x10] ; LDG.E.64 R26, [R26.64+0x18] ; IMAD R43, R0, c[0x0][0x1dc], R35 ; STS.64 [R35], R28 ; LDS.64 R28, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R34, R36, R24, R28 ; DFMA R32, R24, R34, R32 ; STS.64 [R43], R34 ; LDS.64 R24, [R44] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; DFMA R24, R36, R22, R24 ; DFMA R32, R22, R24, R32 ; IADD3 R23, R41, 0xc, R42 ; STS.64 [R44], R24 ; LDS.64 R28, [R43] ; IMAD.WIDE R24, R23, R0, c[0x0][0x178] ; LDG.E.64 R22, [R24.64] ; IMAD R35, R0, c[0x0][0x1dc], R43 ; DFMA R28, R36, R30, R28 ; DFMA R32, R30, R28, R32 ; STS.64 [R43], R28 ; LDS.64 R30, [R35] ; LDG.E.64 R28, [R24.64+0x8] ; DFMA R30, R36, R26, R30 ; DFMA R32, R26, R30, R32 ; LDG.E.64 R26, [R24.64+0x10] ; LDG.E.64 R24, [R24.64+0x18] ; IMAD R34, R0, c[0x0][0x1dc], R35 ; STS.64 [R35], R30 ; LDS.64 R30, [R34] ; IMAD R43, R0, c[0x0][0x1dc], R34 ; IMAD R35, R0, c[0x0][0x1dc], R43 ; IADD3 R40, R40, -0x10, RZ ; ISETP.GT.AND P2, PT, R40, 0xc, PT ; DFMA R30, R36, R22, R30 ; DFMA R32, R22, R30, R32 ; STS.64 [R34], R30 ; LDS.64 R22, [R43] ; DFMA R30, R36, R28, R22 ; STS.64 [R43], R30 ; LDS.64 R22, [R35] ; IMAD R34, R0, c[0x0][0x1dc], R35 ; DFMA R32, R28, R30, R32 ; DFMA R22, R36, R26, R22 ; STS.64 [R35], R22 ; LDS.64 R28, [R34] ; DFMA R32, R26, R22, R32 ; IADD3 R42, R42, 0x10, RZ ; IMAD R44, R0, c[0x0][0x1dc], R34 ; DFMA R28, R36, R24, R28 ; STS.64 [R34], R28 ; DFMA R32, R24, R28, R32 ; @P2 BRA 0x4a70 ; BSYNC B5 ; ISETP.GT.AND P2, PT, R40, 0x4, PT ; BSSY B5, 0x54f0 ; @!P2 BRA 0x54e0 ; IMAD.IADD R35, R41, 0x1, R42 ; LDS.64 R26, [R44] ; IMAD.WIDE R34, R35, R0, c[0x0][0x178] ; LDG.E.64 R24, [R34.64] ; LDG.E.64 R30, [R34.64+0x8] ; LDG.E.64 R22, [R34.64+0x10] ; LDG.E.64 R28, [R34.64+0x18] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; DFMA R26, R36, R24, R26 ; DFMA R24, R24, R26, R32 ; STS.64 [R44], R26 ; LDS.64 R32, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R32, R36, R30, R32 ; DFMA R30, R30, R32, R24 ; STS.64 [R43], R32 ; IADD3 R25, R41, 0x4, R42 ; IMAD.WIDE R34, R25, R0, c[0x0][0x178] ; LDS.64 R24, [R44] ; LDG.E.64 R26, [R34.64] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; LDG.E.64 R32, [R34.64+0x18] ; DFMA R24, R36, R22, R24 ; DFMA R22, R22, R24, R30 ; STS.64 [R44], R24 ; LDS.64 R30, [R43] ; LDG.E.64 R24, [R34.64+0x8] ; DFMA R30, R36, R28, R30 ; DFMA R28, R28, R30, R22 ; LDG.E.64 R22, [R34.64+0x10] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; STS.64 [R43], R30 ; LDS.64 R30, [R44] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R40, R40, -0x8, RZ ; IADD3 R42, R42, 0x8, RZ ; DFMA R30, R36, R26, R30 ; DFMA R28, R26, R30, R28 ; STS.64 [R44], R30 ; LDS.64 R26, [R43] ; IMAD R31, R0, c[0x0][0x1dc], R43 ; DFMA R34, R36, R24, R26 ; STS.64 [R43], R34 ; LDS.64 R26, [R31] ; DFMA R28, R24, R34, R28 ; IMAD R35, R0, c[0x0][0x1dc], R31 ; DFMA R26, R36, R22, R26 ; STS.64 [R31], R26 ; LDS.64 R24, [R35] ; DFMA R28, R22, R26, R28 ; IMAD R44, R0, c[0x0][0x1dc], R35 ; DFMA R24, R36, R32, R24 ; STS.64 [R35], R24 ; DFMA R32, R32, R24, R28 ; BSYNC B5 ; ISETP.NE.OR P0, PT, R40, RZ, P0 ; @!P0 BREAK B4 ; @!P0 BRA 0x5710 ; BSYNC B4 ; IADD3 R35, R41, R42, RZ ; LDS.64 R28, [R44] ; IMAD.WIDE R34, R35, R0, c[0x0][0x178] ; LDG.E.64 R30, [R34.64] ; LDG.E.64 R26, [R34.64+0x8] ; LDG.E.64 R24, [R34.64+0x10] ; LDG.E.64 R22, [R34.64+0x18] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; IADD3 R40, R40, -0x4, RZ ; IADD3 R42, R42, 0x4, RZ ; ISETP.NE.AND P0, PT, R40, RZ, PT ; IMAD R35, R0, c[0x0][0x1dc], R43 ; IMAD R34, R0, c[0x0][0x1dc], R35 ; DFMA R28, R36, R30, R28 ; DFMA R30, R30, R28, R32 ; STS.64 [R44], R28 ; LDS.64 R32, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R34 ; DFMA R28, R36, R26, R32 ; DFMA R30, R26, R28, R30 ; STS.64 [R43], R28 ; LDS.64 R32, [R35] ; DFMA R26, R36, R24, R32 ; DFMA R30, R24, R26, R30 ; STS.64 [R35], R26 ; LDS.64 R32, [R34] ; DFMA R32, R36, R22, R32 ; STS.64 [R34], R32 ; DFMA R32, R22, R32, R30 ; @P0 BRA 0x5530 ; BSYNC B3 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x58c0 ; IMAD.IADD R23, R41, 0x1, R42 ; IMAD.WIDE R22, R23, R0, c[0x0][0x178] ; LDG.E.64 R24, [R22.64] ; IMAD R42, R42, c[0x0][0x1dc], R2 ; ISETP.NE.AND P0, PT, R10, 0x1, PT ; SHF.L.U32 R29, R42, 0x3, RZ ; LDS.64 R26, [R29] ; DFMA R26, R36, R24, R26 ; DFMA R32, R24, R26, R32 ; STS.64 [R29], R26 ; @!P0 BRA 0x58c0 ; LDG.E.64 R24, [R22.64+0x8] ; ISETP.NE.AND P0, PT, R10, 0x2, PT ; @P0 LDG.E.64 R26, [R22.64+0x10] ; IMAD R41, R0, c[0x0][0x1dc], R29 ; @P0 IMAD R35, R0, c[0x0][0x1dc], R41 ; LDS.64 R28, [R41] ; DFMA R28, R36, R24, R28 ; DFMA R32, R24, R28, R32 ; STS.64 [R41], R28 ; @P0 LDS.64 R30, [R35] ; @P0 DFMA R30, R36, R26, R30 ; @P0 DFMA R32, R26, R30, R32 ; @P0 STS.64 [R35], R30 ; BSYNC B2 ; DMUL R32, R32, R18 ; BSSY B2, 0x59a0 ; DSETP.GEU.AND P0, PT, R16, |R32|, PT ; DSETP.GT.AND P2, PT, R32, RZ, PT ; @!P0 BRA P2, 0x5980 ; DSETP.GEU.AND P0, PT, R16, |R32|, PT ; CS2R R22, SRZ ; DSETP.GEU.OR P0, PT, R32, RZ, P0 ; @P0 BRA 0x5990 ; DADD R22, R16, R32 ; BRA 0x5990 ; DADD R22, -R16, R32 ; BSYNC B2 ; ISETP.NE.AND P2, PT, R8, 0x1, PT ; BSSY B2, 0x5b60 ; ISETP.EQ.AND P0, PT, R45, RZ, PT ; @!P2 BRA P0, 0x5b50 ; DADD R30, R14, 1 ; IMAD.MOV.U32 R26, RZ, RZ, 0x1 ; FSETP.GEU.AND P3, PT, |R23|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x5b50 ; MUFU.RCP64H R27, R31 ; DFMA R24, -R30, R26, 1 ; DFMA R24, R24, R24, R24 ; DFMA R24, R26, R24, R26 ; DFMA R28, -R30, R24, 1 ; DFMA R28, R24, R28, R24 ; DMUL R24, R28, R22 ; DFMA R26, -R30, R24, R22 ; DFMA R32, R28, R26, R24 ; FFMA R0, RZ, R31, R33 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P3, 0x5b40 ; MOV R26, R22 ; IMAD.MOV.U32 R27, RZ, RZ, R23 ; MOV R24, R30 ; IMAD.MOV.U32 R25, RZ, RZ, R31 ; MOV R0, 0x5b40 ; CALL.REL.NOINC 0x70e0 ; BSYNC B3 ; BSYNC B2 ; IADD3 R23, R4, R45, RZ ; IMAD.MOV.U32 R0, RZ, RZ, 0x8 ; DSETP.EQ.OR P0, PT, R32, RZ, !P1 ; BSSY B2, 0x6940 ; IMAD.WIDE R22, R23, R0, c[0x0][0x160] ; STG.E.64 [R22.64], R32 ; @P0 BRA 0x6930 ; ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; BSSY B3, 0x67c0 ; IMAD R40, R3, R45, R6 ; MOV R41, RZ ; @!P0 BRA 0x67b0 ; ISETP.GT.AND P0, PT, R39, RZ, PT ; BSSY B4, 0x6610 ; IMAD.MOV.U32 R41, RZ, RZ, RZ ; MOV R42, R39 ; IMAD.MOV.U32 R43, RZ, RZ, R11 ; @!P0 BRA 0x6600 ; ISETP.GT.AND P3, PT, R42, 0xc, PT ; BSSY B5, 0x62a0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P3 BRA 0x6290 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R23, R40, R41, RZ ; LDS.64 R28, [R43] ; IMAD.WIDE R22, R23, R0, c[0x0][0x178] ; LDG.E.64 R30, [R22.64] ; LDG.E.64 R24, [R22.64+0x8] ; LDG.E.64 R26, [R22.64+0x10] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; LDG.E.64 R22, [R22.64+0x18] ; IADD3 R35, R40, 0x4, R41 ; IMAD.WIDE R34, R35, R0, c[0x0][0x178] ; DFMA R30, R30, -R32, R28 ; STS.64 [R43], R30 ; LDS.64 R28, [R44] ; DFMA R28, R24, -R32, R28 ; STS.64 [R44], R28 ; LDG.E.64 R28, [R34.64] ; IMAD R44, R0, c[0x0][0x1dc], R44 ; LDS.64 R24, [R44] ; DFMA R26, R26, -R32, R24 ; LDG.E.64 R24, [R34.64+0x8] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; STS.64 [R44], R26 ; LDS.64 R30, [R43] ; LDG.E.64 R26, [R34.64+0x10] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R30, R22, -R32, R30 ; LDG.E.64 R22, [R34.64+0x18] ; STS.64 [R43], R30 ; LDS.64 R30, [R44] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; DFMA R30, R28, -R32, R30 ; STS.64 [R44], R30 ; LDS.64 R28, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R28, R24, -R32, R28 ; IADD3 R25, R40, 0x8, R41 ; IMAD.WIDE R34, R25, R0, c[0x0][0x178] ; STS.64 [R43], R28 ; LDS.64 R24, [R44] ; LDG.E.64 R28, [R34.64] ; DFMA R24, R26, -R32, R24 ; LDG.E.64 R26, [R34.64+0x8] ; STS.64 [R44], R24 ; LDG.E.64 R24, [R34.64+0x10] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; LDS.64 R30, [R43] ; DFMA R30, R22, -R32, R30 ; LDG.E.64 R22, [R34.64+0x18] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; STS.64 [R43], R30 ; LDS.64 R30, [R44] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; DFMA R30, R28, -R32, R30 ; STS.64 [R44], R30 ; LDS.64 R28, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R28, R26, -R32, R28 ; IADD3 R27, R40, 0xc, R41 ; IMAD.WIDE R34, R27, R0, c[0x0][0x178] ; STS.64 [R43], R28 ; LDS.64 R26, [R44] ; LDG.E.64 R28, [R34.64] ; DFMA R24, R24, -R32, R26 ; LDG.E.64 R26, [R34.64+0x8] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; STS.64 [R44], R24 ; LDS.64 R30, [R43] ; LDG.E.64 R24, [R34.64+0x10] ; DFMA R30, R22, -R32, R30 ; LDG.E.64 R22, [R34.64+0x18] ; STS.64 [R43], R30 ; IMAD R43, R0, c[0x0][0x1dc], R43 ; LDS.64 R30, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; IADD3 R42, R42, -0x10, RZ ; ISETP.GT.AND P3, PT, R42, 0xc, PT ; IADD3 R41, R41, 0x10, RZ ; DFMA R28, R28, -R32, R30 ; STS.64 [R43], R28 ; LDS.64 R28, [R44] ; DFMA R26, R26, -R32, R28 ; IMAD R29, R0, c[0x0][0x1dc], R44 ; STS.64 [R44], R26 ; LDS.64 R26, [R29] ; IMAD R35, R0, c[0x0][0x1dc], R29 ; DFMA R30, R24, -R32, R26 ; STS.64 [R29], R30 ; LDS.64 R24, [R35] ; IMAD R43, R0, c[0x0][0x1dc], R35 ; DFMA R22, R22, -R32, R24 ; STS.64 [R35], R22 ; @P3 BRA 0x5cd0 ; BSYNC B5 ; ISETP.GT.AND P3, PT, R42, 0x4, PT ; BSSY B5, 0x65d0 ; @!P3 BRA 0x65c0 ; IMAD.IADD R35, R40, 0x1, R41 ; LDS.64 R28, [R43] ; IMAD.WIDE R34, R35, R0, c[0x0][0x178] ; LDG.E.64 R30, [R34.64] ; LDG.E.64 R26, [R34.64+0x8] ; LDG.E.64 R22, [R34.64+0x10] ; LDG.E.64 R24, [R34.64+0x18] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R30, R30, -R32, R28 ; STS.64 [R43], R30 ; LDS.64 R28, [R44] ; DFMA R26, R26, -R32, R28 ; IADD3 R29, R40, 0x4, R41 ; STS.64 [R44], R26 ; IMAD.WIDE R34, R29, R0, c[0x0][0x178] ; LDG.E.64 R28, [R34.64] ; IMAD R44, R0, c[0x0][0x1dc], R44 ; LDS.64 R26, [R44] ; IMAD R43, R0, c[0x0][0x1dc], R44 ; DFMA R22, R22, -R32.reuse, R26 ; LDG.E.64 R26, [R34.64+0x18] ; STS.64 [R44], R22 ; LDS.64 R30, [R43] ; LDG.E.64 R22, [R34.64+0x8] ; DFMA R30, R24, -R32, R30 ; LDG.E.64 R24, [R34.64+0x10] ; STS.64 [R43], R30 ; IMAD R43, R0, c[0x0][0x1dc], R43 ; LDS.64 R30, [R43] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; DFMA R28, R28, -R32, R30 ; STS.64 [R43], R28 ; LDS.64 R28, [R44] ; DFMA R22, R22, -R32, R28 ; IMAD R29, R0, c[0x0][0x1dc], R44 ; STS.64 [R44], R22 ; LDS.64 R22, [R29] ; IMAD R35, R0, c[0x0][0x1dc], R29 ; DFMA R30, R24, -R32, R22 ; STS.64 [R29], R30 ; LDS.64 R24, [R35] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD R43, R0, c[0x0][0x1dc], R35 ; IADD3 R42, R42, -0x8, RZ ; IADD3 R41, R41, 0x8, RZ ; DFMA R24, R26, -R32, R24 ; STS.64 [R35], R24 ; BSYNC B5 ; ISETP.NE.OR P0, PT, R42, RZ, P0 ; @!P0 BREAK B4 ; @!P0 BRA 0x67b0 ; BSYNC B4 ; IADD3 R35, R40, R41, RZ ; LDS.64 R28, [R43] ; IMAD.WIDE R34, R35, R0, c[0x0][0x178] ; LDG.E.64 R30, [R34.64] ; LDG.E.64 R26, [R34.64+0x8] ; LDG.E.64 R24, [R34.64+0x10] ; LDG.E.64 R22, [R34.64+0x18] ; IMAD R44, R0, c[0x0][0x1dc], R43 ; IADD3 R42, R42, -0x4, RZ ; IADD3 R41, R41, 0x4, RZ ; ISETP.NE.AND P0, PT, R42, RZ, PT ; DFMA R28, R30, -R32, R28 ; STS.64 [R43], R28 ; LDS.64 R30, [R44] ; IMAD R29, R0, c[0x0][0x1dc], R44 ; IMAD R35, R0, c[0x0][0x1dc], R29 ; IMAD R43, R0, c[0x0][0x1dc], R35 ; DFMA R30, R26, -R32, R30 ; STS.64 [R44], R30 ; LDS.64 R26, [R29] ; DFMA R26, R24, -R32, R26 ; STS.64 [R29], R26 ; LDS.64 R24, [R35] ; DFMA R22, R22, -R32, R24 ; STS.64 [R35], R22 ; @P0 BRA 0x6610 ; BSYNC B3 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x6930 ; IMAD.IADD R23, R40, 0x1, R41 ; IMAD.WIDE R22, R23, R0, c[0x0][0x178] ; LDG.E.64 R24, [R22.64] ; IMAD R41, R41, c[0x0][0x1dc], R2 ; ISETP.NE.AND P0, PT, R10, 0x1, PT ; SHF.L.U32 R41, R41, 0x3, RZ ; LDS.64 R26, [R41] ; DFMA R24, R24, -R32, R26 ; STS.64 [R41], R24 ; @!P0 BRA 0x6930 ; LDG.E.64 R24, [R22.64+0x8] ; ISETP.NE.AND P0, PT, R10, 0x2, PT ; @P0 LDG.E.64 R26, [R22.64+0x10] ; IMAD R41, R0, c[0x0][0x1dc], R41 ; @P0 IMAD R31, R0, c[0x0][0x1dc], R41 ; LDS.64 R28, [R41] ; DFMA R24, R24, -R32, R28 ; STS.64 [R41], R24 ; @P0 LDS.64 R28, [R31] ; @P0 DFMA R26, R26, -R32, R28 ; @P0 STS.64 [R31], R26 ; BSYNC B2 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1d8] ; DADD R22, R36, -R32 ; ISETP.NE.AND P0, PT, R0.reuse, 0x2, PT ; DMUL R22, R22, R22 ; ISETP.NE.AND P0, PT, R0, 0x4, P0 ; @!P0 DMUL R24, R22, R18 ; @!P0 ISETP.NE.AND P2, PT, R45.reuse, RZ, !P2 ; IADD3 R45, R45, 0x1, RZ ; @!P0 ISETP.EQ.OR P2, PT, R8, RZ, P2 ; @!P0 FSEL R25, R25, R23, P2 ; @!P0 FSEL R0, R24, R22, P2 ; ISETP.GE.AND P2, PT, R45, R7, PT ; @!P0 IMAD.MOV.U32 R23, RZ, RZ, R25 ; @!P0 MOV R22, R0 ; DSETP.GT.AND P0, PT, R22, R12, PT ; FSEL R12, R22, R12, P0 ; FSEL R13, R23, R13, P0 ; @P2 CALL.REL.NOINC 0x6a70 ; BRA 0x3d00 ; BSYNC B1 ; IADD3 R38, R38, 0x1, RZ ; DSETP.GE.AND P2, PT, R12, R20, PT ; ISETP.GE.AND P0, PT, R38, R5, PT ; @!P0 BRA P2, 0xee0 ; BSYNC B0 ; WARPSYNC 0xffffffff ; S2R R3, SR_CTAID.X ; ISETP.GE.AND P1, PT, R7, 0x1, PT ; IMAD R3, R3, c[0x0][0x1dc], R2 ; SHF.R.S32.HI R0, RZ, 0x1f, R3 ; LEA R2, P0, R3, c[0x0][0x198], 0x3 ; LEA.HI.X R3, R3, c[0x0][0x19c], R0, 0x3, P0 ; @!P1 EXIT ; LDG.E.64 R2, [R2.64] ; IADD3 R0, R7.reuse, -0x1, RZ ; BSSY B0, 0x6d30 ; LOP3.LUT R16, R7, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; ISETP.NE.AND P1, PT, R16, RZ, PT ; MOV R5, RZ ; @!P0 BRA 0x6d20 ; HFMA2.MMA R5, -RZ, RZ, 0, 0 ; IMAD.IADD R0, R7, 0x1, -R16 ; MOV R7, 0x8 ; IMAD.IADD R6, R4, 0x1, R5 ; IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; LDG.E.64 R8, [R6.64] ; LDG.E.64 R10, [R6.64+0x8] ; LDG.E.64 R12, [R6.64+0x10] ; LDG.E.64 R14, [R6.64+0x18] ; IADD3 R0, R0, -0x4, RZ ; IADD3 R5, R5, 0x4, RZ ; ISETP.NE.AND P0, PT, R0, RZ, PT ; DMUL R8, R2, R8 ; DMUL R10, R2, R10 ; STG.E.64 [R6.64], R8 ; DMUL R12, R2, R12 ; STG.E.64 [R6.64+0x8], R10 ; DMUL R14, R2, R14 ; STG.E.64 [R6.64+0x10], R12 ; STG.E.64 [R6.64+0x18], R14 ; @P0 BRA 0x6bf0 ; BSYNC B0 ; @!P1 EXIT ; IMAD.IADD R4, R4, 0x1, R5 ; MOV R5, 0x8 ; IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; IMAD.MOV.U32 R0, RZ, RZ, R4 ; MOV R9, R5 ; IMAD.MOV.U32 R6, RZ, RZ, R0 ; MOV R7, R9 ; LDG.E.64 R4, [R6.64] ; IADD3 R16, R16, -0x1, RZ ; IADD3 R0, P1, R6, 0x8, RZ ; ISETP.NE.AND P0, PT, R16, RZ, PT ; IMAD.X R9, RZ, RZ, R7, P1 ; DMUL R4, R2, R4 ; STG.E.64 [R6.64], R4 ; @P0 BRA 0x6d90 ; EXIT ; DSETP.GTU.AND P0, PT, |R10|, +INF , PT ; BSSY B2, 0x7090 ; @P0 BRA 0x7060 ; LOP3.LUT R9, R11, 0x7fffffff, RZ, 0xc0, !PT ; IADD3 R12, R9, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R12, 0x7fefffff, PT ; @P0 LOP3.LUT R13, R11, 0x7ff00000, RZ, 0x3c, !PT ; @P0 MOV R12, RZ ; @P0 BRA 0x7080 ; ISETP.GE.U32.AND P0, PT, R9, 0x1000001, PT ; @!P0 BRA 0x6fc0 ; IADD3 R13, R11, -0x3fe00000, RZ ; IMAD.MOV.U32 R12, RZ, RZ, R10 ; MUFU.RCP64H R19, R13 ; DFMA R22, -R12, R18, 1 ; DFMA R22, R22, R22, R22 ; DFMA R22, R18, R22, R18 ; DFMA R18, -R12, R22, 1 ; DFMA R18, R22, R18, R22 ; DMUL R18, R18, 2.2250738585072013831e-308 ; DFMA R10, -R10, R18, 1 ; DFMA R10, R10, R10, R10 ; DFMA R12, R18, R10, R18 ; BRA 0x7080 ; DMUL R10, R10, 8.11296384146066816958e+31 ; MOV R12, R18 ; MUFU.RCP64H R13, R11 ; DFMA R18, -R10, R12, 1 ; DFMA R18, R18, R18, R18 ; DFMA R18, R12, R18, R12 ; DFMA R12, -R10, R18, 1 ; DFMA R12, R18, R12, R18 ; DMUL R12, R12, 8.11296384146066816958e+31 ; BRA 0x7080 ; LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R12, RZ, RZ, R10 ; BSYNC B2 ; MOV R10, R0 ; IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; MOV R18, R12 ; IMAD.MOV.U32 R19, RZ, RZ, R13 ; RET.REL.NODEC R10 0x0 ; FSETP.GEU.AND P0, PT, |R25|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R32, RZ, RZ, 0x1 ; LOP3.LUT R22, R25, 0x800fffff, RZ, 0xc0, !PT ; BSSY B4, 0x7670 ; FSETP.GEU.AND P4, PT, |R27|, 1.469367938527859385e-39, PT ; LOP3.LUT R23, R22, 0x3ff00000, RZ, 0xfc, !PT ; MOV R22, R24 ; LOP3.LUT R40, R27, 0x7ff00000, RZ, 0xc0, !PT ; MOV R41, 0x1ca00000 ; @!P0 DMUL R22, R24, 8.98846567431157953865e+307 ; LOP3.LUT R43, R25, 0x7ff00000, RZ, 0xc0, !PT ; @!P4 LOP3.LUT R29, R25, 0x7ff00000, RZ, 0xc0, !PT ; MUFU.RCP64H R33, R23 ; ISETP.GE.U32.AND P3, PT, R40.reuse, R43, PT ; @!P4 ISETP.GE.U32.AND P5, PT, R40, R29, PT ; SEL R29, R41.reuse, 0x63400000, !P3 ; @!P4 SEL R35, R41, 0x63400000, !P5 ; LOP3.LUT R29, R29, 0x800fffff, R27, 0xf8, !PT ; @!P4 LOP3.LUT R28, R35, 0x80000000, R27, 0xf8, !PT ; @!P0 LOP3.LUT R43, R23, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R30, R32, -R22, 1 ; DFMA R30, R30, R30, R30 ; DFMA R30, R32, R30, R32 ; @!P4 LOP3.LUT R33, R28, 0x100000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R28, RZ, RZ, R26 ; @!P4 MOV R32, RZ ; @!P4 DFMA R28, R28, 2, -R32 ; DFMA R32, R30, -R22, 1 ; DFMA R30, R30, R32, R30 ; DMUL R32, R30, R28 ; DFMA R34, R32, -R22, R28 ; DFMA R34, R30, R34, R32 ; IMAD.MOV.U32 R32, RZ, RZ, R40 ; @!P4 LOP3.LUT R32, R29, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R30, R32, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R30, 0x7feffffe, PT ; IADD3 R30, R43, -0x1, RZ ; ISETP.GT.U32.OR P0, PT, R30, 0x7feffffe, P0 ; @P0 BRA 0x7510 ; LOP3.LUT R27, R25, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R26, R40.reuse, -R27.reuse, RZ ; ISETP.GE.U32.AND P0, PT, R40, R27, PT ; IMNMX R26, R26, -0x46a00000, !PT ; SEL R41, R41, 0x63400000, !P0 ; IMNMX R26, R26, 0x46a00000, PT ; IMAD.IADD R32, R26, 0x1, -R41 ; MOV R26, RZ ; IADD3 R27, R32, 0x7fe00000, RZ ; DMUL R30, R34, R26 ; FSETP.GTU.AND P0, PT, |R31|, 1.469367938527859385e-39, PT ; @P0 BRA 0x7660 ; DFMA R22, R34, -R22, R28 ; IMAD.MOV.U32 R26, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R23.reuse, RZ, PT ; LOP3.LUT R25, R23, 0x80000000, R25, 0x48, !PT ; LOP3.LUT R27, R25, R27, RZ, 0xfc, !PT ; @!P0 BRA 0x7660 ; IADD3 R23, -R32, RZ, RZ ; IMAD.MOV.U32 R22, RZ, RZ, RZ ; DMUL.RP R26, R34, R26 ; DFMA R22, R30, -R22, R34 ; LOP3.LUT R25, R27, R25, RZ, 0x3c, !PT ; IADD3 R22, -R32, -0x43300000, RZ ; FSETP.NEU.AND P0, PT, |R23|, R22, PT ; FSEL R30, R26, R30, !P0 ; FSEL R31, R25, R31, !P0 ; BRA 0x7660 ; DSETP.NAN.AND P0, PT, R26, R26, PT ; @P0 BRA 0x7640 ; DSETP.NAN.AND P0, PT, R24, R24, PT ; @P0 BRA 0x7610 ; ISETP.NE.AND P0, PT, R32, R43, PT ; IMAD.MOV.U32 R31, RZ, RZ, -0x80000 ; MOV R30, 0x0 ; @!P0 BRA 0x7660 ; ISETP.NE.AND P0, PT, R32, 0x7ff00000, PT ; LOP3.LUT R31, R27, 0x80000000, R25, 0x48, !PT ; ISETP.EQ.OR P0, PT, R43, RZ, !P0 ; @P0 LOP3.LUT R22, R31, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 MOV R30, RZ ; @P0 IMAD.MOV.U32 R30, RZ, RZ, RZ ; @P0 MOV R31, R22 ; BRA 0x7660 ; LOP3.LUT R31, R25, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R30, RZ, RZ, R24 ; BRA 0x7660 ; LOP3.LUT R31, R27, 0x80000, RZ, 0xfc, !PT ; MOV R30, R26 ; BSYNC B4 ; HFMA2.MMA R23, -RZ, RZ, 0, 0 ; IMAD.MOV.U32 R22, RZ, RZ, R0 ; MOV R33, R31 ; IMAD.MOV.U32 R32, RZ, RZ, R30 ; RET.REL.NODEC R22 0x0 ; BRA 0x76c0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; ULDC UR4, c[0x0][0x1e0] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1e4] ; UIADD3 UR4, UR4, -0x1, URZ ; S2R R3, SR_TID.X ; ISETP.NE.AND P0, PT, R2, UR4, PT ; SEL R0, R0, c[0x0][0x1dc], !P0 ; ISETP.GE.AND P0, PT, R3, R0, PT ; @P0 EXIT ; IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD R0, R2, c[0x0][0x1dc], R3 ; IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; LDG.E.64 R2, [R2.64] ; F2I.F64.TRUNC R4, R2 ; ISETP.NE.AND P0, PT, R4, 0x1, PT ; @P0 EXIT ; IMAD.SHL.U32 R10, R0, 0x8, RZ ; SHF.R.S32.HI R3, RZ, 0x1f, R0 ; SHF.L.U64.HI R11, R0, 0x3, R3 ; IADD3 R6, P0, R10, c[0x0][0x1c8], RZ ; IADD3.X R7, R11, c[0x0][0x1cc], RZ, P0, !PT ; LDG.E.64 R6, [R6.64] ; IADD3 R4, P0, R10.reuse, c[0x0][0x168], RZ ; IADD3 R16, P1, R10.reuse, c[0x0][0x1c0], RZ ; IADD3.X R5, R11.reuse, c[0x0][0x16c], RZ, P0, !PT ; IADD3 R8, P0, R10.reuse, c[0x0][0x1b0], RZ ; IADD3.X R17, R11.reuse, c[0x0][0x1c4], RZ, P1, !PT ; IADD3.X R9, R11, c[0x0][0x1b4], RZ, P0, !PT ; LDG.E.64 R4, [R4.64] ; LDG.E.64 R16, [R16.64] ; LDG.E.64 R8, [R8.64] ; IADD3 R20, P1, R10.reuse, c[0x0][0x180], RZ ; BSSY B0, 0x3560 ; IADD3 R22, P2, R10, c[0x0][0x188], RZ ; IADD3 R14, P3, R10.reuse, c[0x0][0x1a8], RZ ; IADD3 R26, P4, R10, c[0x0][0x1d0], RZ ; IADD3.X R21, R11.reuse, c[0x0][0x184], RZ, P1, !PT ; IADD3.X R23, R11.reuse, c[0x0][0x18c], RZ, P2, !PT ; IADD3.X R15, R11.reuse, c[0x0][0x1ac], RZ, P3, !PT ; IADD3.X R27, R11, c[0x0][0x1d4], RZ, P4, !PT ; F2I.F64.TRUNC R0, R6 ; ISETP.GE.AND P0, PT, R0, 0x1, PT ; F2I.F64.TRUNC R2, R4 ; F2I.F64.TRUNC R3, R8 ; DSETP.GTU.OR P0, PT, R16, c[0x2][0x0], !P0 ; @P0 BRA 0x3550 ; LDG.E.64 R14, [R14.64] ; LDG.E.64 R20, [R20.64] ; LDG.E.64 R22, [R22.64] ; LDG.E.64 R8, [R26.64] ; IADD3 R12, P0, R10, c[0x0][0x1b8], RZ ; IADD3 R10, P1, R10, c[0x0][0x1a0], RZ ; IADD3.X R13, R11.reuse, c[0x0][0x1bc], RZ, P0, !PT ; IADD3.X R11, R11, c[0x0][0x1a4], RZ, P1, !PT ; LDG.E.64 R12, [R12.64] ; LDG.E.64 R10, [R10.64] ; BSSY B1, 0x4e0 ; F2I.F64.TRUNC R4, R14 ; F2I.F64.TRUNC R5, R20 ; I2F.F64 R18, R4 ; MUFU.RCP64H R25, R19 ; IADD3 R24, R19, 0x300402, RZ ; FSETP.GEU.AND P0, PT, |R24|, 5.8789094863358348022e-39, PT ; DFMA R6, -R18, R24, 1 ; DFMA R26, R6, R6, R6 ; F2I.F64.TRUNC R6, R22 ; DFMA R26, R24, R26, R24 ; F2I.F64.TRUNC R7, R8 ; DFMA R28, -R18, R26, 1 ; DFMA R14, R26, R28, R26 ; @P0 BRA 0x4d0 ; LOP3.LUT R8, R19, 0x7fffffff, RZ, 0xc0, !PT ; IADD3 R20, R8, -0x100000, RZ ; MOV R8, 0x4d0 ; CALL.REL.NOINC 0x38e0 ; BSYNC B1 ; DADD R18, -R12.reuse, 1 ; LOP3.LUT R9, R4.reuse, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R37, RZ, RZ, RZ ; IADD3 R8, R4.reuse, -0x1, RZ ; DMUL R12, R12, R10 ; IMAD.IADD R36, R4, 0x1, -R9 ; DMUL R10, R10, R18 ; ISETP.GE.AND P0, PT, R3, 0x1, PT ; BSSY B1, 0x3510 ; CS2R R18, SRZ ; @!P0 BRA 0x3500 ; IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x1d8] ; LOP3.LUT R18, R18, 0x2, RZ, 0xfc, !PT ; ISETP.NE.AND P0, PT, R18, 0x3, PT ; CS2R R18, SRZ ; @!P0 BRA 0x1d80 ; IMAD.MOV.U32 R39, RZ, RZ, RZ ; IMAD.IADD R21, R2, 0x1, R39 ; IMAD.MOV.U32 R38, RZ, RZ, 0x8 ; IMAD.WIDE R20, R21, R38, c[0x0][0x160] ; LDG.E.64 R20, [R20.64] ; BSSY B2, 0x1540 ; CS2R R32, SRZ ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; @P0 BRA 0x1120 ; ISETP.GE.AND P0, PT, R4, 0x1, PT ; @!P0 BRA 0x1530 ; ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; BSSY B3, 0xfe0 ; IMAD R41, R4, R39, R5 ; CS2R R32, SRZ ; IMAD.MOV.U32 R42, RZ, RZ, RZ ; @!P0 BRA 0xfd0 ; ISETP.GT.AND P0, PT, R36, RZ, PT ; BSSY B4, 0xe50 ; IMAD.MOV.U32 R42, RZ, RZ, RZ ; CS2R R32, SRZ ; IMAD.MOV.U32 R44, RZ, RZ, c[0x0][0x190] ; IMAD.MOV.U32 R43, RZ, RZ, c[0x0][0x194] ; IMAD.MOV.U32 R40, RZ, RZ, R36 ; IMAD.WIDE R22, R41, R38, c[0x0][0x178] ; @!P0 BRA 0xe40 ; ISETP.GT.AND P1, PT, R40, 0xc, PT ; BSSY B5, 0xba0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0xb90 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.MOV.U32 R45, RZ, RZ, R43 ; LDG.E.64 R30, [R22.64] ; IMAD.WIDE R24, R6, 0x8, R44 ; LDG.E.64 R26, [R22.64+0x8] ; LDG.E.64 R34, [R24.64] ; LDG.E.64 R28, [R24.64+0x8] ; DFMA R32, R34, R30, R32 ; LDG.E.64 R30, [R24.64+0x10] ; DFMA R32, R28, R26, R32 ; LDG.E.64 R34, [R22.64+0x18] ; LDG.E.64 R28, [R22.64+0x10] ; LDG.E.64 R26, [R24.64+0x18] ; DFMA R28, R30, R28, R32 ; LDG.E.64 R30, [R24.64+0x20] ; DFMA R34, R26, R34, R28 ; LDG.E.64 R32, [R22.64+0x28] ; LDG.E.64 R28, [R22.64+0x20] ; LDG.E.64 R26, [R24.64+0x28] ; DFMA R28, R30, R28, R34 ; LDG.E.64 R30, [R24.64+0x30] ; DFMA R32, R26, R32, R28 ; LDG.E.64 R34, [R22.64+0x38] ; LDG.E.64 R28, [R22.64+0x30] ; LDG.E.64 R26, [R24.64+0x38] ; DFMA R28, R30, R28, R32 ; LDG.E.64 R30, [R24.64+0x40] ; DFMA R34, R26, R34, R28 ; LDG.E.64 R32, [R22.64+0x48] ; LDG.E.64 R28, [R22.64+0x40] ; LDG.E.64 R26, [R24.64+0x48] ; DFMA R28, R30, R28, R34 ; LDG.E.64 R30, [R24.64+0x50] ; DFMA R32, R26, R32, R28 ; LDG.E.64 R34, [R22.64+0x58] ; LDG.E.64 R28, [R22.64+0x50] ; LDG.E.64 R26, [R24.64+0x58] ; DFMA R28, R30, R28, R32 ; LDG.E.64 R30, [R22.64+0x60] ; LDG.E.64 R32, [R24.64+0x60] ; DFMA R34, R26, R34, R28 ; LDG.E.64 R26, [R22.64+0x68] ; LDG.E.64 R28, [R24.64+0x68] ; DFMA R30, R32, R30, R34 ; LDG.E.64 R34, [R24.64+0x78] ; LDG.E.64 R32, [R22.64+0x78] ; DFMA R30, R28, R26, R30 ; LDG.E.64 R26, [R22.64+0x70] ; LDG.E.64 R28, [R24.64+0x70] ; IADD3 R40, R40, -0x10, RZ ; ISETP.GT.AND P1, PT, R40, 0xc, PT ; IADD3 R44, P2, R44, 0x80, RZ ; IADD3 R42, R42, 0x10, RZ ; IMAD.X R43, RZ, RZ, R43, P2 ; DFMA R26, R28, R26, R30 ; IADD3 R28, P3, R22, 0x80, RZ ; IMAD.X R29, RZ, RZ, R23, P3 ; DFMA R32, R34, R32, R26 ; IMAD.MOV.U32 R22, RZ, RZ, R28 ; IMAD.MOV.U32 R23, RZ, RZ, R29 ; @P1 BRA 0x7d0 ; BSYNC B5 ; ISETP.GT.AND P1, PT, R40, 0x4, PT ; BSSY B5, 0xe10 ; @!P1 BRA 0xe00 ; IMAD.MOV.U32 R45, RZ, RZ, R43 ; LDG.E.64 R28, [R22.64] ; IMAD.WIDE R24, R6, 0x8, R44 ; LDG.E.64 R34, [R22.64+0x8] ; LDG.E.64 R30, [R24.64] ; LDG.E.64 R26, [R24.64+0x8] ; DFMA R28, R30, R28, R32 ; LDG.E.64 R30, [R22.64+0x10] ; LDG.E.64 R32, [R24.64+0x10] ; DFMA R34, R26, R34, R28 ; LDG.E.64 R26, [R22.64+0x18] ; LDG.E.64 R28, [R24.64+0x18] ; DFMA R30, R32, R30, R34 ; LDG.E.64 R32, [R22.64+0x28] ; LDG.E.64 R34, [R24.64+0x28] ; DFMA R26, R28, R26, R30 ; LDG.E.64 R28, [R22.64+0x20] ; LDG.E.64 R30, [R24.64+0x20] ; DFMA R26, R30, R28, R26 ; LDG.E.64 R28, [R24.64+0x30] ; DFMA R32, R34, R32, R26 ; LDG.E.64 R30, [R22.64+0x38] ; LDG.E.64 R26, [R22.64+0x30] ; LDG.E.64 R34, [R24.64+0x38] ; IADD3 R44, P1, R44, 0x40, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R42, R42, 0x8, RZ ; IMAD.X R43, RZ, RZ, R43, P1 ; IADD3 R40, R40, -0x8, RZ ; DFMA R32, R28, R26, R32 ; IADD3 R26, P2, R22, 0x40, RZ ; IMAD.X R27, RZ, RZ, R23, P2 ; DFMA R32, R34, R30, R32 ; IMAD.MOV.U32 R22, RZ, RZ, R26 ; IMAD.MOV.U32 R23, RZ, RZ, R27 ; BSYNC B5 ; ISETP.NE.OR P0, PT, R40, RZ, P0 ; @!P0 BREAK B4 ; @!P0 BRA 0xfd0 ; BSYNC B4 ; IMAD.MOV.U32 R45, RZ, RZ, R43 ; LDG.E.64 R30, [R22.64] ; IMAD.WIDE R24, R6, 0x8, R44 ; LDG.E.64 R26, [R22.64+0x8] ; LDG.E.64 R34, [R24.64] ; LDG.E.64 R28, [R24.64+0x8] ; DFMA R30, R34, R30, R32 ; LDG.E.64 R34, [R24.64+0x18] ; DFMA R30, R28, R26, R30 ; LDG.E.64 R32, [R22.64+0x18] ; LDG.E.64 R26, [R22.64+0x10] ; LDG.E.64 R28, [R24.64+0x10] ; IADD3 R40, R40, -0x4, RZ ; ISETP.NE.AND P0, PT, R40, RZ, PT ; IADD3 R44, P1, R44, 0x20, RZ ; IADD3 R42, R42, 0x4, RZ ; IMAD.X R43, RZ, RZ, R43, P1 ; DFMA R26, R28, R26, R30 ; IADD3 R28, P2, R22, 0x20, RZ ; IMAD.X R29, RZ, RZ, R23, P2 ; DFMA R32, R34, R32, R26 ; IMAD.MOV.U32 R22, RZ, RZ, R28 ; IMAD.MOV.U32 R23, RZ, RZ, R29 ; @P0 BRA 0xe50 ; BSYNC B3 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x1530 ; IMAD.IADD R23, R6, 0x1, R42.reuse ; IMAD.IADD R25, R41, 0x1, R42 ; IMAD.WIDE R22, R23, R38, c[0x0][0x190] ; IMAD.WIDE R24, R25, R38, c[0x0][0x178] ; LDG.E.64 R28, [R22.64] ; LDG.E.64 R26, [R24.64] ; ISETP.NE.AND P0, PT, R9, 0x1, PT ; DFMA R32, R28, R26, R32 ; @!P0 BRA 0x1530 ; LDG.E.64 R28, [R22.64+0x8] ; LDG.E.64 R26, [R24.64+0x8] ; ISETP.NE.AND P0, PT, R9, 0x2, PT ; DFMA R32, R28, R26, R32 ; @!P0 BRA 0x1530 ; LDG.E.64 R22, [R22.64+0x10] ; LDG.E.64 R24, [R24.64+0x10] ; DFMA R32, R22, R24, R32 ; BRA 0x1530 ; ISETP.GE.AND P0, PT, R4, 0x1, PT ; @!P0 BRA 0x1530 ; ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; BSSY B3, 0x13b0 ; ISETP.NE.AND P1, PT, R9, RZ, PT ; IMAD R40, R4, R39, R5 ; CS2R R32, SRZ ; IMAD.MOV.U32 R41, RZ, RZ, RZ ; @!P0 BRA 0x13a0 ; IMAD.MOV.U32 R41, RZ, RZ, RZ ; CS2R R32, SRZ ; IMAD.MOV.U32 R42, RZ, RZ, R36 ; IMAD.IADD R29, R40, 0x1, R41.reuse ; IMAD.IADD R27, R6, 0x1, R41 ; IMAD.WIDE R28, R29, R38, c[0x0][0x178] ; IMAD.WIDE R26, R27, R38, c[0x0][0x190] ; LDG.E.64 R34, [R28.64] ; LDG.E.64 R44, [R26.64] ; LDG.E.64 R24, [R26.64+0x8] ; LDG.E.64 R30, [R26.64+0x10] ; DFMA R44, R20, R34, R44 ; STG.E.64 [R26.64], R44 ; LDG.E.64 R22, [R28.64+0x8] ; DFMA R34, R34, R44, R32 ; DFMA R24, R20, R22, R24 ; STG.E.64 [R26.64+0x8], R24 ; LDG.E.64 R32, [R28.64+0x10] ; DFMA R34, R22, R24, R34 ; LDG.E.64 R22, [R26.64+0x18] ; DFMA R30, R20, R32, R30 ; STG.E.64 [R26.64+0x10], R30 ; LDG.E.64 R44, [R28.64+0x18] ; IADD3 R42, R42, -0x4, RZ ; ISETP.NE.AND P0, PT, R42, RZ, PT ; DFMA R32, R32, R30, R34 ; IADD3 R41, R41, 0x4, RZ ; DFMA R22, R20, R44, R22 ; STG.E.64 [R26.64+0x18], R22 ; DFMA R32, R44, R22, R32 ; @P0 BRA 0x11e0 ; BSYNC B3 ; @!P1 BRA 0x1530 ; IMAD.IADD R23, R40, 0x1, R41.reuse ; IMAD.IADD R25, R6, 0x1, R41 ; IMAD.WIDE R22, R23, R38, c[0x0][0x178] ; IMAD.WIDE R24, R25, R38, c[0x0][0x190] ; LDG.E.64 R28, [R22.64] ; LDG.E.64 R26, [R24.64] ; ISETP.NE.AND P0, PT, R9, 0x1, PT ; DFMA R26, R20, R28, R26 ; DFMA R32, R28, R26, R32 ; STG.E.64 [R24.64], R26 ; @!P0 BRA 0x1530 ; LDG.E.64 R28, [R22.64+0x8] ; LDG.E.64 R26, [R24.64+0x8] ; ISETP.NE.AND P0, PT, R9, 0x2, PT ; DFMA R26, R20, R28, R26 ; DFMA R32, R28, R26, R32 ; STG.E.64 [R24.64+0x8], R26 ; @!P0 BRA 0x1530 ; LDG.E.64 R22, [R22.64+0x10] ; LDG.E.64 R26, [R24.64+0x10] ; DFMA R26, R20, R22, R26 ; DFMA R32, R22, R26, R32 ; STG.E.64 [R24.64+0x10], R26 ; BSYNC B2 ; DMUL R32, R32, R14 ; BSSY B2, 0x1610 ; DSETP.GEU.AND P0, PT, R12, |R32|, PT ; DSETP.GT.AND P1, PT, R32, RZ, PT ; @!P0 BRA P1, 0x15f0 ; DSETP.GEU.AND P0, PT, R12, |R32|, PT ; CS2R R22, SRZ ; DSETP.GEU.OR P0, PT, R32, RZ, P0 ; @P0 BRA 0x1600 ; DADD R22, R12, R32 ; BRA 0x1600 ; DADD R22, -R12, R32 ; BSYNC B2 ; IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x1d8] ; ISETP.EQ.AND P2, PT, R39, RZ, PT ; BSSY B2, 0x1850 ; ISETP.NE.AND P0, PT, R24, 0x2, PT ; ISETP.NE.AND P1, PT, R24, 0x4, P0 ; ISETP.NE.AND P0, PT, R7, 0x1, PT ; CS2R R24, SRZ ; @!P1 IMAD.MOV.U32 R24, RZ, RZ, R14 ; @!P1 IMAD.MOV.U32 R25, RZ, RZ, R15 ; @!P0 BRA P2, 0x1840 ; DADD R24, R10, R24 ; IMAD.MOV.U32 R26, RZ, RZ, 0x1 ; FSETP.GEU.AND P2, PT, |R23|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x1840 ; MUFU.RCP64H R27, R25 ; DFMA R28, -R24, R26, 1 ; DFMA R28, R28, R28, R28 ; DFMA R28, R26, R28, R26 ; DFMA R30, -R24, R28, 1 ; DFMA R30, R28, R30, R28 ; DMUL R26, R30, R22 ; DFMA R28, -R24, R26, R22 ; DFMA R32, R30, R28, R26 ; FFMA R26, RZ, R25, R33 ; FSETP.GT.AND P1, PT, |R26|, 1.469367938527859385e-39, PT ; @P1 BRA P2, 0x1830 ; IMAD.MOV.U32 R26, RZ, RZ, R22 ; MOV R38, 0x1810 ; IMAD.MOV.U32 R27, RZ, RZ, R23 ; IMAD.MOV.U32 R22, RZ, RZ, R24 ; IMAD.MOV.U32 R23, RZ, RZ, R25 ; CALL.REL.NOINC 0x3b90 ; IMAD.MOV.U32 R32, RZ, RZ, R24 ; IMAD.MOV.U32 R33, RZ, RZ, R25 ; BSYNC B3 ; BSYNC B2 ; IMAD.IADD R23, R2, 0x1, R39 ; ISETP.GE.AND P1, PT, R4, 0x1, PT ; IMAD.MOV.U32 R34, RZ, RZ, 0x8 ; BSSY B2, 0x1c40 ; IMAD.WIDE R22, R23, R34, c[0x0][0x160] ; STG.E.64 [R22.64], R32 ; DSETP.EQ.OR P1, PT, R32, RZ, !P1 ; @P1 BRA 0x1c30 ; ISETP.GE.U32.AND P1, PT, R8, 0x3, PT ; BSSY B3, 0x1ae0 ; ISETP.NE.AND P2, PT, R9, RZ, PT ; IMAD R35, R4, R39, R5 ; IMAD.MOV.U32 R38, RZ, RZ, RZ ; @!P1 BRA 0x1ad0 ; IMAD.MOV.U32 R38, RZ, RZ, RZ ; IMAD.MOV.U32 R40, RZ, RZ, R36 ; IMAD.IADD R23, R6, 0x1, R38.reuse ; IMAD.IADD R25, R35, 0x1, R38 ; IMAD.WIDE R22, R23, R34, c[0x0][0x190] ; IMAD.WIDE R24, R25, R34, c[0x0][0x178] ; LDG.E.64 R42, [R22.64] ; LDG.E.64 R26, [R24.64] ; LDG.E.64 R30, [R22.64+0x8] ; DFMA R42, R26, -R32, R42 ; STG.E.64 [R22.64], R42 ; LDG.E.64 R26, [R24.64+0x8] ; DFMA R30, R26, -R32.reuse, R30 ; LDG.E.64 R26, [R22.64+0x10] ; STG.E.64 [R22.64+0x8], R30 ; LDG.E.64 R28, [R24.64+0x10] ; DFMA R26, R28, -R32, R26 ; LDG.E.64 R28, [R22.64+0x18] ; STG.E.64 [R22.64+0x10], R26 ; LDG.E.64 R44, [R24.64+0x18] ; IADD3 R40, R40, -0x4, RZ ; ISETP.NE.AND P1, PT, R40, RZ, PT ; IADD3 R38, R38, 0x4, RZ ; DFMA R28, R44, -R32, R28 ; STG.E.64 [R22.64+0x18], R28 ; @P1 BRA 0x1950 ; BSYNC B3 ; @!P2 BRA 0x1c30 ; IMAD.IADD R23, R35, 0x1, R38.reuse ; IMAD.IADD R35, R6, 0x1, R38 ; IMAD.WIDE R22, R23, R34, c[0x0][0x178] ; IMAD.WIDE R34, R35, R34, c[0x0][0x190] ; LDG.E.64 R26, [R22.64] ; LDG.E.64 R24, [R34.64] ; ISETP.NE.AND P1, PT, R9, 0x1, PT ; DFMA R24, R26, -R32, R24 ; STG.E.64 [R34.64], R24 ; @!P1 BRA 0x1c30 ; LDG.E.64 R26, [R22.64+0x8] ; LDG.E.64 R24, [R34.64+0x8] ; ISETP.NE.AND P1, PT, R9, 0x2, PT ; DFMA R24, R26, -R32, R24 ; STG.E.64 [R34.64+0x8], R24 ; @!P1 BRA 0x1c30 ; LDG.E.64 R22, [R22.64+0x10] ; LDG.E.64 R24, [R34.64+0x10] ; DFMA R24, R22, -R32, R24 ; STG.E.64 [R34.64+0x10], R24 ; BSYNC B2 ; IMAD.MOV.U32 R22, RZ, RZ, c[0x0][0x1d8] ; DADD R20, R20, -R32 ; ISETP.NE.AND P1, PT, R22.reuse, 0x2, PT ; DMUL R20, R20, R20 ; ISETP.NE.AND P1, PT, R22, 0x4, P1 ; @!P1 DMUL R22, R20, R14 ; @!P1 ISETP.NE.AND P0, PT, R39.reuse, RZ, !P0 ; IADD3 R39, R39, 0x1, RZ ; @!P1 ISETP.EQ.OR P0, PT, R7, RZ, P0 ; @!P1 FSEL R22, R22, R20, P0 ; @!P1 FSEL R23, R23, R21, P0 ; @!P1 IMAD.MOV.U32 R20, RZ, RZ, R22 ; @!P1 IMAD.MOV.U32 R21, RZ, RZ, R23 ; ISETP.GE.AND P1, PT, R39, R3, PT ; DSETP.GT.AND P0, PT, R20, R18, PT ; FSEL R18, R20, R18, P0 ; FSEL R19, R21, R19, P0 ; @P1 CALL.REL.NOINC 0x1d70 ; BRA 0x5f0 ; BRA 0x3500 ; IMAD.MOV.U32 R39, RZ, RZ, RZ ; IMAD.IADD R21, R2, 0x1, R39 ; IMAD.MOV.U32 R38, RZ, RZ, 0x8 ; IMAD.WIDE R20, R21, R38, c[0x0][0x160] ; LDG.E.64 R20, [R20.64] ; BSSY B2, 0x2d30 ; CS2R R30, SRZ ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; @P0 BRA 0x2910 ; ISETP.GE.AND P0, PT, R4, 0x1, PT ; @!P0 BRA 0x2d20 ; ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; BSSY B3, 0x27d0 ; IMAD R43, R4, R39, R5 ; CS2R R30, SRZ ; IMAD.MOV.U32 R44, RZ, RZ, RZ ; @!P0 BRA 0x27c0 ; ISETP.GT.AND P0, PT, R36, RZ, PT ; BSSY B4, 0x2680 ; IMAD.MOV.U32 R44, RZ, RZ, RZ ; CS2R R30, SRZ ; IMAD.MOV.U32 R42, RZ, RZ, R36 ; @!P0 BRA 0x2670 ; ISETP.GT.AND P1, PT, R42, 0xc, PT ; BSSY B5, 0x23c0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x23b0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.IADD R25, R43, 0x1, R44.reuse ; IMAD.IADD R23, R6, 0x1, R44 ; IMAD.WIDE R24, R25, R38, c[0x0][0x178] ; IMAD.WIDE R22, R23, R38, c[0x0][0x190] ; LDG.E.64 R26, [R24.64] ; LDG.E.64 R28, [R22.64] ; LDG.E.64 R34, [R22.64+0x8] ; LDG.E.64 R32, [R24.64+0x8] ; DFMA R30, R28, R26, R30 ; LDG.E.64 R28, [R22.64+0x10] ; LDG.E.64 R26, [R24.64+0x10] ; IADD3 R45, R44, 0x4, RZ ; DFMA R30, R34, R32, R30 ; LDG.E.64 R32, [R22.64+0x18] ; IMAD.IADD R41, R43, 0x1, R45 ; LDG.E.64 R34, [R24.64+0x18] ; IMAD.IADD R45, R6, 0x1, R45 ; IMAD.WIDE R22, R41, R38, c[0x0][0x178] ; LDG.E.64 R24, [R22.64+0x10] ; DFMA R26, R28, R26, R30 ; IMAD.WIDE R28, R45, R38, c[0x0][0x190] ; LDG.E.64 R30, [R22.64] ; LDG.E.64 R40, [R28.64] ; DFMA R34, R32, R34, R26 ; LDG.E.64 R32, [R28.64+0x8] ; LDG.E.64 R26, [R22.64+0x8] ; DFMA R40, R40, R30, R34 ; LDG.E.64 R30, [R28.64+0x10] ; LDG.E.64 R34, [R22.64+0x18] ; DFMA R26, R32, R26, R40 ; IADD3 R41, R44, 0x8, RZ ; LDG.E.64 R32, [R28.64+0x18] ; IMAD.IADD R45, R43, 0x1, R41 ; IMAD.IADD R41, R6, 0x1, R41 ; IMAD.WIDE R40, R41, R38, c[0x0][0x190] ; LDG.E.64 R28, [R40.64] ; DFMA R24, R30, R24, R26 ; IMAD.WIDE R26, R45, R38, c[0x0][0x178] ; LDG.E.64 R30, [R26.64] ; DFMA R34, R32, R34, R24 ; LDG.E.64 R32, [R40.64+0x8] ; LDG.E.64 R24, [R26.64+0x8] ; DFMA R34, R28, R30, R34 ; LDG.E.64 R28, [R40.64+0x10] ; LDG.E.64 R30, [R26.64+0x10] ; IADD3 R23, R44, 0xc, RZ ; DFMA R24, R32, R24, R34 ; IMAD.IADD R33, R6, 0x1, R23.reuse ; IMAD.IADD R23, R43, 0x1, R23 ; LDG.E.64 R26, [R26.64+0x18] ; DFMA R30, R28, R30, R24 ; LDG.E.64 R28, [R40.64+0x18] ; IMAD.WIDE R24, R33, R38, c[0x0][0x190] ; LDG.E.64 R32, [R24.64+0x8] ; IMAD.WIDE R40, R23, R38, c[0x0][0x178] ; LDG.E.64 R22, [R24.64] ; LDG.E.64 R34, [R40.64] ; DFMA R28, R28, R26, R30 ; LDG.E.64 R30, [R40.64+0x8] ; LDG.E.64 R26, [R40.64+0x10] ; DFMA R34, R22, R34, R28 ; LDG.E.64 R28, [R24.64+0x10] ; LDG.E.64 R22, [R40.64+0x18] ; LDG.E.64 R24, [R24.64+0x18] ; IADD3 R42, R42, -0x10, RZ ; ISETP.GT.AND P1, PT, R42, 0xc, PT ; IADD3 R44, R44, 0x10, RZ ; DFMA R30, R32, R30, R34 ; DFMA R30, R28, R26, R30 ; DFMA R30, R24, R22, R30 ; @P1 BRA 0x1f40 ; BSYNC B5 ; ISETP.GT.AND P1, PT, R42, 0x4, PT ; BSSY B5, 0x2640 ; @!P1 BRA 0x2630 ; IMAD.IADD R33, R43, 0x1, R44.reuse ; IMAD.IADD R29, R6, 0x1, R44 ; IMAD.WIDE R32, R33, R38, c[0x0][0x178] ; IMAD.WIDE R28, R29, R38, c[0x0][0x190] ; LDG.E.64 R34, [R32.64] ; LDG.E.64 R22, [R28.64] ; LDG.E.64 R26, [R28.64+0x8] ; LDG.E.64 R24, [R32.64+0x8] ; DFMA R34, R22, R34, R30 ; LDG.E.64 R22, [R28.64+0x10] ; LDG.E.64 R30, [R32.64+0x10] ; IADD3 R41, R44, 0x4, RZ ; DFMA R24, R26, R24, R34 ; IMAD.IADD R27, R6, 0x1, R41.reuse ; LDG.E.64 R28, [R28.64+0x18] ; IMAD.IADD R41, R43, 0x1, R41 ; IMAD.WIDE R26, R27, R38, c[0x0][0x190] ; IMAD.WIDE R40, R41, R38, c[0x0][0x178] ; LDG.E.64 R34, [R40.64] ; DFMA R30, R22, R30, R24 ; LDG.E.64 R24, [R32.64+0x18] ; LDG.E.64 R22, [R26.64] ; LDG.E.64 R32, [R26.64+0x8] ; DFMA R24, R28, R24, R30 ; LDG.E.64 R30, [R40.64+0x8] ; DFMA R34, R22, R34, R24 ; LDG.E.64 R28, [R40.64+0x18] ; LDG.E.64 R22, [R26.64+0x10] ; LDG.E.64 R24, [R40.64+0x10] ; LDG.E.64 R26, [R26.64+0x18] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R42, R42, -0x8, RZ ; IADD3 R44, R44, 0x8, RZ ; DFMA R30, R32, R30, R34 ; DFMA R30, R22, R24, R30 ; DFMA R30, R26, R28, R30 ; BSYNC B5 ; ISETP.NE.OR P0, PT, R42, RZ, P0 ; @!P0 BREAK B4 ; @!P0 BRA 0x27c0 ; BSYNC B4 ; IMAD.IADD R25, R43, 0x1, R44.reuse ; IMAD.IADD R23, R6, 0x1, R44 ; IMAD.WIDE R24, R25, R38, c[0x0][0x178] ; IMAD.WIDE R22, R23, R38, c[0x0][0x190] ; LDG.E.64 R34, [R24.64] ; LDG.E.64 R26, [R22.64] ; LDG.E.64 R32, [R22.64+0x8] ; LDG.E.64 R28, [R22.64+0x10] ; LDG.E.64 R40, [R22.64+0x18] ; DFMA R34, R26, R34, R30 ; LDG.E.64 R30, [R24.64+0x8] ; LDG.E.64 R26, [R24.64+0x10] ; LDG.E.64 R24, [R24.64+0x18] ; IADD3 R42, R42, -0x4, RZ ; ISETP.NE.AND P0, PT, R42, RZ, PT ; IADD3 R44, R44, 0x4, RZ ; DFMA R30, R32, R30, R34 ; DFMA R30, R28, R26, R30 ; DFMA R30, R40, R24, R30 ; @P0 BRA 0x2680 ; BSYNC B3 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x2d20 ; IMAD.IADD R23, R6, 0x1, R44.reuse ; IMAD.IADD R25, R43, 0x1, R44 ; IMAD.WIDE R22, R23, R38, c[0x0][0x190] ; IMAD.WIDE R24, R25, R38, c[0x0][0x178] ; LDG.E.64 R28, [R22.64] ; LDG.E.64 R26, [R24.64] ; ISETP.NE.AND P0, PT, R9, 0x1, PT ; DFMA R30, R28, R26, R30 ; @!P0 BRA 0x2d20 ; LDG.E.64 R28, [R22.64+0x8] ; LDG.E.64 R26, [R24.64+0x8] ; ISETP.NE.AND P0, PT, R9, 0x2, PT ; DFMA R30, R28, R26, R30 ; @!P0 BRA 0x2d20 ; LDG.E.64 R22, [R22.64+0x10] ; LDG.E.64 R24, [R24.64+0x10] ; DFMA R30, R22, R24, R30 ; BRA 0x2d20 ; ISETP.GE.AND P0, PT, R4, 0x1, PT ; @!P0 BRA 0x2d20 ; ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; BSSY B3, 0x2ba0 ; ISETP.NE.AND P1, PT, R9, RZ, PT ; IMAD R40, R4, R39, R5 ; CS2R R30, SRZ ; IMAD.MOV.U32 R41, RZ, RZ, RZ ; @!P0 BRA 0x2b90 ; IMAD.MOV.U32 R41, RZ, RZ, RZ ; CS2R R30, SRZ ; IMAD.MOV.U32 R42, RZ, RZ, R36 ; IMAD.IADD R29, R40, 0x1, R41.reuse ; IMAD.IADD R27, R6, 0x1, R41 ; IMAD.WIDE R28, R29, R38, c[0x0][0x178] ; IMAD.WIDE R26, R27, R38, c[0x0][0x190] ; LDG.E.64 R34, [R28.64] ; LDG.E.64 R44, [R26.64] ; LDG.E.64 R24, [R26.64+0x8] ; LDG.E.64 R32, [R26.64+0x10] ; DFMA R44, R20, R34, R44 ; STG.E.64 [R26.64], R44 ; LDG.E.64 R22, [R28.64+0x8] ; DFMA R34, R34, R44, R30 ; DFMA R24, R20, R22, R24 ; STG.E.64 [R26.64+0x8], R24 ; LDG.E.64 R30, [R28.64+0x10] ; DFMA R34, R22, R24, R34 ; LDG.E.64 R22, [R26.64+0x18] ; DFMA R32, R20, R30, R32 ; STG.E.64 [R26.64+0x10], R32 ; LDG.E.64 R44, [R28.64+0x18] ; IADD3 R42, R42, -0x4, RZ ; ISETP.NE.AND P0, PT, R42, RZ, PT ; DFMA R30, R30, R32, R34 ; IADD3 R41, R41, 0x4, RZ ; DFMA R22, R20, R44, R22 ; STG.E.64 [R26.64+0x18], R22 ; DFMA R30, R44, R22, R30 ; @P0 BRA 0x29d0 ; BSYNC B3 ; @!P1 BRA 0x2d20 ; IMAD.IADD R23, R40, 0x1, R41.reuse ; IMAD.IADD R25, R6, 0x1, R41 ; IMAD.WIDE R22, R23, R38, c[0x0][0x178] ; IMAD.WIDE R24, R25, R38, c[0x0][0x190] ; LDG.E.64 R28, [R22.64] ; LDG.E.64 R26, [R24.64] ; ISETP.NE.AND P0, PT, R9, 0x1, PT ; DFMA R26, R20, R28, R26 ; DFMA R30, R28, R26, R30 ; STG.E.64 [R24.64], R26 ; @!P0 BRA 0x2d20 ; LDG.E.64 R28, [R22.64+0x8] ; LDG.E.64 R26, [R24.64+0x8] ; ISETP.NE.AND P0, PT, R9, 0x2, PT ; DFMA R26, R20, R28, R26 ; DFMA R30, R28, R26, R30 ; STG.E.64 [R24.64+0x8], R26 ; @!P0 BRA 0x2d20 ; LDG.E.64 R22, [R22.64+0x10] ; LDG.E.64 R26, [R24.64+0x10] ; DFMA R26, R20, R22, R26 ; DFMA R30, R22, R26, R30 ; STG.E.64 [R24.64+0x10], R26 ; BSYNC B2 ; DMUL R30, R30, R14 ; BSSY B2, 0x2e00 ; DSETP.GEU.AND P0, PT, R12, |R30|, PT ; DSETP.GT.AND P1, PT, R30, RZ, PT ; @!P0 BRA P1, 0x2de0 ; DSETP.GEU.AND P0, PT, R12, |R30|, PT ; CS2R R22, SRZ ; DSETP.GEU.OR P0, PT, R30, RZ, P0 ; @P0 BRA 0x2df0 ; DADD R22, R12, R30 ; BRA 0x2df0 ; DADD R22, -R12, R30 ; BSYNC B2 ; ISETP.NE.AND P0, PT, R7, 0x1, PT ; BSSY B2, 0x2fe0 ; ISETP.EQ.AND P1, PT, R39, RZ, PT ; @!P0 BRA P1, 0x2fd0 ; DADD R30, R10, 1 ; IMAD.MOV.U32 R24, RZ, RZ, 0x1 ; FSETP.GEU.AND P2, PT, |R23|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x2fb0 ; MUFU.RCP64H R25, R31 ; DFMA R26, -R30, R24, 1 ; DFMA R26, R26, R26, R26 ; DFMA R24, R24, R26, R24 ; DFMA R26, -R30, R24, 1 ; DFMA R24, R24, R26, R24 ; DMUL R26, R24, R22 ; DFMA R28, -R30, R26, R22 ; DFMA R24, R24, R28, R26 ; FFMA R26, RZ, R31, R25 ; FSETP.GT.AND P1, PT, |R26|, 1.469367938527859385e-39, PT ; @P1 BRA P2, 0x2fa0 ; IMAD.MOV.U32 R26, RZ, RZ, R22 ; MOV R38, 0x2fa0 ; IMAD.MOV.U32 R27, RZ, RZ, R23 ; IMAD.MOV.U32 R22, RZ, RZ, R30 ; IMAD.MOV.U32 R23, RZ, RZ, R31 ; CALL.REL.NOINC 0x3b90 ; BSYNC B3 ; IMAD.MOV.U32 R30, RZ, RZ, R24 ; IMAD.MOV.U32 R31, RZ, RZ, R25 ; BSYNC B2 ; IMAD.IADD R23, R2, 0x1, R39 ; ISETP.GE.AND P1, PT, R4, 0x1, PT ; IMAD.MOV.U32 R34, RZ, RZ, 0x8 ; BSSY B2, 0x33d0 ; IMAD.WIDE R22, R23, R34, c[0x0][0x160] ; STG.E.64 [R22.64], R30 ; DSETP.EQ.OR P1, PT, R30, RZ, !P1 ; @P1 BRA 0x33c0 ; ISETP.GE.U32.AND P1, PT, R8, 0x3, PT ; BSSY B3, 0x3270 ; ISETP.NE.AND P2, PT, R9, RZ, PT ; IMAD R35, R4, R39, R5 ; IMAD.MOV.U32 R38, RZ, RZ, RZ ; @!P1 BRA 0x3260 ; IMAD.MOV.U32 R38, RZ, RZ, RZ ; IMAD.MOV.U32 R40, RZ, RZ, R36 ; IMAD.IADD R23, R6, 0x1, R38.reuse ; IMAD.IADD R25, R35, 0x1, R38 ; IMAD.WIDE R22, R23, R34, c[0x0][0x190] ; IMAD.WIDE R24, R25, R34, c[0x0][0x178] ; LDG.E.64 R42, [R22.64] ; LDG.E.64 R26, [R24.64] ; LDG.E.64 R32, [R22.64+0x8] ; DFMA R42, R26, -R30, R42 ; STG.E.64 [R22.64], R42 ; LDG.E.64 R26, [R24.64+0x8] ; DFMA R32, R26, -R30.reuse, R32 ; LDG.E.64 R26, [R22.64+0x10] ; STG.E.64 [R22.64+0x8], R32 ; LDG.E.64 R28, [R24.64+0x10] ; DFMA R26, R28, -R30, R26 ; LDG.E.64 R28, [R22.64+0x18] ; STG.E.64 [R22.64+0x10], R26 ; LDG.E.64 R44, [R24.64+0x18] ; IADD3 R40, R40, -0x4, RZ ; ISETP.NE.AND P1, PT, R40, RZ, PT ; IADD3 R38, R38, 0x4, RZ ; DFMA R28, R44, -R30, R28 ; STG.E.64 [R22.64+0x18], R28 ; @P1 BRA 0x30e0 ; BSYNC B3 ; @!P2 BRA 0x33c0 ; IMAD.IADD R23, R35, 0x1, R38.reuse ; IMAD.IADD R35, R6, 0x1, R38 ; IMAD.WIDE R22, R23, R34, c[0x0][0x178] ; IMAD.WIDE R34, R35, R34, c[0x0][0x190] ; LDG.E.64 R26, [R22.64] ; LDG.E.64 R24, [R34.64] ; ISETP.NE.AND P1, PT, R9, 0x1, PT ; DFMA R24, R26, -R30, R24 ; STG.E.64 [R34.64], R24 ; @!P1 BRA 0x33c0 ; LDG.E.64 R26, [R22.64+0x8] ; LDG.E.64 R24, [R34.64+0x8] ; ISETP.NE.AND P1, PT, R9, 0x2, PT ; DFMA R24, R26, -R30, R24 ; STG.E.64 [R34.64+0x8], R24 ; @!P1 BRA 0x33c0 ; LDG.E.64 R22, [R22.64+0x10] ; LDG.E.64 R24, [R34.64+0x10] ; DFMA R24, R22, -R30, R24 ; STG.E.64 [R34.64+0x10], R24 ; BSYNC B2 ; IMAD.MOV.U32 R22, RZ, RZ, c[0x0][0x1d8] ; DADD R20, R20, -R30 ; ISETP.NE.AND P1, PT, R22.reuse, 0x2, PT ; DMUL R20, R20, R20 ; ISETP.NE.AND P1, PT, R22, 0x4, P1 ; @!P1 DMUL R22, R20, R14 ; @!P1 ISETP.NE.AND P0, PT, R39.reuse, RZ, !P0 ; IADD3 R39, R39, 0x1, RZ ; @!P1 ISETP.EQ.OR P0, PT, R7, RZ, P0 ; @!P1 FSEL R22, R22, R20, P0 ; @!P1 FSEL R23, R23, R21, P0 ; @!P1 IMAD.MOV.U32 R20, RZ, RZ, R22 ; @!P1 IMAD.MOV.U32 R21, RZ, RZ, R23 ; ISETP.GE.AND P1, PT, R39, R3, PT ; DSETP.GT.AND P0, PT, R20, R18, PT ; FSEL R18, R20, R18, P0 ; FSEL R19, R21, R19, P0 ; @P1 CALL.REL.NOINC 0x3500 ; BRA 0x1d90 ; BSYNC B1 ; IADD3 R37, R37, 0x1, RZ ; DSETP.GE.AND P1, PT, R18, R16, PT ; ISETP.GE.AND P0, PT, R37, R0, PT ; @!P0 BRA P1, 0x550 ; BSYNC B0 ; WARPSYNC 0xffffffff ; S2R R0, SR_TID.X ; ISETP.GE.AND P1, PT, R3, 0x1, PT ; S2R R5, SR_CTAID.X ; IMAD R0, R5, c[0x0][0x1dc], R0 ; SHF.R.S32.HI R5, RZ, 0x1f, R0 ; LEA R4, P0, R0, c[0x0][0x198], 0x3 ; LEA.HI.X R5, R0, c[0x0][0x19c], R5, 0x3, P0 ; @!P1 EXIT ; LDG.E.64 R4, [R4.64] ; IADD3 R0, R3.reuse, -0x1, RZ ; BSSY B0, 0x37d0 ; LOP3.LUT R16, R3, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R17, RZ, RZ, RZ ; ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; ISETP.NE.AND P1, PT, R16, RZ, PT ; @!P0 BRA 0x37c0 ; IMAD.IADD R3, R3, 0x1, -R16 ; IMAD.MOV.U32 R17, RZ, RZ, RZ ; IMAD.IADD R6, R2, 0x1, R17 ; IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; LDG.E.64 R8, [R6.64] ; LDG.E.64 R10, [R6.64+0x8] ; LDG.E.64 R12, [R6.64+0x10] ; LDG.E.64 R14, [R6.64+0x18] ; IADD3 R3, R3, -0x4, RZ ; IADD3 R17, R17, 0x4, RZ ; ISETP.NE.AND P0, PT, R3, RZ, PT ; DMUL R8, R4, R8 ; DMUL R10, R4, R10 ; STG.E.64 [R6.64], R8 ; DMUL R12, R4, R12 ; STG.E.64 [R6.64+0x8], R10 ; DMUL R14, R4, R14 ; STG.E.64 [R6.64+0x10], R12 ; STG.E.64 [R6.64+0x18], R14 ; @P0 BRA 0x3690 ; BSYNC B0 ; @!P1 EXIT ; IMAD.IADD R2, R2, 0x1, R17 ; IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; IMAD.MOV.U32 R0, RZ, RZ, R2 ; IMAD.MOV.U32 R9, RZ, RZ, R3 ; IMAD.MOV.U32 R6, RZ, RZ, R0 ; IMAD.MOV.U32 R7, RZ, RZ, R9 ; LDG.E.64 R2, [R6.64] ; IADD3 R16, R16, -0x1, RZ ; IADD3 R0, P1, R6, 0x8, RZ ; ISETP.NE.AND P0, PT, R16, RZ, PT ; IMAD.X R9, RZ, RZ, R7, P1 ; DMUL R2, R4, R2 ; STG.E.64 [R6.64], R2 ; @P0 BRA 0x3830 ; EXIT ; IMAD.MOV.U32 R14, RZ, RZ, R18 ; BSSY B2, 0x3b50 ; IMAD.MOV.U32 R15, RZ, RZ, R19 ; DSETP.GTU.AND P0, PT, |R14|, +INF , PT ; @P0 BRA 0x3b20 ; LOP3.LUT R9, R19, 0x7fffffff, RZ, 0xc0, !PT ; IADD3 R18, R9, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R18, 0x7fefffff, PT ; @P0 LOP3.LUT R19, R15, 0x7ff00000, RZ, 0x3c, !PT ; @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; @P0 BRA 0x3b40 ; ISETP.GE.U32.AND P0, PT, R9, 0x1000001, PT ; @!P0 BRA 0x3a80 ; IADD3 R19, R15, -0x3fe00000, RZ ; IMAD.MOV.U32 R18, RZ, RZ, R14 ; MUFU.RCP64H R21, R19 ; DFMA R22, -R18, R20, 1 ; DFMA R22, R22, R22, R22 ; DFMA R22, R20, R22, R20 ; DFMA R20, -R18, R22, 1 ; DFMA R20, R22, R20, R22 ; DMUL R20, R20, 2.2250738585072013831e-308 ; DFMA R14, -R14, R20, 1 ; DFMA R14, R14, R14, R14 ; DFMA R18, R20, R14, R20 ; BRA 0x3b40 ; DMUL R14, R14, 8.11296384146066816958e+31 ; IMAD.MOV.U32 R18, RZ, RZ, R20 ; MUFU.RCP64H R19, R15 ; DFMA R20, -R14, R18, 1 ; DFMA R20, R20, R20, R20 ; DFMA R20, R18, R20, R18 ; DFMA R18, -R14, R20, 1 ; DFMA R18, R20, R18, R20 ; DMUL R18, R18, 8.11296384146066816958e+31 ; BRA 0x3b40 ; LOP3.LUT R19, R15, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R18, RZ, RZ, R14 ; BSYNC B2 ; IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; IMAD.MOV.U32 R14, RZ, RZ, R18 ; IMAD.MOV.U32 R15, RZ, RZ, R19 ; RET.REL.NODEC R8 0x0 ; FSETP.GEU.AND P1, PT, |R23|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R25, RZ, RZ, R27 ; LOP3.LUT R34, R23.reuse, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R28, RZ, RZ, 0x1 ; LOP3.LUT R43, R23, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R41, RZ, RZ, 0x1ca00000 ; LOP3.LUT R35, R34, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R34, RZ, RZ, R22 ; FSETP.GEU.AND P3, PT, |R25|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R24, RZ, RZ, R26 ; LOP3.LUT R40, R25, 0x7ff00000, RZ, 0xc0, !PT ; BSSY B4, 0x4140 ; @!P1 DMUL R34, R22, 8.98846567431157953865e+307 ; ISETP.GE.U32.AND P2, PT, R40, R43, PT ; IMAD.MOV.U32 R32, RZ, RZ, R24 ; SEL R33, R41, 0x63400000, !P2 ; MUFU.RCP64H R29, R35 ; @!P3 LOP3.LUT R27, R23, 0x7ff00000, RZ, 0xc0, !PT ; @!P3 IMAD.MOV.U32 R30, RZ, RZ, RZ ; LOP3.LUT R33, R33, 0x800fffff, R25, 0xf8, !PT ; @!P3 ISETP.GE.U32.AND P4, PT, R40, R27, PT ; @!P1 LOP3.LUT R43, R35, 0x7ff00000, RZ, 0xc0, !PT ; @!P3 SEL R31, R41, 0x63400000, !P4 ; @!P3 LOP3.LUT R31, R31, 0x80000000, R25, 0xf8, !PT ; DFMA R26, R28, -R34, 1 ; @!P3 LOP3.LUT R31, R31, 0x100000, RZ, 0xfc, !PT ; DFMA R26, R26, R26, R26 ; @!P3 DFMA R32, R32, 2, -R30 ; DFMA R26, R28, R26, R28 ; DFMA R30, R26, -R34, 1 ; DFMA R30, R26, R30, R26 ; DMUL R26, R30, R32 ; DFMA R28, R26, -R34, R32 ; DFMA R28, R30, R28, R26 ; IMAD.MOV.U32 R30, RZ, RZ, R40 ; @!P3 LOP3.LUT R30, R33, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R26, R30, -0x1, RZ ; ISETP.GT.U32.AND P1, PT, R26, 0x7feffffe, PT ; IADD3 R26, R43, -0x1, RZ ; ISETP.GT.U32.OR P1, PT, R26, 0x7feffffe, P1 ; @P1 BRA 0x3fe0 ; LOP3.LUT R25, R23, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P1, PT, R40.reuse, R25, PT ; IMAD.IADD R24, R40, 0x1, -R25 ; SEL R41, R41, 0x63400000, !P1 ; IMNMX R24, R24, -0x46a00000, !PT ; IMNMX R24, R24, 0x46a00000, PT ; IMAD.IADD R30, R24, 0x1, -R41 ; IMAD.MOV.U32 R24, RZ, RZ, RZ ; IADD3 R25, R30, 0x7fe00000, RZ ; DMUL R26, R28, R24 ; FSETP.GTU.AND P1, PT, |R27|, 1.469367938527859385e-39, PT ; @P1 BRA 0x4130 ; DFMA R32, R28, -R34, R32 ; IMAD.MOV.U32 R24, RZ, RZ, RZ ; FSETP.NEU.AND P1, PT, R33.reuse, RZ, PT ; LOP3.LUT R31, R33, 0x80000000, R23, 0x48, !PT ; LOP3.LUT R25, R31, R25, RZ, 0xfc, !PT ; @!P1 BRA 0x4130 ; IMAD.MOV R23, RZ, RZ, -R30 ; DMUL.RP R24, R28, R24 ; IMAD.MOV.U32 R22, RZ, RZ, RZ ; DFMA R22, R26, -R22, R28 ; LOP3.LUT R31, R25, R31, RZ, 0x3c, !PT ; IADD3 R22, -R30, -0x43300000, RZ ; FSETP.NEU.AND P1, PT, |R23|, R22, PT ; FSEL R26, R24, R26, !P1 ; FSEL R27, R31, R27, !P1 ; BRA 0x4130 ; DSETP.NAN.AND P1, PT, R24, R24, PT ; @P1 BRA 0x4110 ; DSETP.NAN.AND P1, PT, R22, R22, PT ; @P1 BRA 0x40e0 ; ISETP.NE.AND P1, PT, R30, R43, PT ; IMAD.MOV.U32 R26, RZ, RZ, 0x0 ; IMAD.MOV.U32 R27, RZ, RZ, -0x80000 ; @!P1 BRA 0x4130 ; ISETP.NE.AND P1, PT, R30, 0x7ff00000, PT ; LOP3.LUT R27, R25, 0x80000000, R23, 0x48, !PT ; ISETP.EQ.OR P1, PT, R43, RZ, !P1 ; @P1 LOP3.LUT R22, R27, 0x7ff00000, RZ, 0xfc, !PT ; @!P1 IMAD.MOV.U32 R26, RZ, RZ, RZ ; @P1 IMAD.MOV.U32 R26, RZ, RZ, RZ ; @P1 IMAD.MOV.U32 R27, RZ, RZ, R22 ; BRA 0x4130 ; LOP3.LUT R27, R23, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R26, RZ, RZ, R22 ; BRA 0x4130 ; LOP3.LUT R27, R25, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R26, RZ, RZ, R24 ; BSYNC B4 ; IMAD.MOV.U32 R22, RZ, RZ, R38 ; IMAD.MOV.U32 R23, RZ, RZ, 0x0 ; IMAD.MOV.U32 R24, RZ, RZ, R26 ; IMAD.MOV.U32 R25, RZ, RZ, R27 ; RET.REL.NODEC R22 0x0 ; BRA 0x4190; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z21model_fit_preparationPdS_S_S_S_S_S_iii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R3, SR_CTAID.X ; ULDC UR4, c[0x0][0x19c] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1a0] ; UIADD3 UR4, UR4, -0x1, URZ ; S2R R2, SR_TID.X ; ISETP.NE.AND P0, PT, R3, UR4, PT ; SEL R0, R0, c[0x0][0x198], !P0 ; ISETP.GE.AND P0, PT, R2, R0, PT ; @P0 EXIT ; IMAD.MOV.U32 R0, RZ, RZ, 0x8 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD R3, R3, c[0x0][0x198], R2 ; IMAD.WIDE R4, R3, R0, c[0x0][0x188] ; LDG.E.64 R4, [R4.64] ; IMAD.WIDE R12, R3, R0, c[0x0][0x190] ; LDG.E.64 R12, [R12.64] ; BSSY B0, 0x920 ; CS2R R10, SRZ ; CS2R R22, SRZ ; SHF.R.S32.HI R8, RZ, 0x1f, R3 ; F2I.F64.TRUNC R6, R4 ; F2I.F64.TRUNC R31, R12 ; ISETP.GE.AND P1, PT, R6, 0x1, PT ; @!P1 BRA 0x910 ; IADD3 R2, R6.reuse, -0x1, RZ ; BSSY B1, 0x820 ; LOP3.LUT R7, R6, 0x3, RZ, 0xc0, !PT ; CS2R R22, SRZ ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; @!P0 BRA 0x810 ; IMAD.IADD R9, R6, 0x1, -R7 ; BSSY B2, 0x710 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; CS2R R22, SRZ ; IMAD.WIDE R4, R31, R0, c[0x0][0x160] ; ISETP.GT.AND P0, PT, R9, RZ, PT ; @!P0 BRA 0x700 ; ISETP.GT.AND P2, PT, R9, 0xc, PT ; BSSY B3, 0x530 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0x520 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E.64 R20, [R4.64] ; LDG.E.64 R24, [R4.64+0x8] ; LDG.E.64 R26, [R4.64+0x10] ; LDG.E.64 R28, [R4.64+0x18] ; LDG.E.64 R34, [R4.64+0x20] ; LDG.E.64 R32, [R4.64+0x28] ; LDG.E.64 R12, [R4.64+0x30] ; LDG.E.64 R14, [R4.64+0x38] ; LDG.E.64 R16, [R4.64+0x40] ; LDG.E.64 R18, [R4.64+0x48] ; DADD R22, R20, R22 ; LDG.E.64 R20, [R4.64+0x50] ; DADD R24, R22, R24 ; LDG.E.64 R22, [R4.64+0x58] ; DADD R26, R24, R26 ; LDG.E.64 R24, [R4.64+0x60] ; DADD R28, R26, R28 ; LDG.E.64 R26, [R4.64+0x68] ; DADD R34, R28, R34 ; LDG.E.64 R28, [R4.64+0x70] ; DADD R32, R34, R32 ; LDG.E.64 R34, [R4.64+0x78] ; IADD3 R9, R9, -0x10, RZ ; DADD R12, R32, R12 ; IADD3 R2, R2, 0x10, RZ ; ISETP.GT.AND P2, PT, R9, 0xc, PT ; DADD R12, R12, R14 ; IADD3 R4, P3, R4, 0x80, RZ ; DADD R12, R12, R16 ; IMAD.X R5, RZ, RZ, R5, P3 ; DADD R12, R12, R18 ; DADD R12, R12, R20 ; DADD R12, R12, R22 ; DADD R12, R12, R24 ; DADD R12, R12, R26 ; DADD R12, R12, R28 ; DADD R22, R12, R34 ; @P2 BRA 0x2c0 ; BSYNC B3 ; ISETP.GT.AND P2, PT, R9, 0x4, PT ; BSSY B3, 0x6d0 ; @!P2 BRA 0x6c0 ; LDG.E.64 R28, [R4.64] ; LDG.E.64 R12, [R4.64+0x8] ; LDG.E.64 R14, [R4.64+0x10] ; LDG.E.64 R16, [R4.64+0x18] ; LDG.E.64 R18, [R4.64+0x20] ; LDG.E.64 R20, [R4.64+0x28] ; LDG.E.64 R24, [R4.64+0x30] ; LDG.E.64 R26, [R4.64+0x38] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R2, R2, 0x8, RZ ; IADD3 R9, R9, -0x8, RZ ; DADD R28, R22, R28 ; DADD R12, R28, R12 ; DADD R12, R12, R14 ; IADD3 R14, P2, R4, 0x40, RZ ; DADD R12, R12, R16 ; IMAD.X R5, RZ, RZ, R5, P2 ; IMAD.MOV.U32 R4, RZ, RZ, R14 ; DADD R12, R12, R18 ; DADD R12, R12, R20 ; DADD R12, R12, R24 ; DADD R22, R12, R26 ; BSYNC B3 ; ISETP.NE.OR P0, PT, R9, RZ, P0 ; @!P0 BREAK B2 ; @!P0 BRA 0x810 ; BSYNC B2 ; LDG.E.64 R14, [R4.64] ; LDG.E.64 R16, [R4.64+0x8] ; LDG.E.64 R18, [R4.64+0x10] ; LDG.E.64 R12, [R4.64+0x18] ; IADD3 R9, R9, -0x4, RZ ; IADD3 R2, R2, 0x4, RZ ; ISETP.NE.AND P0, PT, R9, RZ, PT ; DADD R14, R14, R22 ; DADD R14, R14, R16 ; IADD3 R16, P2, R4, 0x20, RZ ; DADD R14, R14, R18 ; IMAD.X R17, RZ, RZ, R5, P2 ; IMAD.MOV.U32 R4, RZ, RZ, R16 ; IMAD.MOV.U32 R5, RZ, RZ, R17 ; DADD R22, R14, R12 ; @P0 BRA 0x710 ; BSYNC B1 ; ISETP.NE.AND P0, PT, R7, RZ, PT ; @!P0 BRA 0x910 ; IMAD.IADD R5, R31, 0x1, R2 ; IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; IMAD.MOV.U32 R0, RZ, RZ, R4 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; IMAD.MOV.U32 R4, RZ, RZ, R0 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; LDG.E.64 R4, [R4.64] ; IADD3 R7, R7, -0x1, RZ ; IADD3 R0, P2, R0, 0x8, RZ ; ISETP.NE.AND P0, PT, R7, RZ, PT ; IMAD.X R9, RZ, RZ, R9, P2 ; DADD R22, R4, R22 ; @P0 BRA 0x880 ; BSYNC B0 ; WARPSYNC 0xffffffff ; I2F.F64 R4, R6 ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; FSETP.GEU.AND P2, PT, |R23|, 6.5827683646048100446e-37, PT ; BSSY B0, 0xac0 ; MUFU.RCP64H R13, R5 ; DFMA R14, -R4, R12, 1 ; DFMA R14, R14, R14, R14 ; DFMA R14, R12, R14, R12 ; DFMA R12, -R4, R14, 1 ; DFMA R12, R14, R12, R14 ; DMUL R14, R12, R22 ; DFMA R16, -R4, R14, R22 ; DFMA R12, R12, R16, R14 ; FFMA R0, RZ, R5, R13 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0xab0 ; IMAD.MOV.U32 R20, RZ, RZ, R22 ; MOV R30, 0xa90 ; IMAD.MOV.U32 R21, RZ, RZ, R23 ; IMAD.MOV.U32 R18, RZ, RZ, R4 ; IMAD.MOV.U32 R19, RZ, RZ, R5 ; CALL.REL.NOINC 0x2410 ; IMAD.MOV.U32 R12, RZ, RZ, R2 ; IMAD.MOV.U32 R13, RZ, RZ, R19 ; BSYNC B0 ; BSSY B0, 0x1440 ; @!P1 BRA 0x1430 ; IADD3 R0, R6.reuse, -0x1, RZ ; BSSY B1, 0x1320 ; LOP3.LUT R7, R6, 0x3, RZ, 0xc0, !PT ; CS2R R10, SRZ ; ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; @!P0 BRA 0x1310 ; IMAD.IADD R2, R6, 0x1, -R7 ; BSSY B2, 0x11e0 ; IMAD.MOV.U32 R14, RZ, RZ, 0x8 ; CS2R R10, SRZ ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; ISETP.GT.AND P0, PT, R2, RZ, PT ; IMAD.WIDE R14, R31, R14, c[0x0][0x160] ; @!P0 BRA 0x11d0 ; ISETP.GT.AND P2, PT, R2, 0xc, PT ; BSSY B3, 0xf90 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0xf80 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E.64 R28, [R14.64] ; LDG.E.64 R24, [R14.64+0x8] ; LDG.E.64 R26, [R14.64+0x10] ; LDG.E.64 R20, [R14.64+0x18] ; LDG.E.64 R22, [R14.64+0x20] ; LDG.E.64 R18, [R14.64+0x28] ; LDG.E.64 R34, [R14.64+0x30] ; LDG.E.64 R16, [R14.64+0x38] ; LDG.E.64 R32, [R14.64+0x40] ; DADD R28, R28, -R12 ; DADD R24, R24, -R12 ; DFMA R10, R28, R28, R10 ; LDG.E.64 R28, [R14.64+0x48] ; DFMA R24, R24, R24, R10 ; DADD R10, R26, -R12.reuse ; LDG.E.64 R26, [R14.64+0x50] ; DADD R20, R20, -R12 ; DFMA R10, R10, R10, R24 ; LDG.E.64 R24, [R14.64+0x58] ; DFMA R20, R20, R20, R10 ; DADD R10, R22, -R12.reuse ; LDG.E.64 R22, [R14.64+0x60] ; DADD R18, R18, -R12 ; DFMA R10, R10, R10, R20 ; LDG.E.64 R20, [R14.64+0x70] ; DFMA R10, R18, R18, R10 ; LDG.E.64 R18, [R14.64+0x68] ; DADD R34, R34, -R12 ; DFMA R34, R34, R34, R10 ; LDG.E.64 R10, [R14.64+0x78] ; DADD R16, R16, -R12 ; DADD R32, R32, -R12 ; DFMA R34, R16, R16, R34 ; DFMA R34, R32, R32, R34 ; IADD3 R2, R2, -0x10, RZ ; ISETP.GT.AND P2, PT, R2, 0xc, PT ; IADD3 R14, P3, R14, 0x80, RZ ; IADD3 R0, R0, 0x10, RZ ; IMAD.X R15, RZ, RZ, R15, P3 ; DADD R28, R28, -R12 ; DFMA R34, R28, R28, R34 ; DADD R26, R26, -R12 ; DFMA R34, R26, R26, R34 ; DADD R24, R24, -R12 ; DFMA R34, R24, R24, R34 ; DADD R22, R22, -R12 ; DFMA R34, R22, R22, R34 ; DADD R18, R18, -R12 ; DADD R20, R20, -R12 ; DFMA R34, R18, R18, R34 ; DADD R10, R10, -R12 ; DFMA R34, R20, R20, R34 ; DFMA R10, R10, R10, R34 ; @P2 BRA 0xc20 ; BSYNC B3 ; ISETP.GT.AND P2, PT, R2, 0x4, PT ; BSSY B3, 0x11a0 ; @!P2 BRA 0x1190 ; LDG.E.64 R32, [R14.64] ; LDG.E.64 R28, [R14.64+0x8] ; LDG.E.64 R26, [R14.64+0x10] ; LDG.E.64 R24, [R14.64+0x18] ; LDG.E.64 R22, [R14.64+0x20] ; LDG.E.64 R18, [R14.64+0x28] ; LDG.E.64 R20, [R14.64+0x30] ; LDG.E.64 R16, [R14.64+0x38] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R0, R0, 0x8, RZ ; IADD3 R2, R2, -0x8, RZ ; IADD3 R14, P2, R14, 0x40, RZ ; IMAD.X R15, RZ, RZ, R15, P2 ; DADD R32, R32, -R12 ; DADD R28, R28, -R12 ; DFMA R10, R32, R32, R10 ; DADD R26, R26, -R12 ; DFMA R10, R28, R28, R10 ; DADD R24, R24, -R12 ; DFMA R10, R26, R26, R10 ; DADD R22, R22, -R12 ; DFMA R10, R24, R24, R10 ; DADD R18, R18, -R12 ; DFMA R10, R22, R22, R10 ; DADD R20, R20, -R12 ; DFMA R10, R18, R18, R10 ; DADD R16, R16, -R12 ; DFMA R10, R20, R20, R10 ; DFMA R10, R16, R16, R10 ; BSYNC B3 ; ISETP.NE.OR P0, PT, R2, RZ, P0 ; @!P0 BREAK B2 ; @!P0 BRA 0x1310 ; BSYNC B2 ; LDG.E.64 R18, [R14.64] ; LDG.E.64 R20, [R14.64+0x8] ; LDG.E.64 R22, [R14.64+0x10] ; LDG.E.64 R16, [R14.64+0x18] ; IADD3 R2, R2, -0x4, RZ ; IADD3 R9, P2, R14, 0x20, RZ ; ISETP.NE.AND P0, PT, R2, RZ, PT ; IADD3 R0, R0, 0x4, RZ ; IMAD.X R15, RZ, RZ, R15, P2 ; IMAD.MOV.U32 R14, RZ, RZ, R9 ; DADD R18, R18, -R12 ; DADD R20, R20, -R12 ; DFMA R10, R18, R18, R10 ; DADD R22, R22, -R12 ; DFMA R10, R20, R20, R10 ; DADD R16, R16, -R12 ; DFMA R10, R22, R22, R10 ; DFMA R10, R16, R16, R10 ; @P0 BRA 0x11e0 ; BSYNC B1 ; ISETP.NE.AND P0, PT, R7, RZ, PT ; @!P0 BRA 0x1430 ; MOV R15, 0x8 ; IMAD.IADD R14, R31, 0x1, R0 ; IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; IMAD.MOV.U32 R0, RZ, RZ, R14 ; IMAD.MOV.U32 R9, RZ, RZ, R15 ; IMAD.MOV.U32 R16, RZ, RZ, R0 ; IMAD.MOV.U32 R17, RZ, RZ, R9 ; LDG.E.64 R14, [R16.64] ; IADD3 R7, R7, -0x1, RZ ; IADD3 R0, P2, R0, 0x8, RZ ; ISETP.NE.AND P0, PT, R7, RZ, PT ; IMAD.X R9, RZ, RZ, R9, P2 ; DADD R14, R14, -R12 ; DFMA R10, R14, R14, R10 ; @P0 BRA 0x1390 ; BSYNC B0 ; WARPSYNC 0xffffffff ; MUFU.RCP64H R13, R5 ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; FSETP.GEU.AND P2, PT, |R11|, 6.5827683646048100446e-37, PT ; BSSY B0, 0x15d0 ; DFMA R14, -R4, R12, 1 ; DFMA R14, R14, R14, R14 ; DFMA R14, R12, R14, R12 ; DFMA R12, -R4, R14, 1 ; DFMA R16, R14, R12, R14 ; DMUL R12, R16, R10 ; DFMA R14, -R4, R12, R10 ; DFMA R12, R16, R14, R12 ; FFMA R0, RZ, R5, R13 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x15c0 ; IMAD.MOV.U32 R20, RZ, RZ, R10 ; MOV R30, 0x15a0 ; IMAD.MOV.U32 R21, RZ, RZ, R11 ; IMAD.MOV.U32 R18, RZ, RZ, R4 ; IMAD.MOV.U32 R19, RZ, RZ, R5 ; CALL.REL.NOINC 0x2410 ; IMAD.MOV.U32 R12, RZ, RZ, R2 ; IMAD.MOV.U32 R13, RZ, RZ, R19 ; BSYNC B0 ; MUFU.RSQ64H R5, R13 ; IADD3 R4, R13, -0x3500000, RZ ; IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; BSSY B0, 0x1730 ; IMAD.MOV.U32 R15, RZ, RZ, 0x3fd80000 ; ISETP.GE.U32.AND P0, PT, R4, 0x7ca00000, PT ; DMUL R10, R4, R4 ; DFMA R10, -R10, R12, 1 ; DFMA R14, R10, R14, 0.5 ; DMUL R10, R4, R10 ; DFMA R16, R14, R10, R4 ; DMUL R18, R16, R12 ; IADD3 R15, R17, -0x100000, RZ ; IMAD.MOV.U32 R14, RZ, RZ, R16 ; DFMA R20, R18, -R18, R12 ; DFMA R10, R20, R14, R18 ; @!P0 BRA 0x1720 ; IMAD.MOV.U32 R10, RZ, RZ, R12 ; MOV R0, 0x1720 ; IMAD.MOV.U32 R11, RZ, RZ, R13 ; CALL.REL.NOINC 0x29f0 ; BSYNC B0 ; IMAD.SHL.U32 R4, R3.reuse, 0x8, RZ ; DSETP.NEU.AND P0, PT, R10, RZ, PT ; SHF.L.U64.HI R8, R3, 0x3, R8 ; IADD3 R2, P2, R4, c[0x0][0x178], RZ ; IADD3.X R3, R8, c[0x0][0x17c], RZ, P2, !PT ; STG.E.64 [R2.64], R10 ; @!P0 EXIT ; IADD3 R14, P0, R4.reuse, c[0x0][0x170], RZ ; IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; IADD3 R4, P2, R4, c[0x0][0x180], RZ ; IMAD.MOV.U32 R17, RZ, RZ, 0x3ff00000 ; IADD3.X R15, R8.reuse, c[0x0][0x174], RZ, P0, !PT ; IADD3.X R5, R8, c[0x0][0x184], RZ, P2, !PT ; STG.E.64 [R14.64], R16 ; LDG.E.64 R20, [R4.64] ; MUFU.RCP64H R3, R11 ; IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; BSSY B0, 0x1970 ; DFMA R8, R2, -R10, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R2, R8, R2 ; DFMA R2, R8, -R10, 1 ; DFMA R2, R8, R2, R8 ; DMUL R8, R20, R2 ; FSETP.GEU.AND P2, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R12, R8, -R10, R20 ; DFMA R2, R2, R12, R8 ; FFMA R0, RZ, R11, R3 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x1960 ; IMAD.MOV.U32 R18, RZ, RZ, R10 ; MOV R30, 0x1950 ; IMAD.MOV.U32 R19, RZ, RZ, R11 ; CALL.REL.NOINC 0x2410 ; IMAD.MOV.U32 R3, RZ, RZ, R19 ; BSYNC B0 ; STG.E.64 [R4.64], R2 ; @!P1 EXIT ; IADD3 R0, R6.reuse, -0x1, RZ ; BSSY B0, 0x2150 ; LOP3.LUT R9, R6, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; @!P0 BRA 0x2140 ; IMAD.IADD R7, R6, 0x1, -R9 ; MOV R8, RZ ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; IMAD.MOV.U32 R12, RZ, RZ, R6 ; IMAD.MOV.U32 R13, RZ, RZ, R5 ; IMAD.WIDE R12, R31, 0x8, R12 ; LDG.E.64 R20, [R12.64] ; MUFU.RCP64H R15, R11 ; IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; BSSY B1, 0x1bf0 ; DFMA R16, R14, -R10, 1 ; DFMA R16, R16, R16, R16 ; DFMA R16, R14, R16, R14 ; DFMA R14, R16, -R10, 1 ; DFMA R18, R16, R14, R16 ; DMUL R14, R18, R20 ; FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R16, R14, -R10, R20 ; DFMA R16, R18, R16, R14 ; FFMA R0, RZ, R11, R17 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1be0 ; IMAD.MOV.U32 R18, RZ, RZ, R10 ; MOV R30, 0x1bc0 ; IMAD.MOV.U32 R19, RZ, RZ, R11 ; CALL.REL.NOINC 0x2410 ; IMAD.MOV.U32 R16, RZ, RZ, R2 ; IMAD.MOV.U32 R17, RZ, RZ, R19 ; BSYNC B1 ; IMAD.MOV.U32 R2, RZ, RZ, R4 ; STG.E.64 [R12.64], R16 ; IMAD.WIDE R14, R31, 0x8, R2 ; STG.E.64 [R14.64], R16 ; LDG.E.64 R20, [R12.64+0x8] ; MUFU.RCP64H R19, R11 ; IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; BSSY B1, 0x1d90 ; DFMA R22, R18, -R10, 1 ; DFMA R22, R22, R22, R22 ; DFMA R22, R18, R22, R18 ; DFMA R18, R22, -R10, 1 ; DFMA R24, R22, R18, R22 ; DMUL R18, R24, R20 ; FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R22, R18, -R10, R20 ; DFMA R18, R24, R22, R18 ; FFMA R0, RZ, R11, R19 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1d80 ; IMAD.MOV.U32 R18, RZ, RZ, R10 ; MOV R30, 0x1d70 ; IMAD.MOV.U32 R19, RZ, RZ, R11 ; CALL.REL.NOINC 0x2410 ; IMAD.MOV.U32 R18, RZ, RZ, R2 ; BSYNC B1 ; STG.E.64 [R12.64+0x8], R18 ; STG.E.64 [R14.64+0x8], R18 ; LDG.E.64 R20, [R12.64+0x10] ; MUFU.RCP64H R17, R11 ; IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; BSSY B1, 0x1f20 ; DFMA R22, R16, -R10, 1 ; DFMA R22, R22, R22, R22 ; DFMA R22, R16, R22, R16 ; DFMA R16, R22, -R10, 1 ; DFMA R24, R22, R16, R22 ; DMUL R16, R24, R20 ; FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R22, R16, -R10, R20 ; DFMA R16, R24, R22, R16 ; FFMA R0, RZ, R11, R17 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1f10 ; IMAD.MOV.U32 R18, RZ, RZ, R10 ; MOV R30, 0x1ef0 ; IMAD.MOV.U32 R19, RZ, RZ, R11 ; CALL.REL.NOINC 0x2410 ; IMAD.MOV.U32 R16, RZ, RZ, R2 ; IMAD.MOV.U32 R17, RZ, RZ, R19 ; BSYNC B1 ; STG.E.64 [R12.64+0x10], R16 ; STG.E.64 [R14.64+0x10], R16 ; LDG.E.64 R20, [R12.64+0x18] ; MUFU.RCP64H R19, R11 ; IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; BSSY B1, 0x20a0 ; DFMA R22, R18, -R10, 1 ; DFMA R22, R22, R22, R22 ; DFMA R22, R18, R22, R18 ; DFMA R18, R22, -R10, 1 ; DFMA R24, R22, R18, R22 ; DMUL R18, R24, R20 ; FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R22, R18, -R10, R20 ; DFMA R18, R24, R22, R18 ; FFMA R0, RZ, R11, R19 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2090 ; IMAD.MOV.U32 R18, RZ, RZ, R10 ; MOV R30, 0x2080 ; IMAD.MOV.U32 R19, RZ, RZ, R11 ; CALL.REL.NOINC 0x2410 ; IMAD.MOV.U32 R18, RZ, RZ, R2 ; BSYNC B1 ; STG.E.64 [R12.64+0x18], R18 ; IADD3 R7, R7, -0x4, RZ ; IADD3 R4, P1, R4, 0x20, RZ ; STG.E.64 [R14.64+0x18], R18 ; ISETP.NE.AND P0, PT, R7, RZ, PT ; IADD3 R6, P2, R6, 0x20, RZ ; IMAD.X R3, RZ, RZ, R3, P1 ; IADD3 R8, R8, 0x4, RZ ; IADD3.X R5, RZ, R5, RZ, P2, !PT ; @P0 BRA 0x1a50 ; BSYNC B0 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 EXIT ; IMAD.IADD R2, R31, 0x1, R8 ; IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; IMAD.MOV.U32 R0, RZ, RZ, R2 ; IMAD.MOV.U32 R15, RZ, RZ, R3 ; IMAD.MOV.U32 R6, RZ, RZ, R0 ; IMAD.MOV.U32 R7, RZ, RZ, R15 ; LDG.E.64 R20, [R6.64] ; MUFU.RCP64H R3, R11 ; IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; BSSY B0, 0x2350 ; DFMA R12, R2, -R10, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R2, R12, R2 ; DFMA R2, R12, -R10, 1 ; DFMA R14, R12, R2, R12 ; DMUL R2, R14, R20 ; FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R12, R2, -R10, R20 ; DFMA R2, R14, R12, R2 ; FFMA R0, RZ, R11, R3 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2340 ; IMAD.MOV.U32 R18, RZ, RZ, R10 ; MOV R30, 0x2330 ; IMAD.MOV.U32 R19, RZ, RZ, R11 ; CALL.REL.NOINC 0x2410 ; IMAD.MOV.U32 R3, RZ, RZ, R19 ; BSYNC B0 ; IMAD.MOV.U32 R12, RZ, RZ, R4 ; STG.E.64 [R6.64], R2 ; IMAD.MOV.U32 R13, RZ, RZ, R5 ; IADD3 R9, R9, -0x1, RZ ; IADD3 R0, P2, R6, 0x8, RZ ; STG.E.64 [R12.64], R2 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; IADD3 R4, P1, R4, 0x8, RZ ; IMAD.X R15, RZ, RZ, R7, P2 ; IMAD.X R5, RZ, RZ, R5, P1 ; @P0 BRA 0x21d0 ; EXIT ; FSETP.GEU.AND P0, PT, |R19|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R0, RZ, RZ, 0x1ca00000 ; LOP3.LUT R16, R19, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R24, RZ, RZ, 0x1 ; FSETP.GEU.AND P3, PT, |R21|.reuse, 1.469367938527859385e-39, PT ; BSSY B2, 0x29a0 ; LOP3.LUT R17, R16, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R16, RZ, RZ, R18 ; LOP3.LUT R2, R21, 0x7ff00000, RZ, 0xc0, !PT ; LOP3.LUT R33, R19, 0x7ff00000, RZ, 0xc0, !PT ; @!P0 DMUL R16, R18, 8.98846567431157953865e+307 ; ISETP.GE.U32.AND P2, PT, R2.reuse, R33, PT ; IMAD.MOV.U32 R32, RZ, RZ, R2 ; @!P3 LOP3.LUT R23, R19, 0x7ff00000, RZ, 0xc0, !PT ; MUFU.RCP64H R25, R17 ; @!P3 ISETP.GE.U32.AND P4, PT, R2, R23, PT ; SEL R23, R0, 0x63400000, !P2 ; @!P3 SEL R27, R0, 0x63400000, !P4 ; LOP3.LUT R23, R23, 0x800fffff, R21.reuse, 0xf8, !PT ; @!P3 LOP3.LUT R22, R27, 0x80000000, R21, 0xf8, !PT ; @!P0 LOP3.LUT R33, R17, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R28, R24, -R16, 1 ; IADD3 R34, R33, -0x1, RZ ; DFMA R26, R28, R28, R28 ; @!P3 LOP3.LUT R29, R22, 0x100000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R22, RZ, RZ, R20 ; @!P3 IMAD.MOV.U32 R28, RZ, RZ, RZ ; DFMA R24, R24, R26, R24 ; @!P3 DFMA R22, R22, 2, -R28 ; DFMA R26, R24, -R16, 1 ; @!P3 LOP3.LUT R32, R23, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R24, R24, R26, R24 ; IADD3 R28, R32, -0x1, RZ ; DMUL R26, R24, R22 ; ISETP.GT.U32.AND P0, PT, R28, 0x7feffffe, PT ; ISETP.GT.U32.OR P0, PT, R34, 0x7feffffe, P0 ; DFMA R28, R26, -R16, R22 ; DFMA R28, R24, R28, R26 ; @P0 BRA 0x2840 ; LOP3.LUT R21, R19, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R2.reuse, R21, PT ; IMAD.IADD R20, R2, 0x1, -R21 ; SEL R0, R0, 0x63400000, !P0 ; IMNMX R20, R20, -0x46a00000, !PT ; IMNMX R21, R20, 0x46a00000, PT ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; IMAD.IADD R0, R21, 0x1, -R0 ; IADD3 R21, R0, 0x7fe00000, RZ ; DMUL R24, R28, R20 ; FSETP.GTU.AND P0, PT, |R25|, 1.469367938527859385e-39, PT ; @P0 BRA 0x2990 ; DFMA R16, R28, -R16, R22 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R17.reuse, RZ, PT ; LOP3.LUT R19, R17, 0x80000000, R19, 0x48, !PT ; LOP3.LUT R21, R19, R21, RZ, 0xfc, !PT ; @!P0 BRA 0x2990 ; IMAD.MOV R17, RZ, RZ, -R0 ; MOV R16, RZ ; DMUL.RP R20, R28, R20 ; DFMA R16, R24, -R16, R28 ; LOP3.LUT R19, R21, R19, RZ, 0x3c, !PT ; IADD3 R16, -R0, -0x43300000, RZ ; FSETP.NEU.AND P0, PT, |R17|, R16, PT ; FSEL R24, R20, R24, !P0 ; FSEL R25, R19, R25, !P0 ; BRA 0x2990 ; DSETP.NAN.AND P0, PT, R20, R20, PT ; @P0 BRA 0x2970 ; DSETP.NAN.AND P0, PT, R18, R18, PT ; @P0 BRA 0x2940 ; ISETP.NE.AND P0, PT, R32, R33, PT ; IMAD.MOV.U32 R24, RZ, RZ, 0x0 ; IMAD.MOV.U32 R25, RZ, RZ, -0x80000 ; @!P0 BRA 0x2990 ; ISETP.NE.AND P0, PT, R32, 0x7ff00000, PT ; LOP3.LUT R25, R21, 0x80000000, R19, 0x48, !PT ; ISETP.EQ.OR P0, PT, R33, RZ, !P0 ; @P0 LOP3.LUT R0, R25, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R24, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R24, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R25, RZ, RZ, R0 ; BRA 0x2990 ; LOP3.LUT R25, R19, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R24, RZ, RZ, R18 ; BRA 0x2990 ; LOP3.LUT R25, R21, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R24, RZ, RZ, R20 ; BSYNC B2 ; IMAD.MOV.U32 R16, RZ, RZ, R30 ; IMAD.MOV.U32 R17, RZ, RZ, 0x0 ; IMAD.MOV.U32 R2, RZ, RZ, R24 ; IMAD.MOV.U32 R19, RZ, RZ, R25 ; RET.REL.NODEC R16 0x0 ; ISETP.GE.U32.AND P0, PT, R4, -0x3400000, PT ; BSSY B1, 0x2c70 ; IMAD.MOV.U32 R14, RZ, RZ, R16 ; IMAD.MOV.U32 R4, RZ, RZ, R20 ; IMAD.MOV.U32 R5, RZ, RZ, R21 ; @!P0 BRA 0x2ad0 ; DFMA.RM R4, R4, R14, R18 ; IADD3 R12, P0, R4, 0x1, RZ ; IMAD.X R13, RZ, RZ, R5, P0 ; DFMA.RP R10, -R4, R12, R10 ; DSETP.GT.AND P0, PT, R10, RZ, PT ; FSEL R4, R12, R4, P0 ; FSEL R5, R13, R5, P0 ; BRA 0x2c60 ; DSETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x2c50 ; ISETP.GE.AND P0, PT, R11, RZ, PT ; @!P0 IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; @!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; @!P0 BRA 0x2c60 ; ISETP.GT.AND P0, PT, R11, 0x7fefffff, PT ; @P0 BRA 0x2c50 ; DMUL R4, R10, 8.11296384146066816958e+31 ; IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; IMAD.MOV.U32 R15, RZ, RZ, 0x3fd80000 ; MUFU.RSQ64H R11, R5 ; DMUL R12, R10, R10 ; DFMA R12, R4, -R12, 1 ; DFMA R14, R12, R14, 0.5 ; DMUL R12, R10, R12 ; DFMA R12, R14, R12, R10 ; DMUL R10, R4, R12 ; IADD3 R13, R13, -0x100000, RZ ; DFMA R14, R10, -R10, R4 ; DFMA R4, R12, R14, R10 ; IADD3 R5, R5, -0x3500000, RZ ; BRA 0x2c60 ; DADD R4, R10, R10 ; BSYNC B1 ; IMAD.MOV.U32 R10, RZ, RZ, R4 ; IMAD.MOV.U32 R11, RZ, RZ, R5 ; IMAD.MOV.U32 R4, RZ, RZ, R0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; RET.REL.NODEC R4 0x0 ; BRA 0x2cc0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R14, SR_CTAID.X ; ULDC UR4, c[0x0][0x1a4] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1a8] ; UIADD3 UR4, UR4, -0x1, URZ ; S2R R3, SR_TID.X ; ISETP.NE.AND P0, PT, R14, UR4, PT ; SEL R0, R0, c[0x0][0x1a0], !P0 ; ISETP.GE.AND P0, PT, R3, R0, PT ; @P0 EXIT ; IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD R14, R14, c[0x0][0x1a0], R3 ; IMAD.WIDE R12, R14, R15, c[0x0][0x198] ; LDG.E.64 R6, [R12.64] ; IMAD.WIDE R4, R14, R15, c[0x0][0x190] ; LDG.E.64 R4, [R4.64] ; IMAD.WIDE R2, R14, R15, c[0x0][0x180] ; LDG.E.64 R2, [R2.64] ; BSSY B0, 0x2610 ; IMAD.WIDE R12, R14, R15, c[0x0][0x188] ; IMAD.WIDE R14, R14, R15, c[0x0][0x178] ; F2I.F64.TRUNC R7, R6 ; F2I.F64.TRUNC R10, R4 ; ISETP.NE.AND P0, PT, R7, 0x1, PT ; F2I.F64.TRUNC R8, R2 ; SEL R9, RZ, 0x1, P0 ; ISETP.GT.AND P0, PT, R10, R9, PT ; @!P0 BRA 0x2600 ; LDG.E.64 R12, [R12.64] ; LDG.E.64 R14, [R14.64] ; IMAD.MOV.U32 R3, RZ, RZ, R9 ; F2I.F64.TRUNC R5, R12 ; F2I.F64.TRUNC R6, R14 ; I2F.F64 R16, R5 ; LOP3.LUT R4, R5, 0x3, RZ, 0xc0, !PT ; IADD3 R2, R5, -0x1, RZ ; IMAD.IADD R0, R5, 0x1, -R4 ; ISETP.GE.AND P1, PT, R5, 0x1, PT ; BSSY B1, 0xa50 ; CS2R R38, SRZ ; CS2R R18, SRZ ; @!P1 BRA 0xa40 ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; BSSY B2, 0x960 ; IMAD R9, R5, R3, R6 ; CS2R R18, SRZ ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; @!P0 BRA 0x950 ; ISETP.GT.AND P0, PT, R0, RZ, PT ; IMAD.MOV.U32 R14, RZ, RZ, 0x8 ; BSSY B3, 0x850 ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; CS2R R18, SRZ ; IMAD.MOV.U32 R11, RZ, RZ, R0 ; IMAD.WIDE R14, R9, R14, c[0x0][0x160] ; @!P0 BRA 0x840 ; ISETP.GT.AND P2, PT, R11, 0xc, PT ; BSSY B4, 0x660 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0x650 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E.64 R30, [R14.64] ; LDG.E.64 R32, [R14.64+0x8] ; LDG.E.64 R20, [R14.64+0x10] ; LDG.E.64 R28, [R14.64+0x18] ; LDG.E.64 R26, [R14.64+0x20] ; LDG.E.64 R24, [R14.64+0x28] ; LDG.E.64 R22, [R14.64+0x30] ; DADD R18, R30, R18 ; LDG.E.64 R30, [R14.64+0x38] ; DADD R18, R18, R32 ; LDG.E.64 R32, [R14.64+0x40] ; DADD R18, R18, R20 ; LDG.E.64 R20, [R14.64+0x48] ; DADD R18, R18, R28 ; LDG.E.64 R28, [R14.64+0x50] ; DADD R18, R18, R26 ; LDG.E.64 R26, [R14.64+0x58] ; DADD R18, R18, R24 ; LDG.E.64 R24, [R14.64+0x60] ; DADD R18, R18, R22 ; LDG.E.64 R22, [R14.64+0x68] ; DADD R30, R18, R30 ; LDG.E.64 R18, [R14.64+0x70] ; DADD R32, R30, R32 ; LDG.E.64 R30, [R14.64+0x78] ; IADD3 R11, R11, -0x10, RZ ; DADD R20, R32, R20 ; IADD3 R13, P3, R14, 0x80, RZ ; ISETP.GT.AND P2, PT, R11, 0xc, PT ; IADD3 R12, R12, 0x10, RZ ; DADD R20, R20, R28 ; IMAD.X R15, RZ, RZ, R15, P3 ; IMAD.MOV.U32 R14, RZ, RZ, R13 ; DADD R20, R20, R26 ; DADD R20, R20, R24 ; DADD R20, R20, R22 ; DADD R18, R20, R18 ; DADD R18, R18, R30 ; @P2 BRA 0x3e0 ; BSYNC B4 ; ISETP.GT.AND P2, PT, R11, 0x4, PT ; BSSY B4, 0x810 ; @!P2 BRA 0x800 ; LDG.E.64 R32, [R14.64] ; LDG.E.64 R20, [R14.64+0x8] ; LDG.E.64 R30, [R14.64+0x10] ; LDG.E.64 R28, [R14.64+0x18] ; LDG.E.64 R26, [R14.64+0x20] ; LDG.E.64 R24, [R14.64+0x28] ; LDG.E.64 R22, [R14.64+0x30] ; DADD R32, R18, R32 ; LDG.E.64 R18, [R14.64+0x38] ; IADD3 R13, P2, R14, 0x40, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; DADD R20, R32, R20 ; IADD3 R12, R12, 0x8, RZ ; IADD3 R11, R11, -0x8, RZ ; DADD R20, R20, R30 ; IMAD.MOV.U32 R14, RZ, RZ, R13 ; DADD R20, R20, R28 ; DADD R20, R20, R26 ; DADD R20, R20, R24 ; DADD R20, R20, R22 ; DADD R18, R20, R18 ; IMAD.X R20, RZ, RZ, R15, P2 ; MOV R15, R20 ; BSYNC B4 ; ISETP.NE.OR P0, PT, R11, RZ, P0 ; @!P0 BREAK B3 ; @!P0 BRA 0x950 ; BSYNC B3 ; LDG.E.64 R22, [R14.64] ; LDG.E.64 R24, [R14.64+0x8] ; LDG.E.64 R26, [R14.64+0x10] ; LDG.E.64 R20, [R14.64+0x18] ; IADD3 R11, R11, -0x4, RZ ; IADD3 R13, P2, R14, 0x20, RZ ; ISETP.NE.AND P0, PT, R11, RZ, PT ; IADD3 R12, R12, 0x4, RZ ; IMAD.MOV.U32 R14, RZ, RZ, R13 ; DADD R22, R22, R18 ; DADD R22, R22, R24 ; DADD R22, R22, R26 ; DADD R18, R22, R20 ; IMAD.X R20, RZ, RZ, R15, P2 ; IMAD.MOV.U32 R15, RZ, RZ, R20 ; @P0 BRA 0x850 ; BSYNC B2 ; ISETP.NE.AND P0, PT, R4, RZ, PT ; @!P0 BRA 0xa40 ; IMAD.IADD R20, R9, 0x1, R12 ; IMAD.MOV.U32 R21, RZ, RZ, 0x8 ; IMAD.WIDE R20, R20, R21, c[0x0][0x160] ; LDG.E.64 R12, [R20.64] ; ISETP.NE.AND P0, PT, R4, 0x1, PT ; DADD R18, R18, R12 ; @!P0 BRA 0xa40 ; ISETP.NE.AND P0, PT, R4, 0x2, PT ; LDG.E.64 R12, [R20.64+0x8] ; @P0 LDG.E.64 R14, [R20.64+0x10] ; DADD R18, R18, R12 ; @P0 DADD R18, R18, R14 ; BSYNC B1 ; MUFU.RCP64H R13, R17 ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; FSETP.GEU.AND P2, PT, |R19|, 6.5827683646048100446e-37, PT ; IMAD.MOV.U32 R32, RZ, RZ, 0x8 ; BSSY B2, 0xbf0 ; DFMA R14, -R16, R12, 1 ; DFMA R14, R14, R14, R14 ; DFMA R14, R12, R14, R12 ; DFMA R12, -R16, R14, 1 ; DFMA R12, R14, R12, R14 ; DMUL R14, R12, R18 ; DFMA R20, -R16, R14, R18 ; DFMA R14, R12, R20, R14 ; IMAD.IADD R13, R8, 0x1, R3 ; IMAD.WIDE R32, R13, R32, c[0x0][0x170] ; SHF.R.S32.HI R34, RZ, 0x1f, R13 ; FFMA R9, RZ, R17, R15 ; FSETP.GT.AND P0, PT, |R9|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0xbe0 ; IMAD.MOV.U32 R22, RZ, RZ, R16 ; MOV R12, 0xbc0 ; IMAD.MOV.U32 R23, RZ, RZ, R17 ; CALL.REL.NOINC 0x26c0 ; IMAD.MOV.U32 R14, RZ, RZ, R20 ; MOV R15, R21 ; BSYNC B2 ; STG.E.64 [R32.64], R14 ; BSSY B1, 0x15f0 ; @!P1 BRA 0x15e0 ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; BSSY B2, 0x14d0 ; IMAD R12, R5, R3, R6 ; CS2R R38, SRZ ; IMAD.MOV.U32 R9, RZ, RZ, RZ ; @!P0 BRA 0x14c0 ; ISETP.GT.AND P0, PT, R0, RZ, PT ; BSSY B3, 0x1390 ; IMAD.MOV.U32 R9, RZ, RZ, RZ ; CS2R R38, SRZ ; IMAD.MOV.U32 R11, RZ, RZ, R0 ; @!P0 BRA 0x1380 ; ISETP.GT.AND P2, PT, R11, 0xc, PT ; BSSY B4, 0x1110 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0x1100 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.IADD R33, R12, 0x1, R9 ; IMAD.MOV.U32 R36, RZ, RZ, 0x8 ; IMAD.WIDE R32, R33, R36, c[0x0][0x160] ; LDG.E.64 R20, [R32.64] ; LDG.E.64 R18, [R32.64+0x8] ; LDG.E.64 R28, [R32.64+0x10] ; LDG.E.64 R22, [R32.64+0x18] ; IADD3 R31, R12, 0x4, R9 ; IMAD.WIDE R30, R31, R36, c[0x0][0x160] ; LDG.E.64 R26, [R30.64] ; LDG.E.64 R24, [R30.64+0x8] ; DADD R20, R20, -R14 ; DADD R18, R18, -R14 ; DFMA R20, R20, R20, R38 ; DFMA R20, R18, R18, R20 ; LDG.E.64 R18, [R30.64+0x10] ; DADD R28, R28, -R14 ; IADD3 R39, R12, 0x8, R9 ; DFMA R28, R28, R28, R20 ; LDG.E.64 R20, [R30.64+0x18] ; DADD R22, R22, -R14 ; IMAD.WIDE R38, R39, R36, c[0x0][0x160] ; DFMA R28, R22, R22, R28 ; LDG.E.64 R30, [R38.64+0x8] ; LDG.E.64 R22, [R38.64] ; DADD R26, R26, -R14 ; DADD R24, R24, -R14 ; DFMA R28, R26, R26, R28 ; DFMA R32, R24, R24, R28 ; IADD3 R37, R12, 0xc, R9 ; IMAD.WIDE R36, R37, R36, c[0x0][0x160] ; LDG.E.64 R26, [R36.64+0x10] ; LDG.E.64 R28, [R36.64+0x18] ; DADD R18, R18, -R14 ; DFMA R32, R18, R18, R32 ; DADD R20, R20, -R14 ; LDG.E.64 R18, [R38.64+0x10] ; DFMA R32, R20, R20, R32 ; LDG.E.64 R20, [R38.64+0x18] ; DADD R24, R22, -R14 ; LDG.E.64 R22, [R36.64] ; DFMA R32, R24, R24, R32 ; LDG.E.64 R24, [R36.64+0x8] ; DADD R30, R30, -R14 ; DFMA R32, R30, R30, R32 ; IADD3 R11, R11, -0x10, RZ ; ISETP.GT.AND P2, PT, R11, 0xc, PT ; DADD R26, R26, -R14 ; DADD R28, R28, -R14 ; IADD3 R9, R9, 0x10, RZ ; DADD R18, R18, -R14 ; DFMA R32, R18, R18, R32 ; DADD R20, R20, -R14 ; DADD R22, R22, -R14 ; DFMA R32, R20, R20, R32 ; DADD R24, R24, -R14 ; DFMA R32, R22, R22, R32 ; DFMA R32, R24, R24, R32 ; DFMA R32, R26, R26, R32 ; DFMA R38, R28, R28, R32 ; @P2 BRA 0xd30 ; BSYNC B4 ; ISETP.GT.AND P2, PT, R11, 0x4, PT ; BSSY B4, 0x1350 ; @!P2 BRA 0x1340 ; IMAD.IADD R36, R12, 0x1, R9 ; IMAD.MOV.U32 R21, RZ, RZ, 0x8 ; IMAD.WIDE R36, R36, R21, c[0x0][0x160] ; LDG.E.64 R28, [R36.64] ; LDG.E.64 R18, [R36.64+0x8] ; IADD3 R20, R12, 0x4, R9 ; LDG.E.64 R26, [R36.64+0x10] ; IMAD.WIDE R20, R20, R21, c[0x0][0x160] ; LDG.E.64 R24, [R36.64+0x18] ; LDG.E.64 R22, [R20.64] ; LDG.E.64 R30, [R20.64+0x10] ; LDG.E.64 R32, [R20.64+0x18] ; DADD R28, R28, -R14 ; DFMA R38, R28, R28, R38 ; LDG.E.64 R28, [R20.64+0x8] ; DADD R18, R18, -R14 ; DADD R26, R26, -R14 ; DFMA R38, R18, R18, R38 ; DADD R24, R24, -R14 ; DFMA R38, R26, R26, R38 ; DADD R22, R22, -R14 ; DFMA R38, R24, R24, R38 ; DFMA R38, R22, R22, R38 ; DADD R30, R30, -R14 ; DADD R32, R32, -R14.reuse ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R11, R11, -0x8, RZ ; IADD3 R9, R9, 0x8, RZ ; DADD R28, R28, -R14 ; DFMA R38, R28, R28, R38 ; DFMA R38, R30, R30, R38 ; DFMA R38, R32, R32, R38 ; BSYNC B4 ; ISETP.NE.OR P0, PT, R11, RZ, P0 ; @!P0 BREAK B3 ; @!P0 BRA 0x14c0 ; BSYNC B3 ; IMAD.IADD R26, R12, 0x1, R9 ; IMAD.MOV.U32 R27, RZ, RZ, 0x8 ; IMAD.WIDE R26, R26, R27, c[0x0][0x160] ; LDG.E.64 R24, [R26.64] ; LDG.E.64 R22, [R26.64+0x8] ; LDG.E.64 R20, [R26.64+0x10] ; LDG.E.64 R18, [R26.64+0x18] ; IADD3 R11, R11, -0x4, RZ ; IADD3 R9, R9, 0x4, RZ ; ISETP.NE.AND P0, PT, R11, RZ, PT ; DADD R24, R24, -R14 ; DADD R22, R22, -R14 ; DFMA R24, R24, R24, R38 ; DADD R20, R20, -R14 ; DFMA R24, R22, R22, R24 ; DADD R18, R18, -R14 ; DFMA R24, R20, R20, R24 ; DFMA R38, R18, R18, R24 ; @P0 BRA 0x1390 ; BSYNC B2 ; ISETP.NE.AND P0, PT, R4, RZ, PT ; @!P0 BRA 0x15e0 ; IMAD.IADD R22, R12, 0x1, R9 ; IMAD.MOV.U32 R23, RZ, RZ, 0x8 ; IMAD.WIDE R22, R22, R23, c[0x0][0x160] ; LDG.E.64 R18, [R22.64] ; ISETP.NE.AND P0, PT, R4, 0x1, PT ; DADD R18, R18, -R14 ; DFMA R38, R18, R18, R38 ; @!P0 BRA 0x15e0 ; ISETP.NE.AND P0, PT, R4, 0x2, PT ; LDG.E.64 R18, [R22.64+0x8] ; @P0 LDG.E.64 R20, [R22.64+0x10] ; DADD R18, R18, -R14 ; DFMA R38, R18, R18, R38 ; @P0 DADD R20, R20, -R14 ; @P0 DFMA R38, R20, R20, R38 ; BSYNC B1 ; MUFU.RCP64H R19, R17 ; MOV R18, 0x1 ; BSSY B2, 0x1770 ; FSETP.GEU.AND P2, PT, |R39|, 6.5827683646048100446e-37, PT ; DFMA R20, -R16, R18, 1 ; DFMA R20, R20, R20, R20 ; DFMA R20, R18, R20, R18 ; DFMA R18, -R16, R20, 1 ; DFMA R22, R20, R18, R20 ; DMUL R18, R22, R38 ; DFMA R20, -R16, R18, R38 ; DFMA R18, R22, R20, R18 ; FFMA R9, RZ, R17, R19 ; FSETP.GT.AND P0, PT, |R9|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x1760 ; IMAD.MOV.U32 R18, RZ, RZ, R38 ; MOV R12, 0x1740 ; IMAD.MOV.U32 R19, RZ, RZ, R39 ; IMAD.MOV.U32 R22, RZ, RZ, R16 ; IMAD.MOV.U32 R23, RZ, RZ, R17 ; CALL.REL.NOINC 0x26c0 ; IMAD.MOV.U32 R18, RZ, RZ, R20 ; IMAD.MOV.U32 R19, RZ, RZ, R21 ; BSYNC B2 ; MUFU.RSQ64H R21, R19 ; IADD3 R20, R19, -0x3500000, RZ ; IMAD.MOV.U32 R28, RZ, RZ, 0x0 ; BSSY B1, 0x18b0 ; IMAD.MOV.U32 R29, RZ, RZ, 0x3fd80000 ; ISETP.GE.U32.AND P0, PT, R20, 0x7ca00000, PT ; DMUL R22, R20, R20 ; DFMA R22, -R22, R18, 1 ; DFMA R28, R22, R28, 0.5 ; DMUL R22, R20, R22 ; DFMA R28, R28, R22, R20 ; DMUL R22, R28, R18 ; IADD3 R27, R29, -0x100000, RZ ; IMAD.MOV.U32 R26, RZ, RZ, R28 ; DFMA R24, R22, -R22, R18 ; DFMA R32, R24, R26, R22 ; @!P0 BRA 0x18a0 ; MOV R12, 0x18a0 ; CALL.REL.NOINC 0x2ca0 ; BSYNC B1 ; LEA R12, P0, R13.reuse, c[0x0][0x168], 0x3 ; BSSY B2, 0x25c0 ; LEA.HI.X R13, R13, c[0x0][0x16c], R34, 0x3, P0 ; STG.E.64 [R12.64], R32 ; @!P1 BRA 0x25b0 ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; BSSY B3, 0x2030 ; IMAD R13, R5, R3, R6 ; IMAD.MOV.U32 R38, RZ, RZ, RZ ; @!P0 BRA 0x2020 ; IMAD.MOV.U32 R38, RZ, RZ, RZ ; MOV R37, R0 ; IMAD.IADD R34, R13, 0x1, R38 ; IMAD.MOV.U32 R35, RZ, RZ, 0x8 ; IMAD.WIDE R34, R34, R35, c[0x0][0x160] ; LDG.E.64 R18, [R34.64] ; MUFU.RCP64H R21, R33 ; IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; IADD3 R37, R37, -0x4, RZ ; BSSY B4, 0x1b20 ; ISETP.NE.AND P1, PT, R37, RZ, PT ; DFMA R22, R20, -R32, 1 ; DFMA R22, R22, R22, R22 ; DFMA R22, R20, R22, R20 ; DFMA R20, R22, -R32, 1 ; DFMA R20, R22, R20, R22 ; DADD R18, R18, -R14 ; DMUL R22, R18, R20 ; FSETP.GEU.AND P2, PT, |R19|, 6.5827683646048100446e-37, PT ; DFMA R24, R22, -R32, R18 ; DFMA R20, R20, R24, R22 ; FFMA R9, RZ, R33, R21 ; FSETP.GT.AND P0, PT, |R9|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x1b10 ; IMAD.MOV.U32 R22, RZ, RZ, R32 ; MOV R12, 0x1b10 ; IMAD.MOV.U32 R23, RZ, RZ, R33 ; CALL.REL.NOINC 0x26c0 ; BSYNC B4 ; LDG.E.64 R22, [R34.64+0x8] ; MUFU.RCP64H R19, R33 ; IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; BSSY B4, 0x1cd0 ; STG.E.64 [R34.64], R20 ; DFMA R24, R18, -R32, 1 ; DFMA R24, R24, R24, R24 ; DFMA R24, R18, R24, R18 ; DFMA R18, R24, -R32, 1 ; DFMA R26, R24, R18, R24 ; DADD R22, R22, -R14 ; DMUL R18, R26, R22 ; FSETP.GEU.AND P2, PT, |R23|, 6.5827683646048100446e-37, PT ; DFMA R24, R18, -R32, R22 ; DFMA R18, R26, R24, R18 ; FFMA R9, RZ, R33, R19 ; FSETP.GT.AND P0, PT, |R9|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x1cc0 ; IMAD.MOV.U32 R18, RZ, RZ, R22 ; MOV R12, 0x1ca0 ; IMAD.MOV.U32 R19, RZ, RZ, R23 ; IMAD.MOV.U32 R22, RZ, RZ, R32 ; IMAD.MOV.U32 R23, RZ, RZ, R33 ; CALL.REL.NOINC 0x26c0 ; IMAD.MOV.U32 R18, RZ, RZ, R20 ; MOV R19, R21 ; BSYNC B4 ; LDG.E.64 R22, [R34.64+0x10] ; MUFU.RCP64H R21, R33 ; IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; BSSY B4, 0x1e60 ; STG.E.64 [R34.64+0x8], R18 ; DFMA R24, R20, -R32, 1 ; DFMA R24, R24, R24, R24 ; DFMA R24, R20, R24, R20 ; DFMA R20, R24, -R32, 1 ; DFMA R26, R24, R20, R24 ; DADD R22, R22, -R14 ; DMUL R20, R26, R22 ; FSETP.GEU.AND P2, PT, |R23|, 6.5827683646048100446e-37, PT ; DFMA R24, R20, -R32, R22 ; DFMA R20, R26, R24, R20 ; FFMA R9, RZ, R33, R21 ; FSETP.GT.AND P0, PT, |R9|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x1e50 ; IMAD.MOV.U32 R18, RZ, RZ, R22 ; MOV R12, 0x1e50 ; IMAD.MOV.U32 R19, RZ, RZ, R23 ; IMAD.MOV.U32 R22, RZ, RZ, R32 ; IMAD.MOV.U32 R23, RZ, RZ, R33 ; CALL.REL.NOINC 0x26c0 ; BSYNC B4 ; LDG.E.64 R18, [R34.64+0x18] ; MUFU.RCP64H R23, R33 ; IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; BSSY B4, 0x1ff0 ; STG.E.64 [R34.64+0x10], R20 ; DFMA R24, R22, -R32, 1 ; DFMA R24, R24, R24, R24 ; DFMA R24, R22, R24, R22 ; DFMA R22, R24, -R32, 1 ; DFMA R26, R24, R22, R24 ; DADD R18, R18, -R14 ; DMUL R22, R26, R18 ; FSETP.GEU.AND P2, PT, |R19|, 6.5827683646048100446e-37, PT ; DFMA R24, R22, -R32, R18 ; DFMA R22, R26, R24, R22 ; FFMA R9, RZ, R33, R23 ; FSETP.GT.AND P0, PT, |R9|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x1fe0 ; IMAD.MOV.U32 R22, RZ, RZ, R32 ; MOV R12, 0x1fc0 ; IMAD.MOV.U32 R23, RZ, RZ, R33 ; CALL.REL.NOINC 0x26c0 ; IMAD.MOV.U32 R22, RZ, RZ, R20 ; IMAD.MOV.U32 R23, RZ, RZ, R21 ; BSYNC B4 ; STG.E.64 [R34.64+0x18], R22 ; IADD3 R38, R38, 0x4, RZ ; @P1 BRA 0x1970 ; BSYNC B3 ; ISETP.NE.AND P0, PT, R4, RZ, PT ; @!P0 BRA 0x25b0 ; MOV R35, 0x8 ; IMAD.IADD R34, R13, 0x1, R38 ; IMAD.WIDE R34, R34, R35, c[0x0][0x160] ; LDG.E.64 R12, [R34.64] ; MUFU.RCP64H R19, R33 ; IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; BSSY B3, 0x2230 ; ISETP.NE.AND P1, PT, R4, 0x1, PT ; DFMA R20, R18, -R32, 1 ; DFMA R20, R20, R20, R20 ; DFMA R18, R18, R20, R18 ; DFMA R22, R18, -R32, 1 ; DFMA R22, R18, R22, R18 ; DADD R20, R12, -R14 ; DMUL R12, R22, R20 ; FSETP.GEU.AND P2, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R18, R12, -R32, R20 ; DFMA R12, R22, R18, R12 ; FFMA R9, RZ, R33, R13 ; FSETP.GT.AND P0, PT, |R9|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x2220 ; IMAD.MOV.U32 R18, RZ, RZ, R20 ; MOV R12, 0x2200 ; IMAD.MOV.U32 R19, RZ, RZ, R21 ; IMAD.MOV.U32 R22, RZ, RZ, R32 ; IMAD.MOV.U32 R23, RZ, RZ, R33 ; CALL.REL.NOINC 0x26c0 ; IMAD.MOV.U32 R12, RZ, RZ, R20 ; IMAD.MOV.U32 R13, RZ, RZ, R21 ; BSYNC B3 ; STG.E.64 [R34.64], R12 ; @!P1 BRA 0x25b0 ; LDG.E.64 R12, [R34.64+0x8] ; MUFU.RCP64H R19, R33 ; IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; BSSY B3, 0x2400 ; ISETP.NE.AND P1, PT, R4, 0x2, PT ; DFMA R20, R18, -R32, 1 ; DFMA R20, R20, R20, R20 ; DFMA R18, R18, R20, R18 ; DFMA R22, R18, -R32, 1 ; DFMA R22, R18, R22, R18 ; DADD R20, R12, -R14 ; DMUL R12, R22, R20 ; FSETP.GEU.AND P2, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R18, R12, -R32, R20 ; DFMA R12, R22, R18, R12 ; FFMA R9, RZ, R33, R13 ; FSETP.GT.AND P0, PT, |R9|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x23f0 ; IMAD.MOV.U32 R18, RZ, RZ, R20 ; MOV R23, R33 ; IMAD.MOV.U32 R19, RZ, RZ, R21 ; MOV R12, 0x23d0 ; IMAD.MOV.U32 R22, RZ, RZ, R32 ; CALL.REL.NOINC 0x26c0 ; IMAD.MOV.U32 R12, RZ, RZ, R20 ; IMAD.MOV.U32 R13, RZ, RZ, R21 ; BSYNC B3 ; STG.E.64 [R34.64+0x8], R12 ; @!P1 BRA 0x25b0 ; LDG.E.64 R12, [R34.64+0x10] ; MUFU.RCP64H R19, R33 ; IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; BSSY B3, 0x25a0 ; DFMA R20, R18, -R32, 1 ; DFMA R20, R20, R20, R20 ; DFMA R20, R18, R20, R18 ; DFMA R22, R20, -R32, 1 ; DFMA R22, R20, R22, R20 ; DADD R18, R12, -R14 ; DMUL R12, R22, R18 ; FSETP.GEU.AND P1, PT, |R19|, 6.5827683646048100446e-37, PT ; DFMA R14, R12, -R32, R18 ; DFMA R12, R22, R14, R12 ; FFMA R9, RZ, R33, R13 ; FSETP.GT.AND P0, PT, |R9|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2590 ; IMAD.MOV.U32 R22, RZ, RZ, R32 ; MOV R12, 0x2570 ; IMAD.MOV.U32 R23, RZ, RZ, R33 ; CALL.REL.NOINC 0x26c0 ; IMAD.MOV.U32 R12, RZ, RZ, R20 ; IMAD.MOV.U32 R13, RZ, RZ, R21 ; BSYNC B3 ; STG.E.64 [R34.64+0x10], R12 ; BSYNC B2 ; IADD3 R3, R3, 0x1, RZ ; ISETP.GE.AND P0, PT, R3, R10, PT ; @P0 CALL.REL.NOINC 0x2600 ; BRA 0x260 ; BSYNC B0 ; WARPSYNC 0xffffffff ; ISETP.NE.AND P0, PT, R7, 0x1, PT ; @P0 EXIT ; IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x3ff00000 ; IMAD.WIDE R2, R8, R9, c[0x0][0x168] ; IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; STG.E.64 [R2.64], R4 ; STG.E.64 [R8.64], R4 ; EXIT ; FSETP.GEU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R28, RZ, RZ, 0x1 ; FSETP.GEU.AND P2, PT, |R23|.reuse, 1.469367938527859385e-39, PT ; BSSY B1, 0x2c50 ; LOP3.LUT R20, R23, 0x800fffff, RZ, 0xc0, !PT ; LOP3.LUT R9, R19, 0x7ff00000, RZ, 0xc0, !PT ; LOP3.LUT R21, R20, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R20, RZ, RZ, R22 ; LOP3.LUT R36, R23.reuse, 0x7ff00000, RZ, 0xc0, !PT ; MOV R11, 0x1ca00000 ; @!P0 IMAD.MOV.U32 R26, RZ, RZ, RZ ; @!P0 LOP3.LUT R24, R23, 0x7ff00000, RZ, 0xc0, !PT ; @!P2 DMUL R20, R22, 8.98846567431157953865e+307 ; ISETP.GE.U32.AND P4, PT, R9, R36, PT ; @!P0 ISETP.GE.U32.AND P3, PT, R9, R24, PT ; IMAD.MOV.U32 R24, RZ, RZ, R18 ; SEL R25, R11.reuse, 0x63400000, !P4 ; MUFU.RCP64H R29, R21 ; @!P0 SEL R27, R11, 0x63400000, !P3 ; LOP3.LUT R25, R25, 0x800fffff, R19.reuse, 0xf8, !PT ; @!P0 LOP3.LUT R27, R27, 0x80000000, R19, 0xf8, !PT ; @!P2 LOP3.LUT R36, R21, 0x7ff00000, RZ, 0xc0, !PT ; @!P0 LOP3.LUT R27, R27, 0x100000, RZ, 0xfc, !PT ; @!P0 DFMA R24, R24, 2, -R26 ; DFMA R26, R28, -R20, 1 ; DFMA R26, R26, R26, R26 ; DFMA R26, R28, R26, R28 ; DFMA R28, R26, -R20, 1 ; DFMA R26, R26, R28, R26 ; DMUL R28, R26, R24 ; DFMA R30, R28, -R20, R24 ; DFMA R30, R26, R30, R28 ; IMAD.MOV.U32 R28, RZ, RZ, R9 ; @!P0 LOP3.LUT R28, R25, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R26, R28, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R26, 0x7feffffe, PT ; IADD3 R26, R36, -0x1, RZ ; ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; @P0 BRA 0x2af0 ; LOP3.LUT R26, R23, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R9.reuse, R26, PT ; IMAD.IADD R18, R9, 0x1, -R26 ; SEL R26, R11, 0x63400000, !P0 ; IMNMX R18, R18, -0x46a00000, !PT ; IMNMX R9, R18, 0x46a00000, PT ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; IMAD.IADD R9, R9, 0x1, -R26 ; IADD3 R19, R9, 0x7fe00000, RZ ; DMUL R26, R30, R18 ; FSETP.GTU.AND P0, PT, |R27|, 1.469367938527859385e-39, PT ; @P0 BRA 0x2c40 ; DFMA R20, R30, -R20, R24 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R21.reuse, RZ, PT ; LOP3.LUT R23, R21, 0x80000000, R23, 0x48, !PT ; LOP3.LUT R21, R23, R19, RZ, 0xfc, !PT ; @!P0 BRA 0x2c40 ; IMAD.MOV R19, RZ, RZ, -R9 ; DMUL.RP R20, R30, R20 ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; IADD3 R9, -R9, -0x43300000, RZ ; DFMA R18, R26, -R18, R30 ; LOP3.LUT R23, R21, R23, RZ, 0x3c, !PT ; FSETP.NEU.AND P0, PT, |R19|, R9, PT ; FSEL R26, R20, R26, !P0 ; FSEL R27, R23, R27, !P0 ; BRA 0x2c40 ; DSETP.NAN.AND P0, PT, R18, R18, PT ; @P0 BRA 0x2c20 ; DSETP.NAN.AND P0, PT, R22, R22, PT ; @P0 BRA 0x2bf0 ; ISETP.NE.AND P0, PT, R28, R36, PT ; IMAD.MOV.U32 R26, RZ, RZ, 0x0 ; MOV R27, 0xfff80000 ; @!P0 BRA 0x2c40 ; ISETP.NE.AND P0, PT, R28, 0x7ff00000, PT ; LOP3.LUT R27, R19, 0x80000000, R23, 0x48, !PT ; ISETP.EQ.OR P0, PT, R36, RZ, !P0 ; @P0 LOP3.LUT R9, R27, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R26, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R26, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R27, RZ, RZ, R9 ; BRA 0x2c40 ; LOP3.LUT R27, R23, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R26, RZ, RZ, R22 ; BRA 0x2c40 ; LOP3.LUT R27, R19, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R26, RZ, RZ, R18 ; BSYNC B1 ; IMAD.MOV.U32 R18, RZ, RZ, R12 ; IMAD.MOV.U32 R19, RZ, RZ, 0x0 ; IMAD.MOV.U32 R20, RZ, RZ, R26 ; IMAD.MOV.U32 R21, RZ, RZ, R27 ; RET.REL.NODEC R18 0x0 ; ISETP.GE.U32.AND P0, PT, R20, -0x3400000, PT ; BSSY B2, 0x2f20 ; IMAD.MOV.U32 R26, RZ, RZ, R28 ; MOV R21, R25 ; IMAD.MOV.U32 R20, RZ, RZ, R24 ; @!P0 BRA 0x2d80 ; DFMA.RM R20, R20, R26, R22 ; IADD3 R22, P0, R20, 0x1, RZ ; IMAD.X R23, RZ, RZ, R21, P0 ; DFMA.RP R18, -R20, R22, R18 ; DSETP.GT.AND P0, PT, R18, RZ, PT ; FSEL R20, R22, R20, P0 ; FSEL R21, R23, R21, P0 ; BRA 0x2f10 ; DSETP.NE.AND P0, PT, R18, RZ, PT ; @!P0 BRA 0x2f00 ; ISETP.GE.AND P0, PT, R19, RZ, PT ; @!P0 IMAD.MOV.U32 R20, RZ, RZ, 0x0 ; @!P0 IMAD.MOV.U32 R21, RZ, RZ, -0x80000 ; @!P0 BRA 0x2f10 ; ISETP.GT.AND P0, PT, R19, 0x7fefffff, PT ; @P0 BRA 0x2f00 ; DMUL R18, R18, 8.11296384146066816958e+31 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; IMAD.MOV.U32 R24, RZ, RZ, 0x0 ; IMAD.MOV.U32 R25, RZ, RZ, 0x3fd80000 ; MUFU.RSQ64H R21, R19 ; DMUL R22, R20, R20 ; DFMA R22, R18, -R22, 1 ; DFMA R24, R22, R24, 0.5 ; DMUL R22, R20, R22 ; DFMA R22, R24, R22, R20 ; DMUL R20, R18, R22 ; IADD3 R23, R23, -0x100000, RZ ; DFMA R24, R20, -R20, R18 ; DFMA R20, R22, R24, R20 ; IADD3 R21, R21, -0x3500000, RZ ; BRA 0x2f10 ; DADD R20, R18, R18 ; BSYNC B2 ; IMAD.MOV.U32 R18, RZ, RZ, R12 ; IMAD.MOV.U32 R19, RZ, RZ, 0x0 ; IMAD.MOV.U32 R32, RZ, RZ, R20 ; IMAD.MOV.U32 R33, RZ, RZ, R21 ; RET.REL.NODEC R18 0x0 ; BRA 0x2f70; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z23predictor_normalizationPdS_S_S_S_S_S_iii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R12, SR_CTAID.X ; ULDC UR4, c[0x0][0x19c] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1a0] ; UIADD3 UR4, UR4, -0x1, URZ ; S2R R3, SR_TID.X ; ISETP.NE.AND P0, PT, R12, UR4, PT ; SEL R0, R0, c[0x0][0x198], !P0 ; ISETP.GE.AND P0, PT, R3, R0, PT ; @P0 EXIT ; IMAD.MOV.U32 R13, RZ, RZ, 0x8 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD R12, R12, c[0x0][0x198], R3 ; IMAD.WIDE R10, R12, R13, c[0x0][0x190] ; LDG.E.64 R14, [R10.64] ; IMAD.WIDE R8, R12, R13, c[0x0][0x188] ; LDG.E.64 R8, [R8.64] ; IMAD.WIDE R6, R12, R13, c[0x0][0x178] ; LDG.E.64 R4, [R6.64] ; BSSY B0, 0x1890 ; IMAD.WIDE R10, R12, R13, c[0x0][0x180] ; IMAD.WIDE R12, R12, R13, c[0x0][0x170] ; F2I.F64.TRUNC R2, R14 ; F2I.F64.TRUNC R3, R8 ; ISETP.NE.AND P0, PT, R2, 0x1, PT ; F2I.F64.TRUNC R4, R4 ; SEL R0, RZ, 0x1, P0 ; ISETP.GT.AND P0, PT, R3, R0, PT ; @!P0 BRA 0x1880 ; LDG.E.64 R10, [R10.64] ; LDG.E.64 R12, [R12.64] ; IMAD.MOV.U32 R7, RZ, RZ, R0 ; F2I.F64.TRUNC R5, R10 ; F2I.F64.TRUNC R6, R12 ; LOP3.LUT R8, R5, 0x3, RZ, 0xc0, !PT ; IADD3 R9, R5, -0x1, RZ ; IMAD.IADD R28, R5, 0x1, -R8 ; ISETP.GE.AND P1, PT, R5, 0x1, PT ; BSSY B1, 0xa10 ; CS2R R18, SRZ ; @!P1 BRA 0xa00 ; ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; BSSY B2, 0x920 ; IMAD R0, R5, R7, R6 ; CS2R R18, SRZ ; IMAD.MOV.U32 R29, RZ, RZ, RZ ; @!P0 BRA 0x910 ; ISETP.GT.AND P0, PT, R28, RZ, PT ; IMAD.MOV.U32 R33, RZ, RZ, 0x8 ; BSSY B3, 0x810 ; IMAD.MOV.U32 R29, RZ, RZ, RZ ; CS2R R18, SRZ ; IMAD.MOV.U32 R34, RZ, RZ, R28 ; IMAD.WIDE R32, R0, R33, c[0x0][0x160] ; @!P0 BRA 0x800 ; ISETP.GT.AND P2, PT, R34, 0xc, PT ; BSSY B4, 0x630 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0x620 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E.64 R20, [R32.64] ; LDG.E.64 R16, [R32.64+0x8] ; LDG.E.64 R14, [R32.64+0x10] ; LDG.E.64 R12, [R32.64+0x18] ; LDG.E.64 R10, [R32.64+0x20] ; LDG.E.64 R26, [R32.64+0x28] ; LDG.E.64 R30, [R32.64+0x30] ; LDG.E.64 R24, [R32.64+0x38] ; LDG.E.64 R22, [R32.64+0x40] ; DFMA R18, R20, R20, R18 ; LDG.E.64 R20, [R32.64+0x48] ; DFMA R16, R16, R16, R18 ; LDG.E.64 R18, [R32.64+0x50] ; DFMA R14, R14, R14, R16 ; LDG.E.64 R16, [R32.64+0x58] ; DFMA R12, R12, R12, R14 ; LDG.E.64 R14, [R32.64+0x60] ; DFMA R10, R10, R10, R12 ; LDG.E.64 R12, [R32.64+0x68] ; DFMA R26, R26, R26, R10 ; LDG.E.64 R10, [R32.64+0x70] ; DFMA R30, R30, R30, R26 ; LDG.E.64 R26, [R32.64+0x78] ; IADD3 R34, R34, -0x10, RZ ; DFMA R30, R24, R24, R30 ; IADD3 R29, R29, 0x10, RZ ; ISETP.GT.AND P2, PT, R34, 0xc, PT ; DFMA R30, R22, R22, R30 ; IADD3 R32, P3, R32, 0x80, RZ ; IMAD.X R33, RZ, RZ, R33, P3 ; DFMA R30, R20, R20, R30 ; DFMA R30, R18, R18, R30 ; DFMA R30, R16, R16, R30 ; DFMA R30, R14, R14, R30 ; DFMA R30, R12, R12, R30 ; DFMA R30, R10, R10, R30 ; DFMA R18, R26, R26, R30 ; @P2 BRA 0x3c0 ; BSYNC B4 ; ISETP.GT.AND P2, PT, R34, 0x4, PT ; BSSY B4, 0x7d0 ; @!P2 BRA 0x7c0 ; LDG.E.64 R26, [R32.64] ; LDG.E.64 R24, [R32.64+0x8] ; LDG.E.64 R22, [R32.64+0x10] ; LDG.E.64 R20, [R32.64+0x18] ; LDG.E.64 R10, [R32.64+0x20] ; LDG.E.64 R12, [R32.64+0x28] ; LDG.E.64 R14, [R32.64+0x30] ; LDG.E.64 R16, [R32.64+0x38] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R29, R29, 0x8, RZ ; IADD3 R34, R34, -0x8, RZ ; DFMA R18, R26, R26, R18 ; DFMA R18, R24, R24, R18 ; DFMA R18, R22, R22, R18 ; DFMA R18, R20, R20, R18 ; DFMA R18, R10, R10, R18 ; IADD3 R10, P2, R32, 0x40, RZ ; DFMA R18, R12, R12, R18 ; IMAD.X R33, RZ, RZ, R33, P2 ; IMAD.MOV.U32 R32, RZ, RZ, R10 ; DFMA R18, R14, R14, R18 ; DFMA R18, R16, R16, R18 ; BSYNC B4 ; ISETP.NE.OR P0, PT, R34, RZ, P0 ; @!P0 BREAK B3 ; @!P0 BRA 0x910 ; BSYNC B3 ; LDG.E.64 R16, [R32.64] ; LDG.E.64 R14, [R32.64+0x8] ; LDG.E.64 R12, [R32.64+0x10] ; LDG.E.64 R10, [R32.64+0x18] ; IADD3 R34, R34, -0x4, RZ ; IADD3 R29, R29, 0x4, RZ ; ISETP.NE.AND P0, PT, R34, RZ, PT ; DFMA R16, R16, R16, R18 ; DFMA R16, R14, R14, R16 ; DFMA R16, R12, R12, R16 ; IADD3 R12, P2, R32, 0x20, RZ ; DFMA R18, R10, R10, R16 ; IMAD.X R13, RZ, RZ, R33, P2 ; IMAD.MOV.U32 R32, RZ, RZ, R12 ; IMAD.MOV.U32 R33, RZ, RZ, R13 ; @P0 BRA 0x810 ; BSYNC B2 ; ISETP.NE.AND P0, PT, R8, RZ, PT ; @!P0 BRA 0xa00 ; IADD3 R14, R0, R29, RZ ; IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; LDG.E.64 R10, [R14.64] ; ISETP.NE.AND P0, PT, R8, 0x1, PT ; DFMA R18, R10, R10, R18 ; @!P0 BRA 0xa00 ; ISETP.NE.AND P0, PT, R8, 0x2, PT ; LDG.E.64 R10, [R14.64+0x8] ; @P0 LDG.E.64 R12, [R14.64+0x10] ; DFMA R18, R10, R10, R18 ; @P0 DFMA R18, R12, R12, R18 ; BSYNC B1 ; MUFU.RSQ64H R21, R19 ; IADD3 R20, R19, -0x3500000, RZ ; IMAD.MOV.U32 R24, RZ, RZ, 0x0 ; BSSY B1, 0xbc0 ; IMAD.MOV.U32 R25, RZ, RZ, 0x3fd80000 ; ISETP.GE.U32.AND P0, PT, R20, 0x7ca00000, PT ; IMAD.IADD R12, R4, 0x1, R7 ; IMAD.MOV.U32 R13, RZ, RZ, 0x8 ; IMAD.WIDE R12, R12, R13, c[0x0][0x168] ; DMUL R10, R20, R20 ; DFMA R10, -R10, R18, 1 ; DFMA R24, R10, R24, 0.5 ; DMUL R10, R20, R10 ; DFMA R24, R24, R10, R20 ; DMUL R14, R24, R18 ; IADD3 R23, R25, -0x100000, RZ ; IMAD.MOV.U32 R22, RZ, RZ, R24 ; DFMA R16, R14, -R14, R18 ; DFMA R10, R16, R22, R14 ; @!P0 BRA 0xbb0 ; IMAD.MOV.U32 R10, RZ, RZ, R18 ; MOV R0, 0xb90 ; IMAD.MOV.U32 R11, RZ, RZ, R19 ; CALL.REL.NOINC 0x1f00 ; IMAD.MOV.U32 R10, RZ, RZ, R14 ; IMAD.MOV.U32 R11, RZ, RZ, R15 ; BSYNC B1 ; STG.E.64 [R12.64], R10 ; BSSY B1, 0x1840 ; @!P1 BRA 0x1830 ; ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; BSSY B2, 0x1320 ; IMAD R29, R5, R7, R6 ; IMAD.MOV.U32 R30, RZ, RZ, RZ ; @!P0 BRA 0x1310 ; IMAD.MOV.U32 R30, RZ, RZ, RZ ; IMAD.MOV.U32 R31, RZ, RZ, R28 ; IADD3 R12, R29, R30, RZ ; IMAD.MOV.U32 R13, RZ, RZ, 0x8 ; IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; LDG.E.64 R14, [R12.64] ; MUFU.RCP64H R17, R11 ; IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; IADD3 R31, R31, -0x4, RZ ; BSSY B3, 0xe40 ; ISETP.NE.AND P1, PT, R31, RZ, PT ; DFMA R18, R16, -R10, 1 ; DFMA R18, R18, R18, R18 ; DFMA R18, R16, R18, R16 ; DFMA R16, R18, -R10, 1 ; DFMA R16, R18, R16, R18 ; DMUL R18, R14, R16 ; FSETP.GEU.AND P2, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R20, R18, -R10, R14 ; DFMA R18, R16, R20, R18 ; FFMA R0, RZ, R11, R19 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0xe30 ; IMAD.MOV.U32 R18, RZ, RZ, R14 ; MOV R0, 0xe10 ; IMAD.MOV.U32 R19, RZ, RZ, R15 ; IMAD.MOV.U32 R16, RZ, RZ, R10 ; IMAD.MOV.U32 R17, RZ, RZ, R11 ; CALL.REL.NOINC 0x1920 ; IMAD.MOV.U32 R18, RZ, RZ, R16 ; IMAD.MOV.U32 R19, RZ, RZ, R17 ; BSYNC B3 ; LDG.E.64 R14, [R12.64+0x8] ; MUFU.RCP64H R17, R11 ; IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; BSSY B3, 0xfc0 ; STG.E.64 [R12.64], R18 ; DFMA R20, R16, -R10, 1 ; DFMA R20, R20, R20, R20 ; DFMA R16, R16, R20, R16 ; DFMA R20, R16, -R10, 1 ; DFMA R16, R16, R20, R16 ; DMUL R22, R16, R14 ; FSETP.GEU.AND P2, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R20, R22, -R10, R14 ; DFMA R16, R16, R20, R22 ; FFMA R0, RZ, R11, R17 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0xfb0 ; IMAD.MOV.U32 R18, RZ, RZ, R14 ; MOV R0, 0xfb0 ; IMAD.MOV.U32 R19, RZ, RZ, R15 ; IMAD.MOV.U32 R16, RZ, RZ, R10 ; IMAD.MOV.U32 R17, RZ, RZ, R11 ; CALL.REL.NOINC 0x1920 ; BSYNC B3 ; LDG.E.64 R14, [R12.64+0x10] ; MUFU.RCP64H R19, R11 ; MOV R18, 0x1 ; BSSY B3, 0x1160 ; STG.E.64 [R12.64+0x8], R16 ; DFMA R20, R18, -R10, 1 ; DFMA R20, R20, R20, R20 ; DFMA R20, R18, R20, R18 ; DFMA R22, R20, -R10, 1 ; DFMA R22, R20, R22, R20 ; DMUL R20, R22, R14 ; FSETP.GEU.AND P2, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R18, R20, -R10, R14 ; DFMA R22, R22, R18, R20 ; FFMA R0, RZ, R11, R23 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x1150 ; IMAD.MOV.U32 R18, RZ, RZ, R14 ; MOV R0, 0x1130 ; IMAD.MOV.U32 R19, RZ, RZ, R15 ; IMAD.MOV.U32 R16, RZ, RZ, R10 ; IMAD.MOV.U32 R17, RZ, RZ, R11 ; CALL.REL.NOINC 0x1920 ; IMAD.MOV.U32 R22, RZ, RZ, R16 ; IMAD.MOV.U32 R23, RZ, RZ, R17 ; BSYNC B3 ; LDG.E.64 R14, [R12.64+0x18] ; MUFU.RCP64H R17, R11 ; IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; BSSY B3, 0x12e0 ; STG.E.64 [R12.64+0x10], R22 ; DFMA R18, R16, -R10, 1 ; DFMA R18, R18, R18, R18 ; DFMA R16, R16, R18, R16 ; DFMA R18, R16, -R10, 1 ; DFMA R16, R16, R18, R16 ; DMUL R18, R16, R14 ; FSETP.GEU.AND P2, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R20, R18, -R10, R14 ; DFMA R16, R16, R20, R18 ; FFMA R0, RZ, R11, R17 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x12d0 ; IMAD.MOV.U32 R18, RZ, RZ, R14 ; MOV R0, 0x12d0 ; IMAD.MOV.U32 R19, RZ, RZ, R15 ; IMAD.MOV.U32 R16, RZ, RZ, R10 ; IMAD.MOV.U32 R17, RZ, RZ, R11 ; CALL.REL.NOINC 0x1920 ; BSYNC B3 ; STG.E.64 [R12.64+0x18], R16 ; IADD3 R30, R30, 0x4, RZ ; @P1 BRA 0xc60 ; BSYNC B2 ; ISETP.NE.AND P0, PT, R8, RZ, PT ; @!P0 BRA 0x1830 ; MOV R13, 0x8 ; IMAD.IADD R12, R29, 0x1, R30 ; IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; LDG.E.64 R18, [R12.64] ; MUFU.RCP64H R15, R11 ; IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; BSSY B2, 0x14f0 ; ISETP.NE.AND P1, PT, R8, 0x1, PT ; DFMA R16, R14, -R10, 1 ; DFMA R16, R16, R16, R16 ; DFMA R16, R14, R16, R14 ; DFMA R14, R16, -R10, 1 ; DFMA R20, R16, R14, R16 ; DMUL R14, R20, R18 ; FSETP.GEU.AND P2, PT, |R19|, 6.5827683646048100446e-37, PT ; DFMA R16, R14, -R10, R18 ; DFMA R14, R20, R16, R14 ; FFMA R0, RZ, R11, R15 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x14e0 ; IMAD.MOV.U32 R16, RZ, RZ, R10 ; MOV R0, 0x14c0 ; IMAD.MOV.U32 R17, RZ, RZ, R11 ; CALL.REL.NOINC 0x1920 ; IMAD.MOV.U32 R14, RZ, RZ, R16 ; IMAD.MOV.U32 R15, RZ, RZ, R17 ; BSYNC B2 ; STG.E.64 [R12.64], R14 ; @!P1 BRA 0x1830 ; LDG.E.64 R18, [R12.64+0x8] ; MUFU.RCP64H R15, R11 ; IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; BSSY B2, 0x1690 ; ISETP.NE.AND P1, PT, R8, 0x2, PT ; DFMA R16, R14, -R10, 1 ; DFMA R16, R16, R16, R16 ; DFMA R16, R14, R16, R14 ; DFMA R14, R16, -R10, 1 ; DFMA R20, R16, R14, R16 ; DMUL R14, R20, R18 ; FSETP.GEU.AND P2, PT, |R19|, 6.5827683646048100446e-37, PT ; DFMA R16, R14, -R10, R18 ; DFMA R14, R20, R16, R14 ; FFMA R0, RZ, R11, R15 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x1680 ; IMAD.MOV.U32 R16, RZ, RZ, R10 ; MOV R0, 0x1660 ; IMAD.MOV.U32 R17, RZ, RZ, R11 ; CALL.REL.NOINC 0x1920 ; IMAD.MOV.U32 R14, RZ, RZ, R16 ; IMAD.MOV.U32 R15, RZ, RZ, R17 ; BSYNC B2 ; STG.E.64 [R12.64+0x8], R14 ; @!P1 BRA 0x1830 ; LDG.E.64 R18, [R12.64+0x10] ; MUFU.RCP64H R15, R11 ; IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; BSSY B2, 0x1820 ; DFMA R16, R14, -R10, 1 ; DFMA R16, R16, R16, R16 ; DFMA R16, R14, R16, R14 ; DFMA R14, R16, -R10, 1 ; DFMA R20, R16, R14, R16 ; DMUL R14, R20, R18 ; FSETP.GEU.AND P1, PT, |R19|, 6.5827683646048100446e-37, PT ; DFMA R16, R14, -R10, R18 ; DFMA R14, R20, R16, R14 ; FFMA R0, RZ, R11, R15 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1810 ; IMAD.MOV.U32 R16, RZ, RZ, R10 ; MOV R17, R11 ; MOV R0, 0x17f0 ; CALL.REL.NOINC 0x1920 ; IMAD.MOV.U32 R14, RZ, RZ, R16 ; IMAD.MOV.U32 R15, RZ, RZ, R17 ; BSYNC B2 ; STG.E.64 [R12.64+0x10], R14 ; BSYNC B1 ; IADD3 R7, R7, 0x1, RZ ; ISETP.GE.AND P0, PT, R7, R3, PT ; @P0 CALL.REL.NOINC 0x1880 ; BRA 0x250 ; BSYNC B0 ; WARPSYNC 0xffffffff ; ISETP.NE.AND P0, PT, R2, 0x1, PT ; @P0 EXIT ; IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; IMAD.MOV.U32 R3, RZ, RZ, 0x3ff00000 ; IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; STG.E.64 [R4.64], R2 ; EXIT ; FSETP.GEU.AND P0, PT, |R17|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R24, RZ, RZ, 0x1 ; LOP3.LUT R14, R17, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R33, RZ, RZ, 0x1ca00000 ; FSETP.GEU.AND P3, PT, |R19|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R20, RZ, RZ, R18 ; LOP3.LUT R15, R14, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R14, RZ, RZ, R16 ; LOP3.LUT R32, R19, 0x7ff00000, RZ, 0xc0, !PT ; BSSY B4, 0x1eb0 ; LOP3.LUT R35, R17, 0x7ff00000, RZ, 0xc0, !PT ; @!P0 DMUL R14, R16, 8.98846567431157953865e+307 ; ISETP.GE.U32.AND P2, PT, R32, R35, PT ; @!P3 LOP3.LUT R21, R17, 0x7ff00000, RZ, 0xc0, !PT ; @!P3 IMAD.MOV.U32 R26, RZ, RZ, RZ ; MUFU.RCP64H R25, R15 ; @!P3 ISETP.GE.U32.AND P4, PT, R32, R21, PT ; SEL R21, R33.reuse, 0x63400000, !P2 ; @!P3 SEL R27, R33, 0x63400000, !P4 ; LOP3.LUT R21, R21, 0x800fffff, R19, 0xf8, !PT ; @!P3 LOP3.LUT R27, R27, 0x80000000, R19, 0xf8, !PT ; @!P0 LOP3.LUT R35, R15, 0x7ff00000, RZ, 0xc0, !PT ; @!P3 LOP3.LUT R27, R27, 0x100000, RZ, 0xfc, !PT ; DFMA R22, R24, -R14, 1 ; @!P3 DFMA R20, R20, 2, -R26 ; DFMA R22, R22, R22, R22 ; DFMA R22, R24, R22, R24 ; DFMA R24, R22, -R14, 1 ; DFMA R22, R22, R24, R22 ; DMUL R24, R22, R20 ; DFMA R26, R24, -R14, R20 ; DFMA R26, R22, R26, R24 ; IMAD.MOV.U32 R24, RZ, RZ, R32 ; @!P3 LOP3.LUT R24, R21, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R22, R24, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ; IADD3 R22, R35, -0x1, RZ ; ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; @P0 BRA 0x1d50 ; LOP3.LUT R19, R17, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R32.reuse, R19, PT ; IMAD.IADD R18, R32, 0x1, -R19 ; SEL R33, R33, 0x63400000, !P0 ; IMNMX R18, R18, -0x46a00000, !PT ; IMNMX R18, R18, 0x46a00000, PT ; IADD3 R24, -R33, R18, RZ ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; IADD3 R19, R24, 0x7fe00000, RZ ; DMUL R22, R26, R18 ; FSETP.GTU.AND P0, PT, |R23|, 1.469367938527859385e-39, PT ; @P0 BRA 0x1ea0 ; DFMA R14, R26, -R14, R20 ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R15.reuse, RZ, PT ; LOP3.LUT R17, R15, 0x80000000, R17, 0x48, !PT ; LOP3.LUT R19, R17, R19, RZ, 0xfc, !PT ; @!P0 BRA 0x1ea0 ; IMAD.MOV R15, RZ, RZ, -R24 ; DMUL.RP R18, R26, R18 ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; DFMA R14, R22, -R14, R26 ; LOP3.LUT R17, R19, R17, RZ, 0x3c, !PT ; IADD3 R14, -R24, -0x43300000, RZ ; FSETP.NEU.AND P0, PT, |R15|, R14, PT ; FSEL R22, R18, R22, !P0 ; FSEL R23, R17, R23, !P0 ; BRA 0x1ea0 ; DSETP.NAN.AND P0, PT, R18, R18, PT ; @P0 BRA 0x1e80 ; DSETP.NAN.AND P0, PT, R16, R16, PT ; @P0 BRA 0x1e50 ; ISETP.NE.AND P0, PT, R24, R35, PT ; IMAD.MOV.U32 R22, RZ, RZ, 0x0 ; IMAD.MOV.U32 R23, RZ, RZ, -0x80000 ; @!P0 BRA 0x1ea0 ; ISETP.NE.AND P0, PT, R24, 0x7ff00000, PT ; LOP3.LUT R23, R19, 0x80000000, R17, 0x48, !PT ; ISETP.EQ.OR P0, PT, R35, RZ, !P0 ; @P0 LOP3.LUT R14, R23, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R22, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R22, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R23, RZ, RZ, R14 ; BRA 0x1ea0 ; LOP3.LUT R23, R17, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R22, RZ, RZ, R16 ; BRA 0x1ea0 ; LOP3.LUT R23, R19, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R22, RZ, RZ, R18 ; BSYNC B4 ; IMAD.MOV.U32 R14, RZ, RZ, R0 ; MOV R17, R23 ; IMAD.MOV.U32 R15, RZ, RZ, 0x0 ; IMAD.MOV.U32 R16, RZ, RZ, R22 ; RET.REL.NODEC R14 0x0 ; ISETP.GE.U32.AND P0, PT, R20, -0x3400000, PT ; BSSY B2, 0x2160 ; IMAD.MOV.U32 R22, RZ, RZ, R24 ; @!P0 BRA 0x1fc0 ; DFMA.RM R22, R16, R22, R14 ; IADD3 R14, P0, R22, 0x1, RZ ; IMAD.X R15, RZ, RZ, R23, P0 ; DFMA.RP R10, -R22, R14, R10 ; DSETP.GT.AND P0, PT, R10, RZ, PT ; FSEL R14, R14, R22, P0 ; FSEL R15, R15, R23, P0 ; BRA 0x2150 ; DSETP.NE.AND P0, PT, R10, RZ, PT ; @!P0 BRA 0x2140 ; ISETP.GE.AND P0, PT, R11, RZ, PT ; @!P0 IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; @!P0 IMAD.MOV.U32 R15, RZ, RZ, -0x80000 ; @!P0 BRA 0x2150 ; ISETP.GT.AND P0, PT, R11, 0x7fefffff, PT ; @P0 BRA 0x2140 ; DMUL R10, R10, 8.11296384146066816958e+31 ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; IMAD.MOV.U32 R19, RZ, RZ, 0x3fd80000 ; MUFU.RSQ64H R15, R11 ; DMUL R16, R14, R14 ; DFMA R16, R10, -R16, 1 ; DFMA R18, R16, R18, 0.5 ; DMUL R16, R14, R16 ; DFMA R16, R18, R16, R14 ; DMUL R14, R10, R16 ; IADD3 R17, R17, -0x100000, RZ ; DFMA R18, R14, -R14, R10 ; DFMA R14, R16, R18, R14 ; IADD3 R15, R15, -0x3500000, RZ ; BRA 0x2150 ; DADD R14, R10, R10 ; BSYNC B2 ; IMAD.MOV.U32 R10, RZ, RZ, R0 ; IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; RET.REL.NODEC R10 0x0 ; BRA 0x2190; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0001aadd_00000000-6_8b767290955cb5f6d829cc319289a569e00a29cf.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z58__device_stub__Z23predictor_normalizationPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii .type _Z58__device_stub__Z23predictor_normalizationPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii, @function _Z58__device_stub__Z23predictor_normalizationPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii: .LFB2051: .cfi_startproc endbr64 subq $232, %rsp .cfi_def_cfa_offset 240 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) movq %rdx, 40(%rsp) movq %rcx, 32(%rsp) movq %r8, 24(%rsp) movq %r9, 16(%rsp) movq 240(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 216(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) leaq 32(%rsp), %rax movq %rax, 152(%rsp) leaq 24(%rsp), %rax movq %rax, 160(%rsp) leaq 16(%rsp), %rax movq %rax, 168(%rsp) leaq 8(%rsp), %rax movq %rax, 176(%rsp) leaq 248(%rsp), %rax movq %rax, 184(%rsp) leaq 256(%rsp), %rax movq %rax, 192(%rsp) leaq 264(%rsp), %rax movq %rax, 200(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 216(%rsp), %rax subq %fs:40, %rax jne .L8 addq $232, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 248 pushq 72(%rsp) .cfi_def_cfa_offset 256 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z23predictor_normalizationPdS_S_S_S_S_S_iii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 240 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z58__device_stub__Z23predictor_normalizationPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii, .-_Z58__device_stub__Z23predictor_normalizationPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii .globl _Z23predictor_normalizationPdS_S_S_S_S_S_iii .type _Z23predictor_normalizationPdS_S_S_S_S_S_iii, @function _Z23predictor_normalizationPdS_S_S_S_S_S_iii: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 pushq 40(%rsp) .cfi_def_cfa_offset 48 call _Z58__device_stub__Z23predictor_normalizationPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii addq $40, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z23predictor_normalizationPdS_S_S_S_S_S_iii, .-_Z23predictor_normalizationPdS_S_S_S_S_S_iii .globl _Z62__device_stub__Z25predictor_standardizationPdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii .type _Z62__device_stub__Z25predictor_standardizationPdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii, @function _Z62__device_stub__Z25predictor_standardizationPdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii: .LFB2053: .cfi_startproc endbr64 subq $232, %rsp .cfi_def_cfa_offset 240 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) movq %rdx, 40(%rsp) movq %rcx, 32(%rsp) movq %r8, 24(%rsp) movq %r9, 16(%rsp) movq 240(%rsp), %rax movq %rax, 8(%rsp) movq 248(%rsp), %rax movq %rax, (%rsp) movq %fs:40, %rax movq %rax, 216(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) leaq 32(%rsp), %rax movq %rax, 152(%rsp) leaq 24(%rsp), %rax movq %rax, 160(%rsp) leaq 16(%rsp), %rax movq %rax, 168(%rsp) leaq 8(%rsp), %rax movq %rax, 176(%rsp) movq %rsp, %rax movq %rax, 184(%rsp) leaq 256(%rsp), %rax movq %rax, 192(%rsp) leaq 264(%rsp), %rax movq %rax, 200(%rsp) leaq 272(%rsp), %rax movq %rax, 208(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 216(%rsp), %rax subq %fs:40, %rax jne .L16 addq $232, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 248 pushq 72(%rsp) .cfi_def_cfa_offset 256 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 240 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2053: .size _Z62__device_stub__Z25predictor_standardizationPdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii, .-_Z62__device_stub__Z25predictor_standardizationPdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii .globl _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii .type _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii, @function _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii: .LFB2054: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 pushq 56(%rsp) .cfi_def_cfa_offset 56 pushq 56(%rsp) .cfi_def_cfa_offset 64 call _Z62__device_stub__Z25predictor_standardizationPdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii addq $56, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii, .-_Z25predictor_standardizationPdS_S_S_S_S_S_S_iii .globl _Z56__device_stub__Z21model_fit_preparationPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii .type _Z56__device_stub__Z21model_fit_preparationPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii, @function _Z56__device_stub__Z21model_fit_preparationPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii: .LFB2055: .cfi_startproc endbr64 subq $232, %rsp .cfi_def_cfa_offset 240 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) movq %rdx, 40(%rsp) movq %rcx, 32(%rsp) movq %r8, 24(%rsp) movq %r9, 16(%rsp) movq 240(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 216(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) leaq 32(%rsp), %rax movq %rax, 152(%rsp) leaq 24(%rsp), %rax movq %rax, 160(%rsp) leaq 16(%rsp), %rax movq %rax, 168(%rsp) leaq 8(%rsp), %rax movq %rax, 176(%rsp) leaq 248(%rsp), %rax movq %rax, 184(%rsp) leaq 256(%rsp), %rax movq %rax, 192(%rsp) leaq 264(%rsp), %rax movq %rax, 200(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L23 .L19: movq 216(%rsp), %rax subq %fs:40, %rax jne .L24 addq $232, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 248 pushq 72(%rsp) .cfi_def_cfa_offset 256 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z21model_fit_preparationPdS_S_S_S_S_S_iii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 240 jmp .L19 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE2055: .size _Z56__device_stub__Z21model_fit_preparationPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii, .-_Z56__device_stub__Z21model_fit_preparationPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii .globl _Z21model_fit_preparationPdS_S_S_S_S_S_iii .type _Z21model_fit_preparationPdS_S_S_S_S_S_iii, @function _Z21model_fit_preparationPdS_S_S_S_S_S_iii: .LFB2056: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 pushq 40(%rsp) .cfi_def_cfa_offset 48 call _Z56__device_stub__Z21model_fit_preparationPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii addq $40, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2056: .size _Z21model_fit_preparationPdS_S_S_S_S_S_iii, .-_Z21model_fit_preparationPdS_S_S_S_S_S_iii .globl _Z60__device_stub__Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .type _Z60__device_stub__Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, @function _Z60__device_stub__Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii: .LFB2057: .cfi_startproc endbr64 subq $360, %rsp .cfi_def_cfa_offset 368 movq %rdi, 120(%rsp) movq %rsi, 112(%rsp) movq %rdx, 104(%rsp) movq %rcx, 96(%rsp) movq %r8, 88(%rsp) movq %r9, 80(%rsp) movq 368(%rsp), %rax movq %rax, 72(%rsp) movq 376(%rsp), %rax movq %rax, 64(%rsp) movq 384(%rsp), %rax movq %rax, 56(%rsp) movq 392(%rsp), %rax movq %rax, 48(%rsp) movq 400(%rsp), %rax movq %rax, 40(%rsp) movq 408(%rsp), %rax movq %rax, 32(%rsp) movq 416(%rsp), %rax movq %rax, 24(%rsp) movq 424(%rsp), %rax movq %rax, 16(%rsp) movq 432(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 344(%rsp) xorl %eax, %eax leaq 120(%rsp), %rax movq %rax, 192(%rsp) leaq 112(%rsp), %rax movq %rax, 200(%rsp) leaq 104(%rsp), %rax movq %rax, 208(%rsp) leaq 96(%rsp), %rax movq %rax, 216(%rsp) leaq 88(%rsp), %rax movq %rax, 224(%rsp) leaq 80(%rsp), %rax movq %rax, 232(%rsp) leaq 72(%rsp), %rax movq %rax, 240(%rsp) leaq 64(%rsp), %rax movq %rax, 248(%rsp) leaq 56(%rsp), %rax movq %rax, 256(%rsp) leaq 48(%rsp), %rax movq %rax, 264(%rsp) leaq 40(%rsp), %rax movq %rax, 272(%rsp) leaq 32(%rsp), %rax movq %rax, 280(%rsp) leaq 24(%rsp), %rax movq %rax, 288(%rsp) leaq 16(%rsp), %rax movq %rax, 296(%rsp) leaq 8(%rsp), %rax movq %rax, 304(%rsp) leaq 440(%rsp), %rax movq %rax, 312(%rsp) leaq 448(%rsp), %rax movq %rax, 320(%rsp) leaq 456(%rsp), %rax movq %rax, 328(%rsp) leaq 464(%rsp), %rax movq %rax, 336(%rsp) movl $1, 144(%rsp) movl $1, 148(%rsp) movl $1, 152(%rsp) movl $1, 156(%rsp) movl $1, 160(%rsp) movl $1, 164(%rsp) leaq 136(%rsp), %rcx leaq 128(%rsp), %rdx leaq 156(%rsp), %rsi leaq 144(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L31 .L27: movq 344(%rsp), %rax subq %fs:40, %rax jne .L32 addq $360, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L31: .cfi_restore_state pushq 136(%rsp) .cfi_def_cfa_offset 376 pushq 136(%rsp) .cfi_def_cfa_offset 384 leaq 208(%rsp), %r9 movq 172(%rsp), %rcx movl 180(%rsp), %r8d movq 160(%rsp), %rsi movl 168(%rsp), %edx leaq _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 368 jmp .L27 .L32: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z60__device_stub__Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, .-_Z60__device_stub__Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .globl _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .type _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, @function _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii: .LFB2058: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 movl 120(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 120(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 120(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 movl 120(%rsp), %eax pushq %rax .cfi_def_cfa_offset 56 pushq 120(%rsp) .cfi_def_cfa_offset 64 pushq 120(%rsp) .cfi_def_cfa_offset 72 pushq 120(%rsp) .cfi_def_cfa_offset 80 pushq 120(%rsp) .cfi_def_cfa_offset 88 pushq 120(%rsp) .cfi_def_cfa_offset 96 pushq 120(%rsp) .cfi_def_cfa_offset 104 pushq 120(%rsp) .cfi_def_cfa_offset 112 pushq 120(%rsp) .cfi_def_cfa_offset 120 pushq 120(%rsp) .cfi_def_cfa_offset 128 call _Z60__device_stub__Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, .-_Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .globl _Z75__device_stub__Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .type _Z75__device_stub__Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, @function _Z75__device_stub__Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii: .LFB2059: .cfi_startproc endbr64 subq $360, %rsp .cfi_def_cfa_offset 368 movq %rdi, 120(%rsp) movq %rsi, 112(%rsp) movq %rdx, 104(%rsp) movq %rcx, 96(%rsp) movq %r8, 88(%rsp) movq %r9, 80(%rsp) movq 368(%rsp), %rax movq %rax, 72(%rsp) movq 376(%rsp), %rax movq %rax, 64(%rsp) movq 384(%rsp), %rax movq %rax, 56(%rsp) movq 392(%rsp), %rax movq %rax, 48(%rsp) movq 400(%rsp), %rax movq %rax, 40(%rsp) movq 408(%rsp), %rax movq %rax, 32(%rsp) movq 416(%rsp), %rax movq %rax, 24(%rsp) movq 424(%rsp), %rax movq %rax, 16(%rsp) movq 432(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 344(%rsp) xorl %eax, %eax leaq 120(%rsp), %rax movq %rax, 192(%rsp) leaq 112(%rsp), %rax movq %rax, 200(%rsp) leaq 104(%rsp), %rax movq %rax, 208(%rsp) leaq 96(%rsp), %rax movq %rax, 216(%rsp) leaq 88(%rsp), %rax movq %rax, 224(%rsp) leaq 80(%rsp), %rax movq %rax, 232(%rsp) leaq 72(%rsp), %rax movq %rax, 240(%rsp) leaq 64(%rsp), %rax movq %rax, 248(%rsp) leaq 56(%rsp), %rax movq %rax, 256(%rsp) leaq 48(%rsp), %rax movq %rax, 264(%rsp) leaq 40(%rsp), %rax movq %rax, 272(%rsp) leaq 32(%rsp), %rax movq %rax, 280(%rsp) leaq 24(%rsp), %rax movq %rax, 288(%rsp) leaq 16(%rsp), %rax movq %rax, 296(%rsp) leaq 8(%rsp), %rax movq %rax, 304(%rsp) leaq 440(%rsp), %rax movq %rax, 312(%rsp) leaq 448(%rsp), %rax movq %rax, 320(%rsp) leaq 456(%rsp), %rax movq %rax, 328(%rsp) leaq 464(%rsp), %rax movq %rax, 336(%rsp) movl $1, 144(%rsp) movl $1, 148(%rsp) movl $1, 152(%rsp) movl $1, 156(%rsp) movl $1, 160(%rsp) movl $1, 164(%rsp) leaq 136(%rsp), %rcx leaq 128(%rsp), %rdx leaq 156(%rsp), %rsi leaq 144(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L39 .L35: movq 344(%rsp), %rax subq %fs:40, %rax jne .L40 addq $360, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L39: .cfi_restore_state pushq 136(%rsp) .cfi_def_cfa_offset 376 pushq 136(%rsp) .cfi_def_cfa_offset 384 leaq 208(%rsp), %r9 movq 172(%rsp), %rcx movl 180(%rsp), %r8d movq 160(%rsp), %rsi movl 168(%rsp), %edx leaq _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 368 jmp .L35 .L40: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size _Z75__device_stub__Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, .-_Z75__device_stub__Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .globl _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .type _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, @function _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii: .LFB2060: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 movl 120(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 120(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 120(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 movl 120(%rsp), %eax pushq %rax .cfi_def_cfa_offset 56 pushq 120(%rsp) .cfi_def_cfa_offset 64 pushq 120(%rsp) .cfi_def_cfa_offset 72 pushq 120(%rsp) .cfi_def_cfa_offset 80 pushq 120(%rsp) .cfi_def_cfa_offset 88 pushq 120(%rsp) .cfi_def_cfa_offset 96 pushq 120(%rsp) .cfi_def_cfa_offset 104 pushq 120(%rsp) .cfi_def_cfa_offset 112 pushq 120(%rsp) .cfi_def_cfa_offset 120 pushq 120(%rsp) .cfi_def_cfa_offset 128 call _Z75__device_stub__Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, .-_Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .globl _Z74__device_stub__Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii .type _Z74__device_stub__Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii, @function _Z74__device_stub__Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii: .LFB2061: .cfi_startproc endbr64 subq $232, %rsp .cfi_def_cfa_offset 240 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) movq %rdx, 40(%rsp) movq %rcx, 32(%rsp) movq %r8, 24(%rsp) movq %r9, 16(%rsp) movq 240(%rsp), %rax movq %rax, 8(%rsp) movq 248(%rsp), %rax movq %rax, (%rsp) movq %fs:40, %rax movq %rax, 216(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) leaq 32(%rsp), %rax movq %rax, 152(%rsp) leaq 24(%rsp), %rax movq %rax, 160(%rsp) leaq 16(%rsp), %rax movq %rax, 168(%rsp) leaq 8(%rsp), %rax movq %rax, 176(%rsp) movq %rsp, %rax movq %rax, 184(%rsp) leaq 256(%rsp), %rax movq %rax, 192(%rsp) leaq 264(%rsp), %rax movq %rax, 200(%rsp) leaq 272(%rsp), %rax movq %rax, 208(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L47 .L43: movq 216(%rsp), %rax subq %fs:40, %rax jne .L48 addq $232, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L47: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 248 pushq 72(%rsp) .cfi_def_cfa_offset 256 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 240 jmp .L43 .L48: call __stack_chk_fail@PLT .cfi_endproc .LFE2061: .size _Z74__device_stub__Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii, .-_Z74__device_stub__Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii .globl _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .type _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii, @function _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii: .LFB2062: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 pushq 56(%rsp) .cfi_def_cfa_offset 56 pushq 56(%rsp) .cfi_def_cfa_offset 64 call _Z74__device_stub__Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii addq $56, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii, .-_Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .globl _Z78__device_stub__Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_iii .type _Z78__device_stub__Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_iii, @function _Z78__device_stub__Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_iii: .LFB2063: .cfi_startproc endbr64 subq $264, %rsp .cfi_def_cfa_offset 272 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movq %rcx, 48(%rsp) movq %r8, 40(%rsp) movq %r9, 32(%rsp) movq 272(%rsp), %rax movq %rax, 24(%rsp) movq 280(%rsp), %rax movq %rax, 16(%rsp) movq 288(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 248(%rsp) xorl %eax, %eax leaq 72(%rsp), %rax movq %rax, 144(%rsp) leaq 64(%rsp), %rax movq %rax, 152(%rsp) leaq 56(%rsp), %rax movq %rax, 160(%rsp) leaq 48(%rsp), %rax movq %rax, 168(%rsp) leaq 40(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 8(%rsp), %rax movq %rax, 208(%rsp) leaq 296(%rsp), %rax movq %rax, 216(%rsp) leaq 304(%rsp), %rax movq %rax, 224(%rsp) leaq 312(%rsp), %rax movq %rax, 232(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) movl $1, 104(%rsp) movl $1, 108(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) leaq 88(%rsp), %rcx leaq 80(%rsp), %rdx leaq 108(%rsp), %rsi leaq 96(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L55 .L51: movq 248(%rsp), %rax subq %fs:40, %rax jne .L56 addq $264, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L55: .cfi_restore_state pushq 88(%rsp) .cfi_def_cfa_offset 280 pushq 88(%rsp) .cfi_def_cfa_offset 288 leaq 160(%rsp), %r9 movq 124(%rsp), %rcx movl 132(%rsp), %r8d movq 112(%rsp), %rsi movl 120(%rsp), %edx leaq _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 272 jmp .L51 .L56: call __stack_chk_fail@PLT .cfi_endproc .LFE2063: .size _Z78__device_stub__Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_iii, .-_Z78__device_stub__Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_iii .globl _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .type _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii, @function _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii: .LFB2064: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 pushq 56(%rsp) .cfi_def_cfa_offset 48 pushq 56(%rsp) .cfi_def_cfa_offset 56 pushq 56(%rsp) .cfi_def_cfa_offset 64 call _Z78__device_stub__Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_iii addq $56, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2064: .size _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii, .-_Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii" .align 8 .LC1: .string "_Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii" .align 8 .LC2: .string "_Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii" .align 8 .LC3: .string "_Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii" .align 8 .LC4: .string "_Z21model_fit_preparationPdS_S_S_S_S_S_iii" .align 8 .LC5: .string "_Z25predictor_standardizationPdS_S_S_S_S_S_S_iii" .align 8 .LC6: .string "_Z23predictor_normalizationPdS_S_S_S_S_S_iii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2066: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC4(%rip), %rdx movq %rdx, %rcx leaq _Z21model_fit_preparationPdS_S_S_S_S_S_iii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z23predictor_normalizationPdS_S_S_S_S_S_iii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2066: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z23predictor_normalizationPdS_S_S_S_S_S_iii ; -- Begin function _Z23predictor_normalizationPdS_S_S_S_S_S_iii .globl _Z23predictor_normalizationPdS_S_S_S_S_S_iii .p2align 8 .type _Z23predictor_normalizationPdS_S_S_S_S_S_iii,@function _Z23predictor_normalizationPdS_S_S_S_S_S_iii: ; @_Z23predictor_normalizationPdS_S_S_S_S_S_iii ; %bb.0: s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x38 s_load_b32 s4, s[0:1], 0x40 s_waitcnt lgkmcnt(0) s_add_i32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_cmp_eq_u32 s15, s3 s_cselect_b32 s3, s4, s2 v_cmp_gt_i32_e32 vcc_lo, s3, v0 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB0_13 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x28 v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_load_b64 s[2:3], s[0:1], 0x18 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[1:2], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s6, v1 v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo v_add_co_u32 v5, vcc_lo, s4, v1 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo s_load_b64 s[4:5], s[0:1], 0x8 global_load_b64 v[3:4], v[3:4], off v_add_co_u32 v7, vcc_lo, s2, v1 v_add_co_ci_u32_e32 v8, vcc_lo, s3, v2, vcc_lo global_load_b64 v[5:6], v[5:6], off global_load_b64 v[8:9], v[7:8], off s_mov_b32 s3, exec_lo s_waitcnt vmcnt(2) v_cvt_i32_f64_e32 v3, v[3:4] s_waitcnt vmcnt(1) v_cvt_i32_f64_e32 v7, v[5:6] s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v0, v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s2, 1, v3 v_cndmask_b32_e64 v8, 0, 1, s2 s_delay_alu instid0(VALU_DEP_1) v_cmpx_lt_i32_e64 v8, v7 s_cbranch_execz .LBB0_11 ; %bb.2: ; %.preheader.lr.ph s_clause 0x1 s_load_b64 s[6:7], s[0:1], 0x20 s_load_b64 s[8:9], s[0:1], 0x10 s_waitcnt lgkmcnt(0) v_add_co_u32 v3, vcc_lo, s6, v1 v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo v_add_co_u32 v1, vcc_lo, s8, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo s_load_b64 s[6:7], s[0:1], 0x0 global_load_b64 v[3:4], v[3:4], off global_load_b64 v[1:2], v[1:2], off s_mov_b32 s8, 0 s_waitcnt vmcnt(1) v_cvt_i32_f64_e32 v9, v[3:4] s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v3, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_lt_i32_e64 s0, 0, v9 v_mad_u64_u32 v[1:2], null, v9, v8, v[3:4] s_branch .LBB0_4 .LBB0_3: ; %Flow106 ; in Loop: Header=BB0_4 Depth=1 s_set_inst_prefetch_distance 0x2 s_or_b32 exec_lo, exec_lo, s9 v_add_nc_u32_e32 v8, 1, v8 v_add_nc_u32_e32 v1, v1, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_ge_i32_e32 vcc_lo, v8, v7 s_or_b32 s8, vcc_lo, s8 s_and_not1_b32 exec_lo, exec_lo, s8 s_cbranch_execz .LBB0_11 .LBB0_4: ; %.preheader ; =>This Loop Header: Depth=1 ; Child Loop BB0_6 Depth 2 ; Child Loop BB0_10 Depth 2 v_mov_b32_e32 v3, 0 v_mov_b32_e32 v4, 0 s_delay_alu instid0(VALU_DEP_3) v_ashrrev_i32_e32 v2, 31, v1 s_and_saveexec_b32 s9, s0 s_cbranch_execz .LBB0_8 ; %bb.5: ; %.lr.ph ; in Loop: Header=BB0_4 Depth=1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) v_lshlrev_b64 v[5:6], 3, v[1:2] v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v10, v9 v_mov_b32_e32 v4, 0 s_mov_b32 s10, 0 s_waitcnt lgkmcnt(0) v_add_co_u32 v5, vcc_lo, s6, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo .LBB0_6: ; Parent Loop BB0_4 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_b64 v[11:12], v[5:6], off v_add_nc_u32_e32 v10, -1, v10 v_add_co_u32 v5, s1, v5, 8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v6, s1, 0, v6, s1 v_cmp_eq_u32_e32 vcc_lo, 0, v10 s_or_b32 s10, vcc_lo, s10 s_waitcnt vmcnt(0) v_fma_f64 v[3:4], v[11:12], v[11:12], v[3:4] s_and_not1_b32 exec_lo, exec_lo, s10 s_cbranch_execnz .LBB0_6 ; %bb.7: ; %Flow107 ; in Loop: Header=BB0_4 Depth=1 s_or_b32 exec_lo, exec_lo, s10 .LBB0_8: ; %Flow108 ; in Loop: Header=BB0_4 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s9 v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[3:4] v_cndmask_b32_e64 v5, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b32_e32 v5, 8, v5 v_ldexp_f64 v[3:4], v[3:4], v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_rsq_f64_e32 v[5:6], v[3:4] s_waitcnt_depctr 0xfff v_mul_f64 v[10:11], v[3:4], v[5:6] v_mul_f64 v[5:6], v[5:6], 0.5 v_fma_f64 v[12:13], -v[5:6], v[10:11], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] v_fma_f64 v[5:6], v[5:6], v[12:13], v[5:6] v_fma_f64 v[12:13], -v[10:11], v[10:11], v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[10:11], v[12:13], v[5:6], v[10:11] v_fma_f64 v[12:13], -v[10:11], v[10:11], v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_fma_f64 v[5:6], v[12:13], v[5:6], v[10:11] v_cndmask_b32_e64 v10, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x260 v_ldexp_f64 v[5:6], v[5:6], v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v3, v5, v3 :: v_dual_add_nc_u32 v10, v8, v0 v_ashrrev_i32_e32 v11, 31, v10 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v4, v6, v4, vcc_lo v_lshlrev_b64 v[10:11], 3, v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s4, v10 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v11, vcc_lo global_store_b64 v[5:6], v[3:4], off s_and_saveexec_b32 s9, s0 s_cbranch_execz .LBB0_3 ; %bb.9: ; %.lr.ph72 ; in Loop: Header=BB0_4 Depth=1 v_lshlrev_b64 v[5:6], 3, v[1:2] v_mov_b32_e32 v2, v9 s_mov_b32 s10, 0 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v5, vcc_lo, s6, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo s_set_inst_prefetch_distance 0x1 .p2align 6 .LBB0_10: ; Parent Loop BB0_4 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_b64 v[10:11], v[5:6], off v_add_nc_u32_e32 v2, -1, v2 s_waitcnt vmcnt(0) v_div_scale_f64 v[12:13], null, v[3:4], v[3:4], v[10:11] v_div_scale_f64 v[18:19], vcc_lo, v[10:11], v[3:4], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[14:15], v[12:13] s_waitcnt_depctr 0xfff v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0 v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0 v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[16:17], v[18:19], v[14:15] v_fma_f64 v[12:13], -v[12:13], v[16:17], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[16:17] v_cmp_eq_u32_e32 vcc_lo, 0, v2 s_or_b32 s10, vcc_lo, s10 v_div_fixup_f64 v[10:11], v[12:13], v[3:4], v[10:11] global_store_b64 v[5:6], v[10:11], off v_add_co_u32 v5, s1, v5, 8 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v6, s1, 0, v6, s1 s_and_not1_b32 exec_lo, exec_lo, s10 s_cbranch_execnz .LBB0_10 s_branch .LBB0_3 .LBB0_11: ; %Flow110 s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 exec_lo, exec_lo, s2 s_cbranch_execz .LBB0_13 ; %bb.12: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v1, 31, v0 v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x3ff00000 v_lshlrev_b64 v[0:1], 3, v[0:1] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo global_store_b64 v[0:1], v[2:3], off .LBB0_13: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z23predictor_normalizationPdS_S_S_S_S_S_iii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 68 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 20 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z23predictor_normalizationPdS_S_S_S_S_S_iii, .Lfunc_end0-_Z23predictor_normalizationPdS_S_S_S_S_S_iii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1040 ; NumSgprs: 18 ; NumVgprs: 20 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 20 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii ; -- Begin function _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii .globl _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii .p2align 8 .type _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii,@function _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii: ; @_Z25predictor_standardizationPdS_S_S_S_S_S_S_iii ; %bb.0: s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x40 s_load_b32 s4, s[0:1], 0x48 s_waitcnt lgkmcnt(0) s_add_i32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_cmp_eq_u32 s15, s3 s_cselect_b32 s3, s4, s2 v_cmp_gt_i32_e32 vcc_lo, s3, v0 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB1_17 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x30 v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_load_b64 s[2:3], s[0:1], 0x20 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[1:2], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s6, v1 v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo v_add_co_u32 v5, vcc_lo, s4, v1 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo s_load_b128 s[4:7], s[0:1], 0x8 global_load_b64 v[3:4], v[3:4], off v_add_co_u32 v7, vcc_lo, s2, v1 v_add_co_ci_u32_e32 v8, vcc_lo, s3, v2, vcc_lo global_load_b64 v[5:6], v[5:6], off global_load_b64 v[7:8], v[7:8], off s_mov_b32 s3, exec_lo s_waitcnt vmcnt(2) v_cvt_i32_f64_e32 v3, v[3:4] s_waitcnt vmcnt(1) v_cvt_i32_f64_e32 v13, v[5:6] s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v0, v[7:8] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s2, 1, v3 v_cndmask_b32_e64 v14, 0, 1, s2 s_delay_alu instid0(VALU_DEP_1) v_cmpx_lt_i32_e64 v14, v13 s_cbranch_execz .LBB1_15 ; %bb.2: ; %.preheader.lr.ph s_load_b64 s[8:9], s[0:1], 0x28 s_mov_b32 s10, 0 s_waitcnt lgkmcnt(0) v_add_co_u32 v3, vcc_lo, s8, v1 v_add_co_ci_u32_e32 v4, vcc_lo, s9, v2, vcc_lo s_load_b64 s[8:9], s[0:1], 0x18 global_load_b64 v[3:4], v[3:4], off s_waitcnt lgkmcnt(0) v_add_co_u32 v1, vcc_lo, s8, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo s_load_b64 s[8:9], s[0:1], 0x0 global_load_b64 v[1:2], v[1:2], off s_waitcnt vmcnt(1) v_cvt_i32_f64_e32 v15, v[3:4] s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v5, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cvt_f64_i32_e32 v[1:2], v15 v_cmp_lt_i32_e64 s0, 0, v15 v_mad_u64_u32 v[3:4], null, v15, v14, v[5:6] s_branch .LBB1_4 .LBB1_3: ; %Flow148 ; in Loop: Header=BB1_4 Depth=1 s_set_inst_prefetch_distance 0x2 s_or_b32 exec_lo, exec_lo, s11 v_add_nc_u32_e32 v14, 1, v14 v_add_nc_u32_e32 v3, v3, v15 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_ge_i32_e32 vcc_lo, v14, v13 s_or_b32 s10, vcc_lo, s10 s_and_not1_b32 exec_lo, exec_lo, s10 s_cbranch_execz .LBB1_15 .LBB1_4: ; %.preheader ; =>This Loop Header: Depth=1 ; Child Loop BB1_6 Depth 2 ; Child Loop BB1_10 Depth 2 ; Child Loop BB1_14 Depth 2 v_mov_b32_e32 v5, 0 v_mov_b32_e32 v6, 0 s_delay_alu instid0(VALU_DEP_3) v_ashrrev_i32_e32 v4, 31, v3 s_and_saveexec_b32 s11, s0 s_cbranch_execz .LBB1_8 ; %bb.5: ; %.lr.ph ; in Loop: Header=BB1_4 Depth=1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) v_lshlrev_b64 v[7:8], 3, v[3:4] v_mov_b32_e32 v5, 0 v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v9, v15 s_mov_b32 s12, 0 s_waitcnt lgkmcnt(0) v_add_co_u32 v7, vcc_lo, s8, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo .LBB1_6: ; Parent Loop BB1_4 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_b64 v[10:11], v[7:8], off v_add_nc_u32_e32 v9, -1, v9 v_add_co_u32 v7, s1, v7, 8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v8, s1, 0, v8, s1 v_cmp_eq_u32_e32 vcc_lo, 0, v9 s_or_b32 s12, vcc_lo, s12 s_waitcnt vmcnt(0) v_add_f64 v[5:6], v[5:6], v[10:11] s_and_not1_b32 exec_lo, exec_lo, s12 s_cbranch_execnz .LBB1_6 ; %bb.7: ; %Flow151 ; in Loop: Header=BB1_4 Depth=1 s_or_b32 exec_lo, exec_lo, s12 .LBB1_8: ; %Flow152 ; in Loop: Header=BB1_4 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s11 v_div_scale_f64 v[7:8], null, v[1:2], v[1:2], v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[9:10], v[7:8] s_waitcnt_depctr 0xfff v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10] v_div_scale_f64 v[11:12], vcc_lo, v[5:6], v[1:2], v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[16:17], v[11:12], v[9:10] v_fma_f64 v[7:8], -v[7:8], v[16:17], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[16:17] v_mov_b32_e32 v9, 0 v_mov_b32_e32 v10, 0 v_div_fixup_f64 v[5:6], v[7:8], v[1:2], v[5:6] v_add_nc_u32_e32 v7, v14, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v8, 31, v7 v_lshlrev_b64 v[7:8], 3, v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v11, vcc_lo, s6, v7 v_add_co_ci_u32_e32 v12, vcc_lo, s7, v8, vcc_lo global_store_b64 v[11:12], v[5:6], off s_and_saveexec_b32 s11, s0 s_cbranch_execz .LBB1_12 ; %bb.9: ; %.lr.ph97 ; in Loop: Header=BB1_4 Depth=1 v_lshlrev_b64 v[11:12], 3, v[3:4] v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v16, v15 v_mov_b32_e32 v10, 0 s_mov_b32 s12, 0 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_3) v_add_co_u32 v11, vcc_lo, s8, v11 v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo .LBB1_10: ; Parent Loop BB1_4 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_b64 v[17:18], v[11:12], off v_add_nc_u32_e32 v16, -1, v16 v_add_co_u32 v11, s1, v11, 8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v12, s1, 0, v12, s1 v_cmp_eq_u32_e32 vcc_lo, 0, v16 s_or_b32 s12, vcc_lo, s12 s_waitcnt vmcnt(0) v_add_f64 v[17:18], v[17:18], -v[5:6] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[9:10], v[17:18], v[17:18], v[9:10] s_and_not1_b32 exec_lo, exec_lo, s12 s_cbranch_execnz .LBB1_10 ; %bb.11: ; %Flow149 ; in Loop: Header=BB1_4 Depth=1 s_or_b32 exec_lo, exec_lo, s12 .LBB1_12: ; %Flow150 ; in Loop: Header=BB1_4 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s11 v_div_scale_f64 v[11:12], null, v[1:2], v[1:2], v[9:10] v_div_scale_f64 v[20:21], vcc_lo, v[9:10], v[1:2], v[9:10] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[16:17], v[11:12] s_waitcnt_depctr 0xfff v_fma_f64 v[18:19], -v[11:12], v[16:17], 1.0 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[11:12], v[16:17], 1.0 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[18:19], v[20:21], v[16:17] v_fma_f64 v[11:12], -v[11:12], v[18:19], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[11:12], v[11:12], v[16:17], v[18:19] v_div_fixup_f64 v[9:10], v[11:12], v[1:2], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[9:10] v_cndmask_b32_e64 v11, 0, 1, vcc_lo v_lshlrev_b32_e32 v11, 8, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[9:10], v[9:10], v11 v_rsq_f64_e32 v[11:12], v[9:10] s_waitcnt_depctr 0xfff v_mul_f64 v[16:17], v[9:10], v[11:12] v_mul_f64 v[11:12], v[11:12], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[11:12], v[16:17], 0.5 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] v_fma_f64 v[11:12], v[11:12], v[18:19], v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[16:17], v[16:17], v[9:10] v_fma_f64 v[16:17], v[18:19], v[11:12], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[16:17], v[16:17], v[9:10] v_fma_f64 v[11:12], v[18:19], v[11:12], v[16:17] v_cndmask_b32_e64 v16, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[9:10], 0x260 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[11:12], v[11:12], v16 v_dual_cndmask_b32 v10, v12, v10 :: v_dual_cndmask_b32 v9, v11, v9 v_add_co_u32 v7, vcc_lo, s4, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo global_store_b64 v[7:8], v[9:10], off s_and_saveexec_b32 s11, s0 s_cbranch_execz .LBB1_3 ; %bb.13: ; %.lr.ph102 ; in Loop: Header=BB1_4 Depth=1 v_lshlrev_b64 v[7:8], 3, v[3:4] v_mov_b32_e32 v4, v15 s_mov_b32 s12, 0 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v7, vcc_lo, s8, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo s_set_inst_prefetch_distance 0x1 .p2align 6 .LBB1_14: ; Parent Loop BB1_4 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_b64 v[11:12], v[7:8], off v_add_nc_u32_e32 v4, -1, v4 s_waitcnt vmcnt(0) v_add_f64 v[11:12], v[11:12], -v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f64 v[16:17], null, v[9:10], v[9:10], v[11:12] v_div_scale_f64 v[22:23], vcc_lo, v[11:12], v[9:10], v[11:12] v_rcp_f64_e32 v[18:19], v[16:17] s_waitcnt_depctr 0xfff v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] v_mul_f64 v[20:21], v[22:23], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], -v[16:17], v[20:21], v[22:23] v_div_fmas_f64 v[16:17], v[16:17], v[18:19], v[20:21] v_cmp_eq_u32_e32 vcc_lo, 0, v4 s_or_b32 s12, vcc_lo, s12 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_div_fixup_f64 v[11:12], v[16:17], v[9:10], v[11:12] global_store_b64 v[7:8], v[11:12], off v_add_co_u32 v7, s1, v7, 8 v_add_co_ci_u32_e64 v8, s1, 0, v8, s1 s_and_not1_b32 exec_lo, exec_lo, s12 s_cbranch_execnz .LBB1_14 s_branch .LBB1_3 .LBB1_15: ; %Flow154 s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 exec_lo, exec_lo, s2 s_cbranch_execz .LBB1_17 ; %bb.16: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_ashrrev_i32_e32 v1, 31, v0 s_mov_b32 s1, 0x3ff00000 s_mov_b32 s0, 0 v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v4, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo global_store_b64 v[4:5], v[2:3], off global_store_b64 v[0:1], v[2:3], off .LBB1_17: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 76 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 24 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii, .Lfunc_end1-_Z25predictor_standardizationPdS_S_S_S_S_S_S_iii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1456 ; NumSgprs: 18 ; NumVgprs: 24 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 24 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z21model_fit_preparationPdS_S_S_S_S_S_iii ; -- Begin function _Z21model_fit_preparationPdS_S_S_S_S_S_iii .globl _Z21model_fit_preparationPdS_S_S_S_S_S_iii .p2align 8 .type _Z21model_fit_preparationPdS_S_S_S_S_S_iii,@function _Z21model_fit_preparationPdS_S_S_S_S_S_iii: ; @_Z21model_fit_preparationPdS_S_S_S_S_S_iii ; %bb.0: s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x38 s_load_b32 s4, s[0:1], 0x40 s_waitcnt lgkmcnt(0) s_add_i32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_cmp_eq_u32 s15, s3 s_cselect_b32 s3, s4, s2 v_cmp_gt_i32_e32 vcc_lo, s3, v0 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB2_13 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x28 v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1] v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_mov_b32 s3, exec_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[0:1], 3, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo global_load_b64 v[4:5], v[4:5], off s_load_b64 s[4:5], s[0:1], 0x0 s_mov_b32 s6, 0 global_load_b64 v[0:1], v[0:1], off s_waitcnt vmcnt(1) v_cvt_i32_f64_e32 v12, v[4:5] s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v0, v[0:1] s_delay_alu instid0(VALU_DEP_2) v_cmpx_lt_i32_e32 0, v12 s_cbranch_execz .LBB2_5 ; %bb.2: ; %.lr.ph.preheader s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_ashrrev_i32_e32 v1, 31, v0 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 v_lshlrev_b64 v[4:5], 3, v[0:1] v_mov_b32_e32 v1, v12 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, s4, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo .LBB2_3: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 global_load_b64 v[8:9], v[4:5], off v_add_nc_u32_e32 v1, -1, v1 v_add_co_u32 v4, s2, v4, 8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v5, s2, 0, v5, s2 v_cmp_eq_u32_e32 vcc_lo, 0, v1 s_or_b32 s6, vcc_lo, s6 s_waitcnt vmcnt(0) v_add_f64 v[6:7], v[6:7], v[8:9] s_and_not1_b32 exec_lo, exec_lo, s6 s_cbranch_execnz .LBB2_3 ; %bb.4: ; %Flow130 s_or_b32 exec_lo, exec_lo, s6 .LBB2_5: ; %Flow131 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s3 v_cvt_f64_i32_e32 v[4:5], v12 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 s_mov_b32 s6, 0 s_mov_b32 s3, exec_lo v_cmpx_lt_i32_e32 0, v12 s_cbranch_execz .LBB2_9 ; %bb.6: ; %.lr.ph80.preheader s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[6:7] v_ashrrev_i32_e32 v1, 31, v0 v_rcp_f64_e32 v[10:11], v[8:9] s_waitcnt_depctr 0xfff v_fma_f64 v[13:14], -v[8:9], v[10:11], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[10:11], v[10:11], v[13:14], v[10:11] v_fma_f64 v[13:14], -v[8:9], v[10:11], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[10:11], v[10:11], v[13:14], v[10:11] v_div_scale_f64 v[13:14], vcc_lo, v[6:7], v[4:5], v[6:7] v_mul_f64 v[15:16], v[13:14], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[8:9], v[15:16], v[13:14] v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_div_fixup_f64 v[6:7], v[8:9], v[4:5], v[6:7] v_lshlrev_b64 v[8:9], 3, v[0:1] v_mov_b32_e32 v1, v12 s_waitcnt lgkmcnt(0) v_add_co_u32 v10, vcc_lo, s4, v8 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v11, vcc_lo, s5, v9, vcc_lo v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 .LBB2_7: ; %.lr.ph80 ; =>This Inner Loop Header: Depth=1 global_load_b64 v[13:14], v[10:11], off v_add_nc_u32_e32 v1, -1, v1 v_add_co_u32 v10, s2, v10, 8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v11, s2, 0, v11, s2 v_cmp_eq_u32_e32 vcc_lo, 0, v1 s_or_b32 s6, vcc_lo, s6 s_waitcnt vmcnt(0) v_add_f64 v[13:14], v[13:14], -v[6:7] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[8:9], v[13:14], v[13:14], v[8:9] s_and_not1_b32 exec_lo, exec_lo, s6 s_cbranch_execnz .LBB2_7 ; %bb.8: ; %Flow128 s_or_b32 exec_lo, exec_lo, s6 .LBB2_9: ; %Flow129 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s3 v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[8:9] v_div_scale_f64 v[15:16], vcc_lo, v[8:9], v[4:5], v[8:9] s_load_b64 s[2:3], s[0:1], 0x18 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[10:11], v[6:7] s_waitcnt_depctr 0xfff v_fma_f64 v[13:14], -v[6:7], v[10:11], 1.0 v_fma_f64 v[10:11], v[10:11], v[13:14], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[13:14], -v[6:7], v[10:11], 1.0 v_fma_f64 v[10:11], v[10:11], v[13:14], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[13:14], v[15:16], v[10:11] v_fma_f64 v[6:7], -v[6:7], v[13:14], v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[13:14] v_div_fixup_f64 v[4:5], v[6:7], v[4:5], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[4:5] v_cndmask_b32_e64 v1, 0, 1, vcc_lo v_lshlrev_b32_e32 v1, 8, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[4:5], v[4:5], v1 v_cndmask_b32_e64 v1, 0, 0xffffff80, vcc_lo v_rsq_f64_e32 v[6:7], v[4:5] v_cmp_class_f64_e64 vcc_lo, v[4:5], 0x260 s_waitcnt_depctr 0xfff v_mul_f64 v[8:9], v[4:5], v[6:7] v_mul_f64 v[6:7], v[6:7], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[10:11], -v[6:7], v[8:9], 0.5 v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9] v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[10:11], -v[8:9], v[8:9], v[4:5] v_fma_f64 v[8:9], v[10:11], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[10:11], -v[8:9], v[8:9], v[4:5] v_fma_f64 v[6:7], v[10:11], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[6:7], v[6:7], v1 v_lshlrev_b64 v[1:2], 3, v[2:3] v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v5, v7, v5 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v6, s2, s2, v1 v_add_co_ci_u32_e64 v7, s2, s3, v2, s2 s_delay_alu instid0(VALU_DEP_3) v_cmp_neq_f64_e32 vcc_lo, 0, v[4:5] global_store_b64 v[6:7], v[4:5], off s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB2_13 ; %bb.10: s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x10 s_load_b64 s[6:7], s[0:1], 0x20 v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0x3ff00000 s_waitcnt lgkmcnt(0) v_add_co_u32 v8, vcc_lo, s2, v1 v_add_co_ci_u32_e32 v9, vcc_lo, s3, v2, vcc_lo v_add_co_u32 v1, vcc_lo, s6, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo global_store_b64 v[8:9], v[6:7], off global_load_b64 v[6:7], v[1:2], off s_waitcnt vmcnt(0) v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[10:11], v[8:9] s_waitcnt_depctr 0xfff v_fma_f64 v[13:14], -v[8:9], v[10:11], 1.0 v_fma_f64 v[10:11], v[10:11], v[13:14], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[13:14], -v[8:9], v[10:11], 1.0 v_fma_f64 v[10:11], v[10:11], v[13:14], v[10:11] v_div_scale_f64 v[13:14], vcc_lo, v[6:7], v[4:5], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[15:16], v[13:14], v[10:11] v_fma_f64 v[8:9], -v[8:9], v[15:16], v[13:14] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[15:16] v_cmp_lt_i32_e32 vcc_lo, 0, v12 v_div_fixup_f64 v[6:7], v[8:9], v[4:5], v[6:7] global_store_b64 v[1:2], v[6:7], off s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB2_13 ; %bb.11: ; %.lr.ph85.preheader s_load_b64 s[0:1], s[0:1], 0x8 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 3, v[0:1] v_add_co_u32 v0, vcc_lo, s4, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s0, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo s_mov_b32 s1, 0 s_set_inst_prefetch_distance 0x1 .p2align 6 .LBB2_12: ; %.lr.ph85 ; =>This Inner Loop Header: Depth=1 global_load_b64 v[6:7], v[0:1], off v_add_nc_u32_e32 v12, -1, v12 s_waitcnt vmcnt(0) v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[6:7] v_div_scale_f64 v[15:16], vcc_lo, v[6:7], v[4:5], v[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[10:11], v[8:9] s_waitcnt_depctr 0xfff v_fma_f64 v[13:14], -v[8:9], v[10:11], 1.0 v_fma_f64 v[10:11], v[10:11], v[13:14], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[13:14], -v[8:9], v[10:11], 1.0 v_fma_f64 v[10:11], v[10:11], v[13:14], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[13:14], v[15:16], v[10:11] v_fma_f64 v[8:9], -v[8:9], v[13:14], v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[13:14] v_cmp_eq_u32_e32 vcc_lo, 0, v12 s_or_b32 s1, vcc_lo, s1 v_div_fixup_f64 v[6:7], v[8:9], v[4:5], v[6:7] global_store_b64 v[0:1], v[6:7], off global_store_b64 v[2:3], v[6:7], off v_add_co_u32 v0, s0, v0, 8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v1, s0, 0, v1, s0 v_add_co_u32 v2, s0, v2, 8 v_add_co_ci_u32_e64 v3, s0, 0, v3, s0 s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB2_12 .LBB2_13: ; %.loopexit s_set_inst_prefetch_distance 0x2 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z21model_fit_preparationPdS_S_S_S_S_S_iii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 68 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 17 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z21model_fit_preparationPdS_S_S_S_S_S_iii, .Lfunc_end2-_Z21model_fit_preparationPdS_S_S_S_S_S_iii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1380 ; NumSgprs: 18 ; NumVgprs: 17 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 17 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii ; -- Begin function _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .globl _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .p2align 8 .type _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii,@function _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii: ; @_Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii ; %bb.0: s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x7c s_load_b32 s4, s[0:1], 0x84 s_waitcnt lgkmcnt(0) s_add_i32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_cmp_eq_u32 s15, s3 s_cselect_b32 s3, s4, s2 v_cmp_gt_i32_e32 vcc_lo, s3, v0 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB3_55 ; %bb.1: s_load_b64 s[4:5], s[0:1], 0x10 v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[3:4], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo global_load_b64 v[5:6], v[5:6], off s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v0, v[5:6] s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 1, v0 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB3_55 ; %bb.2: s_clause 0x2 s_load_b128 s[16:19], s[0:1], 0x0 s_load_b128 s[4:7], s[0:1], 0x60 s_load_b64 s[2:3], s[0:1], 0x50 s_waitcnt lgkmcnt(0) v_add_co_u32 v5, vcc_lo, s18, v3 v_add_co_ci_u32_e32 v6, vcc_lo, s19, v4, vcc_lo v_add_co_u32 v7, vcc_lo, s6, v3 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo v_add_co_u32 v9, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v10, vcc_lo, s5, v4, vcc_lo global_load_b64 v[7:8], v[7:8], off v_add_co_u32 v11, vcc_lo, s2, v3 v_add_co_ci_u32_e32 v12, vcc_lo, s3, v4, vcc_lo global_load_b64 v[3:4], v[9:10], off global_load_b64 v[5:6], v[5:6], off global_load_b64 v[9:10], v[11:12], off s_mov_b32 s3, 0x426d1a94 s_mov_b32 s2, 0xa2000000 s_mov_b32 s18, 0 s_waitcnt vmcnt(3) v_cvt_i32_f64_e32 v28, v[7:8] s_waitcnt vmcnt(2) v_cmp_ge_f64_e32 vcc_lo, s[2:3], v[3:4] s_waitcnt vmcnt(1) v_cvt_i32_f64_e32 v0, v[5:6] s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v27, v[9:10] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_lt_i32_e64 s2, 0, v28 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s19, s2 s_cbranch_execz .LBB3_52 ; %bb.3: ; %.preheader209.lr.ph s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x40 s_load_b64 s[2:3], s[0:1], 0x58 v_lshlrev_b64 v[5:6], 3, v[1:2] s_load_b256 s[8:15], s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v7, vcc_lo, s6, v5 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo v_add_co_u32 v9, vcc_lo, s2, v5 v_add_co_ci_u32_e32 v10, vcc_lo, s3, v6, vcc_lo global_load_b64 v[7:8], v[7:8], off s_load_b64 s[2:3], s[0:1], 0x70 v_add_co_u32 v13, vcc_lo, s12, v5 s_load_b32 s12, s[0:1], 0x78 global_load_b64 v[9:10], v[9:10], off v_add_co_ci_u32_e32 v14, vcc_lo, s13, v6, vcc_lo s_mov_b32 s13, 0 global_load_b64 v[13:14], v[13:14], off s_waitcnt lgkmcnt(0) v_add_co_u32 v15, vcc_lo, s2, v5 v_add_co_ci_u32_e32 v16, vcc_lo, s3, v6, vcc_lo v_add_co_u32 v17, vcc_lo, s10, v5 v_add_co_ci_u32_e32 v18, vcc_lo, s11, v6, vcc_lo v_add_co_u32 v5, vcc_lo, s4, v5 global_load_b64 v[15:16], v[15:16], off v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo global_load_b64 v[17:18], v[17:18], off global_load_b64 v[19:20], v[5:6], off s_and_b32 s4, s12, -3 v_cmp_lt_i32_e64 s2, 0, v27 s_cmp_lg_u32 s4, 1 s_cselect_b32 s10, -1, 0 s_waitcnt vmcnt(5) v_cvt_i32_f64_e32 v29, v[7:8] s_waitcnt vmcnt(3) v_cvt_i32_f64_e32 v13, v[13:14] s_waitcnt vmcnt(2) v_cvt_i32_f64_e32 v15, v[15:16] s_waitcnt vmcnt(1) v_cvt_i32_f64_e32 v30, v[17:18] s_delay_alu instid0(VALU_DEP_4) v_cvt_f64_i32_e32 v[7:8], v29 v_cmp_lt_i32_e64 s3, 0, v29 v_ashrrev_i32_e32 v14, 31, v13 v_cmp_eq_u32_e64 s4, 1, v15 v_cmp_eq_u32_e64 s5, 0, v15 v_div_scale_f64 v[11:12], null, v[7:8], v[7:8], 1.0 v_div_scale_f64 v[23:24], vcc_lo, 1.0, v[7:8], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[5:6], v[11:12] s_waitcnt_depctr 0xfff v_fma_f64 v[21:22], -v[11:12], v[5:6], 1.0 v_fma_f64 v[5:6], v[5:6], v[21:22], v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[21:22], -v[11:12], v[5:6], 1.0 v_fma_f64 v[5:6], v[5:6], v[21:22], v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[21:22], v[23:24], v[5:6] v_fma_f64 v[11:12], -v[11:12], v[21:22], v[23:24] s_delay_alu instid0(VALU_DEP_1) v_div_fmas_f64 v[11:12], v[11:12], v[5:6], v[21:22] v_add_f64 v[21:22], -v[9:10], 1.0 s_waitcnt vmcnt(0) v_mul_f64 v[5:6], v[9:10], v[19:20] v_cmp_gt_i32_e32 vcc_lo, 1, v29 s_xor_b32 s11, vcc_lo, -1 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_div_fixup_f64 v[7:8], v[11:12], v[7:8], 1.0 v_mul_f64 v[9:10], v[19:20], v[21:22] v_lshlrev_b64 v[11:12], 3, v[13:14] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v11, s6, s14, v11 v_add_co_ci_u32_e64 v12, s6, s15, v12, s6 .LBB3_4: ; %.preheader209 ; =>This Loop Header: Depth=1 ; Child Loop BB3_8 Depth 2 ; Child Loop BB3_11 Depth 3 ; Child Loop BB3_17 Depth 3 ; Child Loop BB3_37 Depth 3 v_mov_b32_e32 v13, 0 v_mov_b32_e32 v14, 0 s_and_saveexec_b32 s14, s2 s_cbranch_execz .LBB3_50 ; %bb.5: ; %.lr.ph220.preheader ; in Loop: Header=BB3_4 Depth=1 v_mov_b32_e32 v13, 0 v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v15, v30 s_mov_b32 s15, 0 s_mov_b32 s20, 0 s_branch .LBB3_8 .LBB3_6: ; %Flow314 ; in Loop: Header=BB3_8 Depth=2 s_or_b32 exec_lo, exec_lo, s6 .LBB3_7: ; in Loop: Header=BB3_8 Depth=2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, v[16:17], v[13:14] s_add_i32 s20, s20, 1 v_add_nc_u32_e32 v15, v15, v29 v_cmp_eq_u32_e64 s6, s20, v27 s_or_b32 s15, s6, s15 v_dual_cndmask_b32 v14, v14, v17 :: v_dual_cndmask_b32 v13, v13, v16 s_and_not1_b32 exec_lo, exec_lo, s15 s_cbranch_execz .LBB3_49 .LBB3_8: ; %.lr.ph220 ; Parent Loop BB3_4 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB3_11 Depth 3 ; Child Loop BB3_17 Depth 3 ; Child Loop BB3_37 Depth 3 v_add_nc_u32_e32 v16, s20, v0 ; implicit-def: $vgpr21_vgpr22 s_mov_b32 s6, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v17, 31, v16 v_lshlrev_b64 v[16:17], 3, v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v19, vcc_lo, s16, v16 v_add_co_ci_u32_e32 v20, vcc_lo, s17, v17, vcc_lo global_load_b64 v[17:18], v[19:20], off s_waitcnt vmcnt(0) v_cmpx_eq_f64_e32 0, v[17:18] s_xor_b32 s7, exec_lo, s6 s_cbranch_execz .LBB3_14 ; %bb.9: ; %.preheader207 ; in Loop: Header=BB3_8 Depth=2 v_mov_b32_e32 v21, 0 v_mov_b32_e32 v22, 0 s_and_saveexec_b32 s21, s3 s_cbranch_execz .LBB3_13 ; %bb.10: ; %.lr.ph ; in Loop: Header=BB3_8 Depth=2 v_ashrrev_i32_e32 v16, 31, v15 v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v24, v12 v_dual_mov_b32 v22, 0 :: v_dual_mov_b32 v23, v11 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_lshlrev_b64 v[25:26], 3, v[15:16] v_mov_b32_e32 v16, v29 s_mov_b32 s22, 0 v_add_co_u32 v25, vcc_lo, s8, v25 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v26, vcc_lo, s9, v26, vcc_lo .p2align 6 .LBB3_11: ; Parent Loop BB3_4 Depth=1 ; Parent Loop BB3_8 Depth=2 ; => This Inner Loop Header: Depth=3 global_load_b64 v[31:32], v[25:26], off global_load_b64 v[33:34], v[23:24], off v_add_nc_u32_e32 v16, -1, v16 v_add_co_u32 v23, vcc_lo, v23, 8 v_add_co_ci_u32_e32 v24, vcc_lo, 0, v24, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v16 v_add_co_u32 v25, s6, v25, 8 v_add_co_ci_u32_e64 v26, s6, 0, v26, s6 s_or_b32 s22, vcc_lo, s22 s_waitcnt vmcnt(0) v_fma_f64 v[21:22], v[31:32], v[33:34], v[21:22] s_and_not1_b32 exec_lo, exec_lo, s22 s_cbranch_execnz .LBB3_11 ; %bb.12: ; %Flow325 ; in Loop: Header=BB3_8 Depth=2 s_or_b32 exec_lo, exec_lo, s22 .LBB3_13: ; %Flow326 ; in Loop: Header=BB3_8 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s21 .LBB3_14: ; %Flow329 ; in Loop: Header=BB3_8 Depth=2 s_and_not1_saveexec_b32 s7, s7 s_cbranch_execz .LBB3_20 ; %bb.15: ; %.preheader205 ; in Loop: Header=BB3_8 Depth=2 v_mov_b32_e32 v21, 0 v_mov_b32_e32 v22, 0 s_and_saveexec_b32 s21, s3 s_cbranch_execz .LBB3_19 ; %bb.16: ; %.lr.ph214 ; in Loop: Header=BB3_8 Depth=2 v_ashrrev_i32_e32 v16, 31, v15 v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v24, v12 v_dual_mov_b32 v22, 0 :: v_dual_mov_b32 v23, v11 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_lshlrev_b64 v[25:26], 3, v[15:16] v_mov_b32_e32 v16, v29 s_mov_b32 s22, 0 v_add_co_u32 v25, vcc_lo, s8, v25 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v26, vcc_lo, s9, v26, vcc_lo .p2align 6 .LBB3_17: ; Parent Loop BB3_4 Depth=1 ; Parent Loop BB3_8 Depth=2 ; => This Inner Loop Header: Depth=3 global_load_b64 v[31:32], v[25:26], off global_load_b64 v[33:34], v[23:24], off v_add_nc_u32_e32 v16, -1, v16 v_add_co_u32 v25, vcc_lo, v25, 8 v_add_co_ci_u32_e32 v26, vcc_lo, 0, v26, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v16 s_or_b32 s22, vcc_lo, s22 s_waitcnt vmcnt(0) v_fma_f64 v[33:34], v[17:18], v[31:32], v[33:34] v_fma_f64 v[21:22], v[31:32], v[33:34], v[21:22] global_store_b64 v[23:24], v[33:34], off v_add_co_u32 v23, s6, v23, 8 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v24, s6, 0, v24, s6 s_and_not1_b32 exec_lo, exec_lo, s22 s_cbranch_execnz .LBB3_17 ; %bb.18: ; %Flow327 ; in Loop: Header=BB3_8 Depth=2 s_or_b32 exec_lo, exec_lo, s22 .LBB3_19: ; %Flow328 ; in Loop: Header=BB3_8 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s21 .LBB3_20: ; %.loopexit206 ; in Loop: Header=BB3_8 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s7 v_mul_f64 v[21:22], v[7:8], v[21:22] ; implicit-def: $vgpr23_vgpr24 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_nlt_f64_e32 vcc_lo, 0, v[21:22] v_cmp_nlt_f64_e64 s6, v[5:6], |v[21:22]| s_or_b32 s6, vcc_lo, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s7, s6 s_xor_b32 s6, exec_lo, s7 s_cbranch_execz .LBB3_24 ; %bb.21: ; in Loop: Header=BB3_8 Depth=2 v_cmp_gt_f64_e32 vcc_lo, 0, v[21:22] v_cmp_lt_f64_e64 s7, v[5:6], |v[21:22]| v_mov_b32_e32 v23, 0 v_mov_b32_e32 v24, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s21, vcc_lo, s7 s_and_saveexec_b32 s7, s21 ; %bb.22: ; in Loop: Header=BB3_8 Depth=2 v_add_f64 v[23:24], v[5:6], v[21:22] ; %bb.23: ; %Flow323 ; in Loop: Header=BB3_8 Depth=2 s_or_b32 exec_lo, exec_lo, s7 .LBB3_24: ; %Flow324 ; in Loop: Header=BB3_8 Depth=2 s_and_not1_saveexec_b32 s6, s6 ; %bb.25: ; in Loop: Header=BB3_8 Depth=2 v_add_f64 v[23:24], v[21:22], -v[5:6] ; %bb.26: ; in Loop: Header=BB3_8 Depth=2 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v25, 0 v_mov_b32_e32 v26, 0x3ff00000 s_and_not1_b32 vcc_lo, exec_lo, s10 s_cbranch_vccnz .LBB3_33 ; %bb.27: ; %NodeBlock ; in Loop: Header=BB3_8 Depth=2 s_cmp_lt_i32 s12, 4 s_cbranch_scc1 .LBB3_29 ; %bb.28: ; %LeafBlock303 ; in Loop: Header=BB3_8 Depth=2 s_cmp_eq_u32 s12, 4 s_mov_b64 s[6:7], 0 s_cselect_b32 s21, -1, 0 s_cbranch_execz .LBB3_30 s_branch .LBB3_31 .LBB3_29: ; in Loop: Header=BB3_8 Depth=2 s_mov_b32 s21, 0 ; implicit-def: $sgpr6_sgpr7 .LBB3_30: ; %LeafBlock ; in Loop: Header=BB3_8 Depth=2 s_cmp_eq_u32 s12, 2 s_mov_b64 s[6:7], 0 s_cselect_b32 s21, -1, 0 .LBB3_31: ; %Flow320 ; in Loop: Header=BB3_8 Depth=2 v_dual_mov_b32 v26, s7 :: v_dual_mov_b32 v25, s6 s_and_not1_b32 vcc_lo, exec_lo, s21 s_cbranch_vccnz .LBB3_33 ; %bb.32: ; in Loop: Header=BB3_8 Depth=2 v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v25, v7 .LBB3_33: ; in Loop: Header=BB3_8 Depth=2 s_cmp_lg_u32 s20, 0 s_cselect_b32 s6, -1, 0 s_xor_b32 s7, s4, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s21, s7, s6 s_and_saveexec_b32 s6, s21 s_cbranch_execz .LBB3_35 ; %bb.34: ; in Loop: Header=BB3_8 Depth=2 v_add_f64 v[21:22], v[9:10], v[25:26] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[25:26], null, v[21:22], v[21:22], v[23:24] v_rcp_f64_e32 v[31:32], v[25:26] s_waitcnt_depctr 0xfff v_fma_f64 v[33:34], -v[25:26], v[31:32], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[31:32], v[31:32], v[33:34], v[31:32] v_fma_f64 v[33:34], -v[25:26], v[31:32], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[31:32], v[31:32], v[33:34], v[31:32] v_div_scale_f64 v[33:34], vcc_lo, v[23:24], v[21:22], v[23:24] v_mul_f64 v[35:36], v[33:34], v[31:32] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[25:26], -v[25:26], v[35:36], v[33:34] v_div_fmas_f64 v[25:26], v[25:26], v[31:32], v[35:36] s_delay_alu instid0(VALU_DEP_1) v_div_fixup_f64 v[21:22], v[25:26], v[21:22], v[23:24] .LBB3_35: ; in Loop: Header=BB3_8 Depth=2 s_or_b32 exec_lo, exec_lo, s6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_neq_f64_e32 vcc_lo, 0, v[21:22] global_store_b64 v[19:20], v[21:22], off s_and_b32 s6, vcc_lo, s11 s_and_saveexec_b32 s21, s6 s_cbranch_execz .LBB3_38 ; %bb.36: ; %.lr.ph217 ; in Loop: Header=BB3_8 Depth=2 v_ashrrev_i32_e32 v16, 31, v15 v_dual_mov_b32 v20, v12 :: v_dual_mov_b32 v19, v11 s_mov_b32 s22, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b64 v[23:24], 3, v[15:16] v_mov_b32_e32 v16, v29 v_add_co_u32 v23, vcc_lo, s8, v23 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v24, vcc_lo, s9, v24, vcc_lo .p2align 6 .LBB3_37: ; Parent Loop BB3_4 Depth=1 ; Parent Loop BB3_8 Depth=2 ; => This Inner Loop Header: Depth=3 global_load_b64 v[25:26], v[19:20], off global_load_b64 v[31:32], v[23:24], off v_add_nc_u32_e32 v16, -1, v16 v_add_co_u32 v23, vcc_lo, v23, 8 v_add_co_ci_u32_e32 v24, vcc_lo, 0, v24, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_cmp_eq_u32_e32 vcc_lo, 0, v16 s_or_b32 s22, vcc_lo, s22 s_waitcnt vmcnt(0) v_fma_f64 v[25:26], -v[21:22], v[31:32], v[25:26] global_store_b64 v[19:20], v[25:26], off v_add_co_u32 v19, s6, v19, 8 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v20, s6, 0, v20, s6 s_and_not1_b32 exec_lo, exec_lo, s22 s_cbranch_execnz .LBB3_37 .LBB3_38: ; %Flow318 ; in Loop: Header=BB3_8 Depth=2 s_or_b32 exec_lo, exec_lo, s21 v_add_f64 v[16:17], v[17:18], -v[21:22] s_cmp_lt_i32 s12, 4 s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[16:17], v[16:17], v[16:17] s_cbranch_scc1 .LBB3_40 ; %bb.39: ; %LeafBlock307 ; in Loop: Header=BB3_8 Depth=2 s_cmp_eq_u32 s12, 4 s_cselect_b32 s6, -1, 0 s_cbranch_execz .LBB3_41 s_branch .LBB3_42 .LBB3_40: ; in Loop: Header=BB3_8 Depth=2 s_mov_b32 s6, 0 .LBB3_41: ; %LeafBlock305 ; in Loop: Header=BB3_8 Depth=2 s_cmp_eq_u32 s12, 2 s_cselect_b32 s6, -1, 0 .LBB3_42: ; %Flow316 ; in Loop: Header=BB3_8 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB3_7 ; %bb.43: ; in Loop: Header=BB3_8 Depth=2 s_cmp_eq_u32 s20, 0 s_cselect_b32 s6, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s6, s7, s6 s_and_saveexec_b32 s7, s6 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s6, exec_lo, s7 s_cbranch_execz .LBB3_47 ; %bb.44: ; in Loop: Header=BB3_8 Depth=2 s_and_saveexec_b32 s7, s5 ; %bb.45: ; in Loop: Header=BB3_8 Depth=2 s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[16:17], v[7:8], v[16:17] ; %bb.46: ; %Flow312 ; in Loop: Header=BB3_8 Depth=2 s_or_b32 exec_lo, exec_lo, s7 .LBB3_47: ; %Flow313 ; in Loop: Header=BB3_8 Depth=2 s_and_not1_saveexec_b32 s6, s6 s_cbranch_execz .LBB3_6 ; %bb.48: ; in Loop: Header=BB3_8 Depth=2 s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[16:17], v[7:8], v[16:17] s_branch .LBB3_6 .LBB3_49: ; %Flow330 ; in Loop: Header=BB3_4 Depth=1 s_or_b32 exec_lo, exec_lo, s15 .LBB3_50: ; %Flow331 ; in Loop: Header=BB3_4 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s14 ; %bb.51: ; %._crit_edge ; in Loop: Header=BB3_4 Depth=1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_nge_f64_e32 vcc_lo, v[13:14], v[3:4] s_add_i32 s13, s13, 1 v_cmp_ge_i32_e64 s6, s13, v28 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s6, vcc_lo, s6 s_and_b32 s6, exec_lo, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s18, s6, s18 s_and_not1_b32 exec_lo, exec_lo, s18 s_cbranch_execnz .LBB3_4 .LBB3_52: ; %Flow333 s_or_b32 exec_lo, exec_lo, s19 s_delay_alu instid0(VALU_DEP_2) v_cmp_lt_i32_e32 vcc_lo, 0, v27 s_mov_b32 s2, 0 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB3_55 ; %bb.53: ; %.lr.ph226.preheader s_load_b64 s[0:1], s[0:1], 0x38 v_lshlrev_b64 v[1:2], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, s0, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo global_load_b64 v[2:3], v[1:2], off v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[0:1] v_add_co_u32 v0, vcc_lo, s16, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo .LBB3_54: ; %.lr.ph226 ; =>This Inner Loop Header: Depth=1 global_load_b64 v[4:5], v[0:1], off v_add_nc_u32_e32 v27, -1, v27 s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v27 s_or_b32 s2, vcc_lo, s2 s_waitcnt vmcnt(0) v_mul_f64 v[4:5], v[2:3], v[4:5] global_store_b64 v[0:1], v[4:5], off v_add_co_u32 v0, s0, v0, 8 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v1, s0, 0, v1, s0 s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB3_54 .LBB3_55: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 136 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 37 .amdhsa_next_free_sgpr 23 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end3: .size _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, .Lfunc_end3-_Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 2192 ; NumSgprs: 25 ; NumVgprs: 37 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 3 ; VGPRBlocks: 4 ; NumSGPRsForWavesPerEU: 25 ; NumVGPRsForWavesPerEU: 37 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii ; -- Begin function _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .globl _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .p2align 8 .type _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii,@function _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii: ; @_Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii ; %bb.0: s_clause 0x1 s_load_b64 s[12:13], s[0:1], 0x7c s_load_b32 s2, s[0:1], 0x84 s_waitcnt lgkmcnt(0) s_add_i32 s3, s13, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_cmp_eq_u32 s15, s3 s_cselect_b32 s2, s2, s12 v_cmp_gt_i32_e32 vcc_lo, s2, v0 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB4_58 ; %bb.1: s_load_b64 s[2:3], s[0:1], 0x10 v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[3:4], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s2, v3 v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo global_load_b64 v[5:6], v[5:6], off s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v5, v[5:6] s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 1, v5 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB4_58 ; %bb.2: s_clause 0x3 s_load_b256 s[4:11], s[0:1], 0x40 s_load_b64 s[2:3], s[0:1], 0x8 s_load_b64 s[14:15], s[0:1], 0x20 s_load_b128 s[16:19], s[0:1], 0x60 s_waitcnt lgkmcnt(0) v_add_co_u32 v5, vcc_lo, s6, v3 v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo global_load_b64 v[20:21], v[5:6], off v_add_co_u32 v5, vcc_lo, s2, v3 v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo s_load_b64 s[2:3], s[0:1], 0x70 v_add_co_u32 v7, vcc_lo, s14, v3 v_add_co_ci_u32_e32 v8, vcc_lo, s15, v4, vcc_lo v_add_co_u32 v9, vcc_lo, s10, v3 v_add_co_ci_u32_e32 v10, vcc_lo, s11, v4, vcc_lo global_load_b64 v[14:15], v[5:6], off global_load_b64 v[6:7], v[7:8], off global_load_b64 v[8:9], v[9:10], off v_add_co_u32 v10, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v11, vcc_lo, s5, v4, vcc_lo v_add_co_u32 v12, vcc_lo, s16, v3 v_add_co_ci_u32_e32 v13, vcc_lo, s17, v4, vcc_lo v_add_co_u32 v16, vcc_lo, s18, v3 v_add_co_ci_u32_e32 v17, vcc_lo, s19, v4, vcc_lo v_add_co_u32 v22, vcc_lo, s8, v3 v_add_co_ci_u32_e32 v23, vcc_lo, s9, v4, vcc_lo s_waitcnt lgkmcnt(0) v_add_co_u32 v24, vcc_lo, s2, v3 v_add_co_ci_u32_e32 v25, vcc_lo, s3, v4, vcc_lo global_load_b64 v[10:11], v[10:11], off global_load_b64 v[3:4], v[12:13], off global_load_b64 v[18:19], v[16:17], off global_load_b64 v[16:17], v[22:23], off global_load_b64 v[12:13], v[24:25], off s_mov_b32 s4, 0 s_mov_b32 s3, exec_lo s_waitcnt vmcnt(8) v_cvt_i32_f64_e32 v26, v[20:21] s_delay_alu instid0(VALU_DEP_1) v_cmpx_lt_i32_e32 0, v26 s_cbranch_execz .LBB4_5 ; %bb.3: ; %.lr.ph.preheader s_load_b128 s[8:11], s[0:1], 0x28 v_lshlrev_b64 v[20:21], 3, v[1:2] v_lshl_add_u32 v5, v0, 3, 0 v_mov_b32_e32 v22, v26 s_lshl_b32 s5, s12, 3 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_add_co_u32 v20, vcc_lo, s8, v20 v_add_co_ci_u32_e32 v21, vcc_lo, s9, v21, vcc_lo global_load_b64 v[20:21], v[20:21], off s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v20, v[20:21] v_ashrrev_i32_e32 v21, 31, v20 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[20:21], 3, v[20:21] v_add_co_u32 v20, vcc_lo, s10, v20 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v21, vcc_lo, s11, v21, vcc_lo .LBB4_4: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 global_load_b64 v[23:24], v[20:21], off v_add_nc_u32_e32 v22, -1, v22 v_add_co_u32 v20, vcc_lo, v20, 8 v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s2, 0, v22 s_or_b32 s4, s2, s4 s_waitcnt vmcnt(0) ds_store_b64 v5, v[23:24] v_add_nc_u32_e32 v5, s5, v5 s_and_not1_b32 exec_lo, exec_lo, s4 s_cbranch_execnz .LBB4_4 .LBB4_5: ; %Flow357 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(2) v_cvt_i32_f64_e32 v28, v[18:19] s_mov_b32 s3, 0x426d1a94 s_mov_b32 s2, 0xa2000000 v_cvt_i32_f64_e32 v5, v[14:15] v_cmp_ge_f64_e32 vcc_lo, s[2:3], v[3:4] s_waitcnt vmcnt(1) v_cvt_i32_f64_e32 v27, v[16:17] s_load_b64 s[8:9], s[0:1], 0x0 s_mov_b32 s13, 0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_lt_i32_e64 s2, 0, v28 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s14, s2 s_cbranch_execz .LBB4_55 ; %bb.6: ; %.preheader219.lr.ph v_cvt_f64_i32_e32 v[14:15], v26 s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v12, v[12:13] v_cvt_i32_f64_e32 v29, v[6:7] v_mul_f64 v[6:7], v[8:9], v[10:11] s_clause 0x1 s_load_b32 s15, s[0:1], 0x78 s_load_b64 s[10:11], s[0:1], 0x18 v_cmp_lt_i32_e64 s2, 0, v27 v_lshl_add_u32 v0, v0, 3, 0 s_mov_b32 s18, 0 s_waitcnt lgkmcnt(0) s_and_b32 s3, s15, -3 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u32 s3, 1 v_cmp_lt_i32_e64 s3, 0, v26 s_cselect_b32 s16, -1, 0 s_lshl_b32 s12, s12, 3 v_div_scale_f64 v[16:17], null, v[14:15], v[14:15], 1.0 v_div_scale_f64 v[22:23], vcc_lo, 1.0, v[14:15], 1.0 v_cmp_eq_u32_e64 s4, 1, v12 v_cmp_eq_u32_e64 s5, 0, v12 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[18:19], v[16:17] s_waitcnt_depctr 0xfff v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[20:21], v[22:23], v[18:19] v_fma_f64 v[16:17], -v[16:17], v[20:21], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_div_fmas_f64 v[16:17], v[16:17], v[18:19], v[20:21] v_add_f64 v[18:19], -v[8:9], 1.0 v_cmp_gt_i32_e32 vcc_lo, 1, v26 s_xor_b32 s17, vcc_lo, -1 v_div_fixup_f64 v[8:9], v[16:17], v[14:15], 1.0 s_delay_alu instid0(VALU_DEP_3) v_mul_f64 v[10:11], v[10:11], v[18:19] .LBB4_7: ; %.preheader219 ; =>This Loop Header: Depth=1 ; Child Loop BB4_11 Depth 2 ; Child Loop BB4_14 Depth 3 ; Child Loop BB4_20 Depth 3 ; Child Loop BB4_40 Depth 3 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_and_saveexec_b32 s19, s2 s_cbranch_execz .LBB4_53 ; %bb.8: ; %.lr.ph233.preheader ; in Loop: Header=BB4_7 Depth=1 v_mov_b32_e32 v12, 0 v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v14, v29 s_mov_b32 s20, 0 s_mov_b32 s21, 0 s_branch .LBB4_11 .LBB4_9: ; %Flow336 ; in Loop: Header=BB4_11 Depth=2 s_or_b32 exec_lo, exec_lo, s6 .LBB4_10: ; in Loop: Header=BB4_11 Depth=2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, v[15:16], v[12:13] s_add_i32 s21, s21, 1 v_add_nc_u32_e32 v14, v14, v26 v_cmp_eq_u32_e64 s6, s21, v27 s_or_b32 s20, s6, s20 v_dual_cndmask_b32 v13, v13, v16 :: v_dual_cndmask_b32 v12, v12, v15 s_and_not1_b32 exec_lo, exec_lo, s20 s_cbranch_execz .LBB4_52 .LBB4_11: ; %.lr.ph233 ; Parent Loop BB4_7 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB4_14 Depth 3 ; Child Loop BB4_20 Depth 3 ; Child Loop BB4_40 Depth 3 v_add_nc_u32_e32 v15, s21, v5 ; implicit-def: $vgpr20_vgpr21 s_mov_b32 s6, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v16, 31, v15 v_lshlrev_b64 v[15:16], 3, v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v18, vcc_lo, s8, v15 v_add_co_ci_u32_e32 v19, vcc_lo, s9, v16, vcc_lo global_load_b64 v[16:17], v[18:19], off s_waitcnt vmcnt(0) v_cmpx_eq_f64_e32 0, v[16:17] s_xor_b32 s7, exec_lo, s6 s_cbranch_execz .LBB4_17 ; %bb.12: ; %.preheader217 ; in Loop: Header=BB4_11 Depth=2 v_mov_b32_e32 v20, 0 v_mov_b32_e32 v21, 0 s_and_saveexec_b32 s22, s3 s_cbranch_execz .LBB4_16 ; %bb.13: ; %.lr.ph224 ; in Loop: Header=BB4_11 Depth=2 v_ashrrev_i32_e32 v15, 31, v14 v_mov_b32_e32 v20, 0 v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v24, v26 s_mov_b32 s23, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b64 v[22:23], 3, v[14:15] v_mov_b32_e32 v15, v0 v_add_co_u32 v22, vcc_lo, s10, v22 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v23, vcc_lo, s11, v23, vcc_lo .LBB4_14: ; Parent Loop BB4_7 Depth=1 ; Parent Loop BB4_11 Depth=2 ; => This Inner Loop Header: Depth=3 global_load_b64 v[30:31], v[22:23], off ds_load_b64 v[32:33], v15 v_add_nc_u32_e32 v24, -1, v24 v_add_co_u32 v22, s6, v22, 8 v_add_nc_u32_e32 v15, s12, v15 v_add_co_ci_u32_e64 v23, s6, 0, v23, s6 s_delay_alu instid0(VALU_DEP_4) v_cmp_eq_u32_e32 vcc_lo, 0, v24 s_or_b32 s23, vcc_lo, s23 s_waitcnt vmcnt(0) lgkmcnt(0) v_fma_f64 v[20:21], v[30:31], v[32:33], v[20:21] s_and_not1_b32 exec_lo, exec_lo, s23 s_cbranch_execnz .LBB4_14 ; %bb.15: ; %Flow347 ; in Loop: Header=BB4_11 Depth=2 s_or_b32 exec_lo, exec_lo, s23 .LBB4_16: ; %Flow348 ; in Loop: Header=BB4_11 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s22 .LBB4_17: ; %Flow351 ; in Loop: Header=BB4_11 Depth=2 s_and_not1_saveexec_b32 s7, s7 s_cbranch_execz .LBB4_23 ; %bb.18: ; %.preheader215 ; in Loop: Header=BB4_11 Depth=2 v_mov_b32_e32 v20, 0 v_mov_b32_e32 v21, 0 s_and_saveexec_b32 s22, s3 s_cbranch_execz .LBB4_22 ; %bb.19: ; %.lr.ph227 ; in Loop: Header=BB4_11 Depth=2 v_ashrrev_i32_e32 v15, 31, v14 v_mov_b32_e32 v20, 0 v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v24, v26 s_mov_b32 s23, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b64 v[22:23], 3, v[14:15] v_mov_b32_e32 v15, v0 v_add_co_u32 v22, vcc_lo, s10, v22 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v23, vcc_lo, s11, v23, vcc_lo .p2align 6 .LBB4_20: ; Parent Loop BB4_7 Depth=1 ; Parent Loop BB4_11 Depth=2 ; => This Inner Loop Header: Depth=3 global_load_b64 v[30:31], v[22:23], off ds_load_b64 v[32:33], v15 v_add_nc_u32_e32 v24, -1, v24 v_add_co_u32 v22, vcc_lo, v22, 8 v_add_co_ci_u32_e32 v23, vcc_lo, 0, v23, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s6, 0, v24 s_or_b32 s23, s6, s23 s_waitcnt vmcnt(0) lgkmcnt(0) v_fma_f64 v[32:33], v[16:17], v[30:31], v[32:33] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[20:21], v[30:31], v[32:33], v[20:21] ds_store_b64 v15, v[32:33] v_add_nc_u32_e32 v15, s12, v15 s_and_not1_b32 exec_lo, exec_lo, s23 s_cbranch_execnz .LBB4_20 ; %bb.21: ; %Flow349 ; in Loop: Header=BB4_11 Depth=2 s_or_b32 exec_lo, exec_lo, s23 .LBB4_22: ; %Flow350 ; in Loop: Header=BB4_11 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s22 .LBB4_23: ; %.loopexit216 ; in Loop: Header=BB4_11 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s7 v_mul_f64 v[20:21], v[8:9], v[20:21] ; implicit-def: $vgpr22_vgpr23 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_nlt_f64_e32 vcc_lo, 0, v[20:21] v_cmp_nlt_f64_e64 s6, v[6:7], |v[20:21]| s_or_b32 s6, vcc_lo, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s7, s6 s_xor_b32 s6, exec_lo, s7 s_cbranch_execz .LBB4_27 ; %bb.24: ; in Loop: Header=BB4_11 Depth=2 v_cmp_gt_f64_e32 vcc_lo, 0, v[20:21] v_cmp_lt_f64_e64 s7, v[6:7], |v[20:21]| v_mov_b32_e32 v22, 0 v_mov_b32_e32 v23, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s22, vcc_lo, s7 s_and_saveexec_b32 s7, s22 ; %bb.25: ; in Loop: Header=BB4_11 Depth=2 v_add_f64 v[22:23], v[6:7], v[20:21] ; %bb.26: ; %Flow345 ; in Loop: Header=BB4_11 Depth=2 s_or_b32 exec_lo, exec_lo, s7 .LBB4_27: ; %Flow346 ; in Loop: Header=BB4_11 Depth=2 s_and_not1_saveexec_b32 s6, s6 ; %bb.28: ; in Loop: Header=BB4_11 Depth=2 v_add_f64 v[22:23], v[20:21], -v[6:7] ; %bb.29: ; in Loop: Header=BB4_11 Depth=2 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v24, 0 v_mov_b32_e32 v25, 0x3ff00000 s_and_not1_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB4_36 ; %bb.30: ; %NodeBlock ; in Loop: Header=BB4_11 Depth=2 s_cmp_lt_i32 s15, 4 s_cbranch_scc1 .LBB4_32 ; %bb.31: ; %LeafBlock325 ; in Loop: Header=BB4_11 Depth=2 s_cmp_eq_u32 s15, 4 s_mov_b64 s[6:7], 0 s_cselect_b32 s22, -1, 0 s_cbranch_execz .LBB4_33 s_branch .LBB4_34 .LBB4_32: ; in Loop: Header=BB4_11 Depth=2 s_mov_b32 s22, 0 ; implicit-def: $sgpr6_sgpr7 .LBB4_33: ; %LeafBlock ; in Loop: Header=BB4_11 Depth=2 s_cmp_eq_u32 s15, 2 s_mov_b64 s[6:7], 0 s_cselect_b32 s22, -1, 0 .LBB4_34: ; %Flow342 ; in Loop: Header=BB4_11 Depth=2 v_dual_mov_b32 v25, s7 :: v_dual_mov_b32 v24, s6 s_and_not1_b32 vcc_lo, exec_lo, s22 s_cbranch_vccnz .LBB4_36 ; %bb.35: ; in Loop: Header=BB4_11 Depth=2 v_dual_mov_b32 v25, v9 :: v_dual_mov_b32 v24, v8 .LBB4_36: ; in Loop: Header=BB4_11 Depth=2 s_cmp_lg_u32 s21, 0 s_cselect_b32 s6, -1, 0 s_xor_b32 s7, s4, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s22, s7, s6 s_and_saveexec_b32 s6, s22 s_cbranch_execz .LBB4_38 ; %bb.37: ; in Loop: Header=BB4_11 Depth=2 v_add_f64 v[20:21], v[10:11], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[24:25], null, v[20:21], v[20:21], v[22:23] v_rcp_f64_e32 v[30:31], v[24:25] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[24:25], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_fma_f64 v[32:33], -v[24:25], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[22:23], v[20:21], v[22:23] v_mul_f64 v[34:35], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], -v[24:25], v[34:35], v[32:33] v_div_fmas_f64 v[24:25], v[24:25], v[30:31], v[34:35] s_delay_alu instid0(VALU_DEP_1) v_div_fixup_f64 v[20:21], v[24:25], v[20:21], v[22:23] .LBB4_38: ; in Loop: Header=BB4_11 Depth=2 s_or_b32 exec_lo, exec_lo, s6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_neq_f64_e32 vcc_lo, 0, v[20:21] global_store_b64 v[18:19], v[20:21], off s_and_b32 s6, vcc_lo, s17 s_and_saveexec_b32 s22, s6 s_cbranch_execz .LBB4_41 ; %bb.39: ; %.lr.ph230 ; in Loop: Header=BB4_11 Depth=2 v_ashrrev_i32_e32 v15, 31, v14 s_mov_b32 s23, 0 v_mov_b32_e32 v22, v26 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b64 v[18:19], 3, v[14:15] v_mov_b32_e32 v15, v0 v_add_co_u32 v18, vcc_lo, s10, v18 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v19, vcc_lo, s11, v19, vcc_lo .p2align 6 .LBB4_40: ; Parent Loop BB4_7 Depth=1 ; Parent Loop BB4_11 Depth=2 ; => This Inner Loop Header: Depth=3 global_load_b64 v[23:24], v[18:19], off ds_load_b64 v[30:31], v15 v_add_nc_u32_e32 v22, -1, v22 v_add_co_u32 v18, vcc_lo, v18, 8 v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s6, 0, v22 s_or_b32 s23, s6, s23 s_waitcnt vmcnt(0) lgkmcnt(0) v_fma_f64 v[23:24], -v[20:21], v[23:24], v[30:31] ds_store_b64 v15, v[23:24] v_add_nc_u32_e32 v15, s12, v15 s_and_not1_b32 exec_lo, exec_lo, s23 s_cbranch_execnz .LBB4_40 .LBB4_41: ; %Flow340 ; in Loop: Header=BB4_11 Depth=2 s_or_b32 exec_lo, exec_lo, s22 v_add_f64 v[15:16], v[16:17], -v[20:21] s_cmp_lt_i32 s15, 4 s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[15:16], v[15:16], v[15:16] s_cbranch_scc1 .LBB4_43 ; %bb.42: ; %LeafBlock329 ; in Loop: Header=BB4_11 Depth=2 s_cmp_eq_u32 s15, 4 s_cselect_b32 s6, -1, 0 s_cbranch_execz .LBB4_44 s_branch .LBB4_45 .LBB4_43: ; in Loop: Header=BB4_11 Depth=2 s_mov_b32 s6, 0 .LBB4_44: ; %LeafBlock327 ; in Loop: Header=BB4_11 Depth=2 s_cmp_eq_u32 s15, 2 s_cselect_b32 s6, -1, 0 .LBB4_45: ; %Flow338 ; in Loop: Header=BB4_11 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB4_10 ; %bb.46: ; in Loop: Header=BB4_11 Depth=2 s_cmp_eq_u32 s21, 0 s_cselect_b32 s6, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s6, s7, s6 s_and_saveexec_b32 s7, s6 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s6, exec_lo, s7 s_cbranch_execz .LBB4_50 ; %bb.47: ; in Loop: Header=BB4_11 Depth=2 s_and_saveexec_b32 s7, s5 ; %bb.48: ; in Loop: Header=BB4_11 Depth=2 s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[15:16], v[8:9], v[15:16] ; %bb.49: ; %Flow334 ; in Loop: Header=BB4_11 Depth=2 s_or_b32 exec_lo, exec_lo, s7 .LBB4_50: ; %Flow335 ; in Loop: Header=BB4_11 Depth=2 s_and_not1_saveexec_b32 s6, s6 s_cbranch_execz .LBB4_9 ; %bb.51: ; in Loop: Header=BB4_11 Depth=2 s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[15:16], v[8:9], v[15:16] s_branch .LBB4_9 .LBB4_52: ; %Flow352 ; in Loop: Header=BB4_7 Depth=1 s_or_b32 exec_lo, exec_lo, s20 .LBB4_53: ; %Flow353 ; in Loop: Header=BB4_7 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s19 ; %bb.54: ; %._crit_edge ; in Loop: Header=BB4_7 Depth=1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_nge_f64_e32 vcc_lo, v[12:13], v[3:4] s_add_i32 s18, s18, 1 v_cmp_ge_i32_e64 s6, s18, v28 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s6, vcc_lo, s6 s_and_b32 s6, exec_lo, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s13, s6, s13 s_and_not1_b32 exec_lo, exec_lo, s13 s_cbranch_execnz .LBB4_7 .LBB4_55: ; %Flow355 s_or_b32 exec_lo, exec_lo, s14 s_delay_alu instid0(VALU_DEP_2) v_cmp_lt_i32_e32 vcc_lo, 0, v27 s_mov_b32 s2, 0 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB4_58 ; %bb.56: ; %.lr.ph239.preheader s_load_b64 s[0:1], s[0:1], 0x38 v_lshlrev_b64 v[0:1], 3, v[1:2] v_ashrrev_i32_e32 v6, 31, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b64 v[2:3], 3, v[5:6] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo v_add_co_u32 v2, vcc_lo, s8, v2 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo global_load_b64 v[0:1], v[0:1], off .LBB4_57: ; %.lr.ph239 ; =>This Inner Loop Header: Depth=1 global_load_b64 v[4:5], v[2:3], off v_add_nc_u32_e32 v27, -1, v27 s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v27 s_or_b32 s2, vcc_lo, s2 s_waitcnt vmcnt(0) v_mul_f64 v[4:5], v[0:1], v[4:5] global_store_b64 v[2:3], v[4:5], off v_add_co_u32 v2, s0, v2, 8 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v3, s0, 0, v3, s0 s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB4_57 .LBB4_58: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 136 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 36 .amdhsa_next_free_sgpr 24 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end4: .size _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, .Lfunc_end4-_Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 2264 ; NumSgprs: 26 ; NumVgprs: 36 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 3 ; VGPRBlocks: 4 ; NumSGPRsForWavesPerEU: 26 ; NumVGPRsForWavesPerEU: 36 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii ; -- Begin function _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .globl _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .p2align 8 .type _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii,@function _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii: ; @_Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii ; %bb.0: s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x40 s_load_b32 s4, s[0:1], 0x48 s_waitcnt lgkmcnt(0) s_add_i32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_cmp_eq_u32 s15, s3 s_cselect_b32 s3, s4, s2 v_cmp_gt_i32_e32 vcc_lo, s3, v0 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB5_5 ; %bb.1: s_load_b64 s[4:5], s[0:1], 0x10 v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[3:4], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo global_load_b64 v[5:6], v[5:6], off s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v0, v[5:6] s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 1, v0 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_5 ; %bb.2: s_load_b128 s[4:7], s[0:1], 0x30 s_waitcnt lgkmcnt(0) v_add_co_u32 v5, vcc_lo, s6, v3 v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo v_add_co_u32 v3, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo global_load_b64 v[5:6], v[5:6], off global_load_b64 v[3:4], v[3:4], off s_waitcnt vmcnt(1) v_cvt_i32_f64_e32 v0, v[5:6] s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v4, v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 1, v0 v_cndmask_b32_e64 v5, 0, 1, vcc_lo v_cmp_lt_i32_e32 vcc_lo, v5, v4 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_5 ; %bb.3: ; %.lr.ph.preheader s_load_b128 s[4:7], s[0:1], 0x0 v_lshlrev_b64 v[0:1], 3, v[1:2] s_load_b64 s[0:1], s[0:1], 0x28 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo global_load_b64 v[0:1], v[0:1], off s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v0, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v0, v0, v5 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 3, v[0:1] v_add_co_u32 v0, vcc_lo, s4, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo v_add_co_u32 v2, vcc_lo, s0, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo s_mov_b32 s1, 0 s_set_inst_prefetch_distance 0x1 .p2align 6 .LBB5_4: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 global_load_b64 v[6:7], v[0:1], off global_load_b64 v[8:9], v[2:3], off v_add_nc_u32_e32 v5, 1, v5 s_waitcnt vmcnt(0) v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], v[6:7] v_div_scale_f64 v[16:17], vcc_lo, v[6:7], v[8:9], v[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[12:13], v[10:11] s_waitcnt_depctr 0xfff v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0 v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0 v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[14:15], v[16:17], v[12:13] v_fma_f64 v[10:11], -v[10:11], v[14:15], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[14:15] v_cmp_ge_i32_e32 vcc_lo, v5, v4 s_or_b32 s1, vcc_lo, s1 v_div_fixup_f64 v[6:7], v[10:11], v[8:9], v[6:7] global_store_b64 v[0:1], v[6:7], off v_add_co_u32 v0, s0, v0, 8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v1, s0, 0, v1, s0 v_add_co_u32 v2, s0, v2, 8 v_add_co_ci_u32_e64 v3, s0, 0, v3, s0 s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB5_4 .LBB5_5: ; %.loopexit s_set_inst_prefetch_distance 0x2 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 76 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 18 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end5: .size _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii, .Lfunc_end5-_Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 556 ; NumSgprs: 18 ; NumVgprs: 18 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 18 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii ; -- Begin function _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .globl _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .p2align 8 .type _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii,@function _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii: ; @_Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii ; %bb.0: s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x48 s_load_b32 s4, s[0:1], 0x50 s_waitcnt lgkmcnt(0) s_add_i32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_cmp_eq_u32 s15, s3 s_cselect_b32 s3, s4, s2 v_cmp_gt_i32_e32 vcc_lo, s3, v0 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB6_8 ; %bb.1: s_load_b64 s[4:5], s[0:1], 0x10 v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[0:1], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo global_load_b64 v[2:3], v[2:3], off s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v2, v[2:3] s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 1, v2 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_8 ; %bb.2: s_clause 0x1 s_load_b128 s[8:11], s[0:1], 0x38 s_load_b128 s[4:7], s[0:1], 0x0 s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s10, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s8, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo global_load_b64 v[2:3], v[2:3], off v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo global_load_b64 v[4:5], v[4:5], off global_load_b64 v[6:7], v[0:1], off s_waitcnt vmcnt(2) v_cvt_i32_f64_e32 v2, v[2:3] s_waitcnt vmcnt(1) v_cvt_i32_f64_e32 v1, v[4:5] s_waitcnt vmcnt(0) v_cvt_i32_f64_e32 v0, v[6:7] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_cmp_eq_u32_e64 s2, 1, v2 v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 v_cndmask_b32_e64 v10, 0, 1, s2 s_delay_alu instid0(VALU_DEP_1) v_cmpx_lt_i32_e64 v10, v1 s_cbranch_execz .LBB6_6 ; %bb.3: ; %.lr.ph.preheader s_load_b128 s[8:11], s[0:1], 0x28 v_add_nc_u32_e32 v2, v0, v10 s_mov_b32 s1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[8:9], 3, v[2:3] v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v4, vcc_lo, s4, v8 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v9, vcc_lo s_waitcnt lgkmcnt(0) v_add_co_u32 v6, vcc_lo, s8, v8 v_add_co_ci_u32_e32 v7, vcc_lo, s9, v9, vcc_lo v_add_co_u32 v8, vcc_lo, s10, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo s_set_inst_prefetch_distance 0x1 .p2align 6 .LBB6_4: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 global_load_b64 v[11:12], v[4:5], off global_load_b64 v[13:14], v[6:7], off v_add_nc_u32_e32 v10, 1, v10 s_waitcnt vmcnt(0) v_div_scale_f64 v[15:16], null, v[13:14], v[13:14], v[11:12] v_div_scale_f64 v[21:22], vcc_lo, v[11:12], v[13:14], v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[17:18], v[15:16] s_waitcnt_depctr 0xfff v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0 v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0 v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[19:20], v[21:22], v[17:18] v_fma_f64 v[15:16], -v[15:16], v[19:20], v[21:22] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4) v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[19:20] v_add_co_u32 v6, vcc_lo, v6, 8 v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo v_cmp_ge_i32_e32 vcc_lo, v10, v1 s_or_b32 s1, vcc_lo, s1 v_div_fixup_f64 v[11:12], v[15:16], v[13:14], v[11:12] global_store_b64 v[4:5], v[11:12], off global_load_b64 v[13:14], v[8:9], off v_add_co_u32 v4, s0, v4, 8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v5, s0, 0, v5, s0 v_add_co_u32 v8, s0, v8, 8 v_add_co_ci_u32_e64 v9, s0, 0, v9, s0 s_waitcnt vmcnt(0) v_fma_f64 v[2:3], v[11:12], v[13:14], v[2:3] s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB6_4 ; %bb.5: ; %Flow82 s_set_inst_prefetch_distance 0x2 s_or_b32 exec_lo, exec_lo, s1 .LBB6_6: ; %Flow83 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s3 s_and_b32 exec_lo, exec_lo, s2 s_cbranch_execz .LBB6_8 ; %bb.7: v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[0:1] v_add_co_u32 v0, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo global_load_b64 v[4:5], v[0:1], off s_waitcnt vmcnt(0) v_add_f64 v[2:3], v[4:5], -v[2:3] global_store_b64 v[0:1], v[2:3], off .LBB6_8: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 84 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 23 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end6: .size _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii, .Lfunc_end6-_Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 696 ; NumSgprs: 18 ; NumVgprs: 23 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 23 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .offset: 56 .size: 4 .value_kind: by_value - .offset: 60 .size: 4 .value_kind: by_value - .offset: 64 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 68 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z23predictor_normalizationPdS_S_S_S_S_S_iii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z23predictor_normalizationPdS_S_S_S_S_S_iii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 20 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .offset: 64 .size: 4 .value_kind: by_value - .offset: 68 .size: 4 .value_kind: by_value - .offset: 72 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 76 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 24 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .offset: 56 .size: 4 .value_kind: by_value - .offset: 60 .size: 4 .value_kind: by_value - .offset: 64 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 68 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z21model_fit_preparationPdS_S_S_S_S_S_iii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z21model_fit_preparationPdS_S_S_S_S_S_iii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 17 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 88 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 96 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 104 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 112 .size: 8 .value_kind: global_buffer - .offset: 120 .size: 4 .value_kind: by_value - .offset: 124 .size: 4 .value_kind: by_value - .offset: 128 .size: 4 .value_kind: by_value - .offset: 132 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 136 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .private_segment_fixed_size: 0 .sgpr_count: 25 .sgpr_spill_count: 0 .symbol: _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 37 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 88 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 96 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 104 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 112 .size: 8 .value_kind: global_buffer - .offset: 120 .size: 4 .value_kind: by_value - .offset: 124 .size: 4 .value_kind: by_value - .offset: 128 .size: 4 .value_kind: by_value - .offset: 132 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 136 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .private_segment_fixed_size: 0 .sgpr_count: 26 .sgpr_spill_count: 0 .symbol: _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 36 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .offset: 64 .size: 4 .value_kind: by_value - .offset: 68 .size: 4 .value_kind: by_value - .offset: 72 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 76 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 18 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .offset: 72 .size: 4 .value_kind: by_value - .offset: 76 .size: 4 .value_kind: by_value - .offset: 80 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 84 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 23 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "8b767290955cb5f6d829cc319289a569e00a29cf.hip" .globl _Z38__device_stub__predictor_normalizationPdS_S_S_S_S_S_iii # -- Begin function _Z38__device_stub__predictor_normalizationPdS_S_S_S_S_S_iii .p2align 4, 0x90 .type _Z38__device_stub__predictor_normalizationPdS_S_S_S_S_S_iii,@function _Z38__device_stub__predictor_normalizationPdS_S_S_S_S_S_iii: # @_Z38__device_stub__predictor_normalizationPdS_S_S_S_S_S_iii .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movq %r9, 48(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z23predictor_normalizationPdS_S_S_S_S_S_iii, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end0: .size _Z38__device_stub__predictor_normalizationPdS_S_S_S_S_S_iii, .Lfunc_end0-_Z38__device_stub__predictor_normalizationPdS_S_S_S_S_S_iii .cfi_endproc # -- End function .globl _Z40__device_stub__predictor_standardizationPdS_S_S_S_S_S_S_iii # -- Begin function _Z40__device_stub__predictor_standardizationPdS_S_S_S_S_S_S_iii .p2align 4, 0x90 .type _Z40__device_stub__predictor_standardizationPdS_S_S_S_S_S_S_iii,@function _Z40__device_stub__predictor_standardizationPdS_S_S_S_S_S_S_iii: # @_Z40__device_stub__predictor_standardizationPdS_S_S_S_S_S_S_iii .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movq %r9, 48(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) leaq 224(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z25predictor_standardizationPdS_S_S_S_S_S_S_iii, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end1: .size _Z40__device_stub__predictor_standardizationPdS_S_S_S_S_S_S_iii, .Lfunc_end1-_Z40__device_stub__predictor_standardizationPdS_S_S_S_S_S_S_iii .cfi_endproc # -- End function .globl _Z36__device_stub__model_fit_preparationPdS_S_S_S_S_S_iii # -- Begin function _Z36__device_stub__model_fit_preparationPdS_S_S_S_S_S_iii .p2align 4, 0x90 .type _Z36__device_stub__model_fit_preparationPdS_S_S_S_S_S_iii,@function _Z36__device_stub__model_fit_preparationPdS_S_S_S_S_S_iii: # @_Z36__device_stub__model_fit_preparationPdS_S_S_S_S_S_iii .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movq %r9, 48(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z21model_fit_preparationPdS_S_S_S_S_S_iii, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end2: .size _Z36__device_stub__model_fit_preparationPdS_S_S_S_S_S_iii, .Lfunc_end2-_Z36__device_stub__model_fit_preparationPdS_S_S_S_S_S_iii .cfi_endproc # -- End function .globl _Z24__device_stub__model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii # -- Begin function _Z24__device_stub__model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .p2align 4, 0x90 .type _Z24__device_stub__model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii,@function _Z24__device_stub__model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii: # @_Z24__device_stub__model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .cfi_startproc # %bb.0: subq $248, %rsp .cfi_def_cfa_offset 256 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movq %r9, 48(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 256(%rsp), %rax movq %rax, 144(%rsp) leaq 264(%rsp), %rax movq %rax, 152(%rsp) leaq 272(%rsp), %rax movq %rax, 160(%rsp) leaq 280(%rsp), %rax movq %rax, 168(%rsp) leaq 288(%rsp), %rax movq %rax, 176(%rsp) leaq 296(%rsp), %rax movq %rax, 184(%rsp) leaq 304(%rsp), %rax movq %rax, 192(%rsp) leaq 312(%rsp), %rax movq %rax, 200(%rsp) leaq 320(%rsp), %rax movq %rax, 208(%rsp) leaq 328(%rsp), %rax movq %rax, 216(%rsp) leaq 336(%rsp), %rax movq %rax, 224(%rsp) leaq 344(%rsp), %rax movq %rax, 232(%rsp) leaq 352(%rsp), %rax movq %rax, 240(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $264, %rsp # imm = 0x108 .cfi_adjust_cfa_offset -264 retq .Lfunc_end3: .size _Z24__device_stub__model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, .Lfunc_end3-_Z24__device_stub__model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .cfi_endproc # -- End function .globl _Z38__device_stub__model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii # -- Begin function _Z38__device_stub__model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .p2align 4, 0x90 .type _Z38__device_stub__model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii,@function _Z38__device_stub__model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii: # @_Z38__device_stub__model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .cfi_startproc # %bb.0: subq $248, %rsp .cfi_def_cfa_offset 256 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movq %r9, 48(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 256(%rsp), %rax movq %rax, 144(%rsp) leaq 264(%rsp), %rax movq %rax, 152(%rsp) leaq 272(%rsp), %rax movq %rax, 160(%rsp) leaq 280(%rsp), %rax movq %rax, 168(%rsp) leaq 288(%rsp), %rax movq %rax, 176(%rsp) leaq 296(%rsp), %rax movq %rax, 184(%rsp) leaq 304(%rsp), %rax movq %rax, 192(%rsp) leaq 312(%rsp), %rax movq %rax, 200(%rsp) leaq 320(%rsp), %rax movq %rax, 208(%rsp) leaq 328(%rsp), %rax movq %rax, 216(%rsp) leaq 336(%rsp), %rax movq %rax, 224(%rsp) leaq 344(%rsp), %rax movq %rax, 232(%rsp) leaq 352(%rsp), %rax movq %rax, 240(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $264, %rsp # imm = 0x108 .cfi_adjust_cfa_offset -264 retq .Lfunc_end4: .size _Z38__device_stub__model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, .Lfunc_end4-_Z38__device_stub__model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .cfi_endproc # -- End function .globl _Z52__device_stub__predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii # -- Begin function _Z52__device_stub__predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .p2align 4, 0x90 .type _Z52__device_stub__predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii,@function _Z52__device_stub__predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii: # @_Z52__device_stub__predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movq %r9, 48(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) leaq 224(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end5: .size _Z52__device_stub__predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii, .Lfunc_end5-_Z52__device_stub__predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .cfi_endproc # -- End function .globl _Z54__device_stub__predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii # -- Begin function _Z54__device_stub__predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .p2align 4, 0x90 .type _Z54__device_stub__predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii,@function _Z54__device_stub__predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii: # @_Z54__device_stub__predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .cfi_startproc # %bb.0: subq $200, %rsp .cfi_def_cfa_offset 208 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movq %r9, 48(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 208(%rsp), %rax movq %rax, 144(%rsp) leaq 216(%rsp), %rax movq %rax, 152(%rsp) leaq 224(%rsp), %rax movq %rax, 160(%rsp) leaq 232(%rsp), %rax movq %rax, 168(%rsp) leaq 240(%rsp), %rax movq %rax, 176(%rsp) leaq 248(%rsp), %rax movq %rax, 184(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $216, %rsp .cfi_adjust_cfa_offset -216 retq .Lfunc_end6: .size _Z54__device_stub__predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii, .Lfunc_end6-_Z54__device_stub__predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB7_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB7_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z23predictor_normalizationPdS_S_S_S_S_S_iii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z25predictor_standardizationPdS_S_S_S_S_S_S_iii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z21model_fit_preparationPdS_S_S_S_S_S_iii, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, %esi movl $.L__unnamed_4, %edx movl $.L__unnamed_4, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, %esi movl $.L__unnamed_5, %edx movl $.L__unnamed_5, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii, %esi movl $.L__unnamed_6, %edx movl $.L__unnamed_6, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii, %esi movl $.L__unnamed_7, %edx movl $.L__unnamed_7, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end7: .size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB8_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB8_2: retq .Lfunc_end8: .size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor .cfi_endproc # -- End function .type _Z23predictor_normalizationPdS_S_S_S_S_S_iii,@object # @_Z23predictor_normalizationPdS_S_S_S_S_S_iii .section .rodata,"a",@progbits .globl _Z23predictor_normalizationPdS_S_S_S_S_S_iii .p2align 3, 0x0 _Z23predictor_normalizationPdS_S_S_S_S_S_iii: .quad _Z38__device_stub__predictor_normalizationPdS_S_S_S_S_S_iii .size _Z23predictor_normalizationPdS_S_S_S_S_S_iii, 8 .type _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii,@object # @_Z25predictor_standardizationPdS_S_S_S_S_S_S_iii .globl _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii .p2align 3, 0x0 _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii: .quad _Z40__device_stub__predictor_standardizationPdS_S_S_S_S_S_S_iii .size _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii, 8 .type _Z21model_fit_preparationPdS_S_S_S_S_S_iii,@object # @_Z21model_fit_preparationPdS_S_S_S_S_S_iii .globl _Z21model_fit_preparationPdS_S_S_S_S_S_iii .p2align 3, 0x0 _Z21model_fit_preparationPdS_S_S_S_S_S_iii: .quad _Z36__device_stub__model_fit_preparationPdS_S_S_S_S_S_iii .size _Z21model_fit_preparationPdS_S_S_S_S_S_iii, 8 .type _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii,@object # @_Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .globl _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .p2align 3, 0x0 _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii: .quad _Z24__device_stub__model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .size _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, 8 .type _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii,@object # @_Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .globl _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .p2align 3, 0x0 _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii: .quad _Z38__device_stub__model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .size _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii, 8 .type _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii,@object # @_Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .globl _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .p2align 3, 0x0 _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii: .quad _Z52__device_stub__predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .size _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii, 8 .type _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii,@object # @_Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .globl _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .p2align 3, 0x0 _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii: .quad _Z54__device_stub__predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .size _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z23predictor_normalizationPdS_S_S_S_S_S_iii" .size .L__unnamed_1, 45 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z25predictor_standardizationPdS_S_S_S_S_S_S_iii" .size .L__unnamed_2, 49 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z21model_fit_preparationPdS_S_S_S_S_S_iii" .size .L__unnamed_3, 43 .type .L__unnamed_4,@object # @3 .L__unnamed_4: .asciz "_Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii" .size .L__unnamed_4, 47 .type .L__unnamed_5,@object # @4 .L__unnamed_5: .asciz "_Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii" .size .L__unnamed_5, 62 .type .L__unnamed_6,@object # @5 .L__unnamed_6: .asciz "_Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii" .size .L__unnamed_6, 61 .type .L__unnamed_7,@object # @6 .L__unnamed_7: .asciz "_Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii" .size .L__unnamed_7, 65 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z38__device_stub__predictor_normalizationPdS_S_S_S_S_S_iii .addrsig_sym _Z40__device_stub__predictor_standardizationPdS_S_S_S_S_S_S_iii .addrsig_sym _Z36__device_stub__model_fit_preparationPdS_S_S_S_S_S_iii .addrsig_sym _Z24__device_stub__model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .addrsig_sym _Z38__device_stub__model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .addrsig_sym _Z52__device_stub__predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .addrsig_sym _Z54__device_stub__predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z23predictor_normalizationPdS_S_S_S_S_S_iii .addrsig_sym _Z25predictor_standardizationPdS_S_S_S_S_S_S_iii .addrsig_sym _Z21model_fit_preparationPdS_S_S_S_S_S_iii .addrsig_sym _Z9model_fitPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .addrsig_sym _Z23model_fit_shared_memoryPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_iiii .addrsig_sym _Z37predictor_coefficient_unnormalizationPdS_S_S_S_S_S_S_iii .addrsig_sym _Z39predictor_coefficient_unstandardizationPdS_S_S_S_S_S_S_S_iii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z6matSumPfS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.Y ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R3, SR_TID.Y ; S2R R2, SR_CTAID.X ; S2R R5, SR_TID.X ; IMAD R0, R0, c[0x0][0x4], R3 ; IMAD R3, R2, c[0x0][0x0], R5 ; LEA R0, R0, R3, 0xa ; IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; LDG.E R2, [R2.64] ; LDG.E R5, [R4.64] ; IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; FADD R9, R2, R5 ; STG.E [R6.64], R9 ; EXIT ; BRA 0x120; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00099df6_00000000-6_a14767193a3b720d376f4367690d8aaacf394edb.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "ROW %d:" .LC1: .string "%.3f\t" .LC2: .string "\n" .text .globl _Z8printMatPA1024_f .type _Z8printMatPA1024_f, @function _Z8printMatPA1024_f: .LFB2058: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $8, %rsp .cfi_def_cfa_offset 64 leaq 4096(%rdi), %rbp movl $0, %r13d leaq .LC0(%rip), %r15 leaq .LC1(%rip), %r12 leaq .LC2(%rip), %r14 .L5: addl $1, %r13d movl %r13d, %edx movq %r15, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq -4096(%rbp), %rbx .L4: pxor %xmm0, %xmm0 cvtss2sd (%rbx), %xmm0 movq %r12, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L4 movq %r14, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4096, %rbp cmpl $1024, %r13d jne .L5 addq $8, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z8printMatPA1024_f, .-_Z8printMatPA1024_f .globl _Z7initMatPA1024_fS0_ .type _Z7initMatPA1024_fS0_, @function _Z7initMatPA1024_fS0_: .LFB2059: .cfi_startproc endbr64 movq %rdi, %r8 movq %rsi, %rdi movq %r8, %rsi addq $4194304, %r8 movss .LC3(%rip), %xmm0 .L10: movq %rsi, %rcx movq %rdi, %rdx movl $0, %eax .L11: movss %xmm0, (%rcx,%rax) movss %xmm0, (%rdx,%rax) addq $4, %rax cmpq $4096, %rax jne .L11 addq $4096, %rsi addq $4096, %rdi cmpq %r8, %rsi jne .L10 ret .cfi_endproc .LFE2059: .size _Z7initMatPA1024_fS0_, .-_Z7initMatPA1024_fS0_ .globl _Z29__device_stub__Z6matSumPfS_S_PfS_S_ .type _Z29__device_stub__Z6matSumPfS_S_PfS_S_, @function _Z29__device_stub__Z6matSumPfS_S_PfS_S_: .LFB2084: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L18 .L14: movq 120(%rsp), %rax subq %fs:40, %rax jne .L19 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L18: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6matSumPfS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L14 .L19: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z29__device_stub__Z6matSumPfS_S_PfS_S_, .-_Z29__device_stub__Z6matSumPfS_S_PfS_S_ .globl _Z6matSumPfS_S_ .type _Z6matSumPfS_S_, @function _Z6matSumPfS_S_: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z29__device_stub__Z6matSumPfS_S_PfS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z6matSumPfS_S_, .-_Z6matSumPfS_S_ .section .rodata.str1.1 .LC5: .string " \n Time taken is %f \n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $80, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax call clock@PLT movq %rax, %rbx leaq 24(%rsp), %rdi movl $4194304, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $4194304, %esi call cudaMalloc@PLT leaq 40(%rsp), %rdi movl $4194304, %esi call cudaMalloc@PLT leaq _ZZ4mainE1B(%rip), %rbp movq %rbp, %rsi leaq _ZZ4mainE1A(%rip), %r12 movq %r12, %rdi call _Z7initMatPA1024_fS0_ movl $1, %ecx movl $4194304, %edx movq %r12, %rsi movq 24(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $4194304, %edx movq %rbp, %rsi movq 32(%rsp), %rdi call cudaMemcpy@PLT movl $32, 48(%rsp) movl $32, 52(%rsp) movl $32, 60(%rsp) movl $32, 64(%rsp) movl $0, %r9d movl $0, %r8d movq 60(%rsp), %rdx movl $1, %ecx movq 48(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L26 .L23: movl $2, %ecx movl $4194304, %edx movq 40(%rsp), %rsi leaq _ZZ4mainE1C(%rip), %rbp movq %rbp, %rdi call cudaMemcpy@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT call clock@PLT subq %rbx, %rax pxor %xmm0, %xmm0 cvtsi2sdq %rax, %xmm0 divsd .LC4(%rip), %xmm0 movsd %xmm0, 8(%rsp) movq %rbp, %rdi call _Z8printMatPA1024_f movsd 8(%rsp), %xmm0 leaq .LC5(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L27 movl $0, %eax addq $80, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L26: .cfi_restore_state movq 40(%rsp), %rdx movq 32(%rsp), %rsi movq 24(%rsp), %rdi call _Z29__device_stub__Z6matSumPfS_S_PfS_S_ jmp .L23 .L27: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC6: .string "_Z6matSumPfS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z6matSumPfS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZZ4mainE1C .comm _ZZ4mainE1C,4194304,32 .local _ZZ4mainE1B .comm _ZZ4mainE1B,4194304,32 .local _ZZ4mainE1A .comm _ZZ4mainE1A,4194304,32 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC3: .long 1065353216 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC4: .long 0 .long 1093567616 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6matSumPfS_S_ ; -- Begin function _Z6matSumPfS_S_ .globl _Z6matSumPfS_S_ .p2align 8 .type _Z6matSumPfS_S_,@function _Z6matSumPfS_S_: ; @_Z6matSumPfS_S_ ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b128 s[4:7], s[0:1], 0x0 v_bfe_u32 v1, v0, 10, 10 v_and_b32_e32 v0, 0x3ff, v0 s_load_b64 s[0:1], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_mul_i32 s15, s15, s3 s_mul_i32 s14, s14, s2 v_add_lshl_u32 v1, s15, v1, 10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add3_u32 v0, s14, v0, v1 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[0:1] v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_add_f32_e32 v2, v2, v3 global_store_b32 v[0:1], v2, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6matSumPfS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6matSumPfS_S_, .Lfunc_end0-_Z6matSumPfS_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 188 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6matSumPfS_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6matSumPfS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "a14767193a3b720d376f4367690d8aaacf394edb.hip" .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI0_0: .quad 0x412e848000000000 # double 1.0E+6 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $128, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 callq clock movq %rax, %rbx leaq 16(%rsp), %rdi movl $4194304, %esi # imm = 0x400000 callq hipMalloc leaq 8(%rsp), %rdi movl $4194304, %esi # imm = 0x400000 callq hipMalloc movq %rsp, %rdi movl $4194304, %esi # imm = 0x400000 callq hipMalloc xorl %eax, %eax xorl %ecx, %ecx .p2align 4, 0x90 .LBB0_1: # %.preheader.i # =>This Loop Header: Depth=1 # Child Loop BB0_2 Depth 2 movq $-4096, %rdx # imm = 0xF000 .p2align 4, 0x90 .LBB0_2: # Parent Loop BB0_1 Depth=1 # => This Inner Loop Header: Depth=2 movl $1065353216, _ZZ4mainE1A+4096(%rax,%rdx) # imm = 0x3F800000 movl $1065353216, _ZZ4mainE1B+4096(%rax,%rdx) # imm = 0x3F800000 addq $4, %rdx jne .LBB0_2 # %bb.3: # in Loop: Header=BB0_1 Depth=1 incq %rcx addq $4096, %rax # imm = 0x1000 cmpq $1024, %rcx # imm = 0x400 jne .LBB0_1 # %bb.4: # %_Z7initMatPA1024_fS0_.exit movq 16(%rsp), %rdi movl $_ZZ4mainE1A, %esi movl $4194304, %edx # imm = 0x400000 movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi movl $_ZZ4mainE1B, %esi movl $4194304, %edx # imm = 0x400000 movl $1, %ecx callq hipMemcpy movabsq $137438953504, %rdi # imm = 0x2000000020 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB0_6 # %bb.5: movq 16(%rsp), %rax movq 8(%rsp), %rcx movq (%rsp), %rdx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movq %rdx, 72(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z6matSumPfS_S_, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB0_6: movq (%rsp), %rsi movl $_ZZ4mainE1C, %r12d movl $_ZZ4mainE1C, %edi movl $4194304, %edx # imm = 0x400000 movl $2, %ecx callq hipMemcpy movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree callq clock movq %rax, %r14 xorl %r15d, %r15d .p2align 4, 0x90 .LBB0_7: # =>This Loop Header: Depth=1 # Child Loop BB0_8 Depth 2 incq %r15 movl $.L.str.1, %edi movl %r15d, %esi xorl %eax, %eax callq printf xorl %r13d, %r13d .p2align 4, 0x90 .LBB0_8: # Parent Loop BB0_7 Depth=1 # => This Inner Loop Header: Depth=2 movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.2, %edi movb $1, %al callq printf incq %r13 cmpq $1024, %r13 # imm = 0x400 jne .LBB0_8 # %bb.9: # in Loop: Header=BB0_7 Depth=1 movl $10, %edi callq putchar@PLT addq $4096, %r12 # imm = 0x1000 cmpq $1024, %r15 # imm = 0x400 jne .LBB0_7 # %bb.10: # %_Z8printMatPA1024_f.exit subq %rbx, %r14 xorps %xmm0, %xmm0 cvtsi2sd %r14, %xmm0 divsd .LCPI0_0(%rip), %xmm0 movl $.L.str, %edi movb $1, %al callq printf xorl %eax, %eax addq $128, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size main, .Lfunc_end0-main .cfi_endproc # -- End function .globl _Z7initMatPA1024_fS0_ # -- Begin function _Z7initMatPA1024_fS0_ .p2align 4, 0x90 .type _Z7initMatPA1024_fS0_,@function _Z7initMatPA1024_fS0_: # @_Z7initMatPA1024_fS0_ .cfi_startproc # %bb.0: xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_2: # Parent Loop BB1_1 Depth=1 # => This Inner Loop Header: Depth=2 movl $1065353216, (%rdi,%rcx,4) # imm = 0x3F800000 movl $1065353216, (%rsi,%rcx,4) # imm = 0x3F800000 incq %rcx cmpq $1024, %rcx # imm = 0x400 jne .LBB1_2 # %bb.3: # in Loop: Header=BB1_1 Depth=1 incq %rax addq $4096, %rsi # imm = 0x1000 addq $4096, %rdi # imm = 0x1000 cmpq $1024, %rax # imm = 0x400 jne .LBB1_1 # %bb.4: retq .Lfunc_end1: .size _Z7initMatPA1024_fS0_, .Lfunc_end1-_Z7initMatPA1024_fS0_ .cfi_endproc # -- End function .globl _Z21__device_stub__matSumPfS_S_ # -- Begin function _Z21__device_stub__matSumPfS_S_ .p2align 4, 0x90 .type _Z21__device_stub__matSumPfS_S_,@function _Z21__device_stub__matSumPfS_S_: # @_Z21__device_stub__matSumPfS_S_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6matSumPfS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end2: .size _Z21__device_stub__matSumPfS_S_, .Lfunc_end2-_Z21__device_stub__matSumPfS_S_ .cfi_endproc # -- End function .globl _Z8printMatPA1024_f # -- Begin function _Z8printMatPA1024_f .p2align 4, 0x90 .type _Z8printMatPA1024_f,@function _Z8printMatPA1024_f: # @_Z8printMatPA1024_f .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx xorl %r14d, %r14d .p2align 4, 0x90 .LBB3_1: # =>This Loop Header: Depth=1 # Child Loop BB3_2 Depth 2 incq %r14 movl $.L.str.1, %edi movl %r14d, %esi xorl %eax, %eax callq printf xorl %r15d, %r15d .p2align 4, 0x90 .LBB3_2: # Parent Loop BB3_1 Depth=1 # => This Inner Loop Header: Depth=2 movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.2, %edi movb $1, %al callq printf incq %r15 cmpq $1024, %r15 # imm = 0x400 jne .LBB3_2 # %bb.3: # in Loop: Header=BB3_1 Depth=1 movl $10, %edi callq putchar@PLT addq $4096, %rbx # imm = 0x1000 cmpq $1024, %r14 # imm = 0x400 jne .LBB3_1 # %bb.4: popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size _Z8printMatPA1024_f, .Lfunc_end3-_Z8printMatPA1024_f .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6matSumPfS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _ZZ4mainE1A,@object # @_ZZ4mainE1A .local _ZZ4mainE1A .comm _ZZ4mainE1A,4194304,16 .type _ZZ4mainE1B,@object # @_ZZ4mainE1B .local _ZZ4mainE1B .comm _ZZ4mainE1B,4194304,16 .type _ZZ4mainE1C,@object # @_ZZ4mainE1C .local _ZZ4mainE1C .comm _ZZ4mainE1C,4194304,16 .type _Z6matSumPfS_S_,@object # @_Z6matSumPfS_S_ .section .rodata,"a",@progbits .globl _Z6matSumPfS_S_ .p2align 3, 0x0 _Z6matSumPfS_S_: .quad _Z21__device_stub__matSumPfS_S_ .size _Z6matSumPfS_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz " \n Time taken is %f \n" .size .L.str, 22 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "ROW %d:" .size .L.str.1, 8 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "%.3f\t" .size .L.str.2, 6 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z6matSumPfS_S_" .size .L__unnamed_1, 16 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__matSumPfS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _ZZ4mainE1A .addrsig_sym _ZZ4mainE1B .addrsig_sym _ZZ4mainE1C .addrsig_sym _Z6matSumPfS_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z7multMatPfS_S_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_TID.X ; ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; HFMA2.MMA R18, -RZ, RZ, 0, 2.384185791015625e-07 ; MOV R16, c[0x0][0x17c] ; S2R R5, SR_CTAID.X ; ULDC.64 UR4, c[0x0][0x118] ; SHF.L.U32 R16, R16, 0x5, RZ ; S2R R7, SR_TID.Y ; S2R R6, SR_CTAID.Y ; @!P0 MOV R23, RZ ; LEA R2, R5, R0, 0x5 ; IMAD R3, R7, c[0x0][0x17c], R2 ; IMAD R3, R16, R6, R3 ; IMAD.WIDE R18, R3, R18, c[0x0][0x170] ; @!P0 BRA 0x740 ; LEA R3, R6.reuse, R7, 0x5 ; IMAD R4, R7.reuse, c[0x0][0x17c], R0.reuse ; MOV R21, 0x4 ; IMAD R6, R6, c[0x0][0x178], RZ ; SHF.L.U32 R7, R7, 0x7, RZ ; IMAD R3, R3, c[0x0][0x178], R0 ; LEA R20, R5, R4, 0x5 ; SHF.L.U32 R6, R6, 0x5, RZ ; IMAD.WIDE R2, R3, R21, c[0x0][0x160] ; MOV R23, RZ ; LEA R4, R0, R7, 0x2 ; IMAD.WIDE R20, R20, R21, c[0x0][0x168] ; MOV R5, R3 ; IADD3 R3, R6, c[0x0][0x178], RZ ; MOV R25, R5 ; LDG.E R29, [R20.64] ; MOV R24, R2 ; LDG.E R25, [R24.64] ; IADD3 R6, R6, 0x20, RZ ; IADD3 R2, P1, R2, 0x80, RZ ; IMAD.WIDE R20, R16, 0x4, R20 ; ISETP.GE.AND P0, PT, R6, R3, PT ; IADD3.X R5, RZ, R5, RZ, P1, !PT ; STS [R4+0x1000], R29 ; STS [R4], R25 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDS R26, [R0.X4+0x1000] ; LDS.128 R12, [R7] ; LDS R28, [R0.X4+0x1080] ; LDS R27, [R0.X4+0x1100] ; LDS R22, [R0.X4+0x1180] ; LDS R17, [R0.X4+0x1200] ; LDS.128 R8, [R7+0x10] ; LDS R24, [R0.X4+0x1280] ; LDS R25, [R0.X4+0x1300] ; FFMA R12, R26, R12, R23 ; LDS R26, [R0.X4+0x1380] ; FFMA R12, R28, R13, R12 ; LDS R23, [R0.X4+0x1400] ; FFMA R12, R27, R14, R12 ; LDS R28, [R0.X4+0x1580] ; FFMA R22, R22, R15, R12 ; LDS.128 R12, [R7+0x20] ; FFMA R8, R17, R8, R22 ; LDS R22, [R0.X4+0x1480] ; FFMA R8, R24, R9, R8 ; LDS R17, [R0.X4+0x1500] ; FFMA R8, R25, R10, R8 ; LDS R25, [R0.X4+0x1600] ; LDS R24, [R0.X4+0x1780] ; FFMA R26, R26, R11, R8 ; LDS.128 R8, [R7+0x30] ; FFMA R12, R23, R12, R26 ; LDS R26, [R0.X4+0x1680] ; LDS R23, [R0.X4+0x1700] ; FFMA R12, R22, R13, R12 ; LDS R22, [R0.X4+0x1880] ; FFMA R12, R17, R14, R12 ; LDS R17, [R0.X4+0x1800] ; FFMA R28, R28, R15, R12 ; LDS.128 R12, [R7+0x40] ; FFMA R8, R25, R8, R28 ; LDS R25, [R0.X4+0x1900] ; LDS R28, [R0.X4+0x1b80] ; FFMA R8, R26, R9, R8 ; LDS R26, [R0.X4+0x1980] ; FFMA R8, R23, R10, R8 ; LDS R23, [R0.X4+0x1a00] ; FFMA R24, R24, R11, R8 ; LDS.128 R8, [R7+0x50] ; FFMA R12, R17, R12, R24 ; LDS R24, [R0.X4+0x1a80] ; FFMA R12, R22, R13, R12 ; LDS R17, [R0.X4+0x1b00] ; LDS R22, [R0.X4+0x1c80] ; FFMA R12, R25, R14, R12 ; LDS R25, [R0.X4+0x1c00] ; FFMA R26, R26, R15, R12 ; LDS.128 R12, [R7+0x60] ; FFMA R8, R23, R8, R26 ; LDS R23, [R0.X4+0x1d00] ; FFMA R8, R24, R9, R8 ; LDS R24, [R0.X4+0x1d80] ; FFMA R8, R17, R10, R8 ; LDS R17, [R0.X4+0x1e00] ; FFMA R28, R28, R11, R8 ; LDS.128 R8, [R7+0x70] ; FFMA R28, R25, R12, R28 ; LDS R12, [R0.X4+0x1e80] ; FFMA R13, R22, R13, R28 ; LDS R25, [R0.X4+0x1f00] ; FFMA R13, R23, R14, R13 ; LDS R22, [R0.X4+0x1f80] ; FFMA R13, R24, R15, R13 ; FFMA R8, R17, R8, R13 ; FFMA R8, R12, R9, R8 ; FFMA R8, R25, R10, R8 ; FFMA R23, R22, R11, R8 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P0 BRA 0x1e0 ; STG.E [R18.64], R23 ; EXIT ; BRA 0x760; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000ea3d5_00000000-6_5a30094893d94381b0bd7341211ed99a757c04b1.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z32__device_stub__Z7multMatPfS_S_iiPfS_S_ii .type _Z32__device_stub__Z7multMatPfS_S_iiPfS_S_ii, @function _Z32__device_stub__Z7multMatPfS_S_iiPfS_S_ii: .LFB2082: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7multMatPfS_S_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z32__device_stub__Z7multMatPfS_S_iiPfS_S_ii, .-_Z32__device_stub__Z7multMatPfS_S_iiPfS_S_ii .globl _Z7multMatPfS_S_ii .type _Z7multMatPfS_S_ii, @function _Z7multMatPfS_S_ii: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z32__device_stub__Z7multMatPfS_S_iiPfS_S_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z7multMatPfS_S_ii, .-_Z7multMatPfS_S_ii .section .rodata.str1.1,"aMS",@progbits,1 .LC3: .string "Time= %2.5f\n" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC9: .string "Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $88, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $4096, %edi call malloc@PLT movq %rax, %r13 movl $4096, %edi call malloc@PLT movq %rax, %r12 movl $4096, %edi call malloc@PLT movq %rax, %rbp movl $0, %eax movss .LC0(%rip), %xmm0 .L12: movss %xmm0, 0(%r13,%rax) movss %xmm0, (%r12,%rax) addq $4, %rax cmpq $4096, %rax jne .L12 leaq 8(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT movl $1, %ecx movl $4096, %edx movq %r13, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $4096, %edx movq %r12, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 32(%rsp), %rdi call cudaEventCreate@PLT leaq 40(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 32(%rsp), %rdi call cudaEventRecord@PLT movl $100000, %ebx jmp .L14 .L13: subl $1, %ebx je .L24 .L14: movl $32, 48(%rsp) movl $32, 52(%rsp) movl 56(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 48(%rsp), %rdx movq 60(%rsp), %rdi movl 68(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L13 movl $32, %r8d movl $32, %ecx movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z32__device_stub__Z7multMatPfS_S_iiPfS_S_ii jmp .L13 .L24: movl $0, %esi movq 40(%rsp), %rdi call cudaEventRecord@PLT movq 40(%rsp), %rdi call cudaEventSynchronize@PLT movl $0x00000000, 4(%rsp) leaq 4(%rsp), %rdi movq 40(%rsp), %rdx movq 32(%rsp), %rsi call cudaEventElapsedTime@PLT movss 4(%rsp), %xmm0 divss .LC2(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 leaq .LC3(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl $2, %ecx movl $4096, %edx movq 24(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT movl $0, %ebx jmp .L17 .L15: addq $1, %rbx cmpq $1024, %rbx je .L25 .L17: movss 0(%rbp,%rbx,4), %xmm0 movaps %xmm0, %xmm1 subss .LC4(%rip), %xmm1 andps .LC5(%rip), %xmm1 cvtss2sd %xmm1, %xmm1 movaps %xmm0, %xmm2 andps .LC5(%rip), %xmm2 cvtss2sd %xmm2, %xmm2 divsd %xmm2, %xmm1 mulsd .LC6(%rip), %xmm1 comisd .LC7(%rip), %xmm1 jbe .L15 cvtss2sd %xmm0, %xmm0 movsd .LC7(%rip), %xmm2 movsd .LC8(%rip), %xmm1 movl %ebx, %edx leaq .LC9(%rip), %rsi movl $2, %edi movl $3, %eax call __printf_chk@PLT jmp .L15 .L25: movq %r13, %rdi call free@PLT movq %r12, %rdi call free@PLT movq %rbp, %rdi call free@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L26 movl $0, %eax addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L26: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC10: .string "_Z7multMatPfS_S_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC10(%rip), %rdx movq %rdx, %rcx leaq _Z7multMatPfS_S_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1065353216 .align 4 .LC2: .long 1203982336 .align 4 .LC4: .long 1107296256 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC5: .long 2147483647 .long 0 .long 0 .long 0 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC6: .long 0 .long 1067450368 .align 8 .LC7: .long -1598689907 .long 1051772663 .align 8 .LC8: .long 0 .long 1077936128 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z7multMatPfS_S_ii ; -- Begin function _Z7multMatPfS_S_ii .globl _Z7multMatPfS_S_ii .p2align 8 .type _Z7multMatPfS_S_ii,@function _Z7multMatPfS_S_ii: ; @_Z7multMatPfS_S_ii ; %bb.0: s_load_b64 s[2:3], s[0:1], 0x18 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v0, v0, 10, 10 s_lshl_b32 s9, s14, 5 s_waitcnt lgkmcnt(0) s_lshl_b32 s8, s3, 5 s_cmp_lt_i32 s2, 1 s_cbranch_scc1 .LBB0_5 ; %bb.1: ; %.lr.ph s_load_b128 s[4:7], s[0:1], 0x0 v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2] v_lshlrev_b32_e32 v7, 2, v1 v_lshlrev_b32_e32 v5, 7, v0 s_mul_i32 s10, s2, s15 s_mov_b32 s11, s9 s_lshl_b32 s10, s10, 5 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2] v_mov_b32_e32 v4, 0 v_or_b32_e32 v6, 0x1000, v7 v_add_nc_u32_e32 v7, v5, v7 s_add_i32 s2, s10, s2 v_add_nc_u32_e32 v8, v6, v5 s_set_inst_prefetch_distance 0x1 .p2align 6 .LBB0_2: ; =>This Loop Header: Depth=1 ; Child Loop BB0_3 Depth 2 v_add_nc_u32_e32 v9, s10, v2 v_add_nc_u32_e32 v11, s11, v3 s_mov_b32 s12, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v10, 31, v9 v_ashrrev_i32_e32 v12, 31, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[9:10], 2, v[9:10] v_lshlrev_b64 v[11:12], 2, v[11:12] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v9, vcc_lo, s4, v9 v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v11, vcc_lo, s6, v11 v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo global_load_b32 v10, v[9:10], off global_load_b32 v11, v[11:12], off v_mov_b32_e32 v9, v6 s_waitcnt vmcnt(1) ds_store_b32 v7, v10 s_waitcnt vmcnt(0) ds_store_b32 v8, v11 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv .LBB0_3: ; Parent Loop BB0_2 Depth=1 ; => This Inner Loop Header: Depth=2 v_add_nc_u32_e32 v10, s12, v5 s_add_i32 s12, s12, 4 ds_load_b32 v11, v9 ds_load_b32 v10, v10 v_add_nc_u32_e32 v9, 0x80, v9 s_cmpk_eq_i32 s12, 0x80 s_waitcnt lgkmcnt(0) v_fmac_f32_e32 v4, v10, v11 s_cbranch_scc0 .LBB0_3 ; %bb.4: ; in Loop: Header=BB0_2 Depth=1 s_add_i32 s10, s10, 32 s_add_i32 s11, s11, s8 s_cmp_ge_i32 s10, s2 s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB0_2 s_branch .LBB0_6 .LBB0_5: v_mov_b32_e32 v4, 0 .LBB0_6: ; %Flow68 s_set_inst_prefetch_distance 0x2 v_mul_lo_u32 v0, v0, s3 v_add_nc_u32_e32 v1, s9, v1 s_load_b64 s[0:1], s[0:1], 0x10 s_mul_i32 s8, s8, s15 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_add3_u32 v0, v1, v0, s8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v4, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z7multMatPfS_S_ii .amdhsa_group_segment_fixed_size 8192 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 13 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z7multMatPfS_S_ii, .Lfunc_end0-_Z7multMatPfS_S_ii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 440 ; NumSgprs: 18 ; NumVgprs: 13 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 8192 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 13 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value .group_segment_fixed_size: 8192 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z7multMatPfS_S_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z7multMatPfS_S_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 13 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "5a30094893d94381b0bd7341211ed99a757c04b1.hip" .globl _Z22__device_stub__multMatPfS_S_ii # -- Begin function _Z22__device_stub__multMatPfS_S_ii .p2align 4, 0x90 .type _Z22__device_stub__multMatPfS_S_ii,@function _Z22__device_stub__multMatPfS_S_ii: # @_Z22__device_stub__multMatPfS_S_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %rsp, %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7multMatPfS_S_ii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z22__device_stub__multMatPfS_S_ii, .Lfunc_end0-_Z22__device_stub__multMatPfS_S_ii .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI1_0: .long 0x47c35000 # float 1.0E+5 .LCPI1_1: .long 0xc2000000 # float -32 .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 .LCPI1_2: .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .LCPI1_3: .quad 0x7fffffffffffffff # double NaN .quad 0x7fffffffffffffff # double NaN .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI1_4: .quad 0x3fa0000000000000 # double 0.03125 .LCPI1_5: .quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7 .LCPI1_6: .quad 0x4040000000000000 # double 32 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $168, %rsp .cfi_def_cfa_offset 224 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $4096, %edi # imm = 0x1000 callq malloc movq %rax, %rbx movl $4096, %edi # imm = 0x1000 callq malloc movq %rax, %r14 movl $4096, %edi # imm = 0x1000 callq malloc movq %rax, %r15 xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000 movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000 incq %rax cmpq $1024, %rax # imm = 0x400 jne .LBB1_1 # %bb.2: leaq 32(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc leaq 24(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc leaq 16(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc movq 32(%rsp), %rdi movl $4096, %edx # imm = 0x1000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 24(%rsp), %rdi movl $4096, %edx # imm = 0x1000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy leaq 48(%rsp), %rdi callq hipEventCreate leaq 8(%rsp), %rdi callq hipEventCreate movq 48(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movl $100000, %ebp # imm = 0x186A0 movabsq $4294967297, %r12 # imm = 0x100000001 movabsq $137438953504, %r13 # imm = 0x2000000020 jmp .LBB1_3 .p2align 4, 0x90 .LBB1_5: # in Loop: Header=BB1_3 Depth=1 decl %ebp je .LBB1_6 .LBB1_3: # =>This Inner Loop Header: Depth=1 movq %r12, %rdi movl $1, %esi movq %r13, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_5 # %bb.4: # in Loop: Header=BB1_3 Depth=1 movq 32(%rsp), %rax movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq %rax, 120(%rsp) movq %rcx, 112(%rsp) movq %rdx, 104(%rsp) movl $32, 44(%rsp) movl $32, 40(%rsp) leaq 120(%rsp), %rax movq %rax, 128(%rsp) leaq 112(%rsp), %rax movq %rax, 136(%rsp) leaq 104(%rsp), %rax movq %rax, 144(%rsp) leaq 44(%rsp), %rax movq %rax, 152(%rsp) leaq 40(%rsp), %rax movq %rax, 160(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d movl $_Z7multMatPfS_S_ii, %edi leaq 128(%rsp), %r9 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 jmp .LBB1_5 .LBB1_6: movq 8(%rsp), %rdi xorl %r12d, %r12d xorl %esi, %esi callq hipEventRecord movq 8(%rsp), %rdi callq hipEventSynchronize movl $0, 128(%rsp) movq 48(%rsp), %rsi movq 8(%rsp), %rdx leaq 128(%rsp), %rdi callq hipEventElapsedTime movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero divss .LCPI1_0(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movl $.L.str, %edi movb $1, %al callq printf movq 16(%rsp), %rsi movl $4096, %edx # imm = 0x1000 movq %r15, %rdi movl $2, %ecx callq hipMemcpy movss .LCPI1_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero movaps .LCPI1_2(%rip), %xmm4 # xmm4 = [NaN,NaN,NaN,NaN] movaps .LCPI1_3(%rip), %xmm5 # xmm5 = [NaN,NaN] movsd .LCPI1_4(%rip), %xmm6 # xmm6 = mem[0],zero movsd .LCPI1_5(%rip), %xmm2 # xmm2 = mem[0],zero jmp .LBB1_7 .p2align 4, 0x90 .LBB1_9: # in Loop: Header=BB1_7 Depth=1 incq %r12 cmpq $1024, %r12 # imm = 0x400 je .LBB1_10 .LBB1_7: # =>This Inner Loop Header: Depth=1 movss (%r15,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero xorps %xmm0, %xmm0 cvtss2sd %xmm1, %xmm0 addss %xmm3, %xmm1 andps %xmm4, %xmm1 cvtss2sd %xmm1, %xmm1 movaps %xmm0, %xmm7 andps %xmm5, %xmm7 divsd %xmm7, %xmm1 mulsd %xmm6, %xmm1 ucomisd %xmm2, %xmm1 jbe .LBB1_9 # %bb.8: # in Loop: Header=BB1_7 Depth=1 movl $.L.str.1, %edi movl %r12d, %esi movsd .LCPI1_6(%rip), %xmm1 # xmm1 = mem[0],zero movb $3, %al callq printf movsd .LCPI1_5(%rip), %xmm2 # xmm2 = mem[0],zero movsd .LCPI1_4(%rip), %xmm6 # xmm6 = mem[0],zero movaps .LCPI1_3(%rip), %xmm5 # xmm5 = [NaN,NaN] movaps .LCPI1_2(%rip), %xmm4 # xmm4 = [NaN,NaN,NaN,NaN] movss .LCPI1_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero jmp .LBB1_9 .LBB1_10: movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free movq 32(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree xorl %eax, %eax addq $168, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7multMatPfS_S_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z7multMatPfS_S_ii,@object # @_Z7multMatPfS_S_ii .section .rodata,"a",@progbits .globl _Z7multMatPfS_S_ii .p2align 3, 0x0 _Z7multMatPfS_S_ii: .quad _Z22__device_stub__multMatPfS_S_ii .size _Z7multMatPfS_S_ii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Time= %2.5f\n" .size .L.str, 13 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n" .size .L.str.1, 55 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z7multMatPfS_S_ii" .size .L__unnamed_1, 19 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__multMatPfS_S_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7multMatPfS_S_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
2,706
4,121
3,290
5,126
103
code for sm_80 Function : _Z9vectorAddPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R6, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R6, R6, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; @P0 EXIT ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; LDG.E R4, [R4.64] ; LDG.E R3, [R2.64] ; IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; IADD3 R9, R4, R3, RZ ; STG.E [R6.64], R9 ; EXIT ; BRA 0x100; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0002e06e_00000000-6_6a1fb9f20234972a70b65fbb345afb96133d2925.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i .type _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, @function _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i: .LFB2082: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z9vectorAddPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i .globl _Z9vectorAddPiS_S_i .type _Z9vectorAddPiS_S_i, @function _Z9vectorAddPiS_S_i: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z9vectorAddPiS_S_i, .-_Z9vectorAddPiS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Matrix A: \n" .LC1: .string "%d " .LC2: .string "\nMatrix B: \n" .LC3: .string "Grid size is %d\n" .LC4: .string "Matrix C: \n" .LC5: .string "Completed Successfully!\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $72, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movl $64, %edi call malloc@PLT movq %rax, %r12 movl $64, %edi call malloc@PLT movq %rax, %rbp movl $64, %edi call malloc@PLT movq %rax, %r13 movl $0, %eax .L12: movl $1, (%r12,%rax) movl $2, 0(%rbp,%rax) addq $4, %rax cmpq $64, %rax jne .L12 leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %r12, %rbx leaq 64(%r12), %r15 leaq .LC1(%rip), %r14 .L13: movl (%rbx), %edx movq %r14, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %r15, %rbx jne .L13 leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %rbp, %rbx leaq 64(%rbp), %r15 leaq .LC1(%rip), %r14 .L14: movl (%rbx), %edx movq %r14, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %r15, %rbx jne .L14 leaq 8(%rsp), %rdi movl $64, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $64, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $64, %esi call cudaMalloc@PLT movl $4, %edx leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %ecx movl $64, %edx movq %r12, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $64, %edx movq %rbp, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $4, 44(%rsp) movl $1, 48(%rsp) movl $4, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L23 .L15: movl $2, %ecx movl $64, %edx movq 24(%rsp), %rsi movq %r13, %rdi call cudaMemcpy@PLT leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %r13, %rbx leaq 64(%r13), %r15 leaq .LC1(%rip), %r14 .L16: movl (%rbx), %edx movq %r14, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %r15, %rbx jne .L16 leaq .LC5(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %r12, %rdi call free@PLT movq %rbp, %rdi call free@PLT movq %r13, %rdi call free@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L24 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state movl $16, %ecx movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i jmp .L15 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC6: .string "_Z9vectorAddPiS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z9vectorAddPiS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9vectorAddPiS_S_i ; -- Begin function _Z9vectorAddPiS_S_i .globl _Z9vectorAddPiS_S_i .p2align 8 .type _Z9vectorAddPiS_S_i,@function _Z9vectorAddPiS_S_i: ; @_Z9vectorAddPiS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_add_nc_u32_e32 v2, v3, v2 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9vectorAddPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9vectorAddPiS_S_i, .Lfunc_end0-_Z9vectorAddPiS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 180 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9vectorAddPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z9vectorAddPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "6a1fb9f20234972a70b65fbb345afb96133d2925.hip" .globl _Z24__device_stub__vectorAddPiS_S_i # -- Begin function _Z24__device_stub__vectorAddPiS_S_i .p2align 4, 0x90 .type _Z24__device_stub__vectorAddPiS_S_i,@function _Z24__device_stub__vectorAddPiS_S_i: # @_Z24__device_stub__vectorAddPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9vectorAddPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z24__device_stub__vectorAddPiS_S_i, .Lfunc_end0-_Z24__device_stub__vectorAddPiS_S_i .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $152, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $64, %edi callq malloc movq %rax, %rbx movl $64, %edi callq malloc movq %rax, %r14 movl $64, %edi callq malloc movq %rax, %r15 xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1, (%rbx,%rax,4) movl $2, (%r14,%rax,4) incq %rax cmpq $16, %rax jne .LBB1_1 # %bb.2: movl $.Lstr, %edi callq puts@PLT xorl %r12d, %r12d .p2align 4, 0x90 .LBB1_3: # =>This Inner Loop Header: Depth=1 movl (%rbx,%r12,4), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r12 cmpq $16, %r12 jne .LBB1_3 # %bb.4: movl $.Lstr.1, %edi callq puts@PLT xorl %r12d, %r12d .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 movl (%r14,%r12,4), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r12 cmpq $16, %r12 jne .LBB1_5 # %bb.6: leaq 24(%rsp), %rdi movl $64, %esi callq hipMalloc leaq 16(%rsp), %rdi movl $64, %esi callq hipMalloc leaq 8(%rsp), %rdi movl $64, %esi callq hipMalloc movl $.L.str.3, %edi movl $4, %esi xorl %eax, %eax callq printf movq 24(%rsp), %rdi movl $64, %edx movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi movl $64, %edx movq %r14, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967300, %rdi # imm = 0x100000004 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_8 # %bb.7: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movl $16, 36(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 36(%rsp), %rax movq %rax, 136(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z9vectorAddPiS_S_i, %edi pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_8: movq 8(%rsp), %rsi movl $64, %edx movq %r15, %rdi movl $2, %ecx callq hipMemcpy movl $.Lstr.2, %edi callq puts@PLT xorl %r12d, %r12d .p2align 4, 0x90 .LBB1_9: # =>This Inner Loop Header: Depth=1 movl (%r15,%r12,4), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r12 cmpq $16, %r12 jne .LBB1_9 # %bb.10: movl $.Lstr.3, %edi callq puts@PLT movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax addq $152, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9vectorAddPiS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z9vectorAddPiS_S_i,@object # @_Z9vectorAddPiS_S_i .section .rodata,"a",@progbits .globl _Z9vectorAddPiS_S_i .p2align 3, 0x0 _Z9vectorAddPiS_S_i: .quad _Z24__device_stub__vectorAddPiS_S_i .size _Z9vectorAddPiS_S_i, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "%d " .size .L.str.1, 4 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Grid size is %d\n" .size .L.str.3, 17 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9vectorAddPiS_S_i" .size .L__unnamed_1, 20 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Matrix A: " .size .Lstr, 11 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "\nMatrix B: " .size .Lstr.1, 12 .type .Lstr.2,@object # @str.2 .Lstr.2: .asciz "Matrix C: " .size .Lstr.2, 11 .type .Lstr.3,@object # @str.3 .Lstr.3: .asciz "Completed Successfully!" .size .Lstr.3, 24 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__vectorAddPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9vectorAddPiS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
540
3,787
2,565
3,919
104
code for sm_80 Function : _Z3addPiS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R6, SR_TID.X ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R3, SR_CTAID.X ; IMAD R6, R3, c[0x0][0x0], R6 ; IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; LDG.E R2, [R2.64] ; LDG.E R5, [R4.64] ; IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; IADD3 R9, R2, R5, RZ ; STG.E [R6.64], R9 ; EXIT ; BRA 0xe0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000b96ad_00000000-6_cd5a992e4b0dd586eafdbb1763b050e97034e04a.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z11random_intsPii .type _Z11random_intsPii, @function _Z11random_intsPii: .LFB2057: .cfi_startproc endbr64 testl %esi, %esi jle .L8 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movslq %esi, %rsi leaq (%rdi,%rsi,4), %rbp .L5: call rand@PLT movslq %eax, %rdx imulq $1374389535, %rdx, %rdx sarq $36, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx imull $50, %edx, %edx subl %edx, %eax movl %eax, (%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L5 addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L8: .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE2057: .size _Z11random_intsPii, .-_Z11random_intsPii .globl _Z26__device_stub__Z3addPiS_S_PiS_S_ .type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function _Z26__device_stub__Z3addPiS_S_PiS_S_: .LFB2083: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 120(%rsp), %rax subq %fs:40, %rax jne .L16 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z3addPiS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_ .globl _Z3addPiS_S_ .type _Z3addPiS_S_, @function _Z3addPiS_S_: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z3addPiS_S_PiS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z3addPiS_S_, .-_Z3addPiS_S_ .globl _Z8testmaini .type _Z8testmaini, @function _Z8testmaini: .LFB2058: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $64, %rsp .cfi_def_cfa_offset 112 movl %edi, %ebp movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leal 0(,%rdi,4), %ebx movslq %ebx, %rbx leaq 8(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 16(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 24(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movq %rbx, %rdi call malloc@PLT movq %rax, %r13 movl %ebp, %esi movq %rax, %rdi call _Z11random_intsPii movq %rbx, %rdi call malloc@PLT movq %rax, %r12 movl %ebp, %esi movq %rax, %rdi call _Z11random_intsPii movq %rbx, %rdi call malloc@PLT movq %rax, %r14 movl $1, %ecx movq %rbx, %rdx movq %r13, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq %r12, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $512, 44(%rsp) movl $1, 48(%rsp) leal 511(%rbp), %eax testl %ebp, %ebp cmovns %ebp, %eax sarl $9, %eax movl %eax, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L23 .L20: call cudaDeviceSynchronize@PLT movl $2, %ecx movq %rbx, %rdx movq 24(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT movq %r13, %rdi call free@PLT movq %r12, %rdi call free@PLT movq %r14, %rdi call free@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L24 movq %r14, %rax addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z26__device_stub__Z3addPiS_S_PiS_S_ jmp .L20 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size _Z8testmaini, .-_Z8testmaini .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z3addPiS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z3addPiS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z3addPiS_S_ ; -- Begin function _Z3addPiS_S_ .globl _Z3addPiS_S_ .p2align 8 .type _Z3addPiS_S_,@function _Z3addPiS_S_: ; @_Z3addPiS_S_ ; %bb.0: s_clause 0x2 s_load_b32 s2, s[0:1], 0x24 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_add_nc_u32_e32 v2, v3, v2 global_store_b32 v[0:1], v2, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z3addPiS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 152 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z3addPiS_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z3addPiS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "cd5a992e4b0dd586eafdbb1763b050e97034e04a.hip" .globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_ .p2align 4, 0x90 .type _Z18__device_stub__addPiS_S_,@function _Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3addPiS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_ .cfi_endproc # -- End function .globl _Z11random_intsPii # -- Begin function _Z11random_intsPii .p2align 4, 0x90 .type _Z11random_intsPii,@function _Z11random_intsPii: # @_Z11random_intsPii .cfi_startproc # %bb.0: testl %esi, %esi jle .LBB1_4 # %bb.1: # %.lr.ph.preheader pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx movl %esi, %r14d xorl %r15d, %r15d .p2align 4, 0x90 .LBB1_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1374389535, %rax, %rcx # imm = 0x51EB851F movq %rcx, %rdx shrq $63, %rdx sarq $36, %rcx addl %edx, %ecx imull $50, %ecx, %ecx subl %ecx, %eax movl %eax, (%rbx,%r15,4) incq %r15 cmpq %r15, %r14 jne .LBB1_2 # %bb.3: popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 .cfi_restore %rbx .cfi_restore %r14 .cfi_restore %r15 .LBB1_4: # %._crit_edge retq .Lfunc_end1: .size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii .cfi_endproc # -- End function .globl _Z8testmaini # -- Begin function _Z8testmaini .p2align 4, 0x90 .type _Z8testmaini,@function _Z8testmaini: # @_Z8testmaini .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $120, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %edi, %r12d leal (,%r12,4), %eax movslq %eax, %rbx leaq 16(%rsp), %rdi movq %rbx, %rsi callq hipMalloc leaq 8(%rsp), %rdi movq %rbx, %rsi callq hipMalloc movq %rsp, %rdi movq %rbx, %rsi callq hipMalloc movq %rbx, %rdi callq malloc movq %rax, %r14 movl %r12d, %r13d testl %r12d, %r12d jle .LBB2_3 # %bb.1: # %.lr.ph.preheader.i xorl %r15d, %r15d .p2align 4, 0x90 .LBB2_2: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1374389535, %rax, %rcx # imm = 0x51EB851F movq %rcx, %rdx shrq $63, %rdx sarq $36, %rcx addl %edx, %ecx imull $50, %ecx, %ecx subl %ecx, %eax movl %eax, (%r14,%r15,4) incq %r15 cmpq %r15, %r13 jne .LBB2_2 .LBB2_3: # %_Z11random_intsPii.exit movq %rbx, %rdi callq malloc movq %rax, %r15 testl %r12d, %r12d jle .LBB2_6 # %bb.4: # %.lr.ph.preheader.i23 xorl %ebp, %ebp .p2align 4, 0x90 .LBB2_5: # %.lr.ph.i25 # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1374389535, %rax, %rcx # imm = 0x51EB851F movq %rcx, %rdx shrq $63, %rdx sarq $36, %rcx addl %edx, %ecx imull $50, %ecx, %ecx subl %ecx, %eax movl %eax, (%r15,%rbp,4) incq %rbp cmpq %rbp, %r13 jne .LBB2_5 .LBB2_6: # %_Z11random_intsPii.exit29 movq %rbx, %rdi callq malloc movq %rax, %r13 movq 16(%rsp), %rdi movq %r14, %rsi movq %rbx, %rdx movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi movq %r15, %rsi movq %rbx, %rdx movl $1, %ecx callq hipMemcpy leal 511(%r12), %edi testl %r12d, %r12d cmovnsl %r12d, %edi sarl $9, %edi movabsq $4294967296, %rdx # imm = 0x100000000 orq %rdx, %rdi orq $512, %rdx # imm = 0x200 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_8 # %bb.7: movq 16(%rsp), %rax movq 8(%rsp), %rcx movq (%rsp), %rdx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movq %rdx, 72(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z3addPiS_S_, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_8: callq hipDeviceSynchronize movq (%rsp), %rsi movq %r13, %rdi movq %rbx, %rdx movl $2, %ecx callq hipMemcpy movq %r14, %rdi callq free movq %r15, %rdi callq free movq %r13, %rdi callq free movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movq %r13, %rax addq $120, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z8testmaini, .Lfunc_end2-_Z8testmaini .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3addPiS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z3addPiS_S_,@object # @_Z3addPiS_S_ .section .rodata,"a",@progbits .globl _Z3addPiS_S_ .p2align 3, 0x0 _Z3addPiS_S_: .quad _Z18__device_stub__addPiS_S_ .size _Z3addPiS_S_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z3addPiS_S_" .size .L__unnamed_1, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__addPiS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3addPiS_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z9reduceSumPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; ULDC.64 UR4, c[0x0][0x118] ; S2R R3, SR_TID.X ; IMAD R4, R0, 0x800, R3 ; IADD3 R6, R4.reuse, 0x400, RZ ; ISETP.GE.U32.AND P0, PT, R4, 0x20000000, PT ; ISETP.GE.U32.AND P1, PT, R6, 0x20000000, PT ; @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; @!P1 IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; @!P0 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; @!P1 IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; @!P0 LDG.E R4, [R4.64] ; @!P1 LDG.E R6, [R6.64] ; LOP3.LUT R2, R3, 0x1, RZ, 0xc0, !PT ; @P0 STS [R3.X4], RZ ; @P1 STS [R3.X4+0x1000], RZ ; @!P0 STS [R3.X4], R4 ; LOP3.LUT P0, RZ, R3, 0x3, RZ, 0xc0, !PT ; @!P1 STS [R3.X4+0x1000], R6 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.U32.AND P1, PT, R2, 0x1, PT ; LDS.64 R8, [R3.X8] ; IMAD.IADD R2, R9, 0x1, R8 ; STS [R3.X8], R2 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P1 LDS R5, [R3.X8] ; @P1 LDS R8, [R3.X8+0x8] ; @P1 IADD3 R8, R5, R8, RZ ; @P1 STS [R3.X8], R8 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LOP3.LUT P1, RZ, R3, 0x7, RZ, 0xc0, !PT ; @!P0 LDS R4, [R3.X8] ; @!P0 LDS R5, [R3.X8+0x10] ; @!P0 IMAD.IADD R4, R4, 0x1, R5 ; @!P0 STS [R3.X8], R4 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LOP3.LUT P0, RZ, R3, 0xf, RZ, 0xc0, !PT ; @!P1 LDS R2, [R3.X8] ; @!P1 LDS R5, [R3.X8+0x20] ; @!P1 IMAD.IADD R2, R2, 0x1, R5 ; @!P1 STS [R3.X8], R2 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LOP3.LUT P1, RZ, R3, 0x1f, RZ, 0xc0, !PT ; @!P0 LDS R5, [R3.X8] ; @!P0 LDS R6, [R3.X8+0x40] ; @!P0 IMAD.IADD R6, R5, 0x1, R6 ; @!P0 STS [R3.X8], R6 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LOP3.LUT P0, RZ, R3, 0x3f, RZ, 0xc0, !PT ; @!P1 LDS R4, [R3.X8] ; @!P1 LDS R5, [R3.X8+0x80] ; @!P1 IADD3 R4, R4, R5, RZ ; @!P1 STS [R3.X8], R4 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LOP3.LUT P1, RZ, R3, 0x7f, RZ, 0xc0, !PT ; @!P0 LDS R2, [R3.X8] ; @!P0 LDS R5, [R3.X8+0x100] ; @!P0 IMAD.IADD R2, R2, 0x1, R5 ; @!P0 STS [R3.X8], R2 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LOP3.LUT P0, RZ, R3, 0xff, RZ, 0xc0, !PT ; @!P1 LDS R5, [R3.X8] ; @!P1 LDS R6, [R3.X8+0x200] ; @!P1 IMAD.IADD R6, R5, 0x1, R6 ; @!P1 STS [R3.X8], R6 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LOP3.LUT P1, RZ, R3, 0x1ff, RZ, 0xc0, !PT ; @!P0 LDS R4, [R3.X8] ; @!P0 LDS R5, [R3.X8+0x400] ; @!P0 IMAD.IADD R4, R4, 0x1, R5 ; @!P0 STS [R3.X8], R4 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LOP3.LUT P0, RZ, R3, 0x3ff, RZ, 0xc0, !PT ; @!P1 LDS R2, [R3.X8] ; @!P1 LDS R5, [R3.X8+0x800] ; @!P1 IADD3 R2, R2, R5, RZ ; @!P1 STS [R3.X8], R2 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.AND P1, PT, R3, RZ, PT ; @!P0 LDS R5, [R3.X8] ; @!P0 LDS R6, [R3.X8+0x1000] ; @!P0 IMAD.IADD R6, R5, 0x1, R6 ; @!P1 IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; @!P0 STS [R3.X8], R6 ; @!P1 IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; @!P1 LDS R7, [RZ] ; @!P1 STG.E [R4.64], R7 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; EXIT ; BRA 0x5a0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000b07c8_00000000-6_8c8018b64d4b1f2cdb5e9bb6d6a7aa84e7235063.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4036: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4036: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z30__device_stub__Z9reduceSumPiS_PiS_ .type _Z30__device_stub__Z9reduceSumPiS_PiS_, @function _Z30__device_stub__Z9reduceSumPiS_PiS_: .LFB4058: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z9reduceSumPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE4058: .size _Z30__device_stub__Z9reduceSumPiS_PiS_, .-_Z30__device_stub__Z9reduceSumPiS_PiS_ .globl _Z9reduceSumPiS_ .type _Z9reduceSumPiS_, @function _Z9reduceSumPiS_: .LFB4059: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z9reduceSumPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4059: .size _Z9reduceSumPiS_, .-_Z9reduceSumPiS_ .globl main .type main, @function main: .LFB4032: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 subq $64, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movq %rsp, %rdi movl $1, %edx movl $2147483648, %ebx movq %rbx, %rsi call cudaMallocManaged@PLT leaq 8(%rsp), %rdi movl $1, %edx movq %rbx, %rsi call cudaMallocManaged@PLT movl $0, %eax movq %rbx, %rcx .L12: movq (%rsp), %rdx movl $1, (%rdx,%rax) addq $4, %rax cmpq %rcx, %rax jne .L12 movl $1024, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $524288, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L20 .L13: call cudaDeviceSynchronize@PLT movl $20, %ebx jmp .L15 .L20: movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z30__device_stub__Z9reduceSumPiS_PiS_ jmp .L13 .L22: movq 8(%rsp), %rdi movq %rdi, %rsi call _Z30__device_stub__Z9reduceSumPiS_PiS_ .L14: call cudaDeviceSynchronize@PLT subl $1, %ebx je .L21 .L15: movl $1024, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl 40(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L14 jmp .L22 .L21: movq 8(%rsp), %rax movl (%rax), %esi leaq _ZSt4cout(%rip), %rdi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L23 movl $0, %eax addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE4032: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z9reduceSumPiS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z9reduceSumPiS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4061: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9reduceSumPiS_ ; -- Begin function _Z9reduceSumPiS_ .globl _Z9reduceSumPiS_ .p2align 8 .type _Z9reduceSumPiS_,@function _Z9reduceSumPiS_: ; @_Z9reduceSumPiS_ ; %bb.0: s_load_b64 s[4:5], s[0:1], 0x0 s_mov_b32 s2, s15 v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 0 v_lshl_or_b32 v1, s2, 11, v0 s_mov_b32 s3, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_u32_e32 0x20000000, v1 s_cbranch_execz .LBB0_2 ; %bb.1: v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v4, vcc_lo, s4, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo global_load_b32 v2, v[4:5], off .LBB0_2: s_or_b32 exec_lo, exec_lo, s3 v_or_b32_e32 v1, 0x400, v1 v_lshlrev_b32_e32 v4, 2, v0 s_mov_b32 s3, exec_lo s_waitcnt vmcnt(0) ds_store_b32 v4, v2 v_cmpx_gt_u32_e32 0x20000000, v1 s_cbranch_execz .LBB0_4 ; %bb.3: v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v1, vcc_lo, s4, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo global_load_b32 v3, v[1:2], off .LBB0_4: s_or_b32 exec_lo, exec_lo, s3 v_lshlrev_b32_e32 v1, 1, v0 v_lshlrev_b32_e32 v2, 3, v0 s_mov_b32 s3, 1 s_waitcnt vmcnt(0) ds_store_b32 v4, v3 offset:4096 s_branch .LBB0_6 .p2align 6 .LBB0_5: ; in Loop: Header=BB0_6 Depth=1 s_or_b32 exec_lo, exec_lo, s4 s_lshl_b32 s4, s3, 1 s_cmpk_gt_u32 s3, 0x200 s_mov_b32 s3, s4 s_cbranch_scc1 .LBB0_8 .LBB0_6: ; =>This Inner Loop Header: Depth=1 s_waitcnt lgkmcnt(0) s_add_i32 s4, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) v_and_b32_e32 v3, s4, v0 s_mov_b32 s4, exec_lo s_barrier buffer_gl0_inv v_cmpx_eq_u32_e32 0, v3 s_cbranch_execz .LBB0_5 ; %bb.7: ; in Loop: Header=BB0_6 Depth=1 v_add_lshl_u32 v3, s3, v1, 2 ds_load_b32 v3, v3 ds_load_b32 v4, v2 s_waitcnt lgkmcnt(0) v_add_nc_u32_e32 v3, v4, v3 ds_store_b32 v2, v3 s_branch .LBB0_5 .LBB0_8: s_mov_b32 s3, 0 s_mov_b32 s4, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_10 ; %bb.9: v_mov_b32_e32 v0, 0 s_load_b64 s[0:1], s[0:1], 0x8 s_lshl_b64 s[2:3], s[2:3], 2 ds_load_b32 v1, v0 s_waitcnt lgkmcnt(0) s_add_u32 s0, s0, s2 s_addc_u32 s1, s1, s3 global_store_b32 v0, v1, s[0:1] .LBB0_10: s_or_b32 exec_lo, exec_lo, s4 s_waitcnt lgkmcnt(0) s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9reduceSumPiS_ .amdhsa_group_segment_fixed_size 8192 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9reduceSumPiS_, .Lfunc_end0-_Z9reduceSumPiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 404 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 8192 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 8192 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9reduceSumPiS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z9reduceSumPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "8c8018b64d4b1f2cdb5e9bb6d6a7aa84e7235063.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z24__device_stub__reduceSumPiS_ # -- Begin function _Z24__device_stub__reduceSumPiS_ .p2align 4, 0x90 .type _Z24__device_stub__reduceSumPiS_,@function _Z24__device_stub__reduceSumPiS_: # @_Z24__device_stub__reduceSumPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z9reduceSumPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z24__device_stub__reduceSumPiS_, .Lfunc_end0-_Z24__device_stub__reduceSumPiS_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $104, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 leaq 96(%rsp), %rdi movl $2147483648, %esi # imm = 0x80000000 movl $1, %edx callq hipMallocManaged leaq 8(%rsp), %rdi movl $2147483648, %esi # imm = 0x80000000 movl $1, %edx callq hipMallocManaged xorl %eax, %eax movq 96(%rsp), %rcx .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1, (%rcx,%rax,4) incq %rax cmpq $536870912, %rax # imm = 0x20000000 jne .LBB1_1 # %bb.2: movabsq $4294968320, %rbx # imm = 0x100000400 leaq 523264(%rbx), %r14 movq %r14, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 96(%rsp), %rax movq 8(%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9reduceSumPiS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: callq hipDeviceSynchronize movl $20, %r12d leaq 24(%rsp), %r13 leaq 16(%rsp), %rbp leaq 80(%rsp), %r15 jmp .LBB1_5 .p2align 4, 0x90 .LBB1_7: # in Loop: Header=BB1_5 Depth=1 callq hipDeviceSynchronize decl %r12d je .LBB1_8 .LBB1_5: # =>This Inner Loop Header: Depth=1 movq %r14, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_7 # %bb.6: # in Loop: Header=BB1_5 Depth=1 movq 8(%rsp), %rax movq %rax, 72(%rsp) movq %rax, 64(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi movq %r13, %rdx movq %rbp, %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d movl $_Z9reduceSumPiS_, %edi movq %r15, %r9 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 jmp .LBB1_7 .LBB1_8: movq 8(%rsp), %rax movl (%rax), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB1_13 # %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB1_11 # %bb.10: movzbl 67(%rbx), %ecx jmp .LBB1_12 .LBB1_11: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %eax, %eax addq $104, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_13: .cfi_def_cfa_offset 160 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9reduceSumPiS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z9reduceSumPiS_,@object # @_Z9reduceSumPiS_ .section .rodata,"a",@progbits .globl _Z9reduceSumPiS_ .p2align 3, 0x0 _Z9reduceSumPiS_: .quad _Z24__device_stub__reduceSumPiS_ .size _Z9reduceSumPiS_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z9reduceSumPiS_" .size .L__unnamed_1, 17 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__reduceSumPiS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9reduceSumPiS_ .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z15MatrixMulKernelPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R4, SR_CTAID.Y ; MOV R0, c[0x0][0x178] ; ULDC.64 UR4, c[0x0][0x118] ; HFMA2.MMA R28, -RZ, RZ, 0, 0 ; S2R R3, SR_TID.Y ; ISETP.GE.AND P0, PT, R0, 0x1, PT ; S2R R2, SR_CTAID.X ; S2R R5, SR_TID.X ; IMAD R4, R4, c[0x0][0x4], R3 ; IMAD R4, R4, c[0x0][0x178], RZ ; IMAD R2, R2, c[0x0][0x0], R5 ; @!P0 BRA 0xbf0 ; IADD3 R3, R0.reuse, -0x1, RZ ; LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; MOV R28, RZ ; MOV R3, RZ ; @!P0 BRA 0xad0 ; IADD3 R6, -R5, c[0x0][0x178], RZ ; HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR6, c[0x0][0x160] ; HFMA2.MMA R3, -RZ, RZ, 0, 0 ; ISETP.GT.AND P0, PT, R6, RZ, PT ; MOV R28, RZ ; IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; @!P0 BRA 0x940 ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x680 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; MOV R12, UR6 ; LDG.E R29, [R24.64] ; MOV R13, UR7 ; IMAD.WIDE R12, R4, 0x4, R12 ; LDG.E R27, [R12.64] ; IMAD.WIDE R10, R0, 0x4, R24 ; LDG.E R17, [R12.64+0x4] ; IMAD.WIDE R18, R0.reuse, 0x4, R10 ; LDG.E R16, [R10.64] ; LDG.E R7, [R12.64+0xc] ; IMAD.WIDE R14, R0, 0x4, R18 ; LDG.E R18, [R18.64] ; IMAD.WIDE R20, R0.reuse, 0x4, R14 ; LDG.E R26, [R14.64] ; LDG.E R9, [R12.64+0x10] ; LDG.E R19, [R12.64+0x8] ; IMAD.WIDE R14, R0, 0x4, R20 ; LDG.E R20, [R20.64] ; IMAD.WIDE R22, R0.reuse, 0x4, R14 ; LDG.E R8, [R14.64] ; LDG.E R11, [R12.64+0x14] ; IMAD.WIDE R24, R0, 0x4, R22 ; LDG.E R10, [R22.64] ; LDG.E R21, [R12.64+0x18] ; FFMA R29, R29, R27, R28 ; LDG.E R27, [R12.64+0x1c] ; LDG.E R28, [R24.64] ; IMAD.WIDE R14, R0, 0x4, R24 ; FFMA R29, R16, R17, R29 ; IMAD.WIDE R16, R0, 0x4, R14 ; LDG.E R14, [R14.64] ; FFMA R29, R18, R19, R29 ; IMAD.WIDE R18, R0, 0x4, R16 ; LDG.E R16, [R16.64] ; FFMA R26, R26, R7, R29 ; IMAD.WIDE R22, R0.reuse, 0x4, R18 ; LDG.E R7, [R12.64+0x20] ; LDG.E R29, [R12.64+0x24] ; IMAD.WIDE R24, R0, 0x4, R22 ; LDG.E R18, [R18.64] ; FFMA R9, R20, R9, R26 ; LDG.E R26, [R12.64+0x28] ; FFMA R11, R8, R11, R9 ; IMAD.WIDE R8, R0, 0x4, R24 ; LDG.E R22, [R22.64] ; LDG.E R17, [R12.64+0x2c] ; FFMA R21, R10, R21, R11 ; LDG.E R15, [R24.64] ; IMAD.WIDE R10, R0, 0x4, R8 ; LDG.E R19, [R8.64] ; LDG.E R23, [R10.64] ; LDG.E R24, [R12.64+0x30] ; LDG.E R25, [R12.64+0x38] ; LDG.E R8, [R12.64+0x3c] ; FFMA R9, R28, R27, R21 ; LDG.E R28, [R12.64+0x34] ; IMAD.WIDE R20, R0, 0x4, R10 ; LDG.E R27, [R20.64] ; IADD3 R6, R6, -0x10, RZ ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; FFMA R7, R14, R7, R9 ; FFMA R7, R16, R29, R7 ; FFMA R7, R18, R26, R7 ; FFMA R7, R22, R17, R7 ; UIADD3 UR6, UP0, UR6, 0x40, URZ ; IADD3 R3, R3, 0x10, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; FFMA R7, R15, R24, R7 ; FFMA R28, R19, R28, R7 ; FFMA R28, R23, R25, R28 ; IMAD.WIDE R24, R0, 0x4, R20 ; FFMA R28, R27, R8, R28 ; @P1 BRA 0x1f0 ; ISETP.GT.AND P1, PT, R6, 0x4, PT ; @!P1 BRA 0x920 ; IMAD.WIDE R16, R0, 0x4, R24 ; MOV R8, UR6 ; LDG.E R7, [R24.64] ; MOV R9, UR7 ; IMAD.WIDE R12, R0, 0x4, R16 ; LDG.E R21, [R16.64] ; IMAD.WIDE R8, R4, 0x4, R8 ; LDG.E R23, [R12.64] ; IMAD.WIDE R14, R0.reuse, 0x4, R12 ; LDG.E R20, [R8.64] ; LDG.E R22, [R8.64+0x4] ; IMAD.WIDE R10, R0, 0x4, R14 ; LDG.E R26, [R8.64+0x8] ; IMAD.WIDE R16, R0.reuse, 0x4, R10 ; LDG.E R14, [R14.64] ; LDG.E R27, [R8.64+0xc] ; IMAD.WIDE R18, R0, 0x4, R16 ; LDG.E R10, [R10.64] ; LDG.E R25, [R8.64+0x10] ; IMAD.WIDE R12, R0, 0x4, R18 ; LDG.E R16, [R16.64] ; LDG.E R29, [R8.64+0x14] ; LDG.E R24, [R18.64] ; LDG.E R11, [R8.64+0x18] ; LDG.E R15, [R12.64] ; LDG.E R18, [R8.64+0x1c] ; UIADD3 UR6, UP0, UR6, 0x20, URZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R3, R3, 0x8, RZ ; IADD3 R6, R6, -0x8, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; FFMA R7, R7, R20, R28 ; FFMA R7, R21, R22, R7 ; FFMA R7, R23, R26, R7 ; FFMA R7, R14, R27, R7 ; FFMA R7, R10, R25, R7 ; FFMA R7, R16, R29, R7 ; FFMA R7, R24, R11, R7 ; IMAD.WIDE R24, R0, 0x4, R12 ; FFMA R28, R15, R18, R7 ; ISETP.NE.OR P0, PT, R6, RZ, P0 ; @!P0 BRA 0xad0 ; MOV R8, UR6 ; IMAD.WIDE R14, R0, 0x4, R24 ; MOV R9, UR7 ; LDG.E R25, [R24.64] ; IMAD.WIDE R8, R4, 0x4, R8 ; IMAD.WIDE R12, R0.reuse, 0x4, R14 ; LDG.E R7, [R8.64] ; LDG.E R14, [R14.64] ; IMAD.WIDE R10, R0, 0x4, R12 ; LDG.E R16, [R8.64+0x4] ; LDG.E R18, [R12.64] ; LDG.E R17, [R8.64+0x8] ; LDG.E R19, [R8.64+0xc] ; LDG.E R20, [R10.64] ; IADD3 R6, R6, -0x4, RZ ; ISETP.NE.AND P0, PT, R6, RZ, PT ; UIADD3 UR6, UP0, UR6, 0x10, URZ ; IADD3 R3, R3, 0x4, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; FFMA R7, R25, R7, R28 ; FFMA R7, R14, R16, R7 ; IMAD.WIDE R24, R0, 0x4, R10 ; FFMA R7, R18, R17, R7 ; FFMA R28, R20, R19, R7 ; @P0 BRA 0x940 ; ISETP.NE.AND P0, PT, R5, RZ, PT ; @!P0 BRA 0xbf0 ; HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; IADD3 R6, R4, R3, RZ ; IMAD R3, R3, c[0x0][0x178], R2 ; IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; MOV R10, R6 ; MOV R6, R10 ; LDG.E R3, [R8.64] ; LDG.E R6, [R6.64] ; IADD3 R5, R5, -0x1, RZ ; IADD3 R10, P1, R10, 0x4, RZ ; ISETP.NE.AND P0, PT, R5, RZ, PT ; IMAD.WIDE R8, R0, 0x4, R8 ; IADD3.X R7, RZ, R7, RZ, P1, !PT ; FFMA R28, R3, R6, R28 ; @P0 BRA 0xb50 ; IADD3 R2, R2, R4, RZ ; MOV R3, 0x4 ; IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; STG.E [R2.64], R28 ; EXIT ; BRA 0xc40; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000b4127_00000000-6_f31b045a0fff6ff508a0a0c5f25792d63c1df962.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i .type _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, @function _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i: .LFB2082: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i .globl _Z15MatrixMulKernelPfS_S_i .type _Z15MatrixMulKernelPfS_S_i, @function _Z15MatrixMulKernelPfS_S_i: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z15MatrixMulKernelPfS_S_i, .-_Z15MatrixMulKernelPfS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC2: .string "%.2f " .LC3: .string "\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $4096, %rsp .cfi_def_cfa_offset 4144 orq $0, (%rsp) subq $4096, %rsp .cfi_def_cfa_offset 8240 orq $0, (%rsp) subq $4096, %rsp .cfi_def_cfa_offset 12336 orq $0, (%rsp) subq $64, %rsp .cfi_def_cfa_offset 12400 movq %fs:40, %rax movq %rax, 12344(%rsp) xorl %eax, %eax leaq 48(%rsp), %rdx leaq 4144(%rsp), %rcx movq %rcx, %rsi movss .LC0(%rip), %xmm1 movss .LC1(%rip), %xmm0 .L12: movl $0, %eax .L13: movss %xmm1, (%rdx,%rax) movss %xmm0, (%rcx,%rax) addq $4, %rax cmpq $128, %rax jne .L13 subq $-128, %rdx subq $-128, %rcx cmpq %rsi, %rdx jne .L12 movq %rsp, %rdi movl $4096, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT leaq 48(%rsp), %rsi movl $1, %ecx movl $4096, %edx movq (%rsp), %rdi call cudaMemcpy@PLT leaq 4144(%rsp), %rsi movl $1, %ecx movl $4096, %edx movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $16, 24(%rsp) movl $16, 28(%rsp) movl $1, 32(%rsp) movl $2, 36(%rsp) movl $2, 40(%rsp) movl $1, 44(%rsp) movl $0, %r9d movl $0, %r8d movq 24(%rsp), %rdx movl $1, %ecx movq 36(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L23 .L15: leaq 8240(%rsp), %rdi movl $2, %ecx movl $4096, %edx movq 16(%rsp), %rsi call cudaMemcpy@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT leaq 8368(%rsp), %rbp leaq 12464(%rsp), %r14 leaq .LC2(%rip), %r12 leaq .LC3(%rip), %r13 .L16: leaq -128(%rbp), %rbx .L17: pxor %xmm0, %xmm0 cvtss2sd (%rbx), %xmm0 movq %r12, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L17 movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT subq $-128, %rbp cmpq %r14, %rbp jne .L16 movq 12344(%rsp), %rax subq %fs:40, %rax jne .L24 movl $0, %eax addq $12352, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state movl $32, %ecx movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i jmp .L15 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC4: .string "_Z15MatrixMulKernelPfS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC4(%rip), %rdx movq %rdx, %rcx leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1065353216 .align 4 .LC1: .long 1073741824 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15MatrixMulKernelPfS_S_i ; -- Begin function _Z15MatrixMulKernelPfS_S_i .globl _Z15MatrixMulKernelPfS_S_i .p2align 8 .type _Z15MatrixMulKernelPfS_S_i,@function _Z15MatrixMulKernelPfS_S_i: ; @_Z15MatrixMulKernelPfS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s3, s[0:1], 0x2c s_load_b32 s2, s[0:1], 0x18 v_bfe_u32 v2, v0, 10, 10 v_and_b32_e32 v3, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_lshr_b32 s4, s3, 16 s_and_b32 s3, s3, 0xffff s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3] v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4] s_cmp_lt_i32 s2, 1 s_cbranch_scc1 .LBB0_3 ; %bb.1: ; %.lr.ph s_load_b128 s[4:7], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mul_lo_u32 v2, v0, s2 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v4, v1 s_mov_b32 s3, s2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo .p2align 6 .LBB0_2: ; =>This Inner Loop Header: Depth=1 v_ashrrev_i32_e32 v5, 31, v4 s_add_i32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_cmp_eq_u32 s3, 0 v_lshlrev_b64 v[7:8], 2, v[4:5] v_add_nc_u32_e32 v4, s2, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v7, vcc_lo, s6, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo global_load_b32 v5, v[2:3], off global_load_b32 v7, v[7:8], off v_add_co_u32 v2, vcc_lo, v2, 4 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo s_waitcnt vmcnt(0) v_fmac_f32_e32 v6, v5, v7 s_cbranch_scc0 .LBB0_2 s_branch .LBB0_4 .LBB0_3: v_mov_b32_e32 v6, 0 .LBB0_4: ; %Flow37 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2] v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[2:3] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v6, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15MatrixMulKernelPfS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z15MatrixMulKernelPfS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 316 ; NumSgprs: 18 ; NumVgprs: 9 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 9 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15MatrixMulKernelPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15MatrixMulKernelPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "f31b045a0fff6ff508a0a0c5f25792d63c1df962.hip" .globl _Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i .p2align 4, 0x90 .type _Z30__device_stub__MatrixMulKernelPfS_S_i,@function _Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z15MatrixMulKernelPfS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z30__device_stub__MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_S_i .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $12400, %rsp # imm = 0x3070 .cfi_def_cfa_offset 12432 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 8304(%rsp), %rax leaq 4208(%rsp), %rcx xorl %edx, %edx .p2align 4, 0x90 .LBB1_1: # %.preheader31 # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 xorl %esi, %esi .p2align 4, 0x90 .LBB1_2: # Parent Loop BB1_1 Depth=1 # => This Inner Loop Header: Depth=2 movl $1065353216, (%rax,%rsi,4) # imm = 0x3F800000 movl $1073741824, (%rcx,%rsi,4) # imm = 0x40000000 incq %rsi cmpq $32, %rsi jne .LBB1_2 # %bb.3: # in Loop: Header=BB1_1 Depth=1 incq %rdx subq $-128, %rax subq $-128, %rcx cmpq $32, %rdx jne .LBB1_1 # %bb.4: leaq 24(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc leaq 16(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc leaq 8(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc movq 24(%rsp), %rdi leaq 8304(%rsp), %rsi movl $4096, %edx # imm = 0x1000 movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi leaq 4208(%rsp), %rsi movl $4096, %edx # imm = 0x1000 movl $1, %ecx callq hipMemcpy movabsq $8589934594, %rdi # imm = 0x200000002 movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_6 # %bb.5: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movl $32, 36(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 36(%rsp), %rax movq %rax, 136(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z15MatrixMulKernelPfS_S_i, %edi pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_6: movq 8(%rsp), %rsi leaq 112(%rsp), %rbx movl $4096, %edx # imm = 0x1000 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_7: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_8 Depth 2 xorl %r15d, %r15d .p2align 4, 0x90 .LBB1_8: # Parent Loop BB1_7 Depth=1 # => This Inner Loop Header: Depth=2 movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str, %edi movb $1, %al callq printf incq %r15 cmpq $32, %r15 jne .LBB1_8 # %bb.9: # in Loop: Header=BB1_7 Depth=1 movl $10, %edi callq putchar@PLT incq %r14 subq $-128, %rbx cmpq $32, %r14 jne .LBB1_7 # %bb.10: xorl %eax, %eax addq $12400, %rsp # imm = 0x3070 .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15MatrixMulKernelPfS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z15MatrixMulKernelPfS_S_i,@object # @_Z15MatrixMulKernelPfS_S_i .section .rodata,"a",@progbits .globl _Z15MatrixMulKernelPfS_S_i .p2align 3, 0x0 _Z15MatrixMulKernelPfS_S_i: .quad _Z30__device_stub__MatrixMulKernelPfS_S_i .size _Z15MatrixMulKernelPfS_S_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%.2f " .size .L.str, 6 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15MatrixMulKernelPfS_S_i" .size .L__unnamed_1, 27 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15MatrixMulKernelPfS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
4,441
3,585
3,200
3,768
107
code for sm_80 Function : _Z11blur_kernelP8PPMImageP8PPMPixel .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; MOV R4, c[0x0][0x160] ; ULDC.64 UR6, c[0x0][0x118] ; MOV R5, c[0x0][0x164] ; LDG.E.64 R6, [R4.64] ; ULDC UR4, c[0x0][0xc] ; ULDC UR5, c[0x0][0x0] ; S2R R9, SR_CTAID.X ; UIMAD UR4, UR4, UR5, URZ ; S2R R0, SR_TID.X ; S2R R10, SR_CTAID.Y ; S2R R3, SR_TID.Y ; IMAD R9, R9, c[0x0][0x0], R0 ; IMAD R10, R10, c[0x0][0x4], R3 ; IMAD R0, R10, UR4, R9 ; IMAD R3, R6, R7, RZ ; ISETP.GE.AND P0, PT, R0, R3, PT ; @P0 EXIT ; LOP3.LUT P0, RZ, R9, R10, RZ, 0xfc, !PT ; HFMA2.MMA R3, -RZ, RZ, 0, 1.78813934326171875e-07 ; SHF.R.S32.HI R8, RZ, 0x1f, R0 ; IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; @!P0 BRA 0x28e0 ; IADD3 R7, R7, -0x1, RZ ; ISETP.EQ.AND P2, PT, R9.reuse, RZ, PT ; ISETP.NE.AND P1, PT, R10, R7, PT ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P1 BRA P2, 0x24e0 ; IADD3 R12, R6, -0x1, RZ ; ISETP.EQ.AND P4, PT, R10.reuse, RZ, PT ; ISETP.NE.AND P3, PT, R9, R12, PT ; ISETP.NE.AND P2, PT, R10, RZ, PT ; @!P3 BRA P4, 0x20f0 ; LDG.E.64 R10, [R4.64+0x8] ; ISETP.EQ.AND P4, PT, R9, R12, PT ; LOP3.LUT R7, RZ, R6.reuse, RZ, 0x33, !PT ; IADD3 R15, R0.reuse, -R6, RZ ; IADD3 R7, R0, R7, RZ ; IMAD.WIDE R14, R15, 0x3, R10 ; IMAD.WIDE R12, R0, 0x3, R10 ; IMAD.WIDE R16, R7, 0x3, R10 ; @!P1 BRA P4, 0x1d30 ; IADD3 R9, R0, -0x1, R6 ; IMAD.WIDE R6, R6, 0x3, R12 ; IMAD.WIDE R10, R9, 0x3, R10 ; @!P0 BRA 0x17a0 ; @!P3 BRA 0x1270 ; @!P2 BRA 0xdb0 ; LDG.E.U8 R14, [R14.64] ; LDG.E.U8 R8, [R16.64] ; LDG.E.U8 R18, [R16.64+0x6] ; LDG.E.U8 R19, [R12.64+-0x3] ; LDG.E.U8 R21, [R12.64] ; LDG.E.U8 R23, [R12.64+0x3] ; I2F.U16 R9, R14 ; I2F.U16 R8, R8 ; I2F.U16 R18, R18 ; FMUL R9, R9, 0.10000000149011611938 ; I2F.U16 R20, R19 ; FFMA R9, R8, 0.050000000745058059692, R9 ; I2F.U16 R22, R21 ; FFMA R9, R18, 0.050000000745058059692, R9 ; I2F.U16 R16, R23 ; FFMA R9, R20, 0.10000000149011611938, R9 ; FFMA R9, R22, 0.40000000596046447754, R9 ; FFMA R16, R16, 0.10000000149011611938, R9 ; @!P1 BRA 0x9f0 ; LDG.E.U8 R8, [R10.64] ; LDG.E.U8 R12, [R6.64] ; LDG.E.U8 R13, [R10.64+0x6] ; I2F.U16 R9, R8 ; I2F.U16 R12, R12 ; I2F.U16 R14, R13 ; FFMA R9, R9, 0.050000000745058059692, R16 ; FFMA R9, R12, 0.10000000149011611938, R9 ; FFMA R14, R14, 0.050000000745058059692, R9 ; F2I.U32.TRUNC.NTZ R15, R14 ; STG.E.U8 [R2.64], R15 ; LDG.E R17, [R4.64] ; LDG.E.64 R6, [R4.64+0x8] ; IADD3 R19, R0, -R17, RZ ; LOP3.LUT R9, RZ, R17, RZ, 0x33, !PT ; IADD3 R13, R0, R9, RZ ; IMAD.WIDE R8, R19, 0x3, R6 ; IMAD.WIDE R10, R0, 0x3, R6.reuse ; LDG.E.U8 R8, [R8.64+0x1] ; IMAD.WIDE R6, R13, 0x3, R6 ; LDG.E.U8 R16, [R6.64+0x1] ; IMAD.WIDE R12, R17, 0x3, R6 ; LDG.E.U8 R18, [R6.64+0x7] ; LDG.E.U8 R19, [R12.64+0x1] ; IMAD.WIDE R14, R17, 0x3, R12 ; LDG.E.U8 R20, [R12.64+0x4] ; IMAD.WIDE R10, R17, 0x3, R10 ; LDG.E.U8 R21, [R12.64+0x7] ; LDG.E.U8 R17, [R14.64+0x1] ; LDG.E.U8 R10, [R10.64+0x1] ; LDG.E.U8 R22, [R14.64+0x7] ; I2F.U16 R8, R8 ; I2F.U16 R16, R16 ; I2F.U16 R18, R18 ; FMUL R7, R8, 0.10000000149011611938 ; I2F.U16 R6, R19 ; FFMA R7, R16, 0.050000000745058059692, R7 ; I2F.U16 R9, R20 ; FFMA R7, R18, 0.050000000745058059692, R7 ; I2F.U16 R21, R21 ; FFMA R6, R6, 0.10000000149011611938, R7 ; I2F.U16 R17, R17 ; FFMA R6, R9, 0.40000000596046447754, R6 ; I2F.U16 R11, R10 ; FFMA R6, R21, 0.10000000149011611938, R6 ; I2F.U16 R7, R22 ; FFMA R6, R17, 0.050000000745058059692, R6 ; FFMA R6, R11, 0.10000000149011611938, R6 ; FFMA R12, R7, 0.050000000745058059692, R6 ; F2I.U32.TRUNC.NTZ R13, R12 ; STG.E.U8 [R2.64+0x1], R13 ; LDG.E R15, [R4.64] ; LDG.E.64 R6, [R4.64+0x8] ; IADD3 R19, R0, -R15, RZ ; LOP3.LUT R9, RZ, R15, RZ, 0x33, !PT ; IADD3 R17, R0, R9, RZ ; IMAD.WIDE R8, R19, 0x3, R6 ; IMAD.WIDE R10, R0, 0x3, R6.reuse ; LDG.E.U8 R8, [R8.64+0x2] ; IMAD.WIDE R6, R17, 0x3, R6 ; LDG.E.U8 R0, [R6.64+0x2] ; IMAD.WIDE R4, R15, 0x3, R6 ; LDG.E.U8 R14, [R6.64+0x8] ; LDG.E.U8 R16, [R4.64+0x2] ; IMAD.WIDE R12, R15, 0x3, R4 ; LDG.E.U8 R17, [R4.64+0x5] ; IMAD.WIDE R10, R15, 0x3, R10 ; LDG.E.U8 R18, [R4.64+0x8] ; LDG.E.U8 R15, [R12.64+0x2] ; LDG.E.U8 R10, [R10.64+0x2] ; LDG.E.U8 R19, [R12.64+0x8] ; I2F.U16 R8, R8 ; I2F.U16 R0, R0 ; I2F.U16 R14, R14 ; FMUL R7, R8, 0.10000000149011611938 ; I2F.U16 R16, R16 ; FFMA R7, R0, 0.050000000745058059692, R7 ; I2F.U16 R6, R17 ; FFMA R7, R14, 0.050000000745058059692, R7 ; I2F.U16 R5, R18 ; FFMA R7, R16, 0.10000000149011611938, R7 ; I2F.U16 R4, R15 ; FFMA R6, R6, 0.40000000596046447754, R7 ; I2F.U16 R9, R10 ; FFMA R5, R5, 0.10000000149011611938, R6 ; I2F.U16 R19, R19 ; FFMA R4, R4, 0.050000000745058059692, R5 ; FFMA R4, R9, 0.10000000149011611938, R4 ; FFMA R4, R19, 0.050000000745058059692, R4 ; F2I.U32.TRUNC.NTZ R5, R4 ; STG.E.U8 [R2.64+0x2], R5 ; EXIT ; F2I.U32.TRUNC.NTZ R7, R16 ; STG.E.U8 [R2.64], R7 ; LDG.E R9, [R4.64] ; LDG.E.64 R10, [R4.64+0x8] ; IADD3 R6, R0, -0x1, RZ ; LOP3.LUT R13, RZ, R9.reuse, RZ, 0x33, !PT ; IADD3 R17, R0.reuse, -R9, RZ ; IADD3 R15, R0, R13, RZ ; IMAD.WIDE R8, R6, 0x3, R10 ; IMAD.WIDE R12, R17, 0x3, R10.reuse ; LDG.E.U8 R16, [R8.64+0x4] ; IMAD.WIDE R10, R15, 0x3, R10 ; LDG.E.U8 R17, [R8.64+0x1] ; LDG.E.U8 R12, [R12.64+0x1] ; LDG.E.U8 R7, [R10.64+0x1] ; LDG.E.U8 R15, [R10.64+0x7] ; LDG.E.U8 R18, [R8.64+0x7] ; I2F.U16 R14, R12 ; I2F.U16 R7, R7 ; I2F.U16 R15, R15 ; FMUL R14, R14, 0.10000000149011611938 ; I2F.U16 R17, R17 ; FFMA R14, R7, 0.050000000745058059692, R14 ; I2F.U16 R19, R16 ; FFMA R14, R15, 0.050000000745058059692, R14 ; I2F.U16 R13, R18 ; FFMA R14, R17, 0.10000000149011611938, R14 ; FFMA R14, R19, 0.40000000596046447754, R14 ; FFMA R13, R13, 0.10000000149011611938, R14 ; F2I.U32.TRUNC.NTZ R13, R13 ; STG.E.U8 [R2.64+0x1], R13 ; LDG.E R7, [R4.64] ; LDG.E.64 R8, [R4.64+0x8] ; LOP3.LUT R15, RZ, R7, RZ, 0x33, !PT ; IADD3 R7, R0, -R7, RZ ; IMAD.WIDE R10, R6, 0x3, R8 ; IADD3 R15, R0, R15, RZ ; IMAD.WIDE R6, R7, 0x3, R8.reuse ; LDG.E.U8 R14, [R10.64+0x2] ; IMAD.WIDE R8, R15, 0x3, R8 ; LDG.E.U8 R13, [R10.64+0x5] ; LDG.E.U8 R6, [R6.64+0x2] ; LDG.E.U8 R0, [R8.64+0x2] ; LDG.E.U8 R12, [R8.64+0x8] ; LDG.E.U8 R15, [R10.64+0x8] ; I2F.U16 R4, R6 ; I2F.U16 R0, R0 ; I2F.U16 R12, R12 ; FMUL R5, R4, 0.10000000149011611938 ; I2F.U16 R14, R14 ; FFMA R5, R0, 0.050000000745058059692, R5 ; I2F.U16 R16, R13 ; FFMA R5, R12, 0.050000000745058059692, R5 ; I2F.U16 R4, R15 ; FFMA R5, R14, 0.10000000149011611938, R5 ; FFMA R5, R16, 0.40000000596046447754, R5 ; FFMA R4, R4, 0.10000000149011611938, R5 ; F2I.U32.TRUNC.NTZ R5, R4 ; STG.E.U8 [R2.64+0x2], R5 ; EXIT ; LDG.E.U8 R9, [R12.64] ; LDG.E.U8 R8, [R12.64+-0x3] ; LDG.E.U8 R14, [R12.64+0x3] ; LDG.E.U8 R16, [R10.64] ; LDG.E.U8 R6, [R6.64] ; LDG.E.U8 R17, [R10.64+0x6] ; I2F.U16 R9, R9 ; I2F.U16 R8, R8 ; I2F.U16 R14, R14 ; FMUL R15, R9, 0.40000000596046447754 ; I2F.U16 R16, R16 ; FFMA R15, R8, 0.10000000149011611938, R15 ; I2F.U16 R18, R6 ; FFMA R15, R14, 0.10000000149011611938, R15 ; I2F.U16 R12, R17 ; FFMA R15, R16, 0.050000000745058059692, R15 ; FFMA R15, R18, 0.10000000149011611938, R15 ; FFMA R15, R12, 0.050000000745058059692, R15 ; F2I.U32.TRUNC.NTZ R15, R15 ; STG.E.U8 [R2.64], R15 ; LDG.E.64 R8, [R4.64+0x8] ; LDG.E R19, [R4.64] ; IADD3 R6, R0, -0x1, RZ ; IMAD.WIDE R10, R6, 0x3, R8 ; LDG.E.U8 R14, [R10.64+0x4] ; IADD3 R17, R6, R19, RZ ; IMAD.WIDE R12, R0, 0x3, R8.reuse ; LDG.E.U8 R7, [R10.64+0x1] ; IMAD.WIDE R8, R17, 0x3, R8 ; LDG.E.U8 R15, [R10.64+0x7] ; IMAD.WIDE R12, R19, 0x3, R12 ; LDG.E.U8 R17, [R8.64+0x1] ; LDG.E.U8 R12, [R12.64+0x1] ; LDG.E.U8 R18, [R8.64+0x7] ; I2F.U16 R14, R14 ; I2F.U16 R7, R7 ; I2F.U16 R15, R15 ; FMUL R16, R14, 0.40000000596046447754 ; I2F.U16 R17, R17 ; FFMA R16, R7, 0.10000000149011611938, R16 ; I2F.U16 R19, R12 ; FFMA R16, R15, 0.10000000149011611938, R16 ; I2F.U16 R11, R18 ; FFMA R16, R17, 0.050000000745058059692, R16 ; FFMA R16, R19, 0.10000000149011611938, R16 ; FFMA R16, R11, 0.050000000745058059692, R16 ; F2I.U32.TRUNC.NTZ R7, R16 ; STG.E.U8 [R2.64+0x1], R7 ; LDG.E.64 R8, [R4.64+0x8] ; LDG.E R15, [R4.64] ; IMAD.WIDE R10, R6, 0x3, R8 ; LDG.E.U8 R14, [R10.64+0x5] ; IADD3 R17, R6, R15, RZ ; IMAD.WIDE R12, R0, 0x3, R8.reuse ; LDG.E.U8 R0, [R10.64+0x2] ; IMAD.WIDE R8, R17, 0x3, R8 ; LDG.E.U8 R6, [R10.64+0x8] ; IMAD.WIDE R12, R15, 0x3, R12 ; LDG.E.U8 R7, [R8.64+0x2] ; LDG.E.U8 R12, [R12.64+0x2] ; LDG.E.U8 R16, [R8.64+0x8] ; I2F.U16 R14, R14 ; I2F.U16 R0, R0 ; I2F.U16 R6, R6 ; FMUL R5, R14, 0.40000000596046447754 ; I2F.U16 R4, R7 ; FFMA R5, R0, 0.10000000149011611938, R5 ; I2F.U16 R15, R12 ; FFMA R5, R6, 0.10000000149011611938, R5 ; I2F.U16 R11, R16 ; FFMA R4, R4, 0.050000000745058059692, R5 ; FFMA R4, R15, 0.10000000149011611938, R4 ; FFMA R4, R11, 0.050000000745058059692, R4 ; F2I.U32.TRUNC.NTZ R5, R4 ; STG.E.U8 [R2.64+0x2], R5 ; EXIT ; LDG.E.U8 R14, [R14.64] ; LDG.E.U8 R16, [R16.64] ; LDG.E.U8 R18, [R12.64+-0x3] ; LDG.E.U8 R20, [R12.64] ; LDG.E.U8 R10, [R10.64] ; LDG.E.U8 R22, [R6.64] ; I2F.U16 R9, R14 ; I2F.U16 R8, R16 ; I2F.U16 R19, R18 ; FMUL R9, R9, 0.10000000149011611938 ; I2F.U16 R21, R20 ; FFMA R8, R8, 0.050000000745058059692, R9 ; I2F.U16 R23, R10 ; FFMA R8, R19, 0.10000000149011611938, R8 ; I2F.U16 R9, R22 ; FFMA R8, R21, 0.40000000596046447754, R8 ; FFMA R8, R23, 0.050000000745058059692, R8 ; FFMA R12, R9, 0.10000000149011611938, R8 ; F2I.U32.TRUNC.NTZ R15, R12 ; STG.E.U8 [R2.64], R15 ; LDG.E R17, [R4.64] ; LDG.E.64 R6, [R4.64+0x8] ; LOP3.LUT R9, RZ, R17, RZ, 0x33, !PT ; IADD3 R11, R0.reuse, -R17, RZ ; IADD3 R9, R0, R9, RZ ; IMAD.WIDE R10, R11, 0x3, R6 ; IMAD.WIDE R8, R9, 0x3, R6 ; LDG.E.U8 R10, [R10.64+0x1] ; IMAD.WIDE R12, R17.reuse, 0x3, R8 ; LDG.E.U8 R16, [R8.64+0x1] ; IMAD.WIDE R6, R0, 0x3, R6 ; LDG.E.U8 R18, [R12.64+0x1] ; IMAD.WIDE R14, R17.reuse, 0x3, R12 ; LDG.E.U8 R19, [R12.64+0x4] ; IMAD.WIDE R6, R17, 0x3, R6 ; LDG.E.U8 R14, [R14.64+0x1] ; LDG.E.U8 R20, [R6.64+0x1] ; I2F.U16 R17, R10 ; I2F.U16 R16, R16 ; I2F.U16 R18, R18 ; FMUL R17, R17, 0.10000000149011611938 ; I2F.U16 R8, R19 ; FFMA R17, R16, 0.050000000745058059692, R17 ; I2F.U16 R9, R14 ; FFMA R17, R18, 0.10000000149011611938, R17 ; I2F.U16 R11, R20 ; FFMA R8, R8, 0.40000000596046447754, R17 ; FFMA R8, R9, 0.050000000745058059692, R8 ; FFMA R12, R11, 0.10000000149011611938, R8 ; F2I.U32.TRUNC.NTZ R15, R12 ; STG.E.U8 [R2.64+0x1], R15 ; LDG.E R17, [R4.64] ; LDG.E.64 R6, [R4.64+0x8] ; LOP3.LUT R9, RZ, R17, RZ, 0x33, !PT ; IADD3 R11, R0.reuse, -R17, RZ ; IADD3 R9, R0, R9, RZ ; IMAD.WIDE R10, R11, 0x3, R6 ; IMAD.WIDE R8, R9, 0x3, R6 ; LDG.E.U8 R10, [R10.64+0x2] ; IMAD.WIDE R12, R17.reuse, 0x3, R8 ; LDG.E.U8 R14, [R8.64+0x2] ; IMAD.WIDE R6, R0, 0x3, R6 ; LDG.E.U8 R15, [R12.64+0x2] ; IMAD.WIDE R4, R17.reuse, 0x3, R12 ; LDG.E.U8 R16, [R12.64+0x5] ; IMAD.WIDE R6, R17, 0x3, R6 ; LDG.E.U8 R4, [R4.64+0x2] ; LDG.E.U8 R6, [R6.64+0x2] ; I2F.U16 R0, R10 ; I2F.U16 R14, R14 ; I2F.U16 R8, R15 ; FMUL R9, R0, 0.10000000149011611938 ; I2F.U16 R11, R16 ; FFMA R9, R14, 0.050000000745058059692, R9 ; I2F.U16 R17, R4 ; FFMA R8, R8, 0.10000000149011611938, R9 ; I2F.U16 R13, R6 ; FFMA R8, R11, 0.40000000596046447754, R8 ; FFMA R8, R17, 0.050000000745058059692, R8 ; FFMA R8, R13, 0.10000000149011611938, R8 ; F2I.U32.TRUNC.NTZ R5, R8 ; STG.E.U8 [R2.64+0x2], R5 ; EXIT ; LDG.E.U8 R16, [R16.64+0x6] ; LDG.E.U8 R14, [R14.64] ; LDG.E.U8 R19, [R12.64] ; LDG.E.U8 R21, [R12.64+0x3] ; LDG.E.U8 R6, [R6.64] ; LDG.E.U8 R23, [R10.64+0x6] ; I2F.U16 R18, R16 ; I2F.U16 R9, R14 ; I2F.U16 R20, R19 ; FMUL R18, R18, 0.050000000745058059692 ; I2F.U16 R22, R21 ; FFMA R9, R9, 0.10000000149011611938, R18 ; I2F.U16 R24, R6 ; FFMA R9, R20, 0.40000000596046447754, R9 ; I2F.U16 R18, R23 ; FFMA R9, R22, 0.10000000149011611938, R9 ; FFMA R9, R24, 0.10000000149011611938, R9 ; FFMA R9, R18, 0.050000000745058059692, R9 ; F2I.U32.TRUNC.NTZ R9, R9 ; STG.E.U8 [R2.64], R9 ; LDG.E R7, [R4.64] ; LDG.E.64 R10, [R4.64+0x8] ; IADD3 R6, R0, 0x1, RZ ; LEA R8, R8, R8, 0x1 ; IADD3 R19, -R7, R6, RZ ; IADD3 R17, R0.reuse, -R7, RZ ; IMAD.WIDE.U32 R12, R0, 0x3, R10 ; IMAD.WIDE R18, R19, 0x3, R10.reuse ; IADD3 R13, R13, R8, RZ ; IADD3 R14, P0, R12, 0x1, RZ ; IMAD.WIDE R16, R17, 0x3, R10 ; LDG.E.U8 R18, [R18.64+0x1] ; IADD3.X R15, RZ, R13, RZ, P0, !PT ; LDG.E.U8 R16, [R16.64+0x1] ; IMAD.WIDE R14, R7.reuse, 0x3, R14 ; LDG.E.U8 R9, [R12.64+0x1] ; IADD3 R7, R7, R6, RZ ; LDG.E.U8 R21, [R12.64+0x4] ; IMAD.WIDE R10, R7, 0x3, R10 ; LDG.E.U8 R14, [R14.64] ; LDG.E.U8 R23, [R10.64+0x1] ; I2F.U16 R18, R18 ; I2F.U16 R7, R16 ; I2F.U16 R22, R9 ; FMUL R20, R18, 0.050000000745058059692 ; I2F.U16 R24, R21 ; FFMA R7, R7, 0.10000000149011611938, R20 ; I2F.U16 R26, R14 ; FFMA R7, R22, 0.40000000596046447754, R7 ; I2F.U16 R12, R23 ; FFMA R7, R24, 0.10000000149011611938, R7 ; FFMA R7, R26, 0.10000000149011611938, R7 ; FFMA R7, R12, 0.050000000745058059692, R7 ; F2I.U32.TRUNC.NTZ R7, R7 ; STG.E.U8 [R2.64+0x1], R7 ; LDG.E R19, [R4.64] ; LDG.E.64 R10, [R4.64+0x8] ; IADD3 R13, R6, -R19, RZ ; IADD3 R9, R0.reuse, -R19, RZ ; IMAD.WIDE.U32 R14, R0, 0x3, R10 ; IMAD.WIDE R12, R13, 0x3, R10.reuse ; IADD3 R15, R8, R15, RZ ; IADD3 R16, P0, R14, 0x2, RZ ; IMAD.WIDE R8, R9, 0x3, R10 ; LDG.E.U8 R12, [R12.64+0x2] ; IADD3.X R17, RZ, R15, RZ, P0, !PT ; LDG.E.U8 R8, [R8.64+0x2] ; IMAD.WIDE R4, R19, 0x3, R16 ; IADD3 R19, R6, R19, RZ ; LDG.E.U8 R18, [R14.64+0x2] ; LDG.E.U8 R6, [R14.64+0x5] ; IMAD.WIDE R10, R19, 0x3, R10 ; LDG.E.U8 R4, [R4.64] ; LDG.E.U8 R10, [R10.64+0x2] ; I2F.U16 R12, R12 ; I2F.U16 R0, R8 ; I2F.U16 R9, R18 ; FMUL R7, R12, 0.050000000745058059692 ; I2F.U16 R13, R6 ; FFMA R0, R0, 0.10000000149011611938, R7 ; I2F.U16 R17, R4 ; FFMA R0, R9, 0.40000000596046447754, R0 ; I2F.U16 R7, R10 ; FFMA R0, R13, 0.10000000149011611938, R0 ; FFMA R0, R17, 0.10000000149011611938, R0 ; FFMA R0, R7, 0.050000000745058059692, R0 ; F2I.U32.TRUNC.NTZ R5, R0 ; STG.E.U8 [R2.64+0x2], R5 ; EXIT ; LDG.E.U8 R14, [R14.64] ; LDG.E.U8 R16, [R16.64] ; LDG.E.U8 R10, [R12.64+-0x3] ; LDG.E.U8 R11, [R12.64] ; I2F.U16 R7, R14 ; I2F.U16 R6, R16 ; I2F.U16 R9, R10 ; FMUL R7, R7, 0.10000000149011611938 ; I2F.U16 R11, R11 ; FFMA R6, R6, 0.050000000745058059692, R7 ; FFMA R6, R9, 0.10000000149011611938, R6 ; FFMA R7, R11, 0.40000000596046447754, R6 ; F2I.U32.TRUNC.NTZ R7, R7 ; STG.E.U8 [R2.64], R7 ; LDG.E R13, [R4.64] ; LDG.E.64 R8, [R4.64+0x8] ; IADD3 R6, R0, -0x1, RZ ; IADD3 R11, R0, -R13.reuse, RZ ; LOP3.LUT R15, RZ, R13, RZ, 0x33, !PT ; IMAD.WIDE R10, R11, 0x3, R8 ; IADD3 R15, R0, R15, RZ ; IMAD.WIDE R12, R6, 0x3, R8.reuse ; LDG.E.U8 R10, [R10.64+0x1] ; IMAD.WIDE R8, R15, 0x3, R8 ; LDG.E.U8 R16, [R12.64+0x1] ; LDG.E.U8 R7, [R8.64+0x1] ; LDG.E.U8 R17, [R12.64+0x4] ; I2F.U16 R14, R10 ; I2F.U16 R7, R7 ; I2F.U16 R15, R16 ; FMUL R14, R14, 0.10000000149011611938 ; I2F.U16 R17, R17 ; FFMA R14, R7, 0.050000000745058059692, R14 ; FFMA R14, R15, 0.10000000149011611938, R14 ; FFMA R14, R17, 0.40000000596046447754, R14 ; F2I.U32.TRUNC.NTZ R15, R14 ; STG.E.U8 [R2.64+0x1], R15 ; LDG.E R11, [R4.64] ; LDG.E.64 R8, [R4.64+0x8] ; LOP3.LUT R13, RZ, R11, RZ, 0x33, !PT ; IADD3 R7, R0, -R11, RZ ; IMAD.WIDE R10, R6, 0x3, R8 ; IADD3 R13, R0, R13, RZ ; IMAD.WIDE R6, R7, 0x3, R8.reuse ; LDG.E.U8 R12, [R10.64+0x2] ; IMAD.WIDE R8, R13, 0x3, R8 ; LDG.E.U8 R14, [R10.64+0x5] ; LDG.E.U8 R6, [R6.64+0x2] ; LDG.E.U8 R8, [R8.64+0x2] ; I2F.U16 R13, R12 ; I2F.U16 R4, R6 ; I2F.U16 R0, R8 ; I2F.U16 R15, R14 ; FMUL R5, R4, 0.10000000149011611938 ; FFMA R0, R0, 0.050000000745058059692, R5 ; FFMA R0, R13, 0.10000000149011611938, R0 ; FFMA R0, R15, 0.40000000596046447754, R0 ; F2I.U32.TRUNC.NTZ R5, R0 ; STG.E.U8 [R2.64+0x2], R5 ; EXIT ; LDG.E.64 R8, [R4.64+0x8] ; IADD3 R7, R0, -0x1, RZ ; IADD3 R13, R6, R7, RZ ; IMAD.WIDE R10, R0, 0x3, R8 ; LDG.E.U8 R15, [R10.64] ; IMAD.WIDE R8, R13, 0x3, R8 ; LDG.E.U8 R14, [R10.64+-0x3] ; IMAD.WIDE R12, R6, 0x3, R10 ; LDG.E.U8 R6, [R8.64] ; LDG.E.U8 R12, [R12.64] ; I2F.U16 R15, R15 ; I2F.U16 R14, R14 ; I2F.U16 R6, R6 ; FMUL R17, R15, 0.40000000596046447754 ; I2F.U16 R16, R12 ; FFMA R17, R14, 0.10000000149011611938, R17 ; FFMA R17, R6, 0.050000000745058059692, R17 ; FFMA R16, R16, 0.10000000149011611938, R17 ; F2I.U32.TRUNC.NTZ R17, R16 ; STG.E.U8 [R2.64], R17 ; LDG.E.64 R8, [R4.64+0x8] ; LDG.E R15, [R4.64] ; IMAD.WIDE R10, R7, 0x3, R8 ; IADD3 R19, R15, R7, RZ ; LDG.E.U8 R14, [R10.64+0x4] ; IMAD.WIDE R12, R0, 0x3, R8 ; LDG.E.U8 R6, [R10.64+0x1] ; IMAD.WIDE R8, R19, 0x3, R8 ; IMAD.WIDE R12, R15, 0x3, R12 ; LDG.E.U8 R16, [R8.64+0x1] ; LDG.E.U8 R12, [R12.64+0x1] ; I2F.U16 R14, R14 ; I2F.U16 R6, R6 ; I2F.U16 R16, R16 ; FMUL R15, R14, 0.40000000596046447754 ; I2F.U16 R18, R12 ; FFMA R15, R6, 0.10000000149011611938, R15 ; FFMA R15, R16, 0.050000000745058059692, R15 ; FFMA R15, R18, 0.10000000149011611938, R15 ; F2I.U32.TRUNC.NTZ R15, R15 ; STG.E.U8 [R2.64+0x1], R15 ; LDG.E.64 R8, [R4.64+0x8] ; LDG.E R13, [R4.64] ; IMAD.WIDE R10, R7, 0x3, R8 ; IADD3 R17, R13, R7, RZ ; LDG.E.U8 R14, [R10.64+0x5] ; IMAD.WIDE R6, R0, 0x3, R8 ; LDG.E.U8 R12, [R10.64+0x2] ; IMAD.WIDE R8, R17, 0x3, R8 ; IMAD.WIDE R6, R13, 0x3, R6 ; LDG.E.U8 R8, [R8.64+0x2] ; LDG.E.U8 R6, [R6.64+0x2] ; I2F.U16 R14, R14 ; I2F.U16 R12, R12 ; I2F.U16 R0, R8 ; FMUL R5, R14, 0.40000000596046447754 ; I2F.U16 R13, R6 ; FFMA R5, R12, 0.10000000149011611938, R5 ; FFMA R0, R0, 0.050000000745058059692, R5 ; FFMA R0, R13, 0.10000000149011611938, R0 ; F2I.U32.TRUNC.NTZ R5, R0 ; STG.E.U8 [R2.64+0x2], R5 ; EXIT ; LDG.E.64 R8, [R4.64+0x8] ; IADD3 R7, R0.reuse, 0x1, RZ ; IADD3 R11, R0, -R6, RZ ; IADD3 R13, -R6, R7, RZ ; IMAD.WIDE R12, R13, 0x3, R8 ; IMAD.WIDE R10, R11, 0x3, R8.reuse ; LDG.E.U8 R12, [R12.64] ; IMAD.WIDE R8, R0, 0x3, R8 ; LDG.E.U8 R10, [R10.64] ; LDG.E.U8 R16, [R8.64] ; LDG.E.U8 R18, [R8.64+0x3] ; I2F.U16 R14, R12 ; I2F.U16 R6, R10 ; I2F.U16 R17, R16 ; FMUL R15, R14, 0.050000000745058059692 ; I2F.U16 R19, R18 ; FFMA R6, R6, 0.10000000149011611938, R15 ; FFMA R6, R17, 0.40000000596046447754, R6 ; FFMA R6, R19, 0.10000000149011611938, R6 ; F2I.U32.TRUNC.NTZ R15, R6 ; STG.E.U8 [R2.64], R15 ; LDG.E R11, [R4.64] ; LDG.E.64 R8, [R4.64+0x8] ; IADD3 R19, -R11, R7, RZ ; IADD3 R17, R0, -R11, RZ ; IMAD.WIDE R10, R19, 0x3, R8 ; IMAD.WIDE R12, R0, 0x3, R8.reuse ; LDG.E.U8 R10, [R10.64+0x1] ; IMAD.WIDE R8, R17, 0x3, R8 ; LDG.E.U8 R16, [R12.64+0x1] ; LDG.E.U8 R6, [R8.64+0x1] ; LDG.E.U8 R17, [R12.64+0x4] ; I2F.U16 R14, R10 ; I2F.U16 R6, R6 ; I2F.U16 R16, R16 ; FMUL R15, R14, 0.050000000745058059692 ; I2F.U16 R18, R17 ; FFMA R15, R6, 0.10000000149011611938, R15 ; FFMA R15, R16, 0.40000000596046447754, R15 ; FFMA R15, R18, 0.10000000149011611938, R15 ; F2I.U32.TRUNC.NTZ R15, R15 ; STG.E.U8 [R2.64+0x1], R15 ; LDG.E R11, [R4.64] ; LDG.E.64 R8, [R4.64+0x8] ; IADD3 R7, -R11, R7, RZ ; IADD3 R13, R0, -R11, RZ ; IMAD.WIDE R6, R7, 0x3, R8 ; IMAD.WIDE R10, R0, 0x3, R8.reuse ; LDG.E.U8 R6, [R6.64+0x2] ; IMAD.WIDE R8, R13, 0x3, R8 ; LDG.E.U8 R12, [R10.64+0x2] ; LDG.E.U8 R8, [R8.64+0x2] ; LDG.E.U8 R14, [R10.64+0x5] ; I2F.U16 R4, R6 ; I2F.U16 R0, R8 ; I2F.U16 R13, R12 ; FMUL R5, R4, 0.050000000745058059692 ; I2F.U16 R15, R14 ; FFMA R0, R0, 0.10000000149011611938, R5 ; FFMA R0, R13, 0.40000000596046447754, R0 ; FFMA R0, R15, 0.10000000149011611938, R0 ; F2I.U32.TRUNC.NTZ R5, R0 ; STG.E.U8 [R2.64+0x2], R5 ; EXIT ; LDG.E.64 R10, [R4.64+0x8] ; LEA R8, R8, R8, 0x1 ; IADD3 R7, R0, 0x1, RZ ; IADD3 R17, R6, R7, RZ ; IMAD.WIDE.U32 R12, R0, 0x3, R10 ; IADD3 R13, R8, R13, RZ ; LDG.E.U8 R9, [R12.64+0x3] ; IMAD.WIDE R14, R6, 0x3, R12 ; LDG.E.U8 R6, [R12.64] ; IMAD.WIDE R10, R17, 0x3, R10 ; LDG.E.U8 R14, [R14.64] ; LDG.E.U8 R18, [R10.64] ; I2F.U16 R9, R9 ; I2F.U16 R6, R6 ; I2F.U16 R16, R14 ; FMUL R17, R9, 0.10000000149011611938 ; I2F.U16 R19, R18 ; FFMA R17, R6, 0.40000000596046447754, R17 ; FFMA R16, R16, 0.10000000149011611938, R17 ; FFMA R19, R19, 0.050000000745058059692, R16 ; F2I.U32.TRUNC.NTZ R19, R19 ; STG.E.U8 [R2.64], R19 ; LDG.E.64 R10, [R4.64+0x8] ; LDG.E R20, [R4.64] ; IMAD.WIDE.U32 R12, R0, 0x3, R10 ; IADD3 R15, R8, R13, RZ ; IADD3 R16, P0, R12, 0x1, RZ ; MOV R14, R12 ; IADD3.X R17, RZ, R15, RZ, P0, !PT ; LDG.E.U8 R9, [R14.64+0x4] ; IADD3 R21, R20.reuse, R7, RZ ; IMAD.WIDE R12, R20, 0x3, R16 ; LDG.E.U8 R6, [R14.64+0x1] ; IMAD.WIDE R10, R21, 0x3, R10 ; LDG.E.U8 R16, [R12.64] ; LDG.E.U8 R18, [R10.64+0x1] ; I2F.U16 R9, R9 ; I2F.U16 R6, R6 ; I2F.U16 R16, R16 ; FMUL R17, R9, 0.10000000149011611938 ; I2F.U16 R18, R18 ; FFMA R17, R6, 0.40000000596046447754, R17 ; FFMA R17, R16, 0.10000000149011611938, R17 ; FFMA R17, R18, 0.050000000745058059692, R17 ; F2I.U32.TRUNC.NTZ R17, R17 ; STG.E.U8 [R2.64+0x1], R17 ; LDG.E.64 R10, [R4.64+0x8] ; LDG.E R6, [R4.64] ; IMAD.WIDE.U32 R12, R0, 0x3, R10 ; IADD3 R13, R8, R13, RZ ; IADD3 R8, P0, R12, 0x2, RZ ; IADD3 R15, R6, R7, RZ ; LDG.E.U8 R14, [R12.64+0x5] ; IADD3.X R9, RZ, R13, RZ, P0, !PT ; LDG.E.U8 R0, [R12.64+0x2] ; IMAD.WIDE R6, R6, 0x3, R8 ; IMAD.WIDE R10, R15, 0x3, R10 ; LDG.E.U8 R6, [R6.64] ; LDG.E.U8 R10, [R10.64+0x2] ; I2F.U16 R14, R14 ; I2F.U16 R0, R0 ; I2F.U16 R4, R6 ; FMUL R5, R14, 0.10000000149011611938 ; I2F.U16 R9, R10 ; FFMA R5, R0, 0.40000000596046447754, R5 ; FFMA R4, R4, 0.10000000149011611938, R5 ; FFMA R4, R9, 0.050000000745058059692, R4 ; F2I.U32.TRUNC.NTZ R5, R4 ; STG.E.U8 [R2.64+0x2], R5 ; EXIT ; BRA 0x2d40; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00033fe5_00000000-6_7b66a891cd13ec272643ec496d30741ecf4d8453.cudafe1.cpp" .text #APP .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%s in %s at line %d\n" #NO_APP .text .type _ZL12cuda_checker9cudaErrorPKci, @function _ZL12cuda_checker9cudaErrorPKci: .LFB2057: .cfi_startproc testl %edi, %edi jne .L6 ret .L6: pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rsi, %rbx movl %edx, %ebp call cudaGetErrorString@PLT movq %rax, %rdx movl %ebp, %r8d movq %rbx, %rcx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %edi call exit@PLT .cfi_endproc .LFE2057: .size _ZL12cuda_checker9cudaErrorPKci, .-_ZL12cuda_checker9cudaErrorPKci .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2064: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2064: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1 .LC1: .string "wb" .LC2: .string "Unable to open file '%s'\n" .LC3: .string "P6\n" .LC4: .string "COMP3231" .LC5: .string "# Created by %s\n" .LC6: .string "%d %d\n" .LC7: .string "%d\n" .text .globl _Z8writePPMPKcP8PPMImage .type _Z8writePPMPKcP8PPMImage, @function _Z8writePPMPKcP8PPMImage: .LFB2059: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %r12 movq %rsi, %rbp leaq .LC1(%rip), %rsi call fopen@PLT testq %rax, %rax je .L12 movq %rax, %rbx leaq .LC3(%rip), %rdx movl $2, %esi movq %rax, %rdi movl $0, %eax call __fprintf_chk@PLT leaq .LC4(%rip), %rcx leaq .LC5(%rip), %rdx movl $2, %esi movq %rbx, %rdi movl $0, %eax call __fprintf_chk@PLT movl 0(%rbp), %ecx movl 4(%rbp), %r8d leaq .LC6(%rip), %rdx movl $2, %esi movq %rbx, %rdi movl $0, %eax call __fprintf_chk@PLT movl $255, %ecx leaq .LC7(%rip), %rdx movl $2, %esi movq %rbx, %rdi movl $0, %eax call __fprintf_chk@PLT movslq 4(%rbp), %rdx movl 0(%rbp), %eax leal (%rax,%rax,2), %esi movslq %esi, %rsi movq 8(%rbp), %rdi movq %rbx, %rcx call fwrite@PLT movq %rbx, %rdi call fclose@PLT popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L12: .cfi_restore_state movq %r12, %rcx leaq .LC2(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .cfi_endproc .LFE2059: .size _Z8writePPMPKcP8PPMImage, .-_Z8writePPMPKcP8PPMImage .globl _Z49__device_stub__Z11blur_kernelP8PPMImageP8PPMPixelP8PPMImageP8PPMPixel .type _Z49__device_stub__Z11blur_kernelP8PPMImageP8PPMPixelP8PPMImageP8PPMPixel, @function _Z49__device_stub__Z11blur_kernelP8PPMImageP8PPMPixelP8PPMImageP8PPMPixel: .LFB2086: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L17 .L13: movq 104(%rsp), %rax subq %fs:40, %rax jne .L18 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L17: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z11blur_kernelP8PPMImageP8PPMPixel(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L13 .L18: call __stack_chk_fail@PLT .cfi_endproc .LFE2086: .size _Z49__device_stub__Z11blur_kernelP8PPMImageP8PPMPixelP8PPMImageP8PPMPixel, .-_Z49__device_stub__Z11blur_kernelP8PPMImageP8PPMPixelP8PPMImageP8PPMPixel .globl _Z11blur_kernelP8PPMImageP8PPMPixel .type _Z11blur_kernelP8PPMImageP8PPMPixel, @function _Z11blur_kernelP8PPMImageP8PPMPixel: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z49__device_stub__Z11blur_kernelP8PPMImageP8PPMPixelP8PPMImageP8PPMPixel addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _Z11blur_kernelP8PPMImageP8PPMPixel, .-_Z11blur_kernelP8PPMImageP8PPMPixel .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC8: .string "/home/ubuntu/Datasets/Stack_v2_cuda-hip/train/7b66a891cd13ec272643ec496d30741ecf4d8453.cu" .text .globl _Z23your_gaussian_blur_funcP8PPMImage .type _Z23your_gaussian_blur_funcP8PPMImage, @function _Z23your_gaussian_blur_funcP8PPMImage: .LFB2060: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $48, %rsp .cfi_def_cfa_offset 80 movq %rdi, %rbx movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $16, %edi call malloc@PLT movq %rax, %rbp movdqu (%rbx), %xmm0 movups %xmm0, (%rax) movl (%rbx), %eax imull 4(%rbx), %eax cltq leaq (%rax,%rax,2), %rsi leaq 8(%rbp), %rdi call cudaMalloc@PLT movl %eax, %edi movl $253, %edx leaq .LC8(%rip), %r12 movq %r12, %rsi call _ZL12cuda_checker9cudaErrorPKci movl (%rbx), %eax imull 4(%rbx), %eax cltq leaq (%rax,%rax,2), %rdx movq 8(%rbx), %rsi movq 8(%rbp), %rdi movl $1, %ecx call cudaMemcpy@PLT movl %eax, %edi movl $254, %edx movq %r12, %rsi call _ZL12cuda_checker9cudaErrorPKci movq %rsp, %rdi movl $16, %esi call cudaMalloc@PLT movl %eax, %edi movl $259, %edx movq %r12, %rsi call _ZL12cuda_checker9cudaErrorPKci movl $1, %ecx movl $16, %edx movq %rbp, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl %eax, %edi movl $260, %edx movq %r12, %rsi call _ZL12cuda_checker9cudaErrorPKci movl (%rbx), %eax imull 4(%rbx), %eax cltq leaq (%rax,%rax,2), %rsi leaq 8(%rsp), %rdi call cudaMalloc@PLT movl %eax, %edi movl $263, %edx movq %r12, %rsi call _ZL12cuda_checker9cudaErrorPKci movl $10, 16(%rsp) movl $10, 20(%rsp) movl 4(%rbx), %eax leal 9(%rax), %edx movslq %edx, %rax imulq $1717986919, %rax, %rax sarq $34, %rax sarl $31, %edx subl %edx, %eax movl (%rbx), %ecx addl $9, %ecx movslq %ecx, %rdx imulq $1717986919, %rdx, %rdx sarq $34, %rdx sarl $31, %ecx subl %ecx, %edx movl %edx, 28(%rsp) movl %eax, 32(%rsp) movl $0, %r9d movl $0, %r8d movq 16(%rsp), %rdx movl $1, %ecx movq 28(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L25 .L22: movl (%rbx), %eax imull 4(%rbx), %eax cltq leaq (%rax,%rax,2), %rdx movq 8(%rbx), %rdi movl $2, %ecx movq 8(%rsp), %rsi call cudaMemcpy@PLT movl %eax, %edi movl $270, %edx leaq .LC8(%rip), %rbx movq %rbx, %rsi call _ZL12cuda_checker9cudaErrorPKci movq 8(%rsp), %rdi call cudaFree@PLT movl %eax, %edi movl $272, %edx movq %rbx, %rsi call _ZL12cuda_checker9cudaErrorPKci movq 8(%rbp), %rdi call cudaFree@PLT movl %eax, %edi movl $273, %edx movq %rbx, %rsi call _ZL12cuda_checker9cudaErrorPKci movq (%rsp), %rdi call cudaFree@PLT movl %eax, %edi movl $274, %edx movq %rbx, %rsi call _ZL12cuda_checker9cudaErrorPKci movq %rbp, %rdi call free@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L26 addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L25: .cfi_restore_state movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z49__device_stub__Z11blur_kernelP8PPMImageP8PPMPixelP8PPMImageP8PPMPixel jmp .L22 .L26: call __stack_chk_fail@PLT .cfi_endproc .LFE2060: .size _Z23your_gaussian_blur_funcP8PPMImage, .-_Z23your_gaussian_blur_funcP8PPMImage .section .rodata.str1.1 .LC9: .string "rb" .LC10: .string "input.ppm" .section .rodata.str1.8 .align 8 .LC11: .string "Invalid image format (must be 'P6')\n" .section .rodata.str1.1 .LC12: .string "Unable to allocate memory\n" .LC13: .string "%d %d" .section .rodata.str1.8 .align 8 .LC14: .string "Invalid image size (error loading '%s')\n" .section .rodata.str1.1 .LC15: .string "%d" .section .rodata.str1.8 .align 8 .LC16: .string "Invalid rgb component (error loading '%s')\n" .align 8 .LC17: .string "'%s' does not have 8-bits components\n" .section .rodata.str1.1 .LC18: .string "Error loading image '%s'\n" .LC19: .string "Time to generate: %3.1f ms \n" .LC20: .string "output.ppm" .text .globl main .type main, @function main: .LFB2061: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $64, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leaq .LC9(%rip), %rsi leaq .LC10(%rip), %rdi call fopen@PLT testq %rax, %rax je .L46 movq %rax, %rbx leaq 32(%rsp), %rdi movq %rax, %rcx movl $16, %edx movl $16, %esi call __fgets_chk@PLT testq %rax, %rax je .L47 cmpb $80, 32(%rsp) jne .L30 cmpb $54, 33(%rsp) jne .L30 movl $16, %edi call malloc@PLT movq %rax, %rbp testq %rax, %rax je .L48 movq %rbx, %rdi call getc@PLT cmpl $35, %eax jne .L33 .L34: movq %rbx, %rdi call getc@PLT cmpl $10, %eax jne .L34 movq %rbx, %rdi call getc@PLT cmpl $35, %eax je .L34 .L33: movq %rbx, %rsi movl %eax, %edi call ungetc@PLT leaq 4(%rbp), %rcx movq %rbp, %rdx leaq .LC13(%rip), %rsi movq %rbx, %rdi movl $0, %eax call __isoc23_fscanf@PLT cmpl $2, %eax jne .L49 leaq 24(%rsp), %rdx leaq .LC15(%rip), %rsi movq %rbx, %rdi movl $0, %eax call __isoc23_fscanf@PLT cmpl $1, %eax jne .L50 cmpl $255, 24(%rsp) jne .L51 .L38: movq %rbx, %rdi call fgetc@PLT cmpl $10, %eax jne .L38 movl 0(%rbp), %r13d movl 4(%rbp), %r12d movl %r13d, %eax imull %r12d, %eax cltq leaq (%rax,%rax,2), %r14 movq %r14, %rdi call malloc@PLT movq %rax, %rdi movq %rax, 8(%rbp) movslq %r12d, %rcx leal 0(%r13,%r13,2), %edx movslq %edx, %rdx movq %rbx, %r8 movq %r14, %rsi call __fread_chk@PLT movq %rax, %rdx movslq 4(%rbp), %rax cmpq %rax, %rdx jne .L52 movq %rbx, %rdi call fclose@PLT leaq 16(%rsp), %rdi call cudaEventCreate@PLT movl %eax, %edi movl $287, %edx leaq .LC8(%rip), %rbx movq %rbx, %rsi call _ZL12cuda_checker9cudaErrorPKci leaq 24(%rsp), %rdi call cudaEventCreate@PLT movl %eax, %edi movl $288, %edx movq %rbx, %rsi call _ZL12cuda_checker9cudaErrorPKci movl $0, %esi movq 16(%rsp), %rdi call cudaEventRecord@PLT movl %eax, %edi movl $289, %edx movq %rbx, %rsi call _ZL12cuda_checker9cudaErrorPKci movq %rbp, %rdi call _Z23your_gaussian_blur_funcP8PPMImage movl $0, %esi movq 24(%rsp), %rdi call cudaEventRecord@PLT movl %eax, %edi movl $293, %edx movq %rbx, %rsi call _ZL12cuda_checker9cudaErrorPKci movq 24(%rsp), %rdi call cudaEventSynchronize@PLT movl %eax, %edi movl $294, %edx movq %rbx, %rsi call _ZL12cuda_checker9cudaErrorPKci leaq 12(%rsp), %rdi movq 24(%rsp), %rdx movq 16(%rsp), %rsi call cudaEventElapsedTime@PLT movl %eax, %edi movl $295, %edx movq %rbx, %rsi call _ZL12cuda_checker9cudaErrorPKci pxor %xmm0, %xmm0 cvtss2sd 12(%rsp), %xmm0 leaq .LC19(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq %rbp, %rsi leaq .LC20(%rip), %rdi call _Z8writePPMPKcP8PPMImage movq 56(%rsp), %rax subq %fs:40, %rax jne .L53 movl $0, %eax addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L46: .cfi_restore_state leaq .LC10(%rip), %rcx leaq .LC2(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L47: leaq .LC10(%rip), %rdi call perror@PLT movl $1, %edi call exit@PLT .L30: leaq .LC11(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L48: leaq .LC12(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L49: leaq .LC10(%rip), %rcx leaq .LC14(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L50: leaq .LC10(%rip), %rcx leaq .LC16(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L51: leaq .LC10(%rip), %rcx leaq .LC17(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L52: leaq .LC10(%rip), %rcx leaq .LC18(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L53: call __stack_chk_fail@PLT .cfi_endproc .LFE2061: .size main, .-main .section .rodata.str1.8 .align 8 .LC21: .string "_Z11blur_kernelP8PPMImageP8PPMPixel" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2089: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC21(%rip), %rdx movq %rdx, %rcx leaq _Z11blur_kernelP8PPMImageP8PPMPixel(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2089: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11blur_kernelP8PPMImageP8PPMPixel ; -- Begin function _Z11blur_kernelP8PPMImageP8PPMPixel .globl _Z11blur_kernelP8PPMImageP8PPMPixel .p2align 8 .type _Z11blur_kernelP8PPMImageP8PPMPixel,@function _Z11blur_kernelP8PPMImageP8PPMPixel: ; @_Z11blur_kernelP8PPMImageP8PPMPixel ; %bb.0: s_clause 0x2 s_load_b32 s2, s[0:1], 0x1c s_load_b64 s[8:9], s[0:1], 0x0 s_load_b32 s3, s[0:1], 0x10 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v0, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s4, s2, 0xffff s_load_b64 s[6:7], s[8:9], 0x0 s_lshr_b32 s2, s2, 16 v_mad_u64_u32 v[4:5], null, s14, s4, v[1:2] v_mad_u64_u32 v[6:7], null, s15, s2, v[0:1] s_mul_i32 s3, s3, s4 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[0:1], null, s3, v6, v[4:5] s_waitcnt lgkmcnt(0) s_mul_i32 s2, s7, s6 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s2, v0 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_34 ; %bb.1: v_cmp_eq_u32_e32 vcc_lo, 0, v4 s_load_b64 s[4:5], s[0:1], 0x8 v_cmp_ne_u32_e64 s0, 0, v4 s_mov_b32 s2, exec_lo ; implicit-def: $vgpr8 ; implicit-def: $sgpr3 ; implicit-def: $vgpr2_vgpr3 v_cndmask_b32_e64 v10, 0, 1, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v6 v_cndmask_b32_e64 v5, 0, 1, vcc_lo v_cmp_ne_u32_e32 vcc_lo, 0, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v1, v5, v10 v_and_b32_e32 v1, 1, v1 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 1, v1 s_xor_b32 s2, exec_lo, s2 ; implicit-def: $vgpr0_vgpr1 s_cbranch_execz .LBB0_3 ; %bb.2: s_load_b64 s[10:11], s[8:9], 0x8 v_add_nc_u32_e32 v3, 1, v0 v_add_nc_u32_e32 v7, s6, v0 s_mov_b32 s3, 0x3d4ccccd s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) v_mad_i64_i32 v[1:2], null, v3, 3, s[10:11] v_mad_i64_i32 v[3:4], null, v0, 3, s[10:11] v_mad_i64_i32 v[5:6], null, v7, 3, s[10:11] s_clause 0xa flat_load_u8 v7, v[1:2] flat_load_u8 v8, v[1:2] offset:1 flat_load_u8 v9, v[3:4] flat_load_u8 v10, v[5:6] flat_load_u8 v11, v[3:4] offset:1 flat_load_u8 v12, v[5:6] offset:3 flat_load_u8 v13, v[5:6] offset:1 flat_load_u8 v2, v[1:2] offset:2 flat_load_u8 v14, v[5:6] offset:4 flat_load_u8 v3, v[3:4] offset:2 flat_load_u8 v4, v[5:6] offset:2 v_ashrrev_i32_e32 v1, 31, v0 s_waitcnt vmcnt(10) lgkmcnt(10) v_cvt_f32_ubyte0_e32 v7, v7 s_waitcnt vmcnt(9) lgkmcnt(9) v_cvt_f32_ubyte0_e32 v8, v8 s_waitcnt vmcnt(8) lgkmcnt(8) v_cvt_f32_ubyte0_e32 v9, v9 s_waitcnt vmcnt(7) lgkmcnt(7) v_cvt_f32_ubyte0_e32 v10, v10 s_waitcnt vmcnt(6) lgkmcnt(6) v_cvt_f32_ubyte0_e32 v11, v11 s_waitcnt vmcnt(5) lgkmcnt(5) v_cvt_f32_ubyte0_e32 v12, v12 v_mul_f32_e32 v15, 0x3dcccccd, v8 s_waitcnt vmcnt(3) lgkmcnt(3) v_cvt_f32_ubyte0_e32 v2, v2 v_cvt_f32_ubyte0_e32 v13, v13 s_waitcnt vmcnt(1) lgkmcnt(1) v_cvt_f32_ubyte0_e32 v3, v3 s_waitcnt vmcnt(0) lgkmcnt(0) v_cvt_f32_ubyte0_e32 v4, v4 v_fmac_f32_e32 v15, 0x3ecccccd, v11 v_mul_f32_e32 v8, 0x3dcccccd, v2 v_cvt_f32_ubyte0_e32 v11, v14 v_add_co_u32 v2, s1, v5, 5 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fmac_f32_e32 v15, 0x3dcccccd, v13 v_fmac_f32_e32 v8, 0x3ecccccd, v3 v_mul_f32_e32 v7, 0x3dcccccd, v7 v_add_co_ci_u32_e64 v3, s1, 0, v6, s1 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fmac_f32_e32 v15, 0x3d4ccccd, v11 v_fmac_f32_e32 v8, 0x3dcccccd, v4 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_fmac_f32_e32 v7, 0x3ecccccd, v9 v_cvt_i32_f32_e32 v6, v15 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fmac_f32_e32 v7, 0x3dcccccd, v10 v_mad_i64_i32 v[9:10], null, v0, 3, s[4:5] v_fmac_f32_e32 v7, 0x3d4ccccd, v12 s_delay_alu instid0(VALU_DEP_1) v_cvt_i32_f32_e32 v5, v7 s_clause 0x1 global_store_b8 v[9:10], v5, off global_store_b8 v[9:10], v6, off offset:1 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $vgpr6_vgpr7 ; implicit-def: $vgpr10 ; implicit-def: $vgpr5 .LBB0_3: ; %Flow626 s_or_saveexec_b32 s10, s2 v_mov_b32_e32 v7, s3 s_xor_b32 exec_lo, exec_lo, s10 s_cbranch_execz .LBB0_33 ; %bb.4: s_add_i32 s2, s7, -1 s_mov_b32 s3, exec_lo v_cmp_eq_u32_e64 s1, s2, v6 ; implicit-def: $vgpr8 ; implicit-def: $sgpr11 ; implicit-def: $vgpr2_vgpr3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v9, 0, 1, s1 v_cmp_ne_u32_e64 s1, s2, v6 v_and_b32_e32 v1, v9, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v1, 1, v1 v_cmpx_eq_u32_e32 1, v1 s_xor_b32 s3, exec_lo, s3 ; implicit-def: $vgpr0_vgpr1 s_cbranch_execz .LBB0_6 ; %bb.5: s_load_b64 s[12:13], s[8:9], 0x8 v_subrev_nc_u32_e32 v3, s6, v0 v_add_nc_u32_e32 v7, 1, v0 s_mov_b32 s11, 0x3dcccccd s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) v_mad_i64_i32 v[1:2], null, v3, 3, s[12:13] v_mad_i64_i32 v[3:4], null, v0, 3, s[12:13] v_mad_i64_i32 v[5:6], null, v7, 3, s[12:13] s_clause 0xa flat_load_u8 v7, v[1:2] offset:3 flat_load_u8 v8, v[1:2] offset:4 flat_load_u8 v9, v[1:2] flat_load_u8 v10, v[3:4] flat_load_u8 v11, v[1:2] offset:1 flat_load_u8 v12, v[5:6] flat_load_u8 v13, v[3:4] offset:1 flat_load_u8 v14, v[1:2] offset:5 flat_load_u8 v15, v[5:6] offset:1 flat_load_u8 v2, v[1:2] offset:2 flat_load_u8 v3, v[3:4] offset:2 v_ashrrev_i32_e32 v1, 31, v0 s_waitcnt vmcnt(10) lgkmcnt(10) v_cvt_f32_ubyte0_e32 v4, v7 s_waitcnt vmcnt(9) lgkmcnt(9) v_cvt_f32_ubyte0_e32 v7, v8 s_waitcnt vmcnt(8) lgkmcnt(8) v_cvt_f32_ubyte0_e32 v8, v9 s_waitcnt vmcnt(7) lgkmcnt(7) v_cvt_f32_ubyte0_e32 v9, v10 s_waitcnt vmcnt(6) lgkmcnt(6) v_cvt_f32_ubyte0_e32 v10, v11 v_dual_mul_f32 v4, 0x3d4ccccd, v4 :: v_dual_mul_f32 v7, 0x3d4ccccd, v7 s_waitcnt vmcnt(5) lgkmcnt(5) v_cvt_f32_ubyte0_e32 v11, v12 s_waitcnt vmcnt(4) lgkmcnt(4) v_cvt_f32_ubyte0_e32 v12, v13 s_waitcnt vmcnt(3) lgkmcnt(3) v_cvt_f32_ubyte0_e32 v13, v14 v_dual_fmac_f32 v4, 0x3dcccccd, v8 :: v_dual_fmac_f32 v7, 0x3dcccccd, v10 s_waitcnt vmcnt(2) lgkmcnt(2) v_cvt_f32_ubyte0_e32 v14, v15 s_waitcnt vmcnt(1) lgkmcnt(1) v_cvt_f32_ubyte0_e32 v2, v2 v_mul_f32_e32 v8, 0x3d4ccccd, v13 v_dual_fmac_f32 v4, 0x3ecccccd, v9 :: v_dual_fmac_f32 v7, 0x3ecccccd, v12 s_waitcnt vmcnt(0) lgkmcnt(0) v_cvt_f32_ubyte0_e32 v12, v3 v_mad_i64_i32 v[9:10], null, v0, 3, s[4:5] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_dual_fmac_f32 v4, 0x3dcccccd, v11 :: v_dual_fmac_f32 v7, 0x3dcccccd, v14 v_fmac_f32_e32 v8, 0x3dcccccd, v2 v_add_co_u32 v2, s2, v5, 2 v_cvt_i32_f32_e32 v4, v4 v_add_co_ci_u32_e64 v3, s2, 0, v6, s2 v_cvt_i32_f32_e32 v5, v7 v_fmac_f32_e32 v8, 0x3ecccccd, v12 s_clause 0x1 global_store_b8 v[9:10], v4, off global_store_b8 v[9:10], v5, off offset:1 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $vgpr5 ; implicit-def: $vgpr9 .LBB0_6: ; %Flow624 s_or_saveexec_b32 s7, s3 v_mov_b32_e32 v7, s11 s_xor_b32 exec_lo, exec_lo, s7 s_cbranch_execz .LBB0_32 ; %bb.7: s_add_i32 s3, s6, -1 s_mov_b32 s11, exec_lo v_cmp_eq_u32_e64 s2, s3, v4 ; implicit-def: $vgpr8 ; implicit-def: $sgpr12 ; implicit-def: $vgpr2_vgpr3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v6, 0, 1, s2 v_cmp_ne_u32_e64 s2, s3, v4 v_and_b32_e32 v1, v5, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v1, 1, v1 v_cmpx_eq_u32_e32 1, v1 s_xor_b32 s11, exec_lo, s11 ; implicit-def: $vgpr0_vgpr1 s_cbranch_execz .LBB0_9 ; %bb.8: s_load_b64 s[12:13], s[8:9], 0x8 v_add_nc_u32_e32 v1, s6, v0 v_add_nc_u32_e32 v6, -1, v0 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_i64_i32 v[2:3], null, v1, 3, s[12:13] v_mad_i64_i32 v[4:5], null, v6, 3, s[12:13] v_mad_i64_i32 v[6:7], null, v0, 3, s[12:13] v_ashrrev_i32_e32 v1, 31, v0 s_mov_b32 s12, 0x3dcccccd s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v8, s3, v2, -3 v_add_co_ci_u32_e64 v9, s3, -1, v3, s3 v_add_co_u32 v10, s3, -3, v2 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v11, s3, -1, v3, s3 s_clause 0xa flat_load_u8 v12, v[6:7] flat_load_u8 v13, v[6:7] offset:1 flat_load_u8 v14, v[4:5] flat_load_u8 v15, v[2:3] flat_load_u8 v16, v[4:5] offset:1 flat_load_u8 v17, v[2:3] offset:1 flat_load_u8 v6, v[6:7] offset:2 flat_load_u8 v7, v[10:11] flat_load_u8 v10, v[8:9] offset:1 flat_load_u8 v4, v[4:5] offset:2 flat_load_u8 v9, v[8:9] offset:2 v_add_co_u32 v2, s3, v2, 2 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v3, s3, 0, v3, s3 s_waitcnt vmcnt(10) lgkmcnt(10) v_cvt_f32_ubyte0_e32 v5, v12 s_waitcnt vmcnt(9) lgkmcnt(9) v_cvt_f32_ubyte0_e32 v8, v13 s_waitcnt vmcnt(8) lgkmcnt(8) v_cvt_f32_ubyte0_e32 v11, v14 s_waitcnt vmcnt(7) lgkmcnt(7) v_cvt_f32_ubyte0_e32 v12, v15 s_waitcnt vmcnt(6) lgkmcnt(6) v_cvt_f32_ubyte0_e32 v13, v16 v_mul_f32_e32 v14, 0x3ecccccd, v5 s_waitcnt vmcnt(4) lgkmcnt(4) v_cvt_f32_ubyte0_e32 v5, v6 v_mul_f32_e32 v15, 0x3ecccccd, v8 s_waitcnt vmcnt(3) lgkmcnt(3) v_cvt_f32_ubyte0_e32 v6, v7 s_waitcnt vmcnt(2) lgkmcnt(2) v_cvt_f32_ubyte0_e32 v7, v10 v_cvt_f32_ubyte0_e32 v10, v17 v_mul_f32_e32 v8, 0x3ecccccd, v5 v_fmac_f32_e32 v15, 0x3dcccccd, v13 s_delay_alu instid0(VALU_DEP_1) v_fmac_f32_e32 v15, 0x3d4ccccd, v7 v_fmac_f32_e32 v14, 0x3dcccccd, v11 s_waitcnt vmcnt(1) lgkmcnt(1) v_cvt_f32_ubyte0_e32 v11, v4 v_mad_i64_i32 v[4:5], null, v0, 3, s[4:5] v_fmac_f32_e32 v15, 0x3dcccccd, v10 v_fmac_f32_e32 v14, 0x3d4ccccd, v6 s_waitcnt vmcnt(0) lgkmcnt(0) v_cvt_f32_ubyte0_e32 v6, v9 v_fmac_f32_e32 v8, 0x3dcccccd, v11 v_cvt_i32_f32_e32 v9, v15 v_fmac_f32_e32 v14, 0x3dcccccd, v12 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmac_f32_e32 v8, 0x3d4ccccd, v6 ; implicit-def: $vgpr6 v_cvt_i32_f32_e32 v7, v14 s_clause 0x1 global_store_b8 v[4:5], v7, off global_store_b8 v[4:5], v9, off offset:1 ; implicit-def: $vgpr9 .LBB0_9: ; %Flow622 s_or_saveexec_b32 s11, s11 v_mov_b32_e32 v7, s12 s_xor_b32 exec_lo, exec_lo, s11 s_cbranch_execz .LBB0_31 ; %bb.10: s_load_b64 s[8:9], s[8:9], 0x8 v_and_b32_e32 v1, v9, v6 s_mov_b32 s12, exec_lo ; implicit-def: $vgpr8 ; implicit-def: $sgpr13 ; implicit-def: $vgpr2_vgpr3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v1, 1, v1 v_cmpx_eq_u32_e32 1, v1 s_xor_b32 s12, exec_lo, s12 ; implicit-def: $vgpr0_vgpr1 s_cbranch_execz .LBB0_12 ; %bb.11: v_subrev_nc_u32_e32 v3, s6, v0 v_add_nc_u32_e32 v7, -1, v0 s_mov_b32 s13, 0x3ecccccd s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_mad_i64_i32 v[1:2], null, v3, 3, s[8:9] v_mad_i64_i32 v[3:4], null, v0, 3, s[8:9] v_mad_i64_i32 v[5:6], null, v7, 3, s[8:9] flat_load_u8 v11, v[1:2] v_add_co_u32 v7, s3, -3, v1 v_add_co_ci_u32_e64 v8, s3, -1, v2, s3 v_add_co_u32 v9, s3, v1, -3 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v10, s3, -1, v2, s3 s_clause 0x9 flat_load_u8 v12, v[1:2] offset:1 flat_load_u8 v13, v[3:4] flat_load_u8 v7, v[7:8] flat_load_u8 v8, v[9:10] offset:1 flat_load_u8 v14, v[5:6] flat_load_u8 v15, v[5:6] offset:1 flat_load_u8 v9, v[9:10] offset:2 flat_load_u8 v2, v[1:2] offset:2 flat_load_u8 v10, v[3:4] offset:1 flat_load_u8 v16, v[5:6] offset:2 v_ashrrev_i32_e32 v1, 31, v0 s_waitcnt vmcnt(9) lgkmcnt(9) v_cvt_f32_ubyte0_e32 v6, v12 v_cvt_f32_ubyte0_e32 v5, v11 s_waitcnt vmcnt(7) lgkmcnt(7) v_cvt_f32_ubyte0_e32 v7, v7 v_cvt_f32_ubyte0_e32 v11, v13 s_delay_alu instid0(VALU_DEP_3) v_dual_mul_f32 v13, 0x3dcccccd, v6 :: v_dual_mul_f32 v12, 0x3dcccccd, v5 s_waitcnt vmcnt(6) lgkmcnt(6) v_cvt_f32_ubyte0_e32 v5, v8 s_waitcnt vmcnt(5) lgkmcnt(5) v_cvt_f32_ubyte0_e32 v6, v14 s_waitcnt vmcnt(2) lgkmcnt(2) v_cvt_f32_ubyte0_e32 v2, v2 v_cvt_f32_ubyte0_e32 v14, v15 v_dual_fmac_f32 v12, 0x3d4ccccd, v7 :: v_dual_fmac_f32 v13, 0x3d4ccccd, v5 v_cvt_f32_ubyte0_e32 v9, v9 s_delay_alu instid0(VALU_DEP_4) v_mul_f32_e32 v8, 0x3dcccccd, v2 s_waitcnt vmcnt(1) lgkmcnt(1) v_cvt_f32_ubyte0_e32 v7, v10 v_fmac_f32_e32 v12, 0x3dcccccd, v6 v_fmac_f32_e32 v13, 0x3dcccccd, v14 s_waitcnt vmcnt(0) lgkmcnt(0) v_cvt_f32_ubyte0_e32 v10, v16 v_fmac_f32_e32 v8, 0x3d4ccccd, v9 v_mad_i64_i32 v[5:6], null, v0, 3, s[4:5] v_fmac_f32_e32 v12, 0x3ecccccd, v11 v_fmac_f32_e32 v13, 0x3ecccccd, v7 v_add_co_u32 v2, s3, v3, 2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_ci_u32_e64 v3, s3, 0, v4, s3 v_cvt_i32_f32_e32 v4, v12 v_fmac_f32_e32 v8, 0x3dcccccd, v10 v_cvt_i32_f32_e32 v7, v13 s_clause 0x1 global_store_b8 v[5:6], v4, off global_store_b8 v[5:6], v7, off offset:1 .LBB0_12: ; %Flow620 s_or_saveexec_b32 s3, s12 v_mov_b32_e32 v7, s13 s_xor_b32 exec_lo, exec_lo, s3 s_cbranch_execz .LBB0_30 ; %bb.13: ; implicit-def: $vgpr8 ; implicit-def: $vgpr7 ; implicit-def: $vgpr2_vgpr3 s_and_saveexec_b32 s12, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s0, exec_lo, s12 ; implicit-def: $vgpr0_vgpr1 s_cbranch_execz .LBB0_27 ; %bb.14: ; implicit-def: $vgpr8 ; implicit-def: $vgpr7 ; implicit-def: $vgpr2_vgpr3 s_and_saveexec_b32 s12, s2 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s2, exec_lo, s12 ; implicit-def: $vgpr0_vgpr1 s_cbranch_execz .LBB0_24 ; %bb.15: ; implicit-def: $vgpr8 ; implicit-def: $vgpr7 ; implicit-def: $vgpr2_vgpr3 s_and_saveexec_b32 s12, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s12, exec_lo, s12 ; implicit-def: $vgpr0_vgpr1 s_cbranch_execz .LBB0_21 ; %bb.16: v_subrev_nc_u32_e32 v11, s6, v0 v_add_nc_u32_e32 v10, -1, v0 v_add_nc_u32_e32 v9, 1, v0 s_waitcnt lgkmcnt(0) v_mad_i64_i32 v[6:7], null, v0, 3, s[8:9] v_mad_i64_i32 v[4:5], null, v11, 3, s[8:9] s_mov_b32 s13, 0x3d4ccccd s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, -3, v4 v_add_co_ci_u32_e32 v2, vcc_lo, -1, v5, vcc_lo s_clause 0x2 flat_load_u8 v3, v[4:5] flat_load_u8 v12, v[4:5] offset:3 flat_load_u8 v8, v[1:2] v_mad_i64_i32 v[1:2], null, v10, 3, s[8:9] flat_load_u8 v13, v[1:2] v_mad_i64_i32 v[1:2], null, v9, 3, s[8:9] s_clause 0x1 flat_load_u8 v7, v[6:7] flat_load_u8 v1, v[1:2] s_waitcnt vmcnt(5) lgkmcnt(5) v_cvt_f32_ubyte0_e32 v2, v3 s_waitcnt vmcnt(3) lgkmcnt(3) v_cvt_f32_ubyte0_e32 v3, v8 ; implicit-def: $vgpr8 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f32_e32 v6, 0x3dcccccd, v2 v_cvt_f32_ubyte0_e32 v2, v12 v_fmac_f32_e32 v6, 0x3d4ccccd, v3 s_waitcnt vmcnt(2) lgkmcnt(2) v_cvt_f32_ubyte0_e32 v3, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_fmac_f32_e32 v6, 0x3d4ccccd, v2 s_waitcnt vmcnt(1) lgkmcnt(1) v_cvt_f32_ubyte0_e32 v2, v7 v_fmac_f32_e32 v6, 0x3dcccccd, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_fmac_f32_e32 v6, 0x3ecccccd, v2 s_waitcnt vmcnt(0) lgkmcnt(0) v_cvt_f32_ubyte0_e32 v2, v1 v_ashrrev_i32_e32 v1, 31, v0 v_fmac_f32_e32 v6, 0x3dcccccd, v2 ; implicit-def: $vgpr2_vgpr3 s_and_saveexec_b32 s14, s1 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s1, exec_lo, s14 s_cbranch_execz .LBB0_18 ; %bb.17: v_mad_i64_i32 v[2:3], null, v11, 3, s[8:9] v_add_co_u32 v7, vcc_lo, v4, -3 v_mad_i64_i32 v[11:12], null, v0, 3, s[8:9] v_add_nc_u32_e32 v17, s6, v0 v_add_co_ci_u32_e32 v8, vcc_lo, -1, v5, vcc_lo v_mad_i64_i32 v[13:14], null, v10, 3, s[8:9] flat_load_u8 v10, v[2:3] offset:1 v_mad_i64_i32 v[15:16], null, v17, 3, s[8:9] s_clause 0x5 flat_load_u8 v17, v[7:8] offset:1 flat_load_u8 v18, v[4:5] offset:4 flat_load_u8 v19, v[11:12] offset:2 flat_load_u8 v20, v[13:14] offset:2 flat_load_u8 v13, v[13:14] offset:1 flat_load_u8 v14, v[2:3] offset:2 v_mad_i64_i32 v[2:3], null, v9, 3, s[8:9] s_clause 0x2 flat_load_u8 v9, v[11:12] offset:1 flat_load_u8 v11, v[7:8] offset:2 flat_load_u8 v12, v[4:5] offset:5 v_add_co_u32 v4, vcc_lo, v15, -3 v_add_co_ci_u32_e32 v5, vcc_lo, -1, v16, vcc_lo v_add_co_u32 v7, vcc_lo, -3, v15 v_add_co_ci_u32_e32 v8, vcc_lo, -1, v16, vcc_lo s_clause 0x9 flat_load_u8 v21, v[2:3] offset:1 flat_load_u8 v2, v[2:3] offset:2 flat_load_u8 v3, v[15:16] flat_load_u8 v7, v[7:8] flat_load_u8 v22, v[4:5] offset:1 flat_load_u8 v23, v[15:16] offset:3 flat_load_u8 v24, v[15:16] offset:1 flat_load_u8 v4, v[4:5] offset:2 flat_load_u8 v5, v[15:16] offset:4 flat_load_u8 v25, v[15:16] offset:2 s_waitcnt vmcnt(17) lgkmcnt(17) v_cvt_f32_ubyte0_e32 v18, v18 v_cvt_f32_ubyte0_e32 v8, v10 v_cvt_f32_ubyte0_e32 v10, v17 s_waitcnt vmcnt(12) lgkmcnt(12) v_cvt_f32_ubyte0_e32 v9, v9 s_delay_alu instid0(VALU_DEP_3) v_mul_f32_e32 v17, 0x3dcccccd, v8 v_cvt_f32_ubyte0_e32 v8, v14 s_waitcnt vmcnt(11) lgkmcnt(11) v_cvt_f32_ubyte0_e32 v11, v11 s_waitcnt vmcnt(10) lgkmcnt(10) v_cvt_f32_ubyte0_e32 v12, v12 s_waitcnt vmcnt(8) lgkmcnt(8) v_cvt_f32_ubyte0_e32 v2, v2 v_mul_f32_e32 v8, 0x3dcccccd, v8 s_waitcnt vmcnt(6) lgkmcnt(6) v_cvt_f32_ubyte0_e32 v7, v7 v_cvt_f32_ubyte0_e32 v3, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_dual_fmac_f32 v8, 0x3d4ccccd, v11 :: v_dual_fmac_f32 v17, 0x3d4ccccd, v10 v_cvt_f32_ubyte0_e32 v10, v13 v_fmac_f32_e32 v6, 0x3d4ccccd, v7 v_cvt_f32_ubyte0_e32 v13, v21 s_delay_alu instid0(VALU_DEP_4) v_dual_fmac_f32 v8, 0x3d4ccccd, v12 :: v_dual_fmac_f32 v17, 0x3d4ccccd, v18 v_cvt_f32_ubyte0_e32 v11, v19 s_waitcnt vmcnt(3) lgkmcnt(3) v_cvt_f32_ubyte0_e32 v12, v24 s_waitcnt vmcnt(1) lgkmcnt(1) v_cvt_f32_ubyte0_e32 v5, v5 v_cvt_f32_ubyte0_e32 v4, v4 v_fmac_f32_e32 v17, 0x3dcccccd, v10 v_cvt_f32_ubyte0_e32 v10, v20 v_fmac_f32_e32 v6, 0x3dcccccd, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_fmac_f32_e32 v8, 0x3dcccccd, v10 v_fmac_f32_e32 v17, 0x3ecccccd, v9 v_cvt_f32_ubyte0_e32 v9, v22 v_cvt_f32_ubyte0_e32 v10, v23 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fmac_f32_e32 v8, 0x3ecccccd, v11 v_fmac_f32_e32 v17, 0x3dcccccd, v13 ; implicit-def: $vgpr11 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmac_f32_e32 v6, 0x3d4ccccd, v10 ; implicit-def: $vgpr10 v_fmac_f32_e32 v17, 0x3d4ccccd, v9 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_fmac_f32_e32 v8, 0x3dcccccd, v2 s_waitcnt vmcnt(0) lgkmcnt(0) v_cvt_f32_ubyte0_e32 v2, v25 v_cvt_i32_f32_e32 v6, v6 ; implicit-def: $vgpr9 v_fmac_f32_e32 v17, 0x3dcccccd, v12 v_dual_fmac_f32 v8, 0x3d4ccccd, v4 :: v_dual_fmac_f32 v17, 0x3d4ccccd, v5 v_mad_i64_i32 v[4:5], null, v0, 3, s[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_fmac_f32_e32 v8, 0x3dcccccd, v2 v_add_co_u32 v2, vcc_lo, v15, 5 v_cvt_i32_f32_e32 v7, v17 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v16, vcc_lo s_clause 0x1 global_store_b8 v[4:5], v6, off global_store_b8 v[4:5], v7, off offset:1 ; implicit-def: $vgpr6 ; implicit-def: $vgpr4_vgpr5 .LBB0_18: ; %Flow s_or_saveexec_b32 s1, s1 v_mov_b32_e32 v7, s13 s_xor_b32 exec_lo, exec_lo, s1 s_cbranch_execz .LBB0_20 ; %bb.19: v_mad_i64_i32 v[2:3], null, v11, 3, s[8:9] v_add_co_u32 v7, vcc_lo, v4, -3 v_mad_i64_i32 v[13:14], null, v0, 3, s[8:9] v_add_co_ci_u32_e32 v8, vcc_lo, -1, v5, vcc_lo v_mad_i64_i32 v[11:12], null, v10, 3, s[8:9] s_clause 0x7 flat_load_u8 v10, v[2:3] offset:1 flat_load_u8 v15, v[7:8] offset:1 flat_load_u8 v16, v[4:5] offset:4 flat_load_u8 v17, v[13:14] offset:2 flat_load_u8 v18, v[11:12] offset:2 flat_load_u8 v19, v[2:3] offset:2 flat_load_u8 v11, v[11:12] offset:1 flat_load_u8 v7, v[7:8] offset:2 v_mad_i64_i32 v[2:3], null, v9, 3, s[8:9] s_clause 0x2 flat_load_u8 v4, v[4:5] offset:5 flat_load_u8 v5, v[13:14] offset:1 flat_load_u8 v9, v[2:3] offset:1 v_cvt_i32_f32_e32 v6, v6 v_add_co_u32 v2, vcc_lo, v2, 2 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo s_waitcnt vmcnt(10) lgkmcnt(10) v_cvt_f32_ubyte0_e32 v8, v10 s_waitcnt vmcnt(9) lgkmcnt(9) v_cvt_f32_ubyte0_e32 v10, v15 s_waitcnt vmcnt(8) lgkmcnt(8) v_cvt_f32_ubyte0_e32 v13, v16 v_mul_f32_e32 v12, 0x3dcccccd, v8 s_waitcnt vmcnt(5) lgkmcnt(5) v_cvt_f32_ubyte0_e32 v8, v19 s_waitcnt vmcnt(3) lgkmcnt(3) v_cvt_f32_ubyte0_e32 v7, v7 v_fmac_f32_e32 v12, 0x3d4ccccd, v10 s_delay_alu instid0(VALU_DEP_3) v_mul_f32_e32 v8, 0x3dcccccd, v8 v_cvt_f32_ubyte0_e32 v10, v11 s_waitcnt vmcnt(2) lgkmcnt(2) v_cvt_f32_ubyte0_e32 v4, v4 s_waitcnt vmcnt(1) lgkmcnt(1) v_cvt_f32_ubyte0_e32 v5, v5 v_fmac_f32_e32 v12, 0x3d4ccccd, v13 v_fmac_f32_e32 v8, 0x3d4ccccd, v7 s_waitcnt vmcnt(0) lgkmcnt(0) v_cvt_f32_ubyte0_e32 v7, v9 v_cvt_f32_ubyte0_e32 v9, v18 v_fmac_f32_e32 v12, 0x3dcccccd, v10 v_fmac_f32_e32 v8, 0x3d4ccccd, v4 v_cvt_f32_ubyte0_e32 v10, v17 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fmac_f32_e32 v12, 0x3ecccccd, v5 v_fmac_f32_e32 v8, 0x3dcccccd, v9 v_mad_i64_i32 v[4:5], null, v0, 3, s[4:5] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_fmac_f32 v12, 0x3dcccccd, v7 :: v_dual_mov_b32 v7, 0x3dcccccd v_fmac_f32_e32 v8, 0x3ecccccd, v10 s_delay_alu instid0(VALU_DEP_2) v_cvt_i32_f32_e32 v9, v12 s_clause 0x1 global_store_b8 v[4:5], v6, off global_store_b8 v[4:5], v9, off offset:1 .LBB0_20: ; %Flow610 s_or_b32 exec_lo, exec_lo, s1 .LBB0_21: ; %Flow612 s_and_not1_saveexec_b32 s1, s12 s_cbranch_execz .LBB0_23 ; %bb.22: v_add_nc_u32_e32 v3, -1, v0 v_add_nc_u32_e32 v7, 1, v0 v_add_nc_u32_e32 v8, s6, v0 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_3) v_mad_i64_i32 v[1:2], null, v3, 3, s[8:9] v_mad_i64_i32 v[3:4], null, v0, 3, s[8:9] v_mad_i64_i32 v[5:6], null, v7, 3, s[8:9] v_mad_i64_i32 v[9:10], null, v8, 3, s[8:9] s_clause 0x3 flat_load_u8 v13, v[3:4] flat_load_u8 v14, v[1:2] flat_load_u8 v15, v[5:6] flat_load_u8 v16, v[3:4] offset:1 v_add_co_u32 v7, vcc_lo, v9, -3 v_add_co_ci_u32_e32 v8, vcc_lo, -1, v10, vcc_lo v_add_co_u32 v11, vcc_lo, -3, v9 v_add_co_ci_u32_e32 v12, vcc_lo, -1, v10, vcc_lo s_clause 0xc flat_load_u8 v17, v[9:10] flat_load_u8 v18, v[9:10] offset:3 flat_load_u8 v19, v[1:2] offset:1 flat_load_u8 v20, v[5:6] offset:1 flat_load_u8 v3, v[3:4] offset:2 flat_load_u8 v2, v[1:2] offset:2 flat_load_u8 v11, v[11:12] flat_load_u8 v12, v[7:8] offset:1 flat_load_u8 v21, v[9:10] offset:1 flat_load_u8 v7, v[7:8] offset:2 flat_load_u8 v22, v[9:10] offset:4 flat_load_u8 v23, v[9:10] offset:2 flat_load_u8 v6, v[5:6] offset:2 v_mad_i64_i32 v[4:5], null, v0, 3, s[4:5] v_ashrrev_i32_e32 v1, 31, v0 s_waitcnt vmcnt(16) lgkmcnt(16) v_cvt_f32_ubyte0_e32 v8, v13 s_waitcnt vmcnt(15) lgkmcnt(15) v_cvt_f32_ubyte0_e32 v14, v14 s_waitcnt vmcnt(14) lgkmcnt(14) v_cvt_f32_ubyte0_e32 v15, v15 s_waitcnt vmcnt(13) lgkmcnt(13) v_cvt_f32_ubyte0_e32 v13, v16 s_waitcnt vmcnt(12) lgkmcnt(12) v_cvt_f32_ubyte0_e32 v17, v17 v_mul_f32_e32 v16, 0x3ecccccd, v8 s_waitcnt vmcnt(10) lgkmcnt(10) v_cvt_f32_ubyte0_e32 v8, v19 s_waitcnt vmcnt(8) lgkmcnt(8) v_cvt_f32_ubyte0_e32 v3, v3 v_mul_f32_e32 v13, 0x3ecccccd, v13 v_cvt_f32_ubyte0_e32 v19, v20 v_fmac_f32_e32 v16, 0x3dcccccd, v14 s_waitcnt vmcnt(7) lgkmcnt(7) v_cvt_f32_ubyte0_e32 v2, v2 s_waitcnt vmcnt(6) lgkmcnt(6) v_cvt_f32_ubyte0_e32 v11, v11 v_fmac_f32_e32 v13, 0x3dcccccd, v8 v_mul_f32_e32 v8, 0x3ecccccd, v3 v_fmac_f32_e32 v16, 0x3dcccccd, v15 s_waitcnt vmcnt(5) lgkmcnt(5) v_cvt_f32_ubyte0_e32 v12, v12 s_waitcnt vmcnt(0) lgkmcnt(0) v_cvt_f32_ubyte0_e32 v6, v6 v_dual_fmac_f32 v13, 0x3dcccccd, v19 :: v_dual_fmac_f32 v8, 0x3dcccccd, v2 v_fmac_f32_e32 v16, 0x3d4ccccd, v11 v_cvt_f32_ubyte0_e32 v3, v21 v_cvt_f32_ubyte0_e32 v18, v18 s_delay_alu instid0(VALU_DEP_4) v_fmac_f32_e32 v13, 0x3d4ccccd, v12 v_cvt_f32_ubyte0_e32 v11, v7 v_fmac_f32_e32 v8, 0x3dcccccd, v6 v_fmac_f32_e32 v16, 0x3dcccccd, v17 v_cvt_f32_ubyte0_e32 v2, v22 v_fmac_f32_e32 v13, 0x3dcccccd, v3 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_dual_mov_b32 v7, 0x3d4ccccd :: v_dual_fmac_f32 v8, 0x3d4ccccd, v11 v_cvt_f32_ubyte0_e32 v6, v23 v_fmac_f32_e32 v16, 0x3d4ccccd, v18 v_fmac_f32_e32 v13, 0x3d4ccccd, v2 v_add_co_u32 v2, vcc_lo, v9, 5 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v10, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_cvt_i32_f32_e32 v9, v16 v_fmac_f32_e32 v8, 0x3dcccccd, v6 v_cvt_i32_f32_e32 v10, v13 s_clause 0x1 global_store_b8 v[4:5], v9, off global_store_b8 v[4:5], v10, off offset:1 .LBB0_23: ; %Flow613 s_or_b32 exec_lo, exec_lo, s1 .LBB0_24: ; %Flow615 s_and_not1_saveexec_b32 s1, s2 s_cbranch_execz .LBB0_26 ; %bb.25: v_subrev_nc_u32_e32 v3, s6, v0 v_add_nc_u32_e32 v7, s6, v0 v_add_nc_u32_e32 v11, -1, v0 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_mad_i64_i32 v[1:2], null, v3, 3, s[8:9] v_mad_i64_i32 v[3:4], null, v0, 3, s[8:9] v_mad_i64_i32 v[5:6], null, v7, 3, s[8:9] v_add_co_u32 v7, vcc_lo, -3, v1 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v8, vcc_lo, -1, v2, vcc_lo v_add_co_u32 v9, vcc_lo, v1, -3 v_add_co_ci_u32_e32 v10, vcc_lo, -1, v2, vcc_lo s_clause 0x5 flat_load_u8 v15, v[7:8] flat_load_u8 v16, v[3:4] flat_load_u8 v17, v[5:6] flat_load_u8 v18, v[1:2] flat_load_u8 v19, v[1:2] offset:1 flat_load_u8 v20, v[3:4] offset:1 v_mad_i64_i32 v[7:8], null, v11, 3, s[8:9] v_add_co_u32 v11, vcc_lo, v5, -3 v_add_co_ci_u32_e32 v12, vcc_lo, -1, v6, vcc_lo v_add_co_u32 v13, vcc_lo, -3, v5 v_add_co_ci_u32_e32 v14, vcc_lo, -1, v6, vcc_lo s_clause 0xa flat_load_u8 v21, v[9:10] offset:1 flat_load_u8 v22, v[7:8] flat_load_u8 v23, v[7:8] offset:1 flat_load_u8 v24, v[9:10] offset:2 flat_load_u8 v2, v[1:2] offset:2 flat_load_u8 v13, v[13:14] flat_load_u8 v14, v[11:12] offset:2 flat_load_u8 v11, v[11:12] offset:1 flat_load_u8 v12, v[5:6] offset:1 flat_load_u8 v3, v[3:4] offset:2 flat_load_u8 v4, v[7:8] offset:2 v_mad_i64_i32 v[9:10], null, v0, 3, s[4:5] v_ashrrev_i32_e32 v1, 31, v0 s_waitcnt vmcnt(14) lgkmcnt(14) v_cvt_f32_ubyte0_e32 v17, v17 s_waitcnt vmcnt(13) lgkmcnt(13) v_cvt_f32_ubyte0_e32 v8, v18 s_waitcnt vmcnt(12) lgkmcnt(12) v_cvt_f32_ubyte0_e32 v18, v19 v_cvt_f32_ubyte0_e32 v7, v16 s_waitcnt vmcnt(11) lgkmcnt(11) v_cvt_f32_ubyte0_e32 v16, v20 v_cvt_f32_ubyte0_e32 v15, v15 v_mul_f32_e32 v19, 0x3dcccccd, v8 s_waitcnt vmcnt(10) lgkmcnt(10) v_cvt_f32_ubyte0_e32 v8, v21 v_mul_f32_e32 v18, 0x3dcccccd, v18 s_waitcnt vmcnt(8) lgkmcnt(8) v_cvt_f32_ubyte0_e32 v21, v23 s_waitcnt vmcnt(5) lgkmcnt(5) v_cvt_f32_ubyte0_e32 v13, v13 v_cvt_f32_ubyte0_e32 v2, v2 v_cvt_f32_ubyte0_e32 v20, v22 v_fmac_f32_e32 v18, 0x3d4ccccd, v8 s_waitcnt vmcnt(0) lgkmcnt(0) v_cvt_f32_ubyte0_e32 v4, v4 v_cvt_f32_ubyte0_e32 v3, v3 v_mul_f32_e32 v8, 0x3dcccccd, v2 v_cvt_f32_ubyte0_e32 v2, v11 v_fmac_f32_e32 v18, 0x3dcccccd, v21 v_cvt_f32_ubyte0_e32 v11, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fmac_f32_e32 v18, 0x3ecccccd, v16 v_fmac_f32_e32 v19, 0x3d4ccccd, v15 v_cvt_f32_ubyte0_e32 v15, v24 v_fmac_f32_e32 v18, 0x3d4ccccd, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fmac_f32_e32 v19, 0x3dcccccd, v20 v_fmac_f32_e32 v8, 0x3d4ccccd, v15 v_add_co_u32 v2, vcc_lo, v5, 2 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fmac_f32_e32 v18, 0x3dcccccd, v11 v_fmac_f32_e32 v19, 0x3ecccccd, v7 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_fmac_f32 v8, 0x3dcccccd, v4 :: v_dual_mov_b32 v7, 0x3dcccccd v_cvt_f32_ubyte0_e32 v4, v14 v_fmac_f32_e32 v19, 0x3d4ccccd, v13 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_fmac_f32_e32 v8, 0x3ecccccd, v3 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v6, vcc_lo v_cvt_i32_f32_e32 v6, v18 v_fmac_f32_e32 v19, 0x3dcccccd, v17 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmac_f32_e32 v8, 0x3d4ccccd, v4 v_cvt_i32_f32_e32 v5, v19 s_clause 0x1 global_store_b8 v[9:10], v5, off global_store_b8 v[9:10], v6, off offset:1 .LBB0_26: ; %Flow616 s_or_b32 exec_lo, exec_lo, s1 .LBB0_27: ; %Flow618 s_and_not1_saveexec_b32 s0, s0 s_cbranch_execz .LBB0_29 ; %bb.28: v_subrev_nc_u32_e32 v5, s6, v0 s_waitcnt lgkmcnt(0) v_mad_i64_i32 v[1:2], null, v0, 3, s[8:9] v_add_nc_u32_e32 v7, 1, v0 v_add_nc_u32_e32 v8, s6, v0 v_mad_i64_i32 v[3:4], null, v5, 3, s[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_mad_i64_i32 v[5:6], null, v7, 3, s[8:9] v_mad_i64_i32 v[9:10], null, v8, 3, s[8:9] s_clause 0x10 flat_load_u8 v7, v[1:2] flat_load_u8 v8, v[1:2] offset:1 flat_load_u8 v11, v[3:4] offset:3 flat_load_u8 v12, v[3:4] offset:4 flat_load_u8 v13, v[3:4] flat_load_u8 v14, v[5:6] flat_load_u8 v15, v[3:4] offset:1 flat_load_u8 v16, v[9:10] flat_load_u8 v17, v[9:10] offset:3 flat_load_u8 v18, v[3:4] offset:5 flat_load_u8 v19, v[5:6] offset:1 flat_load_u8 v3, v[3:4] offset:2 flat_load_u8 v20, v[9:10] offset:1 flat_load_u8 v21, v[9:10] offset:2 flat_load_u8 v6, v[5:6] offset:2 flat_load_u8 v2, v[1:2] offset:2 flat_load_u8 v22, v[9:10] offset:4 v_mad_i64_i32 v[4:5], null, v0, 3, s[4:5] v_ashrrev_i32_e32 v1, 31, v0 s_waitcnt vmcnt(16) lgkmcnt(16) v_cvt_f32_ubyte0_e32 v7, v7 s_waitcnt vmcnt(15) lgkmcnt(15) v_cvt_f32_ubyte0_e32 v23, v8 s_waitcnt vmcnt(14) lgkmcnt(14) v_cvt_f32_ubyte0_e32 v8, v11 s_waitcnt vmcnt(13) lgkmcnt(13) v_cvt_f32_ubyte0_e32 v11, v12 s_waitcnt vmcnt(12) lgkmcnt(12) v_cvt_f32_ubyte0_e32 v12, v13 s_waitcnt vmcnt(11) lgkmcnt(11) v_cvt_f32_ubyte0_e32 v13, v14 s_waitcnt vmcnt(10) lgkmcnt(10) v_cvt_f32_ubyte0_e32 v14, v15 v_mul_f32_e32 v15, 0x3d4ccccd, v8 v_mul_f32_e32 v11, 0x3d4ccccd, v11 s_waitcnt vmcnt(7) lgkmcnt(7) v_cvt_f32_ubyte0_e32 v8, v18 v_cvt_f32_ubyte0_e32 v16, v16 s_waitcnt vmcnt(5) lgkmcnt(5) v_cvt_f32_ubyte0_e32 v3, v3 v_cvt_f32_ubyte0_e32 v17, v17 v_mul_f32_e32 v8, 0x3d4ccccd, v8 s_waitcnt vmcnt(1) lgkmcnt(1) v_cvt_f32_ubyte0_e32 v2, v2 v_cvt_f32_ubyte0_e32 v6, v6 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_fmac_f32_e32 v8, 0x3dcccccd, v3 s_waitcnt vmcnt(0) lgkmcnt(0) v_cvt_f32_ubyte0_e32 v3, v22 v_fmac_f32_e32 v8, 0x3ecccccd, v2 v_fmac_f32_e32 v15, 0x3dcccccd, v12 v_cvt_f32_ubyte0_e32 v12, v19 v_add_co_u32 v2, vcc_lo, v9, 5 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_fmac_f32_e32 v8, 0x3dcccccd, v6 v_fmac_f32_e32 v11, 0x3dcccccd, v14 v_fmac_f32_e32 v15, 0x3ecccccd, v7 v_cvt_f32_ubyte0_e32 v7, v20 v_fmac_f32_e32 v11, 0x3ecccccd, v23 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmac_f32_e32 v15, 0x3dcccccd, v13 v_fmac_f32_e32 v11, 0x3dcccccd, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fmac_f32_e32 v15, 0x3dcccccd, v16 v_cvt_f32_ubyte0_e32 v12, v21 v_fmac_f32_e32 v11, 0x3dcccccd, v7 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fmac_f32_e32 v15, 0x3d4ccccd, v17 v_fmac_f32_e32 v8, 0x3dcccccd, v12 v_mov_b32_e32 v7, 0x3d4ccccd s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fmac_f32_e32 v11, 0x3d4ccccd, v3 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v10, vcc_lo v_cvt_i32_f32_e32 v6, v15 v_cvt_i32_f32_e32 v9, v11 s_clause 0x1 global_store_b8 v[4:5], v6, off global_store_b8 v[4:5], v9, off offset:1 .LBB0_29: ; %Flow619 s_or_b32 exec_lo, exec_lo, s0 .LBB0_30: ; %Flow621 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s3 .LBB0_31: ; %Flow623 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s11 .LBB0_32: ; %Flow625 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s7 .LBB0_33: ; %.sink.split s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s10 flat_load_u8 v4, v[2:3] s_waitcnt lgkmcnt(0) v_mad_u64_u32 v[2:3], null, v0, 3, s[4:5] v_mov_b32_e32 v0, v3 s_waitcnt vmcnt(0) v_cvt_f32_ubyte0_e32 v5, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[3:4], null, v1, 3, v[0:1] v_fmac_f32_e32 v8, v7, v5 s_delay_alu instid0(VALU_DEP_1) v_cvt_i32_f32_e32 v0, v8 global_store_b8 v[2:3], v0, off offset:2 .LBB0_34: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11blur_kernelP8PPMImageP8PPMPixel .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 26 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11blur_kernelP8PPMImageP8PPMPixel, .Lfunc_end0-_Z11blur_kernelP8PPMImageP8PPMPixel ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 5056 ; NumSgprs: 18 ; NumVgprs: 26 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 3 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 26 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11blur_kernelP8PPMImageP8PPMPixel .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z11blur_kernelP8PPMImageP8PPMPixel.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 26 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "7b66a891cd13ec272643ec496d30741ecf4d8453.hip" .globl _Z8writePPMPKcP8PPMImage # -- Begin function _Z8writePPMPKcP8PPMImage .p2align 4, 0x90 .type _Z8writePPMPKcP8PPMImage,@function _Z8writePPMPKcP8PPMImage: # @_Z8writePPMPKcP8PPMImage .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rsi, %rbx movq %rdi, %r15 movl $.L.str, %esi callq fopen testq %rax, %rax je .LBB0_1 # %bb.2: movq %rax, %r14 movl $.L.str.2, %edi movl $3, %esi movl $1, %edx movq %rax, %rcx callq fwrite movl $.L.str.3, %esi movl $.L.str.4, %edx movq %r14, %rdi xorl %eax, %eax callq fprintf movl (%rbx), %edx movl 4(%rbx), %ecx movl $.L.str.5, %esi movq %r14, %rdi xorl %eax, %eax callq fprintf movl $.L.str.6, %esi movq %r14, %rdi movl $255, %edx xorl %eax, %eax callq fprintf movq 8(%rbx), %rdi movslq (%rbx), %rax leaq (%rax,%rax,2), %rsi movslq 4(%rbx), %rdx movq %r14, %rcx callq fwrite movq %r14, %rdi popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 jmp fclose # TAILCALL .LBB0_1: .cfi_def_cfa_offset 32 movq stderr(%rip), %rdi movl $.L.str.1, %esi movq %r15, %rdx xorl %eax, %eax callq fprintf movl $1, %edi callq exit .Lfunc_end0: .size _Z8writePPMPKcP8PPMImage, .Lfunc_end0-_Z8writePPMPKcP8PPMImage .cfi_endproc # -- End function .globl _Z26__device_stub__blur_kernelP8PPMImageP8PPMPixel # -- Begin function _Z26__device_stub__blur_kernelP8PPMImageP8PPMPixel .p2align 4, 0x90 .type _Z26__device_stub__blur_kernelP8PPMImageP8PPMPixel,@function _Z26__device_stub__blur_kernelP8PPMImageP8PPMPixel: # @_Z26__device_stub__blur_kernelP8PPMImageP8PPMPixel .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z11blur_kernelP8PPMImageP8PPMPixel, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end1: .size _Z26__device_stub__blur_kernelP8PPMImageP8PPMPixel, .Lfunc_end1-_Z26__device_stub__blur_kernelP8PPMImageP8PPMPixel .cfi_endproc # -- End function .globl _Z23your_gaussian_blur_funcP8PPMImage # -- Begin function _Z23your_gaussian_blur_funcP8PPMImage .p2align 4, 0x90 .type _Z23your_gaussian_blur_funcP8PPMImage,@function _Z23your_gaussian_blur_funcP8PPMImage: # @_Z23your_gaussian_blur_funcP8PPMImage .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $96, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %r15 movl $16, %edi callq malloc movq %rax, %rbx movups (%r15), %xmm0 movups %xmm0, (%rax) leaq 8(%rax), %r14 movslq (%r15), %rax movslq 4(%r15), %rcx imulq %rax, %rcx leaq (%rcx,%rcx,2), %rsi movq %r14, %rdi callq hipMalloc testl %eax, %eax jne .LBB2_1 # %bb.3: # %_ZL12cuda_checker10hipError_tPKci.exit movq (%r14), %rdi movq 8(%r15), %rsi movslq (%r15), %rax movslq 4(%r15), %rcx imulq %rax, %rcx leaq (%rcx,%rcx,2), %rdx movl $1, %ecx callq hipMemcpy testl %eax, %eax jne .LBB2_4 # %bb.5: # %_ZL12cuda_checker10hipError_tPKci.exit26 leaq 8(%rsp), %rdi movl $16, %esi callq hipMalloc testl %eax, %eax jne .LBB2_6 # %bb.7: # %_ZL12cuda_checker10hipError_tPKci.exit28 movq 8(%rsp), %rdi movl $16, %edx movq %rbx, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax jne .LBB2_8 # %bb.9: # %_ZL12cuda_checker10hipError_tPKci.exit30 movslq (%r15), %rax movslq 4(%r15), %rcx imulq %rax, %rcx leaq (%rcx,%rcx,2), %rsi movq %rsp, %rdi callq hipMalloc testl %eax, %eax jne .LBB2_10 # %bb.11: # %_ZL12cuda_checker10hipError_tPKci.exit32 movl (%r15), %eax movl 4(%r15), %ecx addl $9, %eax cltq imulq $1717986919, %rax, %rax # imm = 0x66666667 movq %rax, %rdx shrq $63, %rdx sarq $34, %rax addl %edx, %eax addl $9, %ecx movslq %ecx, %rcx imulq $1717986919, %rcx, %rdi # imm = 0x66666667 movq %rdi, %rcx shrq $63, %rcx sarq $34, %rdi addl %ecx, %edi shlq $32, %rdi orq %rax, %rdi movabsq $42949672970, %rdx # imm = 0xA0000000A movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_13 # %bb.12: movq 8(%rsp), %rax movq (%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z11blur_kernelP8PPMImageP8PPMPixel, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_13: movq 8(%r15), %rdi movq (%rsp), %rsi movslq (%r15), %rax movslq 4(%r15), %rcx imulq %rax, %rcx leaq (%rcx,%rcx,2), %rdx movl $2, %ecx callq hipMemcpy testl %eax, %eax jne .LBB2_14 # %bb.15: # %_ZL12cuda_checker10hipError_tPKci.exit34 movq (%rsp), %rdi callq hipFree testl %eax, %eax jne .LBB2_16 # %bb.17: # %_ZL12cuda_checker10hipError_tPKci.exit36 movq (%r14), %rdi callq hipFree testl %eax, %eax jne .LBB2_18 # %bb.19: # %_ZL12cuda_checker10hipError_tPKci.exit38 movq 8(%rsp), %rdi callq hipFree testl %eax, %eax jne .LBB2_20 # %bb.21: # %_ZL12cuda_checker10hipError_tPKci.exit40 movq %rbx, %rdi callq free addq $96, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB2_1: .cfi_def_cfa_offset 128 movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $255, %ecx jmp .LBB2_2 .LBB2_4: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $256, %ecx # imm = 0x100 jmp .LBB2_2 .LBB2_6: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $261, %ecx # imm = 0x105 jmp .LBB2_2 .LBB2_8: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $262, %ecx # imm = 0x106 jmp .LBB2_2 .LBB2_10: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $265, %ecx # imm = 0x109 jmp .LBB2_2 .LBB2_14: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $272, %ecx # imm = 0x110 jmp .LBB2_2 .LBB2_16: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $274, %ecx # imm = 0x112 jmp .LBB2_2 .LBB2_18: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $275, %ecx # imm = 0x113 jmp .LBB2_2 .LBB2_20: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $276, %ecx # imm = 0x114 .LBB2_2: xorl %eax, %eax callq printf movl $1, %edi callq exit .Lfunc_end2: .size _Z23your_gaussian_blur_funcP8PPMImage, .Lfunc_end2-_Z23your_gaussian_blur_funcP8PPMImage .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $40, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $.L.str.8, %edi movl $.L.str.12, %esi callq fopen testq %rax, %rax je .LBB3_1 # %bb.3: movq %rax, %r14 leaq 16(%rsp), %rdi movl $16, %esi movq %rax, %rdx callq fgets testq %rax, %rax je .LBB3_36 # %bb.4: cmpb $80, 16(%rsp) jne .LBB3_6 # %bb.5: cmpb $54, 17(%rsp) jne .LBB3_6 # %bb.8: movl $16, %edi callq malloc testq %rax, %rax je .LBB3_9 # %bb.10: movq %rax, %rbx .p2align 4, 0x90 .LBB3_11: # =>This Loop Header: Depth=1 # Child Loop BB3_12 Depth 2 movq %r14, %rdi callq getc cmpl $35, %eax jne .LBB3_13 .LBB3_12: # %.preheader44.i # Parent Loop BB3_11 Depth=1 # => This Inner Loop Header: Depth=2 movq %r14, %rdi callq getc cmpl $10, %eax jne .LBB3_12 jmp .LBB3_11 .LBB3_13: # %._crit_edge.i movl %eax, %edi movq %r14, %rsi callq ungetc movq %rbx, %rcx addq $4, %rcx movl $.L.str.15, %esi movq %r14, %rdi movq %rbx, %rdx xorl %eax, %eax callq __isoc23_fscanf cmpl $2, %eax jne .LBB3_14 # %bb.15: movq %rsp, %rdx movl $.L.str.17, %esi movq %r14, %rdi xorl %eax, %eax callq __isoc23_fscanf cmpl $1, %eax jne .LBB3_16 # %bb.17: cmpl $255, (%rsp) jne .LBB3_18 .p2align 4, 0x90 .LBB3_19: # %.preheader.i # =>This Inner Loop Header: Depth=1 movq %r14, %rdi callq fgetc cmpl $10, %eax jne .LBB3_19 # %bb.20: movslq (%rbx), %rax movslq 4(%rbx), %r15 leaq (%rax,%rax,2), %r12 movq %r12, %rdi imulq %r15, %rdi callq malloc movq %rax, 8(%rbx) movq %rax, %rdi movq %r12, %rsi movq %r15, %rdx movq %r14, %rcx callq fread movslq 4(%rbx), %rcx cmpq %rcx, %rax jne .LBB3_21 # %bb.22: # %_ZL7readPPMPKc.exit movq %r14, %rdi callq fclose leaq 16(%rsp), %rdi callq hipEventCreate testl %eax, %eax jne .LBB3_23 # %bb.25: # %_ZL12cuda_checker10hipError_tPKci.exit movq %rsp, %rdi callq hipEventCreate testl %eax, %eax jne .LBB3_26 # %bb.27: # %_ZL12cuda_checker10hipError_tPKci.exit4 movq 16(%rsp), %rdi xorl %esi, %esi callq hipEventRecord testl %eax, %eax jne .LBB3_28 # %bb.29: # %_ZL12cuda_checker10hipError_tPKci.exit6 movq %rbx, %rdi callq _Z23your_gaussian_blur_funcP8PPMImage movq (%rsp), %rdi xorl %esi, %esi callq hipEventRecord testl %eax, %eax jne .LBB3_30 # %bb.31: # %_ZL12cuda_checker10hipError_tPKci.exit8 movq (%rsp), %rdi callq hipEventSynchronize testl %eax, %eax jne .LBB3_32 # %bb.33: # %_ZL12cuda_checker10hipError_tPKci.exit10 movq 16(%rsp), %rsi movq (%rsp), %rdx leaq 12(%rsp), %rdi callq hipEventElapsedTime testl %eax, %eax jne .LBB3_34 # %bb.35: # %_ZL12cuda_checker10hipError_tPKci.exit12 movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.9, %edi movb $1, %al callq printf movl $.L.str.10, %edi movq %rbx, %rsi callq _Z8writePPMPKcP8PPMImage xorl %eax, %eax addq $40, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB3_1: .cfi_def_cfa_offset 80 movq stderr(%rip), %rdi movl $.L.str.1, %esi jmp .LBB3_2 .LBB3_36: movl $.L.str.8, %edi callq perror movl $1, %edi callq exit .LBB3_6: movq stderr(%rip), %rcx movl $.L.str.13, %edi movl $36, %esi jmp .LBB3_7 .LBB3_9: movq stderr(%rip), %rcx movl $.L.str.14, %edi movl $26, %esi .LBB3_7: movl $1, %edx callq fwrite movl $1, %edi callq exit .LBB3_14: movq stderr(%rip), %rdi movl $.L.str.16, %esi jmp .LBB3_2 .LBB3_16: movq stderr(%rip), %rdi movl $.L.str.18, %esi jmp .LBB3_2 .LBB3_18: movq stderr(%rip), %rdi movl $.L.str.19, %esi jmp .LBB3_2 .LBB3_21: movq stderr(%rip), %rdi movl $.L.str.20, %esi .LBB3_2: movl $.L.str.8, %edx xorl %eax, %eax callq fprintf movl $1, %edi callq exit .LBB3_23: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $289, %ecx # imm = 0x121 jmp .LBB3_24 .LBB3_26: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $290, %ecx # imm = 0x122 jmp .LBB3_24 .LBB3_28: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $291, %ecx # imm = 0x123 jmp .LBB3_24 .LBB3_30: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $295, %ecx # imm = 0x127 jmp .LBB3_24 .LBB3_32: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $296, %ecx # imm = 0x128 jmp .LBB3_24 .LBB3_34: movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movl $.L.str.7, %edx movq %rax, %rsi movl $297, %ecx # imm = 0x129 .LBB3_24: xorl %eax, %eax callq printf movl $1, %edi callq exit .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11blur_kernelP8PPMImageP8PPMPixel, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "wb" .size .L.str, 3 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Unable to open file '%s'\n" .size .L.str.1, 26 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "P6\n" .size .L.str.2, 4 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "# Created by %s\n" .size .L.str.3, 17 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "COMP3231" .size .L.str.4, 9 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "%d %d\n" .size .L.str.5, 7 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "%d\n" .size .L.str.6, 4 .type _Z11blur_kernelP8PPMImageP8PPMPixel,@object # @_Z11blur_kernelP8PPMImageP8PPMPixel .section .rodata,"a",@progbits .globl _Z11blur_kernelP8PPMImageP8PPMPixel .p2align 3, 0x0 _Z11blur_kernelP8PPMImageP8PPMPixel: .quad _Z26__device_stub__blur_kernelP8PPMImageP8PPMPixel .size _Z11blur_kernelP8PPMImageP8PPMPixel, 8 .type .L.str.7,@object # @.str.7 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.7: .asciz "/home/ubuntu/Datasets/Stack_v2_cuda-hip-as/7b66a891cd13ec272643ec496d30741ecf4d8453.hip" .size .L.str.7, 88 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "input.ppm" .size .L.str.8, 10 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Time to generate: %3.1f ms \n" .size .L.str.9, 30 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "output.ppm" .size .L.str.10, 11 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "%s in %s at line %d\n" .size .L.str.11, 21 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz "rb" .size .L.str.12, 3 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz "Invalid image format (must be 'P6')\n" .size .L.str.13, 37 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz "Unable to allocate memory\n" .size .L.str.14, 27 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "%d %d" .size .L.str.15, 6 .type .L.str.16,@object # @.str.16 .L.str.16: .asciz "Invalid image size (error loading '%s')\n" .size .L.str.16, 41 .type .L.str.17,@object # @.str.17 .L.str.17: .asciz "%d" .size .L.str.17, 3 .type .L.str.18,@object # @.str.18 .L.str.18: .asciz "Invalid rgb component (error loading '%s')\n" .size .L.str.18, 44 .type .L.str.19,@object # @.str.19 .L.str.19: .asciz "'%s' does not have 8-bits components\n" .size .L.str.19, 38 .type .L.str.20,@object # @.str.20 .L.str.20: .asciz "Error loading image '%s'\n" .size .L.str.20, 26 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z11blur_kernelP8PPMImageP8PPMPixel" .size .L__unnamed_1, 36 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub__blur_kernelP8PPMImageP8PPMPixel .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z11blur_kernelP8PPMImageP8PPMPixel .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
18,575
7,725
20,276
9,253
108
code for sm_80 Function : _Z11dot_productPKiS0_Pi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R7, SR_TID.X ; IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE.U32 R2, R7, R4, c[0x0][0x160] ; IMAD.WIDE.U32 R4, R7.reuse, R4, c[0x0][0x168] ; LDG.E R3, [R2.64] ; LDG.E R4, [R4.64] ; ISETP.NE.AND P0, PT, R7, RZ, PT ; IMAD R0, R4, R3, RZ ; STS [R7.X4], R0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P0 EXIT ; LDS.128 R8, [RZ] ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; LDS.128 R24, [0x10] ; LDS.128 R4, [0x20] ; LDS.128 R20, [0x30] ; LDS.128 R16, [0x40] ; LDS.128 R12, [0x50] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x60] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x70] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x80] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x90] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0xa0] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0xb0] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0xc0] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0xd0] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0xe0] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0xf0] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x100] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x110] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x120] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x130] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x140] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x150] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x160] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x170] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x180] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x190] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x1a0] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x1b0] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x1c0] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x1d0] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x1e0] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x1f0] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x200] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x210] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x220] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x230] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x240] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x250] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x260] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x270] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x280] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x290] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x2a0] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x2b0] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x2c0] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x2d0] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x2e0] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x2f0] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x300] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x310] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x320] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x330] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x340] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x350] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x360] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x370] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x380] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x390] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x3a0] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x3b0] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x3c0] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x3d0] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x3e0] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x3f0] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x400] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x410] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x420] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x430] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x440] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x450] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x460] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x470] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x480] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x490] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x4a0] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x4b0] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x4c0] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x4d0] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x4e0] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x4f0] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x500] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x510] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x520] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x530] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x540] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x550] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x560] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x570] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x580] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x590] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x5a0] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x5b0] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x5c0] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x5d0] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x5e0] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x5f0] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x600] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x610] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x620] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x630] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x640] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x650] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x660] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x670] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x680] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x690] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x6a0] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x6b0] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x6c0] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x6d0] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x6e0] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x6f0] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x700] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x710] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x720] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x730] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x740] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x750] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x760] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x770] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x780] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x790] ; IADD3 R4, R6, R5, R4 ; IADD3 R20, R20, R7, R4 ; LDS.128 R4, [0x7a0] ; IADD3 R20, R22, R21, R20 ; IADD3 R16, R16, R23, R20 ; LDS.128 R20, [0x7b0] ; IADD3 R16, R18, R17, R16 ; IADD3 R12, R12, R19, R16 ; LDS.128 R16, [0x7c0] ; IADD3 R12, R14, R13, R12 ; IADD3 R8, R8, R15, R12 ; LDS.128 R12, [0x7d0] ; IADD3 R8, R10, R9, R8 ; IADD3 R24, R24, R11, R8 ; LDS.128 R8, [0x7e0] ; IADD3 R24, R26, R25, R24 ; IADD3 R4, R4, R27, R24 ; LDS.128 R24, [0x7f0] ; IADD3 R4, R6, R5, R4 ; IADD3 R4, R20, R7, R4 ; IADD3 R4, R22, R21, R4 ; IADD3 R4, R16, R23, R4 ; IADD3 R4, R18, R17, R4 ; IADD3 R4, R12, R19, R4 ; IADD3 R4, R14, R13, R4 ; IADD3 R4, R8, R15, R4 ; IADD3 R4, R10, R9, R4 ; IADD3 R4, R24, R11, R4 ; IADD3 R4, R26, R25, R4 ; IMAD.IADD R27, R4, 0x1, R27 ; STG.E [R2.64], R27 ; EXIT ; BRA 0x1910; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000735df_00000000-6_4ffdbbabee4f61da9c6560ec49d62a1c1b8fa719.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z37__device_stub__Z11dot_productPKiS0_PiPKiS0_Pi .type _Z37__device_stub__Z11dot_productPKiS0_PiPKiS0_Pi, @function _Z37__device_stub__Z11dot_productPKiS0_PiPKiS0_Pi: .LFB2082: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z11dot_productPKiS0_Pi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z37__device_stub__Z11dot_productPKiS0_PiPKiS0_Pi, .-_Z37__device_stub__Z11dot_productPKiS0_PiPKiS0_Pi .globl _Z11dot_productPKiS0_Pi .type _Z11dot_productPKiS0_Pi, @function _Z11dot_productPKiS0_Pi: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z37__device_stub__Z11dot_productPKiS0_PiPKiS0_Pi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z11dot_productPKiS0_Pi, .-_Z11dot_productPKiS0_Pi .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "DEBUG: Size of 'int' type: %lu\n" .align 8 .LC1: .string "DEBUG: Total footprint size: %d bytes\n" .section .rodata.str1.1,"aMS",@progbits,1 .LC2: .string "DEBUG: a[%d]=%d, b[%d]=%d\n" .section .rodata.str1.8 .align 8 .LC3: .string "INFO: Launching CUDA kernel: dot product with blocks=%d, threads=%d..." .section .rodata.str1.1 .LC4: .string " Done\n" .LC7: .string "INFO: PASS\n" .LC8: .string "ERROR: *** FAILED *** sum=%d\n" .LC9: .string "DEBUG: a[0]=%d, b[0]=%d\n" .section .rodata.str1.8 .align 8 .LC10: .string "DEBUG: a[%d]=%d, b[%d]=%d, c=%d\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $72, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leaq 24(%rsp), %rdi call time@PLT movl %eax, %edi call srand@PLT movl $4, %edx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $2048, %edx leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %rsp, %rdi movl $2048, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $2048, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT movl $2048, %edi call malloc@PLT movq %rax, %rbp movl $2048, %edi call malloc@PLT movq %rax, %rbx movl $4, %edi call malloc@PLT movq %rax, %r12 movl $0, %eax .L12: movl $5, 0(%rbp,%rax) movl $5, (%rbx,%rax) addq $4, %rax cmpq $2048, %rax jne .L12 movl 0(%rbp), %ecx movl (%rbx), %r9d movl $0, %r8d movl $0, %edx leaq .LC2(%rip), %r13 movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl 4(%rbp), %ecx movl 4(%rbx), %r9d movl $1, %r8d movl $1, %edx movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %ecx movl $2048, %edx movq %rbp, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $2048, %edx movq %rbx, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $512, %ecx movl $1, %edx leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $512, 44(%rsp) movl $1, 48(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L24 .L13: leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $2, %ecx movl $4, %edx movq 16(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT movl $0, %eax movl $0, %ecx .L14: movl 0(%rbp,%rax), %edx imull (%rbx,%rax), %edx addl %edx, %ecx addq $4, %rax cmpq $2048, %rax jne .L14 movl %ecx, %eax subl (%r12), %eax pxor %xmm0, %xmm0 cvtsi2sdl %eax, %xmm0 andpd .LC5(%rip), %xmm0 movsd .LC6(%rip), %xmm1 comisd %xmm0, %xmm1 jbe .L22 leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L17: movl (%rbx), %ecx movl 0(%rbp), %edx leaq .LC9(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl 4(%rbp), %ecx subq $8, %rsp .cfi_def_cfa_offset 120 movl (%r12), %eax pushq %rax .cfi_def_cfa_offset 128 movl 4(%rbx), %r9d movl $1, %r8d movl $1, %edx leaq .LC10(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %rbp, %rdi call free@PLT movq %rbx, %rdi call free@PLT movq %r12, %rdi call free@PLT addq $16, %rsp .cfi_def_cfa_offset 112 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT call cudaDeviceReset@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L25 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L24: .cfi_restore_state movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z37__device_stub__Z11dot_productPKiS0_PiPKiS0_Pi jmp .L13 .L22: movl %ecx, %edx leaq .LC8(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L17 .L25: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC11: .string "_Z11dot_productPKiS0_Pi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC11(%rip), %rdx movq %rdx, %rcx leaq _Z11dot_productPKiS0_Pi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC5: .long -1 .long 2147483647 .long 0 .long 0 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC6: .long -1998362383 .long 1055193269 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11dot_productPKiS0_Pi ; -- Begin function _Z11dot_productPKiS0_Pi .globl _Z11dot_productPKiS0_Pi .p2align 8 .type _Z11dot_productPKiS0_Pi,@function _Z11dot_productPKiS0_Pi: ; @_Z11dot_productPKiS0_Pi ; %bb.0: s_load_b128 s[4:7], s[0:1], 0x0 v_lshlrev_b32_e32 v1, 2, v0 s_mov_b32 s2, 0 s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b32 v2, v1, s[4:5] global_load_b32 v3, v1, s[6:7] s_waitcnt vmcnt(0) v_mul_lo_u32 v2, v3, v2 ds_store_b32 v1, v2 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_4 ; %bb.1: ; %.preheader.preheader v_mov_b32_e32 v0, 0 .LBB0_2: ; %.preheader ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v1, s2 s_add_i32 s2, s2, 4 s_delay_alu instid0(SALU_CYCLE_1) s_cmpk_eq_i32 s2, 0x800 ds_load_b32 v1, v1 s_waitcnt lgkmcnt(0) v_add_nc_u32_e32 v0, v1, v0 s_cbranch_scc0 .LBB0_2 ; %bb.3: s_load_b64 s[0:1], s[0:1], 0x10 v_mov_b32_e32 v1, 0 s_waitcnt lgkmcnt(0) global_store_b32 v1, v0, s[0:1] .LBB0_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11dot_productPKiS0_Pi .amdhsa_group_segment_fixed_size 2048 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 8 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11dot_productPKiS0_Pi, .Lfunc_end0-_Z11dot_productPKiS0_Pi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 164 ; NumSgprs: 8 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 2048 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 8 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 2048 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11dot_productPKiS0_Pi .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z11dot_productPKiS0_Pi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "4ffdbbabee4f61da9c6560ec49d62a1c1b8fa719.hip" .globl _Z26__device_stub__dot_productPKiS0_Pi # -- Begin function _Z26__device_stub__dot_productPKiS0_Pi .p2align 4, 0x90 .type _Z26__device_stub__dot_productPKiS0_Pi,@function _Z26__device_stub__dot_productPKiS0_Pi: # @_Z26__device_stub__dot_productPKiS0_Pi .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z11dot_productPKiS0_Pi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z26__device_stub__dot_productPKiS0_Pi, .Lfunc_end0-_Z26__device_stub__dot_productPKiS0_Pi .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI1_0: .quad 0x7fffffffffffffff # double NaN .quad 0x7fffffffffffffff # double NaN .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI1_1: .quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $136, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 128(%rsp), %rdi callq time movl %eax, %edi callq srand xorl %r12d, %r12d movl $.L.str, %edi movl $4, %esi xorl %eax, %eax callq printf movl $.L.str.1, %edi movl $2048, %esi # imm = 0x800 xorl %eax, %eax callq printf leaq 16(%rsp), %rdi movl $2048, %esi # imm = 0x800 callq hipMalloc leaq 8(%rsp), %rdi movl $2048, %esi # imm = 0x800 callq hipMalloc movq %rsp, %rdi movl $4, %esi callq hipMalloc movl $2048, %edi # imm = 0x800 callq malloc movq %rax, %rbx movl $2048, %edi # imm = 0x800 callq malloc movq %rax, %r14 movl $4, %edi callq malloc movq %rax, %r15 .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $5, (%rbx,%r12,4) movl $5, (%r14,%r12,4) incq %r12 cmpq $512, %r12 # imm = 0x200 jne .LBB1_1 # %bb.2: movl (%rbx), %edx movl (%r14), %r8d xorl %r12d, %r12d movl $.L.str.2, %edi xorl %esi, %esi xorl %ecx, %ecx xorl %eax, %eax callq printf movl 4(%rbx), %edx movl 4(%r14), %r8d movl $.L.str.2, %edi movl $1, %esi movl $1, %ecx xorl %eax, %eax callq printf movq 16(%rsp), %rdi movl $2048, %edx # imm = 0x800 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi movl $2048, %edx # imm = 0x800 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movl $.L.str.3, %edi movl $1, %esi movl $512, %edx # imm = 0x200 xorl %eax, %eax callq printf movabsq $4294967297, %rdi # imm = 0x100000001 leaq 511(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 16(%rsp), %rax movq 8(%rsp), %rcx movq (%rsp), %rdx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movq %rdx, 72(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z11dot_productPKiS0_Pi, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: movl $.Lstr, %edi callq puts@PLT movq (%rsp), %rsi movl $4, %edx movq %r15, %rdi movl $2, %ecx callq hipMemcpy xorl %eax, %eax .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 movl (%r14,%rax,4), %ecx imull (%rbx,%rax,4), %ecx addl %ecx, %r12d incq %rax cmpq $512, %rax # imm = 0x200 jne .LBB1_5 # %bb.6: movl %r12d, %eax subl (%r15), %eax cvtsi2sd %eax, %xmm0 andpd .LCPI1_0(%rip), %xmm0 movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero ucomisd %xmm0, %xmm1 jbe .LBB1_8 # %bb.7: movl $.Lstr.1, %edi callq puts@PLT jmp .LBB1_9 .LBB1_8: movl $.L.str.6, %edi movl %r12d, %esi xorl %eax, %eax callq printf .LBB1_9: movl (%rbx), %esi movl (%r14), %edx movl $.L.str.7, %edi xorl %eax, %eax callq printf movl 4(%rbx), %edx movl 4(%r14), %r8d movl (%r15), %r9d movl $.L.str.8, %edi movl $1, %esi movl $1, %ecx xorl %eax, %eax callq printf movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree callq hipDeviceReset xorl %eax, %eax addq $136, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11dot_productPKiS0_Pi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z11dot_productPKiS0_Pi,@object # @_Z11dot_productPKiS0_Pi .section .rodata,"a",@progbits .globl _Z11dot_productPKiS0_Pi .p2align 3, 0x0 _Z11dot_productPKiS0_Pi: .quad _Z26__device_stub__dot_productPKiS0_Pi .size _Z11dot_productPKiS0_Pi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "DEBUG: Size of 'int' type: %lu\n" .size .L.str, 32 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "DEBUG: Total footprint size: %d bytes\n" .size .L.str.1, 39 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "DEBUG: a[%d]=%d, b[%d]=%d\n" .size .L.str.2, 27 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "INFO: Launching CUDA kernel: dot product with blocks=%d, threads=%d..." .size .L.str.3, 71 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "ERROR: *** FAILED *** sum=%d\n" .size .L.str.6, 30 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "DEBUG: a[0]=%d, b[0]=%d\n" .size .L.str.7, 25 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "DEBUG: a[%d]=%d, b[%d]=%d, c=%d\n" .size .L.str.8, 33 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z11dot_productPKiS0_Pi" .size .L__unnamed_1, 24 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz " Done" .size .Lstr, 7 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "INFO: PASS" .size .Lstr.1, 11 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub__dot_productPKiS0_Pi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z11dot_productPKiS0_Pi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
8,746
4,333
2,095
4,624
109
code for sm_80 Function : _Z5PyrUpPhS_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R7, SR_CTAID.Y ; S2R R8, SR_TID.Y ; S2R R0, SR_CTAID.X ; S2R R9, SR_TID.X ; IMAD R7, R7, 0x6, R8 ; ISETP.GE.AND P0, PT, R7, c[0x0][0x174], PT ; IMAD R0, R0, 0x6, R9 ; ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; @P0 EXIT ; ULDC UR5, c[0x0][0x170] ; ISETP.GE.AND P0, PT, R7.reuse, 0x2, PT ; UMOV UR6, 0x2 ; LEA.HI R2, R0.reuse, R0, RZ, 0x1 ; UMOV UR4, URZ ; LEA.HI R3, R7.reuse, R7, RZ, 0x1 ; UIMAD.WIDE.U32 UR6, UR6, UR5, UR4 ; ISETP.LT.OR P0, PT, R0, 0x2, !P0 ; IMAD R6, R7, c[0x0][0x170], R0 ; SHF.R.S32.HI R2, RZ, 0x1, R2 ; USHF.R.S32.HI UR7, URZ, 0x1, UR7 ; SHF.R.S32.HI R3, RZ, 0x1, R3 ; ULDC.64 UR8, c[0x0][0x118] ; IMAD R5, R3, UR7, R2 ; IADD3 R2, P1, R6, c[0x0][0x168], RZ ; IADD3 R4, P2, R5.reuse, c[0x0][0x160], RZ ; LEA.HI.X.SX32 R3, R6, c[0x0][0x16c], 0x1, P1 ; IMAD R6, R8, c[0x0][0x4], R9 ; LEA.HI.X.SX32 R5, R5, c[0x0][0x164], 0x1, P2 ; @P0 BRA 0x8f0 ; UIADD3 UR6, UR5, -0x3, URZ ; ISETP.GT.AND P0, PT, R0, UR6, PT ; @P0 BRA 0x8a0 ; ULDC UR6, c[0x0][0x174] ; UIADD3 UR6, UR6, -0x3, URZ ; ISETP.GT.AND P0, PT, R7, UR6, PT ; @P0 BRA 0x850 ; LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ; LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; ISETP.NE.U32.AND P0, PT, R7, 0x1, PT ; PRMT R7, RZ, 0x7610, R7 ; ISETP.EQ.U32.OR P0, PT, R0, 0x1, !P0 ; @!P0 LDG.E.U8 R7, [R4.64] ; WARPSYNC 0xffffffff ; ISETP.GE.U32.AND P0, PT, R8, 0x2, PT ; LOP3.LUT P1, RZ, R9.reuse, 0xfffffff8, R8, 0xc8, !PT ; ISETP.LT.U32.OR P0, PT, R9, 0x2, !P0 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; STS.U8 [R6], R7 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P0 EXIT ; IMAD R4, R8, 0xa, R9 ; LDS.U8 R15, [R4+-0x16] ; LDS.U8 R22, [R4+-0x15] ; LDS.U8 R17, [R4+-0x14] ; LDS.U8 R20, [R4+-0x13] ; LDS.U8 R21, [R4+-0x12] ; LDS.U8 R16, [R4+-0xc] ; LDS.U8 R18, [R4+-0xb] ; LDS.U8 R12, [R4+-0xa] ; LDS.U8 R13, [R4+-0x9] ; LDS.U8 R10, [R4+-0x8] ; LDS.U8 R9, [R4+-0x2] ; I2F.U16 R15, R15 ; LDS.U8 R8, [R4+-0x1] ; LDS.U8 R7, [R4] ; I2F.U16 R22, R22 ; LDS.U8 R6, [R4+0x1] ; LDS.U8 R5, [R4+0x2] ; I2F.U16 R17, R17 ; LDS.U8 R23, [R4+0x8] ; LDS.U8 R19, [R4+0x9] ; I2F.U16 R20, R20 ; FFMA R22, R22, 4, R15 ; LDS.U8 R14, [R4+0xa] ; LDS.U8 R11, [R4+0xb] ; I2F.U16 R21, R21 ; FFMA R25, R17, 6, R22 ; LDS.U8 R0, [R4+0xc] ; LDS.U8 R15, [R4+0x12] ; I2F.U16 R16, R16 ; FFMA R20, R20, 4, R25 ; I2F.U16 R18, R18 ; FADD R21, R20, R21 ; LDS.U8 R20, [R4+0x13] ; I2F.U16 R12, R12 ; FFMA R21, R16, 4, R21 ; LDS.U8 R16, [R4+0x14] ; I2F.U16 R13, R13 ; FFMA R21, R18, 16, R21 ; I2F.U16 R10, R10 ; FFMA R12, R12, 24, R21 ; I2F.U16 R9, R9 ; FFMA R13, R13, 16, R12 ; LDS.U8 R12, [R4+0x15] ; I2F.U16 R8, R8 ; FFMA R10, R10, 4, R13 ; I2F.U16 R7, R7 ; FFMA R13, R9, 6, R10 ; LDS.U8 R9, [R4+0x16] ; I2F.U16 R6, R6 ; FFMA R8, R8, 24, R13 ; I2F.U16 R5, R5 ; FFMA R7, R7, 36, R8 ; I2F.U16 R17, R23 ; FFMA R6, R6, 24, R7 ; I2F.U16 R19, R19 ; FFMA R6, R5, 6, R6 ; I2F.U16 R14, R14 ; FFMA R6, R17, 4, R6 ; I2F.U16 R11, R11 ; FFMA R19, R19, 16, R6 ; I2F.U16 R0, R0 ; FFMA R14, R14, 24, R19 ; I2F.U16 R15, R15 ; FFMA R11, R11, 16, R14 ; I2F.U16 R5, R20 ; FFMA R0, R0, 4, R11 ; I2F.U16 R7, R16 ; FADD R0, R0, R15 ; I2F.U16 R13, R12 ; FFMA R0, R5, 4, R0 ; I2F.U16 R9, R9 ; FFMA R0, R7, 6, R0 ; FFMA R0, R13, 4, R0 ; FADD R0, R0, R9 ; FMUL R0, R0, 0.015625 ; FMNMX.NAN R0, R0, 255, PT ; FSETP.GEU.AND P0, PT, R0, RZ, PT ; FSEL R0, R0, RZ, P0 ; F2I.U32.TRUNC.NTZ R5, R0 ; STG.E.U8 [R2.64], R5 ; EXIT ; LDG.E.U8 R7, [R4.64] ; STG.E.U8 [R2.64], R7 ; LDG.E.U8 R9, [R4.64] ; STS.U8 [R6], R9 ; EXIT ; LDG.E.U8 R9, [R4.64] ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R7, [R4.64] ; STS.U8 [R6], R7 ; EXIT ; LDG.E.U8 R9, [R4.64] ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R7, [R4.64] ; STS.U8 [R6], R7 ; EXIT ; BRA 0x940; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z7PyrDownPhS_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R7, SR_CTAID.Y ; S2R R8, SR_TID.Y ; S2R R0, SR_CTAID.X ; S2R R11, SR_TID.X ; IMAD R7, R7, 0x6, R8 ; ISETP.GE.AND P0, PT, R7, c[0x0][0x174], PT ; IMAD R0, R0, 0x6, R11 ; ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; @P0 EXIT ; ULDC UR5, c[0x0][0x170] ; ISETP.GE.AND P0, PT, R7.reuse, 0x2, PT ; UMOV UR6, 0x2 ; LEA.HI R2, R0.reuse, R0, RZ, 0x1 ; UMOV UR4, URZ ; LEA.HI R3, R7.reuse, R7, RZ, 0x1 ; UIMAD.WIDE.U32 UR6, UR6, UR5, UR4 ; ISETP.LT.OR P0, PT, R0, 0x2, !P0 ; IMAD R5, R7, c[0x0][0x170], R0 ; SHF.R.S32.HI R2, RZ, 0x1, R2 ; USHF.R.S32.HI UR7, URZ, 0x1, UR7 ; SHF.R.S32.HI R3, RZ, 0x1, R3 ; ULDC.64 UR8, c[0x0][0x118] ; IADD3 R4, P1, R5, c[0x0][0x160], RZ ; IMAD R6, R8, c[0x0][0x4], R11 ; IMAD R3, R3, UR7, R2 ; LEA.HI.X.SX32 R5, R5, c[0x0][0x164], 0x1, P1 ; IADD3 R2, P2, R3, c[0x0][0x168], RZ ; LEA.HI.X.SX32 R3, R3, c[0x0][0x16c], 0x1, P2 ; @P0 BRA 0x8e0 ; UIADD3 UR6, UR5, -0x3, URZ ; ISETP.GT.AND P0, PT, R0, UR6, PT ; @P0 BRA 0x890 ; LDG.E.U8 R9, [R4.64] ; ULDC UR6, c[0x0][0x174] ; UIADD3 UR6, UR6, -0x3, URZ ; ISETP.GT.AND P0, PT, R7, UR6, PT ; @P0 BRA 0x850 ; STS.U8 [R6], R9 ; WARPSYNC 0xffffffff ; LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ; LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.U32.AND P0, PT, R7, 0x1, PT ; ISETP.EQ.U32.OR P0, PT, R0, 0x1, !P0 ; @P0 EXIT ; ISETP.GE.U32.AND P0, PT, R8, 0x2, PT ; LOP3.LUT P1, RZ, R11.reuse, 0xfffffff8, R8, 0xc8, !PT ; ISETP.LT.U32.OR P0, PT, R11, 0x2, !P0 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 EXIT ; IMAD R4, R8, 0xa, R11 ; LDS.U8 R15, [R4+-0x16] ; LDS.U8 R22, [R4+-0x15] ; LDS.U8 R17, [R4+-0x14] ; LDS.U8 R20, [R4+-0x13] ; LDS.U8 R21, [R4+-0x12] ; LDS.U8 R16, [R4+-0xc] ; LDS.U8 R18, [R4+-0xb] ; LDS.U8 R12, [R4+-0xa] ; LDS.U8 R13, [R4+-0x9] ; LDS.U8 R10, [R4+-0x8] ; LDS.U8 R9, [R4+-0x2] ; I2F.U16 R15, R15 ; LDS.U8 R8, [R4+-0x1] ; LDS.U8 R7, [R4] ; I2F.U16 R22, R22 ; LDS.U8 R6, [R4+0x1] ; LDS.U8 R5, [R4+0x2] ; I2F.U16 R17, R17 ; LDS.U8 R23, [R4+0x8] ; LDS.U8 R19, [R4+0x9] ; I2F.U16 R20, R20 ; FFMA R22, R22, 4, R15 ; LDS.U8 R14, [R4+0xa] ; LDS.U8 R11, [R4+0xb] ; I2F.U16 R21, R21 ; FFMA R25, R17, 6, R22 ; LDS.U8 R0, [R4+0xc] ; LDS.U8 R15, [R4+0x12] ; I2F.U16 R16, R16 ; FFMA R20, R20, 4, R25 ; I2F.U16 R18, R18 ; FADD R21, R20, R21 ; LDS.U8 R20, [R4+0x13] ; I2F.U16 R12, R12 ; FFMA R21, R16, 4, R21 ; LDS.U8 R16, [R4+0x14] ; I2F.U16 R13, R13 ; FFMA R21, R18, 16, R21 ; I2F.U16 R10, R10 ; FFMA R12, R12, 24, R21 ; I2F.U16 R9, R9 ; FFMA R13, R13, 16, R12 ; LDS.U8 R12, [R4+0x15] ; I2F.U16 R8, R8 ; FFMA R10, R10, 4, R13 ; I2F.U16 R7, R7 ; FFMA R13, R9, 6, R10 ; LDS.U8 R9, [R4+0x16] ; I2F.U16 R6, R6 ; FFMA R8, R8, 24, R13 ; I2F.U16 R5, R5 ; FFMA R7, R7, 36, R8 ; I2F.U16 R17, R23 ; FFMA R6, R6, 24, R7 ; I2F.U16 R19, R19 ; FFMA R6, R5, 6, R6 ; I2F.U16 R14, R14 ; FFMA R6, R17, 4, R6 ; I2F.U16 R11, R11 ; FFMA R19, R19, 16, R6 ; I2F.U16 R0, R0 ; FFMA R14, R14, 24, R19 ; I2F.U16 R15, R15 ; FFMA R11, R11, 16, R14 ; I2F.U16 R5, R20 ; FFMA R0, R0, 4, R11 ; I2F.U16 R7, R16 ; FADD R0, R0, R15 ; I2F.U16 R13, R12 ; FFMA R0, R5, 4, R0 ; I2F.U16 R9, R9 ; FFMA R0, R7, 6, R0 ; FFMA R0, R13, 4, R0 ; FADD R0, R0, R9 ; FMUL R0, R0, 0.00390625 ; FMNMX.NAN R0, R0, 255, PT ; FSETP.GEU.AND P0, PT, R0, RZ, PT ; FSEL R0, R0, RZ, P0 ; F2I.U32.TRUNC.NTZ R5, R0 ; STG.E.U8 [R2.64], R5 ; EXIT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R5, [R4.64] ; STS.U8 [R6], R5 ; EXIT ; LDG.E.U8 R9, [R4.64] ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R7, [R4.64] ; STS.U8 [R6], R7 ; EXIT ; LDG.E.U8 R9, [R4.64] ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R7, [R4.64] ; STS.U8 [R6], R7 ; EXIT ; BRA 0x930; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000f4963_00000000-6_54e4a13d4c79104b2e640d4e8a5631e5d956170d.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2033: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2033: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z11CPU_pyrdownPhS_ii .type _Z11CPU_pyrdownPhS_ii, @function _Z11CPU_pyrdownPhS_ii: .LFB2029: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $152, %rsp .cfi_def_cfa_offset 208 movq %rdi, %r12 movq %rsi, %r14 movl %edx, %ebx movl %ecx, %ebp movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax movss .LC1(%rip), %xmm1 movss %xmm1, 32(%rsp) movss .LC2(%rip), %xmm0 movss %xmm0, 36(%rsp) movss .LC3(%rip), %xmm2 movss %xmm2, 40(%rsp) movss %xmm0, 44(%rsp) movss %xmm1, 48(%rsp) movss %xmm0, 52(%rsp) movss .LC4(%rip), %xmm3 movss %xmm3, 56(%rsp) movss .LC5(%rip), %xmm4 movss %xmm4, 60(%rsp) movss %xmm3, 64(%rsp) movss %xmm0, 68(%rsp) movss %xmm2, 72(%rsp) movss %xmm4, 76(%rsp) movl $0x42100000, 80(%rsp) movss %xmm4, 84(%rsp) movss %xmm2, 88(%rsp) movss %xmm0, 92(%rsp) movss %xmm3, 96(%rsp) movss %xmm4, 100(%rsp) movss %xmm3, 104(%rsp) movss %xmm0, 108(%rsp) movss %xmm1, 112(%rsp) movss %xmm0, 116(%rsp) movss %xmm2, 120(%rsp) movss %xmm0, 124(%rsp) movss %xmm1, 128(%rsp) movl %ecx, %edi imull %edx, %edi movslq %edi, %rdi call malloc@PLT movq %rax, %r9 testl %ebp, %ebp jle .L4 movl $0, %ecx movl $0, %esi movslq %ebx, %rdi addq %rax, %rdi jmp .L5 .L6: movb $0, (%rax) addq $1, %rax cmpq %rdx, %rax jne .L6 .L9: leal 1(%rsi), %eax addl %ebx, %ecx cmpl %eax, %ebp je .L7 movl %eax, %esi .L5: movslq %ecx, %rdx leaq (%r9,%rdx), %rax addq %rdi, %rdx testl %ebx, %ebx jg .L6 jmp .L9 .L7: cmpl $3, %esi jle .L10 leal (%rbx,%rbx), %eax subl $1, %esi movslq %ebx, %r8 leaq (%r8,%r8), %rdx movq %r12, %r11 subq %rdx, %r11 movl $2, %ecx leal -2(%rbx), %r13d movss .LC7(%rip), %xmm2 movl $-1, %r12d pxor %xmm3, %xmm3 movl $0, %r15d movl %esi, 20(%rsp) movq %r14, 24(%rsp) movl %ebp, %r10d movq %r13, %rdi jmp .L11 .L32: cvttss2sil %xmm1, %eax .L14: movb %al, (%r9,%rsi) addq $1, %rsi cmpq %r13, %rsi je .L28 .L17: leaq (%rsi,%r11), %rbp leaq -8(%rsp), %rcx movl $0, %r14d pxor %xmm1, %xmm1 .L16: movq $-2, %rax .L12: movzbl 0(%rbp,%rax), %edx pxor %xmm0, %xmm0 cvtsi2ssl %edx, %xmm0 mulss 48(%rcx,%rax,4), %xmm0 addss %xmm0, %xmm1 addq $1, %rax cmpq $3, %rax jne .L12 addq %r8, %rbp addl $5, %r14d addq $20, %rcx cmpl $25, %r14d jne .L16 mulss %xmm2, %xmm1 movl %r12d, %eax comiss .LC8(%rip), %xmm1 ja .L14 movl %r15d, %eax comiss %xmm1, %xmm3 jbe .L32 jmp .L14 .L28: movl 12(%rsp), %ecx movl 16(%rsp), %eax .L15: addl $1, %ecx addl %ebx, %eax movl 20(%rsp), %esi cmpl %esi, %ecx je .L29 .L11: cmpl $4, %ebx jle .L15 movslq %eax, %r13 leaq 2(%r13), %rsi addq %rdi, %r13 movl %ecx, 12(%rsp) movl %eax, 16(%rsp) jmp .L17 .L29: movq 24(%rsp), %r14 movl %r10d, %ebp .L10: movl %ebp, %r11d shrl $31, %r11d addl %ebp, %r11d sarl %r11d cmpl $1, %ebp jle .L4 movl %ebx, %ecx shrl $31, %ecx addl %ebx, %ecx sarl %ecx movl $0, %ebp movl $0, %r10d movl $0, %r8d jmp .L18 .L20: movslq %r10d, %rax leaq (%r9,%rax,2), %rdi movl $0, %eax movslq %ebp, %rsi addq %r14, %rsi .L19: movzbl (%rdi,%rax,2), %edx movb %dl, (%rsi,%rax) addq $1, %rax cmpl %eax, %ecx jg .L19 .L21: addl $1, %r8d addl %ebx, %r10d addl %ecx, %ebp cmpl %r11d, %r8d jge .L4 .L18: cmpl $1, %ebx jg .L20 jmp .L21 .L4: movq %r9, %rdi call free@PLT movq 136(%rsp), %rax subq %fs:40, %rax jne .L33 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L33: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2029: .size _Z11CPU_pyrdownPhS_ii, .-_Z11CPU_pyrdownPhS_ii .globl _Z9CPU_pyrupPhS_ii .type _Z9CPU_pyrupPhS_ii, @function _Z9CPU_pyrupPhS_ii: .LFB2030: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $152, %rsp .cfi_def_cfa_offset 208 movq %rdi, 8(%rsp) movq %rsi, %rbx movl %edx, %ebp movl %ecx, %r12d movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax movss .LC1(%rip), %xmm1 movss %xmm1, 32(%rsp) movss .LC2(%rip), %xmm0 movss %xmm0, 36(%rsp) movss .LC3(%rip), %xmm2 movss %xmm2, 40(%rsp) movss %xmm0, 44(%rsp) movss %xmm1, 48(%rsp) movss %xmm0, 52(%rsp) movss .LC4(%rip), %xmm3 movss %xmm3, 56(%rsp) movss .LC5(%rip), %xmm4 movss %xmm4, 60(%rsp) movss %xmm3, 64(%rsp) movss %xmm0, 68(%rsp) movss %xmm2, 72(%rsp) movss %xmm4, 76(%rsp) movl $0x42100000, 80(%rsp) movss %xmm4, 84(%rsp) movss %xmm2, 88(%rsp) movss %xmm0, 92(%rsp) movss %xmm3, 96(%rsp) movss %xmm4, 100(%rsp) movss %xmm3, 104(%rsp) movss %xmm0, 108(%rsp) movss %xmm1, 112(%rsp) movss %xmm0, 116(%rsp) movss %xmm2, 120(%rsp) movss %xmm0, 124(%rsp) movss %xmm1, 128(%rsp) movl %ecx, %edi imull %edx, %edi sall $2, %edi movslq %edi, %rdi call malloc@PLT movq %rax, %rdi leal (%r12,%r12), %esi testl %esi, %esi jle .L35 leal (%rbp,%rbp), %ecx movl %ebp, %r9d leal 0(,%rbp,4), %r13d leal -2(%rcx), %r14d shrl %r14d movl %r14d, %r14d movl $0, %r11d movl $0, %r10d movl $0, %r8d leaq 2(%rax), %r15 jmp .L36 .L39: movslq %r10d, %rax addq %rdi, %rax movslq %r11d, %rdx addq %r14, %rdx leaq (%r15,%rdx,2), %rdx .L37: movb $0, 1(%rax) addq $2, %rax cmpq %rdx, %rax jne .L37 .L40: addl $2, %r8d addl %r13d, %r10d addl %ecx, %r11d cmpl %esi, %r8d jge .L38 .L36: cmpl $1, %ecx jg .L39 jmp .L40 .L38: cmpl $1, %esi jle .L41 leal 1(%rsi), %r11d leal -1(%rcx), %eax movl %ecx, %r10d movl $1, %r8d leaq 1(%rdi,%rax), %r14 jmp .L42 .L44: movslq %r10d, %rax addq %rdi, %rax movslq %r9d, %rdx leaq (%r14,%rdx,2), %rdx .L43: movb $0, (%rax) addq $1, %rax cmpq %rdx, %rax jne .L43 .L45: addl $2, %r8d addl %r13d, %r10d addl %ecx, %r9d cmpl %r11d, %r8d je .L41 .L42: testl %ebp, %ebp jg .L44 jmp .L45 .L48: leal (%r10,%r10), %eax cltq leaq (%rdi,%rax,2), %r8 movl $0, %eax movslq %r10d, %rcx addq %r13, %rcx .L46: movzbl (%rcx,%rax), %edx movb %dl, (%r8,%rax,2) addq $1, %rax leal (%rax,%rax), %edx cmpl %edx, %r9d jg .L46 .L49: addl $2, %r11d addl %ebp, %r10d cmpl %esi, %r11d jge .L47 .L57: testl %ebp, %ebp jg .L48 jmp .L49 .L47: leal -2(%rbp,%rbp), %r13d cmpl $4, %esi jle .L35 leal (%rbp,%rbp), %eax leal -2(%r12,%r12), %esi leal -5(%rax), %r8d movslq %ebp, %rdx leaq (%rdx,%rdx), %r9 salq $2, %rdx movq %rdi, %r12 subq %rdx, %r12 movl $2, %ecx leaq 3(%r8), %r14 movss .LC9(%rip), %xmm2 movl $-1, %r11d pxor %xmm3, %xmm3 movl $0, %r15d movq %rdi, 24(%rsp) movl %r13d, 16(%rsp) movl %esi, 20(%rsp) jmp .L50 .L70: cvttss2sil %xmm1, %eax .L53: movb %al, (%rbx,%rsi) addq $1, %rsi cmpq %r13, %rsi je .L67 .L56: leaq (%rsi,%r12), %r8 leaq -8(%rsp), %rdi movl $0, %r10d pxor %xmm1, %xmm1 .L55: movq $-2, %rax .L51: movzbl (%r8,%rax), %edx pxor %xmm0, %xmm0 cvtsi2ssl %edx, %xmm0 mulss 48(%rdi,%rax,4), %xmm0 addss %xmm0, %xmm1 addq $1, %rax cmpq $3, %rax jne .L51 addq %r9, %r8 addl $5, %r10d addq $20, %rdi cmpl $25, %r10d jne .L55 mulss %xmm2, %xmm1 movl %r11d, %eax comiss .LC8(%rip), %xmm1 ja .L53 movl %r15d, %eax comiss %xmm1, %xmm3 jbe .L70 jmp .L53 .L67: movl %ecx, %eax movl 8(%rsp), %ecx .L54: addl $1, %ecx addl %ebp, %eax movl 20(%rsp), %esi cmpl %esi, %ecx je .L68 .L50: cmpl $2, 16(%rsp) jle .L54 leal (%rax,%rax), %esi movslq %esi, %rsi addq $2, %rsi movslq %eax, %r10 leaq (%r14,%r10,2), %r13 movl %ecx, 8(%rsp) movl %eax, %ecx jmp .L56 .L68: movq 24(%rsp), %rdi .L35: call free@PLT movq 136(%rsp), %rax subq %fs:40, %rax jne .L71 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L41: .cfi_restore_state leal (%rbp,%rbp), %r9d movl $0, %r10d movl $0, %r11d movq 8(%rsp), %r13 jmp .L57 .L71: call __stack_chk_fail@PLT .cfi_endproc .LFE2030: .size _Z9CPU_pyrupPhS_ii, .-_Z9CPU_pyrupPhS_ii .globl _Z30__device_stub__Z7PyrDownPhS_iiPhS_ii .type _Z30__device_stub__Z7PyrDownPhS_iiPhS_ii, @function _Z30__device_stub__Z7PyrDownPhS_iiPhS_ii: .LFB2055: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L76 .L72: movq 136(%rsp), %rax subq %fs:40, %rax jne .L77 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L76: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7PyrDownPhS_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L72 .L77: call __stack_chk_fail@PLT .cfi_endproc .LFE2055: .size _Z30__device_stub__Z7PyrDownPhS_iiPhS_ii, .-_Z30__device_stub__Z7PyrDownPhS_iiPhS_ii .globl _Z7PyrDownPhS_ii .type _Z7PyrDownPhS_ii, @function _Z7PyrDownPhS_ii: .LFB2056: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z7PyrDownPhS_iiPhS_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2056: .size _Z7PyrDownPhS_ii, .-_Z7PyrDownPhS_ii .globl _Z7PyrDownPhS_ii4dim3S0_ .type _Z7PyrDownPhS_ii4dim3S0_, @function _Z7PyrDownPhS_ii4dim3S0_: .LFB2027: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $24, %rsp .cfi_def_cfa_offset 64 movq %rdi, %rbx movq %rsi, %rbp movl %edx, %r12d movl %ecx, %r13d movq %r8, %rdi movl %r9d, %esi movl 72(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 64(%rsp), %rdx call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L83 .L80: addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L83: .cfi_restore_state movl %r13d, %ecx movl %r12d, %edx movq %rbp, %rsi movq %rbx, %rdi call _Z30__device_stub__Z7PyrDownPhS_iiPhS_ii jmp .L80 .cfi_endproc .LFE2027: .size _Z7PyrDownPhS_ii4dim3S0_, .-_Z7PyrDownPhS_ii4dim3S0_ .globl _Z28__device_stub__Z5PyrUpPhS_iiPhS_ii .type _Z28__device_stub__Z5PyrUpPhS_iiPhS_ii, @function _Z28__device_stub__Z5PyrUpPhS_iiPhS_ii: .LFB2057: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L88 .L84: movq 136(%rsp), %rax subq %fs:40, %rax jne .L89 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L88: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z5PyrUpPhS_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L84 .L89: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z28__device_stub__Z5PyrUpPhS_iiPhS_ii, .-_Z28__device_stub__Z5PyrUpPhS_iiPhS_ii .globl _Z5PyrUpPhS_ii .type _Z5PyrUpPhS_ii, @function _Z5PyrUpPhS_ii: .LFB2058: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z28__device_stub__Z5PyrUpPhS_iiPhS_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z5PyrUpPhS_ii, .-_Z5PyrUpPhS_ii .globl _Z5PyrUpPhS_ii4dim3S0_ .type _Z5PyrUpPhS_ii4dim3S0_, @function _Z5PyrUpPhS_ii4dim3S0_: .LFB2028: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $24, %rsp .cfi_def_cfa_offset 64 movq %rdi, %rbx movq %rsi, %rbp movl %edx, %r12d movl %ecx, %r13d movq %r8, %rdi movl %r9d, %esi movl 72(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 64(%rsp), %rdx call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L95 .L92: addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L95: .cfi_restore_state movl %r13d, %ecx movl %r12d, %edx movq %rbp, %rsi movq %rbx, %rdi call _Z28__device_stub__Z5PyrUpPhS_iiPhS_ii jmp .L92 .cfi_endproc .LFE2028: .size _Z5PyrUpPhS_ii4dim3S0_, .-_Z5PyrUpPhS_ii4dim3S0_ .section .rodata.str1.1,"aMS",@progbits,1 .LC10: .string "_Z5PyrUpPhS_ii" .LC11: .string "_Z7PyrDownPhS_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2060: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC10(%rip), %rdx movq %rdx, %rcx leaq _Z5PyrUpPhS_ii(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC11(%rip), %rdx movq %rdx, %rcx leaq _Z7PyrDownPhS_ii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 1065353216 .align 4 .LC2: .long 1082130432 .align 4 .LC3: .long 1086324736 .align 4 .LC4: .long 1098907648 .align 4 .LC5: .long 1103101952 .align 4 .LC7: .long 998244352 .align 4 .LC8: .long 1132396544 .align 4 .LC9: .long 1015021568 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z7PyrDownPhS_ii ; -- Begin function _Z7PyrDownPhS_ii .globl _Z7PyrDownPhS_ii .p2align 8 .type _Z7PyrDownPhS_ii,@function _Z7PyrDownPhS_ii: ; @_Z7PyrDownPhS_ii ; %bb.0: s_load_b64 s[8:9], s[0:1], 0x10 v_dual_mov_b32 v15, 0x41c00000 :: v_dual_mov_b32 v12, 1.0 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 v_dual_mov_b32 v14, 0x41800000 :: v_dual_mov_b32 v13, 4.0 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mov_b32_e32 v21, v15 s_mov_b32 s5, 4.0 v_mad_u64_u32 v[6:7], null, s14, 6, v[2:3] v_mad_u64_u32 v[4:5], null, s15, 6, v[3:4] s_mov_b32 s7, s5 s_mov_b32 s6, 0x40c00000 s_mov_b32 s4, 1.0 v_dual_mov_b32 v18, 0x40c00000 :: v_dual_mov_b32 v17, v13 v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v19, v15 s_waitcnt lgkmcnt(0) v_cmp_gt_i32_e32 vcc_lo, s8, v6 v_cmp_gt_i32_e64 s2, s9, v4 v_dual_mov_b32 v11, s7 :: v_dual_mov_b32 v10, s6 v_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4 v_dual_mov_b32 v20, v14 :: v_dual_mov_b32 v23, v13 v_mov_b32_e32 v22, v14 scratch_store_b128 off, v[16:19], off offset:48 v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, 0x42100000 v_mov_b32_e32 v19, v13 s_and_b32 s2, vcc_lo, s2 s_clause 0x5 scratch_store_b128 off, v[8:11], off offset:16 scratch_store_b128 off, v[12:15], off offset:32 scratch_store_b128 off, v[20:23], off offset:80 scratch_store_b128 off, v[16:19], off offset:64 scratch_store_b128 off, v[8:11], off offset:96 scratch_store_b32 off, v12, off offset:112 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_19 ; %bb.1: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b128 s[4:7], s[0:1], 0x0 v_lshrrev_b32_e32 v0, 31, v4 v_lshrrev_b32_e32 v1, 31, v6 v_mad_u64_u32 v[7:8], null, v4, s8, v[6:7] s_lshr_b32 s0, s8, 31 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_nc_u32_e32 v0, v4, v0 v_add_nc_u32_e32 v1, v6, v1 s_add_i32 s0, s8, s0 v_min_i32_e32 v9, v6, v4 s_ashr_i32 s0, s0, 1 v_ashrrev_i32_e32 v8, 1, v0 v_ashrrev_i32_e32 v5, 1, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[0:1], null, s0, v8, v[5:6] s_waitcnt lgkmcnt(0) s_lshr_b32 s0, s2, 16 v_mad_u32_u24 v1, v3, s0, v2 s_mov_b32 s0, exec_lo v_cmpx_lt_i32_e32 1, v9 s_xor_b32 s2, exec_lo, s0 s_cbranch_execz .LBB0_17 ; %bb.2: s_add_i32 s0, s8, -3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_ge_i32_e32 vcc_lo, s0, v6 s_and_saveexec_b32 s0, vcc_lo s_xor_b32 s3, exec_lo, s0 s_cbranch_execz .LBB0_14 ; %bb.3: v_ashrrev_i32_e32 v6, 31, v7 v_add_co_u32 v5, vcc_lo, s4, v7 s_add_i32 s0, s9, -3 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo v_cmp_ge_i32_e32 vcc_lo, s0, v4 global_load_u8 v7, v[5:6], off s_and_saveexec_b32 s0, vcc_lo s_xor_b32 s8, exec_lo, s0 s_cbranch_execz .LBB0_11 ; %bb.4: v_or_b32_e32 v4, v2, v3 v_min_u32_e32 v6, v2, v3 s_waitcnt vmcnt(0) ds_store_b8 v1, v7 s_waitcnt lgkmcnt(0) s_waitcnt_vscnt null, 0x0 s_barrier v_and_b32_e32 v5, 1, v4 v_cmp_lt_u32_e64 s0, 1, v6 v_cmp_gt_u32_e64 s1, 8, v4 buffer_gl0_inv v_cmp_eq_u32_e32 vcc_lo, 0, v5 s_and_b32 s0, s0, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s0, s1, s0 s_and_saveexec_b32 s9, s0 s_cbranch_execz .LBB0_10 ; %bb.5: ; %.preheader.preheader v_mul_u32_u24_e32 v3, 10, v3 v_mov_b32_e32 v1, 16 s_mov_b32 s0, -2 s_delay_alu instid0(VALU_DEP_2) v_add3_u32 v2, v2, v3, 0xffffffea v_mov_b32_e32 v3, 0 .p2align 6 .LBB0_6: ; %.preheader ; =>This Loop Header: Depth=1 ; Child Loop BB0_7 Depth 2 s_delay_alu instid0(VALU_DEP_3) v_mov_b32_e32 v4, v1 s_mov_b32 s1, 0 .LBB0_7: ; Parent Loop BB0_6 Depth=1 ; => This Inner Loop Header: Depth=2 scratch_load_b32 v5, v4, off v_add_nc_u32_e32 v6, s1, v2 s_add_i32 s1, s1, 1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) s_cmp_eq_u32 s1, 5 ds_load_u8 v6, v6 s_waitcnt lgkmcnt(0) v_cvt_f32_ubyte0_e32 v6, v6 s_waitcnt vmcnt(0) v_dual_fmac_f32 v3, v5, v6 :: v_dual_add_nc_u32 v4, 4, v4 s_cbranch_scc0 .LBB0_7 ; %bb.8: ; in Loop: Header=BB0_6 Depth=1 v_add_nc_u32_e32 v1, 20, v1 v_add_nc_u32_e32 v2, 10, v2 s_add_i32 s0, s0, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s0, 3 s_cbranch_scc0 .LBB0_6 ; %bb.9: v_mul_f32_e32 v1, 0x3b800000, v3 v_ashrrev_i32_e32 v3, 31, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_cmp_lt_f32_e32 vcc_lo, 0x437f0000, v1 v_cmp_ngt_f32_e64 s0, 0, v1 v_cmp_gt_f32_e64 s1, 0, v1 v_cvt_i32_f32_e32 v1, v1 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) s_or_b32 vcc_lo, s1, vcc_lo v_cndmask_b32_e64 v2, 0, -1, s0 v_cndmask_b32_e32 v2, v1, v2, vcc_lo v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo global_store_b8 v[0:1], v2, off .LBB0_10: ; %Flow s_or_b32 exec_lo, exec_lo, s9 ; implicit-def: $vgpr0_vgpr1 ; implicit-def: $vgpr7 ; implicit-def: $vgpr5_vgpr6 ; implicit-def: $vgpr1 .LBB0_11: ; %Flow265 s_and_not1_saveexec_b32 s0, s8 s_cbranch_execz .LBB0_13 ; %bb.12: v_ashrrev_i32_e32 v3, 31, v0 v_add_co_u32 v2, vcc_lo, s6, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo s_waitcnt vmcnt(0) global_store_b8 v[2:3], v7, off global_load_u8 v0, v[5:6], off s_waitcnt vmcnt(0) ds_store_b8 v1, v0 .LBB0_13: ; %Flow266 s_or_b32 exec_lo, exec_lo, s0 ; implicit-def: $vgpr0_vgpr1 ; implicit-def: $vgpr7_vgpr8 ; implicit-def: $vgpr1 .LBB0_14: ; %Flow267 s_and_not1_saveexec_b32 s0, s3 s_cbranch_execz .LBB0_16 ; %bb.15: s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v3, 31, v7 v_add_co_u32 v2, vcc_lo, s4, v7 v_ashrrev_i32_e32 v5, 31, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo global_load_u8 v6, v[2:3], off s_waitcnt vmcnt(0) global_store_b8 v[4:5], v6, off global_load_u8 v0, v[2:3], off s_waitcnt vmcnt(0) ds_store_b8 v1, v0 .LBB0_16: ; %Flow268 s_or_b32 exec_lo, exec_lo, s0 ; implicit-def: $vgpr0_vgpr1 ; implicit-def: $vgpr7_vgpr8 ; implicit-def: $vgpr1 .LBB0_17: ; %Flow269 s_and_not1_saveexec_b32 s0, s2 s_cbranch_execz .LBB0_19 ; %bb.18: s_waitcnt vmcnt(0) v_ashrrev_i32_e32 v3, 31, v7 v_add_co_u32 v2, vcc_lo, s4, v7 v_ashrrev_i32_e32 v5, 31, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo global_load_u8 v6, v[2:3], off s_waitcnt vmcnt(0) global_store_b8 v[4:5], v6, off global_load_u8 v0, v[2:3], off s_waitcnt vmcnt(0) ds_store_b8 v1, v0 .LBB0_19: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z7PyrDownPhS_ii .amdhsa_group_segment_fixed_size 100 .amdhsa_private_segment_fixed_size 128 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 1 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 24 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z7PyrDownPhS_ii, .Lfunc_end0-_Z7PyrDownPhS_ii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 980 ; NumSgprs: 18 ; NumVgprs: 24 ; ScratchSize: 128 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 100 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 24 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .protected _Z5PyrUpPhS_ii ; -- Begin function _Z5PyrUpPhS_ii .globl _Z5PyrUpPhS_ii .p2align 8 .type _Z5PyrUpPhS_ii,@function _Z5PyrUpPhS_ii: ; @_Z5PyrUpPhS_ii ; %bb.0: s_load_b64 s[8:9], s[0:1], 0x10 v_dual_mov_b32 v17, 0x41c00000 :: v_dual_mov_b32 v14, 1.0 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 v_dual_mov_b32 v16, 0x41800000 :: v_dual_mov_b32 v15, 4.0 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mov_b32_e32 v23, v17 s_mov_b32 s5, 4.0 v_mad_u64_u32 v[8:9], null, s14, 6, v[2:3] v_mad_u64_u32 v[6:7], null, s15, 6, v[3:4] s_mov_b32 s7, s5 s_mov_b32 s6, 0x40c00000 s_mov_b32 s4, 1.0 v_dual_mov_b32 v20, 0x40c00000 :: v_dual_mov_b32 v19, v15 v_dual_mov_b32 v18, v16 :: v_dual_mov_b32 v21, v17 s_waitcnt lgkmcnt(0) v_cmp_gt_i32_e32 vcc_lo, s8, v8 v_cmp_gt_i32_e64 s2, s9, v6 v_dual_mov_b32 v13, s7 :: v_dual_mov_b32 v12, s6 v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v10, s4 v_dual_mov_b32 v22, v16 :: v_dual_mov_b32 v25, v15 v_mov_b32_e32 v24, v16 scratch_store_b128 off, v[18:21], off offset:48 v_dual_mov_b32 v19, v17 :: v_dual_mov_b32 v18, 0x42100000 v_mov_b32_e32 v21, v15 s_and_b32 s2, vcc_lo, s2 s_clause 0x5 scratch_store_b128 off, v[10:13], off offset:16 scratch_store_b128 off, v[14:17], off offset:32 scratch_store_b128 off, v[22:25], off offset:80 scratch_store_b128 off, v[18:21], off offset:64 scratch_store_b128 off, v[10:13], off offset:96 scratch_store_b32 off, v14, off offset:112 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB1_21 ; %bb.1: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b128 s[4:7], s[0:1], 0x0 v_lshrrev_b32_e32 v0, 31, v6 v_lshrrev_b32_e32 v1, 31, v8 s_lshr_b32 s0, s8, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) s_add_i32 s0, s8, s0 v_add_nc_u32_e32 v4, v6, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_nc_u32_e32 v5, v8, v1 v_mad_u64_u32 v[0:1], null, v6, s8, v[8:9] s_ashr_i32 s0, s0, 1 v_ashrrev_i32_e32 v7, 1, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v1, 1, v5 v_min_i32_e32 v9, v8, v6 v_mad_u64_u32 v[4:5], null, s0, v7, v[1:2] s_waitcnt lgkmcnt(0) s_lshr_b32 s0, s2, 16 s_delay_alu instid0(SALU_CYCLE_1) v_mad_u32_u24 v1, v3, s0, v2 s_mov_b32 s0, exec_lo v_cmpx_lt_i32_e32 1, v9 s_xor_b32 s2, exec_lo, s0 s_cbranch_execz .LBB1_19 ; %bb.2: s_add_i32 s0, s8, -3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_ge_i32_e32 vcc_lo, s0, v8 s_and_saveexec_b32 s0, vcc_lo s_xor_b32 s3, exec_lo, s0 s_cbranch_execz .LBB1_16 ; %bb.3: s_add_i32 s0, s9, -3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_ge_i32_e32 vcc_lo, s0, v6 s_and_saveexec_b32 s0, vcc_lo s_xor_b32 s8, exec_lo, s0 s_cbranch_execz .LBB1_13 ; %bb.4: v_or_b32_e32 v5, v2, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v5, 1, v5 v_cmp_eq_u32_e32 vcc_lo, 0, v5 v_mov_b32_e32 v5, 0 s_and_saveexec_b32 s0, vcc_lo s_cbranch_execz .LBB1_6 ; %bb.5: v_ashrrev_i32_e32 v5, 31, v4 v_add_co_u32 v4, vcc_lo, s4, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo global_load_u8 v5, v[4:5], off .LBB1_6: s_or_b32 exec_lo, exec_lo, s0 v_add_nc_u32_e32 v4, -8, v2 v_add_nc_u32_e32 v6, -8, v3 s_mov_b32 s9, exec_lo s_waitcnt vmcnt(0) ds_store_b8 v1, v5 s_waitcnt lgkmcnt(0) s_waitcnt_vscnt null, 0x0 s_barrier v_min_u32_e32 v4, v4, v6 buffer_gl0_inv v_cmpx_lt_u32_e32 -7, v4 s_cbranch_execz .LBB1_12 ; %bb.7: ; %.preheader.preheader v_mul_u32_u24_e32 v3, 10, v3 v_mov_b32_e32 v1, 16 s_mov_b32 s0, -2 s_delay_alu instid0(VALU_DEP_2) v_add3_u32 v2, v2, v3, 0xffffffea v_mov_b32_e32 v3, 0 .p2align 6 .LBB1_8: ; %.preheader ; =>This Loop Header: Depth=1 ; Child Loop BB1_9 Depth 2 s_delay_alu instid0(VALU_DEP_3) v_mov_b32_e32 v4, v1 s_mov_b32 s1, 0 .LBB1_9: ; Parent Loop BB1_8 Depth=1 ; => This Inner Loop Header: Depth=2 scratch_load_b32 v5, v4, off v_add_nc_u32_e32 v6, s1, v2 s_add_i32 s1, s1, 1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) s_cmp_eq_u32 s1, 5 ds_load_u8 v6, v6 s_waitcnt lgkmcnt(0) v_cvt_f32_ubyte0_e32 v6, v6 s_waitcnt vmcnt(0) v_dual_fmac_f32 v3, v5, v6 :: v_dual_add_nc_u32 v4, 4, v4 s_cbranch_scc0 .LBB1_9 ; %bb.10: ; in Loop: Header=BB1_8 Depth=1 v_add_nc_u32_e32 v1, 20, v1 v_add_nc_u32_e32 v2, 10, v2 s_add_i32 s0, s0, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s0, 3 s_cbranch_scc0 .LBB1_8 ; %bb.11: v_mul_f32_e32 v1, 0x3c800000, v3 v_ashrrev_i32_e32 v3, 31, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_cmp_lt_f32_e32 vcc_lo, 0x437f0000, v1 v_cmp_ngt_f32_e64 s0, 0, v1 v_cmp_gt_f32_e64 s1, 0, v1 v_cvt_i32_f32_e32 v1, v1 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) s_or_b32 vcc_lo, s1, vcc_lo v_cndmask_b32_e64 v2, 0, -1, s0 v_cndmask_b32_e32 v2, v1, v2, vcc_lo v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo global_store_b8 v[0:1], v2, off .LBB1_12: ; %Flow s_or_b32 exec_lo, exec_lo, s9 ; implicit-def: $vgpr0_vgpr1 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $vgpr1 .LBB1_13: ; %Flow282 s_and_not1_saveexec_b32 s0, s8 s_cbranch_execz .LBB1_15 ; %bb.14: v_ashrrev_i32_e32 v3, 31, v4 v_add_co_u32 v2, vcc_lo, s4, v4 v_ashrrev_i32_e32 v5, 31, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo global_load_u8 v6, v[2:3], off s_waitcnt vmcnt(0) global_store_b8 v[4:5], v6, off global_load_u8 v0, v[2:3], off s_waitcnt vmcnt(0) ds_store_b8 v1, v0 .LBB1_15: ; %Flow283 s_or_b32 exec_lo, exec_lo, s0 ; implicit-def: $vgpr0_vgpr1 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $vgpr1 .LBB1_16: ; %Flow284 s_and_not1_saveexec_b32 s0, s3 s_cbranch_execz .LBB1_18 ; %bb.17: v_ashrrev_i32_e32 v3, 31, v4 v_add_co_u32 v2, vcc_lo, s4, v4 v_ashrrev_i32_e32 v5, 31, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo global_load_u8 v6, v[2:3], off s_waitcnt vmcnt(0) global_store_b8 v[4:5], v6, off global_load_u8 v0, v[2:3], off s_waitcnt vmcnt(0) ds_store_b8 v1, v0 .LBB1_18: ; %Flow285 s_or_b32 exec_lo, exec_lo, s0 ; implicit-def: $vgpr0_vgpr1 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $vgpr1 .LBB1_19: ; %Flow286 s_and_not1_saveexec_b32 s0, s2 s_cbranch_execz .LBB1_21 ; %bb.20: v_ashrrev_i32_e32 v3, 31, v4 v_add_co_u32 v2, vcc_lo, s4, v4 v_ashrrev_i32_e32 v5, 31, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo global_load_u8 v6, v[2:3], off s_waitcnt vmcnt(0) global_store_b8 v[4:5], v6, off global_load_u8 v0, v[2:3], off s_waitcnt vmcnt(0) ds_store_b8 v1, v0 .LBB1_21: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5PyrUpPhS_ii .amdhsa_group_segment_fixed_size 100 .amdhsa_private_segment_fixed_size 128 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 1 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 26 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z5PyrUpPhS_ii, .Lfunc_end1-_Z5PyrUpPhS_ii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1012 ; NumSgprs: 18 ; NumVgprs: 26 ; ScratchSize: 128 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 100 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 3 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 26 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 100 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z7PyrDownPhS_ii .private_segment_fixed_size: 128 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z7PyrDownPhS_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 24 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 100 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5PyrUpPhS_ii .private_segment_fixed_size: 128 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z5PyrUpPhS_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 26 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "54e4a13d4c79104b2e640d4e8a5631e5d956170d.hip" .globl _Z22__device_stub__PyrDownPhS_ii # -- Begin function _Z22__device_stub__PyrDownPhS_ii .p2align 4, 0x90 .type _Z22__device_stub__PyrDownPhS_ii,@function _Z22__device_stub__PyrDownPhS_ii: # @_Z22__device_stub__PyrDownPhS_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7PyrDownPhS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z22__device_stub__PyrDownPhS_ii, .Lfunc_end0-_Z22__device_stub__PyrDownPhS_ii .cfi_endproc # -- End function .globl _Z7PyrDownPhS_ii4dim3S0_ # -- Begin function _Z7PyrDownPhS_ii4dim3S0_ .p2align 4, 0x90 .type _Z7PyrDownPhS_ii4dim3S0_,@function _Z7PyrDownPhS_ii4dim3S0_: # @_Z7PyrDownPhS_ii4dim3S0_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $120, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %ecx, %ebx movl %edx, %ebp movq %rsi, %r14 movq %rdi, %r15 movq 160(%rsp), %rdx movl 168(%rsp), %ecx movq %r8, %rdi movl %r9d, %esi xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq %r15, 72(%rsp) movq %r14, 64(%rsp) movl %ebp, 12(%rsp) movl %ebx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7PyrDownPhS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: addq $120, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z7PyrDownPhS_ii4dim3S0_, .Lfunc_end1-_Z7PyrDownPhS_ii4dim3S0_ .cfi_endproc # -- End function .globl _Z20__device_stub__PyrUpPhS_ii # -- Begin function _Z20__device_stub__PyrUpPhS_ii .p2align 4, 0x90 .type _Z20__device_stub__PyrUpPhS_ii,@function _Z20__device_stub__PyrUpPhS_ii: # @_Z20__device_stub__PyrUpPhS_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z5PyrUpPhS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end2: .size _Z20__device_stub__PyrUpPhS_ii, .Lfunc_end2-_Z20__device_stub__PyrUpPhS_ii .cfi_endproc # -- End function .globl _Z5PyrUpPhS_ii4dim3S0_ # -- Begin function _Z5PyrUpPhS_ii4dim3S0_ .p2align 4, 0x90 .type _Z5PyrUpPhS_ii4dim3S0_,@function _Z5PyrUpPhS_ii4dim3S0_: # @_Z5PyrUpPhS_ii4dim3S0_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $120, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %ecx, %ebx movl %edx, %ebp movq %rsi, %r14 movq %rdi, %r15 movq 160(%rsp), %rdx movl 168(%rsp), %ecx movq %r8, %rdi movl %r9d, %esi xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_2 # %bb.1: movq %r15, 72(%rsp) movq %r14, 64(%rsp) movl %ebp, 12(%rsp) movl %ebx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z5PyrUpPhS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_2: addq $120, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size _Z5PyrUpPhS_ii4dim3S0_, .Lfunc_end3-_Z5PyrUpPhS_ii4dim3S0_ .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function _Z11CPU_pyrdownPhS_ii .LCPI4_0: .long 0x3b800000 # float 0.00390625 .LCPI4_1: .long 0x437f0000 # float 255 .text .globl _Z11CPU_pyrdownPhS_ii .p2align 4, 0x90 .type _Z11CPU_pyrdownPhS_ii,@function _Z11CPU_pyrdownPhS_ii: # @_Z11CPU_pyrdownPhS_ii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %ecx, %ebx movl %edx, %r14d movq %rsi, %r15 movq %rdi, %r13 movl %ecx, %eax imull %edx, %eax movslq %eax, %rdi callq malloc movq %r14, %r8 movq %rax, %r12 movl %r8d, %ebp movq %rbx, (%rsp) # 8-byte Spill testl %ebx, %ebx movq %r14, 8(%rsp) # 8-byte Spill jle .LBB4_5 # %bb.1: # %.preheader76.lr.ph movl (%rsp), %ebx # 4-byte Reload xorl %r14d, %r14d jmp .LBB4_2 .p2align 4, 0x90 .LBB4_4: # %._crit_edge # in Loop: Header=BB4_2 Depth=1 addl %r8d, %r14d decq %rbx je .LBB4_5 .LBB4_2: # %.preheader76 # =>This Inner Loop Header: Depth=1 testl %r8d, %r8d jle .LBB4_4 # %bb.3: # %.lr.ph # in Loop: Header=BB4_2 Depth=1 movl %r14d, %edi addq %r12, %rdi xorl %esi, %esi movq %rbp, %rdx callq memset@PLT movq 8(%rsp), %r8 # 8-byte Reload jmp .LBB4_4 .LBB4_5: # %._crit_edge79 cmpl $5, (%rsp) # 4-byte Folded Reload jl .LBB4_15 # %bb.6: # %.preheader75.lr.ph leal -2(%r8), %ecx movq (%rsp), %rax # 8-byte Reload addl $-2, %eax movq %rax, 16(%rsp) # 8-byte Spill movl %ecx, %ecx movl $2, %edx xorl %ebx, %ebx movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movss .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero jmp .LBB4_7 .p2align 4, 0x90 .LBB4_14: # %._crit_edge85 # in Loop: Header=BB4_7 Depth=1 incq %rdx addq %rbp, %rbx cmpq 16(%rsp), %rdx # 8-byte Folded Reload movq 8(%rsp), %r8 # 8-byte Reload je .LBB4_15 .LBB4_7: # %.preheader75 # =>This Loop Header: Depth=1 # Child Loop BB4_9 Depth 2 # Child Loop BB4_10 Depth 3 # Child Loop BB4_11 Depth 4 cmpl $5, %r8d jl .LBB4_14 # %bb.8: # %.preheader74.lr.ph # in Loop: Header=BB4_7 Depth=1 movl %edx, %edi imull 8(%rsp), %edi # 4-byte Folded Reload addq %r12, %rdi movl $2, %r8d movq %rbx, %rsi .p2align 4, 0x90 .LBB4_9: # %.preheader74 # Parent Loop BB4_7 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB4_10 Depth 3 # Child Loop BB4_11 Depth 4 xorps %xmm2, %xmm2 movq $-2, %r10 movl $.L__const._Z9CPU_pyrupPhS_ii.laplacianMatrix, %r11d movq %rsi, %r9 .p2align 4, 0x90 .LBB4_10: # %.preheader73 # Parent Loop BB4_7 Depth=1 # Parent Loop BB4_9 Depth=2 # => This Loop Header: Depth=3 # Child Loop BB4_11 Depth 4 xorl %r14d, %r14d .p2align 4, 0x90 .LBB4_11: # Parent Loop BB4_7 Depth=1 # Parent Loop BB4_9 Depth=2 # Parent Loop BB4_10 Depth=3 # => This Inner Loop Header: Depth=4 leal (%r9,%r14), %eax cltq movzbl (%r13,%rax), %eax xorps %xmm3, %xmm3 cvtsi2ss %eax, %xmm3 mulss (%r11,%r14,4), %xmm3 addss %xmm3, %xmm2 incq %r14 cmpq $5, %r14 jne .LBB4_11 # %bb.12: # in Loop: Header=BB4_10 Depth=3 incq %r10 addq $20, %r11 addq %rbp, %r9 cmpq $3, %r10 jne .LBB4_10 # %bb.13: # in Loop: Header=BB4_9 Depth=2 mulss %xmm0, %xmm2 movaps %xmm1, %xmm3 minss %xmm2, %xmm3 xorps %xmm2, %xmm2 maxss %xmm3, %xmm2 cvttss2si %xmm2, %eax movb %al, (%rdi,%r8) incq %r8 incq %rsi cmpq %rcx, %r8 jne .LBB4_9 jmp .LBB4_14 .LBB4_15: # %.preheader72 movq (%rsp), %r11 # 8-byte Reload cmpl $2, %r11d jl .LBB4_21 # %bb.16: # %.preheader.lr.ph shrl %r11d movl %r8d, %eax shrl $31, %eax addl %r8d, %eax sarl %eax movslq %eax, %rcx leal (%r8,%r8), %edx xorl %esi, %esi xorl %edi, %edi jmp .LBB4_17 .p2align 4, 0x90 .LBB4_20: # %._crit_edge89 # in Loop: Header=BB4_17 Depth=1 incq %rdi addq %rcx, %r15 addl %edx, %esi cmpq %r11, %rdi movq 8(%rsp), %r8 # 8-byte Reload je .LBB4_21 .LBB4_17: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB4_19 Depth 2 cmpl $2, %r8d jl .LBB4_20 # %bb.18: # %.lr.ph88 # in Loop: Header=BB4_17 Depth=1 movl %esi, %r8d xorl %r9d, %r9d .p2align 4, 0x90 .LBB4_19: # Parent Loop BB4_17 Depth=1 # => This Inner Loop Header: Depth=2 movslq %r8d, %r8 movzbl (%r12,%r8), %r10d movb %r10b, (%r15,%r9) incq %r9 addl $2, %r8d cmpq %r9, %rax jne .LBB4_19 jmp .LBB4_20 .LBB4_21: # %._crit_edge91 movq %r12, %rdi addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 jmp free # TAILCALL .Lfunc_end4: .size _Z11CPU_pyrdownPhS_ii, .Lfunc_end4-_Z11CPU_pyrdownPhS_ii .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function _Z9CPU_pyrupPhS_ii .LCPI5_0: .long 0x3c800000 # float 0.015625 .LCPI5_1: .long 0x437f0000 # float 255 .text .globl _Z9CPU_pyrupPhS_ii .p2align 4, 0x90 .type _Z9CPU_pyrupPhS_ii,@function _Z9CPU_pyrupPhS_ii: # @_Z9CPU_pyrupPhS_ii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $40, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %ecx, %r12d movl %edx, %ebx movq %rsi, 24(%rsp) # 8-byte Spill movq %rdi, %r13 leal (%rbx,%rbx), %r14d leal (%r12,%r12), %eax movq %rax, (%rsp) # 8-byte Spill # kill: def $eax killed $eax killed $rax imull %r14d, %eax movslq %eax, %rdi callq malloc movq %rax, %r15 testl %r12d, %r12d jle .LBB5_6 # %bb.1: # %.preheader95.lr.ph movslq %r14d, %rax movslq (%rsp), %rcx # 4-byte Folded Reload leal (,%rbx,4), %edx xorl %esi, %esi xorl %edi, %edi jmp .LBB5_2 .p2align 4, 0x90 .LBB5_5: # %._crit_edge # in Loop: Header=BB5_2 Depth=1 addq $2, %rdi addl %edx, %esi cmpq %rcx, %rdi jge .LBB5_6 .LBB5_2: # %.preheader95 # =>This Loop Header: Depth=1 # Child Loop BB5_4 Depth 2 testl %ebx, %ebx jle .LBB5_5 # %bb.3: # %.lr.ph # in Loop: Header=BB5_2 Depth=1 movslq %esi, %r8 addq %r15, %r8 movl $1, %r9d .p2align 4, 0x90 .LBB5_4: # Parent Loop BB5_2 Depth=1 # => This Inner Loop Header: Depth=2 movb $0, (%r8,%r9) addq $2, %r9 cmpq %rax, %r9 jl .LBB5_4 jmp .LBB5_5 .LBB5_6: # %.preheader94 movq %r13, 8(%rsp) # 8-byte Spill movq %r12, 16(%rsp) # 8-byte Spill testl %r12d, %r12d jle .LBB5_11 # %bb.7: # %.preheader93.lr.ph leal (,%rbx,4), %r13d cmpl $2, %r14d movl $1, %eax cmovgel %r14d, %eax movq %rax, 32(%rsp) # 8-byte Spill movq (%rsp), %rax # 8-byte Reload cmpl $4, %eax movl $3, %r12d cmovgel %eax, %r12d addl $-2, %r12d shrl %r12d notq %r12 movl %r14d, %ebp jmp .LBB5_8 .p2align 4, 0x90 .LBB5_10: # %._crit_edge100 # in Loop: Header=BB5_8 Depth=1 addl %r13d, %ebp incq %r12 je .LBB5_11 .LBB5_8: # %.preheader93 # =>This Inner Loop Header: Depth=1 testl %ebx, %ebx jle .LBB5_10 # %bb.9: # %.lr.ph99 # in Loop: Header=BB5_8 Depth=1 movslq %ebp, %rdi addq %r15, %rdi xorl %esi, %esi movq 32(%rsp), %rdx # 8-byte Reload callq memset@PLT jmp .LBB5_10 .LBB5_11: # %.preheader92 movq 16(%rsp), %r12 # 8-byte Reload testl %r12d, %r12d movq 8(%rsp), %r13 # 8-byte Reload jle .LBB5_17 # %bb.12: # %.preheader91.lr.ph cmpl $3, %r14d movl $2, %eax movl $2, %ecx cmovgel %r14d, %ecx decl %ecx shrl %ecx incl %ecx movq (%rsp), %rdx # 8-byte Reload cmpl $3, %edx cmovgel %edx, %eax decl %eax shrl %eax incl %eax leal (,%rbx,4), %edx xorl %esi, %esi xorl %edi, %edi xorl %r8d, %r8d jmp .LBB5_13 .p2align 4, 0x90 .LBB5_16: # %._crit_edge105 # in Loop: Header=BB5_13 Depth=1 incq %r8 addl %edx, %edi addl %ebx, %esi cmpq %rax, %r8 je .LBB5_17 .LBB5_13: # %.preheader91 # =>This Loop Header: Depth=1 # Child Loop BB5_15 Depth 2 testl %ebx, %ebx jle .LBB5_16 # %bb.14: # %.lr.ph104 # in Loop: Header=BB5_13 Depth=1 movslq %edi, %r9 addq %r15, %r9 movl %esi, %r10d addq %r13, %r10 xorl %r11d, %r11d .p2align 4, 0x90 .LBB5_15: # Parent Loop BB5_13 Depth=1 # => This Inner Loop Header: Depth=2 movzbl (%r10,%r11), %ebp movb %bpl, (%r9,%r11,2) incq %r11 cmpq %r11, %rcx jne .LBB5_15 jmp .LBB5_16 .LBB5_17: # %._crit_edge108 cmpl $3, %r12d jl .LBB5_27 # %bb.18: # %.preheader90.lr.ph movq (%rsp), %rdx # 8-byte Reload addl $-2, %edx leal -2(%r14), %eax cmpl $4, %eax movl $3, %ecx cmovll %ecx, %eax cmpl $4, %edx cmovll %ecx, %edx movq %rdx, (%rsp) # 8-byte Spill movl $2, %ecx xorl %edx, %edx movss .LCPI5_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movss .LCPI5_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero jmp .LBB5_19 .p2align 4, 0x90 .LBB5_26: # %._crit_edge114 # in Loop: Header=BB5_19 Depth=1 incq %rcx addq %r14, %rdx cmpq (%rsp), %rcx # 8-byte Folded Reload je .LBB5_27 .LBB5_19: # %.preheader90 # =>This Loop Header: Depth=1 # Child Loop BB5_21 Depth 2 # Child Loop BB5_22 Depth 3 # Child Loop BB5_23 Depth 4 cmpl $3, %ebx jl .LBB5_26 # %bb.20: # %.preheader89.lr.ph # in Loop: Header=BB5_19 Depth=1 movl %r14d, %esi imull %ecx, %esi movslq %esi, %rsi addq 24(%rsp), %rsi # 8-byte Folded Reload movl $2, %edi movq %rdx, %r8 .p2align 4, 0x90 .LBB5_21: # %.preheader89 # Parent Loop BB5_19 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB5_22 Depth 3 # Child Loop BB5_23 Depth 4 xorps %xmm2, %xmm2 movq $-2, %r9 movl $.L__const._Z9CPU_pyrupPhS_ii.laplacianMatrix, %r10d movq %r8, %r11 .p2align 4, 0x90 .LBB5_22: # %.preheader # Parent Loop BB5_19 Depth=1 # Parent Loop BB5_21 Depth=2 # => This Loop Header: Depth=3 # Child Loop BB5_23 Depth 4 xorl %r12d, %r12d .p2align 4, 0x90 .LBB5_23: # Parent Loop BB5_19 Depth=1 # Parent Loop BB5_21 Depth=2 # Parent Loop BB5_22 Depth=3 # => This Inner Loop Header: Depth=4 leal (%r11,%r12), %ebp movslq %ebp, %r13 movzbl (%r15,%r13), %ebp xorps %xmm3, %xmm3 cvtsi2ss %ebp, %xmm3 mulss (%r10,%r12,4), %xmm3 addss %xmm3, %xmm2 incq %r12 cmpq $5, %r12 jne .LBB5_23 # %bb.24: # in Loop: Header=BB5_22 Depth=3 incq %r9 addq $20, %r10 addq %r14, %r11 cmpq $3, %r9 jne .LBB5_22 # %bb.25: # in Loop: Header=BB5_21 Depth=2 mulss %xmm0, %xmm2 movaps %xmm1, %xmm3 minss %xmm2, %xmm3 xorps %xmm2, %xmm2 maxss %xmm3, %xmm2 cvttss2si %xmm2, %r9d movb %r9b, (%rsi,%rdi) incq %rdi incq %r8 cmpq %rax, %rdi jne .LBB5_21 jmp .LBB5_26 .LBB5_27: # %._crit_edge116 movq %r15, %rdi addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 jmp free # TAILCALL .Lfunc_end5: .size _Z9CPU_pyrupPhS_ii, .Lfunc_end5-_Z9CPU_pyrupPhS_ii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB6_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB6_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7PyrDownPhS_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5PyrUpPhS_ii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end6: .size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB7_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB7_2: retq .Lfunc_end7: .size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor .cfi_endproc # -- End function .type _Z7PyrDownPhS_ii,@object # @_Z7PyrDownPhS_ii .section .rodata,"a",@progbits .globl _Z7PyrDownPhS_ii .p2align 3, 0x0 _Z7PyrDownPhS_ii: .quad _Z22__device_stub__PyrDownPhS_ii .size _Z7PyrDownPhS_ii, 8 .type _Z5PyrUpPhS_ii,@object # @_Z5PyrUpPhS_ii .globl _Z5PyrUpPhS_ii .p2align 3, 0x0 _Z5PyrUpPhS_ii: .quad _Z20__device_stub__PyrUpPhS_ii .size _Z5PyrUpPhS_ii, 8 .type .L__const._Z9CPU_pyrupPhS_ii.laplacianMatrix,@object # @__const._Z9CPU_pyrupPhS_ii.laplacianMatrix .p2align 4, 0x0 .L__const._Z9CPU_pyrupPhS_ii.laplacianMatrix: .long 0x3f800000 # float 1 .long 0x40800000 # float 4 .long 0x40c00000 # float 6 .long 0x40800000 # float 4 .long 0x3f800000 # float 1 .long 0x40800000 # float 4 .long 0x41800000 # float 16 .long 0x41c00000 # float 24 .long 0x41800000 # float 16 .long 0x40800000 # float 4 .long 0x40c00000 # float 6 .long 0x41c00000 # float 24 .long 0x42100000 # float 36 .long 0x41c00000 # float 24 .long 0x40c00000 # float 6 .long 0x40800000 # float 4 .long 0x41800000 # float 16 .long 0x41c00000 # float 24 .long 0x41800000 # float 16 .long 0x40800000 # float 4 .long 0x3f800000 # float 1 .long 0x40800000 # float 4 .long 0x40c00000 # float 6 .long 0x40800000 # float 4 .long 0x3f800000 # float 1 .size .L__const._Z9CPU_pyrupPhS_ii.laplacianMatrix, 100 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z7PyrDownPhS_ii" .size .L__unnamed_1, 17 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z5PyrUpPhS_ii" .size .L__unnamed_2, 15 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__PyrDownPhS_ii .addrsig_sym _Z20__device_stub__PyrUpPhS_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7PyrDownPhS_ii .addrsig_sym _Z5PyrUpPhS_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
6,432
9,651
11,224
11,514
110
code for sm_80 Function : _Z20Convolution3x3KernelP6uchar4S0_iii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R2, SR_CTAID.Y ; ULDC.64 UR10, c[0x0][0x0] ; BSSY B0, 0x3f0 ; USHF.L.U32 UR5, UR11, 0x8, URZ ; S2R R4, SR_TID.X ; USHF.L.U32 UR4, UR10, 0x8, URZ ; USHF.R.S32.HI UR5, URZ, 0x8, UR5 ; S2R R0, SR_CTAID.X ; USHF.R.S32.HI UR4, URZ, 0x8, UR4 ; ULDC.64 UR8, c[0x0][0x118] ; S2R R3, SR_TID.Y ; SHF.L.U32 R2, R2, 0x8, RZ ; ISETP.GT.U32.AND P1, PT, R4, 0x9, PT ; SHF.R.S32.HI R2, RZ, 0x8, R2 ; SHF.L.U32 R0, R0, 0x8, RZ ; SHF.R.S32.HI R5, RZ, 0x8, R0 ; IMAD R0, R2, UR5, R3 ; IMAD R2, R5, UR4, R4 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; ISETP.GE.OR P0, PT, R2, c[0x0][0x170], P0 ; @P1 BRA 0x3e0 ; ISETP.GT.U32.AND P1, PT, R3, 0x1, PT ; USHF.L.U32 UR4, UR10, 0x7, URZ ; PLOP3.LUT P3, PT, PT, PT, PT, 0x8, 0x0 ; ULDC UR5, c[0x0][0x170] ; HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; USHF.R.S32.HI UR4, URZ, 0x8, UR4 ; ULDC UR6, c[0x0][0x178] ; IMAD R5, R5, UR4, R4 ; USHF.R.S32.HI UR4, URZ, 0x2, UR5 ; @!P1 IADD3 R7, R0, 0xf, RZ ; USHF.L.U32 UR5, UR6, 0x7, URZ ; @!P1 MOV R6, c[0x0][0x174] ; @!P1 ISETP.GE.AND P2, PT, R7, c[0x0][0x174], PT ; USHF.R.S32.HI UR5, URZ, 0x8, UR5 ; IADD3 R5, R5, -0x1, RZ ; @!P1 PLOP3.LUT P3, PT, P2, PT, PT, 0x80, 0x0 ; ISETP.GE.AND P2, PT, R5.reuse, RZ, PT ; IMNMX R5, R5, UR4, PT ; @!P1 ISETP.GE.AND P4, PT, R0, -0xf, PT ; SEL R5, R5, RZ, P2 ; @P3 IADD3 R7, R6, -0x1, RZ ; IMNMX R6, R0.reuse, c[0x0][0x174], PT ; ISETP.GE.AND P3, PT, R0, 0x1, PT ; @!P1 IMAD.SHL.U32 R7, R7, 0x100, RZ ; LEA R6, R6, 0xffffff00, 0x8 ; SHF.R.S32.HI R6, RZ, 0x8, R6 ; @!P1 SHF.R.S32.HI R7, RZ, 0x8, R7 ; SEL R6, R6, RZ, P3 ; @!P1 SEL R8, R7, RZ, P4 ; IMAD R6, R6, UR5, R5.reuse ; @!P1 IMAD R8, R8, UR5, R5 ; IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; @!P1 IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; LDG.E.64 R6, [R6.64] ; @!P1 LDG.E.64 R8, [R8.64] ; SHF.L.U32 R5, R3, 0x8, RZ ; SHF.R.S32.HI R5, RZ, 0x8, R5 ; IMAD R5, R5, 0xa, R4 ; STS.64 [R5.X8], R6 ; @!P1 STS.64 [R5.X8+0x500], R8 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P0 EXIT ; IMAD.SHL.U32 R3, R3, 0x100, RZ ; ULDC UR4, c[0x0][0x178] ; SHF.L.U32 R0, R0, 0x8, RZ ; USHF.L.U32 UR4, UR4, 0x8, URZ ; SHF.R.S32.HI R3, RZ, 0x8, R3 ; USHF.R.S32.HI UR4, URZ, 0x8, UR4 ; IMAD R20, R3, 0x14, R4 ; LDS.U8 R7, [R20.X4+0x8] ; LDS.U8 R16, [R20.X4+0x7] ; LDS.U8 R8, [R20.X4+0x9] ; LDS.U8 R17, [R20.X4+0xa] ; LDS.U8 R12, [R20.X4+0xb] ; LDS.U8 R15, [R20.X4+0x57] ; LDS.U8 R11, [R20.X4+0x58] ; LDS.U8 R13, [R20.X4+0x59] ; LDS.U8 R18, [R20.X4+0xc] ; LDS.U8 R6, [R20.X4+0x5a] ; LDS.U8 R5, [R20.X4+0xa7] ; I2F.U16 R7, R7 ; LDS.U8 R3, [R20.X4+0xa8] ; LDS.U8 R10, [R20.X4+0xa9] ; I2F.U16 R16, R16 ; LDS.U8 R4, [R20.X4+0x5b] ; LDS.U8 R21, [R20.X4+0x5c] ; I2F.U16 R8, R8 ; FMUL R23, R7, c[0x3][0x4] ; LDS.U8 R19, [R20.X4+0xaa] ; LDS.U8 R14, [R20.X4+0xab] ; I2F.U16 R17, R17 ; FFMA R23, R16, c[0x3][0x0], R23 ; LDS.U8 R9, [R20.X4+0xac] ; I2F.U16 R12, R12 ; FMUL R24, R8, c[0x3][0x4] ; FFMA R22, R8, c[0x3][0x8], R23 ; FFMA R24, R7, c[0x3][0x0], R24 ; I2F.U16 R15, R15 ; FMUL R23, R17.reuse, c[0x3][0x4] ; FFMA R24, R17, c[0x3][0x8], R24 ; FFMA R23, R8, c[0x3][0x0], R23 ; I2F.U16 R11, R11 ; FMUL R26, R12.reuse, c[0x3][0x4] ; FFMA R12, R12, c[0x3][0x8], R23 ; FFMA R17, R17, c[0x3][0x0], R26 ; I2F.U16 R13, R13 ; FFMA R22, R15, c[0x3][0xc], R22 ; I2F.U16 R18, R18 ; FFMA R24, R11.reuse, c[0x3][0xc], R24 ; FFMA R22, R11, c[0x3][0x10], R22 ; I2F.U16 R6, R6 ; FFMA R11, R13.reuse, c[0x3][0xc], R12 ; FFMA R7, R13.reuse, c[0x3][0x10], R24 ; FFMA R22, R13, c[0x3][0x14], R22 ; I2F.U16 R5, R5 ; FFMA R17, R18, c[0x3][0x8], R17 ; I2F.U16 R3, R3 ; FFMA R17, R6.reuse, c[0x3][0xc], R17 ; FFMA R11, R6.reuse, c[0x3][0x10], R11 ; FFMA R6, R6, c[0x3][0x14], R7 ; I2F.U16 R10, R10 ; FFMA R22, R5, c[0x3][0x18], R22 ; I2F.U16 R4, R4 ; FFMA R5, R3.reuse, c[0x3][0x18], R6 ; FFMA R3, R3, c[0x3][0x1c], R22 ; I2F.U16 R16, R21 ; FFMA R3, R10, c[0x3][0x20], R3 ; FSETP.GEU.AND P0, PT, R3.reuse, RZ, PT ; I2F.U16 R19, R19 ; FFMA R17, R4.reuse, c[0x3][0x10], R17 ; FMNMX.NAN R3, R3, 255, PT ; FFMA R11, R4, c[0x3][0x14], R11 ; FFMA R4, R10.reuse, c[0x3][0x1c], R5 ; FSEL R3, R3, RZ, P0 ; FFMA R6, R10, c[0x3][0x18], R11 ; I2F.U16 R14, R14 ; FFMA R16, R16, c[0x3][0x14], R17 ; I2F.U16 R8, R9 ; FFMA R4, R19.reuse, c[0x3][0x20], R4 ; FFMA R7, R19.reuse, c[0x3][0x18], R16 ; FFMA R5, R19, c[0x3][0x1c], R6 ; FSETP.GEU.AND P0, PT, R4.reuse, RZ, PT ; FMNMX.NAN R4, R4, 255, PT ; FFMA R7, R14.reuse, c[0x3][0x1c], R7 ; F2I.U32.TRUNC.NTZ R3, R3 ; FFMA R5, R14, c[0x3][0x20], R5 ; FSEL R4, R4, RZ, P0 ; SHF.R.S32.HI R9, RZ, 0x8, R0 ; FFMA R7, R8, c[0x3][0x20], R7 ; FSETP.GEU.AND P0, PT, R5.reuse, RZ, PT ; F2I.U32.TRUNC.NTZ R4, R4 ; FMNMX.NAN R5, R5, 255, PT ; IMAD R2, R9, UR4, R2 ; FSETP.GEU.AND P1, PT, R7, RZ, PT ; FSEL R5, R5, RZ, P0 ; FMNMX.NAN R7, R7, 255, PT ; FSEL R7, R7, RZ, P1 ; F2I.U32.TRUNC.NTZ R5, R5 ; PRMT R4, R4, 0x7604, R3 ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; F2I.U32.TRUNC.NTZ R7, R7 ; IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; PRMT R4, R5, 0x7054, R4 ; PRMT R5, R7, 0x654, R4 ; STG.E [R2.64], R5 ; EXIT ; BRA 0xa90; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000114cc_00000000-6_d9f338f6266cee4dc2a77df7179d4659de29bcbe.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2030: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2030: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii .type _Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii, @function _Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii: .LFB2052: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z20Convolution3x3KernelP6uchar4S0_iii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2052: .size _Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii, .-_Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii .globl _Z20Convolution3x3KernelP6uchar4S0_iii .type _Z20Convolution3x3KernelP6uchar4S0_iii, @function _Z20Convolution3x3KernelP6uchar4S0_iii: .LFB2053: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2053: .size _Z20Convolution3x3KernelP6uchar4S0_iii, .-_Z20Convolution3x3KernelP6uchar4S0_iii .globl Convolution3x3 .type Convolution3x3, @function Convolution3x3: .LFB2027: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $32, %rsp .cfi_def_cfa_offset 80 movq %rdi, %r13 movq %rsi, %r14 movl %edx, %ebx movl %ecx, %ebp movq %r8, %r12 movl $1, %r8d movl $0, %ecx movl $36, %edx leaq FilterCoeff_CPU(%rip), %rsi leaq _ZL11FilterCoeff(%rip), %rdi call cudaMemcpyToSymbol@PLT testl %eax, %eax jne .L11 movl %ebp, %edx shrl $4, %edx movl %edx, %eax addl $1, %eax testb $15, %bpl cmove %edx, %eax movl %ebx, %ecx shrl $6, %ecx movl %ecx, %edx addl $1, %edx testb $63, %bl cmove %ecx, %edx movl %edx, 20(%rsp) movl %eax, 24(%rsp) movl $16, 8(%rsp) movl $16, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 8(%rsp), %rdx movl $1, %ecx movq 20(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L19 .L17: call cudaThreadSynchronize@PLT .L11: addq $32, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state leal 3(%r12), %r8d testl %r12d, %r12d cmovns %r12d, %r8d sarl $2, %r8d movl %ebp, %ecx movl %ebx, %edx movq %r14, %rsi movq %r13, %rdi call _Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii jmp .L17 .cfi_endproc .LFE2027: .size Convolution3x3, .-Convolution3x3 .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z20Convolution3x3KernelP6uchar4S0_iii" .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "FilterCoeff" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2055: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z20Convolution3x3KernelP6uchar4S0_iii(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $36, %r9d movl $0, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _ZL11FilterCoeff(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2055: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .globl FilterCoeff_CPU .data .align 32 .type FilterCoeff_CPU, @object .size FilterCoeff_CPU, 36 FilterCoeff_CPU: .long -1082130432 .long -1073741824 .long -1082130432 .long -1073741824 .long 1094713344 .long -1073741824 .long -1082130432 .long -1073741824 .long -1082130432 .local _ZL11FilterCoeff .comm _ZL11FilterCoeff,36,32 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii ; -- Begin function _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii .globl _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii .p2align 8 .type _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii,@function _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii: ; @_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii ; %bb.0: s_clause 0x2 s_load_b32 s4, s[0:1], 0x2c s_load_b64 s[2:3], s[0:1], 0x10 s_load_b32 s6, s[0:1], 0x18 v_bfe_u32 v3, v0, 10, 10 v_and_b32_e32 v4, 0x3ff, v0 s_bfe_i32 s7, s15, 0x180000 s_bfe_i32 s8, s14, 0x180000 s_mov_b32 s9, exec_lo s_waitcnt lgkmcnt(0) s_lshr_b32 s5, s4, 16 s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[0:1], null, s7, s5, v[3:4] s_and_b32 s7, s4, 0xffff v_cmpx_gt_u32_e32 10, v4 s_cbranch_execz .LBB0_3 ; %bb.1: s_lshr_b32 s4, s7, 1 s_delay_alu instid0(VALU_DEP_2) v_add_nc_u32_e32 v1, -1, v0 s_mul_i32 s4, s4, s8 s_add_i32 s10, s3, -1 v_add3_u32 v2, v4, s4, -1 s_ashr_i32 s4, s2, 2 v_min_i32_e32 v1, s10, v1 s_bfe_i32 s11, s6, 0x180001 v_lshlrev_b32_e32 v7, 3, v4 v_min_i32_e32 v5, s4, v2 v_cmp_lt_i32_e32 vcc_lo, -1, v2 v_and_b32_e32 v6, 0xffffff, v1 s_load_b64 s[4:5], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v1, 0, v5, vcc_lo v_cmp_lt_i32_e32 vcc_lo, 0, v0 v_cndmask_b32_e32 v2, 0, v6, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_i32_i24 v5, v2, s11, v1 v_mul_u32_u24_e32 v2, 10, v3 v_ashrrev_i32_e32 v6, 31, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshl_add_u32 v2, v2, 3, v7 v_lshlrev_b64 v[5:6], 3, v[5:6] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s4, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo v_cmp_gt_u32_e32 vcc_lo, 2, v3 global_load_b64 v[5:6], v[5:6], off s_waitcnt vmcnt(0) ds_store_b64 v2, v[5:6] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_3 ; %bb.2: v_add_nc_u32_e32 v5, 15, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s3, v5 v_cndmask_b32_e32 v5, s10, v5, vcc_lo v_cmp_lt_i32_e32 vcc_lo, -16, v0 v_cndmask_b32_e32 v5, 0, v5, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_i32_i24 v5, v5, s11, v1 v_ashrrev_i32_e32 v6, 31, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[5:6], 3, v[5:6] v_add_co_u32 v5, vcc_lo, s4, v5 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo global_load_b64 v[5:6], v[5:6], off s_waitcnt vmcnt(0) ds_store_b64 v2, v[5:6] offset:1280 .LBB0_3: s_or_b32 exec_lo, exec_lo, s9 v_mad_u64_u32 v[1:2], null, s8, s7, v[4:5] s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmp_gt_i32_e32 vcc_lo, s2, v1 v_cmp_gt_i32_e64 s2, s3, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_5 ; %bb.4: v_lshlrev_b32_e32 v2, 2, v4 s_getpc_b64 s[2:3] s_add_u32 s2, s2, FilterCoeff@rel32@lo+4 s_addc_u32 s3, s3, FilterCoeff@rel32@hi+12 s_getpc_b64 s[4:5] s_add_u32 s4, s4, FilterCoeff@rel32@lo+8 s_addc_u32 s5, s5, FilterCoeff@rel32@hi+16 s_getpc_b64 s[8:9] s_add_u32 s8, s8, FilterCoeff@rel32@lo+12 s_addc_u32 s9, s9, FilterCoeff@rel32@hi+20 s_getpc_b64 s[10:11] s_add_u32 s10, s10, FilterCoeff@rel32@lo+16 s_addc_u32 s11, s11, FilterCoeff@rel32@hi+24 v_mad_u32_u24 v2, v3, 0x50, v2 s_getpc_b64 s[12:13] s_add_u32 s12, s12, FilterCoeff@rel32@lo+20 s_addc_u32 s13, s13, FilterCoeff@rel32@hi+28 s_getpc_b64 s[14:15] s_add_u32 s14, s14, FilterCoeff@rel32@lo+24 s_addc_u32 s15, s15, FilterCoeff@rel32@hi+32 s_getpc_b64 s[16:17] s_add_u32 s16, s16, FilterCoeff@rel32@lo+28 s_addc_u32 s17, s17, FilterCoeff@rel32@hi+36 s_getpc_b64 s[18:19] s_add_u32 s18, s18, FilterCoeff@rel32@lo+32 s_addc_u32 s19, s19, FilterCoeff@rel32@hi+40 ds_load_u8 v3, v2 offset:7 ds_load_u8 v4, v2 offset:8 s_clause 0x2 s_load_b32 s2, s[2:3], 0x0 s_load_b32 s3, s[4:5], 0x0 s_load_b32 s4, s[8:9], 0x0 ds_load_u8 v5, v2 offset:9 ds_load_u8 v6, v2 offset:10 ds_load_u8 v7, v2 offset:11 ds_load_u8 v8, v2 offset:12 ds_load_u8 v9, v2 offset:87 ds_load_u8 v10, v2 offset:88 ds_load_u8 v11, v2 offset:89 ds_load_u8 v12, v2 offset:167 ds_load_u8 v13, v2 offset:168 ds_load_u8 v14, v2 offset:169 s_getpc_b64 s[20:21] s_add_u32 s20, s20, FilterCoeff@rel32@lo+36 s_addc_u32 s21, s21, FilterCoeff@rel32@hi+44 s_clause 0x5 s_load_b32 s5, s[10:11], 0x0 s_load_b32 s7, s[12:13], 0x0 s_load_b32 s8, s[14:15], 0x0 s_load_b32 s9, s[16:17], 0x0 s_load_b32 s10, s[18:19], 0x0 s_load_b32 s11, s[20:21], 0x0 ds_load_u8 v16, v2 offset:90 ds_load_u8 v17, v2 offset:170 ds_load_u8 v18, v2 offset:91 s_load_b64 s[0:1], s[0:1], 0x8 v_mad_i32_i24 v0, v0, s6, v1 s_delay_alu instid0(VALU_DEP_1) v_ashrrev_i32_e32 v1, 31, v0 s_waitcnt lgkmcnt(0) v_cvt_f32_ubyte0_e32 v5, v5 v_cvt_f32_ubyte0_e32 v6, v6 v_cvt_f32_ubyte0_e32 v7, v7 v_cvt_f32_ubyte0_e32 v9, v9 v_cvt_f32_ubyte0_e32 v10, v10 v_cvt_f32_ubyte0_e32 v3, v3 v_cvt_f32_ubyte0_e32 v4, v4 v_cvt_f32_ubyte0_e32 v11, v11 v_cvt_f32_ubyte0_e32 v12, v12 v_cvt_f32_ubyte0_e32 v13, v13 v_cvt_f32_ubyte0_e32 v16, v16 v_mul_f32_e32 v15, s3, v4 v_cvt_f32_ubyte0_e32 v8, v8 v_lshlrev_b64 v[0:1], 2, v[0:1] v_mul_f32_e32 v20, s3, v7 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_fmac_f32_e32 v15, s2, v3 ds_load_u8 v3, v2 offset:92 ds_load_u8 v19, v2 offset:171 ds_load_u8 v2, v2 offset:172 v_fmac_f32_e32 v15, s4, v5 v_fmac_f32_e32 v15, s5, v9 v_cvt_f32_ubyte0_e32 v9, v14 v_mul_f32_e32 v14, s3, v5 s_delay_alu instid0(VALU_DEP_1) v_fmac_f32_e32 v14, s2, v4 v_mul_f32_e32 v4, s3, v6 v_fmac_f32_e32 v15, s7, v10 s_waitcnt lgkmcnt(2) v_cvt_f32_ubyte0_e32 v3, v3 s_waitcnt lgkmcnt(0) v_cvt_f32_ubyte0_e32 v2, v2 v_dual_fmac_f32 v14, s4, v6 :: v_dual_fmac_f32 v15, s8, v11 v_fmac_f32_e32 v4, s2, v5 v_cvt_f32_ubyte0_e32 v5, v17 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_fmac_f32 v15, s9, v12 :: v_dual_fmac_f32 v20, s2, v6 v_fmac_f32_e32 v4, s4, v7 v_cvt_f32_ubyte0_e32 v6, v18 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_fmac_f32 v15, s10, v13 :: v_dual_fmac_f32 v14, s5, v10 v_dual_fmac_f32 v4, s5, v11 :: v_dual_fmac_f32 v15, s11, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmac_f32_e32 v14, s7, v11 v_fmac_f32_e32 v4, s7, v16 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v15 v_fmac_f32_e32 v14, s8, v16 s_delay_alu instid0(VALU_DEP_3) v_fmac_f32_e32 v4, s8, v6 v_cndmask_b32_e32 v7, 0x437f0000, v15, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0, v15 v_fmac_f32_e32 v20, s4, v8 v_fmac_f32_e32 v14, s9, v13 v_fmac_f32_e32 v4, s9, v9 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fmac_f32_e32 v20, s5, v16 v_fmac_f32_e32 v14, s10, v9 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fmac_f32_e32 v4, s10, v5 v_fmac_f32_e32 v20, s7, v6 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fmac_f32_e32 v14, s11, v5 v_cvt_f32_ubyte0_e32 v6, v19 v_fmac_f32_e32 v20, s8, v3 v_cndmask_b32_e32 v3, 0, v7, vcc_lo s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v14 v_fmac_f32_e32 v4, s11, v6 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fmac_f32_e32 v20, s9, v5 v_cvt_i32_f32_e32 v3, v3 v_cndmask_b32_e32 v5, 0x437f0000, v14, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0, v14 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v20, s10, v6 v_fmac_f32_e32 v20, s11, v2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v2, 0, v5, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v4 v_cvt_i32_f32_e32 v2, v2 v_cndmask_b32_e32 v5, 0x437f0000, v4, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v20 v_cndmask_b32_e32 v6, 0x437f0000, v20, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0, v4 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v4, 0, v5, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0, v20 v_cvt_i32_f32_e32 v4, v4 v_cndmask_b32_e32 v5, 0, v6, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_cvt_i32_f32_e32 v5, v5 s_clause 0x3 global_store_b8 v[0:1], v3, off global_store_b8 v[0:1], v2, off offset:1 global_store_b8 v[0:1], v4, off offset:2 global_store_b8 v[0:1], v5, off offset:3 .LBB0_5: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii .amdhsa_group_segment_fixed_size 1440 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 21 .amdhsa_next_free_sgpr 22 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii, .Lfunc_end0-_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1340 ; NumSgprs: 24 ; NumVgprs: 21 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 1440 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 24 ; NumVGPRsForWavesPerEU: 21 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .protected FilterCoeff ; @FilterCoeff .type FilterCoeff,@object .section .bss,"aw",@nobits .globl FilterCoeff .p2align 4, 0x0 FilterCoeff: .zero 36 .size FilterCoeff, 36 .type __hip_cuid_,@object ; @__hip_cuid_ .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym FilterCoeff .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 1440 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii .private_segment_fixed_size: 0 .sgpr_count: 24 .sgpr_spill_count: 0 .symbol: _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 21 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "d9f338f6266cee4dc2a77df7179d4659de29bcbe.hip" .globl _Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii # -- Begin function _Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii .p2align 4, 0x90 .type _Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii,@function _Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii: # @_Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 4(%rsp), %rax movq %rax, 112(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii, .Lfunc_end0-_Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii .cfi_endproc # -- End function .globl Convolution3x3 # -- Begin function Convolution3x3 .p2align 4, 0x90 .type Convolution3x3,@function Convolution3x3: # @Convolution3x3 .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $128, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r8, %r15 movl %ecx, %ebx movl %edx, %ebp movq %rsi, %r14 movq %rdi, %r12 movl $FilterCoeff, %edi movl $FilterCoeff_CPU, %esi movl $36, %edx xorl %ecx, %ecx movl $1, %r8d callq hipMemcpyToSymbol testl %eax, %eax jne .LBB1_4 # %bb.1: movl %ebp, %eax shrl $6, %eax leal 1(%rax), %ecx testb $63, %bpl cmovel %eax, %ecx movl %ebx, %eax shrl $4, %eax leal 1(%rax), %edi testb $15, %bl cmovel %eax, %edi shlq $32, %rdi orq %rcx, %rdi movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_3 # %bb.2: leal 3(%r15), %eax testl %r15d, %r15d cmovnsl %r15d, %eax sarl $2, %eax movq %r12, 72(%rsp) movq %r14, 64(%rsp) movl %ebp, 12(%rsp) movl %ebx, 8(%rsp) movl %eax, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 4(%rsp), %rax movq %rax, 112(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_3: callq hipDeviceSynchronize .LBB1_4: addq $128, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size Convolution3x3, .Lfunc_end1-Convolution3x3 .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $0, 8(%rsp) movl $1, (%rsp) movl $FilterCoeff, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movl $36, %r9d movq %rbx, %rdi xorl %r8d, %r8d callq __hipRegisterVar movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type FilterCoeff,@object # @FilterCoeff .local FilterCoeff .comm FilterCoeff,36,16 .type FilterCoeff_CPU,@object # @FilterCoeff_CPU .data .globl FilterCoeff_CPU .p2align 4, 0x0 FilterCoeff_CPU: .long 0xbf800000 # float -1 .long 0xc0000000 # float -2 .long 0xbf800000 # float -1 .long 0xc0000000 # float -2 .long 0x41400000 # float 12 .long 0xc0000000 # float -2 .long 0xbf800000 # float -1 .long 0xc0000000 # float -2 .long 0xbf800000 # float -1 .size FilterCoeff_CPU, 36 .type _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii,@object # @_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii .section .rodata,"a",@progbits .globl _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii .p2align 3, 0x0 _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii: .quad _Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii .size _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii" .size .L__unnamed_1, 56 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "FilterCoeff" .size .L__unnamed_2, 12 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym FilterCoeff .addrsig_sym FilterCoeff_CPU .addrsig_sym _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
4,195
3,401
7,177
3,846
111
code for sm_80 Function : _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R5, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R5, R5, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ; @P0 EXIT ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x184] ; ULDC.64 UR6, c[0x0][0x118] ; IMAD.MOV.U32 R0, RZ, RZ, 0x8 ; IMAD R9, R2, 0x2, R5 ; IMAD.WIDE R2, R5, R0, c[0x0][0x160] ; IMAD.WIDE R8, R9, R0, c[0x0][0x168] ; LDG.E.64 R6, [R2.64] ; LDG.E.64 R8, [R8.64] ; IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x17c] ; IABS R13, c[0x0][0x178] ; BSSY B0, 0xdc0 ; IABS R17, c[0x0][0x17c] ; IMAD R14, R15, c[0x0][0x178], RZ ; I2F.RP R12, R13 ; IABS R22, c[0x0][0x180] ; IABS R4, R14 ; I2F.RP R16, R4 ; MUFU.RCP R12, R12 ; MUFU.RCP R16, R16 ; IADD3 R18, R12, 0xffffffe, RZ ; I2F.RP R21, R17 ; IADD3 R10, R16, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R19, R18 ; IABS R16, R5 ; F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; IADD3 R20, RZ, -R19, RZ ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; MUFU.RCP R21, R21 ; IMAD R23, R20, R13, RZ ; IMAD.MOV R12, RZ, RZ, -R11 ; IMAD.HI.U32 R19, R19, R23, R18 ; IMAD.MOV.U32 R23, RZ, RZ, R12 ; IMAD.HI.U32 R12, R19, R16, RZ ; IMAD R23, R23, R4, RZ ; IMAD.MOV.U32 R18, RZ, RZ, R22 ; IABS R22, R14 ; IMAD.HI.U32 R11, R11, R23, R10 ; I2F.RP R20, R18 ; IADD3 R23, RZ, -R22, RZ ; IMAD.MOV R10, RZ, RZ, -R12 ; IMAD.HI.U32 R19, R11, R16, RZ ; IADD3 R11, R21, 0xffffffe, RZ ; IMAD R10, R13, R10, R16.reuse ; IMAD R23, R19, R23, R16 ; F2I.FTZ.U32.TRUNC.NTZ R11, R11 ; ISETP.GT.U32.AND P0, PT, R13, R10, PT ; ISETP.GT.U32.AND P4, PT, R4, R23, PT ; MUFU.RCP R20, R20 ; @!P0 IMAD.IADD R10, R10, 0x1, -R13 ; @!P0 IADD3 R12, R12, 0x1, RZ ; @!P4 IMAD.IADD R23, R23, 0x1, -R4 ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; ISETP.GE.U32.AND P5, PT, R10, R13, PT ; ISETP.GE.U32.AND P3, PT, R23, R4, PT ; LOP3.LUT R4, R5.reuse, c[0x0][0x178], RZ, 0x3c, !PT ; IADD3 R21, R20, 0xffffffe, RZ ; ISETP.GE.AND P2, PT, R4, RZ, PT ; F2I.FTZ.U32.TRUNC.NTZ R13, R21 ; LOP3.LUT R10, R5, R14, RZ, 0x3c, !PT ; @P5 IADD3 R12, R12, 0x1, RZ ; ISETP.GE.AND P1, PT, R10, RZ, PT ; IMAD.MOV R10, RZ, RZ, -R11 ; @!P4 IADD3 R19, R19, 0x1, RZ ; IMAD.MOV.U32 R4, RZ, RZ, R12 ; ISETP.NE.AND P4, PT, R14, RZ, PT ; IMAD R21, R10, R17, RZ ; @P3 IADD3 R19, R19, 0x1, RZ ; @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; @!P0 LOP3.LUT R4, RZ, c[0x0][0x178], RZ, 0x33, !PT ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; IADD3 R23, RZ, -R13, RZ ; IABS R12, R4 ; @!P1 IMAD.MOV R19, RZ, RZ, -R19 ; ISETP.GE.AND P2, PT, R4, RZ, PT ; IMAD.HI.U32 R10, R11, R21, R10 ; @!P4 LOP3.LUT R19, RZ, R14, RZ, 0x33, !PT ; IMAD.MOV.U32 R11, RZ, RZ, R12 ; IABS R20, R19 ; IMAD R21, R23, R18, RZ ; ISETP.GE.AND P4, PT, R19, RZ, PT ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; IMAD.HI.U32 R10, R10, R11, RZ ; IMAD.HI.U32 R12, R13, R21, R12 ; MOV R13, R20 ; IMAD.MOV R10, RZ, RZ, -R10 ; IMAD.HI.U32 R12, R12, R13, RZ ; IMAD.MOV R12, RZ, RZ, -R12 ; IMAD R10, R17.reuse, R10, R11 ; IMAD R11, R18.reuse, R12, R13 ; IMAD.MOV R12, RZ, RZ, -R4 ; ISETP.GT.U32.AND P0, PT, R17, R10, PT ; ISETP.GT.U32.AND P1, PT, R18, R11, PT ; @!P0 IMAD.IADD R10, R10, 0x1, -R17 ; @!P1 IMAD.IADD R11, R11, 0x1, -R18 ; ISETP.NE.AND P1, PT, RZ, c[0x0][0x180], PT ; ISETP.GT.U32.AND P0, PT, R17, R10, PT ; ISETP.GT.U32.AND P3, PT, R18, R11, PT ; @!P0 IADD3 R10, R10, -R17, RZ ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x17c], PT ; @!P3 IMAD.IADD R11, R11, 0x1, -R18 ; SHF.R.S32.HI R18, RZ, 0x1f, R5 ; IMAD.MOV.U32 R4, RZ, RZ, R10 ; IMAD.MOV.U32 R10, RZ, RZ, R11 ; IMAD R11, R12, c[0x0][0x178], R5 ; @!P2 IADD3 R4, -R4, RZ, RZ ; @!P4 IMAD.MOV R10, RZ, RZ, -R10 ; LEA R12, P4, R5, c[0x0][0x1b0], 0x3 ; @!P1 LOP3.LUT R10, RZ, c[0x0][0x180], RZ, 0x33, !PT ; @!P0 LOP3.LUT R4, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; LEA.HI.X R13, R5, c[0x0][0x1b4], R18, 0x3, P4 ; ISETP.GE.AND P0, PT, R11, c[0x0][0x19c], PT ; ISETP.GE.AND P2, PT, R4, c[0x0][0x194], PT ; ISETP.GE.AND P1, PT, R10, c[0x0][0x18c], PT ; ISETP.LE.AND P0, PT, R11, c[0x0][0x1a0], P0 ; ISETP.LE.AND P2, PT, R4, c[0x0][0x198], P2 ; ISETP.LE.AND P1, PT, R10, c[0x0][0x190], P1 ; PLOP3.LUT P0, PT, P0, P2, P1, 0x80, 0x0 ; DSETP.GTU.AND P3, PT, R8, R6, PT ; @!P3 IMAD.MOV.U32 R6, RZ, RZ, R8 ; @!P3 STG.E.64 [R2.64], R8 ; @!P3 IMAD.MOV.U32 R7, RZ, RZ, R9 ; STG.E.64 [R12.64], R6 ; @!P0 BRA 0xdb0 ; IMAD R14, R14, c[0x0][0x180], RZ ; IADD3 R15, R15, -0x1, RZ ; UMOV UR5, 0x1 ; IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; ULDC UR4, c[0x0][0x178] ; IABS R9, R14 ; UIADD3 UR4, -UR5, UR4, URZ ; I2F.RP R8, R9 ; MUFU.RCP R8, R8 ; IADD3 R6, R8, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; MOV R6, RZ ; IMAD.MOV R12, RZ, RZ, -R7 ; IMAD R13, R12, R9, RZ ; IABS R12, R14 ; IMAD.HI.U32 R7, R7, R13, R6 ; LOP3.LUT R6, R5, R14, RZ, 0x3c, !PT ; IMAD.MOV R12, RZ, RZ, -R12 ; ISETP.GE.AND P2, PT, R6, RZ, PT ; IMAD.HI.U32 R7, R7, R16, RZ ; IMAD R16, R7, R12, R16 ; ISETP.GT.U32.AND P1, PT, R9, R16, PT ; @!P1 IMAD.IADD R16, R16, 0x1, -R9 ; @!P1 IADD3 R7, R7, 0x1, RZ ; ISETP.NE.AND P1, PT, R14, RZ, PT ; ISETP.GE.U32.AND P0, PT, R16, R9, PT ; IADD3 R16, R4, 0x1, RZ ; IADD3 R9, R11, -0x1, RZ ; @P0 IADD3 R7, R7, 0x1, RZ ; ISETP.GE.AND P0, PT, R4, 0x1, PT ; @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; @!P1 LOP3.LUT R7, RZ, R14, RZ, 0x33, !PT ; ISETP.GE.AND P2, PT, R4.reuse, R15, PT ; ISETP.GE.AND P1, PT, R11, 0x1, PT ; IMAD R15, R7, c[0x0][0x174], RZ ; IADD3 R7, R4, -0x1, RZ ; IADD3 R14, R11, 0x1, RZ ; IMAD R17, R10, c[0x0][0x188], R15 ; SEL R12, R16, R7, !P0 ; ISETP.GE.AND P0, PT, R11.reuse, UR4, PT ; IMAD R13, R4, c[0x0][0x178], R17 ; SEL R6, R14.reuse, R9.reuse, !P1 ; ULDC UR4, c[0x0][0x180] ; SEL R14, R14, R9, !P0 ; UIADD3 UR4, -UR5, UR4, URZ ; SEL R16, R16, R7, !P2 ; IMAD.IADD R7, R11, 0x1, R13.reuse ; IADD3 R9, R6, R13, RZ ; IMAD.IADD R13, R14, 0x1, R13 ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1b8], PT ; IMAD.WIDE R6, R7, R0, c[0x0][0x160] ; ISETP.GE.AND P1, PT, R10, UR4, PT ; IMAD.WIDE R8, R9, R0.reuse, c[0x0][0x160] ; LDG.E.64 R6, [R6.64] ; IMAD R20, R12, c[0x0][0x178], R11 ; LDG.E.64 R8, [R8.64] ; IMAD.WIDE R12, R13, R0, c[0x0][0x160] ; IMAD.IADD R19, R17, 0x1, R20 ; IMAD R16, R16, c[0x0][0x178], R11 ; SEL R11, R18, 0xffffffff, !P1 ; LDG.E.64 R12, [R12.64] ; IMAD.WIDE R18, R19, R0, c[0x0][0x160] ; @P0 IADD3 R21, R14, R15, RZ ; IMAD.IADD R17, R17, 0x1, R16 ; SEL R11, R11, RZ, P0 ; LDG.E.64 R14, [R18.64] ; IMAD.WIDE R16, R17, R0, c[0x0][0x160] ; IMAD.IADD R10, R10, 0x1, R11 ; @P0 IMAD R21, R4, c[0x0][0x178], R21 ; LDG.E.64 R16, [R16.64] ; @P0 IMAD R21, R10, c[0x0][0x188], R21 ; CS2R R10, SRZ ; @P0 IMAD.WIDE R20, R21, R0, c[0x0][0x160] ; @P0 LDG.E.64 R10, [R20.64] ; I2F.F64 R22, c[0x0][0x1a4] ; DADD R22, R22, R22 ; IMAD.WIDE R4, R5, R0, c[0x0][0x1b0] ; DFMA R6, R6, R22, R8 ; DADD R6, R12, R6 ; DADD R14, R14, R6 ; CS2R R6, SRZ ; @P0 IMAD.MOV.U32 R6, RZ, RZ, R12 ; @P0 IMAD.MOV.U32 R7, RZ, RZ, R13 ; DADD R14, R16, R14 ; DADD R6, R14, R6 ; DADD R6, R6, R10 ; DMUL R6, R6, 0.25 ; DMUL R6, R6, c[0x0][0x1a8] ; STG.E.64 [R4.64], R6 ; BSYNC B0 ; STG.E.64 [R2.64], R6 ; EXIT ; BRA 0xde0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z19resvisc_gpu_kernel2Pdiiiiiiidd .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; @P0 EXIT ; IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; LDG.E.64 R4, [R2.64] ; DSETP.NEU.AND P0, PT, RZ, c[0x0][0x190], PT ; DMUL R4, |R4|, c[0x0][0x188] ; STG.E.64 [R2.64], R4 ; @!P0 EXIT ; MUFU.RCP64H R7, c[0x0][0x194] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x194] ; MOV R11, c[0x0][0x194] ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x190] ; IADD3 R6, R0, 0x300402, RZ ; FSETP.GEU.AND P0, PT, |R6|, 5.8789094863358348022e-39, PT ; DFMA R8, R6, -R10, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R10, R8, -R10, 1 ; DFMA R8, R8, R10, R8 ; @P0 BRA 0x1e0 ; LOP3.LUT R0, R0, 0x7fffffff, RZ, 0xc0, !PT ; IADD3 R10, R0, -0x100000, RZ ; MOV R0, 0x1e0 ; CALL.REL.NOINC 0x210 ; DMUL R8, R4, R8 ; STG.E.64 [R2.64], R8 ; EXIT ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x190] ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x194] ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x194] ; DSETP.GTU.AND P0, PT, |R6|, +INF , PT ; @P0 BRA 0x450 ; LOP3.LUT R12, R11, 0x7fffffff, RZ, 0xc0, !PT ; IADD3 R8, R12, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R8, 0x7fefffff, PT ; @P0 LOP3.LUT R9, R11, 0x7ff00000, RZ, 0x3c, !PT ; @P0 MOV R8, RZ ; @P0 BRA 0x470 ; ISETP.GE.U32.AND P0, PT, R12, 0x1000001, PT ; @!P0 BRA 0x3b0 ; IADD3 R9, R11, -0x3fe00000, RZ ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x190] ; MUFU.RCP64H R11, R9 ; DFMA R12, -R8, R10, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R10, R12, R10 ; DFMA R10, -R8, R12, 1 ; DFMA R10, R12, R10, R12 ; DMUL R10, R10, 2.2250738585072013831e-308 ; DFMA R6, R10, -R6, 1 ; DFMA R6, R6, R6, R6 ; DFMA R8, R10, R6, R10 ; BRA 0x470 ; DMUL R6, R6, 8.11296384146066816958e+31 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MUFU.RCP64H R9, R7 ; DFMA R10, -R6, R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, -R6, R10, 1 ; DFMA R8, R10, R8, R10 ; DMUL R8, R8, 8.11296384146066816958e+31 ; BRA 0x470 ; LOP3.LUT R9, R11, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x190] ; MOV R6, R0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; RET.REL.NODEC R6 0x0 ; BRA 0x4a0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z19resvisc_gpu_kernel1PdiiiiiiiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; @P0 EXIT ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x174] ; IABS R8, R0 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD R2, R2, c[0x0][0x170], RZ ; IMAD R5, R2, c[0x0][0x178], RZ ; IABS R7, R5.reuse ; IABS R10, R5 ; I2F.RP R4, R7 ; MUFU.RCP R4, R4 ; IADD3 R2, R4, 0xffffffe, RZ ; IADD3 R4, RZ, -R10, RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IADD3 R6, RZ, -R3, RZ ; IMAD R9, R6, R7, RZ ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; IMAD.HI.U32 R3, R3, R9, R2 ; IMAD.HI.U32 R3, R3, R6, RZ ; IMAD R2, R3, R4, R6 ; ISETP.GT.U32.AND P2, PT, R7, R2, PT ; @!P2 IMAD.IADD R2, R2, 0x1, -R7 ; @!P2 IADD3 R3, R3, 0x1, RZ ; ISETP.NE.AND P2, PT, R5, RZ, PT ; ISETP.GE.U32.AND P0, PT, R2, R7, PT ; HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; LOP3.LUT R2, R0, R5, RZ, 0x3c, !PT ; ISETP.GE.AND P1, PT, R2, RZ, PT ; @P0 IADD3 R3, R3, 0x1, RZ ; MOV R4, R3 ; IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; @!P2 LOP3.LUT R4, RZ, R5, RZ, 0x33, !PT ; IMAD.WIDE R4, R4, R7, c[0x0][0x188] ; LDG.E.64 R6, [R2.64] ; LDG.E.64 R4, [R4.64] ; DMUL R6, R4, R6 ; DMUL R6, R4, R6 ; STG.E.64 [R2.64], R6 ; EXIT ; BRA 0x2d0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; @P0 EXIT ; IABS R6, c[0x0][0x16c] ; IMAD.MOV.U32 R31, RZ, RZ, 0x1 ; IABS R7, R0 ; ULDC.64 UR4, c[0x0][0x118] ; I2F.RP R4, R6 ; ISETP.GE.AND P2, PT, R0, RZ, PT ; IADD3 R17, -R31, c[0x0][0x170], RZ ; MUFU.RCP R4, R4 ; IADD3 R2, R4, 0xffffffe, RZ ; IADD3 R4, -R31, c[0x0][0x174], RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IADD3 R31, -R31, c[0x0][0x178], RZ ; IMAD R21, R4, c[0x0][0x170], RZ ; IMAD R31, R31, c[0x0][0x180], RZ ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.MOV R5, RZ, RZ, -R3 ; IMAD R5, R5, R6, RZ ; IMAD.HI.U32 R3, R3, R5, R2 ; MOV R5, R7 ; IMAD.HI.U32 R3, R3, R5, RZ ; IMAD.MOV R3, RZ, RZ, -R3 ; IMAD R3, R6, R3, R5 ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; ISETP.GT.U32.AND P0, PT, R6, R3, PT ; @!P0 IMAD.IADD R3, R3, 0x1, -R6 ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x16c], PT ; ISETP.GT.U32.AND P1, PT, R6, R3, PT ; @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; @!P2 IADD3 R3, -R3, RZ, RZ ; @!P0 LOP3.LUT R3, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; IMAD.IADD R2, R0, 0x1, -R3 ; HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; IMAD R6, R5, 0x2, R2 ; IADD3 R8, R2.reuse, R21, RZ ; IMAD.IADD R38, R2, 0x1, R17 ; IMAD.WIDE R6, R6, R3, c[0x0][0x160] ; IMAD.WIDE R40, R2, R3, c[0x0][0x188] ; IMAD.WIDE R12, R31, 0x8, R6.reuse ; LDG.E.64 R40, [R40.64] ; IMAD.WIDE R10, R21, 0x8, R6 ; IMAD.WIDE R20, R21, 0x8, R12 ; IMAD.WIDE R4, R2, R3, c[0x0][0x190] ; IMAD.WIDE R38, R38, R3.reuse, c[0x0][0x188] ; LDG.E.64 R4, [R4.64] ; IMAD.WIDE R8, R8, R3, c[0x0][0x190] ; LDG.E.64 R38, [R38.64] ; IMAD.WIDE R14, R17.reuse, 0x8, R6 ; LDG.E.64 R6, [R6.64] ; IMAD.WIDE R18, R17, 0x8, R12 ; LDG.E.64 R8, [R8.64] ; IMAD.WIDE R22, R17.reuse, 0x8, R20 ; LDG.E.64 R12, [R12.64] ; IMAD.WIDE R32, R17, 0x8, R10 ; LDG.E.64 R10, [R10.64] ; LDG.E.64 R14, [R14.64] ; LDG.E.64 R16, [R32.64] ; LDG.E.64 R18, [R18.64] ; LDG.E.64 R20, [R20.64] ; LDG.E.64 R22, [R22.64] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1a0], PT ; CS2R R24, SRZ ; CS2R R26, SRZ ; IMAD.WIDE R28, R2, R3, c[0x0][0x198] ; @!P0 BRA 0x5c0 ; IMAD.IADD R2, R2, 0x1, R31 ; LDG.E.64 R30, [R28.64] ; IMAD.WIDE R2, R2, R3, c[0x0][0x198] ; LDG.E.64 R2, [R2.64] ; BSSY B0, 0x5c0 ; DADD R30, -R30, R2 ; MUFU.RCP64H R27, R31 ; IADD3 R26, R31, 0x300402, RZ ; DFMA R32, -R30, R26, 1 ; FSETP.GEU.AND P1, PT, |R26|, 5.8789094863358348022e-39, PT ; DFMA R32, R32, R32, R32 ; DFMA R32, R26, R32, R26 ; DFMA R34, -R30, R32, 1 ; DFMA R26, R32, R34, R32 ; @P1 BRA 0x5b0 ; LOP3.LUT R34, R31, 0x7fffffff, RZ, 0xc0, !PT ; MOV R2, 0x590 ; IADD3 R34, R34, -0x100000, RZ ; CALL.REL.NOINC 0xb20 ; IMAD.MOV.U32 R26, RZ, RZ, R32 ; MOV R27, R33 ; BSYNC B0 ; IMAD.MOV.U32 R35, RZ, RZ, 0x8 ; IMAD.WIDE R34, R0, R35, c[0x0][0x188] ; LDG.E.64 R32, [R34.64] ; DADD R30, -R40, R38 ; BSSY B0, 0x710 ; MUFU.RCP64H R3, R31 ; IADD3 R2, R31, 0x300402, RZ ; FSETP.GEU.AND P1, PT, |R2|, 5.8789094863358348022e-39, PT ; DFMA R36, -R30, R2, 1 ; DFMA R36, R36, R36, R36 ; DFMA R36, R2, R36, R2 ; SHF.R.S32.HI R3, RZ, 0x1f, R0 ; DFMA R38, -R30, R36, 1 ; DADD R40, -R40, R32 ; DFMA R32, R36, R38, R36 ; @P1 BRA 0x700 ; LOP3.LUT R34, R31, 0x7fffffff, RZ, 0xc0, !PT ; MOV R2, 0x700 ; IADD3 R34, R34, -0x100000, RZ ; CALL.REL.NOINC 0xb20 ; BSYNC B0 ; IMAD.MOV.U32 R35, RZ, RZ, 0x8 ; IMAD.WIDE R34, R0, R35, c[0x0][0x190] ; LDG.E.64 R34, [R34.64] ; DADD R30, -R4, R8 ; BSSY B0, 0x860 ; DMUL R40, R40, R32 ; MUFU.RCP64H R9, R31 ; IADD3 R8, R31, 0x300402, RZ ; FSETP.GEU.AND P1, PT, |R8|, 5.8789094863358348022e-39, PT ; DFMA R36, -R30, R8, 1 ; DFMA R36, R36, R36, R36 ; DFMA R36, R8, R36, R8 ; DFMA R38, -R30, R36, 1 ; DFMA R32, R36, R38, R36 ; DADD R4, -R4, R34 ; @P1 BRA 0x850 ; LOP3.LUT R34, R31, 0x7fffffff, RZ, 0xc0, !PT ; MOV R2, 0x850 ; IADD3 R34, R34, -0x100000, RZ ; CALL.REL.NOINC 0xb20 ; BSYNC B0 ; @P0 LEA R8, P1, R0.reuse, c[0x0][0x198], 0x3 ; @P0 LDG.E.64 R28, [R28.64] ; @P0 LEA.HI.X R9, R0, c[0x0][0x19c], R3, 0x3, P1 ; @P0 LDG.E.64 R8, [R8.64] ; DADD R30, -R20, R22 ; DADD R30, -R18, R30 ; DADD R2, R14, -R6 ; DADD R30, -R16, R30 ; DADD R16, -R10, R16 ; DADD R30, R14, R30 ; DMUL R4, R4, R32 ; DADD R22, -R6, R10 ; DFMA R2, R40, R2, R6 ; DADD R16, -R14, R16 ; DADD R20, -R12, R20 ; DADD R18, -R12, R18 ; DADD R30, R12, R30 ; DFMA R2, R4, R22, R2 ; DADD R12, -R6, R12 ; DADD R20, -R10, R20 ; DADD R16, R6, R16 ; DADD R30, R10, R30 ; DADD R20, R6, R20 ; DMUL R16, R40, R16 ; DADD R30, -R6, R30 ; DMUL R20, R4, R20 ; DMUL R30, R4, R30 ; @P0 DADD R28, -R28, R8 ; @P0 DMUL R24, R28, R26 ; DADD R8, -R14, R18 ; DFMA R2, R12, R24, R2 ; DADD R8, R6, R8 ; DFMA R2, R4, R16, R2 ; DMUL R8, R8, R24 ; DFMA R2, R20, R24, R2 ; MOV R5, c[0x0][0x17c] ; DMUL R30, R30, R24 ; DFMA R2, R40, R8, R2 ; IMAD R4, R5, 0x2, R0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; DFMA R2, R40, R30, R2 ; IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; STG.E.64 [R4.64], R2 ; EXIT ; DSETP.GTU.AND P1, PT, |R30|, +INF , PT ; BSSY B1, 0xd60 ; @P1 BRA 0xd30 ; LOP3.LUT R35, R31, 0x7fffffff, RZ, 0xc0, !PT ; IADD3 R32, R35, -0x1, RZ ; ISETP.GE.U32.AND P1, PT, R32, 0x7fefffff, PT ; @P1 LOP3.LUT R33, R31, 0x7ff00000, RZ, 0x3c, !PT ; @P1 MOV R32, RZ ; @P1 BRA 0xd50 ; ISETP.GE.U32.AND P1, PT, R35, 0x1000001, PT ; @!P1 BRA 0xca0 ; IADD3 R33, R31, -0x3fe00000, RZ ; IMAD.MOV.U32 R32, RZ, RZ, R30 ; MUFU.RCP64H R35, R33 ; DFMA R36, -R32, R34, 1 ; DFMA R36, R36, R36, R36 ; DFMA R36, R34, R36, R34 ; DFMA R34, -R32, R36, 1 ; DFMA R34, R36, R34, R36 ; DMUL R34, R34, 2.2250738585072013831e-308 ; DFMA R30, -R30, R34, 1 ; DFMA R30, R30, R30, R30 ; DFMA R32, R34, R30, R34 ; BRA 0xd50 ; DMUL R30, R30, 8.11296384146066816958e+31 ; MUFU.RCP64H R35, R31 ; DFMA R32, -R30, R34, 1 ; DFMA R32, R32, R32, R32 ; DFMA R32, R34, R32, R34 ; DFMA R34, -R30, R32, 1 ; DFMA R32, R32, R34, R32 ; DMUL R32, R32, 8.11296384146066816958e+31 ; BRA 0xd50 ; LOP3.LUT R33, R31, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R32, RZ, RZ, R30 ; BSYNC B1 ; MOV R30, R2 ; IMAD.MOV.U32 R31, RZ, RZ, 0x0 ; RET.REL.NODEC R30 0x0 ; BRA 0xd90; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ; @P0 EXIT ; HFMA2.MMA R13, -RZ, RZ, 0, 4.76837158203125e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R0, R13, c[0x0][0x178] ; IMAD.WIDE R4, R0.reuse, R13.reuse, c[0x0][0x170] ; LDG.E.64 R2, [R2.64] ; IMAD.WIDE R8, R0, R13, c[0x0][0x180] ; LDG.E.64 R4, [R4.64] ; LDG.E.64 R8, [R8.64] ; BSSY B0, 0x230 ; DMUL R6, R2, R2 ; IMAD.WIDE R2, R0, R13, c[0x0][0x168] ; DFMA R6, R4, R4, R6 ; DFMA R6, R8, R8, R6 ; F2F.F32.F64 R6, R6 ; IADD3 R10, R6, -0xd000000, RZ ; MUFU.RSQ R11, R6 ; ISETP.GT.U32.AND P0, PT, R10, 0x727fffff, PT ; @!P0 BRA 0x1e0 ; BSSY B1, 0x1c0 ; MOV R10, 0x1b0 ; CALL.REL.NOINC 0x6c0 ; BSYNC B1 ; IMAD.MOV.U32 R4, RZ, RZ, R6 ; BRA 0x220 ; FMUL.FTZ R5, R6, R11 ; FMUL.FTZ R11, R11, 0.5 ; FFMA R4, -R5, R5, R6 ; FFMA R4, R4, R11, R5 ; BSYNC B0 ; LDG.E.64 R2, [R2.64] ; MOV R5, c[0x0][0x1a0] ; IABS R11, R0 ; IMAD R5, R5, c[0x0][0x19c], RZ ; IMAD R5, R5, c[0x0][0x1a4], RZ ; IABS R10, R5.reuse ; IABS R12, R5 ; I2F.RP R8, R10 ; MUFU.RCP R8, R8 ; IADD3 R6, R8, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; HFMA2.MMA R6, -RZ, RZ, 0, 0 ; IMAD.MOV R9, RZ, RZ, -R7 ; IMAD R9, R9, R10, RZ ; IMAD.HI.U32 R7, R7, R9, R6 ; IMAD.MOV.U32 R9, RZ, RZ, R11 ; IADD3 R11, RZ, -R12, RZ ; IMAD.HI.U32 R8, R7, R9, RZ ; F2F.F64.F32 R6, R4 ; IMAD R9, R8, R11, R9 ; IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; ISETP.GT.U32.AND P2, PT, R10, R9, PT ; @!P2 IADD3 R9, R9, -R10.reuse, RZ ; @!P2 IADD3 R8, R8, 0x1, RZ ; ISETP.GE.U32.AND P0, PT, R9, R10, PT ; LOP3.LUT R9, R0, R5, RZ, 0x3c, !PT ; ISETP.NE.AND P2, PT, R5, RZ, PT ; ISETP.GE.AND P1, PT, R9, RZ, PT ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x198] ; IADD3 R4, R9, 0x1, RZ ; @P0 IADD3 R8, R8, 0x1, RZ ; ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; MOV R10, R8 ; @!P1 IMAD.MOV R10, RZ, RZ, -R10 ; @!P2 LOP3.LUT R10, RZ, R5, RZ, 0x33, !PT ; DADD R6, R6, R2 ; IMAD.WIDE R2, R0, R11, c[0x0][0x190] ; STG.E.64 [R2.64], R6 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P0 BRA 0x5f0 ; LEA.HI R4, R9, c[0x0][0x198], RZ, 0x1 ; SHF.R.S32.HI R11, RZ, 0x1, R4 ; ISETP.GE.U32.AND P0, PT, R10, R11, PT ; BSSY B0, 0x5b0 ; @P0 BRA 0x5a0 ; IADD3 R6, R0, R11, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; LDG.E.64 R4, [R2.64] ; IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x190] ; LDG.E.64 R6, [R6.64] ; F2F.F32.F64 R4, R4 ; F2F.F32.F64 R9, R6 ; FMNMX R9, R4, R9, !PT ; F2F.F64.F32 R8, R9 ; STG.E.64 [R2.64], R8 ; BSYNC B0 ; SHF.R.U32.HI R11, RZ, 0x1, R11 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.AND P0, PT, R11, RZ, PT ; @P0 BRA 0x4d0 ; IADD3 R2, R0, -R10, RZ ; IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; IMAD.WIDE R2, R2, R11, c[0x0][0x190] ; IMAD.WIDE R6, R10, R11, c[0x0][0x1c0] ; LDG.E.64 R2, [R2.64] ; LDG.E.64 R6, [R6.64] ; MOV R9, c[0x0][0x1b8] ; IMAD R8, R9, 0x2, R0 ; IMAD.WIDE R8, R8, R11, c[0x0][0x160] ; DMUL R4, R2, c[0x0][0x1b0] ; DMUL R4, R4, R6 ; STG.E.64 [R8.64], R4 ; EXIT ; LOP3.LUT P0, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; @!P0 MOV R4, R6 ; @!P0 BRA 0x7f0 ; FSETP.GEU.FTZ.AND P0, PT, R6, RZ, PT ; @!P0 IMAD.MOV.U32 R4, RZ, RZ, 0x7fffffff ; @!P0 BRA 0x7f0 ; FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; @P0 FADD.FTZ R4, R6, 1 ; @P0 BRA 0x7f0 ; FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; @P0 FFMA R5, R6, 1.84467440737095516160e+19, RZ ; @P0 MUFU.RSQ R4, R5 ; @P0 FMUL.FTZ R8, R5, R4 ; @P0 FMUL.FTZ R9, R4, 0.5 ; @!P0 MOV R4, R6 ; @P0 FADD.FTZ R7, -R8, -RZ ; @P0 FFMA R7, R8, R7, R5 ; @P0 FFMA R7, R7, R9, R8 ; @P0 FMUL.FTZ R4, R7, 2.3283064365386962891e-10 ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; MOV R4, R10 ; IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; RET.REL.NODEC R4 0x0 ; BRA 0x830; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z4mxm1PdiS_iS_iiiiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R4, SR_CTAID.X ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x188] ; S2R R5, SR_TID.X ; IMAD R3, R0, c[0x0][0x168], RZ ; IMAD R4, R4, c[0x0][0x0], R5 ; IMAD R5, R3, c[0x0][0x18c], RZ ; ISETP.GE.AND P0, PT, R4, R5, PT ; @P0 EXIT ; IABS R8, R3.reuse ; ULDC.64 UR4, c[0x0][0x118] ; IABS R9, R4 ; I2F.RP R2, R8 ; IABS R10, R3 ; IABS R11, c[0x0][0x188] ; MUFU.RCP R2, R2 ; IADD3 R6, R2, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IADD3 R5, RZ, -R7, RZ ; IMAD R5, R5, R8, RZ ; IMAD.HI.U32 R7, R7, R5, R6 ; MOV R5, R9 ; IMAD.MOV R9, RZ, RZ, -R10 ; MOV R10, R11 ; IMAD.HI.U32 R2, R7, R5, RZ ; I2F.RP R6, R10 ; IMAD R5, R2, R9, R5 ; ISETP.GT.U32.AND P2, PT, R8, R5, PT ; MUFU.RCP R6, R6 ; @!P2 IMAD.IADD R5, R5, 0x1, -R8 ; @!P2 IADD3 R2, R2, 0x1, RZ ; ISETP.NE.AND P2, PT, R3, RZ, PT ; ISETP.GE.U32.AND P0, PT, R5, R8, PT ; LOP3.LUT R5, R4, R3, RZ, 0x3c, !PT ; ISETP.GE.AND P1, PT, R5, RZ, PT ; IADD3 R5, R6, 0xffffffe, RZ ; @P0 IADD3 R2, R2, 0x1, RZ ; F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; @!P1 IADD3 R2, -R2, RZ, RZ ; @!P2 LOP3.LUT R2, RZ, R3, RZ, 0x33, !PT ; IADD3 R6, -R2, RZ, RZ ; IMAD R6, R3, R6, R4 ; HFMA2.MMA R4, -RZ, RZ, 0, 0 ; IMAD.MOV R7, RZ, RZ, -R5 ; IMAD R3, R7, R10, RZ ; IABS R7, R6 ; IMAD.HI.U32 R4, R5, R3, R4 ; IMAD.MOV.U32 R3, RZ, RZ, R7 ; IMAD.HI.U32 R4, R4, R3, RZ ; IADD3 R5, -R4, RZ, RZ ; IMAD R3, R10, R5, R3 ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x178] ; ISETP.GT.U32.AND P1, PT, R10, R3, PT ; @!P1 IADD3 R3, R3, -R10.reuse, RZ ; @!P1 IADD3 R4, R4, 0x1, RZ ; ISETP.GE.U32.AND P2, PT, R3, R10, PT ; IMAD R10, R2, c[0x0][0x198], R6 ; LOP3.LUT R3, R6, c[0x0][0x188], RZ, 0x3c, !PT ; ISETP.GE.AND P1, PT, R5, 0x1, PT ; ISETP.GE.AND P0, PT, R3, RZ, PT ; MOV R3, 0x8 ; IMAD.WIDE R10, R10, R3, c[0x0][0x180] ; @P2 IADD3 R4, R4, 0x1, RZ ; ISETP.NE.AND P2, PT, RZ, c[0x0][0x188], PT ; STG.E.64 [R10.64], RZ ; @!P0 IADD3 R4, -R4, RZ, RZ ; @!P1 EXIT ; IADD3 R8, R5, -0x1, RZ ; CS2R R16, SRZ ; @!P2 LOP3.LUT R4, RZ, c[0x0][0x188], RZ, 0x33, !PT ; ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; IMAD.MOV R7, RZ, RZ, -R4 ; MOV R8, RZ ; IMAD R7, R7, c[0x0][0x188], R6 ; @!P0 BRA 0x1060 ; IADD3 R6, -R5, c[0x0][0x178], RZ ; IMAD R20, R2, c[0x0][0x194], R7 ; MOV R9, c[0x0][0x190] ; ULDC.64 UR6, c[0x0][0x160] ; ISETP.GT.AND P0, PT, R6, RZ, PT ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; CS2R R16, SRZ ; IMAD R9, R2, R9, c[0x0][0x19c] ; IMAD.WIDE R20, R20, R3, c[0x0][0x170] ; IMAD R9, R4, c[0x0][0x178], R9 ; @!P0 BRA 0xe90 ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0xb50 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; MOV R12, UR6 ; LDG.E.64 R14, [R20.64] ; MOV R13, UR7 ; IMAD.WIDE R12, R9, 0x8, R12 ; LDG.E.64 R24, [R12.64] ; IMAD.WIDE R22, R0, 0x8, R20 ; DFMA R24, R14, R24, R16 ; STG.E.64 [R10.64], R24 ; LDG.E.64 R14, [R22.64] ; LDG.E.64 R28, [R12.64+0x8] ; IMAD.WIDE R26, R0, 0x8, R22 ; DFMA R28, R14, R28, R24 ; STG.E.64 [R10.64], R28 ; LDG.E.64 R16, [R26.64] ; LDG.E.64 R14, [R12.64+0x10] ; IMAD.WIDE R18, R0, 0x8, R26 ; DFMA R16, R16, R14, R28 ; STG.E.64 [R10.64], R16 ; LDG.E.64 R24, [R18.64] ; LDG.E.64 R14, [R12.64+0x18] ; IMAD.WIDE R22, R0, 0x8, R18 ; DFMA R24, R24, R14, R16 ; STG.E.64 [R10.64], R24 ; LDG.E.64 R20, [R22.64] ; LDG.E.64 R14, [R12.64+0x20] ; IMAD.WIDE R26, R0, 0x8, R22 ; DFMA R20, R20, R14, R24 ; STG.E.64 [R10.64], R20 ; LDG.E.64 R16, [R26.64] ; LDG.E.64 R14, [R12.64+0x28] ; IMAD.WIDE R18, R0, 0x8, R26 ; DFMA R16, R16, R14, R20 ; STG.E.64 [R10.64], R16 ; LDG.E.64 R24, [R18.64] ; LDG.E.64 R14, [R12.64+0x30] ; IMAD.WIDE R22, R0, 0x8, R18 ; DFMA R24, R24, R14, R16 ; STG.E.64 [R10.64], R24 ; LDG.E.64 R20, [R22.64] ; LDG.E.64 R14, [R12.64+0x38] ; IMAD.WIDE R26, R0, 0x8, R22 ; DFMA R20, R20, R14, R24 ; STG.E.64 [R10.64], R20 ; LDG.E.64 R16, [R26.64] ; LDG.E.64 R14, [R12.64+0x40] ; IMAD.WIDE R18, R0, 0x8, R26 ; DFMA R16, R16, R14, R20 ; STG.E.64 [R10.64], R16 ; LDG.E.64 R24, [R18.64] ; LDG.E.64 R14, [R12.64+0x48] ; IMAD.WIDE R22, R0, 0x8, R18 ; DFMA R24, R24, R14, R16 ; STG.E.64 [R10.64], R24 ; LDG.E.64 R20, [R22.64] ; LDG.E.64 R14, [R12.64+0x50] ; IMAD.WIDE R26, R0, 0x8, R22 ; DFMA R20, R20, R14, R24 ; STG.E.64 [R10.64], R20 ; LDG.E.64 R16, [R26.64] ; LDG.E.64 R14, [R12.64+0x58] ; IMAD.WIDE R18, R0, 0x8, R26 ; DFMA R16, R16, R14, R20 ; STG.E.64 [R10.64], R16 ; LDG.E.64 R24, [R18.64] ; LDG.E.64 R14, [R12.64+0x60] ; IMAD.WIDE R22, R0, 0x8, R18 ; DFMA R24, R24, R14, R16 ; STG.E.64 [R10.64], R24 ; LDG.E.64 R20, [R22.64] ; LDG.E.64 R14, [R12.64+0x68] ; DFMA R20, R20, R14, R24 ; IMAD.WIDE R14, R0, 0x8, R22 ; STG.E.64 [R10.64], R20 ; LDG.E.64 R16, [R14.64] ; LDG.E.64 R18, [R12.64+0x70] ; IADD3 R6, R6, -0x10, RZ ; DFMA R26, R16, R18, R20 ; IMAD.WIDE R18, R0, 0x8, R14 ; STG.E.64 [R10.64], R26 ; LDG.E.64 R24, [R12.64+0x78] ; LDG.E.64 R16, [R18.64] ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; UIADD3 UR6, UP0, UR6, 0x80, URZ ; IADD3 R8, R8, 0x10, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD.WIDE R20, R0, 0x8, R18 ; DFMA R16, R16, R24, R26 ; STG.E.64 [R10.64], R16 ; @P1 BRA 0x5c0 ; ISETP.GT.AND P1, PT, R6, 0x4, PT ; @!P1 BRA 0xe70 ; MOV R13, UR7 ; IMAD.U32 R12, RZ, RZ, UR6 ; LDG.E.64 R22, [R20.64] ; IMAD.WIDE R12, R9, 0x8, R12 ; LDG.E.64 R14, [R12.64] ; IMAD.WIDE R24, R0, 0x8, R20 ; DFMA R22, R22, R14, R16 ; STG.E.64 [R10.64], R22 ; LDG.E.64 R16, [R24.64] ; LDG.E.64 R14, [R12.64+0x8] ; IMAD.WIDE R26, R0, 0x8, R24 ; DFMA R16, R16, R14, R22 ; STG.E.64 [R10.64], R16 ; LDG.E.64 R18, [R26.64] ; LDG.E.64 R14, [R12.64+0x10] ; IMAD.WIDE R20, R0, 0x8, R26 ; DFMA R18, R18, R14, R16 ; STG.E.64 [R10.64], R18 ; LDG.E.64 R22, [R20.64] ; LDG.E.64 R14, [R12.64+0x18] ; IMAD.WIDE R24, R0, 0x8, R20 ; DFMA R22, R22, R14, R18 ; STG.E.64 [R10.64], R22 ; LDG.E.64 R16, [R24.64] ; LDG.E.64 R14, [R12.64+0x20] ; DFMA R16, R16, R14, R22 ; IMAD.WIDE R14, R0, 0x8, R24 ; STG.E.64 [R10.64], R16 ; LDG.E.64 R18, [R14.64] ; LDG.E.64 R20, [R12.64+0x28] ; DFMA R18, R18, R20, R16 ; IMAD.WIDE R20, R0, 0x8, R14 ; STG.E.64 [R10.64], R18 ; LDG.E.64 R22, [R20.64] ; LDG.E.64 R24, [R12.64+0x30] ; DFMA R24, R22, R24, R18 ; IMAD.WIDE R22, R0, 0x8, R20 ; STG.E.64 [R10.64], R24 ; LDG.E.64 R26, [R12.64+0x38] ; LDG.E.64 R16, [R22.64] ; UIADD3 UR6, UP0, UR6, 0x40, URZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.WIDE R20, R0, 0x8, R22 ; IADD3 R8, R8, 0x8, RZ ; IADD3 R6, R6, -0x8, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; DFMA R16, R16, R26, R24 ; STG.E.64 [R10.64], R16 ; ISETP.NE.OR P0, PT, R6, RZ, P0 ; @!P0 BRA 0x1060 ; MOV R12, UR6 ; IMAD.U32 R13, RZ, RZ, UR7 ; LDG.E.64 R14, [R20.64] ; IMAD.WIDE R12, R9, 0x8, R12 ; LDG.E.64 R26, [R12.64] ; IMAD.WIDE R24, R0, 0x8, R20 ; DFMA R26, R14, R26, R16 ; STG.E.64 [R10.64], R26 ; LDG.E.64 R14, [R24.64] ; LDG.E.64 R22, [R12.64+0x8] ; DFMA R22, R14, R22, R26 ; IMAD.WIDE R14, R0, 0x8, R24 ; STG.E.64 [R10.64], R22 ; LDG.E.64 R16, [R14.64] ; LDG.E.64 R18, [R12.64+0x10] ; IADD3 R6, R6, -0x4, RZ ; DFMA R28, R16, R18, R22 ; IMAD.WIDE R18, R0, 0x8, R14 ; STG.E.64 [R10.64], R28 ; LDG.E.64 R20, [R12.64+0x18] ; LDG.E.64 R16, [R18.64] ; ISETP.NE.AND P0, PT, R6, RZ, PT ; UIADD3 UR6, UP0, UR6, 0x20, URZ ; IADD3 R8, R8, 0x4, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; DFMA R16, R16, R20, R28 ; IMAD.WIDE R20, R0, 0x8, R18 ; STG.E.64 [R10.64], R16 ; @P0 BRA 0xe90 ; ISETP.NE.AND P0, PT, R5, RZ, PT ; @!P0 EXIT ; IADD3 R9, R8, c[0x0][0x19c], RZ ; IMAD R7, R2, c[0x0][0x194], R7 ; IMAD R9, R2, c[0x0][0x190], R9 ; IMAD R2, R8, c[0x0][0x188], R7 ; IMAD R6, R4, c[0x0][0x178], R9 ; IMAD.WIDE R6, R6, R3, c[0x0][0x160] ; IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; MOV R4, R6 ; MOV R13, R7 ; IMAD.MOV.U32 R8, RZ, RZ, R4 ; MOV R9, R13 ; LDG.E.64 R6, [R2.64] ; LDG.E.64 R8, [R8.64] ; IADD3 R5, R5, -0x1, RZ ; IADD3 R4, P1, R4, 0x8, RZ ; ISETP.NE.AND P0, PT, R5, RZ, PT ; IMAD.WIDE R2, R0, 0x8, R2 ; IADD3.X R13, RZ, R13, RZ, P1, !PT ; DFMA R16, R6, R8, R16 ; STG.E.64 [R10.64], R16 ; @P0 BRA 0x1110 ; EXIT ; BRA 0x11e0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; @P0 EXIT ; IABS R5, c[0x0][0x1f0] ; IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; IABS R28, R0 ; ULDC.64 UR4, c[0x0][0x118] ; I2F.RP R4, R5 ; ISETP.GE.AND P2, PT, R0.reuse, RZ, PT ; IMAD.WIDE R8, R0, R15, c[0x0][0x200] ; LDG.E.64 R8, [R8.64] ; MUFU.RCP R4, R4 ; IADD3 R2, R4, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.MOV R6, RZ, RZ, -R3 ; IMAD R7, R6, R5, RZ ; IMAD.HI.U32 R3, R3, R7, R2 ; IMAD.HI.U32 R3, R3, R28, RZ ; IMAD.MOV R3, RZ, RZ, -R3 ; IMAD R28, R5, R3, R28 ; ISETP.GT.U32.AND P0, PT, R5, R28, PT ; @!P0 IMAD.IADD R28, R28, 0x1, -R5 ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1f0], PT ; ISETP.GT.U32.AND P1, PT, R5, R28, PT ; @!P1 IMAD.IADD R28, R28, 0x1, -R5 ; IMAD.WIDE R4, R0, R15, c[0x0][0x208] ; @!P2 IMAD.MOV R28, RZ, RZ, -R28 ; @!P0 LOP3.LUT R28, RZ, c[0x0][0x1f0], RZ, 0x33, !PT ; LDG.E.64 R4, [R4.64] ; IMAD.WIDE R12, R28, R15, c[0x0][0x1a8] ; IMAD.WIDE R20, R28, R15.reuse, c[0x0][0x1a0] ; LDG.E.64 R12, [R12.64] ; LDG.E.64 R10, [R20.64] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x248], PT ; IMAD.WIDE R6, R0, R15, c[0x0][0x1f8] ; LDG.E.64 R18, [R6.64] ; IMAD.WIDE R16, R0, R15, c[0x0][0x218] ; DMUL R2, R12, R4 ; IMAD.WIDE R4, R0, R15, c[0x0][0x1e8] ; DFMA R10, R10, R8, R2 ; IMAD.WIDE R12, R0, R15, c[0x0][0x220] ; SHF.R.S32.HI R3, RZ, 0x1f, R0 ; IMAD.WIDE R8, R28, R15, c[0x0][0x1b8] ; IMAD.WIDE R14, R28, R15, c[0x0][0x1c0] ; @!P0 BRA 0x660 ; IMAD.SHL.U32 R2, R28, 0x8, RZ ; SHF.R.S32.HI R21, RZ, 0x1f, R28 ; IMAD.SHL.U32 R27, R0.reuse, 0x8, RZ ; SHF.L.U64.HI R26, R0, 0x3, R3 ; SHF.L.U64.HI R28, R28, 0x3, R21 ; IADD3 R22, P1, R2, c[0x0][0x1b0], RZ ; IADD3 R20, P0, R27, c[0x0][0x210], RZ ; IADD3.X R23, R28, c[0x0][0x1b4], RZ, P1, !PT ; IADD3.X R21, R26, c[0x0][0x214], RZ, P0, !PT ; LDG.E.64 R22, [R22.64] ; LDG.E.64 R24, [R20.64] ; DFMA R24, R22, R24, R10 ; IADD3 R10, P0, R2, c[0x0][0x1c8], RZ ; DMUL R18, R18, R24 ; STG.E.64 [R4.64], R18 ; LDG.E.64 R14, [R14.64] ; LDG.E.64 R12, [R12.64] ; IADD3.X R11, R28, c[0x0][0x1cc], RZ, P0, !PT ; LDG.E.64 R8, [R8.64] ; LDG.E.64 R16, [R16.64] ; LDG.E.64 R22, [R20.64] ; LDG.E.64 R10, [R10.64] ; LDG.E.64 R24, [R6.64] ; DMUL R12, R14, R12 ; IADD3 R14, P3, R2, c[0x0][0x1d8], RZ ; IADD3.X R15, R28, c[0x0][0x1dc], RZ, P3, !PT ; DFMA R8, R8, R16, R12 ; IADD3 R12, P4, R27.reuse, c[0x0][0x238], RZ ; IADD3 R16, P0, R27.reuse, c[0x0][0x240], RZ ; IADD3.X R13, R26, c[0x0][0x23c], RZ, P4, !PT ; DFMA R22, R10, R22, R8 ; IADD3 R8, P1, R27, c[0x0][0x230], RZ ; IADD3 R10, P3, R2, c[0x0][0x1e0], RZ ; DFMA R24, R22, R24, R18 ; IADD3.X R9, R26, c[0x0][0x234], RZ, P1, !PT ; IADD3 R18, P2, R2, c[0x0][0x1d0], RZ ; STG.E.64 [R4.64], R24 ; IADD3.X R19, R28, c[0x0][0x1d4], RZ, P2, !PT ; LDG.E.64 R14, [R14.64] ; LDG.E.64 R12, [R12.64] ; IADD3.X R17, R26, c[0x0][0x244], RZ, P0, !PT ; IADD3.X R11, R28, c[0x0][0x1e4], RZ, P3, !PT ; LDG.E.64 R18, [R18.64] ; LDG.E.64 R8, [R8.64] ; LDG.E.64 R16, [R16.64] ; LDG.E.64 R10, [R10.64] ; LDG.E.64 R6, [R6.64] ; DMUL R20, R14, R12 ; DFMA R20, R18, R8, R20 ; DFMA R20, R10, R16, R20 ; DFMA R20, R20, R6, R24 ; STG.E.64 [R4.64], R20 ; BRA 0x710 ; DMUL R10, R18, R10 ; STG.E.64 [R4.64], R10 ; LDG.E.64 R14, [R14.64] ; LDG.E.64 R12, [R12.64] ; LDG.E.64 R8, [R8.64] ; LDG.E.64 R16, [R16.64] ; LDG.E.64 R6, [R6.64] ; DMUL R18, R14, R12 ; DFMA R18, R8, R16, R18 ; DFMA R20, R18, R6, R10 ; STG.E.64 [R4.64], R20 ; LEA R2, P0, R0, c[0x0][0x168], 0x3 ; LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x3, P0 ; LDG.E.64 R4, [R2.64] ; DADD R4, R4, R20 ; STG.E.64 [R2.64], R4 ; EXIT ; BRA 0x770; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; @P0 EXIT ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; ISETP.NE.AND P0, PT, R2, 0x1, PT ; IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; LDG.E.64 R8, [R2.64] ; @P0 IMAD.WIDE R16, R5, c[0x0][0x188], R2 ; @P0 LDG.E.64 R16, [R16.64] ; @!P0 MOV R13, c[0x0][0x188] ; IMAD.WIDE R10, R0, R5, c[0x0][0x168] ; @!P0 IMAD R13, R13, c[0x0][0x184], RZ ; @!P0 IMAD.WIDE R12, R13, 0x8, R2 ; @P0 DADD R14, R8, -R16 ; @P0 STG.E.64 [R10.64], R14 ; @!P0 LDG.E.64 R12, [R12.64] ; IMAD.SHL.U32 R4, R0, 0x8, RZ ; SHF.R.S32.HI R7, RZ, 0x1f, R0 ; SHF.L.U64.HI R6, R0, 0x3, R7 ; IADD3 R20, P1, R4, c[0x0][0x1a0], RZ ; IADD3.X R21, R6, c[0x0][0x1a4], RZ, P1, !PT ; @!P0 DADD R14, R8, -R12 ; DMUL R8, R14, c[0x0][0x178] ; @!P0 STG.E.64 [R10.64], R14 ; STG.E.64 [R10.64], R8 ; LDG.E.64 R16, [R20.64] ; LDG.E.64 R12, [R2.64] ; IADD3 R18, P0, R4, c[0x0][0x190], RZ ; IADD3 R22, P1, R4, c[0x0][0x1a8], RZ ; IADD3.X R19, R6.reuse, c[0x0][0x194], RZ, P0, !PT ; IADD3.X R23, R6, c[0x0][0x1ac], RZ, P1, !PT ; DMUL R12, R12, R16 ; STG.E.64 [R18.64], R12 ; LDG.E.64 R16, [R22.64] ; LDG.E.64 R14, [R2.64] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1b8], PT ; IMAD.WIDE R8, R5, c[0x0][0x198], R18 ; DMUL R14, R14, R16 ; STG.E.64 [R8.64], R14 ; @!P0 EXIT ; IADD3 R8, P0, R4, c[0x0][0x1b0], RZ ; LDG.E.64 R2, [R2.64] ; IADD3.X R9, R6, c[0x0][0x1b4], RZ, P0, !PT ; LDG.E.64 R6, [R8.64] ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x198] ; LEA R4, R11, R0, 0x1 ; IMAD.WIDE R4, R4, R5, c[0x0][0x190] ; DMUL R6, R2, R6 ; STG.E.64 [R4.64], R6 ; EXIT ; BRA 0x370; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z26compute_entropy_gpu_kernelPdS_S_iidddi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; @P0 EXIT ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; ULDC.64 UR8, c[0x0][0x118] ; IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; IADD3 R3, R3, -0x1, RZ ; IMAD R3, R3, c[0x0][0x198], R2 ; IMAD.WIDE R6, R3, R4, c[0x0][0x170] ; LDG.E.64 R6, [R6.64] ; IMAD.WIDE R4, R2, R4, c[0x0][0x168] ; LDG.E.64 R4, [R4.64] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x194] ; BSSY B0, 0x250 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x190] ; LOP3.LUT R0, R0, 0x7ff00000, RZ, 0xc0, !PT ; LEA.HI R0, R0, 0xfffffc0c, RZ, 0xc ; SHF.L.U32 R3, R9.reuse, R0.reuse, RZ ; SHF.L.U64.HI R0, R9, R0, c[0x0][0x194] ; ISETP.NE.U32.AND P0, PT, R3.reuse, RZ, PT ; ISETP.NE.U32.AND P1, PT, R3, RZ, PT ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; ISETP.NE.AND.EX P0, PT, R0.reuse, -0x80000000, PT, P0 ; ISETP.NE.AND.EX P1, PT, R0, -0x80000000, PT, P1 ; DSETP.MAX.AND P3, P2, R6, c[0x0][0x180], PT ; IMAD.MOV.U32 R0, RZ, RZ, R7 ; FSEL R9, R0, c[0x0][0x184], P3 ; SEL R6, R6, c[0x0][0x180], P3 ; MOV R0, 0x240 ; @P2 LOP3.LUT R9, R3, 0x80000, RZ, 0xfc, !PT ; SHF.R.S32.HI R3, RZ, 0x1f, R2 ; IMAD.MOV.U32 R7, RZ, RZ, R9 ; CALL.REL.NOINC 0x11b0 ; BSYNC B0 ; ISETP.GT.OR P1, PT, R7, -0x1, P1 ; DSETP.NEU.AND P2, PT, R6, RZ, PT ; IMAD.MOV.U32 R9, RZ, RZ, R17 ; BSSY B0, 0x3d0 ; IMAD.MOV.U32 R8, RZ, RZ, R16 ; @!P1 LOP3.LUT R11, R9, 0x80000000, RZ, 0x3c, !PT ; @!P1 IMAD.MOV.U32 R9, RZ, RZ, R11 ; @!P2 BRA 0x350 ; FRND.F64.TRUNC R10, c[0x0][0x190] ; PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ; DSETP.NEU.AND P1, PT, R10, c[0x0][0x190], PT ; ISETP.GT.OR P1, PT, R7, -0x1, !P1 ; @P1 BRA 0x3c0 ; IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; IMAD.MOV.U32 R9, RZ, RZ, -0x80000 ; BRA 0x3c0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x190] ; ISETP.LE.AND P1, PT, RZ, c[0x0][0x194], PT ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x194] ; DSETP.NEU.AND P0, PT, |R8|, 0.5, !P0 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; SEL R9, R7, RZ, P0 ; @!P1 LOP3.LUT R9, R9, 0x7ff00000, RZ, 0xfc, !PT ; BSYNC B0 ; DADD R10, R6, c[0x0][0x190] ; BSSY B0, 0x610 ; LOP3.LUT R10, R11, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R10, 0x7ff00000, PT ; @P1 BRA 0x600 ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x190] ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x194] ; DSETP.GTU.AND P1, PT, |R10|, +INF , PT ; DSETP.GTU.OR P1, PT, |R6|, +INF , P1 ; @P1 BRA 0x5f0 ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x194] ; ISETP.NE.AND P1, PT, RZ, c[0x0][0x190], PT ; LOP3.LUT R0, R11, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.EQ.AND P1, PT, R0, 0x7ff00000, !P1 ; @!P1 BRA 0x540 ; ISETP.LE.AND P1, PT, RZ, c[0x0][0x194], PT ; DSETP.GT.AND P0, PT, |R6|, 1, PT ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; SEL R0, RZ, 0x7ff00000, !P0 ; DSETP.NEU.AND P0, PT, R6, -1, PT ; @!P1 LOP3.LUT R0, R0, 0x7ff00000, RZ, 0x3c, !PT ; SEL R9, R0, 0x3ff00000, P0 ; BRA 0x600 ; ISETP.NE.AND P1, PT, R6, RZ, PT ; LOP3.LUT R10, R7, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P1, PT, R10, 0x7ff00000, P1 ; @P1 BRA 0x600 ; ISETP.LT.AND P0, PT, R7, RZ, P0 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; ISETP.GT.AND P1, PT, R11, -0x1, PT ; ISETP.NE.AND P0, PT, R0, 0x3fe00000, P0 ; SEL R9, RZ, 0x7ff00000, !P1 ; @P0 IADD3 R9, R9, -0x80000000, RZ ; BRA 0x600 ; DADD R8, R6, c[0x0][0x190] ; BSYNC B0 ; DSETP.NEU.AND P0, PT, R6, 1, PT ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; BSSY B0, 0x770 ; DSETP.EQ.OR P0, PT, RZ, c[0x0][0x190], !P0 ; FSEL R11, R9, 1.875, !P0 ; FSEL R10, R8, RZ, !P0 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; MUFU.RCP64H R9, R11 ; DFMA R12, -R10, R8, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R8, R12, R8 ; DFMA R8, -R10, R12, 1 ; DFMA R8, R12, R8, R12 ; DMUL R12, R4, R8 ; DFMA R14, -R10, R12, R4 ; DFMA R8, R8, R14, R12 ; FFMA R0, RZ, R11, R9 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x760 ; MOV R0, 0x760 ; CALL.REL.NOINC 0xbc0 ; BSYNC B0 ; ISETP.GT.AND P0, PT, R9, 0xfffff, PT ; IMAD.MOV.U32 R10, RZ, RZ, R8 ; BSSY B0, 0xb80 ; IMAD.MOV.U32 R11, RZ, RZ, R9.reuse ; DMUL R6, R6, c[0x0][0x188] ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; @!P0 DMUL R10, R10, 1.80143985094819840000e+16 ; @!P0 IMAD.MOV.U32 R5, RZ, RZ, R11 ; IADD3 R0, R5, -0x1, RZ ; ISETP.GE.U32.AND P1, PT, R0, 0x7fefffff, PT ; IMAD.MOV.U32 R0, RZ, RZ, -0x3ff ; @!P0 IMAD.MOV.U32 R0, RZ, RZ, -0x435 ; @P1 IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; @P1 FSETP.NEU.AND P2, PT, R11, RZ, PT ; @P1 IMAD.MOV.U32 R13, RZ, RZ, 0x7ff00000 ; @P1 DFMA R12, R10, R12, +INF ; IMAD.MOV.U32 R11, RZ, RZ, R8 ; @!P0 IMAD.MOV.U32 R11, RZ, RZ, R10 ; @P1 FSEL R8, R12, RZ, P2 ; @P1 FSEL R9, R13, -QNAN , P2 ; LEA R4, P2, R2, c[0x0][0x160], 0x3 ; @P1 BRA 0xb70 ; LOP3.LUT R8, R5.reuse, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; LEA.HI R0, R5, R0, RZ, 0xc ; IMAD.MOV.U32 R18, RZ, RZ, 0x3ae80f1e ; LOP3.LUT R9, R8, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R8, RZ, RZ, R11 ; IMAD.MOV.U32 R19, RZ, RZ, 0x3eb1380b ; ISETP.GE.AND P0, PT, R9, 0x3ff6a09f, PT ; @P0 IADD3 R11, R9, -0x100000, RZ ; @P0 IADD3 R0, R0, 0x1, RZ ; @P0 IMAD.MOV.U32 R9, RZ, RZ, R11 ; DADD R16, R8, 1 ; DADD R8, R8, -1 ; MUFU.RCP64H R11, R17 ; DFMA R12, -R16, R10, 1 ; LOP3.LUT R16, R0, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV.U32 R17, RZ, RZ, 0x43300000 ; DFMA R12, R12, R12, R12 ; DADD R16, R16, c[0x2][0x38] ; DFMA R10, R10, R12, R10 ; DMUL R14, R10, R8 ; DFMA R14, R10, R8, R14 ; DMUL R12, R14, R14 ; DADD R20, R8, -R14 ; DFMA R18, R12, R18, c[0x2][0x0] ; DADD R22, R20, R20 ; DFMA R18, R12, R18, c[0x2][0x8] ; DFMA R22, R8, -R14, R22 ; DFMA R18, R12, R18, c[0x2][0x10] ; DMUL R22, R10, R22 ; DFMA R18, R12, R18, c[0x2][0x18] ; DFMA R18, R12, R18, c[0x2][0x20] ; DFMA R20, R12, R18, c[0x2][0x28] ; DFMA R18, R16, c[0x2][0x40], R14 ; DFMA R20, R12, R20, c[0x2][0x30] ; DFMA R8, -R16, c[0x2][0x40], R18 ; DMUL R20, R12, R20 ; DADD R8, -R14, R8 ; DFMA R20, R14, R20, R22 ; DADD R8, R20, -R8 ; DFMA R8, R16, c[0x2][0x48], R8 ; DADD R8, R18, R8 ; BSYNC B0 ; DMUL R6, R6, R8 ; LEA.HI.X R5, R2, c[0x0][0x164], R3, 0x3, P2 ; STG.E.64 [R4.64], R6 ; EXIT ; FSETP.GEU.AND P0, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R15, RZ, RZ, 0x1ca00000 ; LOP3.LUT R8, R11, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R12, RZ, RZ, R4 ; LOP3.LUT R9, R8, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; LOP3.LUT R14, R5, 0x7ff00000, RZ, 0xc0, !PT ; BSSY B1, 0x1160 ; LOP3.LUT R21, R11, 0x7ff00000, RZ, 0xc0, !PT ; @!P0 DMUL R8, R10, 8.98846567431157953865e+307 ; ISETP.GE.U32.AND P1, PT, R14, R21, PT ; @!P2 LOP3.LUT R13, R11, 0x7ff00000, RZ, 0xc0, !PT ; @!P2 IMAD.MOV.U32 R18, RZ, RZ, RZ ; MUFU.RCP64H R17, R9 ; @!P2 ISETP.GE.U32.AND P3, PT, R14, R13, PT ; SEL R13, R15.reuse, 0x63400000, !P1 ; @!P2 SEL R19, R15, 0x63400000, !P3 ; LOP3.LUT R13, R13, 0x800fffff, R5, 0xf8, !PT ; @!P2 LOP3.LUT R19, R19, 0x80000000, R5, 0xf8, !PT ; @!P2 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; DFMA R22, R16, -R8, 1 ; @!P2 DFMA R12, R12, 2, -R18 ; IMAD.MOV.U32 R18, RZ, RZ, R14 ; DFMA R22, R22, R22, R22 ; IMAD.MOV.U32 R19, RZ, RZ, R21 ; @!P0 LOP3.LUT R19, R9, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R16, R16, R22, R16 ; @!P2 LOP3.LUT R18, R13, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R24, R19, -0x1, RZ ; DFMA R22, R16, -R8, 1 ; DFMA R16, R16, R22, R16 ; IADD3 R22, R18, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ; DMUL R20, R16, R12 ; ISETP.GT.U32.OR P0, PT, R24, 0x7feffffe, P0 ; DFMA R22, R20, -R8, R12 ; DFMA R16, R16, R22, R20 ; @P0 BRA 0x1000 ; LOP3.LUT R5, R11, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R14.reuse, R5, PT ; IMAD.IADD R4, R14, 0x1, -R5 ; SEL R15, R15, 0x63400000, !P0 ; IMNMX R4, R4, -0x46a00000, !PT ; IMNMX R4, R4, 0x46a00000, PT ; IMAD.IADD R18, R4, 0x1, -R15 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; IADD3 R5, R18, 0x7fe00000, RZ ; DMUL R14, R16, R4 ; FSETP.GTU.AND P0, PT, |R15|, 1.469367938527859385e-39, PT ; @P0 BRA 0x1150 ; DFMA R8, R16, -R8, R12 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R9.reuse, RZ, PT ; LOP3.LUT R11, R9, 0x80000000, R11, 0x48, !PT ; LOP3.LUT R5, R11, R5, RZ, 0xfc, !PT ; @!P0 BRA 0x1150 ; IMAD.MOV R9, RZ, RZ, -R18 ; DMUL.RP R4, R16, R4 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; DFMA R8, R14, -R8, R16 ; LOP3.LUT R11, R5, R11, RZ, 0x3c, !PT ; IADD3 R8, -R18, -0x43300000, RZ ; FSETP.NEU.AND P0, PT, |R9|, R8, PT ; FSEL R14, R4, R14, !P0 ; FSEL R15, R11, R15, !P0 ; BRA 0x1150 ; DSETP.NAN.AND P0, PT, R4, R4, PT ; @P0 BRA 0x1130 ; DSETP.NAN.AND P0, PT, R10, R10, PT ; @P0 BRA 0x1100 ; ISETP.NE.AND P0, PT, R18, R19, PT ; IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; IMAD.MOV.U32 R15, RZ, RZ, -0x80000 ; @!P0 BRA 0x1150 ; ISETP.NE.AND P0, PT, R18, 0x7ff00000, PT ; LOP3.LUT R15, R5, 0x80000000, R11, 0x48, !PT ; ISETP.EQ.OR P0, PT, R19, RZ, !P0 ; @P0 LOP3.LUT R4, R15, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R15, RZ, RZ, R4 ; BRA 0x1150 ; LOP3.LUT R15, R11, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R14, RZ, RZ, R10 ; BRA 0x1150 ; LOP3.LUT R15, R5, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R14, RZ, RZ, R4 ; BSYNC B1 ; IMAD.MOV.U32 R4, RZ, RZ, R0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; IMAD.MOV.U32 R8, RZ, RZ, R14 ; IMAD.MOV.U32 R9, RZ, RZ, R15 ; RET.REL.NODEC R4 0x0 ; DADD R10, -RZ, |R6| ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; ULDC.64 UR6, c[0x0][0x190] ; IMAD.MOV.U32 R18, RZ, RZ, 0x7d2cafe2 ; USHF.L.U32 UR5, UR7, 0x1, URZ ; IMAD.MOV.U32 R19, RZ, RZ, 0x3eb0f5ff ; ULOP3.LUT UR4, UR7, 0xff0fffff, URZ, 0xc0, !UPT ; UISETP.GT.U32.AND UP0, UPT, UR5, -0x2000001, UPT ; SHF.R.U32.HI R26, RZ, 0x14, R11 ; USEL UR5, UR4, UR7, UP0 ; ISETP.NE.AND P2, PT, R26, RZ, PT ; UMOV UR4, UR6 ; @!P2 DMUL R8, R10, 1.80143985094819840000e+16 ; @!P2 IMAD.MOV.U32 R11, RZ, RZ, R9 ; @!P2 LEA.HI R26, R9, 0xffffffca, RZ, 0xc ; @!P2 IMAD.MOV.U32 R10, RZ, RZ, R8 ; IMAD.MOV.U32 R9, RZ, RZ, 0x43300000 ; LOP3.LUT R11, R11, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R12, RZ, RZ, R10 ; IADD3 R8, R26, -0x3ff, RZ ; LOP3.LUT R13, R11, 0x3ff00000, RZ, 0xfc, !PT ; ISETP.GE.U32.AND P3, PT, R13, 0x3ff6a09f, PT ; @P3 IADD3 R11, R13, -0x100000, RZ ; @P3 IADD3 R8, R26, -0x3fe, RZ ; @P3 IMAD.MOV.U32 R13, RZ, RZ, R11 ; LOP3.LUT R8, R8, 0x80000000, RZ, 0x3c, !PT ; DADD R16, R12, 1 ; DADD R12, R12, -1 ; MUFU.RCP64H R15, R17 ; DFMA R10, -R16, R14, 1 ; DFMA R10, R10, R10, R10 ; DFMA R14, R14, R10, R14 ; DMUL R10, R14, R12 ; DFMA R10, R14, R12, R10 ; DMUL R20, R10, R10 ; DADD R16, R12, -R10 ; DFMA R18, R20, R18, c[0x2][0x50] ; DADD R16, R16, R16 ; DFMA R18, R20, R18, c[0x2][0x58] ; DFMA R16, R12, -R10, R16 ; DFMA R18, R20, R18, c[0x2][0x60] ; DMUL R14, R14, R16 ; DFMA R18, R20, R18, c[0x2][0x68] ; DMUL R16, R10, R10 ; DFMA R18, R20, R18, c[0x2][0x70] ; DFMA R24, R10, R10, -R16 ; DFMA R18, R20, R18, c[0x2][0x78] ; DFMA R12, R20, R18, c[0x2][0x80] ; DADD R22, -R12, c[0x2][0x80] ; DFMA R20, R20, R18, R22 ; IADD3 R23, R15, 0x100000, RZ ; IMAD.MOV.U32 R22, RZ, RZ, R14 ; DMUL R18, R10, R16 ; DADD R20, RZ, R20 ; DFMA R22, R10, R22, R24 ; DFMA R24, R10, R16, -R18 ; DADD R20, R20, c[0x2][0x88] ; DFMA R24, R14, R16, R24 ; DADD R16, R12, R20 ; DFMA R22, R10, R22, R24 ; DADD R24, R12, -R16 ; DMUL R12, R16, R18 ; DADD R24, R20, R24 ; DFMA R20, R16, R18, -R12 ; DFMA R20, R16, R22, R20 ; DFMA R24, R24, R18, R20 ; IMAD.MOV.U32 R20, RZ, RZ, 0x69ce2bdf ; IMAD.MOV.U32 R21, RZ, RZ, 0x3e5ade15 ; DADD R18, R12, R24 ; DADD R16, R10, R18 ; DADD R12, R12, -R18 ; DADD R10, R10, -R16 ; DADD R12, R24, R12 ; DADD R10, R18, R10 ; DADD R10, R12, R10 ; DADD R14, R14, R10 ; DADD R10, R8, c[0x2][0x38] ; DADD R12, R16, R14 ; DFMA R8, R10, c[0x2][0x40], R12 ; DADD R16, R16, -R12 ; DFMA R18, -R10, c[0x2][0x40], R8 ; DADD R16, R14, R16 ; IMAD.MOV.U32 R14, RZ, RZ, 0x652b82fe ; DADD R18, -R12, R18 ; IMAD.MOV.U32 R15, RZ, RZ, 0x3ff71547 ; DADD R16, R16, -R18 ; DFMA R16, R10, c[0x2][0x48], R16 ; DADD R10, R8, R16 ; DADD R12, R8, -R10 ; DMUL R8, R10, UR4 ; DADD R12, R16, R12 ; DFMA R10, R10, UR4, -R8 ; DFMA R10, R12, UR4, R10 ; DADD R12, R8, R10 ; DFMA R14, R12, R14, 6.75539944105574400000e+15 ; FSETP.GEU.AND P2, PT, |R13|, 4.1917929649353027344, PT ; DADD R16, R14, -6.75539944105574400000e+15 ; DFMA R18, R16, c[0x2][0x90], R12 ; DFMA R16, R16, c[0x2][0x98], R18 ; DFMA R18, R16, R20, c[0x2][0xa0] ; DFMA R18, R16, R18, c[0x2][0xa8] ; DFMA R18, R16, R18, c[0x2][0xb0] ; DFMA R18, R16, R18, c[0x2][0xb8] ; DFMA R18, R16, R18, c[0x2][0xc0] ; DFMA R18, R16, R18, c[0x2][0xc8] ; DFMA R18, R16, R18, c[0x2][0xd0] ; DFMA R18, R16, R18, c[0x2][0xd8] ; DFMA R18, R16, R18, c[0x2][0xe0] ; DFMA R18, R16, R18, 1 ; DFMA R18, R16, R18, 1 ; IMAD R17, R14, 0x100000, R19 ; IMAD.MOV.U32 R16, RZ, RZ, R18 ; @!P2 BRA 0x1980 ; FSETP.GEU.AND P3, PT, |R13|, 4.2275390625, PT ; DADD R16, R12, +INF ; DSETP.GEU.AND P2, PT, R12, RZ, PT ; FSEL R16, R16, RZ, P2 ; @!P3 LEA.HI R15, R14, R14, RZ, 0x1 ; FSEL R17, R17, RZ, P2 ; @!P3 SHF.R.S32.HI R15, RZ, 0x1, R15 ; @!P3 IMAD.IADD R14, R14, 0x1, -R15 ; @!P3 IMAD R19, R15, 0x100000, R19 ; @!P3 LEA R15, R14, 0x3ff00000, 0x14 ; @!P3 IMAD.MOV.U32 R14, RZ, RZ, RZ ; @!P3 DMUL R16, R18, R14 ; LOP3.LUT R14, R17, 0x7fffffff, RZ, 0xc0, !PT ; DADD R8, R8, -R12 ; ISETP.NE.AND P2, PT, R14, 0x7ff00000, PT ; DADD R8, R10, R8 ; ISETP.EQ.AND P2, PT, R16, RZ, !P2 ; @!P2 DFMA R16, R8, R16, R16 ; IMAD.MOV.U32 R8, RZ, RZ, R0 ; IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; RET.REL.NODEC R8 0x0 ; BRA 0x1a10; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00080d67_00000000-6_03a04df5f71e1ae979c3a9a4d1c5d8d5006e6a23.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2066: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2066: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z56__device_stub__Z26compute_entropy_gpu_kernelPdS_S_iidddiPdS_S_iidddi .type _Z56__device_stub__Z26compute_entropy_gpu_kernelPdS_S_iidddiPdS_S_iidddi, @function _Z56__device_stub__Z26compute_entropy_gpu_kernelPdS_S_iidddiPdS_S_iidddi: .LFB2088: .cfi_startproc endbr64 subq $216, %rsp .cfi_def_cfa_offset 224 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) movq %rdx, 40(%rsp) movl %ecx, 36(%rsp) movl %r8d, 32(%rsp) movsd %xmm0, 24(%rsp) movsd %xmm1, 16(%rsp) movsd %xmm2, 8(%rsp) movl %r9d, 4(%rsp) movq %fs:40, %rax movq %rax, 200(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) leaq 36(%rsp), %rax movq %rax, 152(%rsp) leaq 32(%rsp), %rax movq %rax, 160(%rsp) leaq 24(%rsp), %rax movq %rax, 168(%rsp) leaq 16(%rsp), %rax movq %rax, 176(%rsp) leaq 8(%rsp), %rax movq %rax, 184(%rsp) leaq 4(%rsp), %rax movq %rax, 192(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 200(%rsp), %rax subq %fs:40, %rax jne .L8 addq $216, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 232 pushq 72(%rsp) .cfi_def_cfa_offset 240 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z26compute_entropy_gpu_kernelPdS_S_iidddi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 224 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2088: .size _Z56__device_stub__Z26compute_entropy_gpu_kernelPdS_S_iidddiPdS_S_iidddi, .-_Z56__device_stub__Z26compute_entropy_gpu_kernelPdS_S_iidddiPdS_S_iidddi .globl _Z26compute_entropy_gpu_kernelPdS_S_iidddi .type _Z26compute_entropy_gpu_kernelPdS_S_iidddi, @function _Z26compute_entropy_gpu_kernelPdS_S_iidddi: .LFB2089: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z56__device_stub__Z26compute_entropy_gpu_kernelPdS_S_iidddiPdS_S_iidddi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2089: .size _Z26compute_entropy_gpu_kernelPdS_S_iidddi, .-_Z26compute_entropy_gpu_kernelPdS_S_iidddi .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "CUDA: Start compute_entropy_gpu_wrapper cuda status: %s\n" .align 8 .LC1: .string "CUDA: Start compute_entropy_gpu_wrapper values ntot = %d, irho = %d, ntol = %lf, rgam = %lf, gmaref = %lf \n" .align 8 .LC5: .string "CUDA: End compute_engropy_wrapper cuda status: %s\n" .text .globl compute_entropy_gpu_wrapper_ .type compute_entropy_gpu_wrapper_, @function compute_entropy_gpu_wrapper_: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %rdi, %r13 movq %rsi, (%rsp) movq %rdx, 8(%rsp) movq %rcx, %r14 movq %r8, %rbx movq %r9, %r12 movq 112(%rsp), %r15 call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %ebp movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movsd (%r15), %xmm0 movl (%r12), %ecx movl (%rbx), %edx movq 128(%rsp), %rax movsd (%rax), %xmm2 movq 120(%rsp), %rax movsd (%rax), %xmm1 leaq .LC1(%rip), %rsi movl $2, %edi movl $3, %eax call __printf_chk@PLT movl 0(%r13), %eax pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 divss %xmm1, %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L12 cvttss2sil %xmm0, %edx pxor %xmm1, %xmm1 cvtsi2ssl %edx, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L12: movl %eax, 36(%rsp) movl $1, 40(%rsp) cvttss2sil %xmm3, %eax movl %eax, 24(%rsp) movl $1, 28(%rsp) movl $0, %r9d movl $0, %r8d movq 36(%rsp), %rdx movl $1, %ecx movq 24(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L15 .L13: call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %ebp, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC5(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state movsd (%r15), %xmm0 movl (%rbx), %ecx movq 136(%rsp), %rax movl (%rax), %r9d movq 128(%rsp), %rax movsd (%rax), %xmm2 movq 120(%rsp), %rax movsd (%rax), %xmm1 movl (%r12), %r8d movq %r14, %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z56__device_stub__Z26compute_entropy_gpu_kernelPdS_S_iidddiPdS_S_iidddi jmp .L13 .cfi_endproc .LFE2057: .size compute_entropy_gpu_wrapper_, .-compute_entropy_gpu_wrapper_ .globl _Z69__device_stub__Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_iPdS_idiiiS_iS_S_S_i .type _Z69__device_stub__Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_iPdS_idiiiS_iS_S_S_i, @function _Z69__device_stub__Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_iPdS_idiiiS_iS_S_S_i: .LFB2090: .cfi_startproc endbr64 subq $264, %rsp .cfi_def_cfa_offset 272 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 60(%rsp) movsd %xmm0, 48(%rsp) movl %ecx, 56(%rsp) movl %r8d, 44(%rsp) movl %r9d, 40(%rsp) movq 272(%rsp), %rax movq %rax, 32(%rsp) movq 288(%rsp), %rax movq %rax, 24(%rsp) movq 296(%rsp), %rax movq %rax, 16(%rsp) movq 304(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 248(%rsp) xorl %eax, %eax leaq 72(%rsp), %rax movq %rax, 144(%rsp) leaq 64(%rsp), %rax movq %rax, 152(%rsp) leaq 60(%rsp), %rax movq %rax, 160(%rsp) leaq 48(%rsp), %rax movq %rax, 168(%rsp) leaq 56(%rsp), %rax movq %rax, 176(%rsp) leaq 44(%rsp), %rax movq %rax, 184(%rsp) leaq 40(%rsp), %rax movq %rax, 192(%rsp) leaq 32(%rsp), %rax movq %rax, 200(%rsp) leaq 280(%rsp), %rax movq %rax, 208(%rsp) leaq 24(%rsp), %rax movq %rax, 216(%rsp) leaq 16(%rsp), %rax movq %rax, 224(%rsp) leaq 8(%rsp), %rax movq %rax, 232(%rsp) leaq 312(%rsp), %rax movq %rax, 240(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) movl $1, 104(%rsp) movl $1, 108(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) leaq 88(%rsp), %rcx leaq 80(%rsp), %rdx leaq 108(%rsp), %rsi leaq 96(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L20 .L16: movq 248(%rsp), %rax subq %fs:40, %rax jne .L21 addq $264, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L20: .cfi_restore_state pushq 88(%rsp) .cfi_def_cfa_offset 280 pushq 88(%rsp) .cfi_def_cfa_offset 288 leaq 160(%rsp), %r9 movq 124(%rsp), %rcx movl 132(%rsp), %r8d movq 112(%rsp), %rsi movl 120(%rsp), %edx leaq _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 272 jmp .L16 .L21: call __stack_chk_fail@PLT .cfi_endproc .LFE2090: .size _Z69__device_stub__Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_iPdS_idiiiS_iS_S_S_i, .-_Z69__device_stub__Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_iPdS_idiiiS_iS_S_S_i .globl _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .type _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i, @function _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i: .LFB2091: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 pushq 56(%rsp) .cfi_def_cfa_offset 32 pushq 56(%rsp) .cfi_def_cfa_offset 40 pushq 56(%rsp) .cfi_def_cfa_offset 48 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 56 pushq 56(%rsp) .cfi_def_cfa_offset 64 call _Z69__device_stub__Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_iPdS_idiiiS_iS_S_S_i addq $56, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2091: .size _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i, .-_Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .globl _Z96__device_stub__Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_iPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .type _Z96__device_stub__Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_iPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i, @function _Z96__device_stub__Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_iPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i: .LFB2092: .cfi_startproc endbr64 subq $536, %rsp .cfi_def_cfa_offset 544 movq %rdi, 200(%rsp) movq %rsi, 192(%rsp) movl %edx, 188(%rsp) movsd %xmm0, 176(%rsp) movl %ecx, 184(%rsp) movl %r8d, 172(%rsp) movl %r9d, 168(%rsp) movq 544(%rsp), %rax movq %rax, 160(%rsp) movq 560(%rsp), %rax movq %rax, 152(%rsp) movq 568(%rsp), %rax movq %rax, 144(%rsp) movq 576(%rsp), %rax movq %rax, 136(%rsp) movq 584(%rsp), %rax movq %rax, 128(%rsp) movq 592(%rsp), %rax movq %rax, 120(%rsp) movq 600(%rsp), %rax movq %rax, 112(%rsp) movq 608(%rsp), %rax movq %rax, 104(%rsp) movq 616(%rsp), %rax movq %rax, 96(%rsp) movq 624(%rsp), %rax movq %rax, 88(%rsp) movq 632(%rsp), %rax movq %rax, 80(%rsp) movq 648(%rsp), %rax movq %rax, 72(%rsp) movq 656(%rsp), %rax movq %rax, 64(%rsp) movq 664(%rsp), %rax movq %rax, 56(%rsp) movq 672(%rsp), %rax movq %rax, 48(%rsp) movq 680(%rsp), %rax movq %rax, 40(%rsp) movq 688(%rsp), %rax movq %rax, 32(%rsp) movq 696(%rsp), %rax movq %rax, 24(%rsp) movq 704(%rsp), %rax movq %rax, 16(%rsp) movq 712(%rsp), %rax movq %rax, 8(%rsp) movq 720(%rsp), %rax movq %rax, (%rsp) movq %fs:40, %rax movq %rax, 520(%rsp) xorl %eax, %eax leaq 200(%rsp), %rax movq %rax, 272(%rsp) leaq 192(%rsp), %rax movq %rax, 280(%rsp) leaq 188(%rsp), %rax movq %rax, 288(%rsp) leaq 176(%rsp), %rax movq %rax, 296(%rsp) leaq 184(%rsp), %rax movq %rax, 304(%rsp) leaq 172(%rsp), %rax movq %rax, 312(%rsp) leaq 168(%rsp), %rax movq %rax, 320(%rsp) leaq 160(%rsp), %rax movq %rax, 328(%rsp) leaq 552(%rsp), %rax movq %rax, 336(%rsp) leaq 152(%rsp), %rax movq %rax, 344(%rsp) leaq 144(%rsp), %rax movq %rax, 352(%rsp) leaq 136(%rsp), %rax movq %rax, 360(%rsp) leaq 128(%rsp), %rax movq %rax, 368(%rsp) leaq 120(%rsp), %rax movq %rax, 376(%rsp) leaq 112(%rsp), %rax movq %rax, 384(%rsp) leaq 104(%rsp), %rax movq %rax, 392(%rsp) leaq 96(%rsp), %rax movq %rax, 400(%rsp) leaq 88(%rsp), %rax movq %rax, 408(%rsp) leaq 80(%rsp), %rax movq %rax, 416(%rsp) leaq 640(%rsp), %rax movq %rax, 424(%rsp) leaq 72(%rsp), %rax movq %rax, 432(%rsp) leaq 64(%rsp), %rax movq %rax, 440(%rsp) leaq 56(%rsp), %rax movq %rax, 448(%rsp) leaq 48(%rsp), %rax movq %rax, 456(%rsp) leaq 40(%rsp), %rax movq %rax, 464(%rsp) leaq 32(%rsp), %rax movq %rax, 472(%rsp) leaq 24(%rsp), %rax movq %rax, 480(%rsp) leaq 16(%rsp), %rax movq %rax, 488(%rsp) leaq 8(%rsp), %rax movq %rax, 496(%rsp) movq %rsp, %rax movq %rax, 504(%rsp) leaq 728(%rsp), %rax movq %rax, 512(%rsp) movl $1, 224(%rsp) movl $1, 228(%rsp) movl $1, 232(%rsp) movl $1, 236(%rsp) movl $1, 240(%rsp) movl $1, 244(%rsp) leaq 216(%rsp), %rcx leaq 208(%rsp), %rdx leaq 236(%rsp), %rsi leaq 224(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L28 .L24: movq 520(%rsp), %rax subq %fs:40, %rax jne .L29 addq $536, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L28: .cfi_restore_state pushq 216(%rsp) .cfi_def_cfa_offset 552 pushq 216(%rsp) .cfi_def_cfa_offset 560 leaq 288(%rsp), %r9 movq 252(%rsp), %rcx movl 260(%rsp), %r8d movq 240(%rsp), %rsi movl 248(%rsp), %edx leaq _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 544 jmp .L24 .L29: call __stack_chk_fail@PLT .cfi_endproc .LFE2092: .size _Z96__device_stub__Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_iPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i, .-_Z96__device_stub__Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_iPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .globl _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .type _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i, @function _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i: .LFB2093: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 200(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 pushq 200(%rsp) .cfi_def_cfa_offset 32 pushq 200(%rsp) .cfi_def_cfa_offset 40 pushq 200(%rsp) .cfi_def_cfa_offset 48 pushq 200(%rsp) .cfi_def_cfa_offset 56 pushq 200(%rsp) .cfi_def_cfa_offset 64 pushq 200(%rsp) .cfi_def_cfa_offset 72 pushq 200(%rsp) .cfi_def_cfa_offset 80 pushq 200(%rsp) .cfi_def_cfa_offset 88 pushq 200(%rsp) .cfi_def_cfa_offset 96 pushq 200(%rsp) .cfi_def_cfa_offset 104 movl 200(%rsp), %eax pushq %rax .cfi_def_cfa_offset 112 pushq 200(%rsp) .cfi_def_cfa_offset 120 pushq 200(%rsp) .cfi_def_cfa_offset 128 pushq 200(%rsp) .cfi_def_cfa_offset 136 pushq 200(%rsp) .cfi_def_cfa_offset 144 pushq 200(%rsp) .cfi_def_cfa_offset 152 pushq 200(%rsp) .cfi_def_cfa_offset 160 pushq 200(%rsp) .cfi_def_cfa_offset 168 pushq 200(%rsp) .cfi_def_cfa_offset 176 pushq 200(%rsp) .cfi_def_cfa_offset 184 pushq 200(%rsp) .cfi_def_cfa_offset 192 movl 200(%rsp), %eax pushq %rax .cfi_def_cfa_offset 200 pushq 200(%rsp) .cfi_def_cfa_offset 208 call _Z96__device_stub__Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_iPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i addq $200, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2093: .size _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i, .-_Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .globl _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii .type _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii, @function _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii: .LFB2094: .cfi_startproc endbr64 subq $216, %rsp .cfi_def_cfa_offset 224 movq %rdi, 40(%rsp) movl %esi, 36(%rsp) movq %rdx, 24(%rsp) movl %ecx, 32(%rsp) movq %r8, 16(%rsp) movl %r9d, 12(%rsp) movq %fs:40, %rax movq %rax, 200(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 36(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 32(%rsp), %rax movq %rax, 136(%rsp) leaq 16(%rsp), %rax movq %rax, 144(%rsp) leaq 12(%rsp), %rax movq %rax, 152(%rsp) leaq 224(%rsp), %rax movq %rax, 160(%rsp) leaq 232(%rsp), %rax movq %rax, 168(%rsp) leaq 240(%rsp), %rax movq %rax, 176(%rsp) leaq 248(%rsp), %rax movq %rax, 184(%rsp) leaq 256(%rsp), %rax movq %rax, 192(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L36 .L32: movq 200(%rsp), %rax subq %fs:40, %rax jne .L37 addq $216, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L36: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 232 pushq 56(%rsp) .cfi_def_cfa_offset 240 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z4mxm1PdiS_iS_iiiiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 224 jmp .L32 .L37: call __stack_chk_fail@PLT .cfi_endproc .LFE2094: .size _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii, .-_Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii .globl _Z4mxm1PdiS_iS_iiiiii .type _Z4mxm1PdiS_iS_iiiiii, @function _Z4mxm1PdiS_iS_iiiiii: .LFB2095: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 56 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 64 call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $56, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2095: .size _Z4mxm1PdiS_iS_iiiiii, .-_Z4mxm1PdiS_iS_iiiiii .section .rodata.str1.8 .align 8 .LC7: .string "CUDA: Start entropy_residual_gpu_wrapper cuda status: %s\n" .align 8 .LC8: .string "CUDA: Start entropy_residual_gpu_wrapper values rdt = %lf, stage = %d, lorder= %d,ltot = %d,lxd = %d, lyd = %d, lzd = %d, lx1 = %d,ly1 = %d,lz1 = %d,if3d = %d,nelt = %d \n" .align 8 .LC9: .string "CUDA: entropy_residual_gpu_wrapper after kernel 1cuda status: %s\n" .align 8 .LC10: .string "CUDA: entropy_residual_gpu_wrapper after 1st mxm 1cuda status: %s\n" .align 8 .LC11: .string "CUDA: entropy_residual_gpu_wrapper after for loop mxm 1cuda status: %s\n" .align 8 .LC12: .string "CUDA: entropy_residual_gpu_wrapper after 3rd mxm 1cuda status: %s\n" .align 8 .LC13: .string "CUDA: entropy_residual_gpu_wrapper before flux_div_mini_gpu_kernel cuda status: %s\n" .align 8 .LC14: .string "CUDA: entropy_residual_gpu_wrapper after flux_div_mini_gpu_kernel cuda status: %s\n" .align 8 .LC15: .string "CUDA: End entropy residual_gpu_wrapper cuda status: %s\n" .text .globl entropy_residual_gpu_wrapper_ .type entropy_residual_gpu_wrapper_, @function entropy_residual_gpu_wrapper_: .LFB2058: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $360, %rsp .cfi_def_cfa_offset 416 movq %rdi, 40(%rsp) movq %rsi, 120(%rsp) movq %rdx, 128(%rsp) movq %rcx, 72(%rsp) movq %r8, 80(%rsp) movq %r9, 88(%rsp) movq 416(%rsp), %rax movq %rax, 96(%rsp) movq 424(%rsp), %rbx movq %rbx, 104(%rsp) movq 432(%rsp), %rdx movq %rdx, 8(%rsp) movq 440(%rsp), %r14 movq 448(%rsp), %r13 movq 456(%rsp), %r10 movq %r10, 24(%rsp) movq 464(%rsp), %r10 movq %r10, 48(%rsp) movq 472(%rsp), %r10 movq %r10, 64(%rsp) movq 480(%rsp), %rbp movq 488(%rsp), %r12 movq 496(%rsp), %r15 movq 504(%rsp), %r10 movq %r10, 136(%rsp) movq 512(%rsp), %r10 movq %r10, 144(%rsp) movq 520(%rsp), %r10 movq %r10, 152(%rsp) movq 528(%rsp), %r10 movq %r10, 160(%rsp) movq 536(%rsp), %r10 movq %r10, 168(%rsp) movq 544(%rsp), %r10 movq %r10, 176(%rsp) movq 552(%rsp), %r10 movq %r10, 184(%rsp) movq 560(%rsp), %r10 movq %r10, 192(%rsp) movq 568(%rsp), %r10 movq %r10, 200(%rsp) movq 576(%rsp), %r10 movq %r10, 208(%rsp) movq 584(%rsp), %r10 movq %r10, 56(%rsp) movq 592(%rsp), %rbx movq 600(%rsp), %rcx movq %rcx, 112(%rsp) movq 608(%rsp), %rcx movq %rcx, 16(%rsp) movq %fs:40, %rax movq %rax, 344(%rsp) xorl %eax, %eax call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 96(%rsp), %rax movl (%rax), %ecx movq 88(%rsp), %r11 movl (%r11), %edx movq 80(%rsp), %r11 movsd (%r11), %xmm0 subq $8, %rsp .cfi_def_cfa_offset 424 movl (%rbx), %eax pushq %rax .cfi_def_cfa_offset 432 movq 72(%rsp), %r10 movl (%r10), %eax pushq %rax .cfi_def_cfa_offset 440 movl (%r15), %eax pushq %rax .cfi_def_cfa_offset 448 movl (%r12), %eax pushq %rax .cfi_def_cfa_offset 456 movl 0(%rbp), %eax pushq %rax .cfi_def_cfa_offset 464 movl 0(%r13), %eax pushq %rax .cfi_def_cfa_offset 472 movl (%r14), %eax pushq %rax .cfi_def_cfa_offset 480 movq 72(%rsp), %rsi movl (%rsi), %r9d movq 168(%rsp), %rax movl (%rax), %r8d leaq .LC8(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq 72(%rsp), %rsi movl (%rsi), %eax imull (%r14), %eax movl %eax, %r14d imull 0(%r13), %r14d movl %r14d, 100(%rsp) movl 0(%rbp), %eax imull (%r12), %eax imull (%r15), %eax movl %eax, %r15d addq $64, %rsp .cfi_def_cfa_offset 416 movl %r14d, %eax imull (%rbx), %eax leal (%rax,%rax,2), %esi movslq %esi, %rsi salq $3, %rsi leaq 232(%rsp), %rdi call cudaMalloc@PLT movl %r15d, %esi imull (%rbx), %esi movslq %esi, %rsi salq $3, %rsi leaq 240(%rsp), %rdi call cudaMalloc@PLT movl %r15d, %esi imull (%rbx), %esi movslq %esi, %rsi salq $3, %rsi leaq 248(%rsp), %rdi call cudaMalloc@PLT movl %r15d, %esi imull (%rbx), %esi movslq %esi, %rsi salq $3, %rsi leaq 256(%rsp), %rdi call cudaMalloc@PLT movl %r15d, %esi imull (%rbx), %esi movslq %esi, %rsi salq $3, %rsi leaq 264(%rsp), %rdi call cudaMalloc@PLT movl %r15d, %esi imull (%rbx), %esi movslq %esi, %rsi salq $3, %rsi leaq 272(%rsp), %rdi call cudaMalloc@PLT movl %r15d, %esi imull (%rbx), %esi movslq %esi, %rsi salq $3, %rsi leaq 280(%rsp), %rdi call cudaMalloc@PLT movl %r15d, %esi imull (%rbx), %esi movslq %esi, %rsi salq $3, %rsi leaq 288(%rsp), %rdi call cudaMalloc@PLT movl %r15d, %esi imull (%rbx), %esi movslq %esi, %rsi salq $3, %rsi leaq 296(%rsp), %rdi call cudaMalloc@PLT movl %r15d, %esi imull (%rbx), %esi movslq %esi, %rsi salq $3, %rsi leaq 304(%rsp), %rdi call cudaMalloc@PLT movl %r15d, %esi imull (%rbx), %esi movslq %esi, %rsi salq $3, %rsi leaq 312(%rsp), %rdi call cudaMalloc@PLT movl %r14d, %eax imull (%rbx), %eax leal (%rax,%rax,2), %edx movslq %edx, %rdx salq $3, %rdx movl $0, %esi movq 232(%rsp), %rdi call cudaMemset@PLT movl %r15d, %edx imull (%rbx), %edx movslq %edx, %rdx salq $3, %rdx movl $0, %esi movq 240(%rsp), %rdi call cudaMemset@PLT movl %r15d, %edx imull (%rbx), %edx movslq %edx, %rdx salq $3, %rdx movl $0, %esi movq 248(%rsp), %rdi call cudaMemset@PLT movl %r15d, %edx imull (%rbx), %edx movslq %edx, %rdx salq $3, %rdx movl $0, %esi movq 256(%rsp), %rdi call cudaMemset@PLT movl %r15d, %edx imull (%rbx), %edx movslq %edx, %rdx salq $3, %rdx movl $0, %esi movq 264(%rsp), %rdi call cudaMemset@PLT movl %r15d, %edx imull (%rbx), %edx movslq %edx, %rdx salq $3, %rdx movl $0, %esi movq 272(%rsp), %rdi call cudaMemset@PLT movl %r15d, %edx imull (%rbx), %edx movslq %edx, %rdx salq $3, %rdx movl $0, %esi movq 280(%rsp), %rdi call cudaMemset@PLT movl %r15d, %edx imull (%rbx), %edx movslq %edx, %rdx salq $3, %rdx movl $0, %esi movq 288(%rsp), %rdi call cudaMemset@PLT movl %r15d, %edx imull (%rbx), %edx movslq %edx, %rdx salq $3, %rdx movl $0, %esi movq 296(%rsp), %rdi call cudaMemset@PLT movl %r15d, %edx imull (%rbx), %edx movslq %edx, %rdx salq $3, %rdx movl $0, %esi movq 304(%rsp), %rdi call cudaMemset@PLT movl %r15d, %edx imull (%rbx), %edx movslq %edx, %rdx salq $3, %rdx movl $0, %esi movq 312(%rsp), %rdi call cudaMemset@PLT movq 40(%rsp), %rax movl (%rax), %eax movl %eax, 216(%rsp) pxor %xmm6, %xmm6 cvtsi2ssl %eax, %xmm6 movss %xmm6, 8(%rsp) movq 72(%rsp), %rax pxor %xmm0, %xmm0 cvtsi2ssl (%rax), %xmm0 divss %xmm6, %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L41 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L41: movl 216(%rsp), %eax movl %eax, %r12d movl %eax, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) cvttss2sil %xmm3, %eax movl %eax, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L83 .L42: call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC9(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl 0(%rbp), %eax movl %eax, %ecx imull %eax, %ecx movl %ecx, 48(%rsp) movq 56(%rsp), %rdi cmpl $0, (%rdi) je .L43 imull %ecx, %eax movl %eax, 24(%rsp) movq 40(%rsp), %rcx movl (%rcx), %ecx movl %ecx, 216(%rsp) pxor %xmm7, %xmm7 cvtsi2ssl %eax, %xmm7 movss %xmm7, 64(%rsp) pxor %xmm4, %xmm4 cvtsi2ssl %ecx, %xmm4 movss %xmm4, 8(%rsp) pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 mulss %xmm7, %xmm0 divss %xmm4, %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L44 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L44: movl 216(%rsp), %eax movl %eax, %r12d movl %eax, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) cvttss2sil %xmm3, %eax movl %eax, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L84 .L45: call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC10(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT cmpl $0, 0(%rbp) jle .L46 movl $0, %r14d movl $0, %r13d movl 48(%rsp), %eax pxor %xmm5, %xmm5 cvtsi2ssl %eax, %xmm5 movss %xmm5, 40(%rsp) movl %r15d, 220(%rsp) movl %eax, %r15d jmp .L49 .L83: movq 88(%rsp), %rax movl (%rax), %ecx movq 80(%rsp), %rax movsd (%rax), %xmm0 movq 72(%rsp), %rax movl (%rax), %edx movq 56(%rsp), %rax movl (%rax), %eax pushq %rax .cfi_def_cfa_offset 424 pushq 72(%rsp) .cfi_def_cfa_offset 432 pushq 64(%rsp) .cfi_def_cfa_offset 440 pushq 48(%rsp) .cfi_def_cfa_offset 448 movl 68(%rsp), %eax pushq %rax .cfi_def_cfa_offset 456 pushq 272(%rsp) .cfi_def_cfa_offset 464 movq 152(%rsp), %rax movl (%rax), %r9d movq 144(%rsp), %rax movl (%rax), %r8d movq 176(%rsp), %rsi movq 168(%rsp), %rdi call _Z69__device_stub__Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_iPdS_idiiiS_iS_S_S_i addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L42 .L84: movl 0(%rbp), %ecx subq $8, %rsp .cfi_def_cfa_offset 424 pushq $0 .cfi_def_cfa_offset 432 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 440 pushq $0 .cfi_def_cfa_offset 448 pushq %rax .cfi_def_cfa_offset 456 movl (%rbx), %eax pushq %rax .cfi_def_cfa_offset 464 movl %ecx, %r9d movq 288(%rsp), %r8 movq 160(%rsp), %rdx movl 96(%rsp), %esi movq 280(%rsp), %rdi call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L45 .L47: movl %r12d, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) cvttss2sil %xmm2, %eax movl %eax, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L85 .L48: addl $1, %r13d addl %r15d, %r14d cmpl %r13d, 0(%rbp) jle .L86 .L49: pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 mulss 40(%rsp), %xmm0 divss 8(%rsp), %xmm0 movaps %xmm0, %xmm2 movss .LC6(%rip), %xmm1 andps %xmm0, %xmm1 movss .LC2(%rip), %xmm7 ucomiss %xmm1, %xmm7 jbe .L47 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm2 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm2 addss %xmm2, %xmm1 movss .LC6(%rip), %xmm2 andnps %xmm0, %xmm2 orps %xmm1, %xmm2 jmp .L47 .L85: movl 0(%rbp), %esi movslq %r14d, %r8 salq $3, %r8 movq %r8, %rdx addq 232(%rsp), %rdx subq $8, %rsp .cfi_def_cfa_offset 424 pushq $0 .cfi_def_cfa_offset 432 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 440 pushq %rax .cfi_def_cfa_offset 448 pushq $0 .cfi_def_cfa_offset 456 movl (%rbx), %eax pushq %rax .cfi_def_cfa_offset 464 movl %esi, %r9d addq 296(%rsp), %r8 movl %esi, %ecx movq 64(%rsp), %rdi call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L48 .L86: movl 220(%rsp), %r15d .L46: call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC11(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 mulss 64(%rsp), %xmm0 divss 8(%rsp), %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L50 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L50: movl %r12d, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) cvttss2sil %xmm3, %eax movl %eax, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L87 .L51: call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC12(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 mulss 64(%rsp), %xmm0 divss 8(%rsp), %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L52 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L52: movl %r12d, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) cvttss2sil %xmm3, %eax movl %eax, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L88 .L53: cmpl $0, 0(%rbp) jle .L54 movl $0, %r14d movl $0, %r13d movl 48(%rsp), %eax pxor %xmm3, %xmm3 cvtsi2ssl %eax, %xmm3 movss %xmm3, 40(%rsp) movl %r15d, 220(%rsp) movl %eax, %r15d jmp .L57 .L87: movl 0(%rbp), %esi subq $8, %rsp .cfi_def_cfa_offset 424 pushq $0 .cfi_def_cfa_offset 432 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 440 pushq %rax .cfi_def_cfa_offset 448 pushq $0 .cfi_def_cfa_offset 456 movl (%rbx), %eax pushq %rax .cfi_def_cfa_offset 464 movl 96(%rsp), %r9d movq 304(%rsp), %r8 movl %esi, %ecx movq 280(%rsp), %rdx movq 64(%rsp), %rdi call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L51 .L88: movl (%rbx), %edx movl 0(%rbp), %ecx movl 36(%rsp), %eax imull %edx, %eax cltq movq 232(%rsp), %rsi leaq (%rsi,%rax,8), %rdi subq $8, %rsp .cfi_def_cfa_offset 424 pushq $0 .cfi_def_cfa_offset 432 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 440 pushq $0 .cfi_def_cfa_offset 448 pushq %rax .cfi_def_cfa_offset 456 pushq %rdx .cfi_def_cfa_offset 464 movl %ecx, %r9d movq 312(%rsp), %r8 movq 160(%rsp), %rdx movl 96(%rsp), %esi call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L53 .L55: movl %r12d, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) cvttss2sil %xmm2, %eax movl %eax, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L89 .L56: addl $1, %r13d addl %r15d, %r14d cmpl %r13d, 0(%rbp) jle .L90 .L57: pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 mulss 40(%rsp), %xmm0 divss 8(%rsp), %xmm0 movaps %xmm0, %xmm2 movss .LC6(%rip), %xmm1 andps %xmm0, %xmm1 movss .LC2(%rip), %xmm7 ucomiss %xmm1, %xmm7 jbe .L55 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm2 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm2 addss %xmm2, %xmm1 movss .LC6(%rip), %xmm2 andnps %xmm0, %xmm2 orps %xmm1, %xmm2 jmp .L55 .L89: movl (%rbx), %ecx movl 0(%rbp), %esi movslq %r14d, %rdx movl 36(%rsp), %eax imull %ecx, %eax cltq addq %rdx, %rax movq 232(%rsp), %rdi leaq (%rdi,%rax,8), %rax subq $8, %rsp .cfi_def_cfa_offset 424 pushq $0 .cfi_def_cfa_offset 432 movl 40(%rsp), %edi pushq %rdi .cfi_def_cfa_offset 440 pushq %rdi .cfi_def_cfa_offset 448 pushq $0 .cfi_def_cfa_offset 456 pushq %rcx .cfi_def_cfa_offset 464 movl %esi, %r9d movq 320(%rsp), %rcx leaq (%rcx,%rdx,8), %r8 movl %esi, %ecx movq %rax, %rdx movq 64(%rsp), %rdi call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L56 .L90: movl 220(%rsp), %r15d .L54: pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 mulss 64(%rsp), %xmm0 divss 8(%rsp), %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L58 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L58: movl %r12d, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) cvttss2sil %xmm3, %eax movl %eax, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L91 .L59: pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 mulss 64(%rsp), %xmm0 divss 8(%rsp), %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L60 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L60: movl %r12d, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) cvttss2sil %xmm3, %eax movl %eax, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L92 .L61: cmpl $0, 0(%rbp) jle .L62 movl $0, %r14d movl $0, %r13d movl 48(%rsp), %eax pxor %xmm4, %xmm4 cvtsi2ssl %eax, %xmm4 movss %xmm4, 40(%rsp) movl %r15d, 112(%rsp) movl %eax, %r15d jmp .L65 .L91: movl (%rbx), %edx movl 0(%rbp), %esi movl 36(%rsp), %eax imull %edx, %eax cltq movq 232(%rsp), %rcx leaq (%rcx,%rax,8), %rax subq $8, %rsp .cfi_def_cfa_offset 424 pushq $0 .cfi_def_cfa_offset 432 movl 40(%rsp), %ecx pushq %rcx .cfi_def_cfa_offset 440 pushq %rcx .cfi_def_cfa_offset 448 pushq $0 .cfi_def_cfa_offset 456 pushq %rdx .cfi_def_cfa_offset 464 movl 96(%rsp), %r9d movq 328(%rsp), %r8 movl %esi, %ecx movq %rax, %rdx movq 64(%rsp), %rdi call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L59 .L92: movl (%rbx), %edx movl 0(%rbp), %ecx movl 36(%rsp), %eax imull %edx, %eax addl %eax, %eax cltq movq 232(%rsp), %rsi leaq (%rsi,%rax,8), %rdi subq $8, %rsp .cfi_def_cfa_offset 424 pushq $0 .cfi_def_cfa_offset 432 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 440 pushq $0 .cfi_def_cfa_offset 448 pushq %rax .cfi_def_cfa_offset 456 pushq %rdx .cfi_def_cfa_offset 464 movl %ecx, %r9d movq 336(%rsp), %r8 movq 160(%rsp), %rdx movl 96(%rsp), %esi call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L61 .L63: movl %r12d, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) cvttss2sil %xmm2, %eax movl %eax, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L93 .L64: addl $1, %r13d addl %r15d, %r14d cmpl %r13d, 0(%rbp) jle .L94 .L65: pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 mulss 40(%rsp), %xmm0 divss 8(%rsp), %xmm0 movaps %xmm0, %xmm2 movss .LC6(%rip), %xmm1 andps %xmm0, %xmm1 movss .LC2(%rip), %xmm7 ucomiss %xmm1, %xmm7 jbe .L63 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm2 movss .LC4(%rip), %xmm5 andps %xmm5, %xmm2 addss %xmm2, %xmm1 movss .LC6(%rip), %xmm2 andnps %xmm0, %xmm2 orps %xmm1, %xmm2 jmp .L63 .L93: movl (%rbx), %ecx movl 0(%rbp), %esi movslq %r14d, %rdx movl 36(%rsp), %eax imull %ecx, %eax addl %eax, %eax cltq addq %rdx, %rax movq 232(%rsp), %rdi leaq (%rdi,%rax,8), %rax subq $8, %rsp .cfi_def_cfa_offset 424 pushq $0 .cfi_def_cfa_offset 432 movl 40(%rsp), %edi pushq %rdi .cfi_def_cfa_offset 440 pushq %rdi .cfi_def_cfa_offset 448 pushq $0 .cfi_def_cfa_offset 456 pushq %rcx .cfi_def_cfa_offset 464 movl %esi, %r9d movq 344(%rsp), %rcx leaq (%rcx,%rdx,8), %r8 movl %esi, %ecx movq %rax, %rdx movq 64(%rsp), %rdi call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L64 .L94: movl 112(%rsp), %r15d .L62: pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 mulss 64(%rsp), %xmm0 divss 8(%rsp), %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L66 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L66: cvttss2sil %xmm3, %r13d movl %r12d, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) movl %r13d, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L95 .L68: call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC13(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl 216(%rsp), %eax movl %eax, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) movl %r13d, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L96 .L77: call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC14(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 232(%rsp), %rdi call cudaFree@PLT movq 240(%rsp), %rdi call cudaFree@PLT movq 264(%rsp), %rdi call cudaFree@PLT movq 288(%rsp), %rdi call cudaFree@PLT movq 248(%rsp), %rdi call cudaFree@PLT movq 272(%rsp), %rdi call cudaFree@PLT movq 296(%rsp), %rdi call cudaFree@PLT movq 256(%rsp), %rdi call cudaFree@PLT movq 280(%rsp), %rdi call cudaFree@PLT movq 304(%rsp), %rdi call cudaFree@PLT movq 312(%rsp), %rdi call cudaFree@PLT call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC15(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 344(%rsp), %rax subq %fs:40, %rax jne .L97 addq $360, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L95: .cfi_restore_state movl (%rbx), %edx movl 0(%rbp), %esi movl 36(%rsp), %eax imull %edx, %eax addl %eax, %eax cltq movq 232(%rsp), %rcx leaq (%rcx,%rax,8), %rax subq $8, %rsp .cfi_def_cfa_offset 424 pushq $0 .cfi_def_cfa_offset 432 movl 40(%rsp), %ebx pushq %rbx .cfi_def_cfa_offset 440 pushq %rbx .cfi_def_cfa_offset 448 pushq $0 .cfi_def_cfa_offset 456 pushq %rdx .cfi_def_cfa_offset 464 movl 96(%rsp), %r9d movq 352(%rsp), %r8 movl %esi, %ecx movq %rax, %rdx movq 64(%rsp), %rdi call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L68 .L43: pxor %xmm7, %xmm7 cvtsi2ssl 48(%rsp), %xmm7 movss %xmm7, 24(%rsp) pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 mulss %xmm7, %xmm0 divss 8(%rsp), %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L69 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L69: movl %r12d, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) cvttss2sil %xmm3, %eax movl %eax, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L98 .L70: pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 mulss 24(%rsp), %xmm0 divss 8(%rsp), %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L71 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L71: movl %r12d, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) cvttss2sil %xmm3, %eax movl %eax, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L99 .L72: pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 mulss 24(%rsp), %xmm0 divss 8(%rsp), %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L73 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L73: movl %r12d, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) cvttss2sil %xmm3, %eax movl %eax, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L100 .L74: pxor %xmm0, %xmm0 cvtsi2ssl (%rbx), %xmm0 mulss 24(%rsp), %xmm0 divss 8(%rsp), %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L75 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L75: cvttss2sil %xmm3, %r13d movl %r12d, 332(%rsp) movl $1, 336(%rsp) movl $1, 340(%rsp) movl %r13d, 320(%rsp) movl $1, 324(%rsp) movl $1, 328(%rsp) movl $0, %r9d movl $0, %r8d movq 332(%rsp), %rdx movl $1, %ecx movq 320(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L68 movl (%rbx), %edx movl 0(%rbp), %esi movl 36(%rsp), %eax imull %edx, %eax cltq movq 232(%rsp), %rcx leaq (%rcx,%rax,8), %rax subq $8, %rsp .cfi_def_cfa_offset 424 pushq $0 .cfi_def_cfa_offset 432 movl 64(%rsp), %ebx pushq %rbx .cfi_def_cfa_offset 440 pushq %rbx .cfi_def_cfa_offset 448 pushq $0 .cfi_def_cfa_offset 456 pushq %rdx .cfi_def_cfa_offset 464 movl %esi, %r9d movq 320(%rsp), %r8 movl %esi, %ecx movq %rax, %rdx movq 64(%rsp), %rdi call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L68 .L98: movl 0(%rbp), %esi subq $8, %rsp .cfi_def_cfa_offset 424 pushq $0 .cfi_def_cfa_offset 432 movl 64(%rsp), %eax pushq %rax .cfi_def_cfa_offset 440 pushq $0 .cfi_def_cfa_offset 448 pushq %rax .cfi_def_cfa_offset 456 movl (%rbx), %eax pushq %rax .cfi_def_cfa_offset 464 movl %esi, %r9d movq 288(%rsp), %r8 movl %esi, %ecx movq 160(%rsp), %rdx movq 280(%rsp), %rdi call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L70 .L99: movl 0(%rbp), %esi subq $8, %rsp .cfi_def_cfa_offset 424 pushq $0 .cfi_def_cfa_offset 432 movl 64(%rsp), %eax pushq %rax .cfi_def_cfa_offset 440 pushq %rax .cfi_def_cfa_offset 448 pushq $0 .cfi_def_cfa_offset 456 movl (%rbx), %eax pushq %rax .cfi_def_cfa_offset 464 movl %esi, %r9d movq 296(%rsp), %r8 movl %esi, %ecx movq 280(%rsp), %rdx movq 64(%rsp), %rdi call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L72 .L100: movl (%rbx), %edx movl 0(%rbp), %esi movl 36(%rsp), %eax imull %edx, %eax cltq movq 232(%rsp), %rcx leaq (%rcx,%rax,8), %rdi subq $8, %rsp .cfi_def_cfa_offset 424 pushq $0 .cfi_def_cfa_offset 432 movl 64(%rsp), %eax pushq %rax .cfi_def_cfa_offset 440 pushq $0 .cfi_def_cfa_offset 448 pushq %rax .cfi_def_cfa_offset 456 pushq %rdx .cfi_def_cfa_offset 464 movl %esi, %r9d movq 312(%rsp), %r8 movl %esi, %ecx movq 160(%rsp), %rdx call _Z35__device_stub__Z4mxm1PdiS_iS_iiiiiiPdiS_iS_iiiiii addq $48, %rsp .cfi_def_cfa_offset 416 jmp .L74 .L96: movq 88(%rsp), %rax movl (%rax), %ecx movq 80(%rsp), %rax movsd (%rax), %xmm0 movq 72(%rsp), %rax movl (%rax), %edx movq 56(%rsp), %rax movl (%rax), %eax pushq %rax .cfi_def_cfa_offset 424 pushq 216(%rsp) .cfi_def_cfa_offset 432 pushq 216(%rsp) .cfi_def_cfa_offset 440 pushq 216(%rsp) .cfi_def_cfa_offset 448 pushq 216(%rsp) .cfi_def_cfa_offset 456 pushq 216(%rsp) .cfi_def_cfa_offset 464 pushq 216(%rsp) .cfi_def_cfa_offset 472 pushq 216(%rsp) .cfi_def_cfa_offset 480 pushq 216(%rsp) .cfi_def_cfa_offset 488 pushq 216(%rsp) .cfi_def_cfa_offset 496 pushq 216(%rsp) .cfi_def_cfa_offset 504 pushq %r15 .cfi_def_cfa_offset 512 pushq 408(%rsp) .cfi_def_cfa_offset 520 pushq 408(%rsp) .cfi_def_cfa_offset 528 pushq 408(%rsp) .cfi_def_cfa_offset 536 pushq 408(%rsp) .cfi_def_cfa_offset 544 pushq 408(%rsp) .cfi_def_cfa_offset 552 pushq 408(%rsp) .cfi_def_cfa_offset 560 pushq 408(%rsp) .cfi_def_cfa_offset 568 pushq 408(%rsp) .cfi_def_cfa_offset 576 pushq 408(%rsp) .cfi_def_cfa_offset 584 pushq 408(%rsp) .cfi_def_cfa_offset 592 movl 212(%rsp), %eax pushq %rax .cfi_def_cfa_offset 600 pushq 416(%rsp) .cfi_def_cfa_offset 608 movq 296(%rsp), %rax movl (%rax), %r9d movq 288(%rsp), %rax movl (%rax), %r8d movq 320(%rsp), %rsi movq 312(%rsp), %rdi call _Z96__device_stub__Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_iPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i addq $192, %rsp .cfi_def_cfa_offset 416 jmp .L77 .L97: call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size entropy_residual_gpu_wrapper_, .-entropy_residual_gpu_wrapper_ .globl _Z60__device_stub__Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_PdS_S_S_S_iS_iiiiS_diS_ .type _Z60__device_stub__Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_PdS_S_S_S_iS_iiiiS_diS_, @function _Z60__device_stub__Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_PdS_S_S_S_iS_iiiiS_diS_: .LFB2096: .cfi_startproc endbr64 subq $280, %rsp .cfi_def_cfa_offset 288 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movq %rcx, 48(%rsp) movq %r8, 40(%rsp) movl %r9d, 36(%rsp) movsd %xmm0, 8(%rsp) movq 288(%rsp), %rax movq %rax, 24(%rsp) movq 328(%rsp), %rax movq %rax, 16(%rsp) movq 344(%rsp), %rax movq %rax, (%rsp) movq %fs:40, %rax movq %rax, 264(%rsp) xorl %eax, %eax leaq 72(%rsp), %rax movq %rax, 144(%rsp) leaq 64(%rsp), %rax movq %rax, 152(%rsp) leaq 56(%rsp), %rax movq %rax, 160(%rsp) leaq 48(%rsp), %rax movq %rax, 168(%rsp) leaq 40(%rsp), %rax movq %rax, 176(%rsp) leaq 36(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 296(%rsp), %rax movq %rax, 200(%rsp) leaq 304(%rsp), %rax movq %rax, 208(%rsp) leaq 312(%rsp), %rax movq %rax, 216(%rsp) leaq 320(%rsp), %rax movq %rax, 224(%rsp) leaq 16(%rsp), %rax movq %rax, 232(%rsp) leaq 8(%rsp), %rax movq %rax, 240(%rsp) leaq 336(%rsp), %rax movq %rax, 248(%rsp) movq %rsp, %rax movq %rax, 256(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) movl $1, 104(%rsp) movl $1, 108(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) leaq 88(%rsp), %rcx leaq 80(%rsp), %rdx leaq 108(%rsp), %rsi leaq 96(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L105 .L101: movq 264(%rsp), %rax subq %fs:40, %rax jne .L106 addq $280, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L105: .cfi_restore_state pushq 88(%rsp) .cfi_def_cfa_offset 296 pushq 88(%rsp) .cfi_def_cfa_offset 304 leaq 160(%rsp), %r9 movq 124(%rsp), %rcx movl 132(%rsp), %r8d movq 112(%rsp), %rsi movl 120(%rsp), %edx leaq _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 288 jmp .L101 .L106: call __stack_chk_fail@PLT .cfi_endproc .LFE2096: .size _Z60__device_stub__Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_PdS_S_S_S_iS_iiiiS_diS_, .-_Z60__device_stub__Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_PdS_S_S_S_iS_iiiiS_diS_ .globl _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .type _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_, @function _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_: .LFB2097: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 pushq 72(%rsp) .cfi_def_cfa_offset 24 movl 72(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 pushq 72(%rsp) .cfi_def_cfa_offset 40 movl 72(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 movl 72(%rsp), %eax pushq %rax .cfi_def_cfa_offset 56 movl 72(%rsp), %eax pushq %rax .cfi_def_cfa_offset 64 movl 72(%rsp), %eax pushq %rax .cfi_def_cfa_offset 72 pushq 72(%rsp) .cfi_def_cfa_offset 80 call _Z60__device_stub__Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_PdS_S_S_S_iS_iiiiS_diS_ addq $72, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2097: .size _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_, .-_Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .section .rodata.str1.8 .align 8 .LC16: .string "CUDA: Start wavevisc_gpu_wrapper cuda status: %s\n" .align 8 .LC17: .string "CUDA: Start compute_entropy_gpu_wrapper values nelt= %d,lelt= %d,lx1= %d,ly1= %d, lz1= %d,c_max= %lf,irho= %d \n" .align 8 .LC18: .string "CUDA: End Wavevisc_gpu_wrapper cuda status: %s\n" .text .globl wavevisc_gpu_wrapper_ .type wavevisc_gpu_wrapper_, @function wavevisc_gpu_wrapper_: .LFB2059: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $152, %rsp .cfi_def_cfa_offset 208 movq %rdi, 16(%rsp) movq %rsi, 40(%rsp) movq %rdx, 48(%rsp) movq %rcx, 56(%rsp) movq %r8, 64(%rsp) movq %r9, 72(%rsp) movq 208(%rsp), %rbp movq 216(%rsp), %r12 movq 224(%rsp), %r15 movq 232(%rsp), %r13 movq 240(%rsp), %r14 movq 248(%rsp), %rax movq %rax, 24(%rsp) movq 256(%rsp), %rbx movq %rbx, 80(%rsp) movq 264(%rsp), %rdx movq %rdx, 88(%rsp) movq 272(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC16(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movsd (%rbx), %xmm0 movl (%r12), %ecx movl 0(%rbp), %edx movq 8(%rsp), %rax movl (%rax), %eax pushq %rax .cfi_def_cfa_offset 216 movl (%r14), %eax pushq %rax .cfi_def_cfa_offset 224 movl 0(%r13), %r9d movl (%r15), %r8d leaq .LC17(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl 0(%rbp), %esi movl (%r15), %ebx movl 0(%r13), %ecx movl (%r14), %edx movl %esi, %r10d imull %ebx, %r10d movl %r10d, %eax imull %ecx, %eax imull %edx, %eax movl %eax, 48(%rsp) imull %ecx, %ebx imull %edx, %ebx movl (%r12), %edx movl %edx, 52(%rsp) addq $16, %rsp .cfi_def_cfa_offset 208 imull %ebx, %esi movslq %esi, %rsi salq $3, %rsi leaq 96(%rsp), %rdi call cudaMalloc@PLT movl %ebx, %esi imull 0(%rbp), %esi movslq %esi, %rsi salq $3, %rsi leaq 104(%rsp), %rdi call cudaMalloc@PLT movl %ebx, %edx imull 0(%rbp), %edx movslq %edx, %rdx salq $3, %rdx movq 8(%rsp), %rcx movl (%rcx), %eax subl $1, %eax imull (%r12), %eax imull %ebx, %eax cltq movq 24(%rsp), %rcx leaq (%rcx,%rax,8), %rsi movl $3, %ecx movq 104(%rsp), %rdi call cudaMemcpy@PLT movq 16(%rsp), %rcx movl (%rcx), %eax pxor %xmm0, %xmm0 cvtsi2ssl 32(%rsp), %xmm0 pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 divss %xmm1, %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L110 cvttss2sil %xmm0, %edx pxor %xmm1, %xmm1 cvtsi2ssl %edx, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L110: movl %eax, 124(%rsp) movl $1, 128(%rsp) cvttss2sil %xmm3, %eax movl %eax, 112(%rsp) movl $1, 116(%rsp) movl $0, %r9d movl $0, %r8d movq 124(%rsp), %rdx movl $1, %ecx movq 112(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L114 .L111: movq 96(%rsp), %rdi call cudaFree@PLT movq 104(%rsp), %rdi call cudaFree@PLT call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC18(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 136(%rsp), %rax subq %fs:40, %rax jne .L115 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L114: .cfi_restore_state movq 80(%rsp), %rax movsd (%rax), %xmm0 pushq 88(%rsp) .cfi_def_cfa_offset 216 movl 44(%rsp), %eax imull %ebx, %eax pushq %rax .cfi_def_cfa_offset 224 pushq 120(%rsp) .cfi_def_cfa_offset 232 movl (%r14), %eax pushq %rax .cfi_def_cfa_offset 240 movl 0(%r13), %eax pushq %rax .cfi_def_cfa_offset 248 movl (%r15), %eax pushq %rax .cfi_def_cfa_offset 256 pushq %rbx .cfi_def_cfa_offset 264 pushq 152(%rsp) .cfi_def_cfa_offset 272 movl 96(%rsp), %r9d movq 136(%rsp), %r8 movq 128(%rsp), %rcx movq 120(%rsp), %rdx movq 112(%rsp), %rsi movq 104(%rsp), %rdi call _Z60__device_stub__Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_PdS_S_S_S_iS_iiiiS_diS_ addq $64, %rsp .cfi_def_cfa_offset 208 jmp .L111 .L115: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size wavevisc_gpu_wrapper_, .-wavevisc_gpu_wrapper_ .globl _Z58__device_stub__Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_iPdiiiiiiiS_S_S_i .type _Z58__device_stub__Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_iPdiiiiiiiS_S_S_i, @function _Z58__device_stub__Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_iPdiiiiiiiS_S_S_i: .LFB2098: .cfi_startproc endbr64 subq $248, %rsp .cfi_def_cfa_offset 256 movq %rdi, 56(%rsp) movl %esi, 52(%rsp) movl %edx, 48(%rsp) movl %ecx, 44(%rsp) movl %r8d, 40(%rsp) movl %r9d, 36(%rsp) movq 272(%rsp), %rax movq %rax, 24(%rsp) movq 280(%rsp), %rax movq %rax, 16(%rsp) movq 288(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 232(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 52(%rsp), %rax movq %rax, 136(%rsp) leaq 48(%rsp), %rax movq %rax, 144(%rsp) leaq 44(%rsp), %rax movq %rax, 152(%rsp) leaq 40(%rsp), %rax movq %rax, 160(%rsp) leaq 36(%rsp), %rax movq %rax, 168(%rsp) leaq 256(%rsp), %rax movq %rax, 176(%rsp) leaq 264(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 8(%rsp), %rax movq %rax, 208(%rsp) leaq 296(%rsp), %rax movq %rax, 216(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L120 .L116: movq 232(%rsp), %rax subq %fs:40, %rax jne .L121 addq $248, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L120: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 264 pushq 72(%rsp) .cfi_def_cfa_offset 272 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 256 jmp .L116 .L121: call __stack_chk_fail@PLT .cfi_endproc .LFE2098: .size _Z58__device_stub__Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_iPdiiiiiiiS_S_S_i, .-_Z58__device_stub__Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_iPdiiiiiiiS_S_S_i .globl _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .type _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i, @function _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i: .LFB2099: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 pushq 56(%rsp) .cfi_def_cfa_offset 32 pushq 56(%rsp) .cfi_def_cfa_offset 40 pushq 56(%rsp) .cfi_def_cfa_offset 48 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 56 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 64 call _Z58__device_stub__Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_iPdiiiiiiiS_S_S_i addq $56, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2099: .size _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i, .-_Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .section .rodata.str1.8 .align 8 .LC19: .string "CUDA: Start max_to_trilin_gpu_wrapper cuda status: %s\n" .align 8 .LC20: .string "CUDA: Start compute_entropy_gpu_wrapper values nelt=%d,lelt=%d,lx1=%d,ly1=%d,lz1=%d,if3d=%d \n" .align 8 .LC21: .string "CUDA: End max_to_trilin_gpu_wrapper cuda status: %s\n" .text .globl max_to_trilin_gpu_wrapper_ .type max_to_trilin_gpu_wrapper_, @function max_to_trilin_gpu_wrapper_: .LFB2060: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsp, %rbp .cfi_def_cfa_register 6 pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $72, %rsp .cfi_offset 15, -24 .cfi_offset 14, -32 .cfi_offset 13, -40 .cfi_offset 12, -48 .cfi_offset 3, -56 movq %rdi, -88(%rbp) movq %rsi, -104(%rbp) movq %rdx, %r13 movq %rcx, %r12 movq %r8, %r15 movq %r8, -112(%rbp) movq %r9, %rbx movq 16(%rbp), %r14 call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC19(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl (%r12), %ecx movl 0(%r13), %edx movq 48(%rbp), %rax movl (%rax), %eax pushq %rax movl (%r14), %eax pushq %rax movl (%rbx), %r9d movl (%r15), %r8d leaq .LC20(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl (%r15), %r15d movl (%rbx), %esi movl %esi, -92(%rbp) movl (%r14), %ecx movl %ecx, -96(%rbp) movl %r15d, %eax imull 0(%r13), %eax imull %esi, %eax imull %eax, %ecx movl %ecx, %r13d movl (%r12), %r12d movq -88(%rbp), %rax movl (%rax), %eax pxor %xmm0, %xmm0 cvtsi2ssl %ecx, %xmm0 pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 divss %xmm1, %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L125 cvttss2sil %xmm0, %edx pxor %xmm1, %xmm1 cvtsi2ssl %edx, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L125: movl %eax, -60(%rbp) movl $1, -56(%rbp) cvttss2sil %xmm3, %eax movl %eax, -72(%rbp) movl $1, -68(%rbp) addq $16, %rsp movl $0, %r9d movl $0, %r8d movq -60(%rbp), %rdx movl $1, %ecx movq -72(%rbp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L128 .L126: call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC21(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq -40(%rbp), %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 popq %rbp .cfi_remember_state .cfi_def_cfa 7, 8 ret .L128: .cfi_restore_state movl -92(%rbp), %edx imull %r15d, %edx movl -96(%rbp), %eax imull %eax, %edx movq -112(%rbp), %rax movl (%rax), %ecx movl (%rbx), %r8d movq 48(%rbp), %rax movl (%rax), %eax pushq %rax pushq 40(%rbp) pushq 32(%rbp) pushq 24(%rbp) movl %ecx, %eax imull %r8d, %eax pushq %rax imull %edx, %r12d pushq %r12 movl (%r14), %r9d movl %r13d, %esi movq -104(%rbp), %rdi call _Z58__device_stub__Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_iPdiiiiiiiS_S_S_i addq $48, %rsp jmp .L126 .cfi_endproc .LFE2060: .size max_to_trilin_gpu_wrapper_, .-max_to_trilin_gpu_wrapper_ .globl _Z48__device_stub__Z19resvisc_gpu_kernel1PdiiiiiiiS_PdiiiiiiiS_ .type _Z48__device_stub__Z19resvisc_gpu_kernel1PdiiiiiiiS_PdiiiiiiiS_, @function _Z48__device_stub__Z19resvisc_gpu_kernel1PdiiiiiiiS_PdiiiiiiiS_: .LFB2100: .cfi_startproc endbr64 subq $200, %rsp .cfi_def_cfa_offset 208 movq %rdi, 40(%rsp) movl %esi, 36(%rsp) movl %edx, 32(%rsp) movl %ecx, 28(%rsp) movl %r8d, 24(%rsp) movl %r9d, 20(%rsp) movq 224(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 36(%rsp), %rax movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 28(%rsp), %rax movq %rax, 136(%rsp) leaq 24(%rsp), %rax movq %rax, 144(%rsp) leaq 20(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) leaq 8(%rsp), %rax movq %rax, 176(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L133 .L129: movq 184(%rsp), %rax subq %fs:40, %rax jne .L134 addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L133: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 216 pushq 56(%rsp) .cfi_def_cfa_offset 224 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z19resvisc_gpu_kernel1PdiiiiiiiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 208 jmp .L129 .L134: call __stack_chk_fail@PLT .cfi_endproc .LFE2100: .size _Z48__device_stub__Z19resvisc_gpu_kernel1PdiiiiiiiS_PdiiiiiiiS_, .-_Z48__device_stub__Z19resvisc_gpu_kernel1PdiiiiiiiS_PdiiiiiiiS_ .globl _Z19resvisc_gpu_kernel1PdiiiiiiiS_ .type _Z19resvisc_gpu_kernel1PdiiiiiiiS_, @function _Z19resvisc_gpu_kernel1PdiiiiiiiS_: .LFB2101: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 pushq 40(%rsp) .cfi_def_cfa_offset 32 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 call _Z48__device_stub__Z19resvisc_gpu_kernel1PdiiiiiiiS_PdiiiiiiiS_ addq $40, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2101: .size _Z19resvisc_gpu_kernel1PdiiiiiiiS_, .-_Z19resvisc_gpu_kernel1PdiiiiiiiS_ .section .rodata.str1.8 .align 8 .LC22: .string "CUDA: Start resvisc_gpu_wrapper cuda status: %s\n" .align 8 .LC23: .string "CUDA: Start compute_entropy_gpu_wrapper values nelt= %d,lelt= %d,lx1= %d,ly1= %d,lz1 = %d,\n" .align 8 .LC24: .string "CUDA: End resvisc_gpu_wrapper cuda status: %s\n" .text .globl resvisc_gpu_wrapper1_ .type resvisc_gpu_wrapper1_, @function resvisc_gpu_wrapper1_: .LFB2061: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsp, %rbp .cfi_def_cfa_register 6 pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $72, %rsp .cfi_offset 15, -24 .cfi_offset 14, -32 .cfi_offset 13, -40 .cfi_offset 12, -48 .cfi_offset 3, -56 movq %rdi, -88(%rbp) movq %rsi, -104(%rbp) movq %rdx, %r13 movq %rcx, %r12 movq %r8, %r14 movq %r8, -112(%rbp) movq %r9, %rbx call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC22(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl (%r12), %ecx movl 0(%r13), %edx subq $8, %rsp movq 16(%rbp), %rax movl (%rax), %eax pushq %rax movl (%rbx), %r9d movl (%r14), %r8d leaq .LC23(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl (%r14), %r14d movl (%rbx), %r15d movq 16(%rbp), %rax movl (%rax), %ecx movl %ecx, -92(%rbp) movl %r14d, %eax imull 0(%r13), %eax imull %r15d, %eax imull %eax, %ecx movl %ecx, %r13d movl (%r12), %r12d movq -88(%rbp), %rax movl (%rax), %eax pxor %xmm0, %xmm0 cvtsi2ssl %ecx, %xmm0 pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 divss %xmm1, %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L138 cvttss2sil %xmm0, %edx pxor %xmm1, %xmm1 cvtsi2ssl %edx, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L138: movl %eax, -60(%rbp) movl $1, -56(%rbp) cvttss2sil %xmm3, %eax movl %eax, -72(%rbp) movl $1, -68(%rbp) addq $16, %rsp movl $0, %r9d movl $0, %r8d movq -60(%rbp), %rdx movl $1, %ecx movq -72(%rbp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L141 .L139: call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC24(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq -40(%rbp), %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 popq %rbp .cfi_remember_state .cfi_def_cfa 7, 8 ret .L141: .cfi_restore_state movl %r14d, %edx imull %r15d, %edx movl -92(%rbp), %eax imull %eax, %edx movq -112(%rbp), %rax movl (%rax), %ecx movl (%rbx), %r8d subq $8, %rsp pushq 24(%rbp) movl %ecx, %eax imull %r8d, %eax pushq %rax imull %edx, %r12d pushq %r12 movq 16(%rbp), %rax movl (%rax), %r9d movl %r13d, %esi movq -104(%rbp), %rdi call _Z48__device_stub__Z19resvisc_gpu_kernel1PdiiiiiiiS_PdiiiiiiiS_ addq $32, %rsp jmp .L139 .cfi_endproc .LFE2061: .size resvisc_gpu_wrapper1_, .-resvisc_gpu_wrapper1_ .globl _Z48__device_stub__Z19resvisc_gpu_kernel2PdiiiiiiiddPdiiiiiiidd .type _Z48__device_stub__Z19resvisc_gpu_kernel2PdiiiiiiiddPdiiiiiiidd, @function _Z48__device_stub__Z19resvisc_gpu_kernel2PdiiiiiiiddPdiiiiiiidd: .LFB2102: .cfi_startproc endbr64 subq $216, %rsp .cfi_def_cfa_offset 224 movq %rdi, 40(%rsp) movl %esi, 36(%rsp) movl %edx, 32(%rsp) movl %ecx, 28(%rsp) movl %r8d, 24(%rsp) movl %r9d, 20(%rsp) movsd %xmm0, 8(%rsp) movsd %xmm1, (%rsp) movq %fs:40, %rax movq %rax, 200(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 36(%rsp), %rax movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 28(%rsp), %rax movq %rax, 136(%rsp) leaq 24(%rsp), %rax movq %rax, 144(%rsp) leaq 20(%rsp), %rax movq %rax, 152(%rsp) leaq 224(%rsp), %rax movq %rax, 160(%rsp) leaq 232(%rsp), %rax movq %rax, 168(%rsp) leaq 8(%rsp), %rax movq %rax, 176(%rsp) movq %rsp, %rax movq %rax, 184(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L146 .L142: movq 200(%rsp), %rax subq %fs:40, %rax jne .L147 addq $216, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L146: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 232 pushq 56(%rsp) .cfi_def_cfa_offset 240 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z19resvisc_gpu_kernel2Pdiiiiiiidd(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 224 jmp .L142 .L147: call __stack_chk_fail@PLT .cfi_endproc .LFE2102: .size _Z48__device_stub__Z19resvisc_gpu_kernel2PdiiiiiiiddPdiiiiiiidd, .-_Z48__device_stub__Z19resvisc_gpu_kernel2PdiiiiiiiddPdiiiiiiidd .globl _Z19resvisc_gpu_kernel2Pdiiiiiiidd .type _Z19resvisc_gpu_kernel2Pdiiiiiiidd, @function _Z19resvisc_gpu_kernel2Pdiiiiiiidd: .LFB2103: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 call _Z48__device_stub__Z19resvisc_gpu_kernel2PdiiiiiiiddPdiiiiiiidd addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2103: .size _Z19resvisc_gpu_kernel2Pdiiiiiiidd, .-_Z19resvisc_gpu_kernel2Pdiiiiiiidd .section .rodata.str1.8 .align 8 .LC25: .string "CUDA: Start resvisc_gpu_wrapper2 cuda status: %s\n" .align 8 .LC26: .string "CUDA: Start compute_entropy_gpu_wrapper values nelt=%d,lelt=%d,lx1=%d,ly1=%d,lz1=%d,c_sub_e=%lf,maxdiff= %.20lf, \n" .align 8 .LC27: .string "CUDA: End resvisc_gpu_wrapper2 cuda status: %s\n" .text .globl resvisc_gpu_wrapper2_ .type resvisc_gpu_wrapper2_, @function resvisc_gpu_wrapper2_: .LFB2062: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsp, %rbp .cfi_def_cfa_register 6 pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $72, %rsp .cfi_offset 15, -24 .cfi_offset 14, -32 .cfi_offset 13, -40 .cfi_offset 12, -48 .cfi_offset 3, -56 movq %rdi, -88(%rbp) movq %rsi, -112(%rbp) movq %rdx, %r14 movq %rcx, %rbx movq %r8, %r13 movq %r9, %r12 call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC25(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 24(%rbp), %rax movsd (%rax), %xmm0 movl (%rbx), %ecx movq %r14, -96(%rbp) movl (%r14), %edx subq $8, %rsp movq 16(%rbp), %rax movl (%rax), %eax pushq %rax movq 32(%rbp), %rax movsd (%rax), %xmm1 movl (%r12), %r9d movl 0(%r13), %r8d leaq .LC26(%rip), %rsi movl $2, %edi movl $2, %eax call __printf_chk@PLT movl 0(%r13), %eax movl %eax, -100(%rbp) movl (%r12), %r15d movq 16(%rbp), %rsi movl (%rsi), %r14d movq -96(%rbp), %rcx imull (%rcx), %eax imull %r15d, %eax imull %r14d, %eax movl %eax, %ecx movl %eax, -96(%rbp) movl (%rbx), %ebx movq -88(%rbp), %rax movl (%rax), %eax pxor %xmm0, %xmm0 cvtsi2ssl %ecx, %xmm0 pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 divss %xmm1, %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L151 cvttss2sil %xmm0, %edx pxor %xmm1, %xmm1 cvtsi2ssl %edx, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L151: movl %eax, -60(%rbp) movl $1, -56(%rbp) cvttss2sil %xmm3, %eax movl %eax, -72(%rbp) movl $1, -68(%rbp) addq $16, %rsp movl $0, %r9d movl $0, %r8d movq -60(%rbp), %rdx movl $1, %ecx movq -72(%rbp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L154 .L152: call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC27(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq -40(%rbp), %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 popq %rbp .cfi_remember_state .cfi_def_cfa 7, 8 ret .L154: .cfi_restore_state movl -100(%rbp), %edx imull %r15d, %edx imull %r14d, %edx movl 0(%r13), %ecx movl (%r12), %r8d movq 24(%rbp), %rax movsd (%rax), %xmm0 movl %ecx, %eax imull %r8d, %eax pushq %rax imull %edx, %ebx pushq %rbx movq 32(%rbp), %rax movsd (%rax), %xmm1 movq 16(%rbp), %rax movl (%rax), %r9d movl -96(%rbp), %esi movq -112(%rbp), %rdi call _Z48__device_stub__Z19resvisc_gpu_kernel2PdiiiiiiiddPdiiiiiiidd addq $16, %rsp jmp .L152 .cfi_endproc .LFE2062: .size resvisc_gpu_wrapper2_, .-resvisc_gpu_wrapper2_ .globl _Z60__device_stub__Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_iPdS_iiiiiiiiiiiiiidS_i .type _Z60__device_stub__Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_iPdS_iiiiiiiiiiiiiidS_i, @function _Z60__device_stub__Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_iPdS_iiiiiiiiiiiiiidS_i: .LFB2104: .cfi_startproc endbr64 subq $280, %rsp .cfi_def_cfa_offset 288 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movl %edx, 28(%rsp) movl %ecx, 24(%rsp) movl %r8d, 20(%rsp) movl %r9d, 16(%rsp) movsd %xmm0, 8(%rsp) movq 368(%rsp), %rax movq %rax, (%rsp) movq %fs:40, %rax movq %rax, 264(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 28(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 20(%rsp), %rax movq %rax, 144(%rsp) leaq 16(%rsp), %rax movq %rax, 152(%rsp) leaq 288(%rsp), %rax movq %rax, 160(%rsp) leaq 296(%rsp), %rax movq %rax, 168(%rsp) leaq 304(%rsp), %rax movq %rax, 176(%rsp) leaq 312(%rsp), %rax movq %rax, 184(%rsp) leaq 320(%rsp), %rax movq %rax, 192(%rsp) leaq 328(%rsp), %rax movq %rax, 200(%rsp) leaq 336(%rsp), %rax movq %rax, 208(%rsp) leaq 344(%rsp), %rax movq %rax, 216(%rsp) leaq 352(%rsp), %rax movq %rax, 224(%rsp) leaq 360(%rsp), %rax movq %rax, 232(%rsp) leaq 8(%rsp), %rax movq %rax, 240(%rsp) movq %rsp, %rax movq %rax, 248(%rsp) leaq 376(%rsp), %rax movq %rax, 256(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L159 .L155: movq 264(%rsp), %rax subq %fs:40, %rax jne .L160 addq $280, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L159: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 296 pushq 56(%rsp) .cfi_def_cfa_offset 304 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 288 jmp .L155 .L160: call __stack_chk_fail@PLT .cfi_endproc .LFE2104: .size _Z60__device_stub__Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_iPdS_iiiiiiiiiiiiiidS_i, .-_Z60__device_stub__Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_iPdS_iiiiiiiiiiiiiidS_i .globl _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .type _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i, @function _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i: .LFB2105: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 pushq 104(%rsp) .cfi_def_cfa_offset 32 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 56 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 64 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 72 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 80 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 88 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 96 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 104 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 112 call _Z60__device_stub__Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_iPdS_iiiiiiiiiiiiiidS_i addq $104, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2105: .size _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i, .-_Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .section .rodata.str1.8 .align 8 .LC28: .string "CUDA: Start evnsmooth_gpu_wrapper cuda status: %s\n" .align 8 .LC29: .string "CUDA: Start compute_entropy_gpu_wrapper values nelt =%d ,lelt=%d,lx1=%d,ly1=%d,lz1=%d,kstart=%d,kend=%d,jstart=%d,jend=%d,istart=%d,iend=%d,ldim=%d ,rldim=%lf,if3d=%d,\n" .align 8 .LC30: .string "CUDA: End evnsmooth_gpu_wrapper cuda status: %s\n" .text .globl evnsmooth_gpu_wrapper_ .type evnsmooth_gpu_wrapper_, @function evnsmooth_gpu_wrapper_: .LFB2063: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $152, %rsp .cfi_def_cfa_offset 208 movq %rdi, 72(%rsp) movq %rsi, 80(%rsp) movq %rdx, 88(%rsp) movq %rcx, %rbx movq %r8, %r12 movq %r9, %rbp movq 208(%rsp), %r14 movq 216(%rsp), %r13 movq 224(%rsp), %rax movq %rax, 8(%rsp) movq 232(%rsp), %rcx movq %rcx, 16(%rsp) movq 240(%rsp), %rdx movq %rdx, 24(%rsp) movq 248(%rsp), %r11 movq %r11, 32(%rsp) movq 256(%rsp), %r15 movq %r15, 40(%rsp) movq 264(%rsp), %r9 movq %r9, 48(%rsp) movq 272(%rsp), %rcx movq %rcx, 56(%rsp) movq 280(%rsp), %r15 movq 288(%rsp), %rdx movq %rdx, 64(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC28(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movsd (%r15), %xmm0 movl (%r12), %ecx movl (%rbx), %edx subq $8, %rsp .cfi_def_cfa_offset 216 movq 72(%rsp), %rsi movl (%rsi), %eax pushq %rax .cfi_def_cfa_offset 224 movq 72(%rsp), %rdi movl (%rdi), %eax pushq %rax .cfi_def_cfa_offset 232 movq 72(%rsp), %r9 movl (%r9), %eax pushq %rax .cfi_def_cfa_offset 240 movq 72(%rsp), %r8 movl (%r8), %eax pushq %rax .cfi_def_cfa_offset 248 movq 72(%rsp), %r11 movl (%r11), %eax pushq %rax .cfi_def_cfa_offset 256 movq 72(%rsp), %r10 movl (%r10), %eax pushq %rax .cfi_def_cfa_offset 264 movq 72(%rsp), %rsi movl (%rsi), %eax pushq %rax .cfi_def_cfa_offset 272 movq 72(%rsp), %rax movl (%rax), %eax pushq %rax .cfi_def_cfa_offset 280 movl 0(%r13), %eax pushq %rax .cfi_def_cfa_offset 288 movl (%r14), %r9d movl 0(%rbp), %r8d leaq .LC29(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl (%rbx), %esi movl 0(%rbp), %ebx movl (%r14), %ecx movl 0(%r13), %edx movl %esi, %eax imull %ebx, %eax imull %ecx, %eax imull %edx, %eax movl %eax, 84(%rsp) imull %ecx, %ebx imull %edx, %ebx movl (%r12), %r12d addq $80, %rsp .cfi_def_cfa_offset 208 imull %ebx, %esi movslq %esi, %rsi salq $3, %rsi leaq 104(%rsp), %rdi call cudaMalloc@PLT movq 72(%rsp), %rcx movl (%rcx), %eax pxor %xmm0, %xmm0 cvtsi2ssl 4(%rsp), %xmm0 pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 divss %xmm1, %xmm0 movaps %xmm0, %xmm3 movss .LC6(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC2(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L164 cvttss2sil %xmm0, %edx pxor %xmm1, %xmm1 cvtsi2ssl %edx, %xmm1 cmpnless %xmm1, %xmm3 movss .LC4(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L164: movl %eax, 124(%rsp) movl $1, 128(%rsp) cvttss2sil %xmm3, %eax movl %eax, 112(%rsp) movl $1, 116(%rsp) movl $0, %r9d movl $0, %r8d movq 124(%rsp), %rdx movl $1, %ecx movq 112(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L168 .L165: movq 104(%rsp), %rdi call cudaFree@PLT call cudaDeviceSynchronize@PLT call cudaPeekAtLastError@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC30(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 136(%rsp), %rax subq %fs:40, %rax jne .L169 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L168: .cfi_restore_state movl 0(%rbp), %r8d movl (%r14), %r9d movsd (%r15), %xmm0 movq 64(%rsp), %rax movl (%rax), %eax pushq %rax .cfi_def_cfa_offset 216 pushq 112(%rsp) .cfi_def_cfa_offset 224 movq 72(%rsp), %rax movl (%rax), %eax pushq %rax .cfi_def_cfa_offset 232 movq 72(%rsp), %rax movl (%rax), %eax subl $1, %eax pushq %rax .cfi_def_cfa_offset 240 movq 72(%rsp), %rax movl (%rax), %eax subl $1, %eax pushq %rax .cfi_def_cfa_offset 248 movq 72(%rsp), %rax movl (%rax), %eax subl $1, %eax pushq %rax .cfi_def_cfa_offset 256 movq 72(%rsp), %rax movl (%rax), %eax subl $1, %eax pushq %rax .cfi_def_cfa_offset 264 movq 72(%rsp), %rax movl (%rax), %eax subl $1, %eax pushq %rax .cfi_def_cfa_offset 272 movq 72(%rsp), %rax movl (%rax), %eax subl $1, %eax pushq %rax .cfi_def_cfa_offset 280 movl %r8d, %eax imull %r9d, %eax pushq %rax .cfi_def_cfa_offset 288 imull %ebx, %r12d pushq %r12 .cfi_def_cfa_offset 296 movl 0(%r13), %eax pushq %rax .cfi_def_cfa_offset 304 movl %ebx, %ecx movl 100(%rsp), %edx movq 184(%rsp), %rsi movq 176(%rsp), %rdi call _Z60__device_stub__Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_iPdS_iiiiiiiiiiiiiidS_i addq $96, %rsp .cfi_def_cfa_offset 208 jmp .L165 .L169: call __stack_chk_fail@PLT .cfi_endproc .LFE2063: .size evnsmooth_gpu_wrapper_, .-evnsmooth_gpu_wrapper_ .section .rodata.str1.8 .align 8 .LC31: .string "_Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i" .align 8 .LC32: .string "_Z19resvisc_gpu_kernel2Pdiiiiiiidd" .align 8 .LC33: .string "_Z19resvisc_gpu_kernel1PdiiiiiiiS_" .align 8 .LC34: .string "_Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i" .align 8 .LC35: .string "_Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_" .section .rodata.str1.1,"aMS",@progbits,1 .LC36: .string "_Z4mxm1PdiS_iS_iiiiii" .section .rodata.str1.8 .align 8 .LC37: .string "_Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i" .align 8 .LC38: .string "_Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i" .align 8 .LC39: .string "_Z26compute_entropy_gpu_kernelPdS_S_iidddi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2107: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC31(%rip), %rdx movq %rdx, %rcx leaq _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC32(%rip), %rdx movq %rdx, %rcx leaq _Z19resvisc_gpu_kernel2Pdiiiiiiidd(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC33(%rip), %rdx movq %rdx, %rcx leaq _Z19resvisc_gpu_kernel1PdiiiiiiiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC34(%rip), %rdx movq %rdx, %rcx leaq _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC35(%rip), %rdx movq %rdx, %rcx leaq _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC36(%rip), %rdx movq %rdx, %rcx leaq _Z4mxm1PdiS_iS_iiiiii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC37(%rip), %rdx movq %rdx, %rcx leaq _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC38(%rip), %rdx movq %rdx, %rcx leaq _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC39(%rip), %rdx movq %rdx, %rcx leaq _Z26compute_entropy_gpu_kernelPdS_S_iidddi(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2107: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC2: .long 1258291200 .align 4 .LC4: .long 1065353216 .align 4 .LC6: .long 2147483647 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z26compute_entropy_gpu_kernelPdS_S_iidddi ; -- Begin function _Z26compute_entropy_gpu_kernelPdS_S_iidddi .globl _Z26compute_entropy_gpu_kernelPdS_S_iidddi .p2align 8 .type _Z26compute_entropy_gpu_kernelPdS_S_iidddi,@function _Z26compute_entropy_gpu_kernelPdS_S_iidddi: ; @_Z26compute_entropy_gpu_kernelPdS_S_iidddi ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x4c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v6 s_cbranch_execz .LBB0_2 ; %bb.1: s_clause 0x3 s_load_b32 s8, s[0:1], 0x1c s_load_b32 s9, s[0:1], 0x38 s_load_b64 s[2:3], s[0:1], 0x10 s_load_b128 s[4:7], s[0:1], 0x20 s_mov_b32 s13, 0x3fd24924 s_mov_b32 s12, 0x924920da s_mov_b32 s15, 0x3fd99999 s_mov_b32 s14, 0x9999999c s_mov_b32 s17, 0x3fe62e42 s_mov_b32 s16, 0xfefa39ef s_mov_b32 s19, 0x3c7abc9e s_mov_b32 s18, 0x3b39803f s_waitcnt lgkmcnt(0) s_add_i32 s8, s8, -1 s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[0:1], null, s8, s9, v[6:7] v_max_f64 v[2:3], s[4:5], s[4:5] s_mov_b32 s5, 0x3fe55555 s_mov_b32 s4, 0x55555555 s_mov_b32 s9, 0x3fbdee67 s_mov_b32 s8, 0x4222de17 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[0:1], 3, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo s_load_b64 s[2:3], s[0:1], 0x30 global_load_b64 v[0:1], v[0:1], off s_waitcnt vmcnt(0) v_max_f64 v[0:1], v[0:1], v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_max_f64 v[0:1], v[0:1], v[2:3] s_waitcnt lgkmcnt(0) v_mov_b32_e32 v2, s3 s_mov_b32 s3, 0x3fba6564 v_cmp_neq_f64_e32 vcc_lo, 1.0, v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v3, 0x3ff00000, v2, vcc_lo v_cndmask_b32_e64 v2, 0, s2, vcc_lo s_mov_b32 s2, 0x968915a9 v_cmp_neq_f64_e32 vcc_lo, 0, v[2:3] v_cndmask_b32_e32 v5, 0x3ff00000, v1, vcc_lo v_cndmask_b32_e32 v4, 0, v0, vcc_lo v_mul_f64 v[0:1], v[0:1], s[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_frexp_mant_f64_e64 v[7:8], |v[4:5]| v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[7:8] v_cndmask_b32_e64 v9, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[7:8], v[7:8], v9 v_add_f64 v[9:10], v[7:8], 1.0 v_add_f64 v[15:16], v[7:8], -1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[11:12], v[9:10] v_add_f64 v[17:18], v[9:10], -1.0 v_add_f64 v[7:8], v[7:8], -v[17:18] s_waitcnt_depctr 0xfff v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], v[13:14], v[11:12], v[11:12] v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], v[13:14], v[11:12], v[11:12] v_mul_f64 v[13:14], v[15:16], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[19:20], v[9:10], v[13:14] v_fma_f64 v[9:10], v[13:14], v[9:10], -v[19:20] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[7:8], v[13:14], v[7:8], v[9:10] v_add_f64 v[9:10], v[19:20], v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[17:18], v[15:16], -v[9:10] v_add_f64 v[19:20], v[9:10], -v[19:20] v_add_f64 v[15:16], v[15:16], -v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[7:8], v[19:20], -v[7:8] v_add_f64 v[9:10], v[15:16], -v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[7:8], v[7:8], v[9:10] v_add_f64 v[7:8], v[17:18], v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[7:8], v[11:12], v[7:8] v_add_f64 v[9:10], v[13:14], v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[11:12], v[9:10], -v[13:14] v_mul_f64 v[13:14], v[9:10], v[9:10] v_add_f64 v[7:8], v[7:8], -v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[11:12], v[9:10], v[9:10], -v[13:14] v_add_f64 v[15:16], v[7:8], v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], v[9:10], v[15:16], v[11:12] v_add_f64 v[15:16], v[13:14], v[11:12] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[17:18], v[15:16], s[8:9], s[2:3] s_mov_b32 s3, 0x3fbe25e4 s_mov_b32 s2, 0x3abe935a v_add_f64 v[13:14], v[15:16], -v[13:14] v_mul_f64 v[23:24], v[9:10], v[15:16] s_mov_b32 s9, 0x3e5ade15 s_mov_b32 s8, 0x6a5dcb37 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3] s_mov_b32 s3, 0x3fc110ef s_mov_b32 s2, 0x47e6c9c2 v_add_f64 v[11:12], v[11:12], -v[13:14] s_delay_alu instid0(VALU_DEP_2) v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3] s_mov_b32 s3, 0x3fc3b13b s_mov_b32 s2, 0xcfa74449 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3] s_mov_b32 s3, 0x3fc745d1 s_mov_b32 s2, 0x71bf3c30 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3] s_mov_b32 s3, 0x3fcc71c7 s_mov_b32 s2, 0x1c7792ce s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3] s_mov_b32 s3, 0xbfe55555 s_mov_b32 s2, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[17:18], v[15:16], v[17:18], s[12:13] s_mov_b32 s12, 0x9b27acf1 v_fma_f64 v[17:18], v[15:16], v[17:18], s[14:15] s_mov_b32 s14, 0x998ef7b6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[19:20], v[15:16], v[17:18] v_fma_f64 v[13:14], v[15:16], v[17:18], -v[19:20] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[13:14], v[11:12], v[17:18], v[13:14] v_add_f64 v[17:18], v[19:20], v[13:14] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[21:22], v[17:18], s[4:5] v_add_f64 v[19:20], v[17:18], -v[19:20] v_add_f64 v[25:26], v[21:22], s[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_add_f64 v[13:14], v[13:14], -v[19:20] v_fma_f64 v[19:20], v[15:16], v[9:10], -v[23:24] s_mov_b32 s3, 0x3c8543b0 s_mov_b32 s2, 0xd5df274d v_add_f64 v[17:18], v[17:18], -v[25:26] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[13:14], v[13:14], s[2:3] v_fma_f64 v[15:16], v[15:16], v[7:8], v[19:20] v_ldexp_f64 v[7:8], v[7:8], 1 s_mov_b32 s3, 0x3ff71547 s_mov_b32 s2, 0x652b82fe s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[13:14], v[13:14], v[17:18] v_fma_f64 v[11:12], v[11:12], v[9:10], v[15:16] v_ldexp_f64 v[9:10], v[9:10], 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[15:16], v[21:22], v[13:14] v_add_f64 v[17:18], v[23:24], v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[19:20], v[21:22], -v[15:16] v_mul_f64 v[21:22], v[17:18], v[15:16] v_add_f64 v[23:24], v[17:18], -v[23:24] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[13:14], v[13:14], v[19:20] v_fma_f64 v[19:20], v[17:18], v[15:16], -v[21:22] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[11:12], v[11:12], -v[23:24] v_fma_f64 v[13:14], v[17:18], v[13:14], v[19:20] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[11:12], v[11:12], v[15:16], v[13:14] v_frexp_exp_i32_f64_e32 v15, v[4:5] v_add_f64 v[13:14], v[21:22], v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_subrev_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo v_cvt_f64_i32_e32 v[15:16], v15 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[17:18], v[9:10], v[13:14] v_add_f64 v[19:20], v[13:14], -v[21:22] v_mul_f64 v[21:22], v[15:16], s[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[9:10], v[17:18], -v[9:10] v_add_f64 v[11:12], v[11:12], -v[19:20] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[19:20], v[15:16], s[16:17], -v[21:22] v_add_f64 v[9:10], v[13:14], -v[9:10] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[7:8], v[7:8], v[11:12] v_fma_f64 v[11:12], v[15:16], s[18:19], v[19:20] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[7:8], v[7:8], v[9:10] v_add_f64 v[9:10], v[21:22], v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[13:14], v[17:18], v[7:8] v_add_f64 v[21:22], v[9:10], -v[21:22] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[15:16], v[9:10], v[13:14] v_add_f64 v[17:18], v[13:14], -v[17:18] v_add_f64 v[11:12], v[11:12], -v[21:22] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[19:20], v[15:16], -v[9:10] v_add_f64 v[7:8], v[7:8], -v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[23:24], v[15:16], -v[19:20] v_add_f64 v[13:14], v[13:14], -v[19:20] v_add_f64 v[17:18], v[11:12], v[7:8] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[9:10], v[9:10], -v[23:24] v_add_f64 v[9:10], v[13:14], v[9:10] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[13:14], v[17:18], -v[11:12] v_add_f64 v[9:10], v[17:18], v[9:10] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[17:18], v[17:18], -v[13:14] v_add_f64 v[7:8], v[7:8], -v[13:14] v_add_f64 v[19:20], v[15:16], v[9:10] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[11:12], v[11:12], -v[17:18] v_add_f64 v[13:14], v[19:20], -v[15:16] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[7:8], v[7:8], v[11:12] v_add_f64 v[9:10], v[9:10], -v[13:14] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[7:8], v[7:8], v[9:10] v_add_f64 v[9:10], v[19:20], v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[11:12], v[9:10], -v[19:20] v_mul_f64 v[13:14], v[2:3], v[9:10] v_add_f64 v[7:8], v[7:8], -v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[9:10], v[2:3], v[9:10], -v[13:14] v_cmp_class_f64_e64 vcc_lo, v[13:14], 0x204 v_fma_f64 v[8:9], v[2:3], v[7:8], v[9:10] v_ashrrev_i32_e32 v7, 31, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[6:7], 3, v[6:7] v_add_f64 v[10:11], v[13:14], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v16, v11, v14 :: v_dual_cndmask_b32 v15, v10, v13 v_add_f64 v[10:11], v[10:11], -v[13:14] v_mul_f64 v[17:18], v[15:16], s[2:3] s_mov_b32 s3, 0xbfe62e42 s_mov_b32 s2, s16 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[8:9], v[8:9], -v[10:11] v_mul_f64 v[10:11], v[2:3], 0.5 v_rndne_f64_e32 v[17:18], v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_fma_f64 v[19:20], v[17:18], s[2:3], v[15:16] s_mov_b32 s3, 0xbc7abc9e s_mov_b32 s2, s18 v_cvt_i32_f64_e32 v12, v[17:18] v_fma_f64 v[19:20], v[17:18], s[2:3], v[19:20] s_mov_b32 s3, 0x3e928af3 s_mov_b32 s2, 0xfca7ab0c s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[21:22], v[19:20], s[8:9], s[2:3] s_mov_b32 s3, 0x3ec71dee s_mov_b32 s2, 0x623fde64 s_load_b128 s[8:11], s[0:1], 0x0 v_cmp_nlt_f64_e64 s0, 0x40900000, v[15:16] v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[15:16] s_delay_alu instid0(VALU_DEP_3) v_fma_f64 v[21:22], v[19:20], v[21:22], s[2:3] s_mov_b32 s3, 0x3efa0199 s_mov_b32 s2, 0x7c89e6b0 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[2:3] s_mov_b32 s3, 0x3f2a01a0 s_mov_b32 s2, 0x14761f6e s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[2:3] s_mov_b32 s3, 0x3f56c16c s_mov_b32 s2, 0x1852b7b0 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[2:3] s_mov_b32 s3, 0x3f811111 s_mov_b32 s2, 0x11122322 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[2:3] s_mov_b32 s3, 0x3fa55555 s_mov_b32 s2, 0x555502a1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[2:3] s_mov_b32 s3, 0x3fc55555 s_mov_b32 s2, 0x55555511 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[2:3] s_mov_b32 s3, 0x3fe00000 s_mov_b32 s2, 11 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[2:3] v_cmp_neq_f64_e64 s2, v[2:3], |v[2:3]| s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[21:22], v[19:20], v[21:22], 1.0 v_fma_f64 v[17:18], v[19:20], v[21:22], 1.0 s_waitcnt lgkmcnt(0) v_add_co_u32 v19, vcc_lo, s10, v6 v_add_co_ci_u32_e32 v20, vcc_lo, s11, v7, vcc_lo v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[15:16]| v_trunc_f64_e32 v[14:15], v[10:11] global_load_b64 v[19:20], v[19:20], off v_ldexp_f64 v[12:13], v[17:18], v12 v_trunc_f64_e32 v[16:17], v[2:3] v_dual_cndmask_b32 v9, 0, v9 :: v_dual_cndmask_b32 v8, 0, v8 s_and_b32 vcc_lo, s1, s0 v_cmp_lt_f64_e64 s3, |v[4:5]|, 1.0 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v13, 0x7ff00000, v13, s0 v_cndmask_b32_e32 v12, 0, v12, vcc_lo v_cmp_neq_f64_e32 vcc_lo, v[14:15], v[10:11] v_cndmask_b32_e64 v13, 0, v13, s1 v_cmp_eq_f64_e64 s1, v[16:17], v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[8:9], v[12:13], v[8:9], v[12:13] v_cmp_class_f64_e64 s0, v[12:13], 0x204 s_and_b32 vcc_lo, s1, vcc_lo v_cndmask_b32_e32 v11, 0x3ff00000, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v9, v9, v13, s0 v_cndmask_b32_e64 v8, v8, v12, s0 v_and_b32_e32 v12, 0x7fffffff, v3 s_xor_b32 s0, s2, s3 v_cmp_gt_f64_e64 s2, 0, v[2:3] v_bfi_b32 v9, 0x7fffffff, v9, v11 v_cndmask_b32_e64 v11, v2, 0, s0 v_cndmask_b32_e64 v12, v12, 0, s0 v_cmp_eq_f64_e64 s0, |v[4:5]|, 1.0 v_cndmask_b32_e64 v10, 0, v8, s1 v_cndmask_b32_e64 v14, 0x7ff80000, v9, s1 v_cmp_gt_f64_e64 s1, 0, v[4:5] v_cmp_eq_f64_e64 s3, 0, v[4:5] v_and_b32_e32 v13, 0x7fffffff, v5 s_delay_alu instid0(VALU_DEP_1) v_cndmask_b32_e64 v12, v12, v13, s0 v_cndmask_b32_e64 v11, v11, v4, s0 v_cmp_class_f64_e64 s0, v[2:3], 0x204 v_cndmask_b32_e64 v9, v9, v14, s1 v_cndmask_b32_e64 v8, v8, v10, s1 v_cmp_class_f64_e64 s1, v[4:5], 0x204 s_xor_b32 s2, s2, s3 v_cndmask_b32_e32 v13, 0, v5, vcc_lo v_cndmask_b32_e64 v10, 0x7ff00000, 0, s2 s_mov_b32 s2, 0xbf559e2b s_delay_alu instid0(VALU_DEP_1) v_bfi_b32 v10, 0x7fffffff, v10, v13 v_cndmask_b32_e64 v8, v8, v11, s0 v_cndmask_b32_e64 v9, v9, v12, s0 s_mov_b32 s0, 0x6b47b09a s_or_b32 vcc_lo, s3, s1 s_mov_b32 s1, 0x3fc38538 v_cndmask_b32_e64 v8, v8, 0, vcc_lo v_cndmask_b32_e32 v9, v9, v10, vcc_lo v_cmp_o_f64_e32 vcc_lo, v[4:5], v[2:3] s_mov_b32 s3, 0x3fc3ab76 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v2, 0, v8, vcc_lo v_cndmask_b32_e32 v3, 0x7ff80000, v9, vcc_lo s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[19:20] v_div_scale_f64 v[12:13], vcc_lo, v[19:20], v[2:3], v[19:20] v_rcp_f64_e32 v[8:9], v[4:5] s_waitcnt_depctr 0xfff v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9] v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9] v_mul_f64 v[10:11], v[12:13], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[4:5], -v[4:5], v[10:11], v[12:13] v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fixup_f64 v[2:3], v[4:5], v[2:3], v[19:20] v_frexp_mant_f64_e32 v[4:5], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[4:5] s_mov_b32 s4, 0x55555780 v_cndmask_b32_e64 v8, 0, 1, vcc_lo v_ldexp_f64 v[4:5], v[4:5], v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[8:9], v[4:5], 1.0 v_add_f64 v[14:15], v[4:5], -1.0 v_rcp_f64_e32 v[10:11], v[8:9] v_add_f64 v[16:17], v[8:9], -1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_f64 v[4:5], v[4:5], -v[16:17] s_waitcnt_depctr 0xfff v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0 v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0 v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[12:13], v[14:15], v[10:11] v_mul_f64 v[18:19], v[8:9], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], v[12:13], v[8:9], -v[18:19] v_fma_f64 v[4:5], v[12:13], v[4:5], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[18:19], v[4:5] v_add_f64 v[16:17], v[14:15], -v[8:9] v_add_f64 v[18:19], v[8:9], -v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[14:15], v[14:15], -v[16:17] v_add_f64 v[4:5], v[18:19], -v[4:5] v_frexp_exp_i32_f64_e32 v18, v[2:3] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[14:15], -v[8:9] v_add_f64 v[4:5], v[4:5], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[4:5], v[16:17], v[4:5] v_mul_f64 v[4:5], v[10:11], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[12:13], v[4:5] v_mul_f64 v[10:11], v[8:9], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_fma_f64 v[14:15], v[10:11], s[2:3], s[0:1] s_mov_b32 s1, 0x3fc7474d s_mov_b32 s0, 0xd7f4df2e v_mul_f64 v[16:17], v[8:9], v[10:11] v_fma_f64 v[14:15], v[10:11], v[14:15], s[0:1] s_mov_b32 s1, 0x3fcc71c0 s_mov_b32 s0, 0x16291751 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[14:15], v[10:11], v[14:15], s[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], v[10:11], v[14:15], s[12:13] v_fma_f64 v[14:15], v[10:11], v[14:15], s[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[10:11], v[10:11], v[14:15], s[4:5] v_ldexp_f64 v[14:15], v[8:9], 1 v_add_f64 v[8:9], v[8:9], -v[12:13] v_mul_f64 v[10:11], v[16:17], v[10:11] v_subrev_co_ci_u32_e32 v16, vcc_lo, 0, v18, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[4:5], v[4:5], -v[8:9] v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x204 v_cvt_f64_i32_e32 v[16:17], v16 v_add_f64 v[12:13], v[14:15], v[10:11] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_ldexp_f64 v[4:5], v[4:5], 1 v_mul_f64 v[18:19], v[16:17], s[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[8:9], v[12:13], -v[14:15] v_fma_f64 v[14:15], v[16:17], s[16:17], -v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[8:9], v[10:11], -v[8:9] v_fma_f64 v[10:11], v[16:17], s[18:19], v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[4:5], v[4:5], v[8:9] v_add_f64 v[8:9], v[18:19], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[14:15], v[12:13], v[4:5] v_add_f64 v[18:19], v[8:9], -v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[16:17], v[8:9], v[14:15] v_add_f64 v[12:13], v[14:15], -v[12:13] v_add_f64 v[10:11], v[10:11], -v[18:19] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[20:21], v[16:17], -v[8:9] v_add_f64 v[4:5], v[4:5], -v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[22:23], v[16:17], -v[20:21] v_add_f64 v[12:13], v[14:15], -v[20:21] v_add_f64 v[14:15], v[10:11], v[4:5] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[8:9], -v[22:23] v_add_f64 v[8:9], v[12:13], v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[12:13], v[14:15], -v[10:11] v_add_f64 v[8:9], v[14:15], v[8:9] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[14:15], v[14:15], -v[12:13] v_add_f64 v[4:5], v[4:5], -v[12:13] v_add_f64 v[18:19], v[16:17], v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[10:11], v[10:11], -v[14:15] v_add_f64 v[12:13], v[18:19], -v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[4:5], v[4:5], v[10:11] v_add_f64 v[8:9], v[8:9], -v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[4:5], v[4:5], v[8:9] v_add_f64 v[4:5], v[18:19], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v5, v5, v3 :: v_dual_cndmask_b32 v4, v4, v2 v_cmp_ngt_f64_e32 vcc_lo, 0, v[2:3] v_cndmask_b32_e32 v5, 0x7ff80000, v5, vcc_lo v_cmp_nge_f64_e32 vcc_lo, 0, v[2:3] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v4, 0, v4, vcc_lo v_cmp_neq_f64_e32 vcc_lo, 0, v[2:3] v_cndmask_b32_e32 v5, 0xfff00000, v5, vcc_lo v_add_co_u32 v2, vcc_lo, s8, v6 v_add_co_ci_u32_e32 v3, vcc_lo, s9, v7, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_mul_f64 v[0:1], v[0:1], v[4:5] global_store_b64 v[2:3], v[0:1], off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z26compute_entropy_gpu_kernelPdS_S_iidddi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 320 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 27 .amdhsa_next_free_sgpr 20 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z26compute_entropy_gpu_kernelPdS_S_iidddi, .Lfunc_end0-_Z26compute_entropy_gpu_kernelPdS_S_iidddi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 3456 ; NumSgprs: 22 ; NumVgprs: 27 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 3 ; NumSGPRsForWavesPerEU: 22 ; NumVGPRsForWavesPerEU: 27 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i ; -- Begin function _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .globl _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .p2align 8 .type _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i,@function _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i: ; @_Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x6c s_load_b32 s3, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB1_3 ; %bb.1: s_clause 0x2 s_load_b128 s[8:11], s[0:1], 0x18 s_load_b32 s5, s[0:1], 0x28 s_load_b128 s[12:15], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_clause 0x2 s_load_b64 s[2:3], s[0:1], 0x30 s_load_b32 s4, s[0:1], 0x38 s_load_b128 s[16:19], s[0:1], 0x40 v_lshlrev_b64 v[4:5], 3, v[1:2] s_waitcnt lgkmcnt(0) s_cmp_eq_u32 s10, 1 s_cselect_b32 s6, s11, 1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[6:7], null, s6, s5, v[1:2] v_add_co_u32 v2, vcc_lo, s12, v4 v_add_co_ci_u32_e32 v3, vcc_lo, s13, v5, vcc_lo s_load_b32 s5, s[0:1], 0x58 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v7, 31, v6 v_lshlrev_b64 v[6:7], 3, v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, s12, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s13, v7, vcc_lo s_clause 0x1 global_load_b64 v[8:9], v[2:3], off global_load_b64 v[6:7], v[6:7], off s_waitcnt lgkmcnt(0) s_cmp_eq_u32 s5, 0 s_waitcnt vmcnt(0) v_add_f64 v[6:7], v[8:9], -v[6:7] v_add_co_u32 v8, vcc_lo, s14, v4 v_add_co_ci_u32_e32 v9, vcc_lo, s15, v5, vcc_lo v_add_co_u32 v10, vcc_lo, s16, v4 v_add_co_ci_u32_e32 v11, vcc_lo, s17, v5, vcc_lo v_mul_f64 v[6:7], v[6:7], s[8:9] global_store_b64 v[8:9], v[6:7], off global_load_b64 v[6:7], v[10:11], off global_load_b64 v[8:9], v[2:3], off s_waitcnt vmcnt(0) v_mul_f64 v[6:7], v[6:7], v[8:9] v_add_co_u32 v8, vcc_lo, s2, v4 v_add_co_ci_u32_e32 v9, vcc_lo, s3, v5, vcc_lo v_add_co_u32 v10, vcc_lo, s18, v4 v_add_co_ci_u32_e32 v11, vcc_lo, s19, v5, vcc_lo global_store_b64 v[8:9], v[6:7], off global_load_b64 v[6:7], v[10:11], off global_load_b64 v[8:9], v[2:3], off s_waitcnt vmcnt(0) v_mul_f64 v[6:7], v[6:7], v[8:9] v_add_nc_u32_e32 v8, s4, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v9, 31, v8 v_lshlrev_b64 v[8:9], 3, v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v8, vcc_lo, s2, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo global_store_b64 v[8:9], v[6:7], off s_cbranch_scc1 .LBB1_3 ; %bb.2: s_load_b64 s[0:1], s[0:1], 0x50 v_lshl_add_u32 v0, s4, 1, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[0:1], 3, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v4, vcc_lo, s0, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo global_load_b64 v[4:5], v[4:5], off global_load_b64 v[2:3], v[2:3], off s_waitcnt vmcnt(0) v_mul_f64 v[2:3], v[4:5], v[2:3] global_store_b64 v[0:1], v[2:3], off .LBB1_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 352 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 20 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i, .Lfunc_end1-_Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 532 ; NumSgprs: 22 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 22 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i ; -- Begin function _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .globl _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .p2align 8 .type _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i,@function _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i: ; @_Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0xfc s_load_b32 s3, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB2_5 ; %bb.1: s_clause 0x1 s_load_b32 s2, s[0:1], 0x90 s_load_b128 s[8:11], s[0:1], 0x98 v_ashrrev_i32_e32 v3, 31, v1 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x40 s_load_b128 s[12:15], s[0:1], 0x58 s_mov_b32 s24, 0 v_add_nc_u32_e32 v4, v1, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_xor_b32_e32 v4, v4, v3 s_waitcnt lgkmcnt(0) s_ashr_i32 s3, s2, 31 s_add_i32 s2, s2, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_xor_b32 s2, s2, s3 v_cvt_f32_u32_e32 v0, s2 s_sub_i32 s3, 0, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v0, v0 s_waitcnt_depctr 0xfff v_mul_f32_e32 v0, 0x4f7ffffe, v0 v_cvt_u32_f32_e32 v0, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, s3, v0 v_mul_hi_u32 v2, v0, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v0, v0, v2 v_mul_hi_u32 v0, v4, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v0, v0, s2 v_sub_nc_u32_e32 v0, v4, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v2, s2, v0 v_cmp_le_u32_e32 vcc_lo, s2, v0 v_cndmask_b32_e32 v0, v0, v2, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v2, s2, v0 v_cmp_le_u32_e32 vcc_lo, s2, v0 s_load_b64 s[2:3], s[0:1], 0xa8 v_cndmask_b32_e32 v0, v0, v2, vcc_lo v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v0, v0, v3 v_lshlrev_b64 v[13:14], 3, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v3, v0, v3 v_ashrrev_i32_e32 v4, 31, v3 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v5, vcc_lo, s2, v13 v_add_co_ci_u32_e32 v6, vcc_lo, s3, v14, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[15:16], 3, v[3:4] v_add_co_u32 v7, vcc_lo, s6, v15 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s7, v16, vcc_lo global_load_b64 v[11:12], v[5:6], off global_load_b64 v[7:8], v[7:8], off v_add_co_u32 v5, vcc_lo, s10, v13 v_add_co_ci_u32_e32 v6, vcc_lo, s11, v14, vcc_lo v_add_co_u32 v9, vcc_lo, s4, v15 v_add_co_ci_u32_e32 v10, vcc_lo, s5, v16, vcc_lo global_load_b64 v[17:18], v[5:6], off global_load_b64 v[19:20], v[9:10], off v_add_co_u32 v5, vcc_lo, s8, v13 v_add_co_ci_u32_e32 v6, vcc_lo, s9, v14, vcc_lo global_load_b64 v[9:10], v[5:6], off s_clause 0x2 s_load_b32 s4, s[0:1], 0xe8 s_load_b64 s[2:3], s[0:1], 0x88 s_load_b128 s[16:19], s[0:1], 0xb8 s_waitcnt lgkmcnt(0) s_cmp_eq_u32 s4, 0 s_waitcnt vmcnt(3) v_mul_f64 v[7:8], v[11:12], v[7:8] s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[11:12], v[17:18], v[19:20], v[7:8] s_cbranch_scc1 .LBB2_6 ; %bb.2: s_clause 0x2 s_load_b64 s[4:5], s[0:1], 0xb0 s_load_b64 s[6:7], s[0:1], 0x50 s_load_b128 s[20:23], s[0:1], 0xd0 s_waitcnt lgkmcnt(0) v_add_co_u32 v17, vcc_lo, s4, v13 v_add_co_ci_u32_e32 v18, vcc_lo, s5, v14, vcc_lo v_add_co_u32 v7, vcc_lo, s6, v15 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v16, vcc_lo s_load_b256 s[4:11], s[0:1], 0x68 global_load_b64 v[19:20], v[17:18], off global_load_b64 v[7:8], v[7:8], off s_waitcnt vmcnt(0) v_fma_f64 v[7:8], v[19:20], v[7:8], v[11:12] s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[19:20], v[9:10], v[7:8] v_add_co_u32 v7, vcc_lo, s2, v13 v_add_co_ci_u32_e32 v8, vcc_lo, s3, v14, vcc_lo v_add_co_u32 v21, vcc_lo, s18, v13 v_add_co_ci_u32_e32 v22, vcc_lo, s19, v14, vcc_lo v_add_co_u32 v23, vcc_lo, s14, v15 v_add_co_ci_u32_e32 v24, vcc_lo, s15, v16, vcc_lo v_add_co_u32 v25, vcc_lo, s16, v13 v_add_co_ci_u32_e32 v26, vcc_lo, s17, v14, vcc_lo v_add_co_u32 v27, vcc_lo, s12, v15 v_add_co_ci_u32_e32 v28, vcc_lo, s13, v16, vcc_lo s_waitcnt lgkmcnt(0) v_add_co_u32 v29, vcc_lo, s4, v15 v_add_co_ci_u32_e32 v30, vcc_lo, s5, v16, vcc_lo s_load_b64 s[4:5], s[0:1], 0xe0 global_store_b64 v[7:8], v[19:20], off global_load_b64 v[21:22], v[21:22], off global_load_b64 v[23:24], v[23:24], off global_load_b64 v[25:26], v[25:26], off global_load_b64 v[27:28], v[27:28], off global_load_b64 v[17:18], v[17:18], off global_load_b64 v[29:30], v[29:30], off global_load_b64 v[31:32], v[5:6], off s_waitcnt vmcnt(5) v_mul_f64 v[21:22], v[21:22], v[23:24] s_waitcnt vmcnt(3) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[21:22], v[25:26], v[27:28], v[21:22] s_waitcnt vmcnt(1) v_fma_f64 v[17:18], v[17:18], v[29:30], v[21:22] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[17:18], v[31:32], v[17:18], v[19:20] v_add_co_u32 v19, vcc_lo, s22, v13 v_add_co_ci_u32_e32 v20, vcc_lo, s23, v14, vcc_lo v_add_co_u32 v21, vcc_lo, s8, v15 v_add_co_ci_u32_e32 v22, vcc_lo, s9, v16, vcc_lo v_add_co_u32 v13, vcc_lo, s20, v13 v_add_co_ci_u32_e32 v14, vcc_lo, s21, v14, vcc_lo v_add_co_u32 v15, vcc_lo, s6, v15 v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo global_store_b64 v[7:8], v[17:18], off global_load_b64 v[19:20], v[19:20], off global_load_b64 v[21:22], v[21:22], off global_load_b64 v[13:14], v[13:14], off global_load_b64 v[15:16], v[15:16], off s_waitcnt vmcnt(2) v_mul_f64 v[19:20], v[19:20], v[21:22] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[13:14], v[13:14], v[15:16], v[19:20] s_and_not1_b32 vcc_lo, exec_lo, s24 s_cbranch_vccnz .LBB2_4 .LBB2_3: s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[17:18], v[9:10], v[11:12] v_lshlrev_b64 v[9:10], 3, v[1:2] v_lshlrev_b64 v[11:12], 3, v[3:4] s_waitcnt lgkmcnt(0) s_mov_b64 s[4:5], s[18:19] s_mov_b64 s[10:11], s[14:15] s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v7, vcc_lo, s2, v9 v_add_co_ci_u32_e32 v8, vcc_lo, s3, v10, vcc_lo v_add_co_u32 v9, vcc_lo, s16, v9 v_add_co_ci_u32_e32 v10, vcc_lo, s17, v10, vcc_lo v_add_co_u32 v11, vcc_lo, s12, v11 v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo global_store_b64 v[7:8], v[17:18], off global_load_b64 v[9:10], v[9:10], off global_load_b64 v[11:12], v[11:12], off s_waitcnt vmcnt(0) v_mul_f64 v[13:14], v[9:10], v[11:12] .LBB2_4: s_waitcnt vmcnt(0) v_lshlrev_b64 v[9:10], 3, v[1:2] v_lshlrev_b64 v[3:4], 3, v[3:4] s_load_b64 s[0:1], s[0:1], 0x8 v_lshlrev_b64 v[0:1], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_3) v_add_co_u32 v9, vcc_lo, s4, v9 v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo v_add_co_u32 v3, vcc_lo, s10, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo global_load_b64 v[9:10], v[9:10], off global_load_b64 v[3:4], v[3:4], off global_load_b64 v[5:6], v[5:6], off s_waitcnt vmcnt(1) v_fma_f64 v[3:4], v[9:10], v[3:4], v[13:14] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[3:4], v[5:6], v[3:4], v[17:18] v_add_co_u32 v5, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v6, vcc_lo, s1, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo global_store_b64 v[7:8], v[3:4], off global_load_b64 v[2:3], v[5:6], off global_load_b64 v[0:1], v[0:1], off s_waitcnt vmcnt(0) v_add_f64 v[0:1], v[2:3], v[0:1] global_store_b64 v[5:6], v[0:1], off .LBB2_5: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .LBB2_6: ; implicit-def: $vgpr7_vgpr8 ; implicit-def: $vgpr17_vgpr18 ; implicit-def: $vgpr13_vgpr14 ; implicit-def: $sgpr10_sgpr11 ; implicit-def: $sgpr4_sgpr5 s_branch .LBB2_3 .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 496 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 33 .amdhsa_next_free_sgpr 25 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end2-_Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1244 ; NumSgprs: 27 ; NumVgprs: 33 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 3 ; VGPRBlocks: 4 ; NumSGPRsForWavesPerEU: 27 ; NumVGPRsForWavesPerEU: 33 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z4mxm1PdiS_iS_iiiiii ; -- Begin function _Z4mxm1PdiS_iS_iiiiii .globl _Z4mxm1PdiS_iS_iiiiii .p2align 8 .type _Z4mxm1PdiS_iS_iiiiii,@function _Z4mxm1PdiS_iS_iiiiii: ; @_Z4mxm1PdiS_iS_iiiiii ; %bb.0: s_clause 0x2 s_load_b32 s4, s[0:1], 0x4c s_load_b32 s5, s[0:1], 0x8 s_load_b64 s[2:3], s[0:1], 0x28 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] s_mul_i32 s4, s2, s5 s_mul_i32 s3, s4, s3 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s3, v1 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB3_4 ; %bb.1: s_ashr_i32 s3, s4, 31 v_ashrrev_i32_e32 v3, 31, v1 s_add_i32 s5, s4, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_xor_b32 s5, s5, s3 v_add_nc_u32_e32 v4, v1, v3 v_cvt_f32_u32_e32 v0, s5 s_sub_i32 s6, 0, s5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v4, v4, v3 v_rcp_iflag_f32_e32 v0, v0 v_xor_b32_e32 v3, s3, v3 s_load_b32 s3, s[0:1], 0x38 s_waitcnt_depctr 0xfff v_mul_f32_e32 v0, 0x4f7ffffe, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v0, v0 v_mul_lo_u32 v2, s6, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v2, v0, v2 v_add_nc_u32_e32 v0, v0, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v0, v4, v0 v_mul_lo_u32 v2, v0, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v2, v4, v2 v_add_nc_u32_e32 v4, 1, v0 v_subrev_nc_u32_e32 v5, s5, v2 v_cmp_le_u32_e32 vcc_lo, s5, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v0, v0, v4, vcc_lo v_cndmask_b32_e32 v2, v2, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v4, 1, v0 v_cmp_le_u32_e32 vcc_lo, s5, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v0, v0, v4, vcc_lo v_xor_b32_e32 v0, v0, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v7, v0, v3 v_mul_lo_u32 v0, v7, s4 s_load_b64 s[4:5], s[0:1], 0x20 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v2, v1, v0 s_waitcnt lgkmcnt(0) v_mad_u64_u32 v[0:1], null, v7, s3, v[2:3] s_load_b32 s3, s[0:1], 0x18 v_mov_b32_e32 v3, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_mov_b32_e32 v4, v3 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[0:1] v_add_co_u32 v0, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s3, 1 global_store_b64 v[0:1], v[3:4], off s_cbranch_scc1 .LBB3_4 ; %bb.2: ; %.lr.ph global_load_b64 v[3:4], v[0:1], off s_ashr_i32 s4, s2, 31 v_ashrrev_i32_e32 v8, 31, v2 s_add_i32 s5, s2, s4 s_load_b32 s8, s[0:1], 0x3c s_xor_b32 s5, s5, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cvt_f32_u32_e32 v5, s5 s_sub_i32 s6, 0, s5 v_add_nc_u32_e32 v9, v2, v8 v_rcp_iflag_f32_e32 v5, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_xor_b32_e32 v9, v9, v8 v_xor_b32_e32 v8, s4, v8 s_waitcnt_depctr 0xfff v_mul_f32_e32 v5, 0x4f7ffffe, v5 v_cvt_u32_f32_e32 v5, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mul_lo_u32 v6, s6, v5 s_load_b64 s[6:7], s[0:1], 0x30 v_mul_hi_u32 v6, v5, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v10, v5, v6 v_mad_u64_u32 v[5:6], null, v9, v10, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v5, v6, s5 v_sub_nc_u32_e32 v5, v9, v5 v_add_nc_u32_e32 v9, 1, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v10, s5, v5 v_cmp_le_u32_e32 vcc_lo, s5, v5 v_dual_cndmask_b32 v6, v6, v9 :: v_dual_cndmask_b32 v5, v5, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v9, 1, v6 v_cmp_le_u32_e32 vcc_lo, s5, v5 s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 v_cndmask_b32_e32 v5, v6, v9, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v5, v5, v8 v_sub_nc_u32_e32 v5, v5, v8 s_waitcnt lgkmcnt(0) v_mul_lo_u32 v8, v7, s6 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_lo_u32 v6, v5, s2 v_mul_lo_u32 v9, v5, s3 v_sub_nc_u32_e32 v2, v2, v6 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_mad_u64_u32 v[5:6], null, v7, s7, v[2:3] v_add3_u32 v7, v8, s8, v9 .p2align 6 .LBB3_3: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_ashrrev_i32_e32 v8, 31, v7 v_ashrrev_i32_e32 v6, 31, v5 s_add_i32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) s_cmp_lg_u32 s3, 0 v_lshlrev_b64 v[8:9], 3, v[7:8] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_lshlrev_b64 v[10:11], 3, v[5:6] v_add_nc_u32_e32 v5, s2, v5 v_add_nc_u32_e32 v7, 1, v7 v_add_co_u32 v8, vcc_lo, s4, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo v_add_co_u32 v10, vcc_lo, s0, v10 v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo global_load_b64 v[8:9], v[8:9], off global_load_b64 v[10:11], v[10:11], off s_waitcnt vmcnt(0) v_fma_f64 v[3:4], v[8:9], v[10:11], v[3:4] global_store_b64 v[0:1], v[3:4], off s_cbranch_scc1 .LBB3_3 .LBB3_4: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z4mxm1PdiS_iS_iiiiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 320 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end3: .size _Z4mxm1PdiS_iS_iiiiii, .Lfunc_end3-_Z4mxm1PdiS_iS_iiiiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 768 ; NumSgprs: 18 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ ; -- Begin function _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .globl _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .p2align 8 .type _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_,@function _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_: ; @_Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x74 s_load_b32 s3, s[0:1], 0x28 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB4_7 ; %bb.1: s_load_b256 s[4:11], s[0:1], 0x8 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[3:4], 3, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v5, vcc_lo, s8, v3 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo v_add_co_u32 v7, vcc_lo, s6, v3 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo global_load_b64 v[5:6], v[5:6], off v_add_co_u32 v9, vcc_lo, s10, v3 global_load_b64 v[7:8], v[7:8], off v_add_co_ci_u32_e32 v10, vcc_lo, s11, v4, vcc_lo v_add_co_u32 v11, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v12, vcc_lo, s5, v4, vcc_lo global_load_b64 v[9:10], v[9:10], off global_load_b64 v[11:12], v[11:12], off s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x30 s_load_b64 s[2:3], s[0:1], 0x40 s_waitcnt lgkmcnt(0) s_mul_i32 s2, s2, s7 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s3, s2, s3 s_ashr_i32 s7, s3, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_add_i32 s3, s3, s7 s_waitcnt vmcnt(3) v_mul_f64 v[5:6], v[5:6], v[5:6] s_waitcnt vmcnt(2) v_fma_f64 v[5:6], v[7:8], v[7:8], v[5:6] s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[5:6], v[9:10], v[9:10], v[5:6] v_cvt_f32_f64_e32 v0, v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f32_e32 v2, 0x4f800000, v0 v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0 v_cndmask_b32_e32 v0, v0, v2, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_sqrt_f32_e32 v2, v0 s_waitcnt_depctr 0xfff v_add_nc_u32_e32 v5, -1, v2 v_add_nc_u32_e32 v6, 1, v2 v_fma_f32 v7, -v5, v2, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v8, -v6, v2, v0 v_cmp_ge_f32_e64 s2, 0, v7 v_ashrrev_i32_e32 v7, 31, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v2, v2, v5, s2 v_cmp_lt_f32_e64 s2, 0, v8 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v8, v1, v7 v_cndmask_b32_e64 v2, v2, v6, s2 s_xor_b32 s2, s3, s7 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) v_xor_b32_e32 v8, v8, v7 v_cvt_f32_u32_e32 v5, s2 s_sub_i32 s3, 0, s2 v_mul_f32_e32 v6, 0x37800000, v2 v_xor_b32_e32 v7, s7, v7 v_rcp_iflag_f32_e32 v5, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v2, v2, v6, vcc_lo v_cmp_class_f32_e64 vcc_lo, v0, 0x260 v_cndmask_b32_e32 v0, v2, v0, vcc_lo s_waitcnt_depctr 0xfff v_mul_f32_e32 v2, 0x4f7ffffe, v5 v_cvt_f64_f32_e32 v[5:6], v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v0, v2 v_mul_lo_u32 v2, s3, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v2, v0, v2 v_add_nc_u32_e32 v0, v0, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v0, v8, v0 v_mul_lo_u32 v2, v0, s2 s_waitcnt vmcnt(0) v_add_f64 v[5:6], v[11:12], v[5:6] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v2, v8, v2 v_add_nc_u32_e32 v8, 1, v0 v_subrev_nc_u32_e32 v9, s2, v2 v_cmp_le_u32_e32 vcc_lo, s2, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v0, v0, v8, vcc_lo v_cndmask_b32_e32 v2, v2, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v8, 1, v0 v_cmp_le_u32_e32 vcc_lo, s2, v2 s_add_i32 s2, s6, 1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) s_cmp_lt_u32 s2, 3 v_cndmask_b32_e32 v0, v0, v8, vcc_lo v_add_co_u32 v3, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v0, v0, v7 v_sub_nc_u32_e32 v2, v0, v7 global_store_b64 v[3:4], v[5:6], off s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB4_6 ; %bb.2: ; %.lr.ph.preheader s_lshr_b32 s2, s6, 31 v_mov_b32_e32 v6, 0 s_add_i32 s2, s6, s2 s_delay_alu instid0(SALU_CYCLE_1) s_ashr_i32 s2, s2, 1 s_set_inst_prefetch_distance 0x1 s_branch .LBB4_4 .p2align 6 .LBB4_3: ; in Loop: Header=BB4_4 Depth=1 s_or_b32 exec_lo, exec_lo, s3 s_lshr_b32 s3, s2, 1 s_cmp_gt_u32 s2, 1 s_mov_b32 s2, s3 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB4_6 .LBB4_4: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_mov_b32 s3, exec_lo v_cmpx_gt_u32_e64 s2, v2 s_cbranch_execz .LBB4_3 ; %bb.5: ; in Loop: Header=BB4_4 Depth=1 v_add_nc_u32_e32 v5, s2, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 3, v[5:6] v_add_co_u32 v7, vcc_lo, s4, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo s_clause 0x1 global_load_b64 v[9:10], v[3:4], off global_load_b64 v[7:8], v[7:8], off s_waitcnt vmcnt(1) v_cvt_f32_f64_e32 v0, v[9:10] s_waitcnt vmcnt(0) v_cvt_f32_f64_e32 v5, v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_max_f32_e32 v0, v0, v5 v_cvt_f64_f32_e32 v[7:8], v0 global_store_b64 v[3:4], v[7:8], off s_branch .LBB4_3 .LBB4_6: ; %._crit_edge s_set_inst_prefetch_distance 0x2 v_sub_nc_u32_e32 v3, v1, v2 s_load_b64 s[2:3], s[0:1], 0x60 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[3:4], 3, v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo global_load_b64 v[4:5], v[3:4], off v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 3, v[2:3] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s2, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_load_b64 v[2:3], v[2:3], off s_clause 0x2 s_load_b64 s[2:3], s[0:1], 0x50 s_load_b32 s4, s[0:1], 0x58 s_load_b64 s[0:1], s[0:1], 0x0 s_waitcnt lgkmcnt(0) v_lshl_add_u32 v0, s4, 1, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[0:1], 3, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(1) v_mul_f64 v[4:5], v[4:5], s[2:3] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[2:3], v[4:5], v[2:3] global_store_b64 v[0:1], v[2:3], off .LBB4_7: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 360 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 13 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end4: .size _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_, .Lfunc_end4-_Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1020 ; NumSgprs: 18 ; NumVgprs: 13 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 13 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i ; -- Begin function _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .globl _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .p2align 8 .type _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i,@function _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i: ; @_Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x54 s_load_b32 s3, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB5_6 ; %bb.1: s_clause 0x1 s_load_b128 s[8:11], s[0:1], 0xc s_load_b64 s[12:13], s[0:1], 0x1c v_ashrrev_i32_e32 v3, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v4, v1, v3 v_xor_b32_e32 v4, v4, v3 s_waitcnt lgkmcnt(0) s_ashr_i32 s2, s8, 31 s_add_i32 s10, s10, -1 s_add_i32 s3, s8, s2 s_lshl_b32 s8, s12, 1 s_xor_b32 s2, s3, s2 s_add_i32 s12, s9, -1 v_cvt_f32_u32_e32 v0, s2 s_sub_i32 s3, 0, s2 s_mul_i32 s10, s10, s9 s_add_i32 s11, s11, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_mul_i32 s9, s11, s13 v_rcp_iflag_f32_e32 v0, v0 s_waitcnt_depctr 0xfff v_mul_f32_e32 v0, 0x4f7ffffe, v0 v_cvt_u32_f32_e32 v0, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, s3, v0 v_mul_hi_u32 v2, v0, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v0, v0, v2 v_mul_hi_u32 v0, v4, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v0, v0, s2 v_sub_nc_u32_e32 v0, v4, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v2, s2, v0 v_cmp_le_u32_e32 vcc_lo, s2, v0 v_cndmask_b32_e32 v0, v0, v2, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_subrev_nc_u32_e32 v2, s2, v0 v_cmp_le_u32_e32 vcc_lo, s2, v0 s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x0 s_load_b128 s[4:7], s[0:1], 0x28 v_cndmask_b32_e32 v0, v0, v2, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v0, v0, v3 v_sub_nc_u32_e32 v0, v3, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v3, v1, v0 v_ashrrev_i32_e32 v4, 31, v3 v_add_nc_u32_e32 v5, s8, v3 v_add_nc_u32_e32 v7, s12, v3 v_add_nc_u32_e32 v9, s10, v3 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[31:32], 3, v[3:4] v_ashrrev_i32_e32 v6, 31, v5 s_delay_alu instid0(VALU_DEP_4) v_ashrrev_i32_e32 v8, 31, v7 v_add_nc_u32_e32 v11, s12, v5 v_add_nc_u32_e32 v13, s10, v5 v_add_nc_u32_e32 v15, s9, v5 v_lshlrev_b64 v[5:6], 3, v[5:6] s_waitcnt lgkmcnt(0) v_add_co_u32 v23, vcc_lo, s4, v31 v_ashrrev_i32_e32 v10, 31, v9 v_add_co_ci_u32_e32 v24, vcc_lo, s5, v32, vcc_lo v_lshlrev_b64 v[7:8], 3, v[7:8] v_add_co_u32 v33, vcc_lo, s6, v31 v_ashrrev_i32_e32 v12, 31, v11 v_add_co_ci_u32_e32 v34, vcc_lo, s7, v32, vcc_lo v_lshlrev_b64 v[9:10], 3, v[9:10] v_add_co_u32 v5, vcc_lo, s2, v5 v_ashrrev_i32_e32 v14, 31, v13 v_add_nc_u32_e32 v17, s12, v13 v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo v_lshlrev_b64 v[11:12], 3, v[11:12] v_add_co_u32 v7, vcc_lo, s4, v7 v_ashrrev_i32_e32 v16, 31, v15 v_add_nc_u32_e32 v19, s12, v15 v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo v_add_nc_u32_e32 v21, s10, v15 v_lshlrev_b64 v[13:14], 3, v[13:14] v_add_co_u32 v29, vcc_lo, s6, v9 v_ashrrev_i32_e32 v18, 31, v17 v_add_co_ci_u32_e32 v30, vcc_lo, s7, v10, vcc_lo v_lshlrev_b64 v[15:16], 3, v[15:16] v_add_co_u32 v11, vcc_lo, s2, v11 v_ashrrev_i32_e32 v20, 31, v19 v_add_nc_u32_e32 v25, s12, v21 v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo v_lshlrev_b64 v[9:10], 3, v[17:18] v_add_co_u32 v13, vcc_lo, s2, v13 v_ashrrev_i32_e32 v22, 31, v21 v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo v_lshlrev_b64 v[19:20], 3, v[19:20] v_add_co_u32 v15, vcc_lo, s2, v15 v_ashrrev_i32_e32 v26, 31, v25 v_add_co_ci_u32_e32 v16, vcc_lo, s3, v16, vcc_lo v_lshlrev_b64 v[21:22], 3, v[21:22] s_clause 0x1 global_load_b64 v[27:28], v[7:8], off global_load_b64 v[17:18], v[23:24], off v_add_co_u32 v23, vcc_lo, s2, v9 v_add_co_ci_u32_e32 v24, vcc_lo, s3, v10, vcc_lo v_lshlrev_b64 v[7:8], 3, v[25:26] v_add_co_u32 v25, vcc_lo, s2, v19 v_add_co_ci_u32_e32 v26, vcc_lo, s3, v20, vcc_lo v_add_co_u32 v21, vcc_lo, s2, v21 v_add_co_ci_u32_e32 v22, vcc_lo, s3, v22, vcc_lo v_add_co_u32 v35, vcc_lo, s2, v7 v_add_co_ci_u32_e32 v36, vcc_lo, s3, v8, vcc_lo s_clause 0x7 global_load_b64 v[5:6], v[5:6], off global_load_b64 v[9:10], v[11:12], off global_load_b64 v[7:8], v[13:14], off global_load_b64 v[19:20], v[23:24], off global_load_b64 v[11:12], v[15:16], off global_load_b64 v[13:14], v[25:26], off global_load_b64 v[21:22], v[21:22], off global_load_b64 v[25:26], v[35:36], off s_clause 0x1 global_load_b64 v[29:30], v[29:30], off global_load_b64 v[23:24], v[33:34], off s_clause 0x1 s_load_b32 s11, s[0:1], 0x40 s_load_b64 s[0:1], s[0:1], 0x38 v_mov_b32_e32 v15, 0 v_mov_b32_e32 v16, 0 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v36, v16 :: v_dual_mov_b32 v35, v15 s_waitcnt lgkmcnt(0) s_cmp_lg_u32 s11, 0 s_cselect_b32 s10, -1, 0 s_cmp_eq_u32 s11, 0 s_cbranch_scc1 .LBB5_3 ; %bb.2: v_add_nc_u32_e32 v33, s9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v34, 31, v33 v_lshlrev_b64 v[33:34], 3, v[33:34] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v33, vcc_lo, s0, v33 v_add_co_ci_u32_e32 v34, vcc_lo, s1, v34, vcc_lo v_add_co_u32 v31, vcc_lo, s0, v31 v_add_co_ci_u32_e32 v32, vcc_lo, s1, v32, vcc_lo s_clause 0x1 global_load_b64 v[33:34], v[33:34], off global_load_b64 v[31:32], v[31:32], off s_waitcnt vmcnt(0) v_add_f64 v[31:32], v[33:34], -v[31:32] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[33:34], null, v[31:32], v[31:32], 1.0 v_rcp_f64_e32 v[35:36], v[33:34] s_waitcnt_depctr 0xfff v_fma_f64 v[37:38], -v[33:34], v[35:36], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[35:36], v[35:36], v[37:38], v[35:36] v_fma_f64 v[37:38], -v[33:34], v[35:36], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[35:36], v[35:36], v[37:38], v[35:36] v_div_scale_f64 v[37:38], vcc_lo, 1.0, v[31:32], 1.0 v_mul_f64 v[39:40], v[37:38], v[35:36] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[33:34], -v[33:34], v[39:40], v[37:38] v_div_fmas_f64 v[33:34], v[33:34], v[35:36], v[39:40] s_delay_alu instid0(VALU_DEP_1) v_div_fixup_f64 v[35:36], v[33:34], v[31:32], 1.0 .LBB5_3: v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[31:32], 3, v[1:2] v_add_co_u32 v33, vcc_lo, s4, v31 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v34, vcc_lo, s5, v32, vcc_lo v_add_co_u32 v31, vcc_lo, s6, v31 v_add_co_ci_u32_e32 v32, vcc_lo, s7, v32, vcc_lo s_and_not1_b32 vcc_lo, exec_lo, s10 global_load_b64 v[33:34], v[33:34], off global_load_b64 v[31:32], v[31:32], off s_cbranch_vccnz .LBB5_5 ; %bb.4: v_lshlrev_b64 v[15:16], 3, v[1:2] v_lshlrev_b64 v[2:3], 3, v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v15, vcc_lo, s0, v15 v_add_co_ci_u32_e32 v16, vcc_lo, s1, v16, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v2, vcc_lo, s0, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo s_clause 0x1 global_load_b64 v[15:16], v[15:16], off global_load_b64 v[2:3], v[2:3], off s_waitcnt vmcnt(0) v_add_f64 v[2:3], v[15:16], -v[2:3] s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[15:16], v[35:36], v[2:3] .LBB5_5: s_waitcnt vmcnt(12) v_add_f64 v[2:3], v[27:28], -v[17:18] s_waitcnt vmcnt(2) v_add_f64 v[27:28], v[29:30], -v[23:24] v_add_f64 v[25:26], v[25:26], -v[21:22] s_waitcnt vmcnt(1) v_add_f64 v[17:18], v[33:34], -v[17:18] s_waitcnt vmcnt(0) v_add_f64 v[23:24], v[31:32], -v[23:24] v_add_f64 v[31:32], v[19:20], -v[7:8] v_add_f64 v[21:22], v[21:22], -v[11:12] v_add_nc_u32_e32 v0, s8, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[0:1], 3, v[0:1] v_div_scale_f64 v[29:30], null, v[2:3], v[2:3], 1.0 v_div_scale_f64 v[35:36], null, v[27:28], v[27:28], 1.0 v_div_scale_f64 v[45:46], vcc_lo, 1.0, v[2:3], 1.0 v_add_f64 v[25:26], v[25:26], -v[13:14] v_add_f64 v[13:14], v[13:14], -v[11:12] v_add_f64 v[21:22], v[21:22], -v[7:8] v_rcp_f64_e32 v[37:38], v[29:30] v_rcp_f64_e32 v[39:40], v[35:36] s_waitcnt_depctr 0xfff v_fma_f64 v[41:42], -v[29:30], v[37:38], 1.0 v_fma_f64 v[43:44], -v[35:36], v[39:40], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[37:38], v[37:38], v[41:42], v[37:38] v_fma_f64 v[39:40], v[39:40], v[43:44], v[39:40] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[41:42], -v[29:30], v[37:38], 1.0 v_fma_f64 v[43:44], -v[35:36], v[39:40], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[37:38], v[37:38], v[41:42], v[37:38] v_div_scale_f64 v[41:42], s0, 1.0, v[27:28], 1.0 v_fma_f64 v[39:40], v[39:40], v[43:44], v[39:40] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[43:44], v[45:46], v[37:38] v_mul_f64 v[47:48], v[41:42], v[39:40] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[29:30], -v[29:30], v[43:44], v[45:46] v_fma_f64 v[35:36], -v[35:36], v[47:48], v[41:42] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fmas_f64 v[29:30], v[29:30], v[37:38], v[43:44] s_mov_b32 vcc_lo, s0 v_div_fmas_f64 v[33:34], v[35:36], v[39:40], v[47:48] v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_div_fixup_f64 v[2:3], v[29:30], v[2:3], 1.0 v_add_f64 v[29:30], v[9:10], -v[5:6] v_div_fixup_f64 v[27:28], v[33:34], v[27:28], 1.0 v_mul_f64 v[2:3], v[2:3], v[17:18] v_add_f64 v[17:18], v[25:26], -v[19:20] v_add_f64 v[19:20], v[7:8], -v[5:6] v_add_f64 v[25:26], v[31:32], -v[9:10] v_mul_f64 v[23:24], v[27:28], v[23:24] v_fma_f64 v[27:28], v[29:30], v[2:3], v[5:6] v_add_f64 v[17:18], v[9:10], v[17:18] v_add_f64 v[29:30], v[11:12], -v[5:6] v_add_f64 v[25:26], v[5:6], v[25:26] v_add_f64 v[9:10], v[13:14], -v[9:10] v_add_f64 v[13:14], v[5:6], v[21:22] v_fma_f64 v[19:20], v[19:20], v[23:24], v[27:28] v_add_f64 v[11:12], v[11:12], v[17:18] v_mul_f64 v[17:18], v[25:26], v[2:3] v_add_f64 v[9:10], v[5:6], v[9:10] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[19:20], v[29:30], v[15:16], v[19:20] v_add_f64 v[7:8], v[7:8], v[11:12] v_mul_f64 v[11:12], v[13:14], v[23:24] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[13:14], v[17:18], v[23:24], v[19:20] v_add_f64 v[4:5], v[7:8], -v[5:6] v_mul_f64 v[6:7], v[9:10], v[15:16] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[8:9], v[11:12], v[15:16], v[13:14] v_mul_f64 v[4:5], v[4:5], v[23:24] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[6:7], v[2:3], v[6:7], v[8:9] v_mul_f64 v[4:5], v[4:5], v[15:16] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7] global_store_b64 v[0:1], v[2:3], off .LBB5_6: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 328 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 49 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end5: .size _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i, .Lfunc_end5-_Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1724 ; NumSgprs: 18 ; NumVgprs: 49 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 6 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 49 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z19resvisc_gpu_kernel1PdiiiiiiiS_ ; -- Begin function _Z19resvisc_gpu_kernel1PdiiiiiiiS_ .globl _Z19resvisc_gpu_kernel1PdiiiiiiiS_ .p2align 8 .type _Z19resvisc_gpu_kernel1PdiiiiiiiS_,@function _Z19resvisc_gpu_kernel1PdiiiiiiiS_: ; @_Z19resvisc_gpu_kernel1PdiiiiiiiS_ ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x3c s_load_b32 s3, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB6_2 ; %bb.1: s_clause 0x2 s_load_b64 s[2:3], s[0:1], 0x10 s_load_b32 s6, s[0:1], 0x18 s_load_b64 s[4:5], s[0:1], 0x28 v_ashrrev_i32_e32 v3, 31, v1 s_load_b64 s[0:1], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v4, v1, v3 v_xor_b32_e32 v4, v4, v3 s_waitcnt lgkmcnt(0) s_mul_i32 s2, s3, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s2, s2, s6 s_ashr_i32 s3, s2, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_add_i32 s2, s2, s3 v_xor_b32_e32 v3, s3, v3 s_xor_b32 s2, s2, s3 v_cvt_f32_u32_e32 v0, s2 s_sub_i32 s6, 0, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v0, v0 s_waitcnt_depctr 0xfff v_mul_f32_e32 v0, 0x4f7ffffe, v0 v_cvt_u32_f32_e32 v0, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, s6, v0 v_mul_hi_u32 v2, v0, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v0, v0, v2 v_mul_hi_u32 v0, v4, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, v0, s2 v_sub_nc_u32_e32 v2, v4, v2 v_add_nc_u32_e32 v4, 1, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_subrev_nc_u32_e32 v5, s2, v2 v_cmp_le_u32_e32 vcc_lo, s2, v2 v_cndmask_b32_e32 v0, v0, v4, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v2, v2, v5, vcc_lo v_add_nc_u32_e32 v4, 1, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cmp_le_u32_e32 vcc_lo, s2, v2 v_ashrrev_i32_e32 v2, 31, v1 v_cndmask_b32_e32 v0, v0, v4, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v0, v0, v3 v_sub_nc_u32_e32 v3, v0, v3 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[0:1], 3, v[1:2] v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 3, v[3:4] v_add_co_u32 v2, vcc_lo, s4, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo global_load_b64 v[4:5], v[0:1], off global_load_b64 v[2:3], v[2:3], off s_waitcnt vmcnt(0) v_mul_f64 v[4:5], v[4:5], v[2:3] v_mul_f64 v[2:3], v[2:3], v[4:5] global_store_b64 v[0:1], v[2:3], off .LBB6_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z19resvisc_gpu_kernel1PdiiiiiiiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 304 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end6: .size _Z19resvisc_gpu_kernel1PdiiiiiiiS_, .Lfunc_end6-_Z19resvisc_gpu_kernel1PdiiiiiiiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 408 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z19resvisc_gpu_kernel2Pdiiiiiiidd ; -- Begin function _Z19resvisc_gpu_kernel2Pdiiiiiiidd .globl _Z19resvisc_gpu_kernel2Pdiiiiiiidd .p2align 8 .type _Z19resvisc_gpu_kernel2Pdiiiiiiidd,@function _Z19resvisc_gpu_kernel2Pdiiiiiiidd: ; @_Z19resvisc_gpu_kernel2Pdiiiiiiidd ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x44 s_load_b32 s3, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB7_4 ; %bb.1: s_load_b64 s[4:5], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_load_b128 s[0:3], s[0:1], 0x28 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo v_cmp_eq_f64_e64 s4, s[2:3], 0 global_load_b64 v[2:3], v[0:1], off s_and_b32 vcc_lo, exec_lo, s4 s_waitcnt vmcnt(0) v_mul_f64 v[2:3], |v[2:3]|, s[0:1] s_cbranch_vccnz .LBB7_3 ; %bb.2: v_div_scale_f64 v[4:5], null, s[2:3], s[2:3], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[6:7], v[4:5] s_waitcnt_depctr 0xfff v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] v_div_scale_f64 v[8:9], vcc_lo, 1.0, s[2:3], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[10:11], v[8:9], v[6:7] v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11] v_div_fixup_f64 v[4:5], v[4:5], s[2:3], 1.0 s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[2:3], v[4:5], v[2:3] .LBB7_3: global_store_b64 v[0:1], v[2:3], off .LBB7_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z19resvisc_gpu_kernel2Pdiiiiiiidd .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 312 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end7: .size _Z19resvisc_gpu_kernel2Pdiiiiiiidd, .Lfunc_end7-_Z19resvisc_gpu_kernel2Pdiiiiiiidd ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 284 ; NumSgprs: 18 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i ; -- Begin function _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .globl _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .p2align 8 .type _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i,@function _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i: ; @_Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x6c s_load_b32 s3, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v2 s_cbranch_execz .LBB8_8 ; %bb.1: s_clause 0x1 s_load_b128 s[12:15], s[0:1], 0x18 s_load_b128 s[8:11], s[0:1], 0x0 v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[3:4], 3, v[2:3] s_waitcnt lgkmcnt(0) v_lshl_add_u32 v0, s15, 1, v2 s_mul_i32 s5, s13, s12 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[0:1] v_add_co_u32 v5, vcc_lo, s10, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v6, vcc_lo, s11, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s8, v3 v_add_co_ci_u32_e32 v1, vcc_lo, s9, v4, vcc_lo global_load_b64 v[5:6], v[5:6], off global_load_b64 v[7:8], v[0:1], off s_waitcnt vmcnt(0) v_cmp_le_f64_e32 vcc_lo, v[5:6], v[7:8] v_ashrrev_i32_e32 v7, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v8, v2, v7 v_xor_b32_e32 v8, v8, v7 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB8_3 ; %bb.2: global_store_b64 v[0:1], v[5:6], off .LBB8_3: s_or_b32 exec_lo, exec_lo, s2 global_load_b64 v[9:10], v[0:1], off s_ashr_i32 s2, s12, 31 s_ashr_i32 s4, s5, 31 s_add_i32 s3, s12, s2 s_add_i32 s6, s5, s4 s_xor_b32 s3, s3, s2 s_xor_b32 s6, s6, s4 v_cvt_f32_u32_e32 v5, s3 v_cvt_f32_u32_e32 v6, s6 s_sub_i32 s7, 0, s3 s_ashr_i32 s11, s14, 31 s_load_b128 s[16:19], s[0:1], 0x2c v_rcp_iflag_f32_e32 v5, v5 v_rcp_iflag_f32_e32 v6, v6 s_waitcnt_depctr 0xfff v_dual_mul_f32 v5, 0x4f7ffffe, v5 :: v_dual_mul_f32 v6, 0x4f7ffffe, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_u32_f32_e32 v5, v5 v_cvt_u32_f32_e32 v6, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mul_lo_u32 v11, s7, v5 s_sub_i32 s7, 0, s6 v_mul_hi_u32 v11, v5, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_nc_u32_e32 v5, v5, v11 v_mul_lo_u32 v11, s7, v6 s_ashr_i32 s7, s13, 31 s_add_i32 s10, s13, s7 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_mul_hi_u32 v5, v8, v5 s_xor_b32 s10, s10, s7 s_add_i32 s7, s14, s11 v_cvt_f32_u32_e32 v16, s10 v_mul_hi_u32 v11, v6, v11 s_xor_b32 s11, s7, s11 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_cvt_f32_u32_e32 v15, s11 v_mul_lo_u32 v12, v5, s3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v6, v6, v11 v_sub_nc_u32_e32 v11, v8, v12 v_add_nc_u32_e32 v12, 1, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cmp_le_u32_e32 vcc_lo, s3, v11 v_subrev_nc_u32_e32 v13, s3, v11 v_cndmask_b32_e32 v5, v5, v12, vcc_lo v_mul_hi_u32 v6, v8, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v11, v11, v13 :: v_dual_add_nc_u32 v14, 1, v6 v_mul_lo_u32 v12, v6, s6 v_sub_nc_u32_e32 v12, v8, v12 s_delay_alu instid0(VALU_DEP_1) v_subrev_nc_u32_e32 v17, s6, v12 v_cmp_le_u32_e32 vcc_lo, s6, v12 v_cndmask_b32_e32 v6, v6, v14, vcc_lo v_rcp_iflag_f32_e32 v14, v15 v_add_nc_u32_e32 v13, 1, v5 v_cndmask_b32_e32 v12, v12, v17, vcc_lo v_cmp_le_u32_e32 vcc_lo, s3, v11 v_add_nc_u32_e32 v17, 1, v6 v_xor_b32_e32 v11, s4, v7 v_rcp_iflag_f32_e32 v15, v16 v_xor_b32_e32 v16, s2, v7 v_cndmask_b32_e32 v5, v5, v13, vcc_lo v_cmp_le_u32_e32 vcc_lo, s6, v12 v_mul_f32_e32 v12, 0x4f7ffffe, v14 s_sub_i32 s3, 0, s11 s_sub_i32 s2, 0, s10 s_load_b64 s[6:7], s[0:1], 0x50 v_cndmask_b32_e32 v6, v6, v17, vcc_lo v_cvt_u32_f32_e32 v12, v12 v_mul_f32_e32 v13, 0x4f7ffffe, v15 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v6, v6, v11 v_cvt_u32_f32_e32 v13, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_sub_nc_u32_e32 v6, v6, v11 v_mul_lo_u32 v11, s3, v12 v_mul_lo_u32 v14, s2, v13 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_ashrrev_i32_e32 v15, 31, v6 v_mul_hi_u32 v11, v12, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_nc_u32_e32 v6, v6, v15 v_xor_b32_e32 v5, v5, v16 v_mul_hi_u32 v14, v13, v14 v_xor_b32_e32 v6, v6, v15 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_sub_nc_u32_e32 v5, v5, v16 v_add_nc_u32_e32 v11, v12, v11 v_add_nc_u32_e32 v13, v13, v14 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_ashrrev_i32_e32 v16, 31, v5 v_mul_hi_u32 v11, v6, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_nc_u32_e32 v17, v5, v16 v_mul_lo_u32 v5, v5, s12 v_mul_lo_u32 v11, v11, s11 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v12, v17, v16 v_sub_nc_u32_e32 v5, v2, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4) v_mul_hi_u32 v13, v12, v13 s_waitcnt lgkmcnt(0) v_add_co_u32 v2, s4, s6, v3 v_sub_nc_u32_e32 v6, v6, v11 v_add_co_ci_u32_e64 v3, s4, s7, v4, s4 v_mul_lo_u32 v13, v13, s10 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_le_u32_e32 vcc_lo, s11, v6 v_sub_nc_u32_e32 v11, v12, v13 v_subrev_nc_u32_e32 v12, s11, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v13, s10, v11 v_cndmask_b32_e32 v6, v6, v12, vcc_lo v_cmp_le_u32_e32 vcc_lo, s10, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_subrev_nc_u32_e32 v12, s11, v6 v_cndmask_b32_e32 v11, v11, v13, vcc_lo v_cmp_le_u32_e32 vcc_lo, s11, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_subrev_nc_u32_e32 v13, s10, v11 v_cndmask_b32_e32 v6, v6, v12, vcc_lo v_cmp_le_u32_e32 vcc_lo, s10, v11 s_load_b64 s[10:11], s[0:1], 0x3c s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_xor_b32_e32 v6, v6, v15 v_cndmask_b32_e32 v11, v11, v13, vcc_lo v_sub_nc_u32_e32 v19, v6, v15 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v11, v11, v16 v_cmp_le_i32_e32 vcc_lo, s16, v19 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v6, v11, v16 v_cmp_ge_i32_e64 s2, s17, v19 v_cmp_le_i32_e64 s3, s18, v6 v_cmp_ge_i32_e64 s4, s19, v6 s_delay_alu instid0(VALU_DEP_2) s_and_b32 s3, vcc_lo, s3 s_waitcnt lgkmcnt(0) v_cmp_le_i32_e32 vcc_lo, s10, v5 s_and_b32 s3, s3, s2 v_cmp_ge_i32_e64 s2, s11, v5 s_and_b32 s3, s4, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 s3, vcc_lo, s3 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_b32 s3, s2, s3 s_waitcnt vmcnt(0) global_store_b64 v[2:3], v[9:10], off s_and_saveexec_b32 s2, s3 s_cbranch_execz .LBB8_7 ; %bb.4: s_mul_i32 s3, s5, s14 v_mul_lo_u32 v20, v6, s12 s_ashr_i32 s4, s3, 31 s_add_i32 s6, s12, -1 s_add_i32 s3, s3, s4 v_xor_b32_e32 v7, s4, v7 s_xor_b32 s3, s3, s4 v_add_nc_u32_e32 v11, 1, v5 v_cvt_f32_u32_e32 v4, s3 s_sub_i32 s5, 0, s3 s_load_b32 s4, s[0:1], 0x58 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v4, v4 s_waitcnt_depctr 0xfff v_mul_f32_e32 v4, 0x4f7ffffe, v4 v_cvt_u32_f32_e32 v4, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mul_lo_u32 v9, s5, v4 s_load_b32 s5, s[0:1], 0x14 v_mul_hi_u32 v9, v4, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v4, v4, v9 v_mad_u64_u32 v[9:10], null, v8, v4, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v4, v10, s3 v_sub_nc_u32_e32 v4, v8, v4 v_add_nc_u32_e32 v8, 1, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_subrev_nc_u32_e32 v9, s3, v4 v_cmp_le_u32_e32 vcc_lo, s3, v4 v_cndmask_b32_e32 v8, v10, v8, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v4, v4, v9 :: v_dual_add_nc_u32 v9, 1, v8 v_cmp_le_u32_e32 vcc_lo, s3, v4 s_load_b32 s3, s[0:1], 0x28 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v4, v8, v9 :: v_dual_add_nc_u32 v9, -1, v6 v_cmp_gt_i32_e32 vcc_lo, 1, v6 v_xor_b32_e32 v4, v4, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v4, v4, v7 s_waitcnt lgkmcnt(0) v_mul_lo_u32 v4, v4, s5 s_add_i32 s5, s13, -1 s_cmp_eq_u32 s4, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mad_u64_u32 v[7:8], null, v19, s3, v[4:5] v_add_nc_u32_e32 v8, -1, v5 v_add_nc_u32_e32 v10, 1, v6 v_cndmask_b32_e32 v12, v9, v10, vcc_lo v_cmp_gt_i32_e32 vcc_lo, s5, v6 v_add_nc_u32_e32 v14, v7, v20 v_dual_cndmask_b32 v13, v9, v10 :: v_dual_add_nc_u32 v6, v7, v5 v_cmp_gt_i32_e32 vcc_lo, 1, v5 v_cndmask_b32_e32 v9, v8, v11, vcc_lo v_cmp_gt_i32_e32 vcc_lo, s6, v5 v_add_nc_u32_e32 v5, v14, v5 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, v14, v9 v_cndmask_b32_e32 v21, v8, v11, vcc_lo v_mad_u64_u32 v[9:10], null, v12, s12, v[6:7] v_mad_u64_u32 v[11:12], null, v13, s12, v[6:7] v_ashrrev_i32_e32 v6, 31, v5 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_add_nc_u32_e32 v13, v14, v21 v_ashrrev_i32_e32 v8, 31, v7 v_ashrrev_i32_e32 v10, 31, v9 v_lshlrev_b64 v[5:6], 3, v[5:6] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_ashrrev_i32_e32 v14, 31, v13 v_lshlrev_b64 v[7:8], 3, v[7:8] v_ashrrev_i32_e32 v12, 31, v11 v_lshlrev_b64 v[9:10], 3, v[9:10] s_delay_alu instid0(VALU_DEP_4) v_lshlrev_b64 v[13:14], 3, v[13:14] v_add_co_u32 v5, vcc_lo, s8, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo v_add_co_u32 v7, vcc_lo, s8, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo v_lshlrev_b64 v[11:12], 3, v[11:12] v_add_co_u32 v13, vcc_lo, s8, v13 v_add_co_ci_u32_e32 v14, vcc_lo, s9, v14, vcc_lo v_add_co_u32 v15, vcc_lo, s8, v9 v_add_co_ci_u32_e32 v16, vcc_lo, s9, v10, vcc_lo v_add_co_u32 v17, vcc_lo, s8, v11 v_add_co_ci_u32_e32 v18, vcc_lo, s9, v12, vcc_lo s_clause 0x4 global_load_b64 v[5:6], v[5:6], off global_load_b64 v[7:8], v[7:8], off global_load_b64 v[9:10], v[13:14], off global_load_b64 v[11:12], v[15:16], off global_load_b64 v[13:14], v[17:18], off v_mov_b32_e32 v17, 0 v_mov_b32_e32 v18, 0 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v15, v17 :: v_dual_mov_b32 v16, v18 s_cbranch_scc1 .LBB8_6 ; %bb.5: s_add_i32 s4, s14, -1 v_add_nc_u32_e32 v4, v21, v4 v_cmp_gt_i32_e32 vcc_lo, s4, v19 s_waitcnt vmcnt(2) v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9 v_cndmask_b32_e64 v15, -1, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v15, v15, v19 v_mul_lo_u32 v15, v15, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add3_u32 v15, v4, v20, v15 v_ashrrev_i32_e32 v16, 31, v15 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[15:16], 3, v[15:16] v_add_co_u32 v15, vcc_lo, s8, v15 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo global_load_b64 v[15:16], v[15:16], off .LBB8_6: s_clause 0x1 s_load_b32 s3, s[0:1], 0x44 s_load_b64 s[0:1], s[0:1], 0x48 s_waitcnt lgkmcnt(0) v_cvt_f64_i32_e32 v[19:20], s3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[19:20], v[19:20], v[19:20] s_waitcnt vmcnt(3) v_fma_f64 v[4:5], v[19:20], v[5:6], v[7:8] s_waitcnt vmcnt(2) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[4:5], v[4:5], v[9:10] s_waitcnt vmcnt(1) v_add_f64 v[4:5], v[4:5], v[11:12] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[4:5], v[4:5], v[13:14] v_add_f64 v[4:5], v[4:5], v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[4:5], v[4:5], v[15:16] v_ldexp_f64 v[4:5], v[4:5], -2 s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[4:5], v[4:5], s[0:1] global_store_b64 v[2:3], v[4:5], off .LBB8_7: ; %Flow s_or_b32 exec_lo, exec_lo, s2 global_load_b64 v[2:3], v[2:3], off s_waitcnt vmcnt(0) global_store_b64 v[0:1], v[2:3], off .LBB8_8: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 352 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 22 .amdhsa_next_free_sgpr 20 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end8: .size _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i, .Lfunc_end8-_Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1752 ; NumSgprs: 22 ; NumVgprs: 22 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 22 ; NumVGPRsForWavesPerEU: 22 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 8 .value_kind: by_value - .offset: 40 .size: 8 .value_kind: by_value - .offset: 48 .size: 8 .value_kind: by_value - .offset: 56 .size: 4 .value_kind: by_value - .offset: 64 .size: 4 .value_kind: hidden_block_count_x - .offset: 68 .size: 4 .value_kind: hidden_block_count_y - .offset: 72 .size: 4 .value_kind: hidden_block_count_z - .offset: 76 .size: 2 .value_kind: hidden_group_size_x - .offset: 78 .size: 2 .value_kind: hidden_group_size_y - .offset: 80 .size: 2 .value_kind: hidden_group_size_z - .offset: 82 .size: 2 .value_kind: hidden_remainder_x - .offset: 84 .size: 2 .value_kind: hidden_remainder_y - .offset: 86 .size: 2 .value_kind: hidden_remainder_z - .offset: 104 .size: 8 .value_kind: hidden_global_offset_x - .offset: 112 .size: 8 .value_kind: hidden_global_offset_y - .offset: 120 .size: 8 .value_kind: hidden_global_offset_z - .offset: 128 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 320 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z26compute_entropy_gpu_kernelPdS_S_iidddi .private_segment_fixed_size: 0 .sgpr_count: 22 .sgpr_spill_count: 0 .symbol: _Z26compute_entropy_gpu_kernelPdS_S_iidddi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 27 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: by_value - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .offset: 56 .size: 4 .value_kind: by_value - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer - .offset: 88 .size: 4 .value_kind: by_value - .offset: 96 .size: 4 .value_kind: hidden_block_count_x - .offset: 100 .size: 4 .value_kind: hidden_block_count_y - .offset: 104 .size: 4 .value_kind: hidden_block_count_z - .offset: 108 .size: 2 .value_kind: hidden_group_size_x - .offset: 110 .size: 2 .value_kind: hidden_group_size_y - .offset: 112 .size: 2 .value_kind: hidden_group_size_z - .offset: 114 .size: 2 .value_kind: hidden_remainder_x - .offset: 116 .size: 2 .value_kind: hidden_remainder_y - .offset: 118 .size: 2 .value_kind: hidden_remainder_z - .offset: 136 .size: 8 .value_kind: hidden_global_offset_x - .offset: 144 .size: 8 .value_kind: hidden_global_offset_y - .offset: 152 .size: 8 .value_kind: hidden_global_offset_z - .offset: 160 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 352 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .private_segment_fixed_size: 0 .sgpr_count: 22 .sgpr_spill_count: 0 .symbol: _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: by_value - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .offset: 56 .size: 4 .value_kind: by_value - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 88 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 96 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 104 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 112 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 120 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 128 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 136 .size: 8 .value_kind: global_buffer - .offset: 144 .size: 4 .value_kind: by_value - .address_space: global .offset: 152 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 160 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 168 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 176 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 184 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 192 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 200 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 208 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 216 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 224 .size: 8 .value_kind: global_buffer - .offset: 232 .size: 4 .value_kind: by_value - .offset: 240 .size: 4 .value_kind: hidden_block_count_x - .offset: 244 .size: 4 .value_kind: hidden_block_count_y - .offset: 248 .size: 4 .value_kind: hidden_block_count_z - .offset: 252 .size: 2 .value_kind: hidden_group_size_x - .offset: 254 .size: 2 .value_kind: hidden_group_size_y - .offset: 256 .size: 2 .value_kind: hidden_group_size_z - .offset: 258 .size: 2 .value_kind: hidden_remainder_x - .offset: 260 .size: 2 .value_kind: hidden_remainder_y - .offset: 262 .size: 2 .value_kind: hidden_remainder_z - .offset: 280 .size: 8 .value_kind: hidden_global_offset_x - .offset: 288 .size: 8 .value_kind: hidden_global_offset_y - .offset: 296 .size: 8 .value_kind: hidden_global_offset_z - .offset: 304 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 496 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .private_segment_fixed_size: 0 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.text .file "03a04df5f71e1ae979c3a9a4d1c5d8d5006e6a23.hip" .globl _Z41__device_stub__compute_entropy_gpu_kernelPdS_S_iidddi # -- Begin function _Z41__device_stub__compute_entropy_gpu_kernelPdS_S_iidddi .p2align 4, 0x90 .type _Z41__device_stub__compute_entropy_gpu_kernelPdS_S_iidddi,@function _Z41__device_stub__compute_entropy_gpu_kernelPdS_S_iidddi: # @_Z41__device_stub__compute_entropy_gpu_kernelPdS_S_iidddi .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 104(%rsp) movq %rsi, 96(%rsp) movq %rdx, 88(%rsp) movl %ecx, 12(%rsp) movl %r8d, 8(%rsp) movsd %xmm0, 80(%rsp) movsd %xmm1, 72(%rsp) movsd %xmm2, 64(%rsp) movl %r9d, 4(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 12(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) leaq 80(%rsp), %rax movq %rax, 152(%rsp) leaq 72(%rsp), %rax movq %rax, 160(%rsp) leaq 64(%rsp), %rax movq %rax, 168(%rsp) leaq 4(%rsp), %rax movq %rax, 176(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z26compute_entropy_gpu_kernelPdS_S_iidddi, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end0: .size _Z41__device_stub__compute_entropy_gpu_kernelPdS_S_iidddi, .Lfunc_end0-_Z41__device_stub__compute_entropy_gpu_kernelPdS_S_iidddi .cfi_endproc # -- End function .globl compute_entropy_gpu_wrapper_ # -- Begin function compute_entropy_gpu_wrapper_ .p2align 4, 0x90 .type compute_entropy_gpu_wrapper_,@function compute_entropy_gpu_wrapper_: # @compute_entropy_gpu_wrapper_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $216, %rsp .cfi_def_cfa_offset 272 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r9, %r13 movq %r8, %rbp movq %rcx, 40(%rsp) # 8-byte Spill movq %rdx, 32(%rsp) # 8-byte Spill movq %rsi, 24(%rsp) # 8-byte Spill movq %rdi, %r14 movq 288(%rsp), %r15 movq 280(%rsp), %r12 movq 272(%rsp), %rbx callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, 8(%rsp) # 4-byte Spill movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movq %rax, %rsi xorl %eax, %eax callq printf movl (%rbp), %esi movl (%r13), %edx movsd (%rbx), %xmm0 # xmm0 = mem[0],zero movsd (%r12), %xmm1 # xmm1 = mem[0],zero movsd (%r15), %xmm2 # xmm2 = mem[0],zero movl $.L.str.1, %edi movb $3, %al callq printf movl (%r14), %r14d xorps %xmm0, %xmm0 cvtsi2ssl (%rbp), %xmm0 xorps %xmm1, %xmm1 cvtsi2ss %r14d, %xmm1 divss %xmm1, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %edi movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi orq %rax, %r14 movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 296(%rsp), %rax movl (%rbp), %ecx movl (%r13), %edx movq 272(%rsp), %rsi movsd (%rsi), %xmm0 # xmm0 = mem[0],zero movq 280(%rsp), %rsi movsd (%rsi), %xmm1 # xmm1 = mem[0],zero movq 288(%rsp), %rsi movsd (%rsi), %xmm2 # xmm2 = mem[0],zero movl (%rax), %eax movq 24(%rsp), %rsi # 8-byte Reload movq %rsi, 136(%rsp) movq 32(%rsp), %rsi # 8-byte Reload movq %rsi, 128(%rsp) movq 40(%rsp), %rsi # 8-byte Reload movq %rsi, 120(%rsp) movl %ecx, 20(%rsp) movl %edx, 16(%rsp) movsd %xmm0, 112(%rsp) movsd %xmm1, 104(%rsp) movsd %xmm2, 96(%rsp) movl %eax, 12(%rsp) leaq 136(%rsp), %rax movq %rax, 144(%rsp) leaq 128(%rsp), %rax movq %rax, 152(%rsp) leaq 120(%rsp), %rax movq %rax, 160(%rsp) leaq 20(%rsp), %rax movq %rax, 168(%rsp) leaq 16(%rsp), %rax movq %rax, 176(%rsp) leaq 112(%rsp), %rax movq %rax, 184(%rsp) leaq 104(%rsp), %rax movq %rax, 192(%rsp) leaq 96(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 80(%rsp), %rdi leaq 64(%rsp), %rsi leaq 56(%rsp), %rdx leaq 48(%rsp), %rcx callq __hipPopCallConfiguration movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 64(%rsp), %rcx movl 72(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z26compute_entropy_gpu_kernelPdS_S_iidddi, %edi pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: callq hipDeviceSynchronize callq hipPeekAtLastError movl 8(%rsp), %edi # 4-byte Reload callq hipGetErrorString movl $.L.str.2, %edi movq %rax, %rsi xorl %eax, %eax callq printf addq $216, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size compute_entropy_gpu_wrapper_, .Lfunc_end1-compute_entropy_gpu_wrapper_ .cfi_endproc # -- End function .globl _Z47__device_stub__entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i # -- Begin function _Z47__device_stub__entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .p2align 4, 0x90 .type _Z47__device_stub__entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i,@function _Z47__device_stub__entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i: # @_Z47__device_stub__entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .cfi_startproc # %bb.0: subq $200, %rsp .cfi_def_cfa_offset 208 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movl %edx, 20(%rsp) movsd %xmm0, 72(%rsp) movl %ecx, 16(%rsp) movl %r8d, 12(%rsp) movl %r9d, 8(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 20(%rsp), %rax movq %rax, 112(%rsp) leaq 72(%rsp), %rax movq %rax, 120(%rsp) leaq 16(%rsp), %rax movq %rax, 128(%rsp) leaq 12(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) leaq 208(%rsp), %rax movq %rax, 152(%rsp) leaq 216(%rsp), %rax movq %rax, 160(%rsp) leaq 224(%rsp), %rax movq %rax, 168(%rsp) leaq 232(%rsp), %rax movq %rax, 176(%rsp) leaq 240(%rsp), %rax movq %rax, 184(%rsp) leaq 248(%rsp), %rax movq %rax, 192(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $216, %rsp .cfi_adjust_cfa_offset -216 retq .Lfunc_end2: .size _Z47__device_stub__entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i, .Lfunc_end2-_Z47__device_stub__entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .cfi_endproc # -- End function .globl _Z39__device_stub__flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i # -- Begin function _Z39__device_stub__flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .p2align 4, 0x90 .type _Z39__device_stub__flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i,@function _Z39__device_stub__flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i: # @_Z39__device_stub__flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .cfi_startproc # %bb.0: subq $344, %rsp # imm = 0x158 .cfi_def_cfa_offset 352 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movl %edx, 20(%rsp) movsd %xmm0, 72(%rsp) movl %ecx, 16(%rsp) movl %r8d, 12(%rsp) movl %r9d, 8(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 20(%rsp), %rax movq %rax, 112(%rsp) leaq 72(%rsp), %rax movq %rax, 120(%rsp) leaq 16(%rsp), %rax movq %rax, 128(%rsp) leaq 12(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) leaq 352(%rsp), %rax movq %rax, 152(%rsp) leaq 360(%rsp), %rax movq %rax, 160(%rsp) leaq 368(%rsp), %rax movq %rax, 168(%rsp) leaq 376(%rsp), %rax movq %rax, 176(%rsp) leaq 384(%rsp), %rax movq %rax, 184(%rsp) leaq 392(%rsp), %rax movq %rax, 192(%rsp) leaq 400(%rsp), %rax movq %rax, 200(%rsp) leaq 408(%rsp), %rax movq %rax, 208(%rsp) leaq 416(%rsp), %rax movq %rax, 216(%rsp) leaq 424(%rsp), %rax movq %rax, 224(%rsp) leaq 432(%rsp), %rax movq %rax, 232(%rsp) leaq 440(%rsp), %rax movq %rax, 240(%rsp) leaq 448(%rsp), %rax movq %rax, 248(%rsp) leaq 456(%rsp), %rax movq %rax, 256(%rsp) leaq 464(%rsp), %rax movq %rax, 264(%rsp) leaq 472(%rsp), %rax movq %rax, 272(%rsp) leaq 480(%rsp), %rax movq %rax, 280(%rsp) leaq 488(%rsp), %rax movq %rax, 288(%rsp) leaq 496(%rsp), %rax movq %rax, 296(%rsp) leaq 504(%rsp), %rax movq %rax, 304(%rsp) leaq 512(%rsp), %rax movq %rax, 312(%rsp) leaq 520(%rsp), %rax movq %rax, 320(%rsp) leaq 528(%rsp), %rax movq %rax, 328(%rsp) leaq 536(%rsp), %rax movq %rax, 336(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $360, %rsp # imm = 0x168 .cfi_adjust_cfa_offset -360 retq .Lfunc_end3: .size _Z39__device_stub__flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end3-_Z39__device_stub__flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .cfi_endproc # -- End function .globl _Z19__device_stub__mxm1PdiS_iS_iiiiii # -- Begin function _Z19__device_stub__mxm1PdiS_iS_iiiiii .p2align 4, 0x90 .type _Z19__device_stub__mxm1PdiS_iS_iiiiii,@function _Z19__device_stub__mxm1PdiS_iS_iiiiii: # @_Z19__device_stub__mxm1PdiS_iS_iiiiii .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 88(%rsp) movl %esi, 20(%rsp) movq %rdx, 80(%rsp) movl %ecx, 16(%rsp) movq %r8, 72(%rsp) movl %r9d, 12(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 20(%rsp), %rax movq %rax, 104(%rsp) leaq 80(%rsp), %rax movq %rax, 112(%rsp) leaq 16(%rsp), %rax movq %rax, 120(%rsp) leaq 72(%rsp), %rax movq %rax, 128(%rsp) leaq 12(%rsp), %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) leaq 224(%rsp), %rax movq %rax, 176(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z4mxm1PdiS_iS_iiiiii, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end4: .size _Z19__device_stub__mxm1PdiS_iS_iiiiii, .Lfunc_end4-_Z19__device_stub__mxm1PdiS_iS_iiiiii .cfi_endproc # -- End function .globl entropy_residual_gpu_wrapper_ # -- Begin function entropy_residual_gpu_wrapper_ .p2align 4, 0x90 .type entropy_residual_gpu_wrapper_,@function entropy_residual_gpu_wrapper_: # @entropy_residual_gpu_wrapper_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $424, %rsp # imm = 0x1A8 .cfi_def_cfa_offset 480 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r9, %r14 movq %r8, %r15 movq %rcx, 352(%rsp) # 8-byte Spill movq %rdx, 408(%rsp) # 8-byte Spill movq %rsi, 400(%rsp) # 8-byte Spill movq %rdi, 264(%rsp) # 8-byte Spill movq 480(%rsp), %r13 movq 512(%rsp), %rbx movq 504(%rsp), %rbp movq 496(%rsp), %r12 callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.3, %edi movq %rax, %rsi xorl %eax, %eax callq printf movq %r15, 384(%rsp) # 8-byte Spill movsd (%r15), %xmm0 # xmm0 = mem[0],zero movq %r14, 392(%rsp) # 8-byte Spill movl (%r14), %esi movl (%r13), %edx movq 488(%rsp), %rax movl (%rax), %ecx movl (%r12), %r8d movl (%rbp), %r9d movl (%rbx), %r10d movq %rbx, %rbp movq 544(%rsp), %rax movl (%rax), %r11d movq 656(%rsp), %rbx movq 552(%rsp), %rax movl (%rax), %r14d movq 560(%rsp), %rax movl (%rax), %r15d movq 648(%rsp), %rax movl (%rax), %r12d movl (%rbx), %r13d movl $.L.str.4, %edi movb $1, %al pushq %r13 .cfi_adjust_cfa_offset 8 pushq %r12 movabsq $4294967296, %r12 # imm = 0x100000000 .cfi_adjust_cfa_offset 8 pushq %r15 .cfi_adjust_cfa_offset 8 pushq %r14 .cfi_adjust_cfa_offset 8 pushq %r11 .cfi_adjust_cfa_offset 8 pushq %r10 .cfi_adjust_cfa_offset 8 callq printf addq $48, %rsp .cfi_adjust_cfa_offset -48 movq 496(%rsp), %rax movslq (%rax), %rax movq 504(%rsp), %rcx movslq (%rcx), %rcx imulq %rax, %rcx movslq (%rbp), %rdx imulq %rcx, %rdx movq 544(%rsp), %rax movslq (%rax), %rax movq 552(%rsp), %rcx movslq (%rcx), %rcx imulq %rax, %rcx movq 560(%rsp), %rax movslq (%rax), %rbp imulq %rcx, %rbp movq %rdx, 256(%rsp) # 8-byte Spill leaq (%rdx,%rdx,2), %r15 movslq (%rbx), %rsi imulq %r15, %rsi shlq $3, %rsi leaq 136(%rsp), %rdi callq hipMalloc movslq (%rbx), %rsi imulq %rbp, %rsi shlq $3, %rsi leaq 296(%rsp), %rdi callq hipMalloc movslq (%rbx), %rsi movslq %ebp, %r14 imulq %r14, %rsi shlq $3, %rsi leaq 288(%rsp), %rdi callq hipMalloc movslq (%rbx), %rsi imulq %r14, %rsi shlq $3, %rsi leaq 344(%rsp), %rdi callq hipMalloc movslq (%rbx), %rsi imulq %r14, %rsi shlq $3, %rsi leaq 280(%rsp), %rdi callq hipMalloc movslq (%rbx), %rsi imulq %r14, %rsi shlq $3, %rsi leaq 272(%rsp), %rdi callq hipMalloc movslq (%rbx), %rsi imulq %r14, %rsi shlq $3, %rsi leaq 336(%rsp), %rdi callq hipMalloc movslq (%rbx), %rsi imulq %r14, %rsi shlq $3, %rsi leaq 328(%rsp), %rdi callq hipMalloc movslq (%rbx), %rsi imulq %r14, %rsi shlq $3, %rsi leaq 320(%rsp), %rdi callq hipMalloc movslq (%rbx), %rsi imulq %r14, %rsi shlq $3, %rsi leaq 312(%rsp), %rdi callq hipMalloc movslq (%rbx), %rsi imulq %r14, %rsi shlq $3, %rsi leaq 360(%rsp), %rdi callq hipMalloc movq 136(%rsp), %rdi movslq (%rbx), %rax movslq %r15d, %rdx imulq %rax, %rdx shlq $3, %rdx xorl %esi, %esi callq hipMemset movq 296(%rsp), %rdi movslq (%rbx), %rdx imulq %r14, %rdx shlq $3, %rdx xorl %esi, %esi callq hipMemset movq 288(%rsp), %rdi movslq (%rbx), %rdx imulq %r14, %rdx shlq $3, %rdx xorl %esi, %esi callq hipMemset movq 344(%rsp), %rdi movslq (%rbx), %rdx imulq %r14, %rdx shlq $3, %rdx xorl %esi, %esi callq hipMemset movq 280(%rsp), %rdi movslq (%rbx), %rdx imulq %r14, %rdx shlq $3, %rdx xorl %esi, %esi callq hipMemset movq 272(%rsp), %rdi movslq (%rbx), %rdx imulq %r14, %rdx shlq $3, %rdx xorl %esi, %esi callq hipMemset movq 336(%rsp), %rdi movslq (%rbx), %rdx imulq %r14, %rdx shlq $3, %rdx xorl %esi, %esi callq hipMemset movq 328(%rsp), %rdi movslq (%rbx), %rdx imulq %r14, %rdx shlq $3, %rdx xorl %esi, %esi callq hipMemset movq 320(%rsp), %rdi movslq (%rbx), %rdx imulq %r14, %rdx shlq $3, %rdx xorl %esi, %esi callq hipMemset movq 312(%rsp), %rdi movslq (%rbx), %rdx imulq %r14, %rdx shlq $3, %rdx xorl %esi, %esi callq hipMemset movq 360(%rsp), %rdi movslq (%rbx), %rdx imulq %r14, %rdx shlq $3, %rdx xorl %esi, %esi callq hipMemset movq 264(%rsp), %rax # 8-byte Reload movq %rax, %r13 movl (%rax), %r15d movq 352(%rsp), %rax # 8-byte Reload cvtsi2ssl (%rax), %xmm0 cvtsi2ss %r15d, %xmm1 movss %xmm1, 20(%rsp) # 4-byte Spill divss %xmm1, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %edi orq %r12, %rdi movq %r15, 416(%rsp) # 8-byte Spill orq %r12, %r15 movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_2 # %bb.1: movq 352(%rsp), %rax # 8-byte Reload movl (%rax), %eax movq 384(%rsp), %rcx # 8-byte Reload movsd (%rcx), %xmm0 # xmm0 = mem[0],zero movq 392(%rsp), %rcx # 8-byte Reload movl (%rcx), %ecx movq 480(%rsp), %rdx movl (%rdx), %edx movq 488(%rsp), %rsi movl (%rsi), %esi movq 648(%rsp), %rdi movl (%rdi), %edi movl %eax, 16(%rsp) movl %ecx, 12(%rsp) movl %edx, 8(%rsp) movl %esi, 4(%rsp) movq 136(%rsp), %rax movq %rax, 64(%rsp) movq 520(%rsp), %rax movq %rax, 56(%rsp) movq 528(%rsp), %rax movq %rax, 48(%rsp) movq 536(%rsp), %rax movq %rax, 40(%rsp) movl %edi, 368(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 112(%rsp), %rax movq %rax, 152(%rsp) leaq 16(%rsp), %rax movq %rax, 160(%rsp) leaq 104(%rsp), %rax movq %rax, 168(%rsp) leaq 12(%rsp), %rax movq %rax, 176(%rsp) leaq 8(%rsp), %rax movq %rax, 184(%rsp) leaq 4(%rsp), %rax movq %rax, 192(%rsp) leaq 64(%rsp), %rax movq %rax, 200(%rsp) leaq 372(%rsp), %rax movq %rax, 208(%rsp) leaq 56(%rsp), %rax movq %rax, 216(%rsp) leaq 48(%rsp), %rax movq %rax, 224(%rsp) leaq 40(%rsp), %rax movq %rax, 232(%rsp) leaq 368(%rsp), %rax movq %rax, 240(%rsp) movq 400(%rsp), %rax # 8-byte Reload movq %rax, 120(%rsp) movq 408(%rsp), %rax # 8-byte Reload movq %rax, 112(%rsp) movsd %xmm0, 104(%rsp) movq 256(%rsp), %rax # 8-byte Reload movl %eax, 372(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB5_2: callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.5, %edi movq %rax, %rsi xorl %eax, %eax callq printf movq 544(%rsp), %rax movl (%rax), %r14d movl %r14d, %eax imull %r14d, %eax movq 648(%rsp), %rcx cmpl $0, (%rcx) movl %eax, 132(%rsp) # 4-byte Spill je .LBB5_31 # %bb.3: movq %rbp, 376(%rsp) # 8-byte Spill imull %eax, %r14d movl (%r13), %ebp movq 656(%rsp), %rcx xorps %xmm0, %xmm0 cvtsi2ssl (%rcx), %xmm0 xorps %xmm1, %xmm1 cvtsi2ss %r14d, %xmm1 movss %xmm1, 252(%rsp) # 4-byte Spill mulss %xmm1, %xmm0 xorps %xmm1, %xmm1 cvtsi2ss %ebp, %xmm1 movss %xmm1, 20(%rsp) # 4-byte Spill divss %xmm1, %xmm0 movl %eax, %r13d callq ceilf@PLT cvttss2si %xmm0, %edi orq %r12, %rdi movq %rbp, 416(%rsp) # 8-byte Spill orq %r12, %rbp movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax movq 544(%rsp), %r15 jne .LBB5_5 # %bb.4: movq 136(%rsp), %rax movl (%r15), %ecx movq 296(%rsp), %rdx movq 656(%rsp), %rsi movl (%rsi), %esi movq %rax, 120(%rsp) movl %r13d, 48(%rsp) movq 664(%rsp), %rax movq %rax, 112(%rsp) movl %ecx, 40(%rsp) movq %rdx, 104(%rsp) movl %ecx, 32(%rsp) movl %esi, 24(%rsp) movl %r14d, 16(%rsp) movl $0, 12(%rsp) movl %r14d, 8(%rsp) movl $0, 4(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 8(%rsp), %rax movq %rax, 216(%rsp) leaq 4(%rsp), %rax movq %rax, 224(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z4mxm1PdiS_iS_iiiiii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB5_5: callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.6, %edi movq %rax, %rsi xorl %eax, %eax callq printf cmpl $0, (%r15) xorps %xmm0, %xmm0 cvtsi2ss %r13d, %xmm0 movss %xmm0, 264(%rsp) # 4-byte Spill movl %r13d, %eax movq %rax, 304(%rsp) # 8-byte Spill movss 20(%rsp), %xmm1 # 4-byte Reload # xmm1 = mem[0],zero,zero,zero jle .LBB5_10 # %bb.6: # %.lr.ph movq 304(%rsp), %rax # 8-byte Reload leaq (,%rax,8), %r15 xorl %r12d, %r12d xorl %r13d, %r13d jmp .LBB5_7 .p2align 4, 0x90 .LBB5_9: # in Loop: Header=BB5_7 Depth=1 incq %r13 movq 544(%rsp), %rax movslq (%rax), %rax addq %r15, %r12 cmpq %rax, %r13 movss 20(%rsp), %xmm1 # 4-byte Reload # xmm1 = mem[0],zero,zero,zero jge .LBB5_10 .LBB5_7: # =>This Inner Loop Header: Depth=1 movq 656(%rsp), %rax xorps %xmm0, %xmm0 cvtsi2ssl (%rax), %xmm0 mulss 264(%rsp), %xmm0 # 4-byte Folded Reload divss %xmm1, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %edi movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_9 # %bb.8: # in Loop: Header=BB5_7 Depth=1 movq 544(%rsp), %rax movl (%rax), %eax movq 136(%rsp), %rcx addq %r12, %rcx movq 656(%rsp), %rdx movl (%rdx), %edx movq %rcx, 112(%rsp) movq 288(%rsp), %rcx addq %r12, %rcx movq %rcx, 104(%rsp) movl %eax, 48(%rsp) movl %eax, 40(%rsp) movl %eax, 32(%rsp) movl %edx, 24(%rsp) movq 672(%rsp), %rax movq %rax, 120(%rsp) movl $0, 16(%rsp) movl %r14d, 12(%rsp) movl %r14d, 8(%rsp) movl $0, 4(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 8(%rsp), %rax movq %rax, 216(%rsp) leaq 4(%rsp), %rax movq %rax, 224(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d movl $_Z4mxm1PdiS_iS_iiiiii, %edi leaq 144(%rsp), %r9 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 jmp .LBB5_9 .LBB5_10: # %._crit_edge callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.7, %edi movq %rax, %rsi xorl %eax, %eax callq printf movq 656(%rsp), %rax xorps %xmm0, %xmm0 cvtsi2ssl (%rax), %xmm0 mulss 252(%rsp), %xmm0 # 4-byte Folded Reload divss 20(%rsp), %xmm0 # 4-byte Folded Reload callq ceilf@PLT cvttss2si %xmm0, %edi movabsq $4294967296, %r15 # imm = 0x100000000 orq %r15, %rdi movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax movq 544(%rsp), %r12 jne .LBB5_12 # %bb.11: movl (%r12), %eax movq 136(%rsp), %rcx movq 344(%rsp), %rdx movq 656(%rsp), %rsi movl (%rsi), %esi movq 672(%rsp), %rdi movq %rdi, 120(%rsp) movl %eax, 48(%rsp) movq %rcx, 112(%rsp) movl %eax, 40(%rsp) movq %rdx, 104(%rsp) movl 132(%rsp), %eax # 4-byte Reload movl %eax, 32(%rsp) movl %esi, 24(%rsp) movl $0, 16(%rsp) movl %r14d, 12(%rsp) movl %r14d, 8(%rsp) movl $0, 4(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 8(%rsp), %rax movq %rax, 216(%rsp) leaq 4(%rsp), %rax movq %rax, 224(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z4mxm1PdiS_iS_iiiiii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB5_12: callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.8, %edi movq %rax, %rsi xorl %eax, %eax callq printf movq 656(%rsp), %rax xorps %xmm0, %xmm0 cvtsi2ssl (%rax), %xmm0 mulss 252(%rsp), %xmm0 # 4-byte Folded Reload divss 20(%rsp), %xmm0 # 4-byte Folded Reload callq ceilf@PLT cvttss2si %xmm0, %edi orq %r15, %rdi movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_14 # %bb.13: movq 656(%rsp), %rax movl (%rax), %eax movl (%r12), %ecx movl %eax, 24(%rsp) imull 256(%rsp), %eax # 4-byte Folded Reload cltq shlq $3, %rax addq 136(%rsp), %rax movq 280(%rsp), %rdx movq %rax, 120(%rsp) movl 132(%rsp), %eax # 4-byte Reload movl %eax, 48(%rsp) movq 664(%rsp), %rax movq %rax, 112(%rsp) movl %ecx, 40(%rsp) movq %rdx, 104(%rsp) movl %ecx, 32(%rsp) movl %r14d, 16(%rsp) movl $0, 12(%rsp) movl %r14d, 8(%rsp) movl $0, 4(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 8(%rsp), %rax movq %rax, 216(%rsp) leaq 4(%rsp), %rax movq %rax, 224(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z4mxm1PdiS_iS_iiiiii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB5_14: cmpl $0, (%r12) movss 20(%rsp), %xmm1 # 4-byte Reload # xmm1 = mem[0],zero,zero,zero jle .LBB5_19 # %bb.15: # %.lr.ph555 movq 304(%rsp), %rax # 8-byte Reload leaq (,%rax,8), %r15 xorl %r12d, %r12d xorl %r13d, %r13d jmp .LBB5_16 .p2align 4, 0x90 .LBB5_18: # in Loop: Header=BB5_16 Depth=1 incq %r13 movq 544(%rsp), %rax movslq (%rax), %rax addq %r15, %r12 cmpq %rax, %r13 movss 20(%rsp), %xmm1 # 4-byte Reload # xmm1 = mem[0],zero,zero,zero jge .LBB5_19 .LBB5_16: # =>This Inner Loop Header: Depth=1 movq 656(%rsp), %rax xorps %xmm0, %xmm0 cvtsi2ssl (%rax), %xmm0 mulss 264(%rsp), %xmm0 # 4-byte Folded Reload divss %xmm1, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %edi movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_18 # %bb.17: # in Loop: Header=BB5_16 Depth=1 movq 544(%rsp), %rax movl (%rax), %eax movq 656(%rsp), %rcx movl (%rcx), %ecx movl %ecx, 24(%rsp) imull 256(%rsp), %ecx # 4-byte Folded Reload movslq %ecx, %rcx shlq $3, %rcx addq 136(%rsp), %rcx addq %r12, %rcx movq %rcx, 112(%rsp) movq 272(%rsp), %rcx addq %r12, %rcx movq %rcx, 104(%rsp) movl %eax, 48(%rsp) movl %eax, 40(%rsp) movl %eax, 32(%rsp) movq 672(%rsp), %rax movq %rax, 120(%rsp) movl $0, 16(%rsp) movl %r14d, 12(%rsp) movl %r14d, 8(%rsp) movl $0, 4(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 8(%rsp), %rax movq %rax, 216(%rsp) leaq 4(%rsp), %rax movq %rax, 224(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d movl $_Z4mxm1PdiS_iS_iiiiii, %edi leaq 144(%rsp), %r9 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 jmp .LBB5_18 .LBB5_19: # %._crit_edge556 movq 656(%rsp), %rax xorps %xmm0, %xmm0 cvtsi2ssl (%rax), %xmm0 mulss 252(%rsp), %xmm0 # 4-byte Folded Reload divss %xmm1, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %edi movabsq $4294967296, %r15 # imm = 0x100000000 orq %r15, %rdi movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax movq 544(%rsp), %r12 jne .LBB5_21 # %bb.20: movl (%r12), %eax movq 656(%rsp), %rcx movl (%rcx), %ecx movl %ecx, 24(%rsp) imull 256(%rsp), %ecx # 4-byte Folded Reload movslq %ecx, %rcx shlq $3, %rcx addq 136(%rsp), %rcx movq 336(%rsp), %rdx movq 672(%rsp), %rsi movq %rsi, 120(%rsp) movl %eax, 48(%rsp) movq %rcx, 112(%rsp) movl %eax, 40(%rsp) movq %rdx, 104(%rsp) movl 132(%rsp), %eax # 4-byte Reload movl %eax, 32(%rsp) movl $0, 16(%rsp) movl %r14d, 12(%rsp) movl %r14d, 8(%rsp) movl $0, 4(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 8(%rsp), %rax movq %rax, 216(%rsp) leaq 4(%rsp), %rax movq %rax, 224(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z4mxm1PdiS_iS_iiiiii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB5_21: movq 656(%rsp), %rax xorps %xmm0, %xmm0 cvtsi2ssl (%rax), %xmm0 mulss 252(%rsp), %xmm0 # 4-byte Folded Reload divss 20(%rsp), %xmm0 # 4-byte Folded Reload callq ceilf@PLT cvttss2si %xmm0, %edi orq %r15, %rdi movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_23 # %bb.22: movq 656(%rsp), %rax movl (%rax), %eax movq 256(%rsp), %rcx # 8-byte Reload # kill: def $ecx killed $ecx killed $rcx imull %eax, %ecx addl %ecx, %ecx movslq %ecx, %rcx shlq $3, %rcx addq 136(%rsp), %rcx movl (%r12), %edx movq 328(%rsp), %rsi movq %rcx, 120(%rsp) movl 132(%rsp), %ecx # 4-byte Reload movl %ecx, 48(%rsp) movq 664(%rsp), %rcx movq %rcx, 112(%rsp) movl %edx, 40(%rsp) movq %rsi, 104(%rsp) movl %edx, 32(%rsp) movl %eax, 24(%rsp) movl %r14d, 16(%rsp) movl $0, 12(%rsp) movl %r14d, 8(%rsp) movl $0, 4(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 8(%rsp), %rax movq %rax, 216(%rsp) leaq 4(%rsp), %rax movq %rax, 224(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z4mxm1PdiS_iS_iiiiii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB5_23: cmpl $0, (%r12) movss 20(%rsp), %xmm2 # 4-byte Reload # xmm2 = mem[0],zero,zero,zero jle .LBB5_28 # %bb.24: # %.lr.ph559 movq 256(%rsp), %rax # 8-byte Reload leal (%rax,%rax), %r15d shlq $3, 304(%rsp) # 8-byte Folded Spill xorl %r12d, %r12d xorl %r13d, %r13d jmp .LBB5_25 .p2align 4, 0x90 .LBB5_27: # in Loop: Header=BB5_25 Depth=1 incq %r13 movq 544(%rsp), %rax movslq (%rax), %rax addq 304(%rsp), %r12 # 8-byte Folded Reload cmpq %rax, %r13 movss 20(%rsp), %xmm2 # 4-byte Reload # xmm2 = mem[0],zero,zero,zero jge .LBB5_28 .LBB5_25: # =>This Inner Loop Header: Depth=1 movq 656(%rsp), %rax xorps %xmm0, %xmm0 cvtsi2ssl (%rax), %xmm0 mulss 264(%rsp), %xmm0 # 4-byte Folded Reload divss %xmm2, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %edi movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_27 # %bb.26: # in Loop: Header=BB5_25 Depth=1 movq 544(%rsp), %rax movl (%rax), %eax movq 656(%rsp), %rcx movl (%rcx), %ecx movl %r15d, %edx imull %ecx, %edx movslq %edx, %rdx shlq $3, %rdx addq 136(%rsp), %rdx addq %r12, %rdx movq %rdx, 112(%rsp) movq 320(%rsp), %rdx addq %r12, %rdx movq %rdx, 104(%rsp) movl %eax, 48(%rsp) movl %eax, 40(%rsp) movl %eax, 32(%rsp) movl %ecx, 24(%rsp) movq 672(%rsp), %rax movq %rax, 120(%rsp) movl $0, 16(%rsp) movl %r14d, 12(%rsp) movl %r14d, 8(%rsp) movl $0, 4(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 8(%rsp), %rax movq %rax, 216(%rsp) leaq 4(%rsp), %rax movq %rax, 224(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d movl $_Z4mxm1PdiS_iS_iiiiii, %edi leaq 144(%rsp), %r9 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 jmp .LBB5_27 .LBB5_28: # %._crit_edge560 movq 656(%rsp), %rax xorps %xmm1, %xmm1 cvtsi2ssl (%rax), %xmm1 movss 252(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero mulss %xmm1, %xmm0 divss %xmm2, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %r12d movq %r12, %rdi movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_29 # %bb.30: movq 544(%rsp), %rax movl (%rax), %eax movq 656(%rsp), %rcx movl (%rcx), %ecx movq 256(%rsp), %rdx # 8-byte Reload # kill: def $edx killed $edx killed $rdx imull %ecx, %edx addl %edx, %edx movslq %edx, %rdx shlq $3, %rdx addq 136(%rsp), %rdx movq 312(%rsp), %rsi movq 672(%rsp), %rdi movq %rdi, 120(%rsp) movl %eax, 48(%rsp) movq %rdx, 112(%rsp) movl %eax, 40(%rsp) movq %rsi, 104(%rsp) movl 132(%rsp), %eax # 4-byte Reload movl %eax, 32(%rsp) movl %ecx, 24(%rsp) movl $0, 16(%rsp) movl %r14d, 12(%rsp) movl %r14d, 8(%rsp) movl $0, 4(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 8(%rsp), %rax movq %rax, 216(%rsp) leaq 4(%rsp), %rax movq %rax, 224(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z4mxm1PdiS_iS_iiiiii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB5_29: movq 648(%rsp), %r13 movq 376(%rsp), %rbp # 8-byte Reload jmp .LBB5_39 .LBB5_31: movq %rcx, %r13 movq 656(%rsp), %rcx xorps %xmm0, %xmm0 cvtsi2ssl (%rcx), %xmm0 xorps %xmm1, %xmm1 cvtsi2ss %eax, %xmm1 movss %xmm1, 264(%rsp) # 4-byte Spill mulss %xmm1, %xmm0 divss 20(%rsp), %xmm0 # 4-byte Folded Reload callq ceilf@PLT cvttss2si %xmm0, %edi orq %r12, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_33 # %bb.32: movq 136(%rsp), %rax movq 544(%rsp), %rcx movl (%rcx), %ecx movq 296(%rsp), %rdx movq 656(%rsp), %rsi movl (%rsi), %esi movq %rax, 120(%rsp) movl %ecx, 48(%rsp) movq 664(%rsp), %rax movq %rax, 112(%rsp) movl %ecx, 40(%rsp) movq %rdx, 104(%rsp) movl %ecx, 32(%rsp) movl %esi, 24(%rsp) movl 132(%rsp), %eax # 4-byte Reload movl %eax, 16(%rsp) movl $0, 12(%rsp) movl %eax, 8(%rsp) movl $0, 4(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 8(%rsp), %rax movq %rax, 216(%rsp) leaq 4(%rsp), %rax movq %rax, 224(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z4mxm1PdiS_iS_iiiiii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB5_33: movq 656(%rsp), %rax xorps %xmm0, %xmm0 cvtsi2ssl (%rax), %xmm0 mulss 264(%rsp), %xmm0 # 4-byte Folded Reload divss 20(%rsp), %xmm0 # 4-byte Folded Reload callq ceilf@PLT cvttss2si %xmm0, %edi orq %r12, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_35 # %bb.34: movq 544(%rsp), %rax movl (%rax), %eax movq 136(%rsp), %rcx movq 288(%rsp), %rdx movq 656(%rsp), %rsi movl (%rsi), %esi movq 672(%rsp), %rdi movq %rdi, 120(%rsp) movl %eax, 48(%rsp) movq %rcx, 112(%rsp) movl %eax, 40(%rsp) movq %rdx, 104(%rsp) movl %eax, 32(%rsp) movl %esi, 24(%rsp) movl $0, 16(%rsp) movl 132(%rsp), %eax # 4-byte Reload movl %eax, 12(%rsp) movl %eax, 8(%rsp) movl $0, 4(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 8(%rsp), %rax movq %rax, 216(%rsp) leaq 4(%rsp), %rax movq %rax, 224(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z4mxm1PdiS_iS_iiiiii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB5_35: movq 656(%rsp), %rax xorps %xmm0, %xmm0 cvtsi2ssl (%rax), %xmm0 mulss 264(%rsp), %xmm0 # 4-byte Folded Reload divss 20(%rsp), %xmm0 # 4-byte Folded Reload callq ceilf@PLT cvttss2si %xmm0, %edi orq %r12, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax movq %r12, %r14 jne .LBB5_37 # %bb.36: movq 656(%rsp), %rax movl (%rax), %eax movq 544(%rsp), %rcx movl (%rcx), %ecx movl %eax, 24(%rsp) imull 256(%rsp), %eax # 4-byte Folded Reload cltq shlq $3, %rax addq 136(%rsp), %rax movq 280(%rsp), %rdx movq %rax, 120(%rsp) movl %ecx, 48(%rsp) movq 664(%rsp), %rax movq %rax, 112(%rsp) movl %ecx, 40(%rsp) movq %rdx, 104(%rsp) movl %ecx, 32(%rsp) movl 132(%rsp), %eax # 4-byte Reload movl %eax, 16(%rsp) movl $0, 12(%rsp) movl %eax, 8(%rsp) movl $0, 4(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 8(%rsp), %rax movq %rax, 216(%rsp) leaq 4(%rsp), %rax movq %rax, 224(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z4mxm1PdiS_iS_iiiiii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB5_37: movq 656(%rsp), %rax xorps %xmm1, %xmm1 cvtsi2ssl (%rax), %xmm1 movss 264(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero mulss %xmm1, %xmm0 divss 20(%rsp), %xmm0 # 4-byte Folded Reload callq ceilf@PLT cvttss2si %xmm0, %r12d movq %r12, %rdi orq %r14, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_39 # %bb.38: movq 544(%rsp), %rax movl (%rax), %eax movq 656(%rsp), %rcx movl (%rcx), %ecx movl %ecx, 24(%rsp) imull 256(%rsp), %ecx # 4-byte Folded Reload movslq %ecx, %rcx shlq $3, %rcx addq 136(%rsp), %rcx movq 272(%rsp), %rdx movq 672(%rsp), %rsi movq %rsi, 120(%rsp) movl %eax, 48(%rsp) movq %rcx, 112(%rsp) movl %eax, 40(%rsp) movq %rdx, 104(%rsp) movl %eax, 32(%rsp) movl $0, 16(%rsp) movl 132(%rsp), %eax # 4-byte Reload movl %eax, 12(%rsp) movl %eax, 8(%rsp) movl $0, 4(%rsp) leaq 120(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 16(%rsp), %rax movq %rax, 200(%rsp) leaq 12(%rsp), %rax movq %rax, 208(%rsp) leaq 8(%rsp), %rax movq %rax, 216(%rsp) leaq 4(%rsp), %rax movq %rax, 224(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z4mxm1PdiS_iS_iiiiii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB5_39: callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.9, %edi movq %rax, %rsi xorl %eax, %eax callq printf movl %r12d, %edi movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi movl 416(%rsp), %edx # 4-byte Reload orq %rax, %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB5_41 # %bb.40: movq 352(%rsp), %rax # 8-byte Reload movl (%rax), %edx movq 384(%rsp), %rax # 8-byte Reload movsd (%rax), %xmm0 # xmm0 = mem[0],zero movq 392(%rsp), %rax # 8-byte Reload movl (%rax), %ecx movq 480(%rsp), %rax movl (%rax), %r8d movq 488(%rsp), %rax movl (%rax), %r9d movl (%r13), %eax movq 400(%rsp), %rdi # 8-byte Reload movq 408(%rsp), %rsi # 8-byte Reload pushq %rax .cfi_adjust_cfa_offset 8 pushq 648(%rsp) .cfi_adjust_cfa_offset 8 pushq 648(%rsp) .cfi_adjust_cfa_offset 8 pushq 648(%rsp) .cfi_adjust_cfa_offset 8 pushq 648(%rsp) .cfi_adjust_cfa_offset 8 pushq 648(%rsp) .cfi_adjust_cfa_offset 8 pushq 648(%rsp) .cfi_adjust_cfa_offset 8 pushq 648(%rsp) .cfi_adjust_cfa_offset 8 pushq 648(%rsp) .cfi_adjust_cfa_offset 8 pushq 648(%rsp) .cfi_adjust_cfa_offset 8 pushq 648(%rsp) .cfi_adjust_cfa_offset 8 pushq %rbp .cfi_adjust_cfa_offset 8 pushq 456(%rsp) .cfi_adjust_cfa_offset 8 pushq 416(%rsp) .cfi_adjust_cfa_offset 8 pushq 432(%rsp) .cfi_adjust_cfa_offset 8 pushq 448(%rsp) .cfi_adjust_cfa_offset 8 pushq 464(%rsp) .cfi_adjust_cfa_offset 8 pushq 408(%rsp) .cfi_adjust_cfa_offset 8 pushq 424(%rsp) .cfi_adjust_cfa_offset 8 pushq 496(%rsp) .cfi_adjust_cfa_offset 8 pushq 448(%rsp) .cfi_adjust_cfa_offset 8 pushq 464(%rsp) .cfi_adjust_cfa_offset 8 pushq 432(%rsp) # 8-byte Folded Reload .cfi_adjust_cfa_offset 8 pushq 320(%rsp) .cfi_adjust_cfa_offset 8 callq _Z39__device_stub__flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i addq $192, %rsp .cfi_adjust_cfa_offset -192 .LBB5_41: callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.10, %edi movq %rax, %rsi xorl %eax, %eax callq printf movq 136(%rsp), %rdi callq hipFree movq 296(%rsp), %rdi callq hipFree movq 280(%rsp), %rdi callq hipFree movq 328(%rsp), %rdi callq hipFree movq 288(%rsp), %rdi callq hipFree movq 272(%rsp), %rdi callq hipFree movq 320(%rsp), %rdi callq hipFree movq 344(%rsp), %rdi callq hipFree movq 336(%rsp), %rdi callq hipFree movq 312(%rsp), %rdi callq hipFree movq 360(%rsp), %rdi callq hipFree callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.11, %edi movq %rax, %rsi xorl %eax, %eax callq printf addq $424, %rsp # imm = 0x1A8 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end5: .size entropy_residual_gpu_wrapper_, .Lfunc_end5-entropy_residual_gpu_wrapper_ .cfi_endproc # -- End function .globl _Z34__device_stub__wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ # -- Begin function _Z34__device_stub__wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .p2align 4, 0x90 .type _Z34__device_stub__wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_,@function _Z34__device_stub__wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_: # @_Z34__device_stub__wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .cfi_startproc # %bb.0: subq $232, %rsp .cfi_def_cfa_offset 240 movq %rdi, 104(%rsp) movq %rsi, 96(%rsp) movq %rdx, 88(%rsp) movq %rcx, 80(%rsp) movq %r8, 72(%rsp) movl %r9d, 12(%rsp) movsd %xmm0, 64(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 80(%rsp), %rax movq %rax, 136(%rsp) leaq 72(%rsp), %rax movq %rax, 144(%rsp) leaq 12(%rsp), %rax movq %rax, 152(%rsp) leaq 240(%rsp), %rax movq %rax, 160(%rsp) leaq 248(%rsp), %rax movq %rax, 168(%rsp) leaq 256(%rsp), %rax movq %rax, 176(%rsp) leaq 264(%rsp), %rax movq %rax, 184(%rsp) leaq 272(%rsp), %rax movq %rax, 192(%rsp) leaq 280(%rsp), %rax movq %rax, 200(%rsp) leaq 64(%rsp), %rax movq %rax, 208(%rsp) leaq 288(%rsp), %rax movq %rax, 216(%rsp) leaq 296(%rsp), %rax movq %rax, 224(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $248, %rsp .cfi_adjust_cfa_offset -248 retq .Lfunc_end6: .size _Z34__device_stub__wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_, .Lfunc_end6-_Z34__device_stub__wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .cfi_endproc # -- End function .globl wavevisc_gpu_wrapper_ # -- Begin function wavevisc_gpu_wrapper_ .p2align 4, 0x90 .type wavevisc_gpu_wrapper_,@function wavevisc_gpu_wrapper_: # @wavevisc_gpu_wrapper_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $328, %rsp # imm = 0x148 .cfi_def_cfa_offset 384 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r9, 72(%rsp) # 8-byte Spill movq %r8, 64(%rsp) # 8-byte Spill movq %rcx, 56(%rsp) # 8-byte Spill movq %rdx, 48(%rsp) # 8-byte Spill movq %rsi, 40(%rsp) # 8-byte Spill movq %rdi, 80(%rsp) # 8-byte Spill movq 416(%rsp), %r13 movq 408(%rsp), %r12 movq 400(%rsp), %rbp movq 448(%rsp), %r15 movq 392(%rsp), %r14 movq 384(%rsp), %rbx callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.12, %edi movq %rax, %rsi xorl %eax, %eax callq printf movl (%rbx), %esi movl (%r14), %edx movl (%rbp), %ecx movl (%r12), %r8d movl (%r13), %r9d movq 432(%rsp), %rax movsd (%rax), %xmm0 # xmm0 = mem[0],zero movl (%r15), %r10d subq $8, %rsp .cfi_adjust_cfa_offset 8 movl $.L.str.13, %edi movb $1, %al pushq %r10 .cfi_adjust_cfa_offset 8 callq printf addq $16, %rsp .cfi_adjust_cfa_offset -16 movl (%rbx), %eax movq %rbx, %r15 movl (%r12), %r12d movl (%r13), %ecx imull (%rbp), %r12d movl %eax, %ebx imull %ecx, %ebx imull %r12d, %ebx imull %ecx, %r12d movl (%r14), %r13d imull %r12d, %eax movslq %eax, %rsi shlq $3, %rsi leaq 32(%rsp), %rdi callq hipMalloc movslq (%r15), %rsi movslq %r12d, %rbp imulq %rbp, %rsi shlq $3, %rsi movq %rsp, %rdi callq hipMalloc movq 448(%rsp), %rax movl (%rax), %eax decl %eax movl (%r14), %ecx imull %ebp, %ecx imull %eax, %ecx movslq %ecx, %rsi shlq $3, %rsi addq 424(%rsp), %rsi movq (%rsp), %rdi movslq (%r15), %rdx imulq %rbp, %rdx shlq $3, %rdx movl $3, %ecx callq hipMemcpy movq 80(%rsp), %rax # 8-byte Reload movl (%rax), %ebp xorps %xmm0, %xmm0 cvtsi2ss %ebx, %xmm0 cvtsi2ss %ebp, %xmm1 divss %xmm1, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %edi movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi orq %rax, %rbp movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB7_2 # %bb.1: movq 440(%rsp), %rax imull %r12d, %r13d movq 32(%rsp), %rcx movq 400(%rsp), %rdx movl (%rdx), %edx movq 408(%rsp), %rsi movl (%rsi), %esi movq 416(%rsp), %rdi movl (%rdi), %edi movq (%rsp), %r8 movq 432(%rsp), %r9 movsd (%r9), %xmm0 # xmm0 = mem[0],zero movq 40(%rsp), %r9 # 8-byte Reload movq %r9, 200(%rsp) movq 48(%rsp), %r9 # 8-byte Reload movq %r9, 192(%rsp) movq 56(%rsp), %r9 # 8-byte Reload movq %r9, 184(%rsp) movq 64(%rsp), %r9 # 8-byte Reload movq %r9, 176(%rsp) movq 72(%rsp), %r9 # 8-byte Reload movq %r9, 168(%rsp) movl %ebx, 28(%rsp) movq %rcx, 160(%rsp) movl %r12d, 24(%rsp) movl %edx, 20(%rsp) movl %esi, 16(%rsp) movl %edi, 12(%rsp) movq %r8, 152(%rsp) movsd %xmm0, 144(%rsp) movl %r13d, 8(%rsp) movq %rax, 136(%rsp) leaq 200(%rsp), %rax movq %rax, 208(%rsp) leaq 192(%rsp), %rax movq %rax, 216(%rsp) leaq 184(%rsp), %rax movq %rax, 224(%rsp) leaq 176(%rsp), %rax movq %rax, 232(%rsp) leaq 168(%rsp), %rax movq %rax, 240(%rsp) leaq 28(%rsp), %rax movq %rax, 248(%rsp) leaq 160(%rsp), %rax movq %rax, 256(%rsp) leaq 24(%rsp), %rax movq %rax, 264(%rsp) leaq 20(%rsp), %rax movq %rax, 272(%rsp) leaq 16(%rsp), %rax movq %rax, 280(%rsp) leaq 12(%rsp), %rax movq %rax, 288(%rsp) leaq 152(%rsp), %rax movq %rax, 296(%rsp) leaq 144(%rsp), %rax movq %rax, 304(%rsp) leaq 8(%rsp), %rax movq %rax, 312(%rsp) leaq 136(%rsp), %rax movq %rax, 320(%rsp) leaq 120(%rsp), %rdi leaq 104(%rsp), %rsi leaq 96(%rsp), %rdx leaq 88(%rsp), %rcx callq __hipPopCallConfiguration movq 120(%rsp), %rsi movl 128(%rsp), %edx movq 104(%rsp), %rcx movl 112(%rsp), %r8d leaq 208(%rsp), %r9 movl $_Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_, %edi pushq 88(%rsp) .cfi_adjust_cfa_offset 8 pushq 104(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB7_2: movq 32(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.14, %edi movq %rax, %rsi xorl %eax, %eax callq printf addq $328, %rsp # imm = 0x148 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end7: .size wavevisc_gpu_wrapper_, .Lfunc_end7-wavevisc_gpu_wrapper_ .cfi_endproc # -- End function .globl _Z39__device_stub__max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i # -- Begin function _Z39__device_stub__max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .p2align 4, 0x90 .type _Z39__device_stub__max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i,@function _Z39__device_stub__max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i: # @_Z39__device_stub__max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 72(%rsp) movl %esi, 20(%rsp) movl %edx, 16(%rsp) movl %ecx, 12(%rsp) movl %r8d, 8(%rsp) movl %r9d, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 20(%rsp), %rax movq %rax, 88(%rsp) leaq 16(%rsp), %rax movq %rax, 96(%rsp) leaq 12(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) leaq 192(%rsp), %rax movq %rax, 128(%rsp) leaq 200(%rsp), %rax movq %rax, 136(%rsp) leaq 208(%rsp), %rax movq %rax, 144(%rsp) leaq 216(%rsp), %rax movq %rax, 152(%rsp) leaq 224(%rsp), %rax movq %rax, 160(%rsp) leaq 232(%rsp), %rax movq %rax, 168(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end8: .size _Z39__device_stub__max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i, .Lfunc_end8-_Z39__device_stub__max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .cfi_endproc # -- End function .globl max_to_trilin_gpu_wrapper_ # -- Begin function max_to_trilin_gpu_wrapper_ .p2align 4, 0x90 .type max_to_trilin_gpu_wrapper_,@function max_to_trilin_gpu_wrapper_: # @max_to_trilin_gpu_wrapper_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $248, %rsp .cfi_def_cfa_offset 304 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r9, %r14 movq %r8, %r15 movq %rcx, %r12 movq %rdx, %rbp movq %rsi, 48(%rsp) # 8-byte Spill movq %rdi, 56(%rsp) # 8-byte Spill movq 336(%rsp), %rbx movq 304(%rsp), %r13 callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.15, %edi movq %rax, %rsi xorl %eax, %eax callq printf movl (%rbp), %esi movl (%r12), %edx movl (%r15), %ecx movl (%r14), %r8d movl (%r13), %r9d movl (%rbx), %r10d subq $8, %rsp .cfi_adjust_cfa_offset 8 movl $.L.str.16, %edi xorl %eax, %eax pushq %r10 .cfi_adjust_cfa_offset 8 callq printf addq $16, %rsp .cfi_adjust_cfa_offset -16 movl (%r15), %ebx movl (%r13), %r13d imull (%r14), %ebx movl (%rbp), %ebp imull %ebx, %ebp imull %r13d, %ebp movl (%r12), %eax movl %eax, 12(%rsp) # 4-byte Spill movq 56(%rsp), %rax # 8-byte Reload movl (%rax), %r12d cvtsi2ss %ebp, %xmm0 cvtsi2ss %r12d, %xmm1 divss %xmm1, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %edi movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi orq %rax, %r12 movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB9_2 # %bb.1: movq 328(%rsp), %rax movq 320(%rsp), %rcx movq 312(%rsp), %rdx imull %r13d, %ebx movl 12(%rsp), %r11d # 4-byte Reload imull %ebx, %r11d movl (%r15), %esi movl (%r14), %edi movq 304(%rsp), %r8 movl (%r8), %r8d movq 336(%rsp), %r9 movl (%r9), %r9d movl %edi, 32(%rsp) imull %esi, %edi movq 48(%rsp), %r10 # 8-byte Reload movq %r10, 136(%rsp) movl %ebp, 44(%rsp) movl %ebx, 40(%rsp) movl %esi, 36(%rsp) movl %r8d, 28(%rsp) movl %r11d, 24(%rsp) movl %edi, 20(%rsp) movq %rdx, 128(%rsp) movq %rcx, 120(%rsp) movq %rax, 112(%rsp) movl %r9d, 16(%rsp) leaq 136(%rsp), %rax movq %rax, 144(%rsp) leaq 44(%rsp), %rax movq %rax, 152(%rsp) leaq 40(%rsp), %rax movq %rax, 160(%rsp) leaq 36(%rsp), %rax movq %rax, 168(%rsp) leaq 32(%rsp), %rax movq %rax, 176(%rsp) leaq 28(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 20(%rsp), %rax movq %rax, 200(%rsp) leaq 128(%rsp), %rax movq %rax, 208(%rsp) leaq 120(%rsp), %rax movq %rax, 216(%rsp) leaq 112(%rsp), %rax movq %rax, 224(%rsp) leaq 16(%rsp), %rax movq %rax, 232(%rsp) leaq 96(%rsp), %rdi leaq 80(%rsp), %rsi leaq 72(%rsp), %rdx leaq 64(%rsp), %rcx callq __hipPopCallConfiguration movq 96(%rsp), %rsi movl 104(%rsp), %edx movq 80(%rsp), %rcx movl 88(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i, %edi pushq 64(%rsp) .cfi_adjust_cfa_offset 8 pushq 80(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB9_2: callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.17, %edi movq %rax, %rsi xorl %eax, %eax callq printf addq $248, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end9: .size max_to_trilin_gpu_wrapper_, .Lfunc_end9-max_to_trilin_gpu_wrapper_ .cfi_endproc # -- End function .globl _Z34__device_stub__resvisc_gpu_kernel1PdiiiiiiiS_ # -- Begin function _Z34__device_stub__resvisc_gpu_kernel1PdiiiiiiiS_ .p2align 4, 0x90 .type _Z34__device_stub__resvisc_gpu_kernel1PdiiiiiiiS_,@function _Z34__device_stub__resvisc_gpu_kernel1PdiiiiiiiS_: # @_Z34__device_stub__resvisc_gpu_kernel1PdiiiiiiiS_ .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 72(%rsp) movl %esi, 20(%rsp) movl %edx, 16(%rsp) movl %ecx, 12(%rsp) movl %r8d, 8(%rsp) movl %r9d, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 20(%rsp), %rax movq %rax, 88(%rsp) leaq 16(%rsp), %rax movq %rax, 96(%rsp) leaq 12(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) leaq 160(%rsp), %rax movq %rax, 128(%rsp) leaq 168(%rsp), %rax movq %rax, 136(%rsp) leaq 176(%rsp), %rax movq %rax, 144(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z19resvisc_gpu_kernel1PdiiiiiiiS_, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end10: .size _Z34__device_stub__resvisc_gpu_kernel1PdiiiiiiiS_, .Lfunc_end10-_Z34__device_stub__resvisc_gpu_kernel1PdiiiiiiiS_ .cfi_endproc # -- End function .globl resvisc_gpu_wrapper1_ # -- Begin function resvisc_gpu_wrapper1_ .p2align 4, 0x90 .type resvisc_gpu_wrapper1_,@function resvisc_gpu_wrapper1_: # @resvisc_gpu_wrapper1_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $184, %rsp .cfi_def_cfa_offset 240 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r9, %r14 movq %r8, %r15 movq %rcx, %r12 movq %rdx, %rbp movq %rsi, 32(%rsp) # 8-byte Spill movq %rdi, 40(%rsp) # 8-byte Spill movq 240(%rsp), %r13 callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.18, %edi movq %rax, %rsi xorl %eax, %eax callq printf movl (%rbp), %esi movl (%r12), %edx movl (%r15), %ecx movl (%r14), %r8d movl (%r13), %r9d movl $.L.str.19, %edi xorl %eax, %eax callq printf movl (%r15), %ebx movl (%r13), %r13d imull (%r14), %ebx movl (%rbp), %ebp imull %ebx, %ebp imull %r13d, %ebp movl (%r12), %eax movl %eax, (%rsp) # 4-byte Spill movq 40(%rsp), %rax # 8-byte Reload movl (%rax), %r12d cvtsi2ss %ebp, %xmm0 cvtsi2ss %r12d, %xmm1 divss %xmm1, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %edi movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi orq %rax, %r12 movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB11_2 # %bb.1: movq 248(%rsp), %rax imull %r13d, %ebx movl (%rsp), %r8d # 4-byte Reload imull %ebx, %r8d movl (%r15), %ecx movl (%r14), %edx movq 240(%rsp), %rsi movl (%rsi), %esi movl %edx, 16(%rsp) imull %ecx, %edx movq 32(%rsp), %rdi # 8-byte Reload movq %rdi, 104(%rsp) movl %ebp, 28(%rsp) movl %ebx, 24(%rsp) movl %ecx, 20(%rsp) movl %esi, 12(%rsp) movl %r8d, 8(%rsp) movl %edx, 4(%rsp) movq %rax, 96(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 28(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 20(%rsp), %rax movq %rax, 136(%rsp) leaq 16(%rsp), %rax movq %rax, 144(%rsp) leaq 12(%rsp), %rax movq %rax, 152(%rsp) leaq 8(%rsp), %rax movq %rax, 160(%rsp) leaq 4(%rsp), %rax movq %rax, 168(%rsp) leaq 96(%rsp), %rax movq %rax, 176(%rsp) leaq 80(%rsp), %rdi leaq 64(%rsp), %rsi leaq 56(%rsp), %rdx leaq 48(%rsp), %rcx callq __hipPopCallConfiguration movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 64(%rsp), %rcx movl 72(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z19resvisc_gpu_kernel1PdiiiiiiiS_, %edi pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB11_2: callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.20, %edi movq %rax, %rsi xorl %eax, %eax callq printf addq $184, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end11: .size resvisc_gpu_wrapper1_, .Lfunc_end11-resvisc_gpu_wrapper1_ .cfi_endproc # -- End function .globl _Z34__device_stub__resvisc_gpu_kernel2Pdiiiiiiidd # -- Begin function _Z34__device_stub__resvisc_gpu_kernel2Pdiiiiiiidd .p2align 4, 0x90 .type _Z34__device_stub__resvisc_gpu_kernel2Pdiiiiiiidd,@function _Z34__device_stub__resvisc_gpu_kernel2Pdiiiiiiidd: # @_Z34__device_stub__resvisc_gpu_kernel2Pdiiiiiiidd .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 88(%rsp) movl %esi, 20(%rsp) movl %edx, 16(%rsp) movl %ecx, 12(%rsp) movl %r8d, 8(%rsp) movl %r9d, 4(%rsp) movsd %xmm0, 80(%rsp) movsd %xmm1, 72(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 20(%rsp), %rax movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 8(%rsp), %rax movq %rax, 128(%rsp) leaq 4(%rsp), %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) leaq 80(%rsp), %rax movq %rax, 160(%rsp) leaq 72(%rsp), %rax movq %rax, 168(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z19resvisc_gpu_kernel2Pdiiiiiiidd, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end12: .size _Z34__device_stub__resvisc_gpu_kernel2Pdiiiiiiidd, .Lfunc_end12-_Z34__device_stub__resvisc_gpu_kernel2Pdiiiiiiidd .cfi_endproc # -- End function .globl resvisc_gpu_wrapper2_ # -- Begin function resvisc_gpu_wrapper2_ .p2align 4, 0x90 .type resvisc_gpu_wrapper2_,@function resvisc_gpu_wrapper2_: # @resvisc_gpu_wrapper2_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $216, %rsp .cfi_def_cfa_offset 272 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r9, %r15 movq %r8, %rbx movq %rcx, %r12 movq %rdx, %rbp movq %rsi, 40(%rsp) # 8-byte Spill movq %rdi, 48(%rsp) # 8-byte Spill movq 280(%rsp), %r13 movq 272(%rsp), %r14 callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.21, %edi movq %rax, %rsi xorl %eax, %eax callq printf movl (%rbp), %esi movl (%r12), %edx movl (%rbx), %ecx movl (%r15), %r8d movl (%r14), %r9d movsd (%r13), %xmm0 # xmm0 = mem[0],zero movq 288(%rsp), %rax movsd (%rax), %xmm1 # xmm1 = mem[0],zero movl $.L.str.22, %edi movb $2, %al callq printf movq %rbx, 32(%rsp) # 8-byte Spill movl (%rbx), %ebx movl (%r14), %r13d imull (%r15), %ebx movl (%rbp), %ebp imull %ebx, %ebp imull %r13d, %ebp movl (%r12), %r14d movq 48(%rsp), %rax # 8-byte Reload movl (%rax), %r12d xorps %xmm0, %xmm0 cvtsi2ss %ebp, %xmm0 xorps %xmm1, %xmm1 cvtsi2ss %r12d, %xmm1 divss %xmm1, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %edi movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi orq %rax, %r12 movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB13_2 # %bb.1: imull %r13d, %ebx imull %ebx, %r14d movq 32(%rsp), %rax # 8-byte Reload movl (%rax), %eax movl (%r15), %ecx movq 272(%rsp), %rdx movl (%rdx), %edx movq 280(%rsp), %rsi movsd (%rsi), %xmm0 # xmm0 = mem[0],zero movq 288(%rsp), %rsi movsd (%rsi), %xmm1 # xmm1 = mem[0],zero movl %ecx, 16(%rsp) imull %eax, %ecx movq 40(%rsp), %rsi # 8-byte Reload movq %rsi, 120(%rsp) movl %ebp, 28(%rsp) movl %ebx, 24(%rsp) movl %eax, 20(%rsp) movl %edx, 12(%rsp) movl %r14d, 8(%rsp) movl %ecx, 4(%rsp) movsd %xmm0, 112(%rsp) movsd %xmm1, 104(%rsp) leaq 120(%rsp), %rax movq %rax, 128(%rsp) leaq 28(%rsp), %rax movq %rax, 136(%rsp) leaq 24(%rsp), %rax movq %rax, 144(%rsp) leaq 20(%rsp), %rax movq %rax, 152(%rsp) leaq 16(%rsp), %rax movq %rax, 160(%rsp) leaq 12(%rsp), %rax movq %rax, 168(%rsp) leaq 8(%rsp), %rax movq %rax, 176(%rsp) leaq 4(%rsp), %rax movq %rax, 184(%rsp) leaq 112(%rsp), %rax movq %rax, 192(%rsp) leaq 104(%rsp), %rax movq %rax, 200(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 128(%rsp), %r9 movl $_Z19resvisc_gpu_kernel2Pdiiiiiiidd, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB13_2: callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.23, %edi movq %rax, %rsi xorl %eax, %eax callq printf addq $216, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end13: .size resvisc_gpu_wrapper2_, .Lfunc_end13-resvisc_gpu_wrapper2_ .cfi_endproc # -- End function .globl _Z35__device_stub__evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i # -- Begin function _Z35__device_stub__evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .p2align 4, 0x90 .type _Z35__device_stub__evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i,@function _Z35__device_stub__evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i: # @_Z35__device_stub__evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .cfi_startproc # %bb.0: subq $248, %rsp .cfi_def_cfa_offset 256 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movl %edx, 20(%rsp) movl %ecx, 16(%rsp) movl %r8d, 12(%rsp) movl %r9d, 8(%rsp) movsd %xmm0, 72(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 20(%rsp), %rax movq %rax, 112(%rsp) leaq 16(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) leaq 8(%rsp), %rax movq %rax, 136(%rsp) leaq 256(%rsp), %rax movq %rax, 144(%rsp) leaq 264(%rsp), %rax movq %rax, 152(%rsp) leaq 272(%rsp), %rax movq %rax, 160(%rsp) leaq 280(%rsp), %rax movq %rax, 168(%rsp) leaq 288(%rsp), %rax movq %rax, 176(%rsp) leaq 296(%rsp), %rax movq %rax, 184(%rsp) leaq 304(%rsp), %rax movq %rax, 192(%rsp) leaq 312(%rsp), %rax movq %rax, 200(%rsp) leaq 320(%rsp), %rax movq %rax, 208(%rsp) leaq 328(%rsp), %rax movq %rax, 216(%rsp) leaq 72(%rsp), %rax movq %rax, 224(%rsp) leaq 336(%rsp), %rax movq %rax, 232(%rsp) leaq 344(%rsp), %rax movq %rax, 240(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $264, %rsp # imm = 0x108 .cfi_adjust_cfa_offset -264 retq .Lfunc_end14: .size _Z35__device_stub__evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i, .Lfunc_end14-_Z35__device_stub__evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .cfi_endproc # -- End function .globl evnsmooth_gpu_wrapper_ # -- Begin function evnsmooth_gpu_wrapper_ .p2align 4, 0x90 .type evnsmooth_gpu_wrapper_,@function evnsmooth_gpu_wrapper_: # @evnsmooth_gpu_wrapper_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $360, %rsp # imm = 0x168 .cfi_def_cfa_offset 416 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r9, %r14 movq %r8, %r13 movq %r8, 112(%rsp) # 8-byte Spill movq %rcx, %r15 movq %rcx, 104(%rsp) # 8-byte Spill movq %rdx, 88(%rsp) # 8-byte Spill movq %rsi, 80(%rsp) # 8-byte Spill movq %rdi, 120(%rsp) # 8-byte Spill movq 432(%rsp), %r12 movq 424(%rsp), %rbp movq 416(%rsp), %rbx callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.24, %edi movq %rax, %rsi xorl %eax, %eax callq printf movl (%r15), %esi movl (%r13), %edx movl (%r14), %ecx movq %r14, %r10 movl (%rbx), %r8d movl (%rbp), %r9d movl (%r12), %eax movq %rax, 96(%rsp) # 8-byte Spill movq 440(%rsp), %rax movl (%rax), %r11d movq 448(%rsp), %rax movl (%rax), %ebx movq 456(%rsp), %rax movl (%rax), %r14d movq 464(%rsp), %rax movl (%rax), %r15d movq 472(%rsp), %rax movl (%rax), %r13d movq 480(%rsp), %rax movl (%rax), %r12d movq 488(%rsp), %rax movsd (%rax), %xmm0 # xmm0 = mem[0],zero movq 496(%rsp), %rax movl (%rax), %ebp movl $.L.str.25, %edi movb $1, %al pushq %rbp .cfi_adjust_cfa_offset 8 pushq %r12 .cfi_adjust_cfa_offset 8 pushq %r13 .cfi_adjust_cfa_offset 8 pushq %r15 movq 456(%rsp), %r15 .cfi_adjust_cfa_offset 8 pushq %r14 movq %r10, %r14 .cfi_adjust_cfa_offset 8 pushq %rbx .cfi_adjust_cfa_offset 8 pushq %r11 .cfi_adjust_cfa_offset 8 pushq 152(%rsp) # 8-byte Folded Reload .cfi_adjust_cfa_offset 8 callq printf addq $64, %rsp .cfi_adjust_cfa_offset -64 movq 104(%rsp), %rax # 8-byte Reload movl (%rax), %eax movq 416(%rsp), %rcx movl (%rcx), %ebp movl (%r15), %ecx imull (%r14), %ebp movl %eax, %ebx imull %ecx, %ebx imull %ebp, %ebx imull %ecx, %ebp movq 112(%rsp), %rcx # 8-byte Reload movl (%rcx), %r13d imull %ebp, %eax movslq %eax, %rsi shlq $3, %rsi leaq 72(%rsp), %rdi callq hipMalloc movq 120(%rsp), %rax # 8-byte Reload movl (%rax), %r12d xorps %xmm0, %xmm0 cvtsi2ss %ebx, %xmm0 cvtsi2ss %r12d, %xmm1 divss %xmm1, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %edi movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi orq %rax, %r12 movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB15_2 # %bb.1: movq 488(%rsp), %rax movsd (%rax), %xmm0 # xmm0 = mem[0],zero movl (%r14), %eax movq 416(%rsp), %rcx movl (%rcx), %ecx movl (%r15), %edx movq 432(%rsp), %rsi movl (%rsi), %esi movq 440(%rsp), %rdi movl (%rdi), %edi movq 448(%rsp), %r8 movl (%r8), %r8d movq 456(%rsp), %r9 movl (%r9), %r9d movq 464(%rsp), %r10 movl (%r10), %r10d movq 472(%rsp), %r11 movl (%r11), %r11d movq 480(%rsp), %r14 movl (%r14), %r14d movq 496(%rsp), %r15 movl (%r15), %r15d movq 80(%rsp), %r12 # 8-byte Reload movq %r12, 200(%rsp) movq 88(%rsp), %r12 # 8-byte Reload movq %r12, 192(%rsp) movl %ebx, 68(%rsp) imull %ebp, %r13d movl %ebp, 64(%rsp) movl %ecx, 56(%rsp) imull %eax, %ecx movl %eax, 60(%rsp) movl %edx, 52(%rsp) movl %r13d, 48(%rsp) movl %ecx, 44(%rsp) decl %esi movl %esi, 40(%rsp) decl %edi movl %edi, 36(%rsp) decl %r8d movl %r8d, 32(%rsp) decl %r9d movl %r9d, 28(%rsp) decl %r10d movl %r10d, 24(%rsp) decl %r11d movl %r11d, 20(%rsp) movl %r14d, 16(%rsp) movq 72(%rsp), %rax movq %rax, 176(%rsp) movl %r15d, 12(%rsp) leaq 200(%rsp), %rax movq %rax, 208(%rsp) leaq 192(%rsp), %rax movq %rax, 216(%rsp) leaq 68(%rsp), %rax movq %rax, 224(%rsp) leaq 64(%rsp), %rax movq %rax, 232(%rsp) leaq 60(%rsp), %rax movq %rax, 240(%rsp) leaq 56(%rsp), %rax movq %rax, 248(%rsp) leaq 52(%rsp), %rax movq %rax, 256(%rsp) leaq 48(%rsp), %rax movq %rax, 264(%rsp) leaq 44(%rsp), %rax movq %rax, 272(%rsp) leaq 40(%rsp), %rax movq %rax, 280(%rsp) leaq 36(%rsp), %rax movq %rax, 288(%rsp) leaq 32(%rsp), %rax movq %rax, 296(%rsp) leaq 28(%rsp), %rax movq %rax, 304(%rsp) leaq 24(%rsp), %rax movq %rax, 312(%rsp) leaq 20(%rsp), %rax movq %rax, 320(%rsp) leaq 16(%rsp), %rax movq %rax, 328(%rsp) leaq 184(%rsp), %rax movq %rax, 336(%rsp) leaq 176(%rsp), %rax movq %rax, 344(%rsp) leaq 12(%rsp), %rax movq %rax, 352(%rsp) movsd %xmm0, 184(%rsp) leaq 160(%rsp), %rdi leaq 144(%rsp), %rsi leaq 136(%rsp), %rdx leaq 128(%rsp), %rcx callq __hipPopCallConfiguration movq 160(%rsp), %rsi movl 168(%rsp), %edx movq 144(%rsp), %rcx movl 152(%rsp), %r8d leaq 208(%rsp), %r9 movl $_Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i, %edi pushq 128(%rsp) .cfi_adjust_cfa_offset 8 pushq 144(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB15_2: movq 72(%rsp), %rdi callq hipFree callq hipDeviceSynchronize callq hipPeekAtLastError movl %eax, %edi callq hipGetErrorString movl $.L.str.26, %edi movq %rax, %rsi xorl %eax, %eax callq printf addq $360, %rsp # imm = 0x168 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end15: .size evnsmooth_gpu_wrapper_, .Lfunc_end15-evnsmooth_gpu_wrapper_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB16_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB16_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z26compute_entropy_gpu_kernelPdS_S_iidddi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z4mxm1PdiS_iS_iiiiii, %esi movl $.L__unnamed_4, %edx movl $.L__unnamed_4, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_, %esi movl $.L__unnamed_5, %edx movl $.L__unnamed_5, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i, %esi movl $.L__unnamed_6, %edx movl $.L__unnamed_6, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z19resvisc_gpu_kernel1PdiiiiiiiS_, %esi movl $.L__unnamed_7, %edx movl $.L__unnamed_7, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z19resvisc_gpu_kernel2Pdiiiiiiidd, %esi movl $.L__unnamed_8, %edx movl $.L__unnamed_8, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i, %esi movl $.L__unnamed_9, %edx movl $.L__unnamed_9, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end16: .size __hip_module_ctor, .Lfunc_end16-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB17_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB17_2: retq .Lfunc_end17: .size __hip_module_dtor, .Lfunc_end17-__hip_module_dtor .cfi_endproc # -- End function .type _Z26compute_entropy_gpu_kernelPdS_S_iidddi,@object # @_Z26compute_entropy_gpu_kernelPdS_S_iidddi .section .rodata,"a",@progbits .globl _Z26compute_entropy_gpu_kernelPdS_S_iidddi .p2align 3, 0x0 _Z26compute_entropy_gpu_kernelPdS_S_iidddi: .quad _Z41__device_stub__compute_entropy_gpu_kernelPdS_S_iidddi .size _Z26compute_entropy_gpu_kernelPdS_S_iidddi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA: Start compute_entropy_gpu_wrapper cuda status: %s\n" .size .L.str, 57 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "CUDA: Start compute_entropy_gpu_wrapper values ntot = %d, irho = %d, ntol = %lf, rgam = %lf, gmaref = %lf \n" .size .L.str.1, 108 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "CUDA: End compute_engropy_wrapper cuda status: %s\n" .size .L.str.2, 51 .type _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i,@object # @_Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .section .rodata,"a",@progbits .globl _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .p2align 3, 0x0 _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i: .quad _Z47__device_stub__entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .size _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i, 8 .type _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i,@object # @_Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .globl _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .p2align 3, 0x0 _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i: .quad _Z39__device_stub__flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .size _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i, 8 .type _Z4mxm1PdiS_iS_iiiiii,@object # @_Z4mxm1PdiS_iS_iiiiii .globl _Z4mxm1PdiS_iS_iiiiii .p2align 3, 0x0 _Z4mxm1PdiS_iS_iiiiii: .quad _Z19__device_stub__mxm1PdiS_iS_iiiiii .size _Z4mxm1PdiS_iS_iiiiii, 8 .type .L.str.3,@object # @.str.3 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.3: .asciz "CUDA: Start entropy_residual_gpu_wrapper cuda status: %s\n" .size .L.str.3, 58 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "CUDA: Start entropy_residual_gpu_wrapper values rdt = %lf, stage = %d, lorder= %d,ltot = %d,lxd = %d, lyd = %d, lzd = %d, lx1 = %d,ly1 = %d,lz1 = %d,if3d = %d,nelt = %d \n" .size .L.str.4, 171 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "CUDA: entropy_residual_gpu_wrapper after kernel 1cuda status: %s\n" .size .L.str.5, 66 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "CUDA: entropy_residual_gpu_wrapper after 1st mxm 1cuda status: %s\n" .size .L.str.6, 67 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "CUDA: entropy_residual_gpu_wrapper after for loop mxm 1cuda status: %s\n" .size .L.str.7, 72 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "CUDA: entropy_residual_gpu_wrapper after 3rd mxm 1cuda status: %s\n" .size .L.str.8, 67 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "CUDA: entropy_residual_gpu_wrapper before flux_div_mini_gpu_kernel cuda status: %s\n" .size .L.str.9, 84 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "CUDA: entropy_residual_gpu_wrapper after flux_div_mini_gpu_kernel cuda status: %s\n" .size .L.str.10, 83 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "CUDA: End entropy residual_gpu_wrapper cuda status: %s\n" .size .L.str.11, 56 .type _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_,@object # @_Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .section .rodata,"a",@progbits .globl _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .p2align 3, 0x0 _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_: .quad _Z34__device_stub__wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .size _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_, 8 .type .L.str.12,@object # @.str.12 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.12: .asciz "CUDA: Start wavevisc_gpu_wrapper cuda status: %s\n" .size .L.str.12, 50 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz "CUDA: Start compute_entropy_gpu_wrapper values nelt= %d,lelt= %d,lx1= %d,ly1= %d, lz1= %d,c_max= %lf,irho= %d \n" .size .L.str.13, 112 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz "CUDA: End Wavevisc_gpu_wrapper cuda status: %s\n" .size .L.str.14, 48 .type _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i,@object # @_Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .section .rodata,"a",@progbits .globl _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .p2align 3, 0x0 _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i: .quad _Z39__device_stub__max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .size _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i, 8 .type .L.str.15,@object # @.str.15 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.15: .asciz "CUDA: Start max_to_trilin_gpu_wrapper cuda status: %s\n" .size .L.str.15, 55 .type .L.str.16,@object # @.str.16 .L.str.16: .asciz "CUDA: Start compute_entropy_gpu_wrapper values nelt=%d,lelt=%d,lx1=%d,ly1=%d,lz1=%d,if3d=%d \n" .size .L.str.16, 94 .type .L.str.17,@object # @.str.17 .L.str.17: .asciz "CUDA: End max_to_trilin_gpu_wrapper cuda status: %s\n" .size .L.str.17, 53 .type _Z19resvisc_gpu_kernel1PdiiiiiiiS_,@object # @_Z19resvisc_gpu_kernel1PdiiiiiiiS_ .section .rodata,"a",@progbits .globl _Z19resvisc_gpu_kernel1PdiiiiiiiS_ .p2align 3, 0x0 _Z19resvisc_gpu_kernel1PdiiiiiiiS_: .quad _Z34__device_stub__resvisc_gpu_kernel1PdiiiiiiiS_ .size _Z19resvisc_gpu_kernel1PdiiiiiiiS_, 8 .type .L.str.18,@object # @.str.18 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.18: .asciz "CUDA: Start resvisc_gpu_wrapper cuda status: %s\n" .size .L.str.18, 49 .type .L.str.19,@object # @.str.19 .L.str.19: .asciz "CUDA: Start compute_entropy_gpu_wrapper values nelt= %d,lelt= %d,lx1= %d,ly1= %d,lz1 = %d,\n" .size .L.str.19, 92 .type .L.str.20,@object # @.str.20 .L.str.20: .asciz "CUDA: End resvisc_gpu_wrapper cuda status: %s\n" .size .L.str.20, 47 .type _Z19resvisc_gpu_kernel2Pdiiiiiiidd,@object # @_Z19resvisc_gpu_kernel2Pdiiiiiiidd .section .rodata,"a",@progbits .globl _Z19resvisc_gpu_kernel2Pdiiiiiiidd .p2align 3, 0x0 _Z19resvisc_gpu_kernel2Pdiiiiiiidd: .quad _Z34__device_stub__resvisc_gpu_kernel2Pdiiiiiiidd .size _Z19resvisc_gpu_kernel2Pdiiiiiiidd, 8 .type .L.str.21,@object # @.str.21 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.21: .asciz "CUDA: Start resvisc_gpu_wrapper2 cuda status: %s\n" .size .L.str.21, 50 .type .L.str.22,@object # @.str.22 .L.str.22: .asciz "CUDA: Start compute_entropy_gpu_wrapper values nelt=%d,lelt=%d,lx1=%d,ly1=%d,lz1=%d,c_sub_e=%lf,maxdiff= %.20lf, \n" .size .L.str.22, 117 .type .L.str.23,@object # @.str.23 .L.str.23: .asciz "CUDA: End resvisc_gpu_wrapper2 cuda status: %s\n" .size .L.str.23, 48 .type _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i,@object # @_Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .section .rodata,"a",@progbits .globl _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .p2align 3, 0x0 _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i: .quad _Z35__device_stub__evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .size _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i, 8 .type .L.str.24,@object # @.str.24 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.24: .asciz "CUDA: Start evnsmooth_gpu_wrapper cuda status: %s\n" .size .L.str.24, 51 .type .L.str.25,@object # @.str.25 .L.str.25: .asciz "CUDA: Start compute_entropy_gpu_wrapper values nelt =%d ,lelt=%d,lx1=%d,ly1=%d,lz1=%d,kstart=%d,kend=%d,jstart=%d,jend=%d,istart=%d,iend=%d,ldim=%d ,rldim=%lf,if3d=%d,\n" .size .L.str.25, 169 .type .L.str.26,@object # @.str.26 .L.str.26: .asciz "CUDA: End evnsmooth_gpu_wrapper cuda status: %s\n" .size .L.str.26, 49 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z26compute_entropy_gpu_kernelPdS_S_iidddi" .size .L__unnamed_1, 43 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i" .size .L__unnamed_2, 56 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i" .size .L__unnamed_3, 83 .type .L__unnamed_4,@object # @3 .L__unnamed_4: .asciz "_Z4mxm1PdiS_iS_iiiiii" .size .L__unnamed_4, 22 .type .L__unnamed_5,@object # @4 .L__unnamed_5: .asciz "_Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_" .size .L__unnamed_5, 47 .type .L__unnamed_6,@object # @5 .L__unnamed_6: .asciz "_Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i" .size .L__unnamed_6, 45 .type .L__unnamed_7,@object # @6 .L__unnamed_7: .asciz "_Z19resvisc_gpu_kernel1PdiiiiiiiS_" .size .L__unnamed_7, 35 .type .L__unnamed_8,@object # @7 .L__unnamed_8: .asciz "_Z19resvisc_gpu_kernel2Pdiiiiiiidd" .size .L__unnamed_8, 35 .type .L__unnamed_9,@object # @8 .L__unnamed_9: .asciz "_Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i" .size .L__unnamed_9, 47 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z41__device_stub__compute_entropy_gpu_kernelPdS_S_iidddi .addrsig_sym _Z47__device_stub__entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .addrsig_sym _Z39__device_stub__flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .addrsig_sym _Z19__device_stub__mxm1PdiS_iS_iiiiii .addrsig_sym _Z34__device_stub__wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .addrsig_sym _Z39__device_stub__max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .addrsig_sym _Z34__device_stub__resvisc_gpu_kernel1PdiiiiiiiS_ .addrsig_sym _Z34__device_stub__resvisc_gpu_kernel2Pdiiiiiiidd .addrsig_sym _Z35__device_stub__evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z26compute_entropy_gpu_kernelPdS_S_iidddi .addrsig_sym _Z32entropy_residual_flux_gpu_kernelPdS_idiiiS_iS_S_S_i .addrsig_sym _Z24flux_div_mini_gpu_kernelPdS_idiiiS_iS_S_S_S_S_S_S_S_S_S_iS_S_S_S_S_S_S_S_S_S_i .addrsig_sym _Z4mxm1PdiS_iS_iiiiii .addrsig_sym _Z19wavevisc_gpu_kernelPdS_S_S_S_iS_iiiiS_diS_ .addrsig_sym _Z24max_to_trilin_gpu_kernelPdiiiiiiiS_S_S_i .addrsig_sym _Z19resvisc_gpu_kernel1PdiiiiiiiS_ .addrsig_sym _Z19resvisc_gpu_kernel2Pdiiiiiiidd .addrsig_sym _Z20evnsmooth_gpu_kernelPdS_iiiiiiiiiiiiiidS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
41,799
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code for sm_80 Function : _Z8mykernelv .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; EXIT ; BRA 0x20; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00075d01_00000000-6_15accfbef24c888d522c76d8c21ba6f11651febf.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z26__device_stub__Z8mykernelvv .type _Z26__device_stub__Z8mykernelvv, @function _Z26__device_stub__Z8mykernelvv: .LFB3694: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 72(%rsp), %rax subq %fs:40, %rax jne .L8 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z8mykernelv(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv .globl _Z8mykernelv .type _Z8mykernelv, @function _Z8mykernelv: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z8mykernelvv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z8mykernelv, .-_Z8mykernelv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Hello World" .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 8(%rsp) movl $1, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L14 .L12: leaq .LC0(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $0, %eax addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L14: .cfi_restore_state call _Z26__device_stub__Z8mykernelvv jmp .L12 .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1 .LC1: .string "_Z8mykernelv" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z8mykernelv(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z8mykernelv ; -- Begin function _Z8mykernelv .globl _Z8mykernelv .p2align 8 .type _Z8mykernelv,@function _Z8mykernelv: ; @_Z8mykernelv ; %bb.0: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z8mykernelv .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 0 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 0 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 1 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z8mykernelv, .Lfunc_end0-_Z8mykernelv ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 4 ; NumSgprs: 0 ; NumVgprs: 0 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 1 ; NumVGPRsForWavesPerEU: 1 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: [] .group_segment_fixed_size: 0 .kernarg_segment_align: 4 .kernarg_segment_size: 0 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z8mykernelv .private_segment_fixed_size: 0 .sgpr_count: 0 .sgpr_spill_count: 0 .symbol: _Z8mykernelv.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "15accfbef24c888d522c76d8c21ba6f11651febf.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv .p2align 4, 0x90 .type _Z23__device_stub__mykernelv,@function _Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z8mykernelv, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end0: .size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $64, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -16 movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z8mykernelv, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movl $_ZSt4cout, %edi movl $.L.str, %esi movl $11, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB1_7 # %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB1_5 # %bb.4: movzbl 67(%rbx), %eax jmp .LBB1_6 .LBB1_5: movq %rbx, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) .LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %eax, %eax addq $64, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .LBB1_7: .cfi_def_cfa_offset 80 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z8mykernelv, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z8mykernelv,@object # @_Z8mykernelv .section .rodata,"a",@progbits .globl _Z8mykernelv .p2align 3, 0x0 _Z8mykernelv: .quad _Z23__device_stub__mykernelv .size _Z8mykernelv, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Hello World" .size .L.str, 12 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z8mykernelv" .size .L__unnamed_1, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z23__device_stub__mykernelv .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z8mykernelv .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
171
2,094
1,463
2,580
113
code for sm_80
.file "tmpxft_00087db9_00000000-6_fbb337691cd157f3d98e8e06bfd9e3ec091fbf7f.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "fbb337691cd157f3d98e8e06bfd9e3ec091fbf7f.hip" .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
8
768
301
226
114
code for sm_80 Function : CUDAlogkernel .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R31, SR_CTAID.X ; MOV R19, 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, 0x10 ; S2R R0, SR_TID.X ; LDC.64 R2, c[0x4][R19] ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; IMAD R31, R31, c[0x0][0x0], R0 ; LEPC R6 ; MOV R9, 0x100 ; MOV R20, 0x80 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R9, R6 ; IADD3.X R21, ~R0, R21, R7, P0, P1 ; CALL.ABS.NOINC R2 ; LDC.64 R2, c[0x4][R19] ; IMAD.MOV.U32 R22, RZ, RZ, R4 ; IMAD.MOV.U32 R23, RZ, RZ, R5 ; IMAD.MOV.U32 R4, RZ, RZ, 0x10 ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; LEPC R6 ; MOV R9, 0x1d0 ; MOV R20, 0x150 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R9, R6 ; IADD3.X R21, ~R0, R21, R7, P0, P1 ; CALL.ABS.NOINC R2 ; LDC.64 R2, c[0x4][R19] ; IMAD.MOV.U32 R16, RZ, RZ, R4 ; IMAD.MOV.U32 R17, RZ, RZ, R5 ; IMAD.MOV.U32 R4, RZ, RZ, 0x10 ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; LEPC R6 ; MOV R9, 0x2a0 ; MOV R20, 0x220 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R9, R6 ; IADD3.X R21, ~R0, R21, R7, P0, P1 ; CALL.ABS.NOINC R2 ; LDC.64 R6, c[0x4][R19] ; IMAD.MOV.U32 R2, RZ, RZ, R5 ; HFMA2.MMA R5, -RZ, RZ, 0, 0 ; IMAD.MOV.U32 R18, RZ, RZ, R4 ; IMAD.MOV.U32 R4, RZ, RZ, 0x10 ; LEPC R8 ; MOV R3, 0x370 ; MOV R20, 0x2f0 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R8 ; IADD3.X R21, ~R0, R21, R9, P0, P1 ; CALL.ABS.NOINC R6 ; IMAD.MOV.U32 R6, RZ, RZ, 0x8 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R8, R31, R6, c[0x0][0x188] ; LDG.E.64 R8, [R8.64] ; IMAD.WIDE R6, R31, R6, c[0x0][0x180] ; LDG.E.64 R6, [R6.64] ; IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x160] ; BSSY B0, 0x5c0 ; IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x164] ; IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; IMAD.WIDE R36, R31, 0x10, R22 ; DADD R32, R20, -c[0x0][0x168] ; MUFU.RCP64H R11, R33 ; DFMA R12, -R32, R10, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R10, R12, R10 ; DFMA R10, -R32, R12, 1 ; DFMA R10, R12, R10, R12 ; DADD R8, R8, R8 ; DMUL R12, R8, -R10 ; DADD R34, R6, R6 ; DFMA R14, -R32, R12, -R8 ; DFMA R10, R10, R14, R12 ; DADD R14, -RZ, -R8 ; DADD R8, R20, c[0x0][0x168] ; FFMA R0, RZ, R33, R11 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DADD R34, -R34, R8 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x5b0 ; IMAD.MOV.U32 R6, RZ, RZ, R32 ; MOV R0, 0x590 ; IMAD.MOV.U32 R21, RZ, RZ, R33 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R10, RZ, RZ, R24 ; IMAD.MOV.U32 R11, RZ, RZ, R25 ; BSYNC B0 ; MUFU.RCP64H R7, R33 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R35|, 6.5827683646048100446e-37, PT ; BSSY B0, 0x740 ; DFMA R8, -R32, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R32, R8, 1 ; DFMA R12, R8, R6, R8 ; DMUL R8, R34, R12 ; DFMA R6, -R32, R8, R34 ; DFMA R8, R12, R6, R8 ; FFMA R0, RZ, R33, R9 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x730 ; IMAD.MOV.U32 R14, RZ, RZ, R34 ; MOV R0, 0x710 ; IMAD.MOV.U32 R15, RZ, RZ, R35 ; IMAD.MOV.U32 R6, RZ, RZ, R32 ; IMAD.MOV.U32 R21, RZ, RZ, R33 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R8, RZ, RZ, R24 ; MOV R9, R25 ; BSYNC B0 ; DSETP.GE.AND P0, PT, R8.reuse, -1, PT ; ULDC.64 UR4, c[0x0][0x118] ; BSSY B1, 0x4400 ; ST.E.128 [R36.64], R8 ; BSSY B0, 0x2630 ; IMAD.WIDE R16, R31, 0x10, R16 ; DSETP.GTU.OR P0, PT, R8, 1, !P0 ; @P0 BRA 0x2600 ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R36.64+0x8] ; DSETP.GTU.AND P0, PT, |R10|, c[0x2][0x0], PT ; @!P0 BREAK B0 ; @P0 BRA 0x2620 ; DSETP.NEU.AND P0, PT, R10, RZ, PT ; BSSY B3, 0x16b0 ; DADD R30, -R8, 1 ; DADD R32, -RZ, -R10 ; DSETP.NEU.OR P0, PT, R30, RZ, P0 ; @!P0 CS2R R30, SRZ ; @!P0 BRA 0x16a0 ; LOP3.LUT R0, R33, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; ISETP.NE.OR P0, PT, R32, RZ, P0 ; @!P0 IMAD.MOV.U32 R30, RZ, RZ, 0x0 ; @!P0 IMAD.MOV.U32 R31, RZ, RZ, 0x7ff00000 ; @!P0 BRA 0x16a0 ; DSETP.GTU.AND P0, PT, |R30|, +INF , PT ; @P0 BRA 0x1520 ; LOP3.LUT R0, R31, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; ISETP.NE.OR P0, PT, R30, RZ, P0 ; @P0 BRA 0xa00 ; ISETP.GT.AND P0, PT, R31, -0x1, PT ; DADD R6, R10, -R10 ; IMAD.MOV.U32 R0, RZ, RZ, R33 ; @!P0 LOP3.LUT R0, R0, 0x80000000, RZ, 0xc0, !PT ; @!P0 DADD R30, -RZ, |R6| ; @P0 LOP3.LUT R3, R7, 0x7fffffff, RZ, 0xc0, !PT ; @P0 IMAD.MOV.U32 R32, RZ, RZ, R6 ; @!P0 LOP3.LUT R0, R0, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R32, RZ, RZ, RZ ; @P0 LOP3.LUT R33, R3, 0x80000000, R33, 0xf8, !PT ; @!P0 IMAD.MOV.U32 R33, RZ, RZ, R0 ; BRA 0x16a0 ; DSETP.GE.AND P0, PT, |R32|, c[0x2][0x8], PT ; BSSY B2, 0xae0 ; DSETP.LTU.AND P0, PT, |R30|, c[0x2][0x8], !P0 ; @!P0 DMUL R30, R30, 0.25 ; @!P0 IMAD.MOV.U32 R36, RZ, RZ, 0x1 ; @!P0 DMUL R32, R10, -0.25 ; @!P0 BRA 0xad0 ; DSETP.GTU.AND P0, PT, |R32|, 4.4501477170144027662e-308, PT ; IMAD.MOV.U32 R36, RZ, RZ, RZ ; DSETP.GTU.OR P0, PT, |R30|, 4.4501477170144027662e-308, P0 ; @!P0 DMUL R30, R30, 4 ; @!P0 IMAD.MOV.U32 R36, RZ, RZ, 0x2 ; @!P0 DMUL R32, R10, -4 ; BSYNC B2 ; DADD R6, -RZ, |R32| ; IMAD.MOV.U32 R19, RZ, RZ, c[0x2][0x14] ; BSSY B4, 0x1480 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; DADD R12, -RZ, |R30| ; IMAD.MOV.U32 R28, RZ, RZ, 0x0 ; IMAD.MOV.U32 R29, RZ, RZ, 0x3fd80000 ; DSETP.GE.AND P2, PT, R30, RZ, PT ; ISETP.GT.U32.AND P1, PT, R6.reuse, R12.reuse, PT ; ISETP.LT.U32.AND P0, PT, R6.reuse, R12.reuse, PT ; ISETP.GT.U32.AND.EX P1, PT, R7.reuse, R13.reuse, PT, P1 ; ISETP.LT.U32.AND.EX P0, PT, R7.reuse, R13.reuse, PT, P0 ; SEL R27, R7, R13, P1 ; SEL R3, R6, R12, P0 ; SEL R34, R7, R13, P0 ; LOP3.LUT R0, R27, 0xffc00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R22, RZ, RZ, R3 ; SEL R26, R6, R12, P1 ; IMAD.MOV.U32 R23, RZ, RZ, R34 ; IADD3 R13, -R0, 0x7fd00000, RZ ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; DMUL R14, R12, R22 ; DMUL R12, R12, R26 ; DMUL R14, R14, R14 ; DFMA R14, R12, R12, R14 ; DSETP.MIN.AND P0, P1, R14, c[0x2][0x10], PT ; IMAD.MOV.U32 R12, RZ, RZ, R15 ; FSEL R13, R12, c[0x2][0x14], P0 ; MOV R12, R14 ; @P1 LOP3.LUT R13, R19, 0x80000, RZ, 0xfc, !PT ; SEL R12, R12, c[0x2][0x10], P0 ; DSETP.NEU.AND P0, PT, R22, RZ, PT ; MUFU.RSQ64H R21, R13 ; ISETP.GE.U32.AND P1, PT, R34, 0x7ff00000, PT ; DMUL R22, R20, R20 ; DFMA R22, R12, -R22, 1 ; DMUL R24, R20, R22 ; DFMA R22, R22, R28, 0.5 ; DFMA R22, R22, R24, R20 ; LOP3.LUT R21, R0, 0x100000, RZ, 0xfc, !PT ; DMUL R22, R14, R22 ; DMUL R22, R22, R20 ; @!P1 FSEL R3, R26, R22, !P0 ; @!P1 FSEL R34, R27, R23, !P0 ; IMAD.MOV.U32 R12, RZ, RZ, R3 ; IMAD.MOV.U32 R13, RZ, RZ, R34 ; @!P2 BRA 0x1120 ; DADD R30, R12, R30 ; BSSY B5, 0xf70 ; DMUL R20, R30, 0.5 ; MUFU.RSQ64H R7, R21 ; IADD3 R6, R21, -0x3500000, RZ ; ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ; DMUL R12, R6, R6 ; DFMA R12, R20, -R12, 1 ; DFMA R14, R12, R28, 0.5 ; DMUL R12, R6, R12 ; DFMA R14, R14, R12, R6 ; DMUL R22, R20, R14 ; IADD3 R13, R15, -0x100000, RZ ; IMAD.MOV.U32 R12, RZ, RZ, R14 ; DFMA R24, R22, -R22, R20 ; DFMA R30, R24, R12, R22 ; @!P0 BRA 0xf60 ; IMAD.MOV.U32 R0, RZ, RZ, R14 ; MOV R19, 0xf40 ; IMAD.MOV.U32 R12, RZ, RZ, R20 ; IMAD.MOV.U32 R14, RZ, RZ, R6 ; IMAD.MOV.U32 R3, RZ, RZ, R13 ; CALL.REL.NOINC 0x6f20 ; IMAD.MOV.U32 R30, RZ, RZ, R38 ; IMAD.MOV.U32 R31, RZ, RZ, R39 ; BSYNC B5 ; DADD R20, R30, R30 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R33|, 6.5827683646048100446e-37, PT ; BSSY B5, 0x10f0 ; MUFU.RCP64H R7, R21 ; DFMA R12, -R20, R6, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R6, R12, R6 ; DFMA R6, -R20, R12, 1 ; DFMA R6, R12, R6, R12 ; DMUL R12, R6, R32 ; DFMA R14, -R20, R12, R32 ; DFMA R6, R6, R14, R12 ; FFMA R0, RZ, R21, R7 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x10e0 ; IMAD.MOV.U32 R14, RZ, RZ, R32 ; MOV R15, R33 ; IMAD.MOV.U32 R6, RZ, RZ, R20 ; MOV R0, 0x10c0 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R6, RZ, RZ, R24 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; BSYNC B5 ; IMAD.MOV.U32 R32, RZ, RZ, R6 ; IMAD.MOV.U32 R33, RZ, RZ, R7 ; BRA 0x1470 ; DADD R30, R12, -R30 ; BSSY B5, 0x12c0 ; DMUL R30, R30, 0.5 ; MUFU.RSQ64H R15, R31 ; IADD3 R14, R31, -0x3500000, RZ ; ISETP.GE.U32.AND P0, PT, R14, 0x7ca00000, PT ; DMUL R12, R14, R14 ; DFMA R12, R30, -R12, 1 ; DFMA R20, R12, R28, 0.5 ; DMUL R12, R14, R12 ; DFMA R20, R20, R12, R14 ; DMUL R22, R30, R20 ; IADD3 R13, R21, -0x100000, RZ ; IMAD.MOV.U32 R12, RZ, RZ, R20 ; DFMA R24, R22, -R22, R30 ; DFMA R34, R24, R12, R22 ; @!P0 BRA 0x12b0 ; IMAD.MOV.U32 R0, RZ, RZ, R20 ; MOV R19, 0x1290 ; IMAD.MOV.U32 R12, RZ, RZ, R30 ; IMAD.MOV.U32 R21, RZ, RZ, R31 ; IMAD.MOV.U32 R3, RZ, RZ, R13 ; CALL.REL.NOINC 0x6f20 ; IMAD.MOV.U32 R34, RZ, RZ, R38 ; IMAD.MOV.U32 R35, RZ, RZ, R39 ; BSYNC B5 ; DADD R22, R34, R34 ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; BSSY B5, 0x1440 ; MUFU.RCP64H R13, R23 ; DFMA R14, -R22, R12, 1 ; DFMA R14, R14, R14, R14 ; DFMA R14, R12, R14, R12 ; DFMA R12, -R22, R14, 1 ; DFMA R12, R14, R12, R14 ; DMUL R14, R12, |R32| ; DFMA R20, -R22, R14, |R32| ; DFMA R30, R12, R20, R14 ; FFMA R0, RZ, R23, R31 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1430 ; DADD R14, -RZ, |R32| ; IMAD.MOV.U32 R6, RZ, RZ, R22 ; MOV R21, R23 ; MOV R0, 0x1410 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R30, RZ, RZ, R24 ; IMAD.MOV.U32 R31, RZ, RZ, R25 ; BSYNC B5 ; LOP3.LUT R3, R35, 0x7fffffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R32, RZ, RZ, R34 ; LOP3.LUT R33, R3, 0x80000000, R33, 0xf8, !PT ; BSYNC B4 ; ISETP.NE.AND P0, PT, R36, 0x1, PT ; @!P0 BRA 0x14f0 ; ISETP.NE.AND P0, PT, R36, 0x2, PT ; @P0 BRA 0x16a0 ; DMUL R32, R32, 0.5 ; DMUL R30, R30, 0.5 ; BRA 0x16a0 ; DADD R32, R32, R32 ; DADD R30, R30, R30 ; BRA 0x16a0 ; DADD R20, R10, -R10 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B4, 0x16a0 ; MUFU.RCP64H R7, R21 ; FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R12, -R20, R6, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R6, R12, R6 ; DFMA R6, -R20, R12, 1 ; DFMA R6, R12, R6, R12 ; DMUL R12, R20, R6 ; DFMA R14, -R20, R12, R20 ; DFMA R32, R6, R14, R12 ; FFMA R0, RZ, R21, R33 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1690 ; IMAD.MOV.U32 R14, RZ, RZ, R20.reuse ; MOV R0, 0x1670 ; IMAD.MOV.U32 R15, RZ, RZ, R21 ; IMAD.MOV.U32 R6, RZ, RZ, R20 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R32, RZ, RZ, R24 ; IMAD.MOV.U32 R33, RZ, RZ, R25 ; BSYNC B4 ; BSYNC B3 ; DADD R36, R8, 1 ; BSSY B3, 0x2570 ; DFMA R34, RZ, R30, -R32 ; DSETP.NEU.AND P0, PT, R36, RZ, PT ; DFMA R30, RZ, R32, R30 ; DSETP.NEU.OR P0, PT, R10, RZ, P0 ; @!P0 CS2R R36, SRZ ; @!P0 IMAD.MOV.U32 R6, RZ, RZ, R10 ; @!P0 IMAD.MOV.U32 R7, RZ, RZ, R11 ; @!P0 BRA 0x2560 ; LOP3.LUT R0, R11, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; ISETP.NE.OR P0, PT, R10, RZ, P0 ; @!P0 IMAD.MOV.U32 R36, RZ, RZ, 0x0 ; @!P0 MOV R7, R11 ; @!P0 IMAD.MOV.U32 R37, RZ, RZ, 0x7ff00000 ; @!P0 IMAD.MOV.U32 R6, RZ, RZ, R10 ; @!P0 BRA 0x2560 ; DSETP.GTU.AND P0, PT, |R36|, +INF , PT ; @P0 BRA 0x23e0 ; LOP3.LUT R0, R37, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; ISETP.NE.OR P0, PT, R36, RZ, P0 ; @P0 BRA 0x18d0 ; ISETP.GT.AND P0, PT, R37, -0x1, PT ; DADD R6, R10, -R10 ; @!P0 LOP3.LUT R0, R11, 0x80000000, RZ, 0xc0, !PT ; @!P0 DADD R36, -RZ, |R6| ; @P0 LOP3.LUT R3, R7, 0x7fffffff, RZ, 0xc0, !PT ; @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; @!P0 LOP3.LUT R0, R0, 0x7ff00000, RZ, 0xfc, !PT ; @P0 LOP3.LUT R7, R3, 0x80000000, R11, 0xf8, !PT ; @!P0 IMAD.MOV.U32 R7, RZ, RZ, R0 ; BRA 0x2560 ; DSETP.GE.AND P0, PT, |R10|, c[0x2][0x8], PT ; BSSY B2, 0x19d0 ; DSETP.LTU.AND P0, PT, |R36|, c[0x2][0x8], !P0 ; @!P0 DMUL R36, R36, 0.25 ; @!P0 IMAD.MOV.U32 R40, RZ, RZ, 0x1 ; @!P0 DMUL R32, R10, 0.25 ; @!P0 BRA 0x19c0 ; DSETP.GTU.AND P0, PT, |R10|, 4.4501477170144027662e-308, PT ; IMAD.MOV.U32 R32, RZ, RZ, R10 ; IMAD.MOV.U32 R33, RZ, RZ, R11 ; IMAD.MOV.U32 R40, RZ, RZ, RZ ; DSETP.GTU.OR P0, PT, |R36|, 4.4501477170144027662e-308, P0 ; @!P0 DMUL R36, R36, 4 ; @!P0 IMAD.MOV.U32 R40, RZ, RZ, 0x2 ; @!P0 DMUL R32, R10, 4 ; BSYNC B2 ; DADD R6, -RZ, |R32| ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; MOV R20, RZ ; IMAD.MOV.U32 R28, RZ, RZ, 0x0 ; DADD R14, -RZ, |R36| ; IMAD.MOV.U32 R29, RZ, RZ, 0x3fd80000 ; BSSY B4, 0x2340 ; DSETP.GE.AND P2, PT, R36, RZ, PT ; ISETP.GT.U32.AND P1, PT, R6.reuse, R14.reuse, PT ; ISETP.LT.U32.AND P0, PT, R6.reuse, R14.reuse, PT ; ISETP.GT.U32.AND.EX P1, PT, R7.reuse, R15.reuse, PT, P1 ; ISETP.LT.U32.AND.EX P0, PT, R7.reuse, R15.reuse, PT, P0 ; SEL R27, R7, R15, P1 ; SEL R3, R6, R14, P0 ; LOP3.LUT R0, R27, 0xffc00000, RZ, 0xc0, !PT ; SEL R38, R7, R15, P0 ; IMAD.MOV.U32 R22, RZ, RZ, R3 ; SEL R26, R6, R14, P1 ; IADD3 R13, -R0, 0x7fd00000, RZ ; IMAD.MOV.U32 R23, RZ, RZ, R38 ; DMUL R14, R12, R26 ; DMUL R12, R12, R22 ; DMUL R12, R12, R12 ; DFMA R12, R14, R14, R12 ; DSETP.MIN.AND P0, P1, R12, c[0x2][0x10], PT ; IMAD.MOV.U32 R14, RZ, RZ, R13 ; FSEL R15, R14, c[0x2][0x14], P0 ; IMAD.MOV.U32 R14, RZ, RZ, c[0x2][0x14] ; @P1 LOP3.LUT R15, R14, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R14, RZ, RZ, R12 ; ISETP.GE.U32.AND P1, PT, R38, 0x7ff00000, PT ; MUFU.RSQ64H R21, R15 ; SEL R14, R14, c[0x2][0x10], P0 ; DSETP.NEU.AND P0, PT, R22, RZ, PT ; DMUL R22, R20, R20 ; DFMA R22, R14, -R22, 1 ; DMUL R24, R20, R22 ; DFMA R22, R22, R28, 0.5 ; DFMA R22, R22, R24, R20 ; DMUL R22, R12, R22 ; LOP3.LUT R13, R0, 0x100000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; DMUL R22, R22, R12 ; @!P1 FSEL R3, R26, R22, !P0 ; @!P1 FSEL R38, R27, R23, !P0 ; IMAD.MOV.U32 R12, RZ, RZ, R3 ; IMAD.MOV.U32 R13, RZ, RZ, R38 ; @!P2 BRA 0x2000 ; DADD R36, R12, R36 ; BSSY B5, 0x1e70 ; DMUL R20, R36, 0.5 ; MUFU.RSQ64H R7, R21 ; IADD3 R6, R21, -0x3500000, RZ ; ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ; DMUL R12, R6, R6 ; DFMA R12, R20, -R12, 1 ; DFMA R14, R12, R28, 0.5 ; DMUL R12, R6, R12 ; DFMA R14, R14, R12, R6 ; DMUL R22, R20, R14 ; IADD3 R13, R15, -0x100000, RZ ; IMAD.MOV.U32 R12, RZ, RZ, R14 ; DFMA R24, R22, -R22, R20 ; DFMA R36, R24, R12, R22 ; @!P0 BRA 0x1e60 ; IMAD.MOV.U32 R0, RZ, RZ, R14 ; MOV R19, 0x1e40 ; IMAD.MOV.U32 R12, RZ, RZ, R20 ; IMAD.MOV.U32 R14, RZ, RZ, R6 ; IMAD.MOV.U32 R3, RZ, RZ, R13 ; CALL.REL.NOINC 0x6f20 ; IMAD.MOV.U32 R36, RZ, RZ, R38 ; IMAD.MOV.U32 R37, RZ, RZ, R39 ; BSYNC B5 ; DADD R20, R36, R36 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R33|, 6.5827683646048100446e-37, PT ; BSSY B5, 0x1ff0 ; MUFU.RCP64H R7, R21 ; DFMA R12, -R20, R6, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R6, R12, R6 ; DFMA R6, -R20, R12, 1 ; DFMA R6, R12, R6, R12 ; DMUL R12, R6, R32 ; DFMA R14, -R20, R12, R32 ; DFMA R6, R6, R14, R12 ; FFMA R0, RZ, R21, R7 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1fe0 ; MOV R14, R32 ; IMAD.MOV.U32 R15, RZ, RZ, R33 ; MOV R0, 0x1fc0 ; IMAD.MOV.U32 R6, RZ, RZ, R20 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R6, RZ, RZ, R24 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; BSYNC B5 ; BRA 0x2330 ; DADD R36, R12, -R36 ; BSSY B5, 0x2180 ; DMUL R36, R36, 0.5 ; MUFU.RSQ64H R15, R37 ; IADD3 R14, R37, -0x3500000, RZ ; ISETP.GE.U32.AND P0, PT, R14, 0x7ca00000, PT ; DMUL R12, R14, R14 ; DFMA R12, R36, -R12, 1 ; DFMA R20, R12, R28, 0.5 ; DMUL R12, R14, R12 ; DFMA R20, R20, R12, R14 ; DMUL R22, R36, R20 ; IADD3 R13, R21, -0x100000, RZ ; IMAD.MOV.U32 R12, RZ, RZ, R20 ; DFMA R24, R22, -R22, R36 ; DFMA R38, R24, R12, R22 ; @!P0 BRA 0x2170 ; IMAD.MOV.U32 R0, RZ, RZ, R20 ; MOV R19, 0x2170 ; IMAD.MOV.U32 R12, RZ, RZ, R36 ; IMAD.MOV.U32 R21, RZ, RZ, R37 ; IMAD.MOV.U32 R3, RZ, RZ, R13 ; CALL.REL.NOINC 0x6f20 ; BSYNC B5 ; DADD R22, R38, R38 ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; BSSY B5, 0x2300 ; MUFU.RCP64H R13, R23 ; DFMA R14, -R22, R12, 1 ; DFMA R14, R14, R14, R14 ; DFMA R14, R12, R14, R12 ; DFMA R12, -R22, R14, 1 ; DFMA R12, R14, R12, R14 ; DMUL R14, R12, |R32| ; DFMA R20, -R22, R14, |R32| ; DFMA R36, R12, R20, R14 ; FFMA R0, RZ, R23, R37 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x22f0 ; DADD R14, -RZ, |R32| ; IMAD.MOV.U32 R6, RZ, RZ, R22 ; MOV R0, 0x22d0 ; IMAD.MOV.U32 R21, RZ, RZ, R23 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R36, RZ, RZ, R24 ; MOV R37, R25 ; BSYNC B5 ; LOP3.LUT R7, R39, 0x7fffffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R6, RZ, RZ, R38 ; LOP3.LUT R7, R7, 0x80000000, R33, 0xf8, !PT ; BSYNC B4 ; ISETP.NE.AND P0, PT, R40, 0x1, PT ; @!P0 BRA 0x23b0 ; ISETP.NE.AND P0, PT, R40, 0x2, PT ; @P0 BRA 0x2560 ; DMUL R6, R6, 0.5 ; DMUL R36, R36, 0.5 ; BRA 0x2560 ; DADD R6, R6, R6 ; DADD R36, R36, R36 ; BRA 0x2560 ; DADD R20, R10, -R10 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B4, 0x2560 ; MUFU.RCP64H R7, R21 ; FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R12, -R20, R6, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R6, R12, R6 ; DFMA R6, -R20, R12, 1 ; DFMA R6, R12, R6, R12 ; DMUL R12, R20, R6 ; DFMA R14, -R20, R12, R20 ; DFMA R6, R6, R14, R12 ; FFMA R0, RZ, R21, R7 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2550 ; IMAD.MOV.U32 R14, RZ, RZ, R20.reuse ; MOV R0, 0x2530 ; IMAD.MOV.U32 R15, RZ, RZ, R21 ; IMAD.MOV.U32 R6, RZ, RZ, R20 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R6, RZ, RZ, R24 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; BSYNC B4 ; BSYNC B3 ; DMUL R12, R30, R36 ; ULDC.64 UR4, c[0x0][0x118] ; DMUL R30, R30, R6 ; DFMA R12, R34, R6, R12 ; DFMA R30, R34, R36, -R30 ; DADD R14, R10, R12 ; DADD R12, R30, R8 ; ST.E.128 [R16.64], R12 ; BRA 0x43f0 ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R36.64+0x8] ; BSYNC B0 ; DSETP.NEU.AND P0, PT, R10, RZ, PT ; BSSY B3, 0x34e0 ; DADD R30, R8, -1 ; DSETP.NEU.OR P1, PT, R30, RZ, P0 ; @!P1 CS2R R30, SRZ ; @!P1 IMAD.MOV.U32 R32, RZ, RZ, R10 ; @!P1 IMAD.MOV.U32 R33, RZ, RZ, R11 ; @!P1 BRA 0x34d0 ; LOP3.LUT R0, R11, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R0, 0x7ff00000, PT ; ISETP.NE.OR P1, PT, R10, RZ, P1 ; @!P1 IMAD.MOV.U32 R30, RZ, RZ, 0x0 ; @!P1 IMAD.MOV.U32 R31, RZ, RZ, 0x7ff00000 ; @!P1 IMAD.MOV.U32 R32, RZ, RZ, R10 ; @!P1 IMAD.MOV.U32 R33, RZ, RZ, R11 ; @!P1 BRA 0x34d0 ; DSETP.GTU.AND P1, PT, |R30|, +INF , PT ; @P1 BRA 0x3350 ; LOP3.LUT R0, R31, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R0, 0x7ff00000, PT ; ISETP.NE.OR P1, PT, R30, RZ, P1 ; @P1 BRA 0x2830 ; ISETP.GT.AND P1, PT, R31, -0x1, PT ; DADD R32, R10, -R10 ; @!P1 LOP3.LUT R0, R11, 0x80000000, RZ, 0xc0, !PT ; @!P1 DADD R30, -RZ, |R32| ; @P1 LOP3.LUT R3, R33, 0x7fffffff, RZ, 0xc0, !PT ; @!P1 LOP3.LUT R0, R0, 0x7ff00000, RZ, 0xfc, !PT ; @P1 LOP3.LUT R33, R3, 0x80000000, R11, 0xf8, !PT ; @!P1 MOV R32, RZ ; @!P1 IMAD.MOV.U32 R33, RZ, RZ, R0 ; BRA 0x34d0 ; DSETP.GE.AND P1, PT, |R10|, c[0x2][0x8], PT ; BSSY B2, 0x2930 ; DSETP.LTU.AND P1, PT, |R30|, c[0x2][0x8], !P1 ; @!P1 DMUL R30, R30, 0.25 ; @!P1 IMAD.MOV.U32 R36, RZ, RZ, 0x1 ; @!P1 DMUL R32, R10, 0.25 ; @!P1 BRA 0x2920 ; DSETP.GTU.AND P1, PT, |R10|, 4.4501477170144027662e-308, PT ; IMAD.MOV.U32 R32, RZ, RZ, R10 ; IMAD.MOV.U32 R33, RZ, RZ, R11 ; IMAD.MOV.U32 R36, RZ, RZ, RZ ; DSETP.GTU.OR P1, PT, |R30|, 4.4501477170144027662e-308, P1 ; @!P1 DMUL R30, R30, 4 ; @!P1 IMAD.MOV.U32 R36, RZ, RZ, 0x2 ; @!P1 DMUL R32, R10, 4 ; BSYNC B2 ; DADD R6, -RZ, |R32| ; IMAD.MOV.U32 R19, RZ, RZ, c[0x2][0x14] ; BSSY B4, 0x32b0 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; DADD R12, -RZ, |R30| ; IMAD.MOV.U32 R34, RZ, RZ, 0x0 ; IMAD.MOV.U32 R35, RZ, RZ, 0x3fd80000 ; DSETP.GE.AND P3, PT, R30, RZ, PT ; ISETP.GT.U32.AND P2, PT, R6.reuse, R12.reuse, PT ; ISETP.LT.U32.AND P1, PT, R6.reuse, R12.reuse, PT ; ISETP.GT.U32.AND.EX P2, PT, R7.reuse, R13.reuse, PT, P2 ; ISETP.LT.U32.AND.EX P1, PT, R7.reuse, R13.reuse, PT, P1 ; SEL R29, R7, R13, P2 ; SEL R26, R6, R12, P1 ; LOP3.LUT R0, R29, 0xffc00000, RZ, 0xc0, !PT ; SEL R27, R7, R13, P1 ; SEL R28, R6, R12, P2 ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; IADD3 R13, -R0, 0x7fd00000, RZ ; DMUL R14, R12, R26 ; DMUL R12, R12, R28 ; DMUL R14, R14, R14 ; DFMA R14, R12, R12, R14 ; DSETP.MIN.AND P1, P2, R14, c[0x2][0x10], PT ; IMAD.MOV.U32 R3, RZ, RZ, R15 ; FSEL R13, R3, c[0x2][0x14], P1 ; IMAD.MOV.U32 R3, RZ, RZ, R14 ; @P2 LOP3.LUT R13, R19, 0x80000, RZ, 0xfc, !PT ; SEL R12, R3, c[0x2][0x10], P1 ; DSETP.NEU.AND P1, PT, R26, RZ, PT ; MUFU.RSQ64H R21, R13 ; ISETP.GE.U32.AND P2, PT, R27, 0x7ff00000, PT ; DMUL R22, R20, R20 ; DFMA R22, R12, -R22, 1 ; DMUL R24, R20, R22 ; DFMA R22, R22, R34, 0.5 ; DFMA R22, R22, R24, R20 ; LOP3.LUT R21, R0, 0x100000, RZ, 0xfc, !PT ; DMUL R22, R14, R22 ; DMUL R22, R22, R20 ; @!P2 FSEL R27, R29, R23, !P1 ; @!P2 FSEL R26, R28, R22, !P1 ; IMAD.MOV.U32 R13, RZ, RZ, R27 ; MOV R12, R26 ; @!P3 BRA 0x2f50 ; DADD R30, R12, R30 ; BSSY B5, 0x2da0 ; DMUL R20, R30, 0.5 ; MUFU.RSQ64H R7, R21 ; IADD3 R6, R21, -0x3500000, RZ ; ISETP.GE.U32.AND P1, PT, R6, 0x7ca00000, PT ; DMUL R12, R6, R6 ; DFMA R12, R20, -R12, 1 ; DFMA R14, R12, R34, 0.5 ; DMUL R12, R6, R12 ; DFMA R14, R14, R12, R6 ; DMUL R22, R20, R14 ; IADD3 R13, R15, -0x100000, RZ ; IMAD.MOV.U32 R12, RZ, RZ, R14 ; DFMA R24, R22, -R22, R20 ; DFMA R30, R24, R12, R22 ; @!P1 BRA 0x2d90 ; IMAD.MOV.U32 R0, RZ, RZ, R14 ; MOV R19, 0x2d70 ; IMAD.MOV.U32 R12, RZ, RZ, R20 ; IMAD.MOV.U32 R14, RZ, RZ, R6 ; IMAD.MOV.U32 R3, RZ, RZ, R13 ; CALL.REL.NOINC 0x6f20 ; IMAD.MOV.U32 R30, RZ, RZ, R38 ; IMAD.MOV.U32 R31, RZ, RZ, R39 ; BSYNC B5 ; DADD R20, R30, R30 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P2, PT, |R33|, 6.5827683646048100446e-37, PT ; BSSY B5, 0x2f20 ; MUFU.RCP64H R7, R21 ; DFMA R12, -R20, R6, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R6, R12, R6 ; DFMA R6, -R20, R12, 1 ; DFMA R6, R12, R6, R12 ; DMUL R12, R6, R32 ; DFMA R14, -R20, R12, R32 ; DFMA R6, R6, R14, R12 ; FFMA R0, RZ, R21, R7 ; FSETP.GT.AND P1, PT, |R0|, 1.469367938527859385e-39, PT ; @P1 BRA P2, 0x2f10 ; IMAD.MOV.U32 R14, RZ, RZ, R32 ; MOV R0, 0x2ef0 ; IMAD.MOV.U32 R15, RZ, RZ, R33 ; IMAD.MOV.U32 R6, RZ, RZ, R20 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R6, RZ, RZ, R24 ; MOV R7, R25 ; BSYNC B5 ; IMAD.MOV.U32 R32, RZ, RZ, R6 ; IMAD.MOV.U32 R33, RZ, RZ, R7 ; BRA 0x32a0 ; DADD R30, R12, -R30 ; BSSY B5, 0x30f0 ; DMUL R30, R30, 0.5 ; MUFU.RSQ64H R15, R31 ; IADD3 R14, R31, -0x3500000, RZ ; ISETP.GE.U32.AND P1, PT, R14, 0x7ca00000, PT ; DMUL R12, R14, R14 ; DFMA R12, R30, -R12, 1 ; DFMA R20, R12, R34, 0.5 ; DMUL R12, R14, R12 ; DFMA R20, R20, R12, R14 ; DMUL R22, R30, R20 ; IADD3 R13, R21, -0x100000, RZ ; IMAD.MOV.U32 R12, RZ, RZ, R20 ; DFMA R24, R22, -R22, R30 ; DFMA R34, R24, R12, R22 ; @!P1 BRA 0x30e0 ; IMAD.MOV.U32 R0, RZ, RZ, R20 ; MOV R19, 0x30c0 ; IMAD.MOV.U32 R12, RZ, RZ, R30 ; IMAD.MOV.U32 R21, RZ, RZ, R31 ; IMAD.MOV.U32 R3, RZ, RZ, R13 ; CALL.REL.NOINC 0x6f20 ; IMAD.MOV.U32 R34, RZ, RZ, R38 ; IMAD.MOV.U32 R35, RZ, RZ, R39 ; BSYNC B5 ; DADD R22, R34, R34 ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; FSETP.GEU.AND P2, PT, |R7|, 6.5827683646048100446e-37, PT ; BSSY B5, 0x3270 ; MUFU.RCP64H R13, R23 ; DFMA R14, -R22, R12, 1 ; DFMA R14, R14, R14, R14 ; DFMA R14, R12, R14, R12 ; DFMA R12, -R22, R14, 1 ; DFMA R12, R14, R12, R14 ; DMUL R14, R12, |R32| ; DFMA R20, -R22, R14, |R32| ; DFMA R30, R12, R20, R14 ; FFMA R0, RZ, R23, R31 ; FSETP.GT.AND P1, PT, |R0|, 1.469367938527859385e-39, PT ; @P1 BRA P2, 0x3260 ; DADD R14, -RZ, |R32| ; IMAD.MOV.U32 R6, RZ, RZ, R22 ; MOV R0, 0x3240 ; IMAD.MOV.U32 R21, RZ, RZ, R23 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R30, RZ, RZ, R24 ; MOV R31, R25 ; BSYNC B5 ; LOP3.LUT R32, R35, 0x7fffffff, RZ, 0xc0, !PT ; LOP3.LUT R33, R32, 0x80000000, R33, 0xf8, !PT ; IMAD.MOV.U32 R32, RZ, RZ, R34 ; BSYNC B4 ; ISETP.NE.AND P1, PT, R36, 0x1, PT ; @!P1 BRA 0x3320 ; ISETP.NE.AND P1, PT, R36, 0x2, PT ; @P1 BRA 0x34d0 ; DMUL R32, R32, 0.5 ; DMUL R30, R30, 0.5 ; BRA 0x34d0 ; DADD R32, R32, R32 ; DADD R30, R30, R30 ; BRA 0x34d0 ; DADD R20, R10, -R10 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B4, 0x34d0 ; MUFU.RCP64H R7, R21 ; FSETP.GEU.AND P2, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R12, -R20, R6, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R6, R12, R6 ; DFMA R6, -R20, R12, 1 ; DFMA R6, R12, R6, R12 ; DMUL R12, R20, R6 ; DFMA R14, -R20, R12, R20 ; DFMA R32, R6, R14, R12 ; FFMA R0, RZ, R21, R33 ; FSETP.GT.AND P1, PT, |R0|, 1.469367938527859385e-39, PT ; @P1 BRA P2, 0x34c0 ; IMAD.MOV.U32 R14, RZ, RZ, R20.reuse ; MOV R0, 0x34a0 ; IMAD.MOV.U32 R15, RZ, RZ, R21 ; IMAD.MOV.U32 R6, RZ, RZ, R20 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R32, RZ, RZ, R24 ; IMAD.MOV.U32 R33, RZ, RZ, R25 ; BSYNC B4 ; BSYNC B3 ; DADD R34, R8, 1 ; BSSY B3, 0x4370 ; DSETP.NEU.OR P0, PT, R34, RZ, P0 ; @!P0 CS2R R34, SRZ ; @!P0 IMAD.MOV.U32 R6, RZ, RZ, R10 ; @!P0 IMAD.MOV.U32 R7, RZ, RZ, R11 ; @!P0 BRA 0x4360 ; LOP3.LUT R0, R11, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; ISETP.NE.OR P0, PT, R10, RZ, P0 ; @!P0 IMAD.MOV.U32 R34, RZ, RZ, 0x0 ; @!P0 IMAD.MOV.U32 R35, RZ, RZ, 0x7ff00000 ; @!P0 IMAD.MOV.U32 R6, RZ, RZ, R10 ; @!P0 IMAD.MOV.U32 R7, RZ, RZ, R11 ; @!P0 BRA 0x4360 ; DSETP.GTU.AND P0, PT, |R34|, +INF , PT ; @P0 BRA 0x41e0 ; LOP3.LUT R0, R35, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; ISETP.NE.OR P0, PT, R34, RZ, P0 ; @P0 BRA 0x36d0 ; ISETP.GT.AND P0, PT, R35, -0x1, PT ; DADD R6, R10, -R10 ; @!P0 LOP3.LUT R0, R11, 0x80000000, RZ, 0xc0, !PT ; @!P0 DADD R34, -RZ, |R6| ; @P0 LOP3.LUT R3, R7, 0x7fffffff, RZ, 0xc0, !PT ; @!P0 LOP3.LUT R0, R0, 0x7ff00000, RZ, 0xfc, !PT ; @P0 LOP3.LUT R7, R3, 0x80000000, R11, 0xf8, !PT ; @!P0 MOV R6, RZ ; @!P0 IMAD.MOV.U32 R7, RZ, RZ, R0 ; BRA 0x4360 ; DSETP.GE.AND P0, PT, |R10|, c[0x2][0x8], PT ; BSSY B2, 0x37d0 ; DSETP.LTU.AND P0, PT, |R34|, c[0x2][0x8], !P0 ; @!P0 DMUL R34, R34, 0.25 ; @!P0 IMAD.MOV.U32 R40, RZ, RZ, 0x1 ; @!P0 DMUL R36, R10, 0.25 ; @!P0 BRA 0x37c0 ; DSETP.GTU.AND P0, PT, |R10|, 4.4501477170144027662e-308, PT ; IMAD.MOV.U32 R36, RZ, RZ, R10 ; IMAD.MOV.U32 R37, RZ, RZ, R11 ; IMAD.MOV.U32 R40, RZ, RZ, RZ ; DSETP.GTU.OR P0, PT, |R34|, 4.4501477170144027662e-308, P0 ; @!P0 DMUL R34, R34, 4 ; @!P0 IMAD.MOV.U32 R40, RZ, RZ, 0x2 ; @!P0 DMUL R36, R10, 4 ; BSYNC B2 ; DADD R6, -RZ, |R36| ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; MOV R28, 0x0 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; DADD R14, -RZ, |R34| ; IMAD.MOV.U32 R29, RZ, RZ, 0x3fd80000 ; BSSY B4, 0x4140 ; DSETP.GE.AND P2, PT, R34, RZ, PT ; ISETP.GT.U32.AND P1, PT, R6.reuse, R14.reuse, PT ; ISETP.LT.U32.AND P0, PT, R6.reuse, R14.reuse, PT ; ISETP.GT.U32.AND.EX P1, PT, R7.reuse, R15.reuse, PT, P1 ; ISETP.LT.U32.AND.EX P0, PT, R7.reuse, R15.reuse, PT, P0 ; SEL R27, R7, R15, P1 ; SEL R3, R6, R14, P0 ; LOP3.LUT R0, R27, 0xffc00000, RZ, 0xc0, !PT ; SEL R38, R7, R15, P0 ; IMAD.MOV.U32 R22, RZ, RZ, R3 ; SEL R26, R6, R14, P1 ; IADD3 R13, -R0, 0x7fd00000, RZ ; IMAD.MOV.U32 R23, RZ, RZ, R38 ; DMUL R14, R12, R26 ; DMUL R12, R12, R22 ; DMUL R12, R12, R12 ; DFMA R12, R14, R14, R12 ; DSETP.MIN.AND P0, P1, R12, c[0x2][0x10], PT ; IMAD.MOV.U32 R14, RZ, RZ, R13 ; FSEL R15, R14, c[0x2][0x14], P0 ; IMAD.MOV.U32 R14, RZ, RZ, c[0x2][0x14] ; @P1 LOP3.LUT R15, R14, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R14, RZ, RZ, R12 ; ISETP.GE.U32.AND P1, PT, R38, 0x7ff00000, PT ; MUFU.RSQ64H R21, R15 ; SEL R14, R14, c[0x2][0x10], P0 ; DSETP.NEU.AND P0, PT, R22, RZ, PT ; DMUL R22, R20, R20 ; DFMA R22, R14, -R22, 1 ; DMUL R24, R20, R22 ; DFMA R22, R22, R28, 0.5 ; DFMA R22, R22, R24, R20 ; DMUL R22, R12, R22 ; LOP3.LUT R13, R0, 0x100000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; DMUL R22, R22, R12 ; @!P1 FSEL R3, R26, R22, !P0 ; @!P1 FSEL R38, R27, R23, !P0 ; IMAD.MOV.U32 R12, RZ, RZ, R3 ; IMAD.MOV.U32 R13, RZ, RZ, R38 ; @!P2 BRA 0x3e00 ; DADD R34, R12, R34 ; BSSY B5, 0x3c70 ; DMUL R20, R34, 0.5 ; MUFU.RSQ64H R7, R21 ; IADD3 R6, R21, -0x3500000, RZ ; ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ; DMUL R12, R6, R6 ; DFMA R12, R20, -R12, 1 ; DFMA R14, R12, R28, 0.5 ; DMUL R12, R6, R12 ; DFMA R14, R14, R12, R6 ; DMUL R22, R20, R14 ; IADD3 R13, R15, -0x100000, RZ ; IMAD.MOV.U32 R12, RZ, RZ, R14 ; DFMA R24, R22, -R22, R20 ; DFMA R34, R24, R12, R22 ; @!P0 BRA 0x3c60 ; IMAD.MOV.U32 R0, RZ, RZ, R14 ; MOV R19, 0x3c40 ; IMAD.MOV.U32 R12, RZ, RZ, R20 ; IMAD.MOV.U32 R14, RZ, RZ, R6 ; IMAD.MOV.U32 R3, RZ, RZ, R13 ; CALL.REL.NOINC 0x6f20 ; IMAD.MOV.U32 R34, RZ, RZ, R38 ; IMAD.MOV.U32 R35, RZ, RZ, R39 ; BSYNC B5 ; DADD R20, R34, R34 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R37|, 6.5827683646048100446e-37, PT ; BSSY B5, 0x3df0 ; MUFU.RCP64H R7, R21 ; DFMA R12, -R20, R6, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R6, R12, R6 ; DFMA R6, -R20, R12, 1 ; DFMA R6, R12, R6, R12 ; DMUL R12, R6, R36 ; DFMA R14, -R20, R12, R36 ; DFMA R6, R6, R14, R12 ; FFMA R0, RZ, R21, R7 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x3de0 ; IMAD.MOV.U32 R14, RZ, RZ, R36 ; MOV R15, R37 ; IMAD.MOV.U32 R6, RZ, RZ, R20 ; MOV R0, 0x3dc0 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R6, RZ, RZ, R24 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; BSYNC B5 ; BRA 0x4130 ; DADD R34, R12, -R34 ; BSSY B5, 0x3f80 ; DMUL R34, R34, 0.5 ; MUFU.RSQ64H R15, R35 ; IADD3 R14, R35, -0x3500000, RZ ; ISETP.GE.U32.AND P0, PT, R14, 0x7ca00000, PT ; DMUL R12, R14, R14 ; DFMA R12, R34, -R12, 1 ; DFMA R20, R12, R28, 0.5 ; DMUL R12, R14, R12 ; DFMA R20, R20, R12, R14 ; DMUL R22, R34, R20 ; IADD3 R13, R21, -0x100000, RZ ; IMAD.MOV.U32 R12, RZ, RZ, R20 ; DFMA R24, R22, -R22, R34 ; DFMA R38, R24, R12, R22 ; @!P0 BRA 0x3f70 ; IMAD.MOV.U32 R0, RZ, RZ, R20 ; MOV R19, 0x3f70 ; IMAD.MOV.U32 R12, RZ, RZ, R34 ; IMAD.MOV.U32 R21, RZ, RZ, R35 ; IMAD.MOV.U32 R3, RZ, RZ, R13 ; CALL.REL.NOINC 0x6f20 ; BSYNC B5 ; DADD R22, R38, R38 ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; BSSY B5, 0x4100 ; MUFU.RCP64H R13, R23 ; DFMA R14, -R22, R12, 1 ; DFMA R14, R14, R14, R14 ; DFMA R14, R12, R14, R12 ; DFMA R12, -R22, R14, 1 ; DFMA R12, R14, R12, R14 ; DMUL R14, R12, |R36| ; DFMA R20, -R22, R14, |R36| ; DFMA R34, R12, R20, R14 ; FFMA R0, RZ, R23, R35 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x40f0 ; DADD R14, -RZ, |R36| ; IMAD.MOV.U32 R6, RZ, RZ, R22 ; MOV R0, 0x40d0 ; IMAD.MOV.U32 R21, RZ, RZ, R23 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R34, RZ, RZ, R24 ; IMAD.MOV.U32 R35, RZ, RZ, R25 ; BSYNC B5 ; LOP3.LUT R7, R39, 0x7fffffff, RZ, 0xc0, !PT ; MOV R6, R38 ; LOP3.LUT R7, R7, 0x80000000, R37, 0xf8, !PT ; BSYNC B4 ; ISETP.NE.AND P0, PT, R40, 0x1, PT ; @!P0 BRA 0x41b0 ; ISETP.NE.AND P0, PT, R40, 0x2, PT ; @P0 BRA 0x4360 ; DMUL R6, R6, 0.5 ; DMUL R34, R34, 0.5 ; BRA 0x4360 ; DADD R6, R6, R6 ; DADD R34, R34, R34 ; BRA 0x4360 ; DADD R20, R10, -R10 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B4, 0x4360 ; MUFU.RCP64H R7, R21 ; FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R12, -R20, R6, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R6, R12, R6 ; DFMA R6, -R20, R12, 1 ; DFMA R6, R12, R6, R12 ; DMUL R12, R20, R6 ; DFMA R14, -R20, R12, R20 ; DFMA R6, R6, R14, R12 ; FFMA R0, RZ, R21, R7 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x4350 ; IMAD.MOV.U32 R14, RZ, RZ, R20.reuse ; MOV R0, 0x4330 ; IMAD.MOV.U32 R15, RZ, RZ, R21 ; IMAD.MOV.U32 R6, RZ, RZ, R20 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R6, RZ, RZ, R24 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; BSYNC B4 ; BSYNC B3 ; DMUL R14, R32, R34 ; ULDC.64 UR4, c[0x0][0x118] ; DMUL R12, R6, R32 ; DFMA R14, R6, R30, R14 ; DFMA R12, R30, R34, -R12 ; DADD R14, -R14, R10 ; DADD R12, -R12, R8 ; ST.E.128 [R16.64], R12 ; BSYNC B1 ; S2R R0, SR_TID.X ; DMUL R10, R12, R14.reuse ; IMAD.MOV.U32 R32, RZ, RZ, c[0x0][0x168] ; ULDC.64 UR4, c[0x0][0x118] ; S2R R3, SR_CTAID.X ; DMUL R6, R14, R14 ; IMAD.MOV.U32 R33, RZ, RZ, c[0x0][0x16c] ; DFMA R22, R12, R14, R10 ; DFMA R20, R12, R12, -R6 ; DADD R32, R32, -c[0x0][0x160] ; DMUL R32, |R32|, 0.5 ; IMAD R19, R3, c[0x0][0x0], R0 ; IMAD.SHL.U32 R3, R19, 0x10, RZ ; SHF.R.S32.HI R0, RZ, 0x1f, R19 ; IADD3 R8, P0, R3, R18, RZ ; SHF.L.U64.HI R18, R19, 0x4, R0 ; IADD3 R10, P1, R3, R4, RZ ; IMAD.X R9, R18.reuse, 0x1, R2, P0 ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; IMAD.X R11, R18, 0x1, R5, P1 ; ST.E.128 [R8.64], R12 ; LEA R30, P1, R19.reuse, c[0x0][0x190], 0x3 ; ISETP.GT.AND P0, PT, R2, -0x1, PT ; ST.E.128 [R10.64], R20 ; LEA.HI.X R31, R19, c[0x0][0x194], R0, 0x3, P1 ; @!P0 BRA 0x68e0 ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.128 R36, [R8.64] ; MUFU.RCP64H R3, R33 ; IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; MOV R5, c[0x0][0x17c] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; BSSY B1, 0x4770 ; LDG.E.64 R34, [R4.64] ; DFMA R6, R2, -R32, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R2, R6, R2 ; DFMA R2, R6, -R32, 1 ; DFMA R2, R6, R2, R6 ; DADD R14, R36, R36 ; DADD R38, R38, R38 ; DMUL R36, R14, R2 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R6, R36, -R32, R14 ; DFMA R36, R2, R6, R36 ; FFMA R0, RZ, R33, R37 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x4760 ; IMAD.MOV.U32 R6, RZ, RZ, R32 ; MOV R0, 0x4740 ; IMAD.MOV.U32 R21, RZ, RZ, R33 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R36, RZ, RZ, R24 ; IMAD.MOV.U32 R37, RZ, RZ, R25 ; BSYNC B1 ; MUFU.RCP64H R3, R33 ; IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R39|, 6.5827683646048100446e-37, PT ; BSSY B1, 0x48f0 ; DFMA R6, R2, -R32, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R2, R6, R2 ; DFMA R2, R6, -R32, 1 ; DFMA R12, R6, R2, R6 ; DMUL R2, R38, R12 ; DFMA R6, R2, -R32, R38 ; DFMA R2, R12, R6, R2 ; FFMA R0, RZ, R33, R3 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x48e0 ; IMAD.MOV.U32 R14, RZ, RZ, R38 ; MOV R0, 0x48c0 ; IMAD.MOV.U32 R15, RZ, RZ, R39 ; IMAD.MOV.U32 R6, RZ, RZ, R32 ; IMAD.MOV.U32 R21, RZ, RZ, R33 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R2, RZ, RZ, R24 ; IMAD.MOV.U32 R3, RZ, RZ, R25 ; BSYNC B1 ; DADD R36, -RZ, |R36| ; IMAD.MOV.U32 R12, RZ, RZ, c[0x2][0x14] ; BSSY B1, 0x4f50 ; IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; DADD R2, -RZ, |R2| ; IMAD.MOV.U32 R19, RZ, RZ, 0x3fd80000 ; ISETP.GT.U32.AND P1, PT, R2.reuse, R36.reuse, PT ; ISETP.LT.U32.AND P0, PT, R2, R36, PT ; ISETP.GT.U32.AND.EX P1, PT, R3.reuse, R37.reuse, PT, P1 ; ISETP.LT.U32.AND.EX P0, PT, R3.reuse, R37.reuse, PT, P0 ; SEL R23, R3.reuse, R37.reuse, P1 ; SEL R26, R3, R37, P0 ; LOP3.LUT R0, R23, 0xffc00000, RZ, 0xc0, !PT ; SEL R20, R2.reuse, R36.reuse, P0 ; IMAD.MOV.U32 R21, RZ, RZ, R26 ; SEL R22, R2, R36, P1 ; IADD3 R3, -R0, 0x7fd00000, RZ ; MOV R2, RZ ; DMUL R6, R2, R20 ; DMUL R2, R2, R22 ; DMUL R6, R6, R6 ; DFMA R6, R2, R2, R6 ; DSETP.MIN.AND P0, P1, R6, c[0x2][0x10], PT ; IMAD.MOV.U32 R2, RZ, RZ, R7 ; FSEL R3, R2, c[0x2][0x14], P0 ; IMAD.MOV.U32 R2, RZ, RZ, R6 ; @P1 LOP3.LUT R3, R12, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; SEL R2, R2, c[0x2][0x10], P0 ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; MUFU.RSQ64H R13, R3 ; ISETP.GE.U32.AND P1, PT, R26, 0x7ff00000, PT ; DMUL R14, R12, R12 ; DFMA R14, R2, -R14, 1 ; DFMA R18, R14, R18, 0.5 ; DMUL R14, R12, R14 ; DFMA R14, R18, R14, R12 ; LOP3.LUT R13, R0, 0x100000, RZ, 0xfc, !PT ; DMUL R14, R6, R14 ; DMUL R14, R14, R12 ; @!P1 FSEL R26, R23, R15, !P0 ; IMAD.MOV.U32 R23, RZ, RZ, -0x3ff ; @!P1 FSEL R20, R22, R14, !P0 ; ISETP.GT.AND P2, PT, R26, 0xfffff, PT ; IMAD.MOV.U32 R3, RZ, RZ, R26 ; IMAD.MOV.U32 R2, RZ, RZ, R20 ; @!P2 DMUL R2, R2, 1.80143985094819840000e+16 ; @!P2 MOV R23, 0xfffffbcb ; @!P2 IMAD.MOV.U32 R26, RZ, RZ, R3 ; @!P2 IMAD.MOV.U32 R20, RZ, RZ, R2 ; IADD3 R0, R26, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R0, 0x7fefffff, PT ; @P0 IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; @P0 FSETP.NEU.AND P1, PT, R3, RZ, PT ; @P0 IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; @P0 DFMA R6, R2, R6, +INF ; @P0 FSEL R24, R6, RZ, P1 ; @P0 FSEL R25, R7, -QNAN , P1 ; @P0 BRA 0x4f40 ; LOP3.LUT R0, R26.reuse, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R2, RZ, RZ, R20 ; LEA.HI R23, R26, R23, RZ, 0xc ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; LOP3.LUT R3, R0, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R20, RZ, RZ, 0x3ae80f1e ; IMAD.MOV.U32 R21, RZ, RZ, 0x3eb1380b ; ISETP.GE.AND P0, PT, R3, 0x3ff6a09f, PT ; @P0 IADD3 R7, R3, -0x100000, RZ ; @P0 IADD3 R23, R23, 0x1, RZ ; @P0 IMAD.MOV.U32 R3, RZ, RZ, R7 ; LOP3.LUT R22, R23, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV.U32 R23, RZ, RZ, 0x43300000 ; DADD R6, R2, 1 ; DADD R2, R2, -1 ; MUFU.RCP64H R13, R7 ; DADD R22, R22, c[0x2][0x50] ; DFMA R14, -R6, R12, 1 ; DFMA R14, R14, R14, R14 ; DFMA R14, R12, R14, R12 ; DMUL R12, R14, R2 ; DFMA R12, R14, R2, R12 ; DMUL R18, R12, R12 ; DADD R6, R2, -R12 ; DFMA R20, R18, R20, c[0x2][0x18] ; DADD R6, R6, R6 ; DFMA R20, R18, R20, c[0x2][0x20] ; DFMA R24, R22, c[0x2][0x58], R12 ; DFMA R20, R18, R20, c[0x2][0x28] ; DFMA R6, R2, -R12, R6 ; DFMA R20, R18, R20, c[0x2][0x30] ; DFMA R2, -R22, c[0x2][0x58], R24 ; DFMA R20, R18, R20, c[0x2][0x38] ; DMUL R6, R14, R6 ; DFMA R20, R18, R20, c[0x2][0x40] ; DADD R2, -R12, R2 ; DFMA R20, R18, R20, c[0x2][0x48] ; DMUL R20, R18, R20 ; DFMA R6, R12, R20, R6 ; DADD R2, R6, -R2 ; DFMA R2, R22, c[0x2][0x60], R2 ; DADD R24, R24, R2 ; BSYNC B1 ; DMUL R24, R34, R24 ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; ULDC.64 UR4, c[0x0][0x118] ; DADD R2, -RZ, -R24 ; STG.E.64 [R30.64], R2 ; @!P0 BRA 0x68e0 ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R34, [R8.64] ; LDG.E.64 R2, [R4.64+0x8] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; ISETP.GE.AND P0, PT, R0, 0x2, PT ; DFMA R34, R34, -R2, -R24 ; STG.E.64 [R30.64], R34 ; @!P0 BRA 0x68e0 ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.128 R36, [R8.64] ; MUFU.RCP64H R3, R33 ; IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; BSSY B1, 0x51e0 ; LDG.E.64 R4, [R4.64+0x10] ; DFMA R6, R2, -R32, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R2, R6, R2 ; DFMA R2, R6, -R32, 1 ; DFMA R6, R6, R2, R6 ; DADD R14, R36, R36 ; DADD R38, R38, R38 ; DMUL R36, R6, R14 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R2, R36, -R32, R14 ; DFMA R36, R6, R2, R36 ; FFMA R0, RZ, R33, R37 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x51d0 ; IMAD.MOV.U32 R6, RZ, RZ, R32 ; MOV R0, 0x51b0 ; IMAD.MOV.U32 R21, RZ, RZ, R33 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R36, RZ, RZ, R24 ; IMAD.MOV.U32 R37, RZ, RZ, R25 ; BSYNC B1 ; MUFU.RCP64H R3, R33 ; IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R39|, 6.5827683646048100446e-37, PT ; BSSY B1, 0x5360 ; DFMA R6, R2, -R32, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R2, R6, R2 ; DFMA R2, R6, -R32, 1 ; DFMA R12, R6, R2, R6 ; DMUL R2, R12, R38 ; DFMA R6, R2, -R32, R38 ; DFMA R2, R12, R6, R2 ; FFMA R0, RZ, R33, R3 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x5350 ; MOV R14, R38 ; IMAD.MOV.U32 R15, RZ, RZ, R39 ; MOV R0, 0x5330 ; IMAD.MOV.U32 R6, RZ, RZ, R32 ; IMAD.MOV.U32 R21, RZ, RZ, R33 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R2, RZ, RZ, R24 ; IMAD.MOV.U32 R3, RZ, RZ, R25 ; BSYNC B1 ; DADD R36, -RZ, |R36| ; IMAD.MOV.U32 R12, RZ, RZ, c[0x2][0x14] ; BSSY B1, 0x59c0 ; IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; DADD R2, -RZ, |R2| ; IMAD.MOV.U32 R19, RZ, RZ, 0x3fd80000 ; ISETP.GT.U32.AND P1, PT, R2.reuse, R36.reuse, PT ; ISETP.LT.U32.AND P0, PT, R2, R36, PT ; ISETP.GT.U32.AND.EX P1, PT, R3.reuse, R37.reuse, PT, P1 ; ISETP.LT.U32.AND.EX P0, PT, R3.reuse, R37.reuse, PT, P0 ; SEL R23, R3.reuse, R37.reuse, P1 ; SEL R26, R3, R37, P0 ; LOP3.LUT R0, R23, 0xffc00000, RZ, 0xc0, !PT ; SEL R20, R2.reuse, R36.reuse, P0 ; IMAD.MOV.U32 R21, RZ, RZ, R26 ; SEL R22, R2, R36, P1 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IADD3 R3, -R0, 0x7fd00000, RZ ; DMUL R6, R2, R20 ; DMUL R2, R2, R22 ; DMUL R6, R6, R6 ; DFMA R6, R2, R2, R6 ; DSETP.MIN.AND P0, P1, R6, c[0x2][0x10], PT ; IMAD.MOV.U32 R2, RZ, RZ, R7 ; FSEL R3, R2, c[0x2][0x14], P0 ; IMAD.MOV.U32 R2, RZ, RZ, R6 ; @P1 LOP3.LUT R3, R12, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; SEL R2, R2, c[0x2][0x10], P0 ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; MUFU.RSQ64H R13, R3 ; ISETP.GE.U32.AND P1, PT, R26, 0x7ff00000, PT ; DMUL R14, R12, R12 ; DFMA R14, R2, -R14, 1 ; DFMA R18, R14, R18, 0.5 ; DMUL R14, R12, R14 ; DFMA R14, R18, R14, R12 ; LOP3.LUT R13, R0, 0x100000, RZ, 0xfc, !PT ; DMUL R14, R6, R14 ; DMUL R14, R14, R12 ; @!P1 FSEL R26, R23, R15, !P0 ; IMAD.MOV.U32 R23, RZ, RZ, -0x3ff ; @!P1 FSEL R20, R22, R14, !P0 ; ISETP.GT.AND P2, PT, R26, 0xfffff, PT ; IMAD.MOV.U32 R3, RZ, RZ, R26 ; MOV R2, R20 ; @!P2 DMUL R2, R2, 1.80143985094819840000e+16 ; @!P2 IMAD.MOV.U32 R23, RZ, RZ, -0x435 ; @!P2 IMAD.MOV.U32 R26, RZ, RZ, R3 ; @!P2 IMAD.MOV.U32 R20, RZ, RZ, R2 ; IADD3 R0, R26, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R0, 0x7fefffff, PT ; @P0 IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; @P0 FSETP.NEU.AND P1, PT, R3, RZ, PT ; @P0 IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; @P0 DFMA R6, R2, R6, +INF ; @P0 FSEL R24, R6, RZ, P1 ; @P0 FSEL R25, R7, -QNAN , P1 ; @P0 BRA 0x59b0 ; LOP3.LUT R0, R26.reuse, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R2, RZ, RZ, R20 ; LEA.HI R23, R26, R23, RZ, 0xc ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; LOP3.LUT R3, R0, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R20, RZ, RZ, 0x3ae80f1e ; IMAD.MOV.U32 R21, RZ, RZ, 0x3eb1380b ; ISETP.GE.AND P0, PT, R3, 0x3ff6a09f, PT ; @P0 IADD3 R7, R3, -0x100000, RZ ; @P0 IADD3 R23, R23, 0x1, RZ ; @P0 IMAD.MOV.U32 R3, RZ, RZ, R7 ; LOP3.LUT R22, R23, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV.U32 R23, RZ, RZ, 0x43300000 ; DADD R6, R2, 1 ; DADD R2, R2, -1 ; MUFU.RCP64H R13, R7 ; DADD R22, R22, c[0x2][0x50] ; DFMA R14, -R6, R12, 1 ; DFMA R14, R14, R14, R14 ; DFMA R14, R12, R14, R12 ; DMUL R12, R14, R2 ; DFMA R12, R14, R2, R12 ; DMUL R18, R12, R12 ; DADD R6, R2, -R12 ; DFMA R20, R18, R20, c[0x2][0x18] ; DADD R6, R6, R6 ; DFMA R20, R18, R20, c[0x2][0x20] ; DFMA R24, R22, c[0x2][0x58], R12 ; DFMA R20, R18, R20, c[0x2][0x28] ; DFMA R6, R2, -R12, R6 ; DFMA R20, R18, R20, c[0x2][0x30] ; DFMA R2, -R22, c[0x2][0x58], R24 ; DFMA R20, R18, R20, c[0x2][0x38] ; DMUL R6, R14, R6 ; DFMA R20, R18, R20, c[0x2][0x40] ; DADD R2, -R12, R2 ; DFMA R20, R18, R20, c[0x2][0x48] ; DMUL R20, R18, R20 ; DFMA R6, R12, R20, R6 ; DADD R2, R6, -R2 ; DFMA R2, R22, c[0x2][0x60], R2 ; DADD R24, R24, R2 ; BSYNC B1 ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R2, [R10.64] ; MOV R0, c[0x0][0x170] ; ISETP.GE.AND P0, PT, R0, 0x4, PT ; DFMA R2, R2, -0.5, R24 ; DFMA R2, R4, R2, R34 ; STG.E.64 [R30.64], R2 ; @!P0 BRA 0x68e0 ; ISETP.NE.AND P0, PT, R0.reuse, 0x4, PT ; IMAD.MOV.U32 R2, RZ, RZ, 0x3 ; IADD3 R3, R0, -0x3, RZ ; LOP3.LUT R18, R3, 0x1, RZ, 0xc0, !PT ; @!P0 BRA 0x6410 ; BSSY B1, 0x6410 ; IMAD.IADD R34, R3, 0x1, -R18 ; IMAD.MOV.U32 R2, RZ, RZ, 0x3 ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.128 R4, [R10.64] ; LD.E.128 R12, [R16.64] ; DMUL R22, R6, R12 ; DMUL R20, R6, R14 ; DFMA R6, R4, R14, R22 ; DFMA R4, R4, R12, -R20 ; ST.E.128 [R10.64], R4 ; LD.E.64 R22, [R8.64] ; IADD3 R20, R2, -0x2, RZ ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; BSSY B3, 0x5d00 ; IMAD.MOV.U32 R37, RZ, RZ, 0x8 ; I2F.F64 R20, R20 ; IMAD.WIDE R36, R2, R37, c[0x0][0x178] ; MUFU.RCP64H R13, R21 ; DFMA R14, -R20, R12, 1 ; DFMA R14, R14, R14, R14 ; DFMA R14, R12, R14, R12 ; DFMA R12, -R20, R14, 1 ; DFMA R12, R14, R12, R14 ; DMUL R38, R22, R12 ; FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; DFMA R6, -R20, R38, R22 ; DFMA R38, R12, R6, R38 ; FFMA R0, RZ, R21, R39 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x5cf0 ; IMAD.MOV.U32 R14, RZ, RZ, R22 ; MOV R0, 0x5cd0 ; IMAD.MOV.U32 R15, RZ, RZ, R23 ; IMAD.MOV.U32 R6, RZ, RZ, R20 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R38, RZ, RZ, R24 ; IMAD.MOV.U32 R39, RZ, RZ, R25 ; BSYNC B3 ; I2F.F64 R20, R2 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x5e80 ; MUFU.RCP64H R7, R21 ; DFMA R12, -R20, R6, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R6, R12, R6 ; DFMA R6, -R20, R12, 1 ; DFMA R6, R12, R6, R12 ; DMUL R12, R4, R6 ; DFMA R14, -R20, R12, R4 ; DFMA R6, R6, R14, R12 ; FFMA R0, RZ, R21, R7 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x5e70 ; IMAD.MOV.U32 R14, RZ, RZ, R4 ; MOV R6, R20 ; IMAD.MOV.U32 R15, RZ, RZ, R5 ; MOV R0, 0x5e50 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R6, RZ, RZ, R24 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; BSYNC B3 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E.64 R4, [R36.64] ; LDG.E.64 R12, [R30.64] ; DADD R6, -R6, R38 ; DFMA R4, R6, R4, R12 ; STG.E.64 [R30.64], R4 ; LD.E.128 R12, [R16.64] ; LD.E.128 R20, [R8.64] ; DMUL R6, R14, R22 ; DMUL R22, R12, R22 ; DFMA R12, R12, R20, -R6 ; DFMA R14, R14, R20, R22 ; ST.E.128 [R8.64], R12 ; LD.E.128 R20, [R16.64] ; LD.E.128 R24, [R10.64] ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; DMUL R6, R20, R26 ; DMUL R4, R22, R26 ; DFMA R6, R22, R24, R6 ; DFMA R4, R20, R24, -R4 ; ST.E.128 [R10.64], R4 ; LD.E.64 R22, [R8.64] ; IADD3 R20, R2, -0x1, RZ ; BSSY B3, 0x6160 ; I2F.F64 R20, R20 ; MUFU.RCP64H R13, R21 ; DFMA R14, -R20, R12, 1 ; DFMA R14, R14, R14, R14 ; DFMA R14, R12, R14, R12 ; DFMA R12, -R20, R14, 1 ; DFMA R12, R14, R12, R14 ; DMUL R38, R22, R12 ; FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; DFMA R6, -R20, R38, R22 ; DFMA R38, R12, R6, R38 ; FFMA R0, RZ, R21, R39 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x6150 ; IMAD.MOV.U32 R14, RZ, RZ, R22 ; MOV R0, 0x6130 ; IMAD.MOV.U32 R15, RZ, RZ, R23 ; IMAD.MOV.U32 R6, RZ, RZ, R20 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R38, RZ, RZ, R24 ; IMAD.MOV.U32 R39, RZ, RZ, R25 ; BSYNC B3 ; IADD3 R20, R2, 0x1, RZ ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x62f0 ; I2F.F64 R20, R20 ; MUFU.RCP64H R7, R21 ; DFMA R12, -R20, R6, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R6, R12, R6 ; DFMA R6, -R20, R12, 1 ; DFMA R6, R12, R6, R12 ; DMUL R12, R4, R6 ; DFMA R14, -R20, R12, R4 ; DFMA R6, R6, R14, R12 ; FFMA R0, RZ, R21, R7 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x62e0 ; IMAD.MOV.U32 R14, RZ, RZ, R4 ; MOV R0, 0x62c0 ; IMAD.MOV.U32 R15, RZ, RZ, R5 ; IMAD.MOV.U32 R6, RZ, RZ, R20 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R6, RZ, RZ, R24 ; MOV R7, R25 ; BSYNC B3 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E.64 R36, [R36.64+0x8] ; LDG.E.64 R4, [R30.64] ; DADD R6, -R6, R38 ; DFMA R4, R6, R36, R4 ; STG.E.64 [R30.64], R4 ; LD.E.128 R12, [R16.64] ; LD.E.128 R20, [R8.64] ; IADD3 R34, R34, -0x2, RZ ; IADD3 R2, R2, 0x2, RZ ; ISETP.NE.AND P0, PT, R34, RZ, PT ; DMUL R6, R14, R22 ; DMUL R22, R12, R22 ; DFMA R12, R12, R20, -R6 ; DFMA R14, R14, R20, R22 ; ST.E.128 [R8.64], R12 ; @P0 BRA 0x5ac0 ; BSYNC B1 ; ISETP.NE.AND P0, PT, R18, RZ, PT ; @!P0 BRA 0x68e0 ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.128 R4, [R10.64] ; LD.E.128 R12, [R16.64] ; DMUL R20, R6, R12 ; DMUL R18, R6, R14 ; DFMA R6, R4, R14, R20 ; DFMA R4, R4, R12, -R18 ; ST.E.128 [R10.64], R4 ; LD.E.64 R20, [R8.64] ; IADD3 R18, R2, -0x2, RZ ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; BSSY B1, 0x6680 ; IMAD.MOV.U32 R35, RZ, RZ, 0x8 ; I2F.F64 R18, R18 ; IMAD.WIDE R34, R2, R35, c[0x0][0x178] ; MUFU.RCP64H R13, R19 ; DFMA R14, -R18, R12, 1 ; DFMA R14, R14, R14, R14 ; DFMA R14, R12, R14, R12 ; DFMA R12, -R18, R14, 1 ; DFMA R12, R14, R12, R14 ; DMUL R10, R20, R12 ; FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R6, -R18, R10, R20 ; DFMA R10, R12, R6, R10 ; FFMA R0, RZ, R19, R11 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x6670 ; IMAD.MOV.U32 R15, RZ, RZ, R21 ; MOV R0, 0x6650 ; IMAD.MOV.U32 R14, RZ, RZ, R20 ; IMAD.MOV.U32 R6, RZ, RZ, R18 ; IMAD.MOV.U32 R21, RZ, RZ, R19 ; CALL.REL.NOINC 0x6940 ; IMAD.MOV.U32 R10, RZ, RZ, R24 ; IMAD.MOV.U32 R11, RZ, RZ, R25 ; BSYNC B1 ; I2F.F64 R2, R2 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; BSSY B1, 0x6810 ; MUFU.RCP64H R7, R3 ; DFMA R12, -R2, R6, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R6, R12, R6 ; DFMA R6, -R2, R12, 1 ; DFMA R6, R12, R6, R12 ; DMUL R12, R4, R6 ; DFMA R14, -R2, R12, R4 ; DFMA R6, R6, R14, R12 ; FFMA R0, RZ, R3, R7 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x6800 ; IMAD.MOV.U32 R14, RZ, RZ, R4 ; MOV R0, 0x67e0 ; IMAD.MOV.U32 R15, RZ, RZ, R5 ; IMAD.MOV.U32 R6, RZ, RZ, R2 ; IMAD.MOV.U32 R21, RZ, RZ, R3 ; CALL.REL.NOINC 0x6940 ; MOV R6, R24 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; BSYNC B1 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E.64 R34, [R34.64] ; LDG.E.64 R2, [R30.64] ; DADD R6, -R6, R10 ; DFMA R2, R6, R34, R2 ; STG.E.64 [R30.64], R2 ; LD.E.128 R16, [R16.64] ; LD.E.128 R4, [R8.64] ; DMUL R10, R18, R6 ; DMUL R6, R16, R6 ; DFMA R12, R16, R4, -R10 ; DFMA R14, R18, R4, R6 ; ST.E.128 [R8.64], R12 ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E.64 R2, [R30.64] ; DMUL R32, R32, c[0x2][0x68] ; DMUL R2, R32, R2 ; STG.E.64 [R30.64], R2 ; EXIT ; FSETP.GEU.AND P3, PT, |R15|, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R12, RZ, RZ, R6 ; FSETP.GEU.AND P1, PT, |R21|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R13, RZ, RZ, R21 ; LOP3.LUT R7, R21, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R19, RZ, RZ, 0x1ca00000 ; LOP3.LUT R3, R15, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; LOP3.LUT R7, R7, 0x3ff00000, RZ, 0xfc, !PT ; BSSY B2, 0x6ef0 ; LOP3.LUT R24, R21, 0x7ff00000, RZ, 0xc0, !PT ; @!P3 LOP3.LUT R20, R13, 0x7ff00000, RZ, 0xc0, !PT ; @!P3 IMAD.MOV.U32 R26, RZ, RZ, RZ ; @!P1 DMUL R6, R12, 8.98846567431157953865e+307 ; ISETP.GE.U32.AND P2, PT, R3.reuse, R24, PT ; @!P3 ISETP.GE.U32.AND P4, PT, R3, R20, PT ; IMAD.MOV.U32 R20, RZ, RZ, R14 ; SEL R21, R19.reuse, 0x63400000, !P2 ; MUFU.RCP64H R23, R7 ; @!P3 SEL R25, R19, 0x63400000, !P4 ; LOP3.LUT R21, R21, 0x800fffff, R15, 0xf8, !PT ; @!P3 LOP3.LUT R25, R25, 0x80000000, R15, 0xf8, !PT ; @!P3 LOP3.LUT R27, R25, 0x100000, RZ, 0xfc, !PT ; @!P3 DFMA R20, R20, 2, -R26 ; DFMA R26, R22, -R6, 1 ; DFMA R26, R26, R26, R26 ; DFMA R22, R22, R26, R22 ; DFMA R26, R22, -R6, 1 ; DFMA R22, R22, R26, R22 ; DMUL R26, R22, R20 ; DFMA R28, R26, -R6, R20 ; DFMA R22, R22, R28, R26 ; IMAD.MOV.U32 R27, RZ, RZ, R3 ; @!P3 LOP3.LUT R27, R21, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R26, RZ, RZ, R24 ; @!P1 LOP3.LUT R26, R7, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R24, R27, -0x1, RZ ; ISETP.GT.U32.AND P1, PT, R24, 0x7feffffe, PT ; IADD3 R24, R26, -0x1, RZ ; ISETP.GT.U32.OR P1, PT, R24, 0x7feffffe, P1 ; @P1 BRA 0x6d90 ; LOP3.LUT R24, R13, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P1, PT, R3.reuse, R24, PT ; IMAD.IADD R14, R3, 0x1, -R24 ; SEL R3, R19, 0x63400000, !P1 ; IMNMX R14, R14, -0x46a00000, !PT ; IMNMX R14, R14, 0x46a00000, PT ; IMAD.IADD R3, R14, 0x1, -R3 ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; IADD3 R15, R3, 0x7fe00000, RZ ; DMUL R24, R22, R14 ; FSETP.GTU.AND P1, PT, |R25|, 1.469367938527859385e-39, PT ; @P1 BRA 0x6ee0 ; DFMA R6, R22, -R6, R20 ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; FSETP.NEU.AND P1, PT, R7.reuse, RZ, PT ; LOP3.LUT R13, R7, 0x80000000, R13, 0x48, !PT ; LOP3.LUT R15, R13, R15, RZ, 0xfc, !PT ; @!P1 BRA 0x6ee0 ; IADD3 R7, -R3.reuse, RZ, RZ ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DMUL.RP R14, R22, R14 ; IADD3 R3, -R3, -0x43300000, RZ ; DFMA R6, R24, -R6, R22 ; LOP3.LUT R13, R15, R13, RZ, 0x3c, !PT ; FSETP.NEU.AND P1, PT, |R7|, R3, PT ; FSEL R24, R14, R24, !P1 ; FSEL R25, R13, R25, !P1 ; BRA 0x6ee0 ; DSETP.NAN.AND P1, PT, R14, R14, PT ; @P1 BRA 0x6ec0 ; DSETP.NAN.AND P1, PT, R12, R12, PT ; @P1 BRA 0x6e90 ; ISETP.NE.AND P1, PT, R27, R26, PT ; IMAD.MOV.U32 R24, RZ, RZ, 0x0 ; IMAD.MOV.U32 R25, RZ, RZ, -0x80000 ; @!P1 BRA 0x6ee0 ; ISETP.NE.AND P1, PT, R27, 0x7ff00000, PT ; LOP3.LUT R25, R15, 0x80000000, R13, 0x48, !PT ; ISETP.EQ.OR P1, PT, R26, RZ, !P1 ; @P1 LOP3.LUT R3, R25, 0x7ff00000, RZ, 0xfc, !PT ; @!P1 IMAD.MOV.U32 R24, RZ, RZ, RZ ; @P1 IMAD.MOV.U32 R24, RZ, RZ, RZ ; @P1 IMAD.MOV.U32 R25, RZ, RZ, R3 ; BRA 0x6ee0 ; LOP3.LUT R25, R13, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R24, RZ, RZ, R12 ; BRA 0x6ee0 ; LOP3.LUT R25, R15, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R24, RZ, RZ, R14 ; BSYNC B2 ; IMAD.MOV.U32 R6, RZ, RZ, R0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; RET.REL.NODEC R6 0x0 ; ISETP.GE.U32.AND P1, PT, R14, -0x3400000, PT ; BSSY B2, 0x71d0 ; IMAD.MOV.U32 R14, RZ, RZ, R12 ; MOV R13, R25 ; IMAD.MOV.U32 R15, RZ, RZ, R21 ; IMAD.MOV.U32 R12, RZ, RZ, R24 ; IMAD.MOV.U32 R20, RZ, RZ, R0 ; IMAD.MOV.U32 R21, RZ, RZ, R3 ; @!P1 BRA 0x7030 ; DFMA.RM R12, R12, R20, R22 ; IADD3 R20, P1, R12, 0x1, RZ ; IMAD.X R21, RZ, RZ, R13, P1 ; DFMA.RP R14, -R12, R20, R14 ; DSETP.GT.AND P1, PT, R14, RZ, PT ; FSEL R12, R20, R12, P1 ; FSEL R13, R21, R13, P1 ; BRA 0x71c0 ; DSETP.NE.AND P1, PT, R14, RZ, PT ; @!P1 BRA 0x71b0 ; ISETP.GE.AND P1, PT, R15, RZ, PT ; @!P1 IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; @!P1 IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; @!P1 BRA 0x71c0 ; ISETP.GT.AND P1, PT, R15, 0x7fefffff, PT ; @P1 BRA 0x71b0 ; DMUL R12, R14, 8.11296384146066816958e+31 ; IMAD.MOV.U32 R22, RZ, RZ, 0x0 ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; IMAD.MOV.U32 R23, RZ, RZ, 0x3fd80000 ; MUFU.RSQ64H R15, R13 ; DMUL R20, R14, R14 ; DFMA R20, R12, -R20, 1 ; DFMA R22, R20, R22, 0.5 ; DMUL R20, R14, R20 ; DFMA R20, R22, R20, R14 ; DMUL R14, R12, R20 ; IADD3 R21, R21, -0x100000, RZ ; DFMA R22, R14, -R14, R12 ; DFMA R12, R20, R22, R14 ; IADD3 R13, R13, -0x3500000, RZ ; BRA 0x71c0 ; DADD R12, R14, R14 ; BSYNC B2 ; IMAD.MOV.U32 R38, RZ, RZ, R12 ; IMAD.MOV.U32 R39, RZ, RZ, R13 ; IMAD.MOV.U32 R12, RZ, RZ, R19 ; IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; RET.REL.NODEC R12 0x0 ; BRA 0x7220; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000acef7_00000000-6_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB5976: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE5976: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z45__device_stub__Z13CUDAlogkernelddiPKdPdS1_S1_ddiPKdPdS1_S1_ .type _Z45__device_stub__Z13CUDAlogkernelddiPKdPdS1_S1_ddiPKdPdS1_S1_, @function _Z45__device_stub__Z13CUDAlogkernelddiPKdPdS1_S1_ddiPKdPdS1_S1_: .LFB5998: .cfi_startproc endbr64 subq $200, %rsp .cfi_def_cfa_offset 208 movsd %xmm0, 56(%rsp) movsd %xmm1, 48(%rsp) movl %edi, 44(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movq %r8, 8(%rsp) movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 44(%rsp), %rax movq %rax, 144(%rsp) leaq 32(%rsp), %rax movq %rax, 152(%rsp) leaq 24(%rsp), %rax movq %rax, 160(%rsp) leaq 16(%rsp), %rax movq %rax, 168(%rsp) leaq 8(%rsp), %rax movq %rax, 176(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 184(%rsp), %rax subq %fs:40, %rax jne .L8 addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 216 pushq 72(%rsp) .cfi_def_cfa_offset 224 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq CUDAlogkernel(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 208 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE5998: .size _Z45__device_stub__Z13CUDAlogkernelddiPKdPdS1_S1_ddiPKdPdS1_S1_, .-_Z45__device_stub__Z13CUDAlogkernelddiPKdPdS1_S1_ddiPKdPdS1_S1_ .globl CUDAlogkernel .type CUDAlogkernel, @function CUDAlogkernel: .LFB5999: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z45__device_stub__Z13CUDAlogkernelddiPKdPdS1_S1_ddiPKdPdS1_S1_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE5999: .size CUDAlogkernel, .-CUDAlogkernel .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDAlogkernel" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "_ZN74_INTERNAL_552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc4cuda3std3__45__cpo5beginE" .align 8 .LC2: .string "_ZN74_INTERNAL_552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc4cuda3std3__45__cpo3endE" .align 8 .LC3: .string "_ZN74_INTERNAL_552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc4cuda3std3__45__cpo6cbeginE" .align 8 .LC4: .string "_ZN74_INTERNAL_552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc4cuda3std3__45__cpo4cendE" .align 8 .LC5: .string "_ZN74_INTERNAL_552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc4cuda3std3__476_GLOBAL__N__552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc6ignoreE" .align 8 .LC6: .string "_ZN74_INTERNAL_552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc4cuda3std3__419piecewise_constructE" .align 8 .LC7: .string "_ZN74_INTERNAL_552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc4cuda3std3__48in_placeE" .align 8 .LC8: .string "_ZN74_INTERNAL_552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc4cuda3std6ranges3__45__cpo4swapE" .align 8 .LC9: .string "_ZN74_INTERNAL_552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc4cuda3std6ranges3__45__cpo9iter_moveE" .align 8 .LC10: .string "_ZN74_INTERNAL_552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc4cuda3std6ranges3__45__cpo7advanceE" .align 8 .LC11: .string "_ZN74_INTERNAL_552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc6thrust20THRUST_200700_800_NS6system6detail10sequential3seqE" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB6001: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq CUDAlogkernel(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__45__cpo5beginE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__45__cpo3endE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC4(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__45__cpo4cendE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__476_GLOBAL__N__552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc6ignoreE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__48in_placeE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC8(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC9(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC10(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC11(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6001: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata .type _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, @object .size _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, 1 _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo7advanceE .section .rodata._ZN4cuda3std6ranges3__45__cpo7advanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo7advanceE,comdat .type _ZN4cuda3std6ranges3__45__cpo7advanceE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo7advanceE, 1 _ZN4cuda3std6ranges3__45__cpo7advanceE: .zero 1 .hidden _ZN4cuda3std3__476_GLOBAL__N__552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc6ignoreE .weak _ZN4cuda3std3__476_GLOBAL__N__552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc6ignoreE .section .rodata._ZN4cuda3std3__476_GLOBAL__N__552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc6ignoreE,"aG",@progbits,_ZN4cuda3std3__476_GLOBAL__N__552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc6ignoreE,comdat .type _ZN4cuda3std3__476_GLOBAL__N__552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc6ignoreE, @gnu_unique_object .size _ZN4cuda3std3__476_GLOBAL__N__552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc6ignoreE, 1 _ZN4cuda3std3__476_GLOBAL__N__552f47f2_43_3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43_cu_ad9f19cc6ignoreE: .zero 1 .weak _ZN4cuda3std3__48in_placeE .section .rodata._ZN4cuda3std3__48in_placeE,"aG",@progbits,_ZN4cuda3std3__48in_placeE,comdat .type _ZN4cuda3std3__48in_placeE, @gnu_unique_object .size _ZN4cuda3std3__48in_placeE, 1 _ZN4cuda3std3__48in_placeE: .zero 1 .weak _ZN4cuda3std3__45__cpo4cendE .section .rodata._ZN4cuda3std3__45__cpo4cendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4cendE,comdat .type _ZN4cuda3std3__45__cpo4cendE, @gnu_unique_object .size _ZN4cuda3std3__45__cpo4cendE, 1 _ZN4cuda3std3__45__cpo4cendE: .zero 1 .weak _ZN4cuda3std3__45__cpo6cbeginE .section .rodata._ZN4cuda3std3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6cbeginE,comdat .type _ZN4cuda3std3__45__cpo6cbeginE, @gnu_unique_object .size _ZN4cuda3std3__45__cpo6cbeginE, 1 _ZN4cuda3std3__45__cpo6cbeginE: .zero 1 .weak _ZN4cuda3std3__45__cpo3endE .section .rodata._ZN4cuda3std3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std3__45__cpo3endE,comdat .type _ZN4cuda3std3__45__cpo3endE, @gnu_unique_object .size _ZN4cuda3std3__45__cpo3endE, 1 _ZN4cuda3std3__45__cpo3endE: .zero 1 .weak _ZN4cuda3std3__45__cpo5beginE .section .rodata._ZN4cuda3std3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std3__45__cpo5beginE,comdat .type _ZN4cuda3std3__45__cpo5beginE, @gnu_unique_object .size _ZN4cuda3std3__45__cpo5beginE, 1 _ZN4cuda3std3__45__cpo5beginE: .zero 1 .weak _ZN4cuda3std3__419piecewise_constructE .section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat .type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object .size _ZN4cuda3std3__419piecewise_constructE, 1 _ZN4cuda3std3__419piecewise_constructE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE .section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat .type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1 _ZN4cuda3std6ranges3__45__cpo9iter_moveE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4swapE .section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat .type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4swapE, 1 _ZN4cuda3std6ranges3__45__cpo4swapE: .zero 1 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .section .text.unlikely.,"ax",@progbits .p2align 2 ; -- Begin function __ockl_dm_alloc .type __ockl_dm_alloc,@function __ockl_dm_alloc: ; @__ockl_dm_alloc ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) s_or_saveexec_b32 s0, -1 scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill s_mov_b32 exec_lo, s0 v_writelane_b32 v40, s34, 0 v_writelane_b32 v40, s35, 1 v_writelane_b32 v40, s36, 2 v_writelane_b32 v40, s37, 3 v_writelane_b32 v40, s38, 4 v_writelane_b32 v40, s39, 5 v_writelane_b32 v40, s40, 6 v_writelane_b32 v40, s30, 7 v_writelane_b32 v40, s31, 8 v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 v_mov_b32_e32 v0, 0 v_mov_b32_e32 v1, 0 s_mov_b32 s24, exec_lo s_delay_alu instid0(VALU_DEP_3) v_cmpx_ne_u64_e32 0, v[2:3] s_cbranch_execz .LBB0_700 ; %bb.1: ; implicit-def: $vgpr0_vgpr1 s_mov_b32 s0, exec_lo v_cmpx_gt_u64_e32 0xc01, v[2:3] s_xor_b32 s25, exec_lo, s0 s_cbranch_execz .LBB0_666 ; %bb.2: v_max_u32_e32 v0, 16, v2 s_load_b64 s[10:11], s[8:9], 0x60 v_dual_mov_b32 v98, 1 :: v_dual_mov_b32 v39, 0x100 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_clz_i32_u32_e32 v1, v0 v_mov_b32_e32 v16, 0 v_not_b32_e32 v2, v1 v_lshlrev_b32_e32 v1, 1, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v3, v16 :: v_dual_and_b32 v2, 15, v2 v_lshlrev_b32_e64 v2, v2, 1 s_waitcnt lgkmcnt(0) s_add_u32 s12, s10, 0x1a800 s_addc_u32 s13, s11, 0 s_add_u32 s14, s10, 0x1a808 s_addc_u32 s15, s11, 0 v_lshrrev_b32_e32 v4, 1, v2 v_cmp_gt_u32_e32 vcc_lo, v0, v2 s_add_u32 s4, s10, 0x800 s_addc_u32 s5, s11, 0 s_getpc_b64 s[0:1] s_add_u32 s0, s0, __unnamed_1@rel32@lo+12 s_addc_u32 s1, s1, __unnamed_1@rel32@hi+20 v_or_b32_e32 v2, v4, v2 v_cndmask_b32_e64 v5, 0, 1, vcc_lo s_getpc_b64 s[2:3] s_add_u32 s2, s2, __unnamed_1@rel32@lo+4 s_addc_u32 s3, s3, __unnamed_1@rel32@hi+12 s_add_u32 s6, s10, 0x1000 s_addc_u32 s7, s11, 0 v_cmp_gt_u32_e32 vcc_lo, v0, v2 v_sub_nc_u32_e32 v1, v5, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v2, vcc_lo, 54, v1, vcc_lo v_lshlrev_b64 v[0:1], 7, v[2:3] v_lshlrev_b64 v[4:5], 5, v[2:3] v_lshrrev_b64 v[6:7], v2, 0xbf v_mov_b32_e32 v3, 0 s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v17, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v18, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v19, vcc_lo, s10, v0 v_add_co_ci_u32_e32 v20, vcc_lo, s11, v1, vcc_lo v_add_co_u32 v21, vcc_lo, v4, s0 v_add_co_ci_u32_e32 v22, vcc_lo, s1, v5, vcc_lo v_add_co_u32 v23, vcc_lo, v4, s2 v_add_co_ci_u32_e32 v24, vcc_lo, s3, v5, vcc_lo v_add_co_u32 v25, vcc_lo, s6, v0 s_add_u32 s0, s10, 0x2000 v_add_co_ci_u32_e32 v26, vcc_lo, s7, v1, vcc_lo s_addc_u32 s1, s11, 0 v_add_co_u32 v27, vcc_lo, s0, v0 s_add_u32 s2, s10, 0x1800 v_add_co_ci_u32_e32 v28, vcc_lo, s1, v1, vcc_lo s_addc_u32 s3, s11, 0 v_add_co_u32 v29, vcc_lo, s2, v0 s_getpc_b64 s[0:1] s_add_u32 s0, s0, __unnamed_1@rel32@lo+24 s_addc_u32 s1, s1, __unnamed_1@rel32@hi+32 v_add_co_ci_u32_e32 v30, vcc_lo, s3, v1, vcc_lo v_add_co_u32 v31, vcc_lo, v4, s0 v_and_b32_e32 v0, 1, v6 s_getpc_b64 s[2:3] s_add_u32 s2, s2, __unnamed_1@rel32@lo+20 s_addc_u32 s3, s3, __unnamed_1@rel32@hi+28 v_add_co_ci_u32_e32 v32, vcc_lo, s1, v5, vcc_lo v_add_co_u32 v33, vcc_lo, v4, s2 s_getpc_b64 s[4:5] s_add_u32 s4, s4, __unnamed_1@rel32@lo+28 s_addc_u32 s5, s5, __unnamed_1@rel32@hi+36 v_add_co_ci_u32_e32 v34, vcc_lo, s3, v5, vcc_lo v_add_co_u32 v35, vcc_lo, v4, s4 v_cmp_eq_u32_e64 s0, 1, v0 v_mov_b32_e32 v0, 0 v_add_co_ci_u32_e32 v36, vcc_lo, s5, v5, vcc_lo v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v1, 0 v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v6, 1 s_mov_b32 s4, 0 .LBB0_3: ; =>This Loop Header: Depth=1 ; Child Loop BB0_6 Depth 2 ; Child Loop BB0_11 Depth 3 ; Child Loop BB0_14 Depth 4 ; Child Loop BB0_43 Depth 4 ; Child Loop BB0_47 Depth 5 ; Child Loop BB0_74 Depth 5 ; Child Loop BB0_92 Depth 6 ; Child Loop BB0_100 Depth 6 ; Child Loop BB0_106 Depth 6 ; Child Loop BB0_115 Depth 6 ; Child Loop BB0_120 Depth 6 ; Child Loop BB0_122 Depth 6 ; Child Loop BB0_142 Depth 6 ; Child Loop BB0_150 Depth 6 ; Child Loop BB0_156 Depth 6 ; Child Loop BB0_165 Depth 6 ; Child Loop BB0_173 Depth 6 ; Child Loop BB0_176 Depth 6 ; Child Loop BB0_178 Depth 6 ; Child Loop BB0_180 Depth 6 ; Child Loop BB0_182 Depth 6 ; Child Loop BB0_184 Depth 6 ; Child Loop BB0_186 Depth 6 ; Child Loop BB0_208 Depth 6 ; Child Loop BB0_216 Depth 6 ; Child Loop BB0_222 Depth 6 ; Child Loop BB0_231 Depth 6 ; Child Loop BB0_238 Depth 6 ; Child Loop BB0_241 Depth 6 ; Child Loop BB0_246 Depth 6 ; Child Loop BB0_253 Depth 6 ; Child Loop BB0_286 Depth 6 ; Child Loop BB0_294 Depth 6 ; Child Loop BB0_300 Depth 6 ; Child Loop BB0_309 Depth 6 ; Child Loop BB0_318 Depth 5 ; Child Loop BB0_321 Depth 5 ; Child Loop BB0_323 Depth 5 ; Child Loop BB0_325 Depth 5 ; Child Loop BB0_327 Depth 5 ; Child Loop BB0_329 Depth 5 ; Child Loop BB0_331 Depth 5 ; Child Loop BB0_345 Depth 3 ; Child Loop BB0_349 Depth 4 ; Child Loop BB0_377 Depth 4 ; Child Loop BB0_395 Depth 5 ; Child Loop BB0_403 Depth 5 ; Child Loop BB0_409 Depth 5 ; Child Loop BB0_418 Depth 5 ; Child Loop BB0_423 Depth 5 ; Child Loop BB0_425 Depth 5 ; Child Loop BB0_445 Depth 5 ; Child Loop BB0_453 Depth 5 ; Child Loop BB0_459 Depth 5 ; Child Loop BB0_468 Depth 5 ; Child Loop BB0_476 Depth 5 ; Child Loop BB0_479 Depth 5 ; Child Loop BB0_481 Depth 5 ; Child Loop BB0_483 Depth 5 ; Child Loop BB0_485 Depth 5 ; Child Loop BB0_487 Depth 5 ; Child Loop BB0_489 Depth 5 ; Child Loop BB0_511 Depth 5 ; Child Loop BB0_519 Depth 5 ; Child Loop BB0_525 Depth 5 ; Child Loop BB0_534 Depth 5 ; Child Loop BB0_541 Depth 5 ; Child Loop BB0_544 Depth 5 ; Child Loop BB0_549 Depth 5 ; Child Loop BB0_556 Depth 5 ; Child Loop BB0_589 Depth 5 ; Child Loop BB0_597 Depth 5 ; Child Loop BB0_603 Depth 5 ; Child Loop BB0_612 Depth 5 ; Child Loop BB0_621 Depth 4 ; Child Loop BB0_624 Depth 4 ; Child Loop BB0_626 Depth 4 ; Child Loop BB0_628 Depth 4 ; Child Loop BB0_630 Depth 4 ; Child Loop BB0_632 Depth 4 ; Child Loop BB0_634 Depth 4 ; Child Loop BB0_647 Depth 3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_dual_mov_b32 v99, v6 :: v_dual_mov_b32 v6, 0 s_mov_b32 s26, exec_lo ;;#ASMSTART ;;#ASMEND v_cmpx_ne_u32_e32 0, v99 s_cbranch_execz .LBB0_664 ; %bb.4: ; in Loop: Header=BB0_3 Depth=1 v_readfirstlane_b32 s1, v2 s_mov_b32 s27, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e64 s1, v2 s_cbranch_execz .LBB0_663 ; %bb.5: ; %.preheader196.preheader ; in Loop: Header=BB0_3 Depth=1 v_mov_b32_e32 v6, 1 .LBB0_6: ; %.preheader196 ; Parent Loop BB0_3 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB0_11 Depth 3 ; Child Loop BB0_14 Depth 4 ; Child Loop BB0_43 Depth 4 ; Child Loop BB0_47 Depth 5 ; Child Loop BB0_74 Depth 5 ; Child Loop BB0_92 Depth 6 ; Child Loop BB0_100 Depth 6 ; Child Loop BB0_106 Depth 6 ; Child Loop BB0_115 Depth 6 ; Child Loop BB0_120 Depth 6 ; Child Loop BB0_122 Depth 6 ; Child Loop BB0_142 Depth 6 ; Child Loop BB0_150 Depth 6 ; Child Loop BB0_156 Depth 6 ; Child Loop BB0_165 Depth 6 ; Child Loop BB0_173 Depth 6 ; Child Loop BB0_176 Depth 6 ; Child Loop BB0_178 Depth 6 ; Child Loop BB0_180 Depth 6 ; Child Loop BB0_182 Depth 6 ; Child Loop BB0_184 Depth 6 ; Child Loop BB0_186 Depth 6 ; Child Loop BB0_208 Depth 6 ; Child Loop BB0_216 Depth 6 ; Child Loop BB0_222 Depth 6 ; Child Loop BB0_231 Depth 6 ; Child Loop BB0_238 Depth 6 ; Child Loop BB0_241 Depth 6 ; Child Loop BB0_246 Depth 6 ; Child Loop BB0_253 Depth 6 ; Child Loop BB0_286 Depth 6 ; Child Loop BB0_294 Depth 6 ; Child Loop BB0_300 Depth 6 ; Child Loop BB0_309 Depth 6 ; Child Loop BB0_318 Depth 5 ; Child Loop BB0_321 Depth 5 ; Child Loop BB0_323 Depth 5 ; Child Loop BB0_325 Depth 5 ; Child Loop BB0_327 Depth 5 ; Child Loop BB0_329 Depth 5 ; Child Loop BB0_331 Depth 5 ; Child Loop BB0_345 Depth 3 ; Child Loop BB0_349 Depth 4 ; Child Loop BB0_377 Depth 4 ; Child Loop BB0_395 Depth 5 ; Child Loop BB0_403 Depth 5 ; Child Loop BB0_409 Depth 5 ; Child Loop BB0_418 Depth 5 ; Child Loop BB0_423 Depth 5 ; Child Loop BB0_425 Depth 5 ; Child Loop BB0_445 Depth 5 ; Child Loop BB0_453 Depth 5 ; Child Loop BB0_459 Depth 5 ; Child Loop BB0_468 Depth 5 ; Child Loop BB0_476 Depth 5 ; Child Loop BB0_479 Depth 5 ; Child Loop BB0_481 Depth 5 ; Child Loop BB0_483 Depth 5 ; Child Loop BB0_485 Depth 5 ; Child Loop BB0_487 Depth 5 ; Child Loop BB0_489 Depth 5 ; Child Loop BB0_511 Depth 5 ; Child Loop BB0_519 Depth 5 ; Child Loop BB0_525 Depth 5 ; Child Loop BB0_534 Depth 5 ; Child Loop BB0_541 Depth 5 ; Child Loop BB0_544 Depth 5 ; Child Loop BB0_549 Depth 5 ; Child Loop BB0_556 Depth 5 ; Child Loop BB0_589 Depth 5 ; Child Loop BB0_597 Depth 5 ; Child Loop BB0_603 Depth 5 ; Child Loop BB0_612 Depth 5 ; Child Loop BB0_621 Depth 4 ; Child Loop BB0_624 Depth 4 ; Child Loop BB0_626 Depth 4 ; Child Loop BB0_628 Depth 4 ; Child Loop BB0_630 Depth 4 ; Child Loop BB0_632 Depth 4 ; Child Loop BB0_634 Depth 4 ; Child Loop BB0_647 Depth 3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_mov_b32_e32 v100, v6 v_mov_b32_e32 v6, 0 s_mov_b32 s28, exec_lo ;;#ASMSTART ;;#ASMEND v_cmpx_ne_u32_e32 0, v100 s_cbranch_execz .LBB0_662 ; %bb.7: ; in Loop: Header=BB0_6 Depth=2 v_mbcnt_lo_u32_b32 v6, exec_lo, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v6 v_mov_b32_e32 v6, 0 s_and_saveexec_b32 s1, vcc_lo s_cbranch_execz .LBB0_9 ; %bb.8: ; in Loop: Header=BB0_6 Depth=2 global_load_b32 v6, v[17:18], off glc .LBB0_9: ; in Loop: Header=BB0_6 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_waitcnt vmcnt(0) v_readfirstlane_b32 s29, v6 s_delay_alu instid0(VALU_DEP_1) s_cmp_gt_u32 s29, 0x100ff s_cbranch_scc0 .LBB0_342 ; %bb.10: ; in Loop: Header=BB0_6 Depth=2 v_mbcnt_lo_u32_b32 v101, exec_lo, 0 v_mov_b32_e32 v15, v2 s_mov_b32 s30, 0 s_bcnt1_i32_b32 s31, exec_lo ; implicit-def: $vgpr7_vgpr8 .LBB0_11: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; => This Loop Header: Depth=3 ; Child Loop BB0_14 Depth 4 ; Child Loop BB0_43 Depth 4 ; Child Loop BB0_47 Depth 5 ; Child Loop BB0_74 Depth 5 ; Child Loop BB0_92 Depth 6 ; Child Loop BB0_100 Depth 6 ; Child Loop BB0_106 Depth 6 ; Child Loop BB0_115 Depth 6 ; Child Loop BB0_120 Depth 6 ; Child Loop BB0_122 Depth 6 ; Child Loop BB0_142 Depth 6 ; Child Loop BB0_150 Depth 6 ; Child Loop BB0_156 Depth 6 ; Child Loop BB0_165 Depth 6 ; Child Loop BB0_173 Depth 6 ; Child Loop BB0_176 Depth 6 ; Child Loop BB0_178 Depth 6 ; Child Loop BB0_180 Depth 6 ; Child Loop BB0_182 Depth 6 ; Child Loop BB0_184 Depth 6 ; Child Loop BB0_186 Depth 6 ; Child Loop BB0_208 Depth 6 ; Child Loop BB0_216 Depth 6 ; Child Loop BB0_222 Depth 6 ; Child Loop BB0_231 Depth 6 ; Child Loop BB0_238 Depth 6 ; Child Loop BB0_241 Depth 6 ; Child Loop BB0_246 Depth 6 ; Child Loop BB0_253 Depth 6 ; Child Loop BB0_286 Depth 6 ; Child Loop BB0_294 Depth 6 ; Child Loop BB0_300 Depth 6 ; Child Loop BB0_309 Depth 6 ; Child Loop BB0_318 Depth 5 ; Child Loop BB0_321 Depth 5 ; Child Loop BB0_323 Depth 5 ; Child Loop BB0_325 Depth 5 ; Child Loop BB0_327 Depth 5 ; Child Loop BB0_329 Depth 5 ; Child Loop BB0_331 Depth 5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_lshlrev_b64 v[9:10], 7, v[15:16] ;;#ASMSTART ;;#ASMEND v_cmp_eq_u32_e64 s1, 0, v101 v_mov_b32_e32 v11, 0 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB0_13 ; %bb.12: ; in Loop: Header=BB0_11 Depth=3 v_add_co_u32 v11, vcc_lo, s10, v9 v_add_co_ci_u32_e32 v12, vcc_lo, s11, v10, vcc_lo global_load_b32 v11, v[11:12], off glc .LBB0_13: ; in Loop: Header=BB0_11 Depth=3 s_or_b32 exec_lo, exec_lo, s2 v_lshlrev_b64 v[12:13], 5, v[15:16] s_getpc_b64 s[2:3] s_add_u32 s2, s2, __unnamed_1@rel32@lo+8 s_addc_u32 s3, s3, __unnamed_1@rel32@hi+16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v12, vcc_lo, v12, s2 v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo s_waitcnt vmcnt(0) v_readfirstlane_b32 s2, v11 global_load_b32 v6, v[12:13], off v_add_nc_u32_e32 v11, s2, v101 s_mov_b32 s2, 0x10100 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v12, v11, 0xff00ff01 v_lshrrev_b32_e32 v12, 16, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_u32_u24_e32 v12, 0x10100, v12 v_sub_nc_u32_e32 v14, v11, v12 v_add_co_u32 v12, vcc_lo, s10, v9 v_add_co_ci_u32_e32 v13, vcc_lo, s11, v10, vcc_lo .LBB0_14: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; => This Inner Loop Header: Depth=4 s_mov_b32 s3, exec_lo ; implicit-def: $vgpr9_vgpr10 s_delay_alu instid0(VALU_DEP_3) v_cmpx_gt_u32_e32 0x100, v14 s_xor_b32 s3, exec_lo, s3 ; %bb.15: ; in Loop: Header=BB0_14 Depth=4 s_add_u32 s6, s10, 0x2800 s_addc_u32 s7, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[37:38], null, v15, 0x1800, s[6:7] v_mad_u64_u32 v[9:10], null, v14, 24, v[37:38] ; %bb.16: ; %Flow982 ; in Loop: Header=BB0_14 Depth=4 s_and_not1_saveexec_b32 s3, s3 s_cbranch_execz .LBB0_18 ; %bb.17: ; in Loop: Header=BB0_14 Depth=4 s_add_u32 s6, s10, 0x2800 v_add_nc_u32_e32 v11, 0xffffff00, v14 s_addc_u32 s7, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[9:10], null, v15, 0x1800, s[6:7] v_lshrrev_b32_e32 v11, 8, v11 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[37:38], null, v11, 24, v[9:10] v_and_b32_e32 v11, 0xff, v14 global_load_b64 v[37:38], v[37:38], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[9:10], null, v11, 24, v[37:38] .LBB0_18: ; in Loop: Header=BB0_14 Depth=4 s_or_b32 exec_lo, exec_lo, s3 global_load_b32 v9, v[9:10], off offset:16 glc s_waitcnt vmcnt(0) v_cmp_lt_u32_e32 vcc_lo, v9, v6 s_cbranch_vccz .LBB0_20 ; %bb.19: ; in Loop: Header=BB0_14 Depth=4 s_ctz_i32_b32 s3, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b32 s3, s3, 2 v_mov_b32_e32 v9, s3 ds_bpermute_b32 v9, v9, v14 s_branch .LBB0_21 .LBB0_20: ; in Loop: Header=BB0_14 Depth=4 v_mov_b32_e32 v9, -1 .LBB0_21: ; in Loop: Header=BB0_14 Depth=4 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v9 s_cmp_eq_u32 s5, -1 s_cselect_b32 s3, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s3 s_cbranch_vccnz .LBB0_24 ; %bb.22: ; in Loop: Header=BB0_14 Depth=4 s_cmpk_lt_u32 s5, 0x100 s_cbranch_scc0 .LBB0_25 ; %bb.23: ; in Loop: Header=BB0_14 Depth=4 s_add_u32 s6, s10, 0x2800 s_addc_u32 s7, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[37:38], null, v15, 0x1800, s[6:7] s_mov_b32 s6, 0 v_mad_u64_u32 v[10:11], null, s5, 24, v[37:38] s_branch .LBB0_26 .LBB0_24: ; in Loop: Header=BB0_14 Depth=4 s_mov_b32 s5, -1 ; implicit-def: $vgpr10_vgpr11 s_branch .LBB0_29 .LBB0_25: ; in Loop: Header=BB0_14 Depth=4 s_mov_b32 s6, -1 ; implicit-def: $vgpr10_vgpr11 .LBB0_26: ; %Flow975 ; in Loop: Header=BB0_14 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_28 ; %bb.27: ; in Loop: Header=BB0_14 Depth=4 s_add_i32 s6, s5, 0xffffff00 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) s_lshr_b32 s16, s6, 8 s_add_u32 s6, s10, 0x2800 s_addc_u32 s7, s11, 0 s_and_b32 s5, s5, 0xff v_mad_u64_u32 v[9:10], null, v15, 0x1800, s[6:7] v_mad_u64_u32 v[37:38], null, s16, 24, v[9:10] global_load_b64 v[37:38], v[37:38], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[10:11], null, s5, 24, v[37:38] .LBB0_28: ; %Flow976 ; in Loop: Header=BB0_14 Depth=4 s_mov_b32 s5, 0 .LBB0_29: ; %Flow978 ; in Loop: Header=BB0_14 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB0_33 ; %bb.30: ; in Loop: Header=BB0_14 Depth=4 v_add_nc_u32_e32 v9, s31, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v10, v9, 0xff00ff01 v_lshrrev_b32_e32 v10, 16, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_u32_u24_e32 v10, 0x10100, v10 v_sub_nc_u32_e32 v14, v9, v10 s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB0_32 ; %bb.31: ; in Loop: Header=BB0_14 Depth=4 global_store_b32 v[12:13], v14, off .LBB0_32: ; in Loop: Header=BB0_14 Depth=4 s_or_b32 exec_lo, exec_lo, s5 v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v10, v7 s_sub_i32 s2, s2, s31 .LBB0_33: ; in Loop: Header=BB0_14 Depth=4 s_and_not1_b32 vcc_lo, exec_lo, s3 s_cbranch_vccz .LBB0_35 ; %bb.34: ; in Loop: Header=BB0_14 Depth=4 s_mov_b32 s3, 0 s_mov_b32 s5, -1 s_mov_b32 s6, -1 ; implicit-def: $sgpr2 ; implicit-def: $vgpr14 s_branch .LBB0_36 .LBB0_35: ; in Loop: Header=BB0_14 Depth=4 s_cmp_lt_i32 s2, 1 s_mov_b32 s5, 0 s_cselect_b32 s6, -1, 0 ; implicit-def: $sgpr3 .LBB0_36: ; %Flow984 ; in Loop: Header=BB0_14 Depth=4 v_dual_mov_b32 v7, v10 :: v_dual_mov_b32 v8, v11 s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_14 ; %bb.37: ; %loop.exit.guard ; in Loop: Header=BB0_11 Depth=3 v_dual_mov_b32 v7, v10 :: v_dual_mov_b32 v8, v11 s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccz .LBB0_340 ; %bb.38: ; in Loop: Header=BB0_11 Depth=3 v_dual_mov_b32 v7, 0 :: v_dual_and_b32 v6, -2, v15 v_cmp_eq_u32_e32 vcc_lo, v15, v2 v_mov_b32_e32 v8, 0 s_mov_b32 s3, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u32_e64 s2, 14, v6 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s34, s2 s_cbranch_execz .LBB0_339 ; %bb.39: ; in Loop: Header=BB0_11 Depth=3 v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v6, 2, v6 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB0_41 ; %bb.40: ; in Loop: Header=BB0_11 Depth=3 v_mov_b32_e32 v7, v16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 7, v[6:7] v_add_co_u32 v7, vcc_lo, s10, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo global_load_b32 v7, v[7:8], off offset:2048 glc .LBB0_41: ; in Loop: Header=BB0_11 Depth=3 s_or_b32 exec_lo, exec_lo, s2 s_waitcnt vmcnt(0) v_readfirstlane_b32 s36, v7 s_mov_b32 s6, -1 s_delay_alu instid0(VALU_DEP_1) s_cmp_gt_u32 s36, 0x100ff s_cbranch_scc1 .LBB0_338 ; %bb.42: ; in Loop: Header=BB0_11 Depth=3 v_mov_b32_e32 v7, v16 s_bcnt1_i32_b32 s35, exec_lo s_getpc_b64 s[2:3] s_add_u32 s2, s2, __unnamed_1@rel32@lo+12 s_addc_u32 s3, s3, __unnamed_1@rel32@hi+20 s_getpc_b64 s[6:7] s_add_u32 s6, s6, __unnamed_1@rel32@lo+4 s_addc_u32 s7, s7, __unnamed_1@rel32@hi+12 s_add_u32 s1, s10, 0x800 v_lshlrev_b64 v[8:9], 7, v[6:7] v_lshlrev_b64 v[10:11], 5, v[6:7] v_lshrrev_b64 v[12:13], v6, 0xbf v_mbcnt_lo_u32_b32 v102, exec_lo, 0 ; implicit-def: $vgpr82_vgpr83 s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v37, vcc_lo, s10, v8 v_add_co_ci_u32_e32 v38, vcc_lo, s11, v9, vcc_lo v_add_co_u32 v48, vcc_lo, v10, s2 v_add_co_ci_u32_e32 v49, vcc_lo, s3, v11, vcc_lo v_add_co_u32 v50, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v51, vcc_lo, s7, v11, vcc_lo s_addc_u32 s2, s11, 0 v_add_co_u32 v52, vcc_lo, s1, v8 s_add_u32 s1, s10, 0x1000 v_add_co_ci_u32_e32 v53, vcc_lo, s2, v9, vcc_lo s_addc_u32 s2, s11, 0 v_add_co_u32 v54, vcc_lo, s1, v8 s_add_u32 s1, s10, 0x2000 v_add_co_ci_u32_e32 v55, vcc_lo, s2, v9, vcc_lo s_addc_u32 s2, s11, 0 v_add_co_u32 v64, vcc_lo, s1, v8 s_add_u32 s1, s10, 0x1800 v_add_co_ci_u32_e32 v65, vcc_lo, s2, v9, vcc_lo s_addc_u32 s5, s11, 0 v_add_co_u32 v66, vcc_lo, s1, v8 v_and_b32_e32 v7, 1, v12 s_getpc_b64 s[2:3] s_add_u32 s2, s2, __unnamed_1@rel32@lo+24 s_addc_u32 s3, s3, __unnamed_1@rel32@hi+32 v_add_co_ci_u32_e32 v67, vcc_lo, s5, v9, vcc_lo v_add_co_u32 v68, vcc_lo, v10, s2 s_getpc_b64 s[6:7] s_add_u32 s6, s6, __unnamed_1@rel32@lo+20 s_addc_u32 s7, s7, __unnamed_1@rel32@hi+28 v_add_co_ci_u32_e32 v69, vcc_lo, s3, v11, vcc_lo v_cmp_eq_u32_e64 s1, 1, v7 v_add_co_u32 v70, vcc_lo, v10, s6 v_mov_b32_e32 v7, 0 s_getpc_b64 s[2:3] s_add_u32 s2, s2, __unnamed_1@rel32@lo+28 s_addc_u32 s3, s3, __unnamed_1@rel32@hi+36 v_add_co_ci_u32_e32 v71, vcc_lo, s7, v11, vcc_lo v_add_co_u32 v80, vcc_lo, v10, s2 v_add_co_ci_u32_e32 v81, vcc_lo, s3, v11, vcc_lo v_mov_b32_e32 v8, v7 v_mov_b32_e32 v9, v7 .LBB0_43: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; => This Loop Header: Depth=4 ; Child Loop BB0_47 Depth 5 ; Child Loop BB0_74 Depth 5 ; Child Loop BB0_92 Depth 6 ; Child Loop BB0_100 Depth 6 ; Child Loop BB0_106 Depth 6 ; Child Loop BB0_115 Depth 6 ; Child Loop BB0_120 Depth 6 ; Child Loop BB0_122 Depth 6 ; Child Loop BB0_142 Depth 6 ; Child Loop BB0_150 Depth 6 ; Child Loop BB0_156 Depth 6 ; Child Loop BB0_165 Depth 6 ; Child Loop BB0_173 Depth 6 ; Child Loop BB0_176 Depth 6 ; Child Loop BB0_178 Depth 6 ; Child Loop BB0_180 Depth 6 ; Child Loop BB0_182 Depth 6 ; Child Loop BB0_184 Depth 6 ; Child Loop BB0_186 Depth 6 ; Child Loop BB0_208 Depth 6 ; Child Loop BB0_216 Depth 6 ; Child Loop BB0_222 Depth 6 ; Child Loop BB0_231 Depth 6 ; Child Loop BB0_238 Depth 6 ; Child Loop BB0_241 Depth 6 ; Child Loop BB0_246 Depth 6 ; Child Loop BB0_253 Depth 6 ; Child Loop BB0_286 Depth 6 ; Child Loop BB0_294 Depth 6 ; Child Loop BB0_300 Depth 6 ; Child Loop BB0_309 Depth 6 ; Child Loop BB0_318 Depth 5 ; Child Loop BB0_321 Depth 5 ; Child Loop BB0_323 Depth 5 ; Child Loop BB0_325 Depth 5 ; Child Loop BB0_327 Depth 5 ; Child Loop BB0_329 Depth 5 ; Child Loop BB0_331 Depth 5 s_cmp_eq_u32 s36, 0 s_mov_b32 s5, -1 ;;#ASMSTART ;;#ASMEND s_cbranch_scc1 .LBB0_71 ; %bb.44: ; in Loop: Header=BB0_43 Depth=4 v_cmp_eq_u32_e64 s2, 0, v102 v_mov_b32_e32 v10, 0 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_46 ; %bb.45: ; in Loop: Header=BB0_43 Depth=4 global_load_b32 v10, v[37:38], off glc .LBB0_46: ; in Loop: Header=BB0_43 Depth=4 s_or_b32 exec_lo, exec_lo, s3 global_load_b32 v12, v[48:49], off v_cvt_f32_u32_e32 v11, s36 s_sub_i32 s3, 0, s36 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v11, v11 s_waitcnt_depctr 0xfff v_mul_f32_e32 v11, 0x4f7ffffe, v11 v_cvt_u32_f32_e32 v11, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mul_lo_u32 v13, s3, v11 s_waitcnt vmcnt(1) v_readfirstlane_b32 s3, v10 v_add_nc_u32_e32 v10, s3, v102 s_mov_b32 s3, s36 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v13, v11, v13 v_add_nc_u32_e32 v13, v11, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v11, v10, v13 v_mul_lo_u32 v11, v11, s36 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v10, v10, v11 v_subrev_nc_u32_e32 v11, s36, v10 v_cmp_le_u32_e32 vcc_lo, s36, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v10, v10, v11, vcc_lo v_subrev_nc_u32_e32 v11, s36, v10 v_cmp_le_u32_e32 vcc_lo, s36, v10 s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e32 v14, v10, v11, vcc_lo .LBB0_47: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_mov_b32 s6, exec_lo ; implicit-def: $vgpr10_vgpr11 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_u32_e32 0x100, v14 s_xor_b32 s6, exec_lo, s6 ; %bb.48: ; in Loop: Header=BB0_47 Depth=5 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[84:85], null, v6, 0x1800, s[16:17] v_mad_u64_u32 v[10:11], null, v14, 24, v[84:85] ; %bb.49: ; %Flow799 ; in Loop: Header=BB0_47 Depth=5 s_and_not1_saveexec_b32 s6, s6 s_cbranch_execz .LBB0_51 ; %bb.50: ; in Loop: Header=BB0_47 Depth=5 s_add_u32 s16, s10, 0x2800 v_add_nc_u32_e32 v15, 0xffffff00, v14 s_addc_u32 s17, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[10:11], null, v6, 0x1800, s[16:17] v_lshrrev_b32_e32 v15, 8, v15 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[84:85], null, v15, 24, v[10:11] v_and_b32_e32 v15, 0xff, v14 global_load_b64 v[84:85], v[84:85], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[10:11], null, v15, 24, v[84:85] .LBB0_51: ; in Loop: Header=BB0_47 Depth=5 s_or_b32 exec_lo, exec_lo, s6 global_load_b32 v10, v[10:11], off offset:16 glc s_waitcnt vmcnt(0) v_cmp_lt_u32_e32 vcc_lo, v10, v12 s_cbranch_vccz .LBB0_53 ; %bb.52: ; in Loop: Header=BB0_47 Depth=5 s_ctz_i32_b32 s6, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b32 s6, s6, 2 v_mov_b32_e32 v10, s6 ds_bpermute_b32 v10, v10, v14 s_branch .LBB0_54 .LBB0_53: ; in Loop: Header=BB0_47 Depth=5 v_mov_b32_e32 v10, -1 .LBB0_54: ; in Loop: Header=BB0_47 Depth=5 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s7, v10 s_cmp_eq_u32 s7, -1 s_cselect_b32 s6, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_57 ; %bb.55: ; in Loop: Header=BB0_47 Depth=5 s_cmpk_lt_u32 s7, 0x100 s_cbranch_scc0 .LBB0_58 ; %bb.56: ; in Loop: Header=BB0_47 Depth=5 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[84:85], null, v6, 0x1800, s[16:17] s_mov_b32 s16, 0 v_mad_u64_u32 v[10:11], null, s7, 24, v[84:85] s_branch .LBB0_59 .LBB0_57: ; in Loop: Header=BB0_47 Depth=5 s_mov_b32 s7, -1 ; implicit-def: $vgpr10_vgpr11 s_branch .LBB0_62 .LBB0_58: ; in Loop: Header=BB0_47 Depth=5 s_mov_b32 s16, -1 ; implicit-def: $vgpr10_vgpr11 .LBB0_59: ; %Flow793 ; in Loop: Header=BB0_47 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB0_61 ; %bb.60: ; in Loop: Header=BB0_47 Depth=5 s_add_i32 s16, s7, 0xffffff00 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) s_lshr_b32 s18, s16, 8 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_and_b32 s7, s7, 0xff v_mad_u64_u32 v[10:11], null, v6, 0x1800, s[16:17] v_mad_u64_u32 v[84:85], null, s18, 24, v[10:11] global_load_b64 v[84:85], v[84:85], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[10:11], null, s7, 24, v[84:85] .LBB0_61: ; %Flow794 ; in Loop: Header=BB0_47 Depth=5 s_mov_b32 s7, 0 .LBB0_62: ; %Flow795 ; in Loop: Header=BB0_47 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s7 s_cbranch_vccnz .LBB0_66 ; %bb.63: ; in Loop: Header=BB0_47 Depth=5 v_add_nc_u32_e32 v10, s35, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v11, v10, v13 v_mul_lo_u32 v11, v11, s36 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v10, v10, v11 v_subrev_nc_u32_e32 v11, s36, v10 v_cmp_le_u32_e32 vcc_lo, s36, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v10, v10, v11, vcc_lo v_subrev_nc_u32_e32 v11, s36, v10 v_cmp_le_u32_e32 vcc_lo, s36, v10 s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e32 v14, v10, v11, vcc_lo s_and_saveexec_b32 s7, s2 s_cbranch_execz .LBB0_65 ; %bb.64: ; in Loop: Header=BB0_47 Depth=5 global_store_b32 v[37:38], v14, off .LBB0_65: ; in Loop: Header=BB0_47 Depth=5 s_or_b32 exec_lo, exec_lo, s7 v_dual_mov_b32 v10, v82 :: v_dual_mov_b32 v11, v83 s_sub_i32 s3, s3, s35 .LBB0_66: ; in Loop: Header=BB0_47 Depth=5 s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccz .LBB0_68 ; %bb.67: ; in Loop: Header=BB0_47 Depth=5 s_mov_b32 s6, 0 s_mov_b32 s7, -1 s_mov_b32 s16, -1 ; implicit-def: $sgpr3 ; implicit-def: $vgpr14 s_branch .LBB0_69 .LBB0_68: ; in Loop: Header=BB0_47 Depth=5 s_cmp_lt_i32 s3, 1 s_mov_b32 s7, 0 s_cselect_b32 s16, -1, 0 ; implicit-def: $sgpr6 .LBB0_69: ; %Flow801 ; in Loop: Header=BB0_47 Depth=5 v_dual_mov_b32 v83, v11 :: v_dual_mov_b32 v82, v10 s_and_not1_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB0_47 ; %bb.70: ; %loop.exit.guard750 ; in Loop: Header=BB0_43 Depth=4 s_xor_b32 s2, s7, -1 s_branch .LBB0_72 .LBB0_71: ; in Loop: Header=BB0_43 Depth=4 s_mov_b32 s2, -1 ; implicit-def: $vgpr10_vgpr11 ; implicit-def: $sgpr6 .LBB0_72: ; %Flow968 ; in Loop: Header=BB0_43 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s2 s_cbranch_vccz .LBB0_312 ; %bb.73: ; %.loopexit188 ; in Loop: Header=BB0_43 Depth=4 v_mbcnt_lo_u32_b32 v103, exec_lo, 0 ; implicit-def: $vgpr84_vgpr85 .LBB0_74: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; => This Loop Header: Depth=5 ; Child Loop BB0_92 Depth 6 ; Child Loop BB0_100 Depth 6 ; Child Loop BB0_106 Depth 6 ; Child Loop BB0_115 Depth 6 ; Child Loop BB0_120 Depth 6 ; Child Loop BB0_122 Depth 6 ; Child Loop BB0_142 Depth 6 ; Child Loop BB0_150 Depth 6 ; Child Loop BB0_156 Depth 6 ; Child Loop BB0_165 Depth 6 ; Child Loop BB0_173 Depth 6 ; Child Loop BB0_176 Depth 6 ; Child Loop BB0_178 Depth 6 ; Child Loop BB0_180 Depth 6 ; Child Loop BB0_182 Depth 6 ; Child Loop BB0_184 Depth 6 ; Child Loop BB0_186 Depth 6 ; Child Loop BB0_208 Depth 6 ; Child Loop BB0_216 Depth 6 ; Child Loop BB0_222 Depth 6 ; Child Loop BB0_231 Depth 6 ; Child Loop BB0_238 Depth 6 ; Child Loop BB0_241 Depth 6 ; Child Loop BB0_246 Depth 6 ; Child Loop BB0_253 Depth 6 ; Child Loop BB0_286 Depth 6 ; Child Loop BB0_294 Depth 6 ; Child Loop BB0_300 Depth 6 ; Child Loop BB0_309 Depth 6 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cmp_eq_u32_e64 s2, 0, v103 v_mov_b32_e32 v10, 0 s_mov_b32 s18, 0 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_76 ; %bb.75: ; in Loop: Header=BB0_74 Depth=5 global_load_b32 v10, v[52:53], off glc .LBB0_76: ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) v_readfirstlane_b32 s37, v10 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_delay_alu instid0(VALU_DEP_3) s_cmp_eq_u32 s37, 0x10100 s_cbranch_scc1 .LBB0_196 ; %bb.77: ; in Loop: Header=BB0_74 Depth=5 v_mov_b32_e32 v10, 0 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_79 ; %bb.78: ; in Loop: Header=BB0_74 Depth=5 v_dual_mov_b32 v10, 0x100 :: v_dual_mov_b32 v11, 0 global_atomic_cmpswap_b32 v10, v[54:55], v[10:11], off glc s_waitcnt vmcnt(0) v_cmp_ne_u32_e32 vcc_lo, 0, v10 v_cndmask_b32_e32 v10, 0x100, v10, vcc_lo .LBB0_79: ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s38, v10 s_cmp_lg_u32 s37, s38 s_cbranch_scc1 .LBB0_136 ; %bb.80: ; in Loop: Header=BB0_74 Depth=5 v_mbcnt_lo_u32_b32 v112, exec_lo, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v112 v_mov_b32_e32 v10, 0 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB0_82 ; %bb.81: ; in Loop: Header=BB0_74 Depth=5 global_load_b32 v10, v[54:55], off glc .LBB0_82: ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) v_readfirstlane_b32 s22, v10 s_mov_b32 s5, 2 s_delay_alu instid0(VALU_DEP_1) s_cmp_eq_u32 s22, 0x10100 s_cbranch_scc1 .LBB0_169 ; %bb.83: ; in Loop: Header=BB0_74 Depth=5 v_mov_b32_e32 v10, 1 s_and_saveexec_b32 s5, vcc_lo s_cbranch_execz .LBB0_87 ; %bb.84: ; in Loop: Header=BB0_74 Depth=5 global_load_b64 v[12:13], v[64:65], off glc s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v10, s3, s6, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_co_ci_u32_e64 v11, s3, s7, v13, s3 v_cmp_lt_u64_e64 s3, 0x752f, v[10:11] v_mov_b32_e32 v10, 1 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s16, s3 s_cbranch_execz .LBB0_86 ; %bb.85: ; in Loop: Header=BB0_74 Depth=5 v_dual_mov_b32 v10, s6 :: v_dual_mov_b32 v11, s7 global_atomic_cmpswap_b64 v[10:11], v[64:65], v[10:13], off glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e64 s3, v[10:11], v[12:13] s_delay_alu instid0(VALU_DEP_1) v_cndmask_b32_e64 v10, 1, 2, s3 .LBB0_86: ; %Flow957 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s16 .LBB0_87: ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s5 v_readfirstlane_b32 s39, v10 s_mov_b32 s5, 1 s_delay_alu instid0(VALU_DEP_1) s_cmp_eq_u32 s39, 1 s_cbranch_scc1 .LBB0_169 ; %bb.88: ; in Loop: Header=BB0_74 Depth=5 v_mov_b32_e32 v14, 0 v_mov_b32_e32 v15, 0 s_and_saveexec_b32 s23, vcc_lo s_cbranch_execz .LBB0_117 ; %bb.89: ; in Loop: Header=BB0_74 Depth=5 s_load_b64 s[16:17], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s3, v15 v_mov_b32_e32 v86, 0 v_mov_b32_e32 v87, 0 v_cmp_eq_u32_e64 s3, s3, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB0_95 ; %bb.90: ; in Loop: Header=BB0_74 Depth=5 s_waitcnt lgkmcnt(0) global_load_b64 v[12:13], v16, s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[10:11], v16, s[16:17] offset:40 global_load_b64 v[86:87], v16, s[16:17] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v11, v11, v13 v_and_b32_e32 v10, v10, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v11, v11, 24 v_mul_hi_u32 v14, v10, 24 v_mul_lo_u32 v10, v10, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v11, v14, v11 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v86, v10 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v11, vcc_lo, v87, v11, vcc_lo global_load_b64 v[10:11], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[86:87], v[12:13] s_cbranch_execz .LBB0_94 ; %bb.91: ; %.preheader3.i.i.i117.preheader ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s7, 0 .LBB0_92: ; %.preheader3.i.i.i117 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 s_clause 0x1 global_load_b64 v[10:11], v16, s[16:17] offset:40 global_load_b64 v[96:97], v16, s[16:17] v_dual_mov_b32 v12, v86 :: v_dual_mov_b32 v13, v87 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v10, v10, v12 v_and_b32_e32 v11, v11, v13 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[86:87], null, v10, 24, v[96:97] v_mov_b32_e32 v10, v87 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[96:97], null, v11, 24, v[10:11] v_mov_b32_e32 v87, v96 global_load_b64 v[10:11], v[86:87], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[86:87], v[12:13] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_92 ; %bb.93: ; %Flow951 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s7 .LBB0_94: ; %Flow953 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB0_95: ; %.loopexit4.i.i.i112 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[96:97], v16, s[16:17] offset:40 global_load_b128 v[10:13], v16, s[16:17] v_readfirstlane_b32 s18, v86 v_readfirstlane_b32 s19, v87 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s20, v96 v_readfirstlane_b32 s21, v97 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[20:21], s[18:19], s[20:21] s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB0_97 ; %bb.96: ; in Loop: Header=BB0_74 Depth=5 v_dual_mov_b32 v113, s6 :: v_dual_mov_b32 v114, 0 s_mul_i32 s6, s21, 24 s_mul_hi_u32 s7, s20, 24 v_dual_mov_b32 v115, 3 :: v_dual_mov_b32 v116, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s20, 24 s_waitcnt vmcnt(0) v_add_co_u32 v86, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v87, vcc_lo, s7, v11, vcc_lo global_store_b128 v[86:87], v[113:116], off offset:8 .LBB0_97: ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[20:21], 12 v_lshlrev_b64 v[14:15], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v86, vcc_lo, v12, s6 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo s_mov_b32 s5, s4 s_mov_b32 s6, s4 s_mov_b32 s7, s4 v_mov_b32_e32 v12, 0 v_add_co_u32 v86, vcc_lo, v86, v14 v_dual_mov_b32 v116, s7 :: v_dual_mov_b32 v113, s4 v_add_co_ci_u32_e32 v87, vcc_lo, v13, v15, vcc_lo v_dual_mov_b32 v115, s6 :: v_dual_mov_b32 v14, 0x1800 v_mov_b32_e32 v13, v12 v_dual_mov_b32 v15, v12 :: v_dual_mov_b32 v114, s5 s_clause 0x3 global_store_b128 v[86:87], v[12:15], off global_store_b128 v[86:87], v[113:116], off offset:16 global_store_b128 v[86:87], v[113:116], off offset:32 global_store_b128 v[86:87], v[113:116], off offset:48 s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB0_105 ; %bb.98: ; in Loop: Header=BB0_74 Depth=5 s_clause 0x1 global_load_b64 v[115:116], v16, s[16:17] offset:32 glc global_load_b64 v[12:13], v16, s[16:17] offset:40 v_dual_mov_b32 v113, s18 :: v_dual_mov_b32 v114, s19 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v12 v_readfirstlane_b32 s7, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[18:19] s_mul_i32 s7, s7, 24 s_mul_hi_u32 vcc_lo, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s7, vcc_lo, s7 v_add_co_u32 v96, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v97, vcc_lo, s7, v11, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[96:97], v[115:116], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v16, v[113:116], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[14:15], v[115:116] s_cbranch_execz .LBB0_101 ; %bb.99: ; %.preheader1.i.i.i115.preheader ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s7, 0 .LBB0_100: ; %.preheader1.i.i.i115 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_dual_mov_b32 v12, s18 :: v_dual_mov_b32 v13, s19 s_sleep 1 global_store_b64 v[96:97], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[12:15], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15] v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_100 .LBB0_101: ; %Flow949 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[12:13], v16, s[16:17] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v14, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v14 s_cbranch_execz .LBB0_103 ; %bb.102: ; in Loop: Header=BB0_74 Depth=5 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v14, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[12:13], v[14:15], off offset:8 .LBB0_103: ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[96:97], v[12:13], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[96:97] s_cbranch_vccnz .LBB0_105 ; %bb.104: ; in Loop: Header=BB0_74 Depth=5 global_load_b32 v15, v[12:13], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[96:97], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_105: ; %Flow950 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s21, 24 s_mul_hi_u32 s6, s20, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s20, 24 v_add_co_u32 v10, vcc_lo, v10, s5 v_add_co_ci_u32_e32 v11, vcc_lo, s6, v11, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v10, 20 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo .LBB0_106: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_mov_b32_e32 v12, 1 s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB0_108 ; %bb.107: ; in Loop: Header=BB0_106 Depth=6 global_load_b32 v12, v[10:11], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v12, 1, v12 .LBB0_108: ; in Loop: Header=BB0_106 Depth=6 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v12 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB0_110 ; %bb.109: ; in Loop: Header=BB0_106 Depth=6 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB0_111 .LBB0_110: ; in Loop: Header=BB0_106 Depth=6 s_mov_b32 s5, -1 .LBB0_111: ; %Flow944 ; in Loop: Header=BB0_106 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB0_106 ; %bb.112: ; in Loop: Header=BB0_74 Depth=5 global_load_b64 v[14:15], v[86:87], off s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB0_116 ; %bb.113: ; in Loop: Header=BB0_74 Depth=5 s_clause 0x2 global_load_b64 v[12:13], v16, s[16:17] offset:40 global_load_b64 v[96:97], v16, s[16:17] offset:24 glc global_load_b64 v[86:87], v16, s[16:17] s_waitcnt vmcnt(2) v_add_co_u32 v113, vcc_lo, v12, 1 v_add_co_ci_u32_e32 v114, vcc_lo, 0, v13, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v113, s18 v_add_co_ci_u32_e32 v11, vcc_lo, s19, v114, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] v_dual_cndmask_b32 v11, v11, v114 :: v_dual_cndmask_b32 v10, v10, v113 v_and_b32_e32 v13, v11, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v12, v10, v12 v_mul_hi_u32 v113, v12, 24 v_mul_lo_u32 v12, v12, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v86, vcc_lo, v86, v12 v_mov_b32_e32 v12, v96 v_mul_lo_u32 v13, v13, 24 v_add_nc_u32_e32 v13, v113, v13 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v87, vcc_lo, v87, v13, vcc_lo v_mov_b32_e32 v13, v97 global_store_b64 v[86:87], v[96:97], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[96:97] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_116 ; %bb.114: ; %.preheader.i.i.i114.preheader ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s3, 0 .LBB0_115: ; %.preheader.i.i.i114 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 global_store_b64 v[86:87], v[12:13], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[96:97], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[96:97], v[12:13] v_dual_mov_b32 v12, v96 :: v_dual_mov_b32 v13, v97 s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB0_115 .LBB0_116: ; %Flow942 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 .LBB0_117: ; %Flow954 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s23 s_waitcnt vmcnt(0) v_readfirstlane_b32 s18, v14 v_readfirstlane_b32 s19, v15 s_cmp_eq_u64 s[18:19], 0 s_cbranch_scc1 .LBB0_168 ; %bb.118: ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s3, exec_lo s_mov_b32 s5, exec_lo v_mbcnt_lo_u32_b32 v12, s3, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_u32_e32 0x300, v12 s_cbranch_execz .LBB0_121 ; %bb.119: ; %.preheader175.preheader ; in Loop: Header=BB0_74 Depth=5 v_lshlrev_b32_e32 v10, 3, v12 s_bcnt1_i32_b32 s6, s3 s_mov_b32 s16, s4 s_lshl_b32 s7, s6, 3 s_mov_b32 s17, 0 v_add_co_u32 v10, s3, s18, v10 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v11, null, s19, 0, s3 .LBB0_120: ; %.preheader175 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v12, s6, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mov_b32_e32 v14, v13 v_cmp_lt_u32_e32 vcc_lo, 0x2ff, v12 global_store_b64 v[10:11], v[13:14], off v_add_co_u32 v10, s3, v10, s7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e64 v11, s3, s16, v11, s3 s_or_b32 s17, vcc_lo, s17 s_and_not1_b32 exec_lo, exec_lo, s17 s_cbranch_execnz .LBB0_120 .LBB0_121: ; %Flow936 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 ; implicit-def: $sgpr5 .LBB0_122: ; %.loopexit176 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 ;;#ASMSTART ;;#ASMEND v_cmp_eq_u32_e32 vcc_lo, 0, v112 v_mov_b32_e32 v10, s22 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB0_124 ; %bb.123: ; in Loop: Header=BB0_122 Depth=6 global_load_b32 v10, v[54:55], off glc .LBB0_124: ; in Loop: Header=BB0_122 Depth=6 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) v_readfirstlane_b32 s22, v10 s_and_not1_b32 s3, s5, exec_lo s_and_b32 s5, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 s5, s3, s5 s_cmp_lg_u32 s22, 0x10100 s_cbranch_scc0 .LBB0_131 ; %bb.125: ; in Loop: Header=BB0_122 Depth=6 v_mov_b32_e32 v10, s39 s_and_saveexec_b32 s6, vcc_lo s_cbranch_execz .LBB0_129 ; %bb.126: ; in Loop: Header=BB0_122 Depth=6 s_add_i32 s3, s22, 0xffffff00 v_mov_b32_e32 v12, 0 s_lshr_b32 s3, s3, 8 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[10:11], null, v6, 0x1800, s[16:17] v_mad_u64_u32 v[14:15], null, s3, 24, v[10:11] v_dual_mov_b32 v11, s19 :: v_dual_mov_b32 v10, s18 v_mov_b32_e32 v13, v12 global_atomic_cmpswap_b64 v[10:11], v[14:15], v[10:13], off glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e64 s3, 0, v[10:11] v_mov_b32_e32 v10, s39 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s7, s3 s_cbranch_execz .LBB0_128 ; %bb.127: ; in Loop: Header=BB0_122 Depth=6 s_waitcnt_vscnt null, 0x0 global_atomic_add_u32 v[54:55], v39, off v_mov_b32_e32 v10, 0 .LBB0_128: ; %Flow929 ; in Loop: Header=BB0_122 Depth=6 s_or_b32 exec_lo, exec_lo, s7 .LBB0_129: ; in Loop: Header=BB0_122 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s6 v_readfirstlane_b32 s3, v10 s_delay_alu instid0(VALU_DEP_1) s_cmp_eq_u32 s3, 0 s_cbranch_scc1 .LBB0_132 ; %bb.130: ; in Loop: Header=BB0_122 Depth=6 s_mov_b32 s6, 0 s_and_not1_b32 vcc_lo, vcc_lo, exec_lo s_sleep 2 ; implicit-def: $sgpr39 s_branch .LBB0_133 .LBB0_131: ; in Loop: Header=BB0_122 Depth=6 s_mov_b32 s16, -1 s_mov_b32 s6, -1 ; implicit-def: $vgpr112 ; implicit-def: $sgpr22 ; implicit-def: $sgpr3 ; implicit-def: $sgpr7 s_branch .LBB0_134 .LBB0_132: ; in Loop: Header=BB0_122 Depth=6 s_mov_b32 s6, -1 ; implicit-def: $vgpr112 ; implicit-def: $sgpr22 ; implicit-def: $sgpr3 .LBB0_133: ; %Flow933 ; in Loop: Header=BB0_122 Depth=6 s_and_not1_b32 s5, s5, exec_lo s_and_b32 s17, vcc_lo, exec_lo s_mov_b32 s7, 0 s_mov_b32 s16, 0 s_or_b32 s5, s5, s17 .LBB0_134: ; %Flow932 ; in Loop: Header=BB0_122 Depth=6 s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_137 ; %bb.135: ; in Loop: Header=BB0_122 Depth=6 s_mov_b32 s39, s3 s_branch .LBB0_122 .LBB0_136: ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s3, -1 ; implicit-def: $sgpr18 s_branch .LBB0_189 .LBB0_137: ; %loop.exit.guard756 ; in Loop: Header=BB0_74 Depth=5 s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccz .LBB0_167 ; %bb.138: ; in Loop: Header=BB0_74 Depth=5 s_and_saveexec_b32 s40, s5 s_cbranch_execz .LBB0_166 ; %bb.139: ; in Loop: Header=BB0_74 Depth=5 s_load_b64 s[16:17], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s3, v15 v_mov_b32_e32 v86, 0 v_mov_b32_e32 v87, 0 v_cmp_eq_u32_e64 s3, s3, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB0_145 ; %bb.140: ; in Loop: Header=BB0_74 Depth=5 s_waitcnt lgkmcnt(0) global_load_b64 v[12:13], v16, s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[10:11], v16, s[16:17] offset:40 global_load_b64 v[86:87], v16, s[16:17] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v11, v11, v13 v_and_b32_e32 v10, v10, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v11, v11, 24 v_mul_hi_u32 v14, v10, 24 v_mul_lo_u32 v10, v10, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v11, v14, v11 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v86, v10 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v11, vcc_lo, v87, v11, vcc_lo global_load_b64 v[10:11], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[86:87], v[12:13] s_cbranch_execz .LBB0_144 ; %bb.141: ; %.preheader3.i.i.i124.preheader ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s7, 0 .LBB0_142: ; %.preheader3.i.i.i124 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 s_clause 0x1 global_load_b64 v[10:11], v16, s[16:17] offset:40 global_load_b64 v[96:97], v16, s[16:17] v_dual_mov_b32 v12, v86 :: v_dual_mov_b32 v13, v87 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v10, v10, v12 v_and_b32_e32 v11, v11, v13 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[86:87], null, v10, 24, v[96:97] v_mov_b32_e32 v10, v87 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[96:97], null, v11, 24, v[10:11] v_mov_b32_e32 v87, v96 global_load_b64 v[10:11], v[86:87], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[86:87], v[12:13] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_142 ; %bb.143: ; %Flow924 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s7 .LBB0_144: ; %Flow926 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB0_145: ; %.loopexit4.i.i.i119 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[96:97], v16, s[16:17] offset:40 global_load_b128 v[10:13], v16, s[16:17] v_readfirstlane_b32 s20, v86 v_readfirstlane_b32 s21, v87 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s22, v96 v_readfirstlane_b32 s23, v97 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[22:23], s[20:21], s[22:23] s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB0_147 ; %bb.146: ; in Loop: Header=BB0_74 Depth=5 v_dual_mov_b32 v112, s6 :: v_dual_mov_b32 v113, 0 s_mul_i32 s6, s23, 24 s_mul_hi_u32 s7, s22, 24 v_dual_mov_b32 v114, 3 :: v_dual_mov_b32 v115, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s22, 24 s_waitcnt vmcnt(0) v_add_co_u32 v86, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v87, vcc_lo, s7, v11, vcc_lo global_store_b128 v[86:87], v[112:115], off offset:8 .LBB0_147: ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[22:23], 12 v_lshlrev_b64 v[14:15], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v12, vcc_lo, v12, s6 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo s_mov_b32 s7, s4 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v86, vcc_lo, v12, v14 s_mov_b32 s5, s4 s_mov_b32 s6, s4 v_dual_mov_b32 v96, 0 :: v_dual_mov_b32 v113, s19 v_add_co_ci_u32_e32 v87, vcc_lo, v13, v15, vcc_lo v_dual_mov_b32 v112, s18 :: v_dual_mov_b32 v15, s7 v_dual_mov_b32 v14, s6 :: v_dual_mov_b32 v13, s5 s_delay_alu instid0(VALU_DEP_4) v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v97, v96 s_clause 0x4 global_store_b64 v[86:87], v[112:113], off global_store_b128 v[86:87], v[12:15], off offset:8 global_store_b128 v[86:87], v[12:15], off offset:24 global_store_b128 v[86:87], v[12:15], off offset:40 global_store_b64 v[86:87], v[96:97], off offset:56 s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB0_155 ; %bb.148: ; in Loop: Header=BB0_74 Depth=5 s_clause 0x1 global_load_b64 v[114:115], v16, s[16:17] offset:32 glc global_load_b64 v[12:13], v16, s[16:17] offset:40 v_dual_mov_b32 v112, s20 :: v_dual_mov_b32 v113, s21 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v12 v_readfirstlane_b32 s7, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[20:21] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s18, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s18, s18, s7 v_add_co_u32 v86, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v87, vcc_lo, s18, v11, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[86:87], v[114:115], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v16, v[112:115], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[14:15], v[114:115] s_cbranch_execz .LBB0_151 ; %bb.149: ; %.preheader1.i.i.i122.preheader ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s7, 0 .LBB0_150: ; %.preheader1.i.i.i122 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_dual_mov_b32 v12, s20 :: v_dual_mov_b32 v13, s21 s_sleep 1 global_store_b64 v[86:87], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[12:15], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15] v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_150 .LBB0_151: ; %Flow922 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[12:13], v16, s[16:17] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v14, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v14 s_cbranch_execz .LBB0_153 ; %bb.152: ; in Loop: Header=BB0_74 Depth=5 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v14, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[12:13], v[14:15], off offset:8 .LBB0_153: ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[86:87], v[12:13], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[86:87] s_cbranch_vccnz .LBB0_155 ; %bb.154: ; in Loop: Header=BB0_74 Depth=5 global_load_b32 v15, v[12:13], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[86:87], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_155: ; %Flow923 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s23, 24 s_mul_hi_u32 s6, s22, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s22, 24 v_add_co_u32 v10, vcc_lo, v10, s5 v_add_co_ci_u32_e32 v11, vcc_lo, s6, v11, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v10, 20 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo .LBB0_156: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_mov_b32_e32 v12, 1 s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB0_158 ; %bb.157: ; in Loop: Header=BB0_156 Depth=6 global_load_b32 v12, v[10:11], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v12, 1, v12 .LBB0_158: ; in Loop: Header=BB0_156 Depth=6 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v12 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB0_160 ; %bb.159: ; in Loop: Header=BB0_156 Depth=6 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB0_161 .LBB0_160: ; in Loop: Header=BB0_156 Depth=6 s_mov_b32 s5, -1 .LBB0_161: ; %Flow917 ; in Loop: Header=BB0_156 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB0_156 ; %bb.162: ; in Loop: Header=BB0_74 Depth=5 s_and_b32 exec_lo, exec_lo, s3 s_cbranch_execz .LBB0_166 ; %bb.163: ; in Loop: Header=BB0_74 Depth=5 s_clause 0x2 global_load_b64 v[12:13], v16, s[16:17] offset:40 global_load_b64 v[86:87], v16, s[16:17] offset:24 glc global_load_b64 v[14:15], v16, s[16:17] s_waitcnt vmcnt(2) v_add_co_u32 v96, vcc_lo, v12, 1 v_add_co_ci_u32_e32 v97, vcc_lo, 0, v13, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v96, s20 v_add_co_ci_u32_e32 v11, vcc_lo, s21, v97, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] v_dual_cndmask_b32 v11, v11, v97 :: v_dual_cndmask_b32 v10, v10, v96 v_and_b32_e32 v13, v11, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v12, v10, v12 v_mul_hi_u32 v96, v12, 24 v_mul_lo_u32 v12, v12, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v14, vcc_lo, v14, v12 v_mov_b32_e32 v12, v86 v_mul_lo_u32 v13, v13, 24 v_add_nc_u32_e32 v13, v96, v13 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v15, vcc_lo, v15, v13, vcc_lo v_mov_b32_e32 v13, v87 global_store_b64 v[14:15], v[86:87], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[86:87] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_166 ; %bb.164: ; %.preheader.i.i.i121.preheader ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s3, 0 .LBB0_165: ; %.preheader.i.i.i121 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 global_store_b64 v[14:15], v[12:13], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[86:87], v[12:13] v_dual_mov_b32 v12, v86 :: v_dual_mov_b32 v13, v87 s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB0_165 .LBB0_166: ; %Flow927 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s40 s_mov_b32 s7, s39 .LBB0_167: ; %Flow928 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s39, s7 .LBB0_168: ; %Flow938 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s5, s39 .LBB0_169: ; %__ockl_devmem_request.exit125 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_cmp_eq_u32 s5, 0 s_cselect_b32 s3, -1, 0 s_and_b32 vcc_lo, exec_lo, s3 s_cbranch_vccnz .LBB0_188 ; %bb.170: ; in Loop: Header=BB0_74 Depth=5 v_mbcnt_lo_u32_b32 v10, exec_lo, 0 s_mov_b32 s18, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB0_187 ; %bb.171: ; in Loop: Header=BB0_74 Depth=5 global_load_b64 v[10:11], v[64:65], off glc s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v10, vcc_lo, s6, v10 v_sub_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_u64_e32 vcc_lo, 0x7530, v[10:11] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_187 ; %bb.172: ; in Loop: Header=BB0_74 Depth=5 v_sub_nc_u32_e32 v10, 0x7530, v10 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) v_readfirstlane_b32 s6, v10 s_delay_alu instid0(VALU_DEP_1) s_ashr_i32 s7, s6, 31 s_waitcnt lgkmcnt(0) s_add_u32 s6, s16, s6 s_addc_u32 s7, s17, s7 .LBB0_173: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_waitcnt lgkmcnt(0) s_add_u32 s20, s16, 0x659 s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccnz .LBB0_176 ; %bb.174: ; %.preheader11.i138 ; in Loop: Header=BB0_173 Depth=6 s_sleep 0x7f s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) s_branch .LBB0_173 .LBB0_175: ; %.preheader9.i137 ; in Loop: Header=BB0_176 Depth=6 s_sleep 63 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_176: ; %Flow908 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_waitcnt lgkmcnt(0) s_add_u32 s20, s16, 0x326 s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccz .LBB0_175 ; %bb.177: ; %Flow905 ; in Loop: Header=BB0_74 Depth=5 s_add_u32 s20, s16, 0x18c s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccnz .LBB0_180 .LBB0_178: ; %.preheader7.i136 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 31 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) s_add_u32 s20, s16, 0x18c s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccnz .LBB0_178 s_branch .LBB0_180 .LBB0_179: ; %.preheader5.i135 ; in Loop: Header=BB0_180 Depth=6 s_sleep 15 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_180: ; %.loopexit8.i128 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_waitcnt lgkmcnt(0) s_add_u32 s20, s16, 0xc0 s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccz .LBB0_179 s_branch .LBB0_182 .LBB0_181: ; %.preheader3.i134 ; in Loop: Header=BB0_182 Depth=6 s_sleep 7 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_182: ; %Flow899 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_waitcnt lgkmcnt(0) s_add_u32 s20, s16, 0x59 s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccz .LBB0_181 s_branch .LBB0_184 .LBB0_183: ; %.preheader1.i133 ; in Loop: Header=BB0_184 Depth=6 s_sleep 3 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_184: ; %Flow896 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_waitcnt lgkmcnt(0) s_add_u32 s20, s16, 38 s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccz .LBB0_183 ; %bb.185: ; %Flow893 ; in Loop: Header=BB0_74 Depth=5 v_cmp_le_u64_e64 s16, s[6:7], s[16:17] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB0_187 .LBB0_186: ; %.preheader.i132 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) v_cmp_gt_u64_e64 s16, s[6:7], s[16:17] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB0_186 .LBB0_187: ; %__ockl_rtcwait_u32.exit139 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s18 s_cmp_lg_u32 s5, 2 v_mov_b32_e32 v85, s4 s_cselect_b32 s5, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) v_cndmask_b32_e64 v84, 0, 1, s5 .LBB0_188: ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s18, 0 .LBB0_189: ; %Flow960 ; in Loop: Header=BB0_74 Depth=5 s_and_b32 vcc_lo, exec_lo, s3 s_cbranch_vccz .LBB0_197 ; %bb.190: ; in Loop: Header=BB0_74 Depth=5 v_mov_b32_e32 v10, 1 v_mov_b32_e32 v11, 0 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_194 ; %bb.191: ; in Loop: Header=BB0_74 Depth=5 global_load_b64 v[12:13], v[66:67], off glc s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v10, vcc_lo, s6, v12 v_sub_co_ci_u32_e32 v11, vcc_lo, s7, v13, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_cmp_lt_u64_e32 vcc_lo, 0x4e1f, v[10:11] v_mov_b32_e32 v10, 1 v_mov_b32_e32 v11, 0 s_and_saveexec_b32 s5, vcc_lo s_cbranch_execz .LBB0_193 ; %bb.192: ; in Loop: Header=BB0_74 Depth=5 v_dual_mov_b32 v10, s6 :: v_dual_mov_b32 v11, s7 global_atomic_cmpswap_b64 v[10:11], v[66:67], v[10:13], off glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[12:13] v_mov_b32_e32 v11, s4 v_cndmask_b32_e64 v10, 0, 1, vcc_lo .LBB0_193: ; %Flow887 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 .LBB0_194: ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s3 v_readfirstlane_b32 s6, v10 v_readfirstlane_b32 s7, v11 s_mov_b32 s18, 0 s_delay_alu instid0(VALU_DEP_1) s_cmp_lg_u64 s[6:7], 0 s_cbranch_scc0 .LBB0_198 ; %bb.195: ; in Loop: Header=BB0_74 Depth=5 v_dual_mov_b32 v11, s7 :: v_dual_mov_b32 v10, s6 .LBB0_196: ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v85, v11 :: v_dual_mov_b32 v84, v10 .LBB0_197: ; %Flow963 ; in Loop: Header=BB0_74 Depth=5 s_xor_b32 s2, s18, -1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s2 s_cbranch_vccnz .LBB0_74 s_branch .LBB0_313 .LBB0_198: ; in Loop: Header=BB0_74 Depth=5 v_mov_b32_e32 v14, 0 v_mov_b32_e32 v15, 0 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_234 ; %bb.199: ; in Loop: Header=BB0_74 Depth=5 s_clause 0x1 global_load_b64 v[12:13], v16, s[12:13] glc global_load_b64 v[10:11], v16, s[14:15] s_waitcnt vmcnt(0) v_cmp_ge_u64_e32 vcc_lo, v[12:13], v[10:11] s_cbranch_vccnz .LBB0_203 ; %bb.200: ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s5, exec_lo s_mov_b32 s2, exec_lo v_mbcnt_lo_u32_b32 v86, s5, 0 ; implicit-def: $vgpr12_vgpr13 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v86 s_cbranch_execz .LBB0_202 ; %bb.201: ; in Loop: Header=BB0_74 Depth=5 s_bcnt1_i32_b32 s5, s5 v_mov_b32_e32 v13, 0 s_lshl_b32 s5, s5, 21 s_delay_alu instid0(SALU_CYCLE_1) v_mov_b32_e32 v12, s5 global_atomic_add_u64 v[12:13], v16, v[12:13], s[12:13] glc .LBB0_202: ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s2 s_waitcnt vmcnt(0) v_readfirstlane_b32 s7, v13 v_readfirstlane_b32 s6, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[14:15], null, v86, 0x200000, s[6:7] v_cmp_ge_u64_e64 s2, v[14:15], v[10:11] s_branch .LBB0_204 .LBB0_203: ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s2, -1 ; implicit-def: $vgpr14_vgpr15 .LBB0_204: ; %Flow884 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s22, s2 s_cbranch_execz .LBB0_233 ; %bb.205: ; in Loop: Header=BB0_74 Depth=5 s_load_b64 s[16:17], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s2, v15 v_mov_b32_e32 v86, 0 v_mov_b32_e32 v87, 0 v_cmp_eq_u32_e64 s2, s2, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_211 ; %bb.206: ; in Loop: Header=BB0_74 Depth=5 s_waitcnt lgkmcnt(0) global_load_b64 v[12:13], v16, s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[10:11], v16, s[16:17] offset:40 global_load_b64 v[86:87], v16, s[16:17] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v11, v11, v13 v_and_b32_e32 v10, v10, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v11, v11, 24 v_mul_hi_u32 v14, v10, 24 v_mul_lo_u32 v10, v10, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v11, v14, v11 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v86, v10 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v11, vcc_lo, v87, v11, vcc_lo global_load_b64 v[10:11], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[86:87], v[12:13] s_cbranch_execz .LBB0_210 ; %bb.207: ; %.preheader3.i.i.i145.preheader ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s7, 0 .LBB0_208: ; %.preheader3.i.i.i145 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 s_clause 0x1 global_load_b64 v[10:11], v16, s[16:17] offset:40 global_load_b64 v[96:97], v16, s[16:17] v_dual_mov_b32 v12, v86 :: v_dual_mov_b32 v13, v87 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v10, v10, v12 v_and_b32_e32 v11, v11, v13 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[86:87], null, v10, 24, v[96:97] v_mov_b32_e32 v10, v87 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[96:97], null, v11, 24, v[10:11] v_mov_b32_e32 v87, v96 global_load_b64 v[10:11], v[86:87], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[86:87], v[12:13] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_208 ; %bb.209: ; %Flow880 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s7 .LBB0_210: ; %Flow882 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB0_211: ; %.loopexit4.i.i.i140 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[96:97], v16, s[16:17] offset:40 global_load_b128 v[10:13], v16, s[16:17] v_readfirstlane_b32 s18, v86 v_readfirstlane_b32 s19, v87 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s20, v96 v_readfirstlane_b32 s21, v97 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[20:21], s[18:19], s[20:21] s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_213 ; %bb.212: ; in Loop: Header=BB0_74 Depth=5 v_dual_mov_b32 v112, s6 :: v_dual_mov_b32 v113, 0 s_mul_i32 s6, s21, 24 s_mul_hi_u32 s7, s20, 24 v_dual_mov_b32 v114, 3 :: v_dual_mov_b32 v115, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s20, 24 s_waitcnt vmcnt(0) v_add_co_u32 v86, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v87, vcc_lo, s7, v11, vcc_lo global_store_b128 v[86:87], v[112:115], off offset:8 .LBB0_213: ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[20:21], 12 v_lshlrev_b64 v[14:15], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v86, vcc_lo, v12, s6 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo s_mov_b32 s5, s4 s_mov_b32 s6, s4 s_mov_b32 s7, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v115, s7 v_add_co_u32 v86, vcc_lo, v86, v14 v_add_co_ci_u32_e32 v87, vcc_lo, v13, v15, vcc_lo v_dual_mov_b32 v14, 0x200000 :: v_dual_mov_b32 v13, v12 v_dual_mov_b32 v15, v12 :: v_dual_mov_b32 v114, s6 v_dual_mov_b32 v113, s5 :: v_dual_mov_b32 v112, s4 s_clause 0x3 global_store_b128 v[86:87], v[12:15], off global_store_b128 v[86:87], v[112:115], off offset:16 global_store_b128 v[86:87], v[112:115], off offset:32 global_store_b128 v[86:87], v[112:115], off offset:48 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_221 ; %bb.214: ; in Loop: Header=BB0_74 Depth=5 s_clause 0x1 global_load_b64 v[114:115], v16, s[16:17] offset:32 glc global_load_b64 v[12:13], v16, s[16:17] offset:40 v_dual_mov_b32 v112, s18 :: v_dual_mov_b32 v113, s19 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v12 v_readfirstlane_b32 s7, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[18:19] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s23, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s23, s23, s7 v_add_co_u32 v96, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v97, vcc_lo, s23, v11, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[96:97], v[114:115], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v16, v[112:115], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[14:15], v[114:115] s_cbranch_execz .LBB0_217 ; %bb.215: ; %.preheader1.i.i.i143.preheader ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s7, 0 .LBB0_216: ; %.preheader1.i.i.i143 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_dual_mov_b32 v12, s18 :: v_dual_mov_b32 v13, s19 s_sleep 1 global_store_b64 v[96:97], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[12:15], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15] v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_216 .LBB0_217: ; %Flow878 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[12:13], v16, s[16:17] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v14, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v14 s_cbranch_execz .LBB0_219 ; %bb.218: ; in Loop: Header=BB0_74 Depth=5 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v14, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[12:13], v[14:15], off offset:8 .LBB0_219: ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[96:97], v[12:13], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[96:97] s_cbranch_vccnz .LBB0_221 ; %bb.220: ; in Loop: Header=BB0_74 Depth=5 global_load_b32 v15, v[12:13], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[96:97], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_221: ; %Flow879 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s21, 24 s_mul_hi_u32 s6, s20, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s20, 24 v_add_co_u32 v10, vcc_lo, v10, s5 v_add_co_ci_u32_e32 v11, vcc_lo, s6, v11, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v10, 20 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo .LBB0_222: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_mov_b32_e32 v12, 1 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_224 ; %bb.223: ; in Loop: Header=BB0_222 Depth=6 global_load_b32 v12, v[10:11], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v12, 1, v12 .LBB0_224: ; in Loop: Header=BB0_222 Depth=6 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v12 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB0_226 ; %bb.225: ; in Loop: Header=BB0_222 Depth=6 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB0_227 .LBB0_226: ; in Loop: Header=BB0_222 Depth=6 s_mov_b32 s5, -1 .LBB0_227: ; %Flow873 ; in Loop: Header=BB0_222 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB0_222 ; %bb.228: ; in Loop: Header=BB0_74 Depth=5 global_load_b64 v[14:15], v[86:87], off s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_232 ; %bb.229: ; in Loop: Header=BB0_74 Depth=5 s_clause 0x2 global_load_b64 v[12:13], v16, s[16:17] offset:40 global_load_b64 v[96:97], v16, s[16:17] offset:24 glc global_load_b64 v[86:87], v16, s[16:17] s_waitcnt vmcnt(2) v_add_co_u32 v112, vcc_lo, v12, 1 v_add_co_ci_u32_e32 v113, vcc_lo, 0, v13, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v112, s18 v_add_co_ci_u32_e32 v11, vcc_lo, s19, v113, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] v_dual_cndmask_b32 v11, v11, v113 :: v_dual_cndmask_b32 v10, v10, v112 v_and_b32_e32 v13, v11, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v12, v10, v12 v_mul_hi_u32 v112, v12, 24 v_mul_lo_u32 v12, v12, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v86, vcc_lo, v86, v12 v_mov_b32_e32 v12, v96 v_mul_lo_u32 v13, v13, 24 v_add_nc_u32_e32 v13, v112, v13 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v87, vcc_lo, v87, v13, vcc_lo v_mov_b32_e32 v13, v97 global_store_b64 v[86:87], v[96:97], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[96:97] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_232 ; %bb.230: ; %.preheader.i.i.i142.preheader ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s2, 0 .LBB0_231: ; %.preheader.i.i.i142 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 global_store_b64 v[86:87], v[12:13], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[96:97], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[96:97], v[12:13] v_dual_mov_b32 v12, v96 :: v_dual_mov_b32 v13, v97 s_or_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB0_231 .LBB0_232: ; %Flow871 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 .LBB0_233: ; %Flow885 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s22 .LBB0_234: ; %__ockl_devmem_request.exit146 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) v_readfirstlane_b32 s16, v14 v_readfirstlane_b32 s17, v15 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_delay_alu instid0(VALU_DEP_3) s_cmp_eq_u64 s[16:17], 0 s_cbranch_scc1 .LBB0_279 ; %bb.235: ; in Loop: Header=BB0_74 Depth=5 v_mbcnt_lo_u32_b32 v10, exec_lo, 0 ;;#ASMSTART ;;#ASMEND global_load_b32 v14, v[50:51], off s_bcnt1_i32_b32 s3, exec_lo s_add_u32 s6, s16, 16 s_addc_u32 s7, s17, 0 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v11, 31, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_lshrrev_b32_e32 v13, 5, v11 s_and_saveexec_b32 s2, s1 s_xor_b32 s5, exec_lo, s2 s_cbranch_execz .LBB0_243 ; %bb.236: ; in Loop: Header=BB0_74 Depth=5 global_load_b32 v15, v[68:69], off s_mov_b32 s18, exec_lo v_cmpx_lt_u32_e64 v10, v13 s_cbranch_execz .LBB0_239 ; %bb.237: ; %.preheader172.preheader ; in Loop: Header=BB0_74 Depth=5 v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v86, v10 s_add_u32 s2, s16, 16 s_addc_u32 s19, s17, 0 s_mov_b32 s20, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[11:12], 2, v[10:11] s_mov_b32 s21, 0 v_add_co_u32 v11, vcc_lo, s2, v11 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v12, vcc_lo, s19, v12, vcc_lo s_lshl_b32 s19, s3, 2 .LBB0_238: ; %.preheader172 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_add_nc_u32_e32 v86, s3, v86 global_store_b32 v[11:12], v16, off v_add_co_u32 v11, s2, v11, s19 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e64 v12, s2, s20, v12, s2 v_cmp_ge_u32_e32 vcc_lo, v86, v13 s_or_b32 s21, vcc_lo, s21 s_and_not1_b32 exec_lo, exec_lo, s21 s_cbranch_execnz .LBB0_238 .LBB0_239: ; %Flow860 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s18 global_load_b32 v86, v[70:71], off s_mov_b32 s2, exec_lo s_waitcnt vmcnt(0) v_mad_u64_u32 v[11:12], null, v15, v10, v[86:87] s_delay_alu instid0(VALU_DEP_1) v_cmpx_lt_u32_e64 v11, v14 s_cbranch_execz .LBB0_242 ; %bb.240: ; %.preheader170.preheader ; in Loop: Header=BB0_74 Depth=5 v_mul_lo_u32 v12, v15, s3 s_mov_b32 s18, 0 .LBB0_241: ; %.preheader170 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_lshlrev_b32_e64 v15, v11, 1 v_lshrrev_b32_e32 v86, 3, v11 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v11, v11, v12 v_and_b32_e32 v86, 0x1ffffffc, v86 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_ge_u32_e32 vcc_lo, v11, v14 global_store_b32 v86, v15, s[6:7] s_or_b32 s18, vcc_lo, s18 s_and_not1_b32 exec_lo, exec_lo, s18 s_cbranch_execnz .LBB0_241 .LBB0_242: ; %Flow857 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s2 .LBB0_243: ; %Flow865 ; in Loop: Header=BB0_74 Depth=5 s_and_not1_saveexec_b32 s5, s5 s_cbranch_execz .LBB0_248 ; %bb.244: ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s18, exec_lo v_cmpx_lt_u32_e64 v10, v13 s_cbranch_execz .LBB0_247 ; %bb.245: ; %.preheader.preheader ; in Loop: Header=BB0_74 Depth=5 global_load_b32 v15, v[80:81], off v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v86, v10 s_add_u32 s2, s16, 16 s_addc_u32 s19, s17, 0 s_mov_b32 s20, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[11:12], 2, v[10:11] s_mov_b32 s21, 0 v_add_co_u32 v11, vcc_lo, s2, v11 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v12, vcc_lo, s19, v12, vcc_lo s_lshl_b32 s19, s3, 2 .LBB0_246: ; %.preheader ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_add_nc_u32_e32 v86, s3, v86 s_waitcnt vmcnt(0) global_store_b32 v[11:12], v15, off v_add_co_u32 v11, s2, v11, s19 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e64 v12, s2, s20, v12, s2 v_cmp_ge_u32_e32 vcc_lo, v86, v13 s_or_b32 s21, vcc_lo, s21 s_and_not1_b32 exec_lo, exec_lo, s21 s_cbranch_execnz .LBB0_246 .LBB0_247: ; %Flow863 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s18 .LBB0_248: ; %.loopexit ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_mov_b32 s2, exec_lo v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB0_252 ; %bb.249: ; in Loop: Header=BB0_74 Depth=5 v_and_b32_e32 v10, 31, v14 s_mov_b32 s3, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_ne_u32_e32 0, v10 s_cbranch_execz .LBB0_251 ; %bb.250: ; in Loop: Header=BB0_74 Depth=5 v_add_nc_u32_e32 v15, -1, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[11:12], 2, v[15:16] v_add_co_u32 v11, vcc_lo, s6, v11 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo global_load_b32 v13, v[11:12], off s_waitcnt vmcnt(0) v_lshl_or_b32 v10, -1, v10, v13 global_store_b32 v[11:12], v10, off .LBB0_251: ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s3 global_store_b128 v16, v[6:9], s[16:17] .LBB0_252: ; %Flow854 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $sgpr5 .LBB0_253: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 ;;#ASMSTART ;;#ASMEND v_cmp_eq_u32_e64 s2, 0, v103 v_mov_b32_e32 v10, s37 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_255 ; %bb.254: ; in Loop: Header=BB0_253 Depth=6 global_load_b32 v10, v[52:53], off glc .LBB0_255: ; in Loop: Header=BB0_253 Depth=6 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) v_readfirstlane_b32 s37, v10 s_and_not1_b32 s3, s5, exec_lo s_and_b32 s5, s2, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 s5, s3, s5 s_cmp_eq_u32 s37, 0x10100 s_cbranch_scc1 .LBB0_262 ; %bb.256: ; in Loop: Header=BB0_253 Depth=6 v_mov_b32_e32 v10, s38 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_258 ; %bb.257: ; in Loop: Header=BB0_253 Depth=6 global_load_b32 v10, v[54:55], off glc .LBB0_258: ; in Loop: Header=BB0_253 Depth=6 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) v_readfirstlane_b32 s38, v10 s_delay_alu instid0(VALU_DEP_1) s_cmp_lg_u32 s37, s38 s_cbranch_scc0 .LBB0_263 ; %bb.259: ; in Loop: Header=BB0_253 Depth=6 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_270 ; %bb.260: ; in Loop: Header=BB0_253 Depth=6 s_cmpk_lt_u32 s37, 0x100 s_cbranch_scc0 .LBB0_264 ; %bb.261: ; in Loop: Header=BB0_253 Depth=6 s_add_u32 s6, s10, 0x2800 s_addc_u32 s7, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[12:13], null, v6, 0x1800, s[6:7] s_mov_b32 s6, 0 v_mad_u64_u32 v[10:11], null, s37, 24, v[12:13] s_branch .LBB0_265 .LBB0_262: ; in Loop: Header=BB0_253 Depth=6 s_mov_b64 s[2:3], 0 s_mov_b32 s20, -1 s_mov_b32 s18, 0 s_mov_b32 s19, -1 ; implicit-def: $sgpr37 ; implicit-def: $sgpr38 ; implicit-def: $sgpr6_sgpr7 s_branch .LBB0_275 .LBB0_263: ; in Loop: Header=BB0_253 Depth=6 s_mov_b32 s18, -1 s_mov_b32 s19, -1 ; implicit-def: $sgpr37 ; implicit-def: $sgpr38 ; implicit-def: $sgpr6_sgpr7 s_branch .LBB0_274 .LBB0_264: ; in Loop: Header=BB0_253 Depth=6 s_mov_b32 s6, -1 ; implicit-def: $vgpr10_vgpr11 .LBB0_265: ; %Flow846 ; in Loop: Header=BB0_253 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_267 ; %bb.266: ; in Loop: Header=BB0_253 Depth=6 s_add_i32 s6, s37, 0xffffff00 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_lshr_b32 s18, s6, 8 s_add_u32 s6, s10, 0x2800 s_addc_u32 s7, s11, 0 v_mad_u64_u32 v[10:11], null, v6, 0x1800, s[6:7] s_and_b32 s6, s37, 0xff s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[12:13], null, s18, 24, v[10:11] global_load_b64 v[12:13], v[12:13], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[10:11], null, s6, 24, v[12:13] .LBB0_267: ; in Loop: Header=BB0_253 Depth=6 v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v13, s17 v_mov_b32_e32 v86, s37 s_delay_alu instid0(VALU_DEP_2) v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v15, v14 global_store_b32 v16, v86, s[16:17] offset:4 global_atomic_cmpswap_b64 v[12:13], v[10:11], v[12:15], off offset:8 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13] v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_and_saveexec_b32 s6, vcc_lo s_cbranch_execz .LBB0_269 ; %bb.268: ; in Loop: Header=BB0_253 Depth=6 s_waitcnt_vscnt null, 0x0 global_atomic_add_u32 v[52:53], v98, off v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10 .LBB0_269: ; %Flow844 ; in Loop: Header=BB0_253 Depth=6 s_or_b32 exec_lo, exec_lo, s6 .LBB0_270: ; %Flow847 ; in Loop: Header=BB0_253 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s3 v_readfirstlane_b32 s6, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s7, v13 s_cmp_lg_u64 s[6:7], 0 s_cbranch_scc0 .LBB0_272 ; %bb.271: ; in Loop: Header=BB0_253 Depth=6 s_mov_b32 s19, -1 ; implicit-def: $sgpr37 ; implicit-def: $sgpr38 s_branch .LBB0_273 .LBB0_272: ; in Loop: Header=BB0_253 Depth=6 s_mov_b32 s19, 0 s_and_not1_b32 s2, s2, exec_lo s_sleep 2 .LBB0_273: ; %Flow852 ; in Loop: Header=BB0_253 Depth=6 s_mov_b32 s18, 0 .LBB0_274: ; %Flow851 ; in Loop: Header=BB0_253 Depth=6 s_and_not1_b32 s3, s5, exec_lo s_and_b32 s2, s2, exec_lo s_mov_b32 s20, 0 s_or_b32 s5, s3, s2 ; implicit-def: $sgpr2_sgpr3 .LBB0_275: ; %Flow850 ; in Loop: Header=BB0_253 Depth=6 s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccz .LBB0_253 ; %bb.276: ; %loop.exit.guard760 ; in Loop: Header=BB0_74 Depth=5 v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2 s_and_b32 vcc_lo, exec_lo, s20 s_cbranch_vccnz .LBB0_196 ; %bb.277: ; %loop.exit.guard761 ; in Loop: Header=BB0_74 Depth=5 s_xor_b32 s2, s18, -1 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s2 s_cbranch_vccz .LBB0_280 ; %bb.278: ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s18, 0 s_branch .LBB0_281 .LBB0_279: ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s18, 0 s_branch .LBB0_196 .LBB0_280: ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s18, -1 ; implicit-def: $sgpr6_sgpr7 .LBB0_281: ; %Flow841 ; in Loop: Header=BB0_74 Depth=5 v_dual_mov_b32 v11, s7 :: v_dual_mov_b32 v10, s6 s_and_not1_b32 vcc_lo, exec_lo, s18 s_cbranch_vccnz .LBB0_196 ; %bb.282: ; in Loop: Header=BB0_74 Depth=5 s_and_saveexec_b32 s3, s5 s_cbranch_execz .LBB0_311 ; %bb.283: ; in Loop: Header=BB0_74 Depth=5 s_load_b64 s[18:19], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s2, v15 v_mov_b32_e32 v86, 0 v_mov_b32_e32 v87, 0 v_cmp_eq_u32_e64 s2, s2, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_289 ; %bb.284: ; in Loop: Header=BB0_74 Depth=5 s_waitcnt lgkmcnt(0) global_load_b64 v[12:13], v16, s[18:19] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[10:11], v16, s[18:19] offset:40 global_load_b64 v[86:87], v16, s[18:19] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v11, v11, v13 v_and_b32_e32 v10, v10, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v11, v11, 24 v_mul_hi_u32 v14, v10, 24 v_mul_lo_u32 v10, v10, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v11, v14, v11 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v86, v10 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v11, vcc_lo, v87, v11, vcc_lo global_load_b64 v[10:11], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[18:19] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[86:87], v[12:13] s_cbranch_execz .LBB0_288 ; %bb.285: ; %.preheader3.i.i.i152.preheader ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s7, 0 .LBB0_286: ; %.preheader3.i.i.i152 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 s_clause 0x1 global_load_b64 v[10:11], v16, s[18:19] offset:40 global_load_b64 v[96:97], v16, s[18:19] v_dual_mov_b32 v12, v86 :: v_dual_mov_b32 v13, v87 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v10, v10, v12 v_and_b32_e32 v11, v11, v13 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[86:87], null, v10, 24, v[96:97] v_mov_b32_e32 v10, v87 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[96:97], null, v11, 24, v[10:11] v_mov_b32_e32 v87, v96 global_load_b64 v[10:11], v[86:87], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[18:19] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[86:87], v[12:13] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_286 ; %bb.287: ; %Flow837 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s7 .LBB0_288: ; %Flow839 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB0_289: ; %.loopexit4.i.i.i147 ; in Loop: Header=BB0_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[96:97], v16, s[18:19] offset:40 global_load_b128 v[10:13], v16, s[18:19] v_readfirstlane_b32 s20, v86 v_readfirstlane_b32 s21, v87 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s22, v96 v_readfirstlane_b32 s23, v97 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[22:23], s[20:21], s[22:23] s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_291 ; %bb.290: ; in Loop: Header=BB0_74 Depth=5 v_dual_mov_b32 v112, s6 :: v_dual_mov_b32 v113, 0 s_mul_i32 s6, s23, 24 s_mul_hi_u32 s7, s22, 24 v_dual_mov_b32 v114, 3 :: v_dual_mov_b32 v115, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s22, 24 s_waitcnt vmcnt(0) v_add_co_u32 v86, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v87, vcc_lo, s7, v11, vcc_lo global_store_b128 v[86:87], v[112:115], off offset:8 .LBB0_291: ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[22:23], 12 v_lshlrev_b64 v[14:15], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v12, vcc_lo, v12, s6 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo s_mov_b32 s7, s4 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v86, vcc_lo, v12, v14 s_mov_b32 s5, s4 s_mov_b32 s6, s4 v_dual_mov_b32 v96, 0 :: v_dual_mov_b32 v113, s17 v_add_co_ci_u32_e32 v87, vcc_lo, v13, v15, vcc_lo v_dual_mov_b32 v112, s16 :: v_dual_mov_b32 v15, s7 v_dual_mov_b32 v14, s6 :: v_dual_mov_b32 v13, s5 s_delay_alu instid0(VALU_DEP_4) v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v97, v96 s_clause 0x4 global_store_b64 v[86:87], v[112:113], off global_store_b128 v[86:87], v[12:15], off offset:8 global_store_b128 v[86:87], v[12:15], off offset:24 global_store_b128 v[86:87], v[12:15], off offset:40 global_store_b64 v[86:87], v[96:97], off offset:56 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_299 ; %bb.292: ; in Loop: Header=BB0_74 Depth=5 s_clause 0x1 global_load_b64 v[114:115], v16, s[18:19] offset:32 glc global_load_b64 v[12:13], v16, s[18:19] offset:40 v_dual_mov_b32 v112, s20 :: v_dual_mov_b32 v113, s21 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v12 v_readfirstlane_b32 s7, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[20:21] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s16, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s16, s16, s7 v_add_co_u32 v86, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v87, vcc_lo, s16, v11, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[86:87], v[114:115], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v16, v[112:115], s[18:19] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[14:15], v[114:115] s_cbranch_execz .LBB0_295 ; %bb.293: ; %.preheader1.i.i.i150.preheader ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s7, 0 .LBB0_294: ; %.preheader1.i.i.i150 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_dual_mov_b32 v12, s20 :: v_dual_mov_b32 v13, s21 s_sleep 1 global_store_b64 v[86:87], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[12:15], s[18:19] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15] v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_294 .LBB0_295: ; %Flow835 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[12:13], v16, s[18:19] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v14, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v14 s_cbranch_execz .LBB0_297 ; %bb.296: ; in Loop: Header=BB0_74 Depth=5 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v14, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[12:13], v[14:15], off offset:8 .LBB0_297: ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[86:87], v[12:13], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[86:87] s_cbranch_vccnz .LBB0_299 ; %bb.298: ; in Loop: Header=BB0_74 Depth=5 global_load_b32 v15, v[12:13], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[86:87], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_299: ; %Flow836 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s23, 24 s_mul_hi_u32 s6, s22, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s22, 24 v_add_co_u32 v10, vcc_lo, v10, s5 v_add_co_ci_u32_e32 v11, vcc_lo, s6, v11, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v10, 20 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo .LBB0_300: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_mov_b32_e32 v12, 1 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_302 ; %bb.301: ; in Loop: Header=BB0_300 Depth=6 global_load_b32 v12, v[10:11], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v12, 1, v12 .LBB0_302: ; in Loop: Header=BB0_300 Depth=6 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v12 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB0_304 ; %bb.303: ; in Loop: Header=BB0_300 Depth=6 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB0_305 .LBB0_304: ; in Loop: Header=BB0_300 Depth=6 s_mov_b32 s5, -1 .LBB0_305: ; %Flow830 ; in Loop: Header=BB0_300 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB0_300 ; %bb.306: ; in Loop: Header=BB0_74 Depth=5 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_310 ; %bb.307: ; in Loop: Header=BB0_74 Depth=5 s_clause 0x2 global_load_b64 v[12:13], v16, s[18:19] offset:40 global_load_b64 v[86:87], v16, s[18:19] offset:24 glc global_load_b64 v[14:15], v16, s[18:19] s_waitcnt vmcnt(2) v_add_co_u32 v96, vcc_lo, v12, 1 v_add_co_ci_u32_e32 v97, vcc_lo, 0, v13, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v96, s20 v_add_co_ci_u32_e32 v11, vcc_lo, s21, v97, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] v_dual_cndmask_b32 v11, v11, v97 :: v_dual_cndmask_b32 v10, v10, v96 v_and_b32_e32 v13, v11, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v12, v10, v12 v_mul_hi_u32 v96, v12, 24 v_mul_lo_u32 v12, v12, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v14, vcc_lo, v14, v12 v_mov_b32_e32 v12, v86 v_mul_lo_u32 v13, v13, 24 v_add_nc_u32_e32 v13, v96, v13 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v15, vcc_lo, v15, v13, vcc_lo v_mov_b32_e32 v13, v87 global_store_b64 v[14:15], v[86:87], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[10:13], s[18:19] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[86:87] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_310 ; %bb.308: ; %.preheader.i.i.i149.preheader ; in Loop: Header=BB0_74 Depth=5 s_mov_b32 s2, 0 .LBB0_309: ; %.preheader.i.i.i149 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; Parent Loop BB0_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 global_store_b64 v[14:15], v[12:13], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[18:19] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[86:87], v[12:13] v_dual_mov_b32 v12, v86 :: v_dual_mov_b32 v13, v87 s_or_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB0_309 .LBB0_310: ; %Flow828 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 v_mov_b32_e32 v103, 0 .LBB0_311: ; %Flow840 ; in Loop: Header=BB0_74 Depth=5 s_or_b32 exec_lo, exec_lo, s3 v_dual_mov_b32 v10, v84 :: v_dual_mov_b32 v11, v85 s_mov_b32 s18, -1 s_branch .LBB0_196 .LBB0_312: ; in Loop: Header=BB0_43 Depth=4 ; implicit-def: $vgpr82_vgpr83 ; implicit-def: $sgpr36 ; implicit-def: $vgpr102 s_branch .LBB0_336 .LBB0_313: ; in Loop: Header=BB0_43 Depth=4 v_cmp_ne_u64_e64 s5, 1, v[84:85] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s5 s_cbranch_vccz .LBB0_315 ; %bb.314: ; in Loop: Header=BB0_43 Depth=4 v_dual_mov_b32 v82, v84 :: v_dual_mov_b32 v83, v85 s_branch .LBB0_335 .LBB0_315: ; in Loop: Header=BB0_43 Depth=4 v_mbcnt_lo_u32_b32 v10, exec_lo, 0 s_mov_b32 s16, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB0_332 ; %bb.316: ; in Loop: Header=BB0_43 Depth=4 global_load_b64 v[10:11], v[66:67], off glc s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v10, vcc_lo, s2, v10 v_sub_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_u64_e32 vcc_lo, 0x4e20, v[10:11] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_332 ; %bb.317: ; in Loop: Header=BB0_43 Depth=4 v_sub_nc_u32_e32 v10, 0x4e20, v10 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) v_readfirstlane_b32 s2, v10 s_delay_alu instid0(VALU_DEP_1) s_ashr_i32 s3, s2, 31 s_waitcnt lgkmcnt(0) s_add_u32 s2, s6, s2 s_addc_u32 s3, s7, s3 .LBB0_318: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x659 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccnz .LBB0_321 ; %bb.319: ; %.preheader11.i166 ; in Loop: Header=BB0_318 Depth=5 s_sleep 0x7f s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_branch .LBB0_318 .LBB0_320: ; %.preheader9.i165 ; in Loop: Header=BB0_321 Depth=5 s_sleep 63 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_321: ; %Flow822 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x326 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccz .LBB0_320 ; %bb.322: ; %Flow819 ; in Loop: Header=BB0_43 Depth=4 s_add_u32 s18, s6, 0x18c s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccnz .LBB0_325 .LBB0_323: ; %.preheader7.i164 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 31 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x18c s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccnz .LBB0_323 s_branch .LBB0_325 .LBB0_324: ; %.preheader5.i163 ; in Loop: Header=BB0_325 Depth=5 s_sleep 15 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_325: ; %.loopexit8.i156 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0xc0 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccz .LBB0_324 s_branch .LBB0_327 .LBB0_326: ; %.preheader3.i162 ; in Loop: Header=BB0_327 Depth=5 s_sleep 7 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_327: ; %Flow813 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x59 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccz .LBB0_326 s_branch .LBB0_329 .LBB0_328: ; %.preheader1.i161 ; in Loop: Header=BB0_329 Depth=5 s_sleep 3 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_329: ; %Flow810 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 38 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccz .LBB0_328 ; %bb.330: ; %Flow807 ; in Loop: Header=BB0_43 Depth=4 v_cmp_le_u64_e64 s6, s[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_332 .LBB0_331: ; %.preheader.i160 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_11 Depth=3 ; Parent Loop BB0_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) v_cmp_gt_u64_e64 s6, s[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_331 .LBB0_332: ; %__ockl_rtcwait_u32.exit167 ; in Loop: Header=BB0_43 Depth=4 s_or_b32 exec_lo, exec_lo, s16 v_mov_b32_e32 v10, s36 s_mov_b32 s2, exec_lo v_cmpx_eq_u32_e32 0, v102 s_cbranch_execz .LBB0_334 ; %bb.333: ; in Loop: Header=BB0_43 Depth=4 global_load_b32 v10, v[52:53], off glc .LBB0_334: ; in Loop: Header=BB0_43 Depth=4 s_or_b32 exec_lo, exec_lo, s2 s_waitcnt vmcnt(0) v_readfirstlane_b32 s36, v10 .LBB0_335: ; in Loop: Header=BB0_43 Depth=4 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v10, v82 :: v_dual_mov_b32 v11, v83 s_mov_b32 s6, 0 .LBB0_336: ; %Flow969 ; in Loop: Header=BB0_43 Depth=4 s_and_b32 vcc_lo, exec_lo, s5 s_cbranch_vccz .LBB0_43 ; %bb.337: ; %Flow970 ; in Loop: Header=BB0_11 Depth=3 v_mov_b32_e32 v6, v2 .LBB0_338: ; %Flow971 ; in Loop: Header=BB0_11 Depth=3 v_dual_mov_b32 v7, v10 :: v_dual_mov_b32 v8, v11 s_delay_alu instid0(VALU_DEP_2) v_mov_b32_e32 v15, v6 s_and_b32 s3, s6, exec_lo .LBB0_339: ; %Flow973 ; in Loop: Header=BB0_11 Depth=3 s_or_b32 exec_lo, exec_lo, s34 .LBB0_340: ; %.loopexit187 ; in Loop: Header=BB0_11 Depth=3 s_xor_b32 s1, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s1, exec_lo, s1 s_or_b32 s30, s1, s30 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s30 s_cbranch_execnz .LBB0_11 ; %bb.341: ; %Flow986 ; in Loop: Header=BB0_6 Depth=2 s_or_b32 exec_lo, exec_lo, s30 s_mov_b32 s1, 0 s_branch .LBB0_343 .LBB0_342: ; in Loop: Header=BB0_6 Depth=2 s_mov_b32 s1, -1 ; implicit-def: $vgpr7_vgpr8 .LBB0_343: ; %Flow1168 ; in Loop: Header=BB0_6 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s1 s_cbranch_vccz .LBB0_640 ; %bb.344: ; in Loop: Header=BB0_6 Depth=2 v_mbcnt_lo_u32_b32 v50, exec_lo, 0 s_bcnt1_i32_b32 s30, exec_lo ; implicit-def: $vgpr12_vgpr13 .LBB0_345: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; => This Loop Header: Depth=3 ; Child Loop BB0_349 Depth 4 ; Child Loop BB0_377 Depth 4 ; Child Loop BB0_395 Depth 5 ; Child Loop BB0_403 Depth 5 ; Child Loop BB0_409 Depth 5 ; Child Loop BB0_418 Depth 5 ; Child Loop BB0_423 Depth 5 ; Child Loop BB0_425 Depth 5 ; Child Loop BB0_445 Depth 5 ; Child Loop BB0_453 Depth 5 ; Child Loop BB0_459 Depth 5 ; Child Loop BB0_468 Depth 5 ; Child Loop BB0_476 Depth 5 ; Child Loop BB0_479 Depth 5 ; Child Loop BB0_481 Depth 5 ; Child Loop BB0_483 Depth 5 ; Child Loop BB0_485 Depth 5 ; Child Loop BB0_487 Depth 5 ; Child Loop BB0_489 Depth 5 ; Child Loop BB0_511 Depth 5 ; Child Loop BB0_519 Depth 5 ; Child Loop BB0_525 Depth 5 ; Child Loop BB0_534 Depth 5 ; Child Loop BB0_541 Depth 5 ; Child Loop BB0_544 Depth 5 ; Child Loop BB0_549 Depth 5 ; Child Loop BB0_556 Depth 5 ; Child Loop BB0_589 Depth 5 ; Child Loop BB0_597 Depth 5 ; Child Loop BB0_603 Depth 5 ; Child Loop BB0_612 Depth 5 ; Child Loop BB0_621 Depth 4 ; Child Loop BB0_624 Depth 4 ; Child Loop BB0_626 Depth 4 ; Child Loop BB0_628 Depth 4 ; Child Loop BB0_630 Depth 4 ; Child Loop BB0_632 Depth 4 ; Child Loop BB0_634 Depth 4 s_delay_alu instid0(VALU_DEP_2) s_cmp_eq_u32 s29, 0 s_mov_b32 s5, -1 ;;#ASMSTART ;;#ASMEND s_cbranch_scc1 .LBB0_374 ; %bb.346: ; in Loop: Header=BB0_345 Depth=3 v_cmp_eq_u32_e64 s1, 0, v50 v_mov_b32_e32 v6, 0 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB0_348 ; %bb.347: ; in Loop: Header=BB0_345 Depth=3 global_load_b32 v6, v[19:20], off glc .LBB0_348: ; in Loop: Header=BB0_345 Depth=3 s_or_b32 exec_lo, exec_lo, s2 global_load_b32 v9, v[21:22], off v_cvt_f32_u32_e32 v7, s29 s_sub_i32 s2, 0, s29 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v7, v7 s_waitcnt_depctr 0xfff v_mul_f32_e32 v7, 0x4f7ffffe, v7 v_cvt_u32_f32_e32 v7, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mul_lo_u32 v8, s2, v7 s_waitcnt vmcnt(1) v_readfirstlane_b32 s2, v6 v_add_nc_u32_e32 v6, s2, v50 s_mov_b32 s2, s29 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v8, v7, v8 v_add_nc_u32_e32 v10, v7, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v7, v6, v10 v_mul_lo_u32 v7, v7, s29 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v6, v6, v7 v_subrev_nc_u32_e32 v7, s29, v6 v_cmp_le_u32_e32 vcc_lo, s29, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v6, v6, v7, vcc_lo v_subrev_nc_u32_e32 v7, s29, v6 v_cmp_le_u32_e32 vcc_lo, s29, v6 s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e32 v11, v6, v7, vcc_lo .LBB0_349: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_mov_b32 s3, exec_lo ; implicit-def: $vgpr6_vgpr7 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_u32_e32 0x100, v11 s_xor_b32 s3, exec_lo, s3 ; %bb.350: ; in Loop: Header=BB0_349 Depth=4 s_add_u32 s6, s10, 0x2800 s_addc_u32 s7, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[14:15], null, v2, 0x1800, s[6:7] v_mad_u64_u32 v[6:7], null, v11, 24, v[14:15] ; %bb.351: ; %Flow995 ; in Loop: Header=BB0_349 Depth=4 s_and_not1_saveexec_b32 s3, s3 s_cbranch_execz .LBB0_353 ; %bb.352: ; in Loop: Header=BB0_349 Depth=4 s_add_u32 s6, s10, 0x2800 v_add_nc_u32_e32 v8, 0xffffff00, v11 s_addc_u32 s7, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[6:7], null, v2, 0x1800, s[6:7] v_lshrrev_b32_e32 v8, 8, v8 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[14:15], null, v8, 24, v[6:7] v_and_b32_e32 v8, 0xff, v11 global_load_b64 v[14:15], v[14:15], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[6:7], null, v8, 24, v[14:15] .LBB0_353: ; in Loop: Header=BB0_349 Depth=4 s_or_b32 exec_lo, exec_lo, s3 global_load_b32 v6, v[6:7], off offset:16 glc s_waitcnt vmcnt(0) v_cmp_lt_u32_e32 vcc_lo, v6, v9 s_cbranch_vccz .LBB0_355 ; %bb.354: ; in Loop: Header=BB0_349 Depth=4 s_ctz_i32_b32 s3, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b32 s3, s3, 2 v_mov_b32_e32 v6, s3 ds_bpermute_b32 v6, v6, v11 s_branch .LBB0_356 .LBB0_355: ; in Loop: Header=BB0_349 Depth=4 v_mov_b32_e32 v6, -1 .LBB0_356: ; in Loop: Header=BB0_349 Depth=4 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s6, v6 s_cmp_eq_u32 s6, -1 s_cselect_b32 s3, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s3 s_cbranch_vccnz .LBB0_359 ; %bb.357: ; in Loop: Header=BB0_349 Depth=4 s_cmpk_lt_u32 s6, 0x100 s_cbranch_scc0 .LBB0_360 ; %bb.358: ; in Loop: Header=BB0_349 Depth=4 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_mov_b32 s7, 0 v_mad_u64_u32 v[14:15], null, v2, 0x1800, s[16:17] s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[7:8], null, s6, 24, v[14:15] s_branch .LBB0_361 .LBB0_359: ; in Loop: Header=BB0_349 Depth=4 s_mov_b32 s6, -1 ; implicit-def: $vgpr7_vgpr8 s_branch .LBB0_364 .LBB0_360: ; in Loop: Header=BB0_349 Depth=4 s_mov_b32 s7, -1 ; implicit-def: $vgpr7_vgpr8 .LBB0_361: ; %Flow988 ; in Loop: Header=BB0_349 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s7 s_cbranch_vccnz .LBB0_363 ; %bb.362: ; in Loop: Header=BB0_349 Depth=4 s_add_i32 s7, s6, 0xffffff00 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) s_lshr_b32 s7, s7, 8 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_and_b32 s6, s6, 0xff v_mad_u64_u32 v[6:7], null, v2, 0x1800, s[16:17] v_mad_u64_u32 v[14:15], null, s7, 24, v[6:7] global_load_b64 v[14:15], v[14:15], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[7:8], null, s6, 24, v[14:15] .LBB0_363: ; %Flow989 ; in Loop: Header=BB0_349 Depth=4 s_mov_b32 s6, 0 .LBB0_364: ; %Flow991 ; in Loop: Header=BB0_349 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_368 ; %bb.365: ; in Loop: Header=BB0_349 Depth=4 v_add_nc_u32_e32 v6, s30, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v7, v6, v10 v_mul_lo_u32 v7, v7, s29 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v6, v6, v7 v_subrev_nc_u32_e32 v7, s29, v6 v_cmp_le_u32_e32 vcc_lo, s29, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v6, v6, v7, vcc_lo v_subrev_nc_u32_e32 v7, s29, v6 v_cmp_le_u32_e32 vcc_lo, s29, v6 s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e32 v11, v6, v7, vcc_lo s_and_saveexec_b32 s6, s1 s_cbranch_execz .LBB0_367 ; %bb.366: ; in Loop: Header=BB0_349 Depth=4 global_store_b32 v[19:20], v11, off .LBB0_367: ; in Loop: Header=BB0_349 Depth=4 s_or_b32 exec_lo, exec_lo, s6 v_dual_mov_b32 v7, v12 :: v_dual_mov_b32 v8, v13 s_sub_i32 s2, s2, s30 .LBB0_368: ; in Loop: Header=BB0_349 Depth=4 s_and_not1_b32 vcc_lo, exec_lo, s3 s_cbranch_vccz .LBB0_370 ; %bb.369: ; in Loop: Header=BB0_349 Depth=4 s_mov_b32 s3, -1 s_mov_b32 s6, -1 ; implicit-def: $sgpr2 ; implicit-def: $vgpr11 s_branch .LBB0_371 .LBB0_370: ; in Loop: Header=BB0_349 Depth=4 s_cmp_lt_i32 s2, 1 s_mov_b32 s3, 0 s_cselect_b32 s6, -1, 0 .LBB0_371: ; %Flow997 ; in Loop: Header=BB0_349 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccz .LBB0_373 ; %bb.372: ; in Loop: Header=BB0_349 Depth=4 v_dual_mov_b32 v13, v8 :: v_dual_mov_b32 v12, v7 s_branch .LBB0_349 .LBB0_373: ; %loop.exit.guard769 ; in Loop: Header=BB0_345 Depth=3 v_dual_mov_b32 v13, v8 :: v_dual_mov_b32 v12, v7 s_xor_b32 s1, s3, -1 s_branch .LBB0_375 .LBB0_374: ; in Loop: Header=BB0_345 Depth=3 s_mov_b32 s1, -1 ; implicit-def: $vgpr7_vgpr8 .LBB0_375: ; %Flow1164 ; in Loop: Header=BB0_345 Depth=3 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s1 s_cbranch_vccz .LBB0_615 ; %bb.376: ; %.loopexit190 ; in Loop: Header=BB0_345 Depth=3 v_mbcnt_lo_u32_b32 v51, exec_lo, 0 ; implicit-def: $vgpr37_vgpr38 .LBB0_377: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; => This Loop Header: Depth=4 ; Child Loop BB0_395 Depth 5 ; Child Loop BB0_403 Depth 5 ; Child Loop BB0_409 Depth 5 ; Child Loop BB0_418 Depth 5 ; Child Loop BB0_423 Depth 5 ; Child Loop BB0_425 Depth 5 ; Child Loop BB0_445 Depth 5 ; Child Loop BB0_453 Depth 5 ; Child Loop BB0_459 Depth 5 ; Child Loop BB0_468 Depth 5 ; Child Loop BB0_476 Depth 5 ; Child Loop BB0_479 Depth 5 ; Child Loop BB0_481 Depth 5 ; Child Loop BB0_483 Depth 5 ; Child Loop BB0_485 Depth 5 ; Child Loop BB0_487 Depth 5 ; Child Loop BB0_489 Depth 5 ; Child Loop BB0_511 Depth 5 ; Child Loop BB0_519 Depth 5 ; Child Loop BB0_525 Depth 5 ; Child Loop BB0_534 Depth 5 ; Child Loop BB0_541 Depth 5 ; Child Loop BB0_544 Depth 5 ; Child Loop BB0_549 Depth 5 ; Child Loop BB0_556 Depth 5 ; Child Loop BB0_589 Depth 5 ; Child Loop BB0_597 Depth 5 ; Child Loop BB0_603 Depth 5 ; Child Loop BB0_612 Depth 5 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cmp_eq_u32_e64 s1, 0, v51 v_mov_b32_e32 v6, 0 s_mov_b32 s18, 0 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB0_379 ; %bb.378: ; in Loop: Header=BB0_377 Depth=4 global_load_b32 v6, v[17:18], off glc .LBB0_379: ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s2 s_waitcnt vmcnt(0) v_readfirstlane_b32 s31, v6 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_delay_alu instid0(VALU_DEP_3) s_cmp_eq_u32 s31, 0x10100 s_cbranch_scc1 .LBB0_499 ; %bb.380: ; in Loop: Header=BB0_377 Depth=4 v_mov_b32_e32 v6, 0 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB0_382 ; %bb.381: ; in Loop: Header=BB0_377 Depth=4 v_dual_mov_b32 v6, 0x100 :: v_dual_mov_b32 v7, 0 global_atomic_cmpswap_b32 v6, v[25:26], v[6:7], off glc s_waitcnt vmcnt(0) v_cmp_ne_u32_e32 vcc_lo, 0, v6 v_cndmask_b32_e32 v6, 0x100, v6, vcc_lo .LBB0_382: ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s34, v6 s_cmp_lg_u32 s31, s34 s_cbranch_scc1 .LBB0_439 ; %bb.383: ; in Loop: Header=BB0_377 Depth=4 v_mbcnt_lo_u32_b32 v52, exec_lo, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v52 v_mov_b32_e32 v6, 0 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_385 ; %bb.384: ; in Loop: Header=BB0_377 Depth=4 global_load_b32 v6, v[25:26], off glc .LBB0_385: ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s2 s_waitcnt vmcnt(0) v_readfirstlane_b32 s22, v6 s_mov_b32 s16, 2 s_delay_alu instid0(VALU_DEP_1) s_cmp_eq_u32 s22, 0x10100 s_cbranch_scc1 .LBB0_472 ; %bb.386: ; in Loop: Header=BB0_377 Depth=4 v_mov_b32_e32 v6, 1 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB0_390 ; %bb.387: ; in Loop: Header=BB0_377 Depth=4 global_load_b64 v[8:9], v[27:28], off glc s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v6, s2, s6, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_co_ci_u32_e64 v7, s2, s7, v9, s2 v_cmp_lt_u64_e64 s2, 0x752f, v[6:7] v_mov_b32_e32 v6, 1 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_389 ; %bb.388: ; in Loop: Header=BB0_377 Depth=4 v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 global_atomic_cmpswap_b64 v[6:7], v[27:28], v[6:9], off glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e64 s2, v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) v_cndmask_b32_e64 v6, 1, 2, s2 .LBB0_389: ; %Flow1153 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 .LBB0_390: ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s3 v_readfirstlane_b32 s3, v6 s_mov_b32 s16, 1 s_delay_alu instid0(VALU_DEP_1) s_cmp_eq_u32 s3, 1 s_cbranch_scc1 .LBB0_472 ; %bb.391: ; in Loop: Header=BB0_377 Depth=4 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_and_saveexec_b32 s23, vcc_lo s_cbranch_execz .LBB0_420 ; %bb.392: ; in Loop: Header=BB0_377 Depth=4 s_load_b64 s[16:17], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s2, v15 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 v_cmp_eq_u32_e64 s2, s2, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_398 ; %bb.393: ; in Loop: Header=BB0_377 Depth=4 s_waitcnt lgkmcnt(0) global_load_b64 v[8:9], v16, s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[6:7], v16, s[16:17] offset:40 global_load_b64 v[10:11], v16, s[16:17] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v7, v7, v9 v_and_b32_e32 v6, v6, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v7, v7, 24 v_mul_hi_u32 v14, v6, 24 v_mul_lo_u32 v6, v6, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, v14, v7 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v10, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, v11, v7, vcc_lo global_load_b64 v[6:7], v[6:7], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[10:11], v[8:9] s_cbranch_execz .LBB0_397 ; %bb.394: ; %.preheader3.i.i.i75.preheader ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s7, 0 .LBB0_395: ; %.preheader3.i.i.i75 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 s_clause 0x1 global_load_b64 v[6:7], v16, s[16:17] offset:40 global_load_b64 v[48:49], v16, s[16:17] v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v6, v6, v8 v_and_b32_e32 v7, v7, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[10:11], null, v6, 24, v[48:49] v_mov_b32_e32 v6, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[48:49], null, v7, 24, v[6:7] v_mov_b32_e32 v11, v48 global_load_b64 v[6:7], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[8:9] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_395 ; %bb.396: ; %Flow1147 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s7 .LBB0_397: ; %Flow1149 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB0_398: ; %.loopexit4.i.i.i70 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[48:49], v16, s[16:17] offset:40 global_load_b128 v[6:9], v16, s[16:17] v_readfirstlane_b32 s18, v10 v_readfirstlane_b32 s19, v11 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s20, v48 v_readfirstlane_b32 s21, v49 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[20:21], s[18:19], s[20:21] s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_400 ; %bb.399: ; in Loop: Header=BB0_377 Depth=4 v_dual_mov_b32 v64, s6 :: v_dual_mov_b32 v65, 0 s_mul_i32 s6, s21, 24 s_mul_hi_u32 s7, s20, 24 v_dual_mov_b32 v66, 3 :: v_dual_mov_b32 v67, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s20, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v7, vcc_lo global_store_b128 v[10:11], v[64:67], off offset:8 .LBB0_400: ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[20:21], 12 v_lshlrev_b64 v[10:11], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v14, vcc_lo, v8, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo s_mov_b32 s5, s4 s_mov_b32 s6, s4 s_mov_b32 s7, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v67, s7 v_add_co_u32 v48, vcc_lo, v14, v10 v_add_co_ci_u32_e32 v49, vcc_lo, v9, v11, vcc_lo v_dual_mov_b32 v10, 0x1800 :: v_dual_mov_b32 v9, v8 v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v66, s6 v_dual_mov_b32 v65, s5 :: v_dual_mov_b32 v64, s4 s_clause 0x3 global_store_b128 v[48:49], v[8:11], off global_store_b128 v[48:49], v[64:67], off offset:16 global_store_b128 v[48:49], v[64:67], off offset:32 global_store_b128 v[48:49], v[64:67], off offset:48 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_408 ; %bb.401: ; in Loop: Header=BB0_377 Depth=4 s_clause 0x1 global_load_b64 v[66:67], v16, s[16:17] offset:32 glc global_load_b64 v[8:9], v16, s[16:17] offset:40 v_dual_mov_b32 v64, s18 :: v_dual_mov_b32 v65, s19 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[18:19] s_mul_i32 s7, s7, 24 s_mul_hi_u32 vcc_lo, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s7, vcc_lo, s7 v_add_co_u32 v14, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v15, vcc_lo, s7, v7, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[14:15], v[66:67], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v16, v[64:67], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[10:11], v[66:67] s_cbranch_execz .LBB0_404 ; %bb.402: ; %.preheader1.i.i.i73.preheader ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s7, 0 .LBB0_403: ; %.preheader1.i.i.i73 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_dual_mov_b32 v8, s18 :: v_dual_mov_b32 v9, s19 s_sleep 1 global_store_b64 v[14:15], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[8:11], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11] v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_403 .LBB0_404: ; %Flow1145 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[8:9], v16, s[16:17] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v10, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB0_406 ; %bb.405: ; in Loop: Header=BB0_377 Depth=4 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[8:9], v[10:11], off offset:8 .LBB0_406: ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[10:11], v[8:9], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] s_cbranch_vccnz .LBB0_408 ; %bb.407: ; in Loop: Header=BB0_377 Depth=4 global_load_b32 v15, v[8:9], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[10:11], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_408: ; %Flow1146 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s21, 24 s_mul_hi_u32 s6, s20, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s20, 24 v_add_co_u32 v6, vcc_lo, v6, s5 v_add_co_ci_u32_e32 v7, vcc_lo, s6, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v6, 20 v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo .LBB0_409: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_mov_b32_e32 v8, 1 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_411 ; %bb.410: ; in Loop: Header=BB0_409 Depth=5 global_load_b32 v8, v[6:7], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v8, 1, v8 .LBB0_411: ; in Loop: Header=BB0_409 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v8 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB0_413 ; %bb.412: ; in Loop: Header=BB0_409 Depth=5 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB0_414 .LBB0_413: ; in Loop: Header=BB0_409 Depth=5 s_mov_b32 s5, -1 .LBB0_414: ; %Flow1140 ; in Loop: Header=BB0_409 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB0_409 ; %bb.415: ; in Loop: Header=BB0_377 Depth=4 global_load_b64 v[10:11], v[48:49], off s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_419 ; %bb.416: ; in Loop: Header=BB0_377 Depth=4 s_clause 0x2 global_load_b64 v[8:9], v16, s[16:17] offset:40 global_load_b64 v[48:49], v16, s[16:17] offset:24 glc global_load_b64 v[14:15], v16, s[16:17] s_waitcnt vmcnt(2) v_add_co_u32 v53, vcc_lo, v8, 1 v_add_co_ci_u32_e32 v54, vcc_lo, 0, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v53, s18 v_add_co_ci_u32_e32 v7, vcc_lo, s19, v54, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7] v_dual_cndmask_b32 v7, v7, v54 :: v_dual_cndmask_b32 v6, v6, v53 v_and_b32_e32 v9, v7, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v8, v6, v8 v_mul_hi_u32 v53, v8, 24 v_mul_lo_u32 v8, v8, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v14, vcc_lo, v14, v8 v_mov_b32_e32 v8, v48 v_mul_lo_u32 v9, v9, 24 v_add_nc_u32_e32 v9, v53, v9 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v15, vcc_lo, v15, v9, vcc_lo v_mov_b32_e32 v9, v49 global_store_b64 v[14:15], v[48:49], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[8:9], v[48:49] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_419 ; %bb.417: ; %.preheader.i.i.i72.preheader ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s2, 0 .LBB0_418: ; %.preheader.i.i.i72 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 global_store_b64 v[14:15], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[48:49], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[48:49], v[8:9] v_dual_mov_b32 v8, v48 :: v_dual_mov_b32 v9, v49 s_or_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB0_418 .LBB0_419: ; %Flow1138 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 .LBB0_420: ; %Flow1150 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s23 s_waitcnt vmcnt(0) v_readfirstlane_b32 s18, v10 v_readfirstlane_b32 s19, v11 s_cmp_eq_u64 s[18:19], 0 s_cbranch_scc1 .LBB0_471 ; %bb.421: ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s2, exec_lo s_mov_b32 s5, exec_lo v_mbcnt_lo_u32_b32 v8, s2, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_u32_e32 0x300, v8 s_cbranch_execz .LBB0_424 ; %bb.422: ; %.preheader185.preheader ; in Loop: Header=BB0_377 Depth=4 v_lshlrev_b32_e32 v6, 3, v8 s_bcnt1_i32_b32 s6, s2 s_mov_b32 s16, s4 s_lshl_b32 s7, s6, 3 s_mov_b32 s17, 0 v_add_co_u32 v6, s2, s18, v6 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v7, null, s19, 0, s2 .LBB0_423: ; %.preheader185 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, s6, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mov_b32_e32 v10, v9 v_cmp_lt_u32_e32 vcc_lo, 0x2ff, v8 global_store_b64 v[6:7], v[9:10], off v_add_co_u32 v6, s2, v6, s7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e64 v7, s2, s16, v7, s2 s_or_b32 s17, vcc_lo, s17 s_and_not1_b32 exec_lo, exec_lo, s17 s_cbranch_execnz .LBB0_423 .LBB0_424: ; %Flow1132 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 ; implicit-def: $sgpr5 .LBB0_425: ; %.loopexit186 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 ;;#ASMSTART ;;#ASMEND v_cmp_eq_u32_e32 vcc_lo, 0, v52 v_mov_b32_e32 v6, s22 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_427 ; %bb.426: ; in Loop: Header=BB0_425 Depth=5 global_load_b32 v6, v[25:26], off glc .LBB0_427: ; in Loop: Header=BB0_425 Depth=5 s_or_b32 exec_lo, exec_lo, s2 s_waitcnt vmcnt(0) v_readfirstlane_b32 s22, v6 s_and_not1_b32 s2, s5, exec_lo s_and_b32 s5, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 s5, s2, s5 s_cmp_lg_u32 s22, 0x10100 s_cbranch_scc0 .LBB0_434 ; %bb.428: ; in Loop: Header=BB0_425 Depth=5 v_mov_b32_e32 v6, s3 s_and_saveexec_b32 s6, vcc_lo s_cbranch_execz .LBB0_432 ; %bb.429: ; in Loop: Header=BB0_425 Depth=5 s_add_i32 s2, s22, 0xffffff00 v_mov_b32_e32 v8, 0 s_lshr_b32 s2, s2, 8 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, v2, 0x1800, s[16:17] v_mad_u64_u32 v[10:11], null, s2, 24, v[6:7] v_dual_mov_b32 v7, s19 :: v_dual_mov_b32 v6, s18 v_mov_b32_e32 v9, v8 global_atomic_cmpswap_b64 v[6:7], v[10:11], v[6:9], off glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e64 s2, 0, v[6:7] v_mov_b32_e32 v6, s3 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s7, s2 s_cbranch_execz .LBB0_431 ; %bb.430: ; in Loop: Header=BB0_425 Depth=5 s_waitcnt_vscnt null, 0x0 global_atomic_add_u32 v[25:26], v39, off v_mov_b32_e32 v6, 0 .LBB0_431: ; %Flow1125 ; in Loop: Header=BB0_425 Depth=5 s_or_b32 exec_lo, exec_lo, s7 .LBB0_432: ; in Loop: Header=BB0_425 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s6 v_readfirstlane_b32 s2, v6 s_delay_alu instid0(VALU_DEP_1) s_cmp_eq_u32 s2, 0 s_cbranch_scc1 .LBB0_435 ; %bb.433: ; in Loop: Header=BB0_425 Depth=5 s_mov_b32 s6, 0 s_and_not1_b32 vcc_lo, vcc_lo, exec_lo s_sleep 2 ; implicit-def: $sgpr3 s_branch .LBB0_436 .LBB0_434: ; in Loop: Header=BB0_425 Depth=5 s_mov_b32 s16, -1 s_mov_b32 s6, -1 ; implicit-def: $vgpr52 ; implicit-def: $sgpr22 ; implicit-def: $sgpr2 ; implicit-def: $sgpr7 s_branch .LBB0_437 .LBB0_435: ; in Loop: Header=BB0_425 Depth=5 s_mov_b32 s6, -1 ; implicit-def: $vgpr52 ; implicit-def: $sgpr22 ; implicit-def: $sgpr2 .LBB0_436: ; %Flow1129 ; in Loop: Header=BB0_425 Depth=5 s_and_not1_b32 s5, s5, exec_lo s_and_b32 s17, vcc_lo, exec_lo s_mov_b32 s7, 0 s_mov_b32 s16, 0 s_or_b32 s5, s5, s17 .LBB0_437: ; %Flow1128 ; in Loop: Header=BB0_425 Depth=5 s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_440 ; %bb.438: ; in Loop: Header=BB0_425 Depth=5 s_mov_b32 s3, s2 s_branch .LBB0_425 .LBB0_439: ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s5, -1 ; implicit-def: $sgpr18 s_branch .LBB0_492 .LBB0_440: ; %loop.exit.guard772 ; in Loop: Header=BB0_377 Depth=4 s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccz .LBB0_470 ; %bb.441: ; in Loop: Header=BB0_377 Depth=4 s_and_saveexec_b32 s35, s5 s_cbranch_execz .LBB0_469 ; %bb.442: ; in Loop: Header=BB0_377 Depth=4 s_load_b64 s[16:17], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s2, v15 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 v_cmp_eq_u32_e64 s2, s2, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_448 ; %bb.443: ; in Loop: Header=BB0_377 Depth=4 s_waitcnt lgkmcnt(0) global_load_b64 v[8:9], v16, s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[6:7], v16, s[16:17] offset:40 global_load_b64 v[10:11], v16, s[16:17] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v7, v7, v9 v_and_b32_e32 v6, v6, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v7, v7, 24 v_mul_hi_u32 v14, v6, 24 v_mul_lo_u32 v6, v6, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, v14, v7 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v10, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, v11, v7, vcc_lo global_load_b64 v[6:7], v[6:7], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[10:11], v[8:9] s_cbranch_execz .LBB0_447 ; %bb.444: ; %.preheader3.i.i.i82.preheader ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s7, 0 .LBB0_445: ; %.preheader3.i.i.i82 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 s_clause 0x1 global_load_b64 v[6:7], v16, s[16:17] offset:40 global_load_b64 v[48:49], v16, s[16:17] v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v6, v6, v8 v_and_b32_e32 v7, v7, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[10:11], null, v6, 24, v[48:49] v_mov_b32_e32 v6, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[48:49], null, v7, 24, v[6:7] v_mov_b32_e32 v11, v48 global_load_b64 v[6:7], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[8:9] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_445 ; %bb.446: ; %Flow1120 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s7 .LBB0_447: ; %Flow1122 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB0_448: ; %.loopexit4.i.i.i77 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[48:49], v16, s[16:17] offset:40 global_load_b128 v[6:9], v16, s[16:17] v_readfirstlane_b32 s20, v10 v_readfirstlane_b32 s21, v11 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s22, v48 v_readfirstlane_b32 s23, v49 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[22:23], s[20:21], s[22:23] s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_450 ; %bb.449: ; in Loop: Header=BB0_377 Depth=4 v_dual_mov_b32 v52, s6 :: v_dual_mov_b32 v53, 0 s_mul_i32 s6, s23, 24 s_mul_hi_u32 s7, s22, 24 v_dual_mov_b32 v54, 3 :: v_dual_mov_b32 v55, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s22, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v7, vcc_lo global_store_b128 v[10:11], v[52:55], off offset:8 .LBB0_450: ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[22:23], 12 v_lshlrev_b64 v[10:11], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v8, vcc_lo, v8, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo s_mov_b32 s7, s4 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v14, vcc_lo, v8, v10 s_mov_b32 s5, s4 s_mov_b32 s6, s4 v_dual_mov_b32 v48, 0 :: v_dual_mov_b32 v53, s19 v_add_co_ci_u32_e32 v15, vcc_lo, v9, v11, vcc_lo v_dual_mov_b32 v52, s18 :: v_dual_mov_b32 v11, s7 v_dual_mov_b32 v10, s6 :: v_dual_mov_b32 v9, s5 s_delay_alu instid0(VALU_DEP_4) v_dual_mov_b32 v8, s4 :: v_dual_mov_b32 v49, v48 s_clause 0x4 global_store_b64 v[14:15], v[52:53], off global_store_b128 v[14:15], v[8:11], off offset:8 global_store_b128 v[14:15], v[8:11], off offset:24 global_store_b128 v[14:15], v[8:11], off offset:40 global_store_b64 v[14:15], v[48:49], off offset:56 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_458 ; %bb.451: ; in Loop: Header=BB0_377 Depth=4 s_clause 0x1 global_load_b64 v[54:55], v16, s[16:17] offset:32 glc global_load_b64 v[8:9], v16, s[16:17] offset:40 v_dual_mov_b32 v52, s20 :: v_dual_mov_b32 v53, s21 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[20:21] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s18, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s18, s18, s7 v_add_co_u32 v14, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v15, vcc_lo, s18, v7, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[14:15], v[54:55], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v16, v[52:55], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[10:11], v[54:55] s_cbranch_execz .LBB0_454 ; %bb.452: ; %.preheader1.i.i.i80.preheader ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s7, 0 .LBB0_453: ; %.preheader1.i.i.i80 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 s_sleep 1 global_store_b64 v[14:15], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[8:11], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11] v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_453 .LBB0_454: ; %Flow1118 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[8:9], v16, s[16:17] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v10, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB0_456 ; %bb.455: ; in Loop: Header=BB0_377 Depth=4 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[8:9], v[10:11], off offset:8 .LBB0_456: ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[10:11], v[8:9], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] s_cbranch_vccnz .LBB0_458 ; %bb.457: ; in Loop: Header=BB0_377 Depth=4 global_load_b32 v15, v[8:9], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[10:11], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_458: ; %Flow1119 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s23, 24 s_mul_hi_u32 s6, s22, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s22, 24 v_add_co_u32 v6, vcc_lo, v6, s5 v_add_co_ci_u32_e32 v7, vcc_lo, s6, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v6, 20 v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo .LBB0_459: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_mov_b32_e32 v8, 1 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_461 ; %bb.460: ; in Loop: Header=BB0_459 Depth=5 global_load_b32 v8, v[6:7], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v8, 1, v8 .LBB0_461: ; in Loop: Header=BB0_459 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v8 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB0_463 ; %bb.462: ; in Loop: Header=BB0_459 Depth=5 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB0_464 .LBB0_463: ; in Loop: Header=BB0_459 Depth=5 s_mov_b32 s5, -1 .LBB0_464: ; %Flow1113 ; in Loop: Header=BB0_459 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB0_459 ; %bb.465: ; in Loop: Header=BB0_377 Depth=4 s_and_b32 exec_lo, exec_lo, s2 s_cbranch_execz .LBB0_469 ; %bb.466: ; in Loop: Header=BB0_377 Depth=4 s_clause 0x2 global_load_b64 v[8:9], v16, s[16:17] offset:40 global_load_b64 v[14:15], v16, s[16:17] offset:24 glc global_load_b64 v[10:11], v16, s[16:17] s_waitcnt vmcnt(2) v_add_co_u32 v48, vcc_lo, v8, 1 v_add_co_ci_u32_e32 v49, vcc_lo, 0, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v48, s20 v_add_co_ci_u32_e32 v7, vcc_lo, s21, v49, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7] v_dual_cndmask_b32 v7, v7, v49 :: v_dual_cndmask_b32 v6, v6, v48 v_and_b32_e32 v9, v7, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v8, v6, v8 v_mul_hi_u32 v48, v8, 24 v_mul_lo_u32 v8, v8, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v10, vcc_lo, v10, v8 v_mov_b32_e32 v8, v14 v_mul_lo_u32 v9, v9, 24 v_add_nc_u32_e32 v9, v48, v9 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v11, vcc_lo, v11, v9, vcc_lo v_mov_b32_e32 v9, v15 global_store_b64 v[10:11], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[8:9], v[14:15] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_469 ; %bb.467: ; %.preheader.i.i.i79.preheader ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s2, 0 .LBB0_468: ; %.preheader.i.i.i79 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 global_store_b64 v[10:11], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[8:9] v_dual_mov_b32 v8, v14 :: v_dual_mov_b32 v9, v15 s_or_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB0_468 .LBB0_469: ; %Flow1123 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s35 s_mov_b32 s7, s3 .LBB0_470: ; %Flow1124 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s3, s7 .LBB0_471: ; %Flow1134 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s16, s3 .LBB0_472: ; %__ockl_devmem_request.exit83 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_cmp_eq_u32 s16, 0 s_cselect_b32 s5, -1, 0 s_and_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB0_491 ; %bb.473: ; in Loop: Header=BB0_377 Depth=4 v_mbcnt_lo_u32_b32 v6, exec_lo, 0 s_mov_b32 s17, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v6 s_cbranch_execz .LBB0_490 ; %bb.474: ; in Loop: Header=BB0_377 Depth=4 global_load_b64 v[6:7], v[27:28], off glc s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v6, vcc_lo, s2, v6 v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_u64_e32 vcc_lo, 0x7530, v[6:7] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_490 ; %bb.475: ; in Loop: Header=BB0_377 Depth=4 v_sub_nc_u32_e32 v6, 0x7530, v6 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) v_readfirstlane_b32 s2, v6 s_delay_alu instid0(VALU_DEP_1) s_ashr_i32 s3, s2, 31 s_waitcnt lgkmcnt(0) s_add_u32 s2, s6, s2 s_addc_u32 s3, s7, s3 .LBB0_476: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x659 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccnz .LBB0_479 ; %bb.477: ; %.preheader11.i ; in Loop: Header=BB0_476 Depth=5 s_sleep 0x7f s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_branch .LBB0_476 .LBB0_478: ; %.preheader9.i ; in Loop: Header=BB0_479 Depth=5 s_sleep 63 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_479: ; %Flow1104 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x326 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccz .LBB0_478 ; %bb.480: ; %Flow1101 ; in Loop: Header=BB0_377 Depth=4 s_add_u32 s18, s6, 0x18c s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccnz .LBB0_483 .LBB0_481: ; %.preheader7.i ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 31 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x18c s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccnz .LBB0_481 s_branch .LBB0_483 .LBB0_482: ; %.preheader5.i ; in Loop: Header=BB0_483 Depth=5 s_sleep 15 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_483: ; %.loopexit8.i ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0xc0 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccz .LBB0_482 s_branch .LBB0_485 .LBB0_484: ; %.preheader3.i ; in Loop: Header=BB0_485 Depth=5 s_sleep 7 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_485: ; %Flow1095 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x59 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccz .LBB0_484 s_branch .LBB0_487 .LBB0_486: ; %.preheader1.i ; in Loop: Header=BB0_487 Depth=5 s_sleep 3 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_487: ; %Flow1092 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 38 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccz .LBB0_486 ; %bb.488: ; %Flow1089 ; in Loop: Header=BB0_377 Depth=4 v_cmp_le_u64_e64 s6, s[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_490 .LBB0_489: ; %.preheader.i ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) v_cmp_gt_u64_e64 s6, s[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_489 .LBB0_490: ; %__ockl_rtcwait_u32.exit ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s17 s_cmp_lg_u32 s16, 2 v_mov_b32_e32 v38, s4 s_cselect_b32 s2, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) v_cndmask_b32_e64 v37, 0, 1, s2 .LBB0_491: ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s18, 0 .LBB0_492: ; %Flow1156 ; in Loop: Header=BB0_377 Depth=4 s_and_b32 vcc_lo, exec_lo, s5 s_cbranch_vccz .LBB0_500 ; %bb.493: ; in Loop: Header=BB0_377 Depth=4 v_mov_b32_e32 v6, 1 v_mov_b32_e32 v7, 0 s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB0_497 ; %bb.494: ; in Loop: Header=BB0_377 Depth=4 global_load_b64 v[8:9], v[29:30], off glc s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v6, vcc_lo, s2, v8 v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v9, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_cmp_lt_u64_e32 vcc_lo, 0x4e1f, v[6:7] v_mov_b32_e32 v6, 1 v_mov_b32_e32 v7, 0 s_and_saveexec_b32 s6, vcc_lo s_cbranch_execz .LBB0_496 ; %bb.495: ; in Loop: Header=BB0_377 Depth=4 v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s3 global_atomic_cmpswap_b64 v[6:7], v[29:30], v[6:9], off glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[8:9] v_mov_b32_e32 v7, s4 v_cndmask_b32_e64 v6, 0, 1, vcc_lo .LBB0_496: ; %Flow1083 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 .LBB0_497: ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s5 v_readfirstlane_b32 s2, v6 v_readfirstlane_b32 s3, v7 s_mov_b32 s18, 0 s_delay_alu instid0(VALU_DEP_1) s_cmp_lg_u64 s[2:3], 0 s_cbranch_scc0 .LBB0_501 ; %bb.498: ; in Loop: Header=BB0_377 Depth=4 v_dual_mov_b32 v7, s3 :: v_dual_mov_b32 v6, s2 .LBB0_499: ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v38, v7 :: v_dual_mov_b32 v37, v6 .LBB0_500: ; %Flow1159 ; in Loop: Header=BB0_377 Depth=4 s_xor_b32 s1, s18, -1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s1 s_cbranch_vccnz .LBB0_377 s_branch .LBB0_616 .LBB0_501: ; in Loop: Header=BB0_377 Depth=4 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_and_saveexec_b32 s20, s1 s_cbranch_execz .LBB0_537 ; %bb.502: ; in Loop: Header=BB0_377 Depth=4 s_clause 0x1 global_load_b64 v[8:9], v16, s[12:13] glc global_load_b64 v[6:7], v16, s[14:15] s_waitcnt vmcnt(0) v_cmp_ge_u64_e32 vcc_lo, v[8:9], v[6:7] s_cbranch_vccnz .LBB0_506 ; %bb.503: ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s2, exec_lo s_mov_b32 s1, exec_lo v_mbcnt_lo_u32_b32 v14, s2, 0 ; implicit-def: $vgpr8_vgpr9 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v14 s_cbranch_execz .LBB0_505 ; %bb.504: ; in Loop: Header=BB0_377 Depth=4 s_bcnt1_i32_b32 s2, s2 v_mov_b32_e32 v9, 0 s_lshl_b32 s2, s2, 21 s_delay_alu instid0(SALU_CYCLE_1) v_mov_b32_e32 v8, s2 global_atomic_add_u64 v[8:9], v16, v[8:9], s[12:13] glc .LBB0_505: ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s1 s_waitcnt vmcnt(0) v_readfirstlane_b32 s3, v9 v_readfirstlane_b32 s2, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[10:11], null, v14, 0x200000, s[2:3] v_cmp_ge_u64_e64 s1, v[10:11], v[6:7] s_branch .LBB0_507 .LBB0_506: ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s1, -1 ; implicit-def: $vgpr10_vgpr11 .LBB0_507: ; %Flow1080 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s21, s1 s_cbranch_execz .LBB0_536 ; %bb.508: ; in Loop: Header=BB0_377 Depth=4 s_load_b64 s[2:3], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s1, v15 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 v_cmp_eq_u32_e64 s1, s1, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB0_514 ; %bb.509: ; in Loop: Header=BB0_377 Depth=4 s_waitcnt lgkmcnt(0) global_load_b64 v[8:9], v16, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[6:7], v16, s[2:3] offset:40 global_load_b64 v[10:11], v16, s[2:3] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v7, v7, v9 v_and_b32_e32 v6, v6, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v7, v7, 24 v_mul_hi_u32 v14, v6, 24 v_mul_lo_u32 v6, v6, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, v14, v7 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v10, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, v11, v7, vcc_lo global_load_b64 v[6:7], v[6:7], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[10:11], v[8:9] s_cbranch_execz .LBB0_513 ; %bb.510: ; %.preheader3.i.i.i89.preheader ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s7, 0 .LBB0_511: ; %.preheader3.i.i.i89 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 s_clause 0x1 global_load_b64 v[6:7], v16, s[2:3] offset:40 global_load_b64 v[48:49], v16, s[2:3] v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v6, v6, v8 v_and_b32_e32 v7, v7, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[10:11], null, v6, 24, v[48:49] v_mov_b32_e32 v6, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[48:49], null, v7, 24, v[6:7] v_mov_b32_e32 v11, v48 global_load_b64 v[6:7], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[8:9] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_511 ; %bb.512: ; %Flow1076 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s7 .LBB0_513: ; %Flow1078 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB0_514: ; %.loopexit4.i.i.i84 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[48:49], v16, s[2:3] offset:40 global_load_b128 v[6:9], v16, s[2:3] v_readfirstlane_b32 s16, v10 v_readfirstlane_b32 s17, v11 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s18, v48 v_readfirstlane_b32 s19, v49 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[18:19], s[16:17], s[18:19] s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB0_516 ; %bb.515: ; in Loop: Header=BB0_377 Depth=4 v_dual_mov_b32 v52, s6 :: v_dual_mov_b32 v53, 0 s_mul_i32 s6, s19, 24 s_mul_hi_u32 s7, s18, 24 v_dual_mov_b32 v54, 3 :: v_dual_mov_b32 v55, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s18, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v7, vcc_lo global_store_b128 v[10:11], v[52:55], off offset:8 .LBB0_516: ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[18:19], 12 v_lshlrev_b64 v[10:11], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v14, vcc_lo, v8, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo s_mov_b32 s5, s4 s_mov_b32 s6, s4 s_mov_b32 s7, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v55, s7 v_add_co_u32 v48, vcc_lo, v14, v10 v_add_co_ci_u32_e32 v49, vcc_lo, v9, v11, vcc_lo v_dual_mov_b32 v10, 0x200000 :: v_dual_mov_b32 v9, v8 v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v54, s6 v_dual_mov_b32 v53, s5 :: v_dual_mov_b32 v52, s4 s_clause 0x3 global_store_b128 v[48:49], v[8:11], off global_store_b128 v[48:49], v[52:55], off offset:16 global_store_b128 v[48:49], v[52:55], off offset:32 global_store_b128 v[48:49], v[52:55], off offset:48 s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB0_524 ; %bb.517: ; in Loop: Header=BB0_377 Depth=4 s_clause 0x1 global_load_b64 v[54:55], v16, s[2:3] offset:32 glc global_load_b64 v[8:9], v16, s[2:3] offset:40 v_dual_mov_b32 v52, s16 :: v_dual_mov_b32 v53, s17 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[16:17] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s22, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s22, s22, s7 v_add_co_u32 v14, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v15, vcc_lo, s22, v7, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[14:15], v[54:55], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v16, v[52:55], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[10:11], v[54:55] s_cbranch_execz .LBB0_520 ; %bb.518: ; %.preheader1.i.i.i87.preheader ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s7, 0 .LBB0_519: ; %.preheader1.i.i.i87 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, s17 s_sleep 1 global_store_b64 v[14:15], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[8:11], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11] v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_519 .LBB0_520: ; %Flow1074 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[8:9], v16, s[2:3] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v10, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB0_522 ; %bb.521: ; in Loop: Header=BB0_377 Depth=4 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[8:9], v[10:11], off offset:8 .LBB0_522: ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[10:11], v[8:9], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] s_cbranch_vccnz .LBB0_524 ; %bb.523: ; in Loop: Header=BB0_377 Depth=4 global_load_b32 v15, v[8:9], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[10:11], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_524: ; %Flow1075 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s19, 24 s_mul_hi_u32 s6, s18, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s18, 24 v_add_co_u32 v6, vcc_lo, v6, s5 v_add_co_ci_u32_e32 v7, vcc_lo, s6, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v6, 20 v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo .LBB0_525: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_mov_b32_e32 v8, 1 s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB0_527 ; %bb.526: ; in Loop: Header=BB0_525 Depth=5 global_load_b32 v8, v[6:7], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v8, 1, v8 .LBB0_527: ; in Loop: Header=BB0_525 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v8 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB0_529 ; %bb.528: ; in Loop: Header=BB0_525 Depth=5 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB0_530 .LBB0_529: ; in Loop: Header=BB0_525 Depth=5 s_mov_b32 s5, -1 .LBB0_530: ; %Flow1069 ; in Loop: Header=BB0_525 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB0_525 ; %bb.531: ; in Loop: Header=BB0_377 Depth=4 global_load_b64 v[10:11], v[48:49], off s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB0_535 ; %bb.532: ; in Loop: Header=BB0_377 Depth=4 s_clause 0x2 global_load_b64 v[8:9], v16, s[2:3] offset:40 global_load_b64 v[48:49], v16, s[2:3] offset:24 glc global_load_b64 v[14:15], v16, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v52, vcc_lo, v8, 1 v_add_co_ci_u32_e32 v53, vcc_lo, 0, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v52, s16 v_add_co_ci_u32_e32 v7, vcc_lo, s17, v53, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7] v_dual_cndmask_b32 v7, v7, v53 :: v_dual_cndmask_b32 v6, v6, v52 v_and_b32_e32 v9, v7, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v8, v6, v8 v_mul_hi_u32 v52, v8, 24 v_mul_lo_u32 v8, v8, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v14, vcc_lo, v14, v8 v_mov_b32_e32 v8, v48 v_mul_lo_u32 v9, v9, 24 v_add_nc_u32_e32 v9, v52, v9 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v15, vcc_lo, v15, v9, vcc_lo v_mov_b32_e32 v9, v49 global_store_b64 v[14:15], v[48:49], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[8:9], v[48:49] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_535 ; %bb.533: ; %.preheader.i.i.i86.preheader ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s1, 0 .LBB0_534: ; %.preheader.i.i.i86 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 global_store_b64 v[14:15], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[48:49], v16, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[48:49], v[8:9] v_dual_mov_b32 v8, v48 :: v_dual_mov_b32 v9, v49 s_or_b32 s1, vcc_lo, s1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB0_534 .LBB0_535: ; %Flow1067 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 .LBB0_536: ; %Flow1081 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s21 .LBB0_537: ; %__ockl_devmem_request.exit90 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s20 s_waitcnt vmcnt(0) v_readfirstlane_b32 s2, v10 v_readfirstlane_b32 s3, v11 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_delay_alu instid0(VALU_DEP_3) s_cmp_eq_u64 s[2:3], 0 s_cbranch_scc1 .LBB0_582 ; %bb.538: ; in Loop: Header=BB0_377 Depth=4 v_mbcnt_lo_u32_b32 v6, exec_lo, 0 ;;#ASMSTART ;;#ASMEND global_load_b32 v10, v[23:24], off s_bcnt1_i32_b32 s5, exec_lo s_add_u32 s6, s2, 16 s_addc_u32 s7, s3, 0 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v7, 31, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_lshrrev_b32_e32 v9, 5, v7 s_and_saveexec_b32 s1, s0 s_xor_b32 s16, exec_lo, s1 s_cbranch_execz .LBB0_546 ; %bb.539: ; in Loop: Header=BB0_377 Depth=4 global_load_b32 v11, v[31:32], off s_mov_b32 s17, exec_lo v_cmpx_lt_u32_e64 v6, v9 s_cbranch_execz .LBB0_542 ; %bb.540: ; %.preheader182.preheader ; in Loop: Header=BB0_377 Depth=4 v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v14, v6 s_add_u32 s1, s2, 16 s_addc_u32 s18, s3, 0 s_mov_b32 s19, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[6:7] s_mov_b32 s20, 0 v_add_co_u32 v7, vcc_lo, s1, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s18, v8, vcc_lo s_lshl_b32 s18, s5, 2 .LBB0_541: ; %.preheader182 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_add_nc_u32_e32 v14, s5, v14 global_store_b32 v[7:8], v16, off v_add_co_u32 v7, s1, v7, s18 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e64 v8, s1, s19, v8, s1 v_cmp_ge_u32_e32 vcc_lo, v14, v9 s_or_b32 s20, vcc_lo, s20 s_and_not1_b32 exec_lo, exec_lo, s20 s_cbranch_execnz .LBB0_541 .LBB0_542: ; %Flow1056 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s17 global_load_b32 v14, v[33:34], off s_mov_b32 s1, exec_lo s_waitcnt vmcnt(0) v_mad_u64_u32 v[7:8], null, v11, v6, v[14:15] s_delay_alu instid0(VALU_DEP_1) v_cmpx_lt_u32_e64 v7, v10 s_cbranch_execz .LBB0_545 ; %bb.543: ; %.preheader180.preheader ; in Loop: Header=BB0_377 Depth=4 v_mul_lo_u32 v8, v11, s5 s_mov_b32 s17, 0 .LBB0_544: ; %.preheader180 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_lshlrev_b32_e64 v11, v7, 1 v_lshrrev_b32_e32 v14, 3, v7 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, v7, v8 v_and_b32_e32 v14, 0x1ffffffc, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_ge_u32_e32 vcc_lo, v7, v10 global_store_b32 v14, v11, s[6:7] s_or_b32 s17, vcc_lo, s17 s_and_not1_b32 exec_lo, exec_lo, s17 s_cbranch_execnz .LBB0_544 .LBB0_545: ; %Flow1053 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s1 .LBB0_546: ; %Flow1061 ; in Loop: Header=BB0_377 Depth=4 s_and_not1_saveexec_b32 s16, s16 s_cbranch_execz .LBB0_551 ; %bb.547: ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s17, exec_lo v_cmpx_lt_u32_e64 v6, v9 s_cbranch_execz .LBB0_550 ; %bb.548: ; %.preheader178.preheader ; in Loop: Header=BB0_377 Depth=4 global_load_b32 v11, v[35:36], off v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v14, v6 s_add_u32 s1, s2, 16 s_addc_u32 s18, s3, 0 s_mov_b32 s19, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[6:7] s_mov_b32 s20, 0 v_add_co_u32 v7, vcc_lo, s1, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s18, v8, vcc_lo s_lshl_b32 s18, s5, 2 .LBB0_549: ; %.preheader178 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_add_nc_u32_e32 v14, s5, v14 s_waitcnt vmcnt(0) global_store_b32 v[7:8], v11, off v_add_co_u32 v7, s1, v7, s18 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e64 v8, s1, s19, v8, s1 v_cmp_ge_u32_e32 vcc_lo, v14, v9 s_or_b32 s20, vcc_lo, s20 s_and_not1_b32 exec_lo, exec_lo, s20 s_cbranch_execnz .LBB0_549 .LBB0_550: ; %Flow1059 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s17 .LBB0_551: ; %.loopexit179 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s16 s_mov_b32 s1, exec_lo v_cmpx_eq_u32_e32 0, v6 s_cbranch_execz .LBB0_555 ; %bb.552: ; in Loop: Header=BB0_377 Depth=4 v_and_b32_e32 v6, 31, v10 s_mov_b32 s5, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_ne_u32_e32 0, v6 s_cbranch_execz .LBB0_554 ; %bb.553: ; in Loop: Header=BB0_377 Depth=4 v_add_nc_u32_e32 v15, -1, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[15:16] v_add_co_u32 v7, vcc_lo, s6, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo global_load_b32 v9, v[7:8], off s_waitcnt vmcnt(0) v_lshl_or_b32 v6, -1, v6, v9 global_store_b32 v[7:8], v6, off .LBB0_554: ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 global_store_b128 v16, v[2:5], s[2:3] .LBB0_555: ; %Flow1050 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s1 ; implicit-def: $sgpr5 .LBB0_556: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 ;;#ASMSTART ;;#ASMEND v_cmp_eq_u32_e64 s1, 0, v51 v_mov_b32_e32 v6, s31 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s6, s1 s_cbranch_execz .LBB0_558 ; %bb.557: ; in Loop: Header=BB0_556 Depth=5 global_load_b32 v6, v[17:18], off glc .LBB0_558: ; in Loop: Header=BB0_556 Depth=5 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) v_readfirstlane_b32 s31, v6 s_and_not1_b32 s5, s5, exec_lo s_and_b32 s6, s1, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 s5, s5, s6 s_cmp_eq_u32 s31, 0x10100 s_cbranch_scc1 .LBB0_565 ; %bb.559: ; in Loop: Header=BB0_556 Depth=5 v_mov_b32_e32 v6, s34 s_and_saveexec_b32 s6, s1 s_cbranch_execz .LBB0_561 ; %bb.560: ; in Loop: Header=BB0_556 Depth=5 global_load_b32 v6, v[25:26], off glc .LBB0_561: ; in Loop: Header=BB0_556 Depth=5 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) v_readfirstlane_b32 s34, v6 s_delay_alu instid0(VALU_DEP_1) s_cmp_lg_u32 s31, s34 s_cbranch_scc0 .LBB0_566 ; %bb.562: ; in Loop: Header=BB0_556 Depth=5 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 s_and_saveexec_b32 s6, s1 s_cbranch_execz .LBB0_573 ; %bb.563: ; in Loop: Header=BB0_556 Depth=5 s_cmpk_lt_u32 s31, 0x100 s_cbranch_scc0 .LBB0_567 ; %bb.564: ; in Loop: Header=BB0_556 Depth=5 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_mov_b32 s7, 0 v_mad_u64_u32 v[8:9], null, v2, 0x1800, s[16:17] s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, s31, 24, v[8:9] s_branch .LBB0_568 .LBB0_565: ; in Loop: Header=BB0_556 Depth=5 s_mov_b64 s[16:17], 0 s_mov_b32 s1, -1 s_mov_b32 s18, 0 s_mov_b32 s19, -1 ; implicit-def: $sgpr31 ; implicit-def: $sgpr34 ; implicit-def: $sgpr6_sgpr7 s_branch .LBB0_578 .LBB0_566: ; in Loop: Header=BB0_556 Depth=5 s_mov_b32 s18, -1 s_mov_b32 s19, -1 ; implicit-def: $sgpr31 ; implicit-def: $sgpr34 ; implicit-def: $sgpr6_sgpr7 s_branch .LBB0_577 .LBB0_567: ; in Loop: Header=BB0_556 Depth=5 s_mov_b32 s7, -1 ; implicit-def: $vgpr6_vgpr7 .LBB0_568: ; %Flow1042 ; in Loop: Header=BB0_556 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s7 s_cbranch_vccnz .LBB0_570 ; %bb.569: ; in Loop: Header=BB0_556 Depth=5 s_add_i32 s7, s31, 0xffffff00 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_lshr_b32 s7, s7, 8 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 v_mad_u64_u32 v[6:7], null, v2, 0x1800, s[16:17] s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[8:9], null, s7, 24, v[6:7] s_and_b32 s7, s31, 0xff global_load_b64 v[8:9], v[8:9], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[6:7], null, s7, 24, v[8:9] .LBB0_570: ; in Loop: Header=BB0_556 Depth=5 v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, s3 v_mov_b32_e32 v14, s31 s_delay_alu instid0(VALU_DEP_2) v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v11, v10 global_store_b32 v16, v14, s[2:3] offset:4 global_atomic_cmpswap_b64 v[8:9], v[6:7], v[8:11], off offset:8 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9] v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 s_and_saveexec_b32 s7, vcc_lo s_cbranch_execz .LBB0_572 ; %bb.571: ; in Loop: Header=BB0_556 Depth=5 s_waitcnt_vscnt null, 0x0 global_atomic_add_u32 v[17:18], v98, off v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 .LBB0_572: ; %Flow1040 ; in Loop: Header=BB0_556 Depth=5 s_or_b32 exec_lo, exec_lo, s7 .LBB0_573: ; %Flow1043 ; in Loop: Header=BB0_556 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s6 v_readfirstlane_b32 s6, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s7, v9 s_cmp_lg_u64 s[6:7], 0 s_cbranch_scc0 .LBB0_575 ; %bb.574: ; in Loop: Header=BB0_556 Depth=5 s_mov_b32 s19, -1 ; implicit-def: $sgpr31 ; implicit-def: $sgpr34 s_branch .LBB0_576 .LBB0_575: ; in Loop: Header=BB0_556 Depth=5 s_mov_b32 s19, 0 s_and_not1_b32 s1, s1, exec_lo s_sleep 2 .LBB0_576: ; %Flow1048 ; in Loop: Header=BB0_556 Depth=5 s_mov_b32 s18, 0 .LBB0_577: ; %Flow1047 ; in Loop: Header=BB0_556 Depth=5 s_and_not1_b32 s5, s5, exec_lo s_and_b32 s16, s1, exec_lo s_mov_b32 s1, 0 s_or_b32 s5, s5, s16 ; implicit-def: $sgpr16_sgpr17 .LBB0_578: ; %Flow1046 ; in Loop: Header=BB0_556 Depth=5 s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccz .LBB0_556 ; %bb.579: ; %loop.exit.guard777 ; in Loop: Header=BB0_377 Depth=4 v_dual_mov_b32 v6, s16 :: v_dual_mov_b32 v7, s17 s_and_b32 vcc_lo, exec_lo, s1 s_cbranch_vccnz .LBB0_499 ; %bb.580: ; %loop.exit.guard778 ; in Loop: Header=BB0_377 Depth=4 s_xor_b32 s1, s18, -1 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s1 s_cbranch_vccz .LBB0_583 ; %bb.581: ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s18, 0 s_branch .LBB0_584 .LBB0_582: ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s18, 0 s_branch .LBB0_499 .LBB0_583: ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s18, -1 ; implicit-def: $sgpr6_sgpr7 .LBB0_584: ; %Flow1037 ; in Loop: Header=BB0_377 Depth=4 v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 s_and_not1_b32 vcc_lo, exec_lo, s18 s_cbranch_vccnz .LBB0_499 ; %bb.585: ; in Loop: Header=BB0_377 Depth=4 s_and_saveexec_b32 s22, s5 s_cbranch_execz .LBB0_614 ; %bb.586: ; in Loop: Header=BB0_377 Depth=4 s_load_b64 s[16:17], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s1, v15 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 v_cmp_eq_u32_e64 s1, s1, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB0_592 ; %bb.587: ; in Loop: Header=BB0_377 Depth=4 s_waitcnt lgkmcnt(0) global_load_b64 v[8:9], v16, s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[6:7], v16, s[16:17] offset:40 global_load_b64 v[10:11], v16, s[16:17] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v7, v7, v9 v_and_b32_e32 v6, v6, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v7, v7, 24 v_mul_hi_u32 v14, v6, 24 v_mul_lo_u32 v6, v6, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, v14, v7 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v10, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, v11, v7, vcc_lo global_load_b64 v[6:7], v[6:7], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[10:11], v[8:9] s_cbranch_execz .LBB0_591 ; %bb.588: ; %.preheader3.i.i.i96.preheader ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s7, 0 .LBB0_589: ; %.preheader3.i.i.i96 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 s_clause 0x1 global_load_b64 v[6:7], v16, s[16:17] offset:40 global_load_b64 v[48:49], v16, s[16:17] v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v6, v6, v8 v_and_b32_e32 v7, v7, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[10:11], null, v6, 24, v[48:49] v_mov_b32_e32 v6, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[48:49], null, v7, 24, v[6:7] v_mov_b32_e32 v11, v48 global_load_b64 v[6:7], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[8:9] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB0_589 ; %bb.590: ; %Flow1033 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s7 .LBB0_591: ; %Flow1035 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB0_592: ; %.loopexit4.i.i.i91 ; in Loop: Header=BB0_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[48:49], v16, s[16:17] offset:40 global_load_b128 v[6:9], v16, s[16:17] v_readfirstlane_b32 s18, v10 v_readfirstlane_b32 s19, v11 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s20, v48 v_readfirstlane_b32 s21, v49 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[20:21], s[18:19], s[20:21] s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB0_594 ; %bb.593: ; in Loop: Header=BB0_377 Depth=4 v_dual_mov_b32 v51, s6 :: v_dual_mov_b32 v52, 0 s_mul_i32 s6, s21, 24 s_mul_hi_u32 s7, s20, 24 v_dual_mov_b32 v53, 3 :: v_dual_mov_b32 v54, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s20, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v7, vcc_lo global_store_b128 v[10:11], v[51:54], off offset:8 .LBB0_594: ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[20:21], 12 v_lshlrev_b64 v[10:11], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v8, vcc_lo, v8, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo s_mov_b32 s7, s4 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v14, vcc_lo, v8, v10 s_mov_b32 s5, s4 s_mov_b32 s6, s4 v_mov_b32_e32 v48, 0 v_mov_b32_e32 v52, s3 v_add_co_ci_u32_e32 v15, vcc_lo, v9, v11, vcc_lo v_mov_b32_e32 v11, s7 v_dual_mov_b32 v51, s2 :: v_dual_mov_b32 v10, s6 v_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4 v_mov_b32_e32 v49, v48 s_clause 0x4 global_store_b64 v[14:15], v[51:52], off global_store_b128 v[14:15], v[8:11], off offset:8 global_store_b128 v[14:15], v[8:11], off offset:24 global_store_b128 v[14:15], v[8:11], off offset:40 global_store_b64 v[14:15], v[48:49], off offset:56 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB0_602 ; %bb.595: ; in Loop: Header=BB0_377 Depth=4 s_clause 0x1 global_load_b64 v[53:54], v16, s[16:17] offset:32 glc global_load_b64 v[8:9], v16, s[16:17] offset:40 v_dual_mov_b32 v51, s18 :: v_dual_mov_b32 v52, s19 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[18:19] s_mul_i32 s3, s7, 24 s_mul_hi_u32 s5, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s5, s5, s3 v_add_co_u32 v14, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v15, vcc_lo, s5, v7, vcc_lo s_mov_b32 s3, exec_lo global_store_b64 v[14:15], v[53:54], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v16, v[51:54], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[10:11], v[53:54] s_cbranch_execz .LBB0_598 ; %bb.596: ; %.preheader1.i.i.i94.preheader ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s5, 0 .LBB0_597: ; %.preheader1.i.i.i94 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_dual_mov_b32 v8, s18 :: v_dual_mov_b32 v9, s19 s_sleep 1 global_store_b64 v[14:15], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[8:11], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11] v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8 s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_597 .LBB0_598: ; %Flow1031 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s3 global_load_b64 v[8:9], v16, s[16:17] offset:16 s_mov_b32 s5, exec_lo s_mov_b32 s3, exec_lo v_mbcnt_lo_u32_b32 v10, s5, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB0_600 ; %bb.599: ; in Loop: Header=BB0_377 Depth=4 s_bcnt1_i32_b32 s5, s5 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, s5 s_waitcnt vmcnt(0) global_atomic_add_u64 v[8:9], v[10:11], off offset:8 .LBB0_600: ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) global_load_b64 v[10:11], v[8:9], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] s_cbranch_vccnz .LBB0_602 ; %bb.601: ; in Loop: Header=BB0_377 Depth=4 global_load_b32 v15, v[8:9], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s3, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[10:11], v[15:16], off s_and_b32 m0, s3, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_602: ; %Flow1032 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s2 s_mul_i32 s2, s21, 24 s_mul_hi_u32 s3, s20, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s3, s3, s2 s_mul_i32 s2, s20, 24 v_add_co_u32 v6, vcc_lo, v6, s2 v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v6, 20 v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo .LBB0_603: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_mov_b32_e32 v8, 1 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB0_605 ; %bb.604: ; in Loop: Header=BB0_603 Depth=5 global_load_b32 v8, v[6:7], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v8, 1, v8 .LBB0_605: ; in Loop: Header=BB0_603 Depth=5 s_or_b32 exec_lo, exec_lo, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s2, v8 s_cmp_eq_u32 s2, 0 s_cbranch_scc1 .LBB0_607 ; %bb.606: ; in Loop: Header=BB0_603 Depth=5 s_mov_b32 s2, 0 s_sleep 1 s_branch .LBB0_608 .LBB0_607: ; in Loop: Header=BB0_603 Depth=5 s_mov_b32 s2, -1 .LBB0_608: ; %Flow1026 ; in Loop: Header=BB0_603 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s2 s_cbranch_vccnz .LBB0_603 ; %bb.609: ; in Loop: Header=BB0_377 Depth=4 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB0_613 ; %bb.610: ; in Loop: Header=BB0_377 Depth=4 s_clause 0x2 global_load_b64 v[8:9], v16, s[16:17] offset:40 global_load_b64 v[14:15], v16, s[16:17] offset:24 glc global_load_b64 v[10:11], v16, s[16:17] s_waitcnt vmcnt(2) v_add_co_u32 v48, vcc_lo, v8, 1 v_add_co_ci_u32_e32 v49, vcc_lo, 0, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v48, s18 v_add_co_ci_u32_e32 v7, vcc_lo, s19, v49, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7] v_dual_cndmask_b32 v7, v7, v49 :: v_dual_cndmask_b32 v6, v6, v48 v_and_b32_e32 v9, v7, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v8, v6, v8 v_mul_hi_u32 v48, v8, 24 v_mul_lo_u32 v8, v8, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v10, vcc_lo, v10, v8 v_mov_b32_e32 v8, v14 v_mul_lo_u32 v9, v9, 24 v_add_nc_u32_e32 v9, v48, v9 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v11, vcc_lo, v11, v9, vcc_lo v_mov_b32_e32 v9, v15 global_store_b64 v[10:11], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[8:9], v[14:15] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_613 ; %bb.611: ; %.preheader.i.i.i93.preheader ; in Loop: Header=BB0_377 Depth=4 s_mov_b32 s1, 0 .LBB0_612: ; %.preheader.i.i.i93 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; Parent Loop BB0_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 global_store_b64 v[10:11], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[8:9] v_dual_mov_b32 v8, v14 :: v_dual_mov_b32 v9, v15 s_or_b32 s1, vcc_lo, s1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB0_612 .LBB0_613: ; %Flow1024 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s2 v_mov_b32_e32 v51, 0 .LBB0_614: ; %Flow1036 ; in Loop: Header=BB0_377 Depth=4 s_or_b32 exec_lo, exec_lo, s22 v_dual_mov_b32 v6, v37 :: v_dual_mov_b32 v7, v38 s_mov_b32 s18, -1 s_branch .LBB0_499 .LBB0_615: ; in Loop: Header=BB0_345 Depth=3 ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $sgpr29 ; implicit-def: $vgpr50 s_branch .LBB0_639 .LBB0_616: ; in Loop: Header=BB0_345 Depth=3 v_cmp_ne_u64_e64 s5, 1, v[37:38] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s5 s_cbranch_vccz .LBB0_618 ; %bb.617: ; in Loop: Header=BB0_345 Depth=3 v_dual_mov_b32 v12, v37 :: v_dual_mov_b32 v13, v38 s_branch .LBB0_638 .LBB0_618: ; in Loop: Header=BB0_345 Depth=3 v_mbcnt_lo_u32_b32 v6, exec_lo, 0 s_mov_b32 s1, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v6 s_cbranch_execz .LBB0_635 ; %bb.619: ; in Loop: Header=BB0_345 Depth=3 global_load_b64 v[6:7], v[29:30], off glc s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v6, vcc_lo, s2, v6 v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_u64_e32 vcc_lo, 0x4e20, v[6:7] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_635 ; %bb.620: ; in Loop: Header=BB0_345 Depth=3 v_sub_nc_u32_e32 v6, 0x4e20, v6 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) v_readfirstlane_b32 s2, v6 s_delay_alu instid0(VALU_DEP_1) s_ashr_i32 s3, s2, 31 s_waitcnt lgkmcnt(0) s_add_u32 s2, s6, s2 s_addc_u32 s3, s7, s3 .LBB0_621: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_waitcnt lgkmcnt(0) s_add_u32 s16, s6, 0x659 s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB0_624 ; %bb.622: ; %.preheader11.i110 ; in Loop: Header=BB0_621 Depth=4 s_sleep 0x7f s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_branch .LBB0_621 .LBB0_623: ; %.preheader9.i109 ; in Loop: Header=BB0_624 Depth=4 s_sleep 63 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_624: ; %Flow1018 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_waitcnt lgkmcnt(0) s_add_u32 s16, s6, 0x326 s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccz .LBB0_623 ; %bb.625: ; %Flow1015 ; in Loop: Header=BB0_345 Depth=3 s_add_u32 s16, s6, 0x18c s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB0_628 .LBB0_626: ; %.preheader7.i108 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_sleep 31 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) s_add_u32 s16, s6, 0x18c s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB0_626 s_branch .LBB0_628 .LBB0_627: ; %.preheader5.i107 ; in Loop: Header=BB0_628 Depth=4 s_sleep 15 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_628: ; %.loopexit8.i100 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_waitcnt lgkmcnt(0) s_add_u32 s16, s6, 0xc0 s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccz .LBB0_627 s_branch .LBB0_630 .LBB0_629: ; %.preheader3.i106 ; in Loop: Header=BB0_630 Depth=4 s_sleep 7 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_630: ; %Flow1009 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_waitcnt lgkmcnt(0) s_add_u32 s16, s6, 0x59 s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccz .LBB0_629 s_branch .LBB0_632 .LBB0_631: ; %.preheader1.i105 ; in Loop: Header=BB0_632 Depth=4 s_sleep 3 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB0_632: ; %Flow1006 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_waitcnt lgkmcnt(0) s_add_u32 s16, s6, 38 s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccz .LBB0_631 ; %bb.633: ; %Flow1003 ; in Loop: Header=BB0_345 Depth=3 v_cmp_le_u64_e64 s6, s[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_635 .LBB0_634: ; %.preheader.i104 ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; Parent Loop BB0_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_sleep 1 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) v_cmp_gt_u64_e64 s6, s[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_634 .LBB0_635: ; %__ockl_rtcwait_u32.exit111 ; in Loop: Header=BB0_345 Depth=3 s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v6, s29 s_mov_b32 s1, exec_lo v_cmpx_eq_u32_e32 0, v50 s_cbranch_execz .LBB0_637 ; %bb.636: ; in Loop: Header=BB0_345 Depth=3 global_load_b32 v6, v[17:18], off glc .LBB0_637: ; in Loop: Header=BB0_345 Depth=3 s_or_b32 exec_lo, exec_lo, s1 s_waitcnt vmcnt(0) v_readfirstlane_b32 s29, v6 .LBB0_638: ; %Flow1020 ; in Loop: Header=BB0_345 Depth=3 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v7, v12 :: v_dual_mov_b32 v8, v13 .LBB0_639: ; %Flow1165 ; in Loop: Header=BB0_345 Depth=3 s_and_b32 vcc_lo, exec_lo, s5 s_cbranch_vccz .LBB0_345 .LBB0_640: ; %.loopexit189 ; in Loop: Header=BB0_6 Depth=2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_readfirstlane_b32 s6, v7 v_readfirstlane_b32 s7, v8 v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0 s_delay_alu instid0(VALU_DEP_2) s_cmp_eq_u64 s[6:7], 0 s_cbranch_scc1 .LBB0_661 ; %bb.641: ; in Loop: Header=BB0_6 Depth=2 s_mov_b32 s5, exec_lo s_delay_alu instid0(SALU_CYCLE_1) v_mbcnt_lo_u32_b32 v8, s5, 0 ;;#ASMSTART ;;#ASMEND global_load_b64 v[0:1], v16, s[6:7] offset:8 glc v_cmp_eq_u32_e32 vcc_lo, 0, v8 s_waitcnt vmcnt(0) global_load_b32 v6, v[0:1], off s_waitcnt vmcnt(0) v_readfirstlane_b32 s2, v6 v_mov_b32_e32 v6, 0 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB0_645 ; %bb.642: ; in Loop: Header=BB0_6 Depth=2 s_mov_b32 s17, exec_lo s_bcnt1_i32_b32 s5, s5 v_mbcnt_lo_u32_b32 v6, s17, 0 s_mov_b32 s16, exec_lo ; implicit-def: $vgpr7 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v6 s_cbranch_execz .LBB0_644 ; %bb.643: ; in Loop: Header=BB0_6 Depth=2 s_bcnt1_i32_b32 s1, s17 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s1, s5, s1 v_mov_b32_e32 v7, s1 global_atomic_add_u32 v7, v[0:1], v7, off offset:8 glc .LBB0_644: ; in Loop: Header=BB0_6 Depth=2 s_or_b32 exec_lo, exec_lo, s16 s_waitcnt vmcnt(0) v_readfirstlane_b32 s1, v7 s_delay_alu instid0(VALU_DEP_1) v_mad_u32_u24 v6, s5, v6, s1 .LBB0_645: ; %Flow791 ; in Loop: Header=BB0_6 Depth=2 s_or_b32 exec_lo, exec_lo, s3 s_mov_b32 s3, s4 s_getpc_b64 s[18:19] s_add_u32 s18, s18, __unnamed_1@rel32@lo+4 s_addc_u32 s19, s19, __unnamed_1@rel32@hi+12 s_lshl_b64 s[16:17], s[2:3], 5 v_readfirstlane_b32 s1, v6 s_add_u32 s18, s16, s18 s_addc_u32 s19, s17, s19 v_mov_b32_e32 v6, 0 s_load_b32 s5, s[18:19], 0x0 v_mov_b32_e32 v7, 0 s_waitcnt lgkmcnt(0) s_add_i32 s3, s5, 31 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lt_u32 s3, 32 s_cbranch_scc1 .LBB0_655 ; %bb.646: ; in Loop: Header=BB0_6 Depth=2 v_cvt_f32_u32_e32 v6, s5 s_getpc_b64 s[18:19] s_add_u32 s18, s18, __unnamed_1@rel32@lo+32 s_addc_u32 s19, s19, __unnamed_1@rel32@hi+40 s_lshr_b32 s3, s3, 5 s_add_u32 s18, s16, s18 s_addc_u32 s19, s17, s19 v_rcp_iflag_f32_e32 v6, v6 s_load_b32 s18, s[18:19], 0x0 s_sub_i32 s19, 0, s5 v_add_nc_u32_e32 v8, s1, v8 s_waitcnt_depctr 0xfff v_mul_f32_e32 v6, 0x4f7ffffe, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v6, v6 v_mul_lo_u32 v7, s19, v6 s_waitcnt lgkmcnt(0) v_mul_lo_u32 v8, s18, v8 s_getpc_b64 s[18:19] s_add_u32 s18, s18, __unnamed_1@rel32@lo+16 s_addc_u32 s19, s19, __unnamed_1@rel32@hi+24 s_add_u32 s16, s16, s18 s_addc_u32 s17, s17, s19 s_lshr_b32 s18, s2, 1 s_bfe_i32 s2, s2, 0x10000 s_add_i32 s18, s18, 4 v_mul_hi_u32 v7, v6, v7 s_add_i32 s19, s3, -1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v6, v6, v7 v_mul_hi_u32 v6, v8, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v6, v6, s5 v_sub_nc_u32_e32 v6, v8, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_subrev_nc_u32_e32 v7, s5, v6 v_cmp_le_u32_e64 s1, s5, v6 v_cndmask_b32_e64 v6, v6, v7, s1 v_add_co_u32 v10, s1, v0, 16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v11, s1, 0, v1, s1 v_subrev_nc_u32_e32 v7, s5, v6 v_cmp_le_u32_e64 s1, s5, v6 s_delay_alu instid0(VALU_DEP_1) v_cndmask_b32_e64 v8, v6, v7, s1 s_lshl_b32 s1, 1, s18 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_lshr_b32 s5, s1, 1 v_lshrrev_b32_e32 v15, 5, v8 s_and_b32 s18, s2, s5 s_mov_b32 s5, 0 s_add_i32 s18, s18, s1 .LBB0_647: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; => This Inner Loop Header: Depth=3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], 2, v[15:16] s_mov_b32 s21, -1 s_mov_b32 s20, exec_lo ; implicit-def: $vgpr12 v_add_co_u32 v8, s1, v10, v8 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v9, s1, v11, v9, s1 global_load_b32 v13, v[8:9], off glc s_waitcnt vmcnt(0) v_cmpx_ne_u32_e32 -1, v13 s_cbranch_execz .LBB0_651 ; %bb.648: ; in Loop: Header=BB0_647 Depth=3 v_not_b32_e32 v12, v13 s_mov_b32 s21, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ctz_i32_b32_e32 v12, v12 v_min_u32_e32 v13, 32, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_lshlrev_b32_e64 v12, v13, 1 global_atomic_or_b32 v8, v[8:9], v12, off glc s_waitcnt vmcnt(0) v_and_b32_e32 v8, v8, v12 v_mov_b32_e32 v12, 0 v_cmp_ne_u32_e64 s1, 0, v8 v_cmpx_eq_u32_e32 0, v8 s_cbranch_execz .LBB0_650 ; %bb.649: ; in Loop: Header=BB0_647 Depth=3 s_load_b32 s2, s[16:17], 0x0 v_lshl_add_u32 v6, v15, 5, v13 v_mov_b32_e32 v12, 2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mul_lo_u32 v6, v6, s18 s_waitcnt lgkmcnt(0) v_add_co_u32 v7, s2, v0, s2 v_add_co_ci_u32_e64 v8, s2, 0, v1, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v6, s2, v7, v6 v_add_co_ci_u32_e64 v7, s2, 0, v8, s2 .LBB0_650: ; in Loop: Header=BB0_647 Depth=3 s_or_b32 exec_lo, exec_lo, s21 s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) s_or_not1_b32 s21, s1, exec_lo .LBB0_651: ; %Flow788 ; in Loop: Header=BB0_647 Depth=3 s_or_b32 exec_lo, exec_lo, s20 s_and_saveexec_b32 s2, s21 s_cbranch_execz .LBB0_653 ; %bb.652: ; in Loop: Header=BB0_647 Depth=3 v_cvt_f32_u32_e32 v8, s3 s_sub_i32 s1, 0, s3 v_add_nc_u32_e32 v12, 1, v15 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v8, v8 s_waitcnt_depctr 0xfff v_mul_f32_e32 v8, 0x4f7ffffe, v8 v_cvt_u32_f32_e32 v8, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v9, s1, v8 v_mul_hi_u32 v9, v8, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v8, v8, v9 v_mul_hi_u32 v8, v12, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v8, v8, s3 v_sub_nc_u32_e32 v8, v12, v8 v_mov_b32_e32 v12, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_subrev_nc_u32_e32 v9, s3, v8 v_cmp_le_u32_e64 s1, s3, v8 v_cndmask_b32_e64 v8, v8, v9, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_subrev_nc_u32_e32 v9, s3, v8 v_cmp_le_u32_e64 s1, s3, v8 v_cndmask_b32_e64 v15, v8, v9, s1 .LBB0_653: ; in Loop: Header=BB0_647 Depth=3 s_or_b32 exec_lo, exec_lo, s2 v_cmp_ne_u32_e64 s1, 0, v12 s_cmp_eq_u32 s19, 0 s_cselect_b32 s2, -1, 0 s_add_i32 s19, s19, -1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s1, s1, s2 s_and_b32 s1, exec_lo, s1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s5, s1, s5 s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_647 ; %bb.654: ; %Flow789 ; in Loop: Header=BB0_6 Depth=2 s_or_b32 exec_lo, exec_lo, s5 .LBB0_655: ; %.loopexit193 ; in Loop: Header=BB0_6 Depth=2 v_cmp_ne_u64_e64 s1, 0, v[6:7] s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_658 ; %bb.656: ; in Loop: Header=BB0_6 Depth=2 s_mov_b32 s3, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mbcnt_lo_u32_b32 v0, s3, 0 v_cmp_eq_u32_e32 vcc_lo, 0, v0 s_and_b32 s5, exec_lo, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 exec_lo, s5 s_cbranch_execz .LBB0_658 ; %bb.657: ; in Loop: Header=BB0_6 Depth=2 s_bcnt1_i32_b32 s1, s1 s_bcnt1_i32_b32 s3, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s1, s1, s3 v_mov_b32_e32 v0, s1 global_atomic_add_u32 v16, v0, s[6:7] offset:16 .LBB0_658: ; in Loop: Header=BB0_6 Depth=2 s_or_b32 exec_lo, exec_lo, s2 v_mov_b32_e32 v0, 0 v_mov_b32_e32 v1, 0 s_mov_b32 s1, exec_lo v_cmpx_ne_u64_e32 0, v[6:7] ; %bb.659: ; in Loop: Header=BB0_6 Depth=2 v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v99, 0 v_dual_mov_b32 v100, 0 :: v_dual_mov_b32 v1, v7 ; %bb.660: ; %Flow ; in Loop: Header=BB0_6 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v6, v100 :: v_dual_mov_b32 v7, v99 .LBB0_661: ; %Flow792 ; in Loop: Header=BB0_6 Depth=2 s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v99, v7 .LBB0_662: ; %Flow1171 ; in Loop: Header=BB0_6 Depth=2 s_or_b32 exec_lo, exec_lo, s28 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mov_b32_e32 v7, v6 ;;#ASMSTART ;;#ASMEND v_cmp_ne_u32_e32 vcc_lo, 0, v7 s_cbranch_vccnz .LBB0_6 .LBB0_663: ; %Flow1173 ; in Loop: Header=BB0_3 Depth=1 s_or_b32 exec_lo, exec_lo, s27 v_mov_b32_e32 v6, v99 .LBB0_664: ; %.loopexit197 ; in Loop: Header=BB0_3 Depth=1 s_or_b32 exec_lo, exec_lo, s26 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mov_b32_e32 v7, v6 ;;#ASMSTART ;;#ASMEND v_cmp_ne_u32_e32 vcc_lo, 0, v7 s_cbranch_vccnz .LBB0_3 ; %bb.665: ; %Flow1175 ; implicit-def: $vgpr2_vgpr3 .LBB0_666: ; %Flow1194 s_and_not1_saveexec_b32 s1, s25 s_cbranch_execz .LBB0_699 ; %bb.667: s_load_b64 s[2:3], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v0, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s0, v0 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 v_cmp_eq_u32_e64 s0, s0, v0 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s4, s0 s_cbranch_execz .LBB0_673 ; %bb.668: v_mov_b32_e32 v1, 0 s_mov_b32 s5, exec_lo s_waitcnt lgkmcnt(0) global_load_b64 v[6:7], v1, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[4:5], v1, s[2:3] offset:40 global_load_b64 v[8:9], v1, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v4, v4, v6 v_and_b32_e32 v5, v5, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v10, v4, 24 v_mul_lo_u32 v5, v5, 24 v_mul_lo_u32 v4, v4, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v5, v10, v5 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v8, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo global_load_b64 v[4:5], v[4:5], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[8:9], v1, v[4:7], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[8:9], v[6:7] s_cbranch_execz .LBB0_672 ; %bb.669: ; %.preheader3.i.i.i.preheader s_mov_b32 s6, 0 .LBB0_670: ; %.preheader3.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[4:5], v1, s[2:3] offset:40 global_load_b64 v[10:11], v1, s[2:3] v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v4, v4, v6 v_and_b32_e32 v5, v5, v7 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11] v_mov_b32_e32 v4, v9 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5] global_load_b64 v[4:5], v[8:9], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[8:9], v1, v[4:7], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7] s_or_b32 s6, vcc_lo, s6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s6 s_cbranch_execnz .LBB0_670 ; %bb.671: ; %Flow1190 s_or_b32 exec_lo, exec_lo, s6 .LBB0_672: ; %Flow1192 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 .LBB0_673: ; %.loopexit4.i.i.i s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 v_mov_b32_e32 v1, 0 v_readfirstlane_b32 s4, v8 v_readfirstlane_b32 s5, v9 s_mov_b32 s11, exec_lo s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[10:11], v1, s[2:3] offset:40 global_load_b128 v[4:7], v1, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v10 v_readfirstlane_b32 s7, v11 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s10, s0 s_cbranch_execz .LBB0_675 ; %bb.674: v_dual_mov_b32 v8, s11 :: v_dual_mov_b32 v9, 0 s_mul_i32 s11, s7, 24 s_mul_hi_u32 s12, s6, 24 v_dual_mov_b32 v10, 3 :: v_dual_mov_b32 v11, 1 s_add_i32 s12, s12, s11 s_mul_i32 s11, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v12, vcc_lo, v4, s11 v_add_co_ci_u32_e32 v13, vcc_lo, s12, v5, vcc_lo global_store_b128 v[12:13], v[8:11], off offset:8 .LBB0_675: s_or_b32 exec_lo, exec_lo, s10 s_lshl_b64 s[10:11], s[6:7], 12 v_lshlrev_b64 v[8:9], 6, v[0:1] s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v6, s10 s_mov_b32 s12, 0 v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo s_mov_b32 s13, s12 s_mov_b32 s14, s12 s_mov_b32 s15, s12 v_mov_b32_e32 v0, 0 v_add_co_u32 v6, vcc_lo, v1, v8 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15 v_mov_b32_e32 v9, s13 v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v10, s14 s_clause 0x3 global_store_b128 v[6:7], v[0:3], off global_store_b128 v[6:7], v[8:11], off offset:16 global_store_b128 v[6:7], v[8:11], off offset:32 global_store_b128 v[6:7], v[8:11], off offset:48 s_and_saveexec_b32 s10, s0 s_cbranch_execz .LBB0_683 ; %bb.676: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4 v_mov_b32_e32 v12, s5 s_clause 0x1 global_load_b64 v[13:14], v10, s[2:3] offset:32 glc global_load_b64 v[0:1], v10, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s12, v0 v_readfirstlane_b32 s13, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[12:13], s[12:13], s[4:5] s_mul_i32 s11, s13, 24 s_mul_hi_u32 s13, s12, 24 s_mul_i32 s12, s12, 24 s_add_i32 s13, s13, s11 v_add_co_u32 v8, vcc_lo, v4, s12 v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo s_mov_b32 s11, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[13:14] s_cbranch_execz .LBB0_679 ; %bb.677: ; %.preheader1.i.i.i.preheader s_mov_b32 s12, 0 .LBB0_678: ; %.preheader1.i.i.i ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 s_sleep 1 global_store_b64 v[8:9], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s12, vcc_lo, s12 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s12 s_cbranch_execnz .LBB0_678 .LBB0_679: ; %Flow1188 s_or_b32 exec_lo, exec_lo, s11 v_mov_b32_e32 v0, 0 s_mov_b32 s12, exec_lo s_mov_b32 s11, exec_lo v_mbcnt_lo_u32_b32 v2, s12, 0 global_load_b64 v[0:1], v0, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB0_681 ; %bb.680: s_bcnt1_i32_b32 s12, s12 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s12 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB0_681: s_or_b32 exec_lo, exec_lo, s11 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB0_683 ; %bb.682: global_load_b32 v0, v[0:1], off offset:24 v_mov_b32_e32 v1, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s11, v0 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[0:1], off s_and_b32 m0, s11, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_683: ; %Flow1189 s_or_b32 exec_lo, exec_lo, s10 s_mul_i32 s7, s7, 24 s_mul_hi_u32 s10, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s10, s10, s7 v_add_co_u32 v0, vcc_lo, v4, s6 v_add_co_ci_u32_e32 v1, vcc_lo, s10, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo .LBB0_684: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s6, s0 s_cbranch_execz .LBB0_686 ; %bb.685: ; in Loop: Header=BB0_684 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 .LBB0_686: ; in Loop: Header=BB0_684 Depth=1 s_or_b32 exec_lo, exec_lo, s6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s6, v2 s_cmp_eq_u32 s6, 0 s_cbranch_scc1 .LBB0_688 ; %bb.687: ; in Loop: Header=BB0_684 Depth=1 s_mov_b32 s6, 0 s_sleep 1 s_branch .LBB0_689 .LBB0_688: ; in Loop: Header=BB0_684 Depth=1 s_mov_b32 s6, -1 .LBB0_689: ; %Flow1183 ; in Loop: Header=BB0_684 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB0_684 ; %bb.690: global_load_b64 v[0:1], v[6:7], off s_and_saveexec_b32 s6, s0 s_cbranch_execz .LBB0_694 ; %bb.691: v_mov_b32_e32 v8, 0 s_clause 0x2 global_load_b64 v[4:5], v8, s[2:3] offset:40 global_load_b64 v[9:10], v8, s[2:3] offset:24 glc global_load_b64 v[6:7], v8, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v11, vcc_lo, v4, 1 v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, v11, s4 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11 v_and_b32_e32 v5, v3, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v4, v2, v4 v_mul_lo_u32 v5, v5, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v11, v4, 24 v_mul_lo_u32 v4, v4, 24 v_add_nc_u32_e32 v5, v11, v5 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, v6, v4 v_mov_b32_e32 v4, v9 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v5, v10 global_store_b64 v[6:7], v[9:10], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_694 ; %bb.692: ; %.preheader.i.i.i.preheader s_mov_b32 s0, 0 .LBB0_693: ; %.preheader.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5] v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_693 .LBB0_694: ; %__ockl_devmem_request.exit s_or_b32 exec_lo, exec_lo, s6 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s0, exec_lo s_waitcnt vmcnt(0) v_cmpx_ne_u64_e32 0, v[0:1] s_cbranch_execz .LBB0_698 ; %bb.695: s_mov_b32 s2, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mbcnt_lo_u32_b32 v2, s2, 0 v_cmp_eq_u32_e32 vcc_lo, 0, v2 s_and_b32 s3, exec_lo, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 exec_lo, s3 s_cbranch_execz .LBB0_698 ; %bb.696: s_mov_b32 s3, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mbcnt_lo_u32_b32 v2, s3, 0 v_cmp_eq_u32_e32 vcc_lo, 0, v2 s_and_b32 s4, exec_lo, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 exec_lo, s4 s_cbranch_execz .LBB0_698 ; %bb.697: s_load_b64 s[4:5], s[8:9], 0x60 s_bcnt1_i32_b32 s2, s2 s_bcnt1_i32_b32 s3, s3 v_mov_b32_e32 v4, 0x1a000 s_mul_i32 s2, s2, s3 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s2 s_waitcnt lgkmcnt(0) global_atomic_add_u64 v4, v[2:3], s[4:5] offset:2184 .LBB0_698: s_or_b32 exec_lo, exec_lo, s0 .LBB0_699: ; %Flow1195 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 .LBB0_700: ; %.loopexit198 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s24 v_readlane_b32 s30, v40, 7 v_readlane_b32 s31, v40, 8 v_readlane_b32 s40, v40, 6 v_readlane_b32 s39, v40, 5 v_readlane_b32 s38, v40, 4 v_readlane_b32 s37, v40, 3 v_readlane_b32 s36, v40, 2 v_readlane_b32 s35, v40, 1 v_readlane_b32 s34, v40, 0 s_or_saveexec_b32 s0, -1 scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload s_mov_b32 exec_lo, s0 s_waitcnt vmcnt(0) lgkmcnt(0) s_setpc_b64 s[30:31] .Lfunc_end0: .size __ockl_dm_alloc, .Lfunc_end0-__ockl_dm_alloc ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 24476 ; NumSgprs: 43 ; NumVgprs: 117 ; ScratchSize: 8 ; MemoryBound: 0 .text .protected CUDAlogkernel ; -- Begin function CUDAlogkernel .globl CUDAlogkernel .p2align 8 .type CUDAlogkernel,@function CUDAlogkernel: ; @CUDAlogkernel ; %bb.0: s_mov_b64 s[42:43], s[0:1] s_load_b32 s0, s[0:1], 0x44 s_clause 0x1 s_load_b128 s[44:47], s[42:43], 0x0 s_load_b128 s[48:51], s[42:43], 0x20 s_mov_b32 s32, 0 s_waitcnt lgkmcnt(0) s_and_b32 s0, s0, 0xffff s_add_u32 s8, s42, 56 v_mad_u64_u32 v[56:57], null, s15, s0, v[0:1] v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0 s_addc_u32 s9, s43, 0 s_getpc_b64 s[52:53] s_add_u32 s52, s52, __ockl_dm_alloc@rel32@lo+4 s_addc_u32 s53, s53, __ockl_dm_alloc@rel32@hi+12 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_swappc_b64 s[30:31], s[52:53] v_dual_mov_b32 v45, v0 :: v_dual_mov_b32 v46, v1 v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0 s_swappc_b64 s[30:31], s[52:53] v_dual_mov_b32 v41, v0 :: v_dual_mov_b32 v42, v1 v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0 s_swappc_b64 s[30:31], s[52:53] s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v43, v0 :: v_dual_mov_b32 v44, v1 v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0 s_swappc_b64 s[30:31], s[52:53] v_ashrrev_i32_e32 v57, 31, v56 v_add_f64 v[6:7], s[44:45], s[46:47] v_add_f64 v[8:9], s[44:45], -s[46:47] s_mov_b32 s1, 0x3d16849b s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 3, v[56:57] v_add_co_u32 v4, vcc_lo, s48, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, s49, v3, vcc_lo v_add_co_u32 v2, vcc_lo, s50, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s51, v3, vcc_lo global_load_b64 v[4:5], v[4:5], off global_load_b64 v[2:3], v[2:3], off s_waitcnt vmcnt(1) v_fma_f64 v[4:5], v[4:5], -2.0, v[6:7] s_waitcnt vmcnt(0) v_mul_f64 v[6:7], v[2:3], -2.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_scale_f64 v[2:3], null, v[8:9], v[8:9], v[4:5] v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], v[6:7] v_div_scale_f64 v[20:21], vcc_lo, v[4:5], v[8:9], v[4:5] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_rcp_f64_e32 v[12:13], v[2:3] v_rcp_f64_e32 v[14:15], v[10:11] s_waitcnt_depctr 0xfff v_fma_f64 v[16:17], -v[2:3], v[12:13], 1.0 v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[16:17], -v[2:3], v[12:13], 1.0 v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] v_div_scale_f64 v[16:17], s0, v[6:7], v[8:9], v[6:7] v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[18:19], v[20:21], v[12:13] v_mul_f64 v[22:23], v[16:17], v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[2:3], -v[2:3], v[18:19], v[20:21] v_fma_f64 v[10:11], -v[10:11], v[22:23], v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_div_fmas_f64 v[2:3], v[2:3], v[12:13], v[18:19] s_mov_b32 vcc_lo, s0 s_mov_b32 s0, 0x86a12b9b v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_fixup_f64 v[2:3], v[2:3], v[8:9], v[4:5] v_div_fixup_f64 v[4:5], v[10:11], v[8:9], v[6:7] v_lshlrev_b64 v[6:7], 4, v[56:57] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_ge_f64_e32 vcc_lo, 1.0, v[2:3] v_cmp_le_f64_e64 s2, |v[4:5]|, s[0:1] v_cmp_le_f64_e64 s0, -1.0, v[2:3] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v6, s1, v45, v6 v_add_co_ci_u32_e64 v7, s1, v46, v7, s1 global_store_b128 v[6:7], v[2:5], off ; implicit-def: $vgpr6_vgpr7 s_and_b32 s1, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s0, s1, s0 s_and_saveexec_b32 s1, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s2, exec_lo, s1 s_cbranch_execz .LBB1_70 ; %bb.1: v_add_f64 v[10:11], -v[2:3], 1.0 v_cmp_neq_f64_e64 s0, 0, v[4:5] v_mov_b32_e32 v8, 0 v_xor_b32_e32 v7, 0x80000000, v5 v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v6, v4 v_cmp_neq_f64_e32 vcc_lo, 0, v[10:11] s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s0 s_cbranch_execz .LBB1_35 ; %bb.2: s_mov_b32 s0, 0 s_mov_b32 s1, 0x7ff00000 v_mov_b32_e32 v8, s0 v_mov_b32_e32 v9, s1 s_mov_b32 s4, exec_lo v_cmpx_neq_f64_e64 0x7ff00000, |v[4:5]| s_cbranch_execz .LBB1_34 ; %bb.3: s_mov_b32 s0, exec_lo v_cmpx_o_f64_e32 v[10:11], v[10:11] s_xor_b32 s5, exec_lo, s0 s_cbranch_execz .LBB1_31 ; %bb.4: s_mov_b32 s1, exec_lo v_cmpx_neq_f64_e64 0x7ff00000, |v[10:11]| s_xor_b32 s6, exec_lo, s1 s_cbranch_execz .LBB1_24 ; %bb.5: s_mov_b32 s1, 0x7fda8279 s_mov_b32 s0, 0x99fcef32 s_mov_b32 s8, 0 v_cmp_ge_f64_e64 s9, |v[10:11]|, s[0:1] s_mov_b32 s7, exec_lo ; implicit-def: $vgpr14_vgpr15 v_cmpx_nge_f64_e64 |v[10:11]|, s[0:1] ; %bb.6: v_cmp_ge_f64_e64 s0, |v[4:5]|, s[0:1] v_xor_b32_e32 v15, 0x80000000, v5 v_mov_b32_e32 v14, v4 s_and_not1_b32 s1, s9, exec_lo s_mov_b32 s8, exec_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s0, s0, exec_lo s_or_b32 s9, s1, s0 ; %bb.7: ; %Flow359 s_or_b32 exec_lo, exec_lo, s7 ; implicit-def: $sgpr1 ; implicit-def: $sgpr7 ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $vgpr8_vgpr9 s_and_saveexec_b32 s0, s9 ; %bb.8: v_ldexp_f64 v[12:13], v[10:11], -2 v_ldexp_f64 v[8:9], -v[4:5], -2 s_mov_b32 s7, -1 s_mov_b32 s1, 0 s_and_not1_b32 s8, s8, exec_lo ; %bb.9: ; %Flow360 s_or_b32 exec_lo, exec_lo, s0 s_and_saveexec_b32 s0, s8 s_cbranch_execz .LBB1_13 ; %bb.10: v_cmp_ge_f64_e64 s8, 0x200000, |v[10:11]| v_cmp_ge_f64_e64 s9, 0x200000, |v[14:15]| s_delay_alu instid0(VALU_DEP_1) s_and_b32 s10, s9, s8 s_mov_b32 s8, 0 s_and_saveexec_b32 s9, s10 ; %bb.11: v_mul_f64 v[10:11], v[10:11], 4.0 v_mul_f64 v[6:7], v[4:5], -4.0 s_mov_b32 s8, exec_lo ; %bb.12: ; %Flow356 s_or_b32 exec_lo, exec_lo, s9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10 s_and_not1_b32 s1, s1, exec_lo s_and_b32 s8, s8, exec_lo s_and_not1_b32 s7, s7, exec_lo s_or_b32 s1, s1, s8 .LBB1_13: s_or_b32 exec_lo, exec_lo, s0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_max_f64 v[6:7], |v[8:9]|, |v[8:9]| v_max_f64 v[10:11], |v[12:13]|, |v[12:13]| v_cmp_class_f64_e64 s8, v[12:13], 0x204 v_cmp_class_f64_e64 s9, v[8:9], 0x204 v_cmp_le_f64_e64 s0, 0, v[12:13] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_max_f64 v[6:7], v[10:11], v[6:7] s_or_b32 s8, s9, s8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_frexp_exp_i32_f64_e32 v18, v[6:7] v_sub_nc_u32_e32 v10, 0, v18 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[6:7], |v[8:9]|, v10 v_ldexp_f64 v[10:11], |v[12:13]|, v10 v_mul_f64 v[6:7], v[6:7], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], v[10:11], v[10:11], v[6:7] v_rsq_f64_e32 v[10:11], v[6:7] v_cmp_eq_f64_e32 vcc_lo, 0, v[6:7] s_waitcnt_depctr 0xfff v_mul_f64 v[14:15], v[6:7], v[10:11] v_mul_f64 v[10:11], v[10:11], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], -v[10:11], v[14:15], 0.5 v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], -v[14:15], v[14:15], v[6:7] v_fma_f64 v[10:11], v[16:17], v[10:11], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v7, v11, v7 :: v_dual_cndmask_b32 v6, v10, v6 v_cmp_o_f64_e32 vcc_lo, v[12:13], v[8:9] ; implicit-def: $vgpr10_vgpr11 v_ldexp_f64 v[6:7], v[6:7], v18 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v6, 0, v6, vcc_lo v_cndmask_b32_e32 v7, 0x7ff80000, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v14, v6, 0, s8 v_cndmask_b32_e64 v15, v7, 0x7ff00000, s8 ; implicit-def: $vgpr6_vgpr7 s_and_saveexec_b32 s8, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s0, exec_lo, s8 s_cbranch_execz .LBB1_15 ; %bb.14: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[12:13], v[14:15] v_mul_f64 v[6:7], v[6:7], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[6:7] v_cndmask_b32_e64 v10, 0, 1, vcc_lo v_lshlrev_b32_e32 v10, 8, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[6:7], v[6:7], v10 v_rsq_f64_e32 v[10:11], v[6:7] s_waitcnt_depctr 0xfff v_mul_f64 v[12:13], v[6:7], v[10:11] v_mul_f64 v[10:11], v[10:11], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], -v[10:11], v[12:13], 0.5 v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], -v[12:13], v[12:13], v[6:7] v_fma_f64 v[12:13], v[14:15], v[10:11], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], -v[12:13], v[12:13], v[6:7] v_fma_f64 v[10:11], v[14:15], v[10:11], v[12:13] v_cndmask_b32_e64 v12, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x260 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[10:11], v[10:11], v12 v_dual_cndmask_b32 v11, v11, v7 :: v_dual_cndmask_b32 v10, v10, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[10:11], v[10:11] v_div_scale_f64 v[12:13], null, v[6:7], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[14:15], v[12:13] s_waitcnt_depctr 0xfff v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0 v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0 v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] v_div_scale_f64 v[16:17], vcc_lo, v[8:9], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[18:19], v[16:17], v[14:15] v_fma_f64 v[12:13], -v[12:13], v[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[18:19] ; implicit-def: $vgpr14_vgpr15 v_div_fixup_f64 v[6:7], v[12:13], v[6:7], v[8:9] ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $vgpr8_vgpr9 .LBB1_15: ; %Flow355 s_or_saveexec_b32 s8, s0 s_xor_b32 s0, s7, -1 s_xor_b32 exec_lo, exec_lo, s8 s_cbranch_execz .LBB1_17 ; %bb.16: v_add_f64 v[6:7], v[14:15], -v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[6:7], v[6:7], 0.5 v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[6:7] v_cndmask_b32_e64 v10, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b32_e32 v10, 8, v10 v_ldexp_f64 v[6:7], v[6:7], v10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_rsq_f64_e32 v[10:11], v[6:7] s_waitcnt_depctr 0xfff v_mul_f64 v[12:13], v[6:7], v[10:11] v_mul_f64 v[10:11], v[10:11], 0.5 v_fma_f64 v[14:15], -v[10:11], v[12:13], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11] v_fma_f64 v[14:15], -v[12:13], v[12:13], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], v[14:15], v[10:11], v[12:13] v_fma_f64 v[14:15], -v[12:13], v[12:13], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_fma_f64 v[10:11], v[14:15], v[10:11], v[12:13] v_cndmask_b32_e64 v12, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x260 v_and_b32_e32 v13, 0x7fffffff, v9 v_ldexp_f64 v[10:11], v[10:11], v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_mov_b32 v12, v8 :: v_dual_cndmask_b32 v7, v11, v7 v_cndmask_b32_e32 v6, v10, v6, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[10:11], v[6:7], v[6:7] v_bfi_b32 v7, 0x7fffffff, v7, v9 v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], v[12:13] v_div_scale_f64 v[12:13], vcc_lo, v[12:13], v[10:11], v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[16:17], v[14:15] s_waitcnt_depctr 0xfff v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[18:19], v[12:13], v[16:17] v_fma_f64 v[12:13], -v[14:15], v[18:19], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[18:19] v_div_fixup_f64 v[10:11], v[12:13], v[10:11], |v[8:9]| .LBB1_17: s_or_b32 exec_lo, exec_lo, s8 s_and_saveexec_b32 s7, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s0, exec_lo, s7 s_cbranch_execz .LBB1_21 ; %bb.18: s_and_saveexec_b32 s7, s1 ; %bb.19: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[10:11], v[10:11], 0.5 v_mul_f64 v[6:7], v[6:7], 0.5 ; %bb.20: ; %Flow350 s_or_b32 exec_lo, exec_lo, s7 .LBB1_21: ; %Flow352 s_and_not1_saveexec_b32 s0, s0 ; %bb.22: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[10:11], v[10:11], v[10:11] v_add_f64 v[6:7], v[6:7], v[6:7] ; %bb.23: ; %Flow353 s_or_b32 exec_lo, exec_lo, s0 .LBB1_24: ; %Flow365 s_and_not1_saveexec_b32 s0, s6 s_cbranch_execz .LBB1_30 ; %bb.25: v_add_f64 v[8:9], v[4:5], -v[4:5] s_mov_b32 s1, exec_lo ; implicit-def: $vgpr6_vgpr7 s_delay_alu instid0(VALU_DEP_3) v_cmpx_lt_i64_e32 -1, v[10:11] s_xor_b32 s1, exec_lo, s1 ; %bb.26: v_xor_b32_e32 v6, 0x80000000, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_bfi_b32 v9, 0x7fffffff, v9, v6 v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9 ; implicit-def: $vgpr8_vgpr9 ; %bb.27: ; %Flow362 s_and_not1_saveexec_b32 s1, s1 ; %bb.28: v_xor_b32_e32 v6, 0x80000000, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_bfi_b32 v11, 0x7fffffff, v11, v6 v_dual_mov_b32 v6, v10 :: v_dual_and_b32 v9, 0x7fffffff, v9 v_mov_b32_e32 v7, v11 s_delay_alu instid0(VALU_DEP_2) v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8 ; %bb.29: ; %Flow363 s_or_b32 exec_lo, exec_lo, s1 .LBB1_30: ; %Flow366 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s0 .LBB1_31: ; %Flow368 s_and_not1_saveexec_b32 s0, s5 ; %bb.32: v_add_f64 v[6:7], v[4:5], -v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[8:9], vcc_lo, v[6:7], v[6:7], v[6:7] v_rcp_f64_e32 v[12:13], v[8:9] s_waitcnt_depctr 0xfff v_fma_f64 v[14:15], -v[8:9], v[12:13], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] v_fma_f64 v[14:15], -v[8:9], v[12:13], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] v_mul_f64 v[14:15], v[8:9], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[8:9], v[14:15], v[8:9] v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[14:15] s_delay_alu instid0(VALU_DEP_1) v_div_fixup_f64 v[6:7], v[8:9], v[6:7], v[6:7] ; %bb.33: ; %Flow369 s_or_b32 exec_lo, exec_lo, s0 v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11 .LBB1_34: ; %Flow371 s_or_b32 exec_lo, exec_lo, s4 .LBB1_35: ; %_ZN6thrust4sqrtIdEENS_7complexIT_EERKS3_.exit s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_4) s_or_b32 exec_lo, exec_lo, s3 v_add_f64 v[10:11], v[2:3], 1.0 v_cmp_neq_f64_e64 s0, 0, v[4:5] v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v13, v5 v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v12, v4 v_cmp_neq_f64_e32 vcc_lo, 0, v[10:11] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s0, vcc_lo, s0 s_and_saveexec_b32 s3, s0 s_cbranch_execz .LBB1_69 ; %bb.36: s_mov_b32 s0, 0 s_mov_b32 s1, 0x7ff00000 v_dual_mov_b32 v14, s0 :: v_dual_mov_b32 v13, v5 v_dual_mov_b32 v15, s1 :: v_dual_mov_b32 v12, v4 s_mov_b32 s4, exec_lo v_cmpx_neq_f64_e64 0x7ff00000, |v[4:5]| s_cbranch_execz .LBB1_68 ; %bb.37: ; implicit-def: $vgpr12_vgpr13 s_mov_b32 s0, exec_lo v_cmpx_o_f64_e32 v[10:11], v[10:11] s_xor_b32 s5, exec_lo, s0 s_cbranch_execz .LBB1_65 ; %bb.38: ; implicit-def: $vgpr12_vgpr13 s_mov_b32 s1, exec_lo v_cmpx_neq_f64_e64 0x7ff00000, |v[10:11]| s_xor_b32 s6, exec_lo, s1 s_cbranch_execz .LBB1_58 ; %bb.39: s_mov_b32 s1, 0x7fda8279 s_mov_b32 s0, 0x99fcef32 s_mov_b32 s8, 0 v_cmp_ge_f64_e64 s9, |v[10:11]|, s[0:1] s_mov_b32 s7, exec_lo v_cmpx_nge_f64_e64 |v[10:11]|, s[0:1] ; %bb.40: v_cmp_ge_f64_e64 s0, |v[4:5]|, s[0:1] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) s_and_not1_b32 s1, s9, exec_lo s_mov_b32 s8, exec_lo s_and_b32 s0, s0, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s9, s1, s0 ; %bb.41: ; %Flow336 s_or_b32 exec_lo, exec_lo, s7 ; implicit-def: $sgpr1 ; implicit-def: $sgpr7 ; implicit-def: $vgpr16_vgpr17 ; implicit-def: $vgpr14_vgpr15 s_and_saveexec_b32 s0, s9 ; %bb.42: v_ldexp_f64 v[16:17], v[10:11], -2 v_ldexp_f64 v[14:15], v[4:5], -2 s_mov_b32 s7, -1 s_mov_b32 s1, 0 s_and_not1_b32 s8, s8, exec_lo ; %bb.43: ; %Flow337 s_or_b32 exec_lo, exec_lo, s0 s_and_saveexec_b32 s0, s8 s_cbranch_execz .LBB1_47 ; %bb.44: v_cmp_ge_f64_e64 s8, 0x200000, |v[10:11]| v_cmp_ge_f64_e64 s9, 0x200000, |v[4:5]| v_dual_mov_b32 v15, v5 :: v_dual_mov_b32 v14, v4 s_delay_alu instid0(VALU_DEP_2) s_and_b32 s10, s9, s8 s_mov_b32 s8, 0 s_and_saveexec_b32 s9, s10 ; %bb.45: v_mul_f64 v[10:11], v[10:11], 4.0 v_mul_f64 v[14:15], v[4:5], 4.0 s_mov_b32 s8, exec_lo ; %bb.46: ; %Flow333 s_or_b32 exec_lo, exec_lo, s9 s_delay_alu instid0(VALU_DEP_2) v_dual_mov_b32 v17, v11 :: v_dual_mov_b32 v16, v10 s_and_not1_b32 s1, s1, exec_lo s_and_b32 s8, s8, exec_lo s_and_not1_b32 s7, s7, exec_lo s_or_b32 s1, s1, s8 .LBB1_47: s_or_b32 exec_lo, exec_lo, s0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_max_f64 v[10:11], |v[14:15]|, |v[14:15]| v_max_f64 v[12:13], |v[16:17]|, |v[16:17]| v_cmp_class_f64_e64 s8, v[16:17], 0x204 v_cmp_class_f64_e64 s9, v[14:15], 0x204 v_cmp_le_f64_e64 s0, 0, v[16:17] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_max_f64 v[10:11], v[12:13], v[10:11] s_or_b32 s8, s9, s8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_frexp_exp_i32_f64_e32 v22, v[10:11] v_sub_nc_u32_e32 v12, 0, v22 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[10:11], |v[14:15]|, v12 v_ldexp_f64 v[12:13], |v[16:17]|, v12 v_mul_f64 v[10:11], v[10:11], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[10:11], v[12:13], v[12:13], v[10:11] v_rsq_f64_e32 v[12:13], v[10:11] v_cmp_eq_f64_e32 vcc_lo, 0, v[10:11] s_waitcnt_depctr 0xfff v_mul_f64 v[18:19], v[10:11], v[12:13] v_mul_f64 v[12:13], v[12:13], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[12:13], v[18:19], 0.5 v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] v_fma_f64 v[12:13], v[12:13], v[20:21], v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[18:19], v[18:19], v[10:11] v_fma_f64 v[12:13], v[20:21], v[12:13], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v12, v10 v_cmp_o_f64_e32 vcc_lo, v[16:17], v[14:15] ; implicit-def: $vgpr12_vgpr13 v_ldexp_f64 v[10:11], v[10:11], v22 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v10, 0, v10, vcc_lo v_cndmask_b32_e32 v11, 0x7ff80000, v11, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v18, v10, 0, s8 v_cndmask_b32_e64 v19, v11, 0x7ff00000, s8 ; implicit-def: $vgpr10_vgpr11 s_and_saveexec_b32 s8, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s0, exec_lo, s8 s_cbranch_execz .LBB1_49 ; %bb.48: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[10:11], v[16:17], v[18:19] v_mul_f64 v[10:11], v[10:11], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[10:11] v_cndmask_b32_e64 v12, 0, 1, vcc_lo v_lshlrev_b32_e32 v12, 8, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[10:11], v[10:11], v12 v_rsq_f64_e32 v[12:13], v[10:11] s_waitcnt_depctr 0xfff v_mul_f64 v[16:17], v[10:11], v[12:13] v_mul_f64 v[12:13], v[12:13], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[12:13], v[16:17], 0.5 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[16:17], v[16:17], v[10:11] v_fma_f64 v[16:17], v[18:19], v[12:13], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[16:17], v[16:17], v[10:11] v_fma_f64 v[12:13], v[18:19], v[12:13], v[16:17] v_cndmask_b32_e64 v16, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x260 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[12:13], v[12:13], v16 v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v12, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[12:13], v[10:11], v[10:11] v_div_scale_f64 v[16:17], null, v[12:13], v[12:13], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[18:19], v[16:17] s_waitcnt_depctr 0xfff v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] v_div_scale_f64 v[20:21], vcc_lo, v[14:15], v[12:13], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[22:23], v[20:21], v[18:19] v_fma_f64 v[16:17], -v[16:17], v[22:23], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[16:17], v[16:17], v[18:19], v[22:23] ; implicit-def: $vgpr18_vgpr19 v_div_fixup_f64 v[12:13], v[16:17], v[12:13], v[14:15] ; implicit-def: $vgpr16_vgpr17 ; implicit-def: $vgpr14_vgpr15 .LBB1_49: ; %Flow332 s_or_saveexec_b32 s8, s0 s_xor_b32 s0, s7, -1 s_xor_b32 exec_lo, exec_lo, s8 s_cbranch_execz .LBB1_51 ; %bb.50: v_add_f64 v[10:11], v[18:19], -v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[10:11], v[10:11], 0.5 v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[10:11] v_cndmask_b32_e64 v12, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b32_e32 v12, 8, v12 v_ldexp_f64 v[10:11], v[10:11], v12 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_rsq_f64_e32 v[12:13], v[10:11] s_waitcnt_depctr 0xfff v_mul_f64 v[16:17], v[10:11], v[12:13] v_mul_f64 v[12:13], v[12:13], 0.5 v_fma_f64 v[18:19], -v[12:13], v[16:17], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13] v_fma_f64 v[18:19], -v[16:17], v[16:17], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], v[18:19], v[12:13], v[16:17] v_fma_f64 v[18:19], -v[16:17], v[16:17], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_fma_f64 v[12:13], v[18:19], v[12:13], v[16:17] v_cndmask_b32_e64 v16, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x260 v_and_b32_e32 v17, 0x7fffffff, v15 v_ldexp_f64 v[12:13], v[12:13], v16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_mov_b32 v16, v14 :: v_dual_cndmask_b32 v13, v13, v11 v_cndmask_b32_e32 v12, v12, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[10:11], v[12:13], v[12:13] v_bfi_b32 v13, 0x7fffffff, v13, v15 v_div_scale_f64 v[18:19], null, v[10:11], v[10:11], v[16:17] v_div_scale_f64 v[16:17], vcc_lo, v[16:17], v[10:11], v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[20:21], v[18:19] s_waitcnt_depctr 0xfff v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0 v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0 v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[22:23], v[16:17], v[20:21] v_fma_f64 v[16:17], -v[18:19], v[22:23], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[16:17], v[16:17], v[20:21], v[22:23] v_div_fixup_f64 v[10:11], v[16:17], v[10:11], |v[14:15]| .LBB1_51: s_or_b32 exec_lo, exec_lo, s8 s_and_saveexec_b32 s7, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s0, exec_lo, s7 s_cbranch_execz .LBB1_55 ; %bb.52: s_and_saveexec_b32 s7, s1 ; %bb.53: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[10:11], v[10:11], 0.5 v_mul_f64 v[12:13], v[12:13], 0.5 ; %bb.54: ; %Flow328 s_or_b32 exec_lo, exec_lo, s7 .LBB1_55: ; %Flow329 s_and_not1_saveexec_b32 s0, s0 ; %bb.56: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[10:11], v[10:11], v[10:11] v_add_f64 v[12:13], v[12:13], v[12:13] ; %bb.57: ; %Flow330 s_or_b32 exec_lo, exec_lo, s0 .LBB1_58: ; %Flow342 s_and_not1_saveexec_b32 s0, s6 s_cbranch_execz .LBB1_64 ; %bb.59: v_add_f64 v[14:15], v[4:5], -v[4:5] s_mov_b32 s1, exec_lo ; implicit-def: $vgpr12_vgpr13 s_delay_alu instid0(VALU_DEP_3) v_cmpx_lt_i64_e32 -1, v[10:11] s_xor_b32 s1, exec_lo, s1 ; %bb.60: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_bfi_b32 v15, 0x7fffffff, v15, v5 v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v13, v15 ; implicit-def: $vgpr14_vgpr15 ; %bb.61: ; %Flow339 s_and_not1_saveexec_b32 s1, s1 ; %bb.62: v_bfi_b32 v11, 0x7fffffff, v11, v5 v_and_b32_e32 v15, 0x7fffffff, v15 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10 v_dual_mov_b32 v10, v14 :: v_dual_mov_b32 v11, v15 ; %bb.63: ; %Flow340 s_or_b32 exec_lo, exec_lo, s1 .LBB1_64: ; %Flow343 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s0 .LBB1_65: ; %Flow345 s_and_not1_saveexec_b32 s0, s5 ; %bb.66: v_add_f64 v[12:13], v[4:5], -v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[14:15], vcc_lo, v[12:13], v[12:13], v[12:13] v_rcp_f64_e32 v[16:17], v[14:15] s_waitcnt_depctr 0xfff v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] v_mul_f64 v[18:19], v[14:15], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], -v[14:15], v[18:19], v[14:15] v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[18:19] s_delay_alu instid0(VALU_DEP_1) v_div_fixup_f64 v[12:13], v[14:15], v[12:13], v[12:13] ; %bb.67: ; %Flow346 s_or_b32 exec_lo, exec_lo, s0 v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10 .LBB1_68: ; %Flow348 s_or_b32 exec_lo, exec_lo, s4 .LBB1_69: ; %_ZN6thrust4sqrtIdEENS_7complexIT_EERKS3_.exit209 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) s_or_b32 exec_lo, exec_lo, s3 v_fma_f64 v[10:11], v[6:7], 0, v[8:9] v_fma_f64 v[6:7], v[8:9], 0, -v[6:7] v_mul_f64 v[8:9], v[10:11], v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[12:13], v[6:7], v[12:13] v_fma_f64 v[6:7], v[6:7], v[14:15], -v[8:9] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[8:9], v[10:11], v[14:15], v[12:13] v_add_f64 v[2:3], v[2:3], v[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[4:5], v[8:9] v_lshlrev_b64 v[4:5], 4, v[56:57] v_add_co_u32 v4, vcc_lo, v41, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, v42, v5, vcc_lo global_store_b64 v[4:5], v[2:3], off ; implicit-def: $vgpr4_vgpr5 .LBB1_70: ; %Flow419 s_and_not1_saveexec_b32 s2, s2 s_cbranch_execz .LBB1_140 ; %bb.71: v_add_f64 v[10:11], v[2:3], -1.0 v_cmp_neq_f64_e64 s0, 0, v[4:5] v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v7, v5 v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v6, v4 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_neq_f64_e32 vcc_lo, 0, v[10:11] s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s0 s_cbranch_execz .LBB1_105 ; %bb.72: s_mov_b32 s0, 0 s_mov_b32 s1, 0x7ff00000 v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v7, v5 v_dual_mov_b32 v9, s1 :: v_dual_mov_b32 v6, v4 s_mov_b32 s4, exec_lo v_cmpx_neq_f64_e64 0x7ff00000, |v[4:5]| s_cbranch_execz .LBB1_104 ; %bb.73: ; implicit-def: $vgpr6_vgpr7 s_mov_b32 s0, exec_lo v_cmpx_o_f64_e32 v[10:11], v[10:11] s_xor_b32 s5, exec_lo, s0 s_cbranch_execz .LBB1_101 ; %bb.74: ; implicit-def: $vgpr6_vgpr7 s_mov_b32 s1, exec_lo v_cmpx_neq_f64_e64 0x7ff00000, |v[10:11]| s_xor_b32 s6, exec_lo, s1 s_cbranch_execz .LBB1_94 ; %bb.75: s_mov_b32 s1, 0x7fda8279 s_mov_b32 s0, 0x99fcef32 s_mov_b32 s8, 0 v_cmp_ge_f64_e64 s9, |v[10:11]|, s[0:1] s_mov_b32 s7, exec_lo v_cmpx_nge_f64_e64 |v[10:11]|, s[0:1] ; %bb.76: v_cmp_ge_f64_e64 s0, |v[4:5]|, s[0:1] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) s_and_not1_b32 s1, s9, exec_lo s_mov_b32 s8, exec_lo s_and_b32 s0, s0, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s9, s1, s0 ; %bb.77: ; %Flow405 s_or_b32 exec_lo, exec_lo, s7 ; implicit-def: $sgpr1 ; implicit-def: $sgpr7 ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $vgpr8_vgpr9 s_and_saveexec_b32 s0, s9 ; %bb.78: v_ldexp_f64 v[12:13], v[10:11], -2 v_ldexp_f64 v[8:9], v[4:5], -2 s_mov_b32 s7, -1 s_mov_b32 s1, 0 s_and_not1_b32 s8, s8, exec_lo ; %bb.79: ; %Flow406 s_or_b32 exec_lo, exec_lo, s0 s_and_saveexec_b32 s0, s8 s_cbranch_execz .LBB1_83 ; %bb.80: v_cmp_ge_f64_e64 s8, 0x200000, |v[10:11]| v_cmp_ge_f64_e64 s9, 0x200000, |v[4:5]| v_dual_mov_b32 v9, v5 :: v_dual_mov_b32 v8, v4 s_delay_alu instid0(VALU_DEP_2) s_and_b32 s10, s9, s8 s_mov_b32 s8, 0 s_and_saveexec_b32 s9, s10 ; %bb.81: v_mul_f64 v[10:11], v[10:11], 4.0 v_mul_f64 v[8:9], v[4:5], 4.0 s_mov_b32 s8, exec_lo ; %bb.82: ; %Flow402 s_or_b32 exec_lo, exec_lo, s9 s_delay_alu instid0(VALU_DEP_2) v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10 s_and_not1_b32 s1, s1, exec_lo s_and_b32 s8, s8, exec_lo s_and_not1_b32 s7, s7, exec_lo s_or_b32 s1, s1, s8 .LBB1_83: s_or_b32 exec_lo, exec_lo, s0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_max_f64 v[6:7], |v[8:9]|, |v[8:9]| v_max_f64 v[10:11], |v[12:13]|, |v[12:13]| v_cmp_class_f64_e64 s8, v[12:13], 0x204 v_cmp_class_f64_e64 s9, v[8:9], 0x204 v_cmp_le_f64_e64 s0, 0, v[12:13] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_max_f64 v[6:7], v[10:11], v[6:7] s_or_b32 s8, s9, s8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_frexp_exp_i32_f64_e32 v18, v[6:7] v_sub_nc_u32_e32 v10, 0, v18 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[6:7], |v[8:9]|, v10 v_ldexp_f64 v[10:11], |v[12:13]|, v10 v_mul_f64 v[6:7], v[6:7], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], v[10:11], v[10:11], v[6:7] v_rsq_f64_e32 v[10:11], v[6:7] v_cmp_eq_f64_e32 vcc_lo, 0, v[6:7] s_waitcnt_depctr 0xfff v_mul_f64 v[14:15], v[6:7], v[10:11] v_mul_f64 v[10:11], v[10:11], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], -v[10:11], v[14:15], 0.5 v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], -v[14:15], v[14:15], v[6:7] v_fma_f64 v[10:11], v[16:17], v[10:11], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v7, v11, v7 :: v_dual_cndmask_b32 v6, v10, v6 v_cmp_o_f64_e32 vcc_lo, v[12:13], v[8:9] ; implicit-def: $vgpr10_vgpr11 v_ldexp_f64 v[6:7], v[6:7], v18 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v6, 0, v6, vcc_lo v_cndmask_b32_e32 v7, 0x7ff80000, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v14, v6, 0, s8 v_cndmask_b32_e64 v15, v7, 0x7ff00000, s8 ; implicit-def: $vgpr6_vgpr7 s_and_saveexec_b32 s8, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s0, exec_lo, s8 s_cbranch_execz .LBB1_85 ; %bb.84: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[12:13], v[14:15] v_mul_f64 v[6:7], v[6:7], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[6:7] v_cndmask_b32_e64 v10, 0, 1, vcc_lo v_lshlrev_b32_e32 v10, 8, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[6:7], v[6:7], v10 v_rsq_f64_e32 v[10:11], v[6:7] s_waitcnt_depctr 0xfff v_mul_f64 v[12:13], v[6:7], v[10:11] v_mul_f64 v[10:11], v[10:11], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], -v[10:11], v[12:13], 0.5 v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], -v[12:13], v[12:13], v[6:7] v_fma_f64 v[12:13], v[14:15], v[10:11], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], -v[12:13], v[12:13], v[6:7] v_fma_f64 v[10:11], v[14:15], v[10:11], v[12:13] v_cndmask_b32_e64 v12, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x260 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[10:11], v[10:11], v12 v_dual_cndmask_b32 v11, v11, v7 :: v_dual_cndmask_b32 v10, v10, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[10:11], v[10:11] v_div_scale_f64 v[12:13], null, v[6:7], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[14:15], v[12:13] s_waitcnt_depctr 0xfff v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0 v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0 v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] v_div_scale_f64 v[16:17], vcc_lo, v[8:9], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[18:19], v[16:17], v[14:15] v_fma_f64 v[12:13], -v[12:13], v[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[18:19] ; implicit-def: $vgpr14_vgpr15 v_div_fixup_f64 v[6:7], v[12:13], v[6:7], v[8:9] ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $vgpr8_vgpr9 .LBB1_85: ; %Flow401 s_or_saveexec_b32 s8, s0 s_xor_b32 s0, s7, -1 s_xor_b32 exec_lo, exec_lo, s8 s_cbranch_execz .LBB1_87 ; %bb.86: v_add_f64 v[6:7], v[14:15], -v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[6:7], v[6:7], 0.5 v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[6:7] v_cndmask_b32_e64 v10, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b32_e32 v10, 8, v10 v_ldexp_f64 v[6:7], v[6:7], v10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_rsq_f64_e32 v[10:11], v[6:7] s_waitcnt_depctr 0xfff v_mul_f64 v[12:13], v[6:7], v[10:11] v_mul_f64 v[10:11], v[10:11], 0.5 v_fma_f64 v[14:15], -v[10:11], v[12:13], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11] v_fma_f64 v[14:15], -v[12:13], v[12:13], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], v[14:15], v[10:11], v[12:13] v_fma_f64 v[14:15], -v[12:13], v[12:13], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_fma_f64 v[10:11], v[14:15], v[10:11], v[12:13] v_cndmask_b32_e64 v12, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x260 v_and_b32_e32 v13, 0x7fffffff, v9 v_ldexp_f64 v[10:11], v[10:11], v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_mov_b32 v12, v8 :: v_dual_cndmask_b32 v7, v11, v7 v_cndmask_b32_e32 v6, v10, v6, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[10:11], v[6:7], v[6:7] v_bfi_b32 v7, 0x7fffffff, v7, v9 v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], v[12:13] v_div_scale_f64 v[12:13], vcc_lo, v[12:13], v[10:11], v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[16:17], v[14:15] s_waitcnt_depctr 0xfff v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[18:19], v[12:13], v[16:17] v_fma_f64 v[12:13], -v[14:15], v[18:19], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[18:19] v_div_fixup_f64 v[10:11], v[12:13], v[10:11], |v[8:9]| .LBB1_87: s_or_b32 exec_lo, exec_lo, s8 s_and_saveexec_b32 s7, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s0, exec_lo, s7 s_cbranch_execz .LBB1_91 ; %bb.88: s_and_saveexec_b32 s7, s1 ; %bb.89: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[10:11], v[10:11], 0.5 v_mul_f64 v[6:7], v[6:7], 0.5 ; %bb.90: ; %Flow396 s_or_b32 exec_lo, exec_lo, s7 .LBB1_91: ; %Flow398 s_and_not1_saveexec_b32 s0, s0 ; %bb.92: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[10:11], v[10:11], v[10:11] v_add_f64 v[6:7], v[6:7], v[6:7] ; %bb.93: ; %Flow399 s_or_b32 exec_lo, exec_lo, s0 .LBB1_94: ; %Flow411 s_and_not1_saveexec_b32 s0, s6 s_cbranch_execz .LBB1_100 ; %bb.95: v_add_f64 v[8:9], v[4:5], -v[4:5] s_mov_b32 s1, exec_lo ; implicit-def: $vgpr6_vgpr7 s_delay_alu instid0(VALU_DEP_3) v_cmpx_lt_i64_e32 -1, v[10:11] s_xor_b32 s1, exec_lo, s1 ; %bb.96: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_bfi_b32 v9, 0x7fffffff, v9, v5 v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9 ; implicit-def: $vgpr8_vgpr9 ; %bb.97: ; %Flow408 s_and_not1_saveexec_b32 s1, s1 ; %bb.98: v_bfi_b32 v11, 0x7fffffff, v11, v5 v_dual_mov_b32 v6, v10 :: v_dual_and_b32 v9, 0x7fffffff, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mov_b32_e32 v7, v11 v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8 ; %bb.99: ; %Flow409 s_or_b32 exec_lo, exec_lo, s1 .LBB1_100: ; %Flow412 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s0 .LBB1_101: ; %Flow414 s_and_not1_saveexec_b32 s0, s5 ; %bb.102: v_add_f64 v[6:7], v[4:5], -v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[8:9], vcc_lo, v[6:7], v[6:7], v[6:7] v_rcp_f64_e32 v[12:13], v[8:9] s_waitcnt_depctr 0xfff v_fma_f64 v[14:15], -v[8:9], v[12:13], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] v_fma_f64 v[14:15], -v[8:9], v[12:13], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] v_mul_f64 v[14:15], v[8:9], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[8:9], v[14:15], v[8:9] v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[14:15] s_delay_alu instid0(VALU_DEP_1) v_div_fixup_f64 v[6:7], v[8:9], v[6:7], v[6:7] ; %bb.103: ; %Flow415 s_or_b32 exec_lo, exec_lo, s0 v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11 .LBB1_104: ; %Flow417 s_or_b32 exec_lo, exec_lo, s4 .LBB1_105: ; %_ZN6thrust4sqrtIdEENS_7complexIT_EERKS3_.exit225 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_4) s_or_b32 exec_lo, exec_lo, s3 v_add_f64 v[10:11], v[2:3], 1.0 v_cmp_neq_f64_e64 s0, 0, v[4:5] v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v13, v5 v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v12, v4 v_cmp_neq_f64_e32 vcc_lo, 0, v[10:11] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s0, vcc_lo, s0 s_and_saveexec_b32 s3, s0 s_cbranch_execz .LBB1_139 ; %bb.106: s_mov_b32 s0, 0 s_mov_b32 s1, 0x7ff00000 v_dual_mov_b32 v14, s0 :: v_dual_mov_b32 v13, v5 v_dual_mov_b32 v15, s1 :: v_dual_mov_b32 v12, v4 s_mov_b32 s4, exec_lo v_cmpx_neq_f64_e64 0x7ff00000, |v[4:5]| s_cbranch_execz .LBB1_138 ; %bb.107: ; implicit-def: $vgpr12_vgpr13 s_mov_b32 s0, exec_lo v_cmpx_o_f64_e32 v[10:11], v[10:11] s_xor_b32 s5, exec_lo, s0 s_cbranch_execz .LBB1_135 ; %bb.108: ; implicit-def: $vgpr12_vgpr13 s_mov_b32 s1, exec_lo v_cmpx_neq_f64_e64 0x7ff00000, |v[10:11]| s_xor_b32 s6, exec_lo, s1 s_cbranch_execz .LBB1_128 ; %bb.109: s_mov_b32 s1, 0x7fda8279 s_mov_b32 s0, 0x99fcef32 s_mov_b32 s8, 0 v_cmp_ge_f64_e64 s9, |v[10:11]|, s[0:1] s_mov_b32 s7, exec_lo v_cmpx_nge_f64_e64 |v[10:11]|, s[0:1] ; %bb.110: v_cmp_ge_f64_e64 s0, |v[4:5]|, s[0:1] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) s_and_not1_b32 s1, s9, exec_lo s_mov_b32 s8, exec_lo s_and_b32 s0, s0, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s9, s1, s0 ; %bb.111: ; %Flow382 s_or_b32 exec_lo, exec_lo, s7 ; implicit-def: $sgpr1 ; implicit-def: $sgpr7 ; implicit-def: $vgpr16_vgpr17 ; implicit-def: $vgpr14_vgpr15 s_and_saveexec_b32 s0, s9 ; %bb.112: v_ldexp_f64 v[16:17], v[10:11], -2 v_ldexp_f64 v[14:15], v[4:5], -2 s_mov_b32 s7, -1 s_mov_b32 s1, 0 s_and_not1_b32 s8, s8, exec_lo ; %bb.113: ; %Flow383 s_or_b32 exec_lo, exec_lo, s0 s_and_saveexec_b32 s0, s8 s_cbranch_execz .LBB1_117 ; %bb.114: v_cmp_ge_f64_e64 s8, 0x200000, |v[10:11]| v_cmp_ge_f64_e64 s9, 0x200000, |v[4:5]| v_dual_mov_b32 v15, v5 :: v_dual_mov_b32 v14, v4 s_delay_alu instid0(VALU_DEP_2) s_and_b32 s10, s9, s8 s_mov_b32 s8, 0 s_and_saveexec_b32 s9, s10 ; %bb.115: v_mul_f64 v[10:11], v[10:11], 4.0 v_mul_f64 v[14:15], v[4:5], 4.0 s_mov_b32 s8, exec_lo ; %bb.116: ; %Flow379 s_or_b32 exec_lo, exec_lo, s9 s_delay_alu instid0(VALU_DEP_2) v_dual_mov_b32 v17, v11 :: v_dual_mov_b32 v16, v10 s_and_not1_b32 s1, s1, exec_lo s_and_b32 s8, s8, exec_lo s_and_not1_b32 s7, s7, exec_lo s_or_b32 s1, s1, s8 .LBB1_117: s_or_b32 exec_lo, exec_lo, s0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_max_f64 v[10:11], |v[14:15]|, |v[14:15]| v_max_f64 v[12:13], |v[16:17]|, |v[16:17]| v_cmp_class_f64_e64 s8, v[16:17], 0x204 v_cmp_class_f64_e64 s9, v[14:15], 0x204 v_cmp_le_f64_e64 s0, 0, v[16:17] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_max_f64 v[10:11], v[12:13], v[10:11] s_or_b32 s8, s9, s8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_frexp_exp_i32_f64_e32 v22, v[10:11] v_sub_nc_u32_e32 v12, 0, v22 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[10:11], |v[14:15]|, v12 v_ldexp_f64 v[12:13], |v[16:17]|, v12 v_mul_f64 v[10:11], v[10:11], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[10:11], v[12:13], v[12:13], v[10:11] v_rsq_f64_e32 v[12:13], v[10:11] v_cmp_eq_f64_e32 vcc_lo, 0, v[10:11] s_waitcnt_depctr 0xfff v_mul_f64 v[18:19], v[10:11], v[12:13] v_mul_f64 v[12:13], v[12:13], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[12:13], v[18:19], 0.5 v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] v_fma_f64 v[12:13], v[12:13], v[20:21], v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[18:19], v[18:19], v[10:11] v_fma_f64 v[12:13], v[20:21], v[12:13], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v12, v10 v_cmp_o_f64_e32 vcc_lo, v[16:17], v[14:15] ; implicit-def: $vgpr12_vgpr13 v_ldexp_f64 v[10:11], v[10:11], v22 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v10, 0, v10, vcc_lo v_cndmask_b32_e32 v11, 0x7ff80000, v11, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v18, v10, 0, s8 v_cndmask_b32_e64 v19, v11, 0x7ff00000, s8 ; implicit-def: $vgpr10_vgpr11 s_and_saveexec_b32 s8, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s0, exec_lo, s8 s_cbranch_execz .LBB1_119 ; %bb.118: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[10:11], v[16:17], v[18:19] v_mul_f64 v[10:11], v[10:11], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[10:11] v_cndmask_b32_e64 v12, 0, 1, vcc_lo v_lshlrev_b32_e32 v12, 8, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[10:11], v[10:11], v12 v_rsq_f64_e32 v[12:13], v[10:11] s_waitcnt_depctr 0xfff v_mul_f64 v[16:17], v[10:11], v[12:13] v_mul_f64 v[12:13], v[12:13], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[12:13], v[16:17], 0.5 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[16:17], v[16:17], v[10:11] v_fma_f64 v[16:17], v[18:19], v[12:13], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[16:17], v[16:17], v[10:11] v_fma_f64 v[12:13], v[18:19], v[12:13], v[16:17] v_cndmask_b32_e64 v16, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x260 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[12:13], v[12:13], v16 v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v12, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[12:13], v[10:11], v[10:11] v_div_scale_f64 v[16:17], null, v[12:13], v[12:13], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[18:19], v[16:17] s_waitcnt_depctr 0xfff v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] v_div_scale_f64 v[20:21], vcc_lo, v[14:15], v[12:13], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[22:23], v[20:21], v[18:19] v_fma_f64 v[16:17], -v[16:17], v[22:23], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[16:17], v[16:17], v[18:19], v[22:23] ; implicit-def: $vgpr18_vgpr19 v_div_fixup_f64 v[12:13], v[16:17], v[12:13], v[14:15] ; implicit-def: $vgpr16_vgpr17 ; implicit-def: $vgpr14_vgpr15 .LBB1_119: ; %Flow378 s_or_saveexec_b32 s8, s0 s_xor_b32 s0, s7, -1 s_xor_b32 exec_lo, exec_lo, s8 s_cbranch_execz .LBB1_121 ; %bb.120: v_add_f64 v[10:11], v[18:19], -v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[10:11], v[10:11], 0.5 v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[10:11] v_cndmask_b32_e64 v12, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b32_e32 v12, 8, v12 v_ldexp_f64 v[10:11], v[10:11], v12 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_rsq_f64_e32 v[12:13], v[10:11] s_waitcnt_depctr 0xfff v_mul_f64 v[16:17], v[10:11], v[12:13] v_mul_f64 v[12:13], v[12:13], 0.5 v_fma_f64 v[18:19], -v[12:13], v[16:17], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13] v_fma_f64 v[18:19], -v[16:17], v[16:17], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], v[18:19], v[12:13], v[16:17] v_fma_f64 v[18:19], -v[16:17], v[16:17], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_fma_f64 v[12:13], v[18:19], v[12:13], v[16:17] v_cndmask_b32_e64 v16, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x260 v_and_b32_e32 v17, 0x7fffffff, v15 v_ldexp_f64 v[12:13], v[12:13], v16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_mov_b32 v16, v14 :: v_dual_cndmask_b32 v13, v13, v11 v_cndmask_b32_e32 v12, v12, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[10:11], v[12:13], v[12:13] v_bfi_b32 v13, 0x7fffffff, v13, v15 v_div_scale_f64 v[18:19], null, v[10:11], v[10:11], v[16:17] v_div_scale_f64 v[16:17], vcc_lo, v[16:17], v[10:11], v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[20:21], v[18:19] s_waitcnt_depctr 0xfff v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0 v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0 v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[22:23], v[16:17], v[20:21] v_fma_f64 v[16:17], -v[18:19], v[22:23], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[16:17], v[16:17], v[20:21], v[22:23] v_div_fixup_f64 v[10:11], v[16:17], v[10:11], |v[14:15]| .LBB1_121: s_or_b32 exec_lo, exec_lo, s8 s_and_saveexec_b32 s7, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s0, exec_lo, s7 s_cbranch_execz .LBB1_125 ; %bb.122: s_and_saveexec_b32 s7, s1 ; %bb.123: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[10:11], v[10:11], 0.5 v_mul_f64 v[12:13], v[12:13], 0.5 ; %bb.124: ; %Flow373 s_or_b32 exec_lo, exec_lo, s7 .LBB1_125: ; %Flow375 s_and_not1_saveexec_b32 s0, s0 ; %bb.126: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[10:11], v[10:11], v[10:11] v_add_f64 v[12:13], v[12:13], v[12:13] ; %bb.127: ; %Flow376 s_or_b32 exec_lo, exec_lo, s0 .LBB1_128: ; %Flow388 s_and_not1_saveexec_b32 s0, s6 s_cbranch_execz .LBB1_134 ; %bb.129: v_add_f64 v[14:15], v[4:5], -v[4:5] s_mov_b32 s1, exec_lo ; implicit-def: $vgpr12_vgpr13 s_delay_alu instid0(VALU_DEP_3) v_cmpx_lt_i64_e32 -1, v[10:11] s_xor_b32 s1, exec_lo, s1 ; %bb.130: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_bfi_b32 v15, 0x7fffffff, v15, v5 v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v13, v15 ; implicit-def: $vgpr14_vgpr15 ; %bb.131: ; %Flow385 s_and_not1_saveexec_b32 s1, s1 ; %bb.132: v_bfi_b32 v11, 0x7fffffff, v11, v5 v_and_b32_e32 v15, 0x7fffffff, v15 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10 v_dual_mov_b32 v10, v14 :: v_dual_mov_b32 v11, v15 ; %bb.133: ; %Flow386 s_or_b32 exec_lo, exec_lo, s1 .LBB1_134: ; %Flow389 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s0 .LBB1_135: ; %Flow391 s_and_not1_saveexec_b32 s0, s5 ; %bb.136: v_add_f64 v[12:13], v[4:5], -v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[14:15], vcc_lo, v[12:13], v[12:13], v[12:13] v_rcp_f64_e32 v[16:17], v[14:15] s_waitcnt_depctr 0xfff v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] v_mul_f64 v[18:19], v[14:15], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], -v[14:15], v[18:19], v[14:15] v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[18:19] s_delay_alu instid0(VALU_DEP_1) v_div_fixup_f64 v[12:13], v[14:15], v[12:13], v[12:13] ; %bb.137: ; %Flow392 s_or_b32 exec_lo, exec_lo, s0 v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10 .LBB1_138: ; %Flow394 s_or_b32 exec_lo, exec_lo, s4 .LBB1_139: ; %_ZN6thrust4sqrtIdEENS_7complexIT_EERKS3_.exit237 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) s_or_b32 exec_lo, exec_lo, s3 v_mul_f64 v[10:11], v[6:7], v[12:13] v_mul_f64 v[12:13], v[8:9], v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[8:9], v[8:9], v[14:15], -v[10:11] v_fma_f64 v[6:7], v[6:7], v[14:15], v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[2:3], v[2:3], -v[8:9] v_add_f64 v[6:7], v[4:5], -v[6:7] v_lshlrev_b64 v[4:5], 4, v[56:57] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, v41, v4 v_add_co_ci_u32_e32 v5, vcc_lo, v42, v5, vcc_lo global_store_b64 v[4:5], v[2:3], off .LBB1_140: ; %Flow420 s_or_b32 exec_lo, exec_lo, s2 v_lshlrev_b64 v[12:13], 4, v[56:57] v_add_f64 v[14:15], s[46:47], -s[44:45] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v2, vcc_lo, v41, v12 v_add_co_ci_u32_e32 v3, vcc_lo, v42, v13, vcc_lo global_store_b64 v[2:3], v[6:7], off offset:8 global_load_b128 v[8:11], v[2:3], off v_add_co_u32 v6, vcc_lo, v43, v12 v_add_co_ci_u32_e32 v7, vcc_lo, v44, v13, vcc_lo v_add_co_u32 v0, vcc_lo, v0, v12 v_add_co_ci_u32_e32 v1, vcc_lo, v1, v13, vcc_lo s_waitcnt vmcnt(0) global_store_b128 v[6:7], v[8:11], off global_load_b128 v[8:11], v[6:7], off s_clause 0x1 s_load_b32 s1, s[42:43], 0x10 s_load_b64 s[2:3], s[42:43], 0x30 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s1, 0 s_waitcnt vmcnt(0) v_mul_f64 v[4:5], v[10:11], v[10:11] v_mul_f64 v[10:11], v[8:9], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[8:9], v[8:9], v[8:9], -v[4:5] v_add_f64 v[10:11], v[10:11], v[10:11] v_mul_f64 v[4:5], |v[14:15]|, 0.5 global_store_b128 v[0:1], v[8:11], off s_cbranch_scc1 .LBB1_146 ; %bb.141: global_load_b128 v[8:11], v[6:7], off s_mov_b32 s5, 0x3fe55555 s_mov_b32 s7, 0x3fc38538 s_mov_b32 s6, 0x6b47b09a s_mov_b32 s9, 0x3fc3ab76 s_mov_b32 s8, 0xbf559e2b s_waitcnt vmcnt(0) v_add_f64 v[8:9], v[8:9], v[8:9] v_add_f64 v[10:11], v[10:11], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_scale_f64 v[12:13], null, v[4:5], v[4:5], v[8:9] v_div_scale_f64 v[14:15], null, v[4:5], v[4:5], v[10:11] v_div_scale_f64 v[24:25], vcc_lo, v[8:9], v[4:5], v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_rcp_f64_e32 v[16:17], v[12:13] v_rcp_f64_e32 v[18:19], v[14:15] s_waitcnt_depctr 0xfff v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0 v_fma_f64 v[22:23], -v[14:15], v[18:19], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17] v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0 v_fma_f64 v[22:23], -v[14:15], v[18:19], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17] v_div_scale_f64 v[20:21], s0, v[10:11], v[4:5], v[10:11] v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[22:23], v[24:25], v[16:17] v_mul_f64 v[26:27], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[12:13], -v[12:13], v[22:23], v[24:25] v_fma_f64 v[14:15], -v[14:15], v[26:27], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[22:23] s_mov_b32 vcc_lo, s0 v_div_fmas_f64 v[14:15], v[14:15], v[18:19], v[26:27] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_fixup_f64 v[8:9], v[12:13], v[4:5], v[8:9] v_div_fixup_f64 v[10:11], v[14:15], v[4:5], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_class_f64_e64 s0, v[8:9], 0x204 v_max_f64 v[12:13], |v[8:9]|, |v[10:11]| v_cmp_class_f64_e64 s4, v[10:11], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_frexp_exp_i32_f64_e32 v20, v[12:13] s_or_b32 s0, s0, s4 s_mov_b32 s4, 0x55555555 s_cmp_eq_u32 s1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v14, 0, v20 v_ldexp_f64 v[12:13], |v[10:11]|, v14 v_ldexp_f64 v[14:15], |v[8:9]|, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[12:13], v[12:13], v[12:13] v_fma_f64 v[12:13], v[14:15], v[14:15], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_rsq_f64_e32 v[14:15], v[12:13] v_cmp_eq_f64_e32 vcc_lo, 0, v[12:13] s_waitcnt_depctr 0xfff v_mul_f64 v[16:17], v[12:13], v[14:15] v_mul_f64 v[14:15], v[14:15], 0.5 v_fma_f64 v[18:19], -v[14:15], v[16:17], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15] v_fma_f64 v[18:19], -v[16:17], v[16:17], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], v[18:19], v[14:15], v[16:17] v_dual_cndmask_b32 v13, v15, v13 :: v_dual_cndmask_b32 v12, v14, v12 v_cmp_o_f64_e32 vcc_lo, v[8:9], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[12:13], v[12:13], v20 v_cndmask_b32_e32 v9, 0x7ff80000, v13, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v9, v9, 0x7ff00000, s0 v_cndmask_b32_e32 v8, 0, v12, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v8, v8, 0, s0 v_frexp_mant_f64_e32 v[10:11], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[10:11] s_mov_b32 s4, 0x55555780 v_cndmask_b32_e64 v12, 0, 1, vcc_lo v_ldexp_f64 v[10:11], v[10:11], v12 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[12:13], v[10:11], 1.0 v_add_f64 v[18:19], v[10:11], -1.0 v_rcp_f64_e32 v[14:15], v[12:13] v_add_f64 v[20:21], v[12:13], -1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_f64 v[10:11], v[10:11], -v[20:21] s_waitcnt_depctr 0xfff v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0 v_fma_f64 v[14:15], v[16:17], v[14:15], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0 v_fma_f64 v[14:15], v[16:17], v[14:15], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[16:17], v[18:19], v[14:15] v_mul_f64 v[22:23], v[12:13], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], v[16:17], v[12:13], -v[22:23] v_fma_f64 v[10:11], v[16:17], v[10:11], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[12:13], v[22:23], v[10:11] v_add_f64 v[20:21], v[18:19], -v[12:13] v_add_f64 v[22:23], v[12:13], -v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[18:19], -v[20:21] v_add_f64 v[10:11], v[22:23], -v[10:11] v_frexp_exp_i32_f64_e32 v22, v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[12:13], v[18:19], -v[12:13] v_add_f64 v[10:11], v[10:11], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[10:11], v[20:21], v[10:11] v_mul_f64 v[10:11], v[14:15], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[12:13], v[16:17], v[10:11] v_mul_f64 v[14:15], v[12:13], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_fma_f64 v[18:19], v[14:15], s[8:9], s[6:7] s_mov_b32 s7, 0x3fc7474d s_mov_b32 s6, 0xd7f4df2e v_mul_f64 v[20:21], v[12:13], v[14:15] v_fma_f64 v[18:19], v[14:15], v[18:19], s[6:7] s_mov_b32 s7, 0x3fcc71c0 s_mov_b32 s6, 0x16291751 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[18:19], v[14:15], v[18:19], s[6:7] s_mov_b32 s7, 0x3fd24924 s_mov_b32 s6, 0x9b27acf1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[18:19], v[14:15], v[18:19], s[6:7] s_mov_b32 s7, 0x3fd99999 s_mov_b32 s6, 0x998ef7b6 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[18:19], v[14:15], v[18:19], s[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) v_fma_f64 v[14:15], v[14:15], v[18:19], s[4:5] v_ldexp_f64 v[18:19], v[12:13], 1 v_add_f64 v[12:13], v[12:13], -v[16:17] s_mov_b32 s5, 0x3fe62e42 s_mov_b32 s4, 0xfefa39ef v_mul_f64 v[14:15], v[20:21], v[14:15] v_subrev_co_ci_u32_e32 v20, vcc_lo, 0, v22, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[10:11], v[10:11], -v[12:13] v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x204 v_cvt_f64_i32_e32 v[20:21], v20 v_add_f64 v[16:17], v[18:19], v[14:15] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_ldexp_f64 v[10:11], v[10:11], 1 v_mul_f64 v[22:23], v[20:21], s[4:5] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[12:13], v[16:17], -v[18:19] v_fma_f64 v[18:19], v[20:21], s[4:5], -v[22:23] s_mov_b32 s5, 0x3c7abc9e s_mov_b32 s4, 0x3b39803f s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[12:13], v[14:15], -v[12:13] v_fma_f64 v[14:15], v[20:21], s[4:5], v[18:19] s_load_b64 s[4:5], s[42:43], 0x18 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[10:11], v[10:11], v[12:13] v_mov_b32_e32 v12, 0 v_add_f64 v[18:19], v[22:23], v[14:15] s_waitcnt lgkmcnt(0) global_load_b64 v[30:31], v12, s[4:5] v_add_f64 v[20:21], v[16:17], v[10:11] v_add_f64 v[22:23], v[18:19], -v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[24:25], v[18:19], v[20:21] v_add_f64 v[16:17], v[20:21], -v[16:17] v_add_f64 v[13:14], v[14:15], -v[22:23] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[26:27], v[24:25], -v[18:19] v_add_f64 v[10:11], v[10:11], -v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[28:29], v[24:25], -v[26:27] v_add_f64 v[15:16], v[20:21], -v[26:27] v_add_f64 v[17:18], v[18:19], -v[28:29] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[19:20], v[13:14], v[10:11] v_add_f64 v[15:16], v[15:16], v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[17:18], v[19:20], -v[13:14] v_add_f64 v[15:16], v[19:20], v[15:16] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[19:20], v[19:20], -v[17:18] v_add_f64 v[10:11], v[10:11], -v[17:18] v_add_f64 v[21:22], v[24:25], v[15:16] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[13:14], v[13:14], -v[19:20] v_add_f64 v[17:18], v[21:22], -v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[10:11], v[10:11], v[13:14] v_add_f64 v[13:14], v[15:16], -v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[10:11], v[10:11], v[13:14] v_add_f64 v[10:11], v[21:22], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v11, v11, v9 :: v_dual_cndmask_b32 v10, v10, v8 v_cmp_ngt_f64_e32 vcc_lo, 0, v[8:9] v_cndmask_b32_e32 v11, 0x7ff80000, v11, vcc_lo v_cmp_nge_f64_e32 vcc_lo, 0, v[8:9] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v10, 0, v10, vcc_lo v_cmp_neq_f64_e32 vcc_lo, 0, v[8:9] v_lshlrev_b64 v[8:9], 3, v[56:57] v_cndmask_b32_e32 v11, 0xfff00000, v11, vcc_lo v_add_co_u32 v8, vcc_lo, s2, v8 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo s_waitcnt vmcnt(0) v_mul_f64 v[10:11], v[10:11], -v[30:31] global_store_b64 v[8:9], v[10:11], off s_cbranch_scc1 .LBB1_146 ; %bb.142: global_load_b64 v[12:13], v12, s[4:5] offset:8 global_load_b64 v[14:15], v[6:7], off s_cmp_lt_i32 s1, 2 s_waitcnt vmcnt(0) v_fma_f64 v[10:11], -v[12:13], v[14:15], v[10:11] global_store_b64 v[8:9], v[10:11], off s_cbranch_scc1 .LBB1_146 ; %bb.143: global_load_b128 v[12:15], v[6:7], off s_mov_b32 s7, 0x3fe55555 s_mov_b32 s9, 0x3fc38538 s_mov_b32 s8, 0x6b47b09a s_mov_b32 s11, 0x3fc3ab76 s_mov_b32 s10, 0xbf559e2b global_load_b64 v[33:34], v[0:1], off s_waitcnt vmcnt(1) v_add_f64 v[12:13], v[12:13], v[12:13] v_add_f64 v[14:15], v[14:15], v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_scale_f64 v[16:17], null, v[4:5], v[4:5], v[12:13] v_div_scale_f64 v[18:19], null, v[4:5], v[4:5], v[14:15] v_div_scale_f64 v[28:29], vcc_lo, v[12:13], v[4:5], v[12:13] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_rcp_f64_e32 v[20:21], v[16:17] v_rcp_f64_e32 v[22:23], v[18:19] s_waitcnt_depctr 0xfff v_fma_f64 v[24:25], -v[16:17], v[20:21], 1.0 v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21] v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[24:25], -v[16:17], v[20:21], 1.0 v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21] v_div_scale_f64 v[24:25], s0, v[14:15], v[4:5], v[14:15] v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[26:27], v[28:29], v[20:21] v_mul_f64 v[30:31], v[24:25], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[16:17], -v[16:17], v[26:27], v[28:29] v_fma_f64 v[18:19], -v[18:19], v[30:31], v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fmas_f64 v[16:17], v[16:17], v[20:21], v[26:27] s_mov_b32 vcc_lo, s0 v_div_fmas_f64 v[18:19], v[18:19], v[22:23], v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_fixup_f64 v[12:13], v[16:17], v[4:5], v[12:13] v_div_fixup_f64 v[14:15], v[18:19], v[4:5], v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_class_f64_e64 s0, v[12:13], 0x204 v_max_f64 v[16:17], |v[12:13]|, |v[14:15]| v_cmp_class_f64_e64 s6, v[14:15], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_frexp_exp_i32_f64_e32 v24, v[16:17] s_or_b32 s0, s0, s6 s_mov_b32 s6, 0x55555555 s_cmp_lt_i32 s1, 4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v18, 0, v24 v_ldexp_f64 v[16:17], |v[14:15]|, v18 v_ldexp_f64 v[18:19], |v[12:13]|, v18 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[16:17], v[16:17], v[16:17] v_fma_f64 v[16:17], v[18:19], v[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_rsq_f64_e32 v[18:19], v[16:17] v_cmp_eq_f64_e32 vcc_lo, 0, v[16:17] s_waitcnt_depctr 0xfff v_mul_f64 v[20:21], v[16:17], v[18:19] v_mul_f64 v[18:19], v[18:19], 0.5 v_fma_f64 v[22:23], -v[18:19], v[20:21], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21] v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19] v_fma_f64 v[22:23], -v[20:21], v[20:21], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[22:23], v[18:19], v[20:21] v_dual_cndmask_b32 v17, v19, v17 :: v_dual_cndmask_b32 v16, v18, v16 v_cmp_o_f64_e32 vcc_lo, v[12:13], v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[16:17], v[16:17], v24 v_cndmask_b32_e32 v12, 0, v16, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v13, 0x7ff80000, v17, vcc_lo v_cndmask_b32_e64 v14, v13, 0x7ff00000, s0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v13, v12, 0, s0 v_frexp_mant_f64_e32 v[15:16], v[13:14] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, s[6:7], v[15:16] s_mov_b32 s6, 0x55555780 v_cndmask_b32_e64 v12, 0, 1, vcc_lo v_ldexp_f64 v[15:16], v[15:16], v12 v_frexp_exp_i32_f64_e32 v12, v[13:14] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[17:18], v[15:16], 1.0 v_add_f64 v[23:24], v[15:16], -1.0 v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[13:14], 0x204 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[19:20], v[17:18] v_add_f64 v[25:26], v[17:18], -1.0 v_add_f64 v[15:16], v[15:16], -v[25:26] s_waitcnt_depctr 0xfff v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[19:20], v[21:22], v[19:20], v[19:20] v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[19:20], v[21:22], v[19:20], v[19:20] v_mul_f64 v[21:22], v[23:24], v[19:20] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[27:28], v[17:18], v[21:22] v_fma_f64 v[17:18], v[21:22], v[17:18], -v[27:28] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[15:16], v[21:22], v[15:16], v[17:18] v_add_f64 v[17:18], v[27:28], v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[25:26], v[23:24], -v[17:18] v_add_f64 v[27:28], v[17:18], -v[27:28] v_add_f64 v[23:24], v[23:24], -v[25:26] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[15:16], v[27:28], -v[15:16] v_add_f64 v[17:18], v[23:24], -v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[15:16], v[15:16], v[17:18] v_add_f64 v[15:16], v[25:26], v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[15:16], v[19:20], v[15:16] v_add_f64 v[17:18], v[21:22], v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[19:20], v[17:18], v[17:18] v_fma_f64 v[23:24], v[19:20], s[10:11], s[8:9] s_mov_b32 s9, 0x3fc7474d s_mov_b32 s8, 0xd7f4df2e v_mul_f64 v[25:26], v[17:18], v[19:20] s_delay_alu instid0(VALU_DEP_2) v_fma_f64 v[23:24], v[19:20], v[23:24], s[8:9] s_mov_b32 s9, 0x3fcc71c0 s_mov_b32 s8, 0x16291751 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[23:24], v[19:20], v[23:24], s[8:9] s_mov_b32 s9, 0x3fd24924 s_mov_b32 s8, 0x9b27acf1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[23:24], v[19:20], v[23:24], s[8:9] s_mov_b32 s9, 0x3fd99999 s_mov_b32 s8, 0x998ef7b6 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[23:24], v[19:20], v[23:24], s[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) v_fma_f64 v[19:20], v[19:20], v[23:24], s[6:7] v_ldexp_f64 v[23:24], v[17:18], 1 v_add_f64 v[17:18], v[17:18], -v[21:22] s_mov_b32 s7, 0x3fe62e42 s_mov_b32 s6, 0xfefa39ef v_mul_f64 v[19:20], v[25:26], v[19:20] v_cvt_f64_i32_e32 v[25:26], v12 v_mov_b32_e32 v12, 0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[15:16], v[15:16], -v[17:18] v_add_f64 v[21:22], v[23:24], v[19:20] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f64 v[27:28], v[25:26], s[6:7] v_ldexp_f64 v[15:16], v[15:16], 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[17:18], v[21:22], -v[23:24] v_fma_f64 v[23:24], v[25:26], s[6:7], -v[27:28] s_mov_b32 s7, 0x3c7abc9e s_mov_b32 s6, 0x3b39803f s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[17:18], v[19:20], -v[17:18] v_fma_f64 v[19:20], v[25:26], s[6:7], v[23:24] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[15:16], v[15:16], v[17:18] v_add_f64 v[17:18], v[27:28], v[19:20] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[23:24], v[21:22], v[15:16] v_add_f64 v[27:28], v[17:18], -v[27:28] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[25:26], v[17:18], v[23:24] v_add_f64 v[21:22], v[23:24], -v[21:22] v_add_f64 v[19:20], v[19:20], -v[27:28] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[29:30], v[25:26], -v[17:18] v_add_f64 v[15:16], v[15:16], -v[21:22] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[31:32], v[25:26], -v[29:30] v_add_f64 v[21:22], v[23:24], -v[29:30] v_add_f64 v[27:28], v[19:20], v[15:16] global_load_b64 v[23:24], v12, s[4:5] offset:16 v_add_f64 v[17:18], v[17:18], -v[31:32] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[17:18], v[21:22], v[17:18] v_add_f64 v[21:22], v[27:28], -v[19:20] v_add_f64 v[17:18], v[27:28], v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[27:28], v[27:28], -v[21:22] v_add_f64 v[15:16], v[15:16], -v[21:22] v_add_f64 v[29:30], v[25:26], v[17:18] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[19:20], v[19:20], -v[27:28] v_add_f64 v[21:22], v[29:30], -v[25:26] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[15:16], v[15:16], v[19:20] v_add_f64 v[17:18], v[17:18], -v[21:22] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[15:16], v[15:16], v[17:18] v_add_f64 v[15:16], v[29:30], v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v15, v15, v13 :: v_dual_cndmask_b32 v16, v16, v14 v_cmp_ngt_f64_e32 vcc_lo, 0, v[13:14] v_cndmask_b32_e32 v16, 0x7ff80000, v16, vcc_lo v_cmp_nge_f64_e32 vcc_lo, 0, v[13:14] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v15, 0, v15, vcc_lo v_cmp_neq_f64_e32 vcc_lo, 0, v[13:14] v_cndmask_b32_e32 v16, 0xfff00000, v16, vcc_lo s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[13:14], v[33:34], -0.5, v[15:16] s_waitcnt vmcnt(0) v_fma_f64 v[10:11], v[23:24], v[13:14], v[10:11] global_store_b64 v[8:9], v[10:11], off s_cbranch_scc1 .LBB1_146 ; %bb.144: ; %.lr.ph v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0x40080000 s_add_i32 s1, s1, -3 s_add_u32 s4, s4, 24 s_addc_u32 s5, s5, 0 .LBB1_145: ; =>This Inner Loop Header: Depth=1 global_load_b128 v[13:16], v[0:1], off s_clause 0x1 global_load_b64 v[17:18], v[2:3], off offset:8 global_load_b64 v[19:20], v[2:3], off s_add_i32 s1, s1, -1 s_waitcnt vmcnt(1) v_mul_f64 v[21:22], v[15:16], v[17:18] v_mul_f64 v[17:18], v[13:14], v[17:18] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[13:14], v[13:14], v[19:20], -v[21:22] v_fma_f64 v[15:16], v[19:20], v[15:16], v[17:18] v_add_f64 v[17:18], v[10:11], -2.0 s_delay_alu instid0(VALU_DEP_3) v_div_scale_f64 v[21:22], null, v[10:11], v[10:11], v[13:14] global_store_b128 v[0:1], v[13:16], off global_load_b64 v[15:16], v[6:7], off global_load_b64 v[31:32], v12, s[4:5] global_load_b64 v[33:34], v[8:9], off v_div_scale_f64 v[35:36], s0, v[13:14], v[10:11], v[13:14] s_add_u32 s4, s4, 8 s_addc_u32 s5, s5, 0 s_cmp_lg_u32 s1, 0 v_rcp_f64_e32 v[25:26], v[21:22] s_waitcnt_depctr 0xfff v_fma_f64 v[29:30], -v[21:22], v[25:26], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[25:26], v[25:26], v[29:30], v[25:26] v_fma_f64 v[29:30], -v[21:22], v[25:26], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[25:26], v[25:26], v[29:30], v[25:26] v_mul_f64 v[29:30], v[35:36], v[25:26] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_fma_f64 v[21:22], -v[21:22], v[29:30], v[35:36] s_waitcnt vmcnt(2) v_div_scale_f64 v[19:20], null, v[17:18], v[17:18], v[15:16] v_div_scale_f64 v[37:38], vcc_lo, v[15:16], v[17:18], v[15:16] v_rcp_f64_e32 v[23:24], v[19:20] s_waitcnt_depctr 0xfff v_fma_f64 v[27:28], -v[19:20], v[23:24], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24] v_fma_f64 v[27:28], -v[19:20], v[23:24], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24] v_mul_f64 v[27:28], v[37:38], v[23:24] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[19:20], -v[19:20], v[27:28], v[37:38] v_div_fmas_f64 v[19:20], v[19:20], v[23:24], v[27:28] s_mov_b32 vcc_lo, s0 v_div_fmas_f64 v[21:22], v[21:22], v[25:26], v[29:30] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_fixup_f64 v[15:16], v[19:20], v[17:18], v[15:16] v_div_fixup_f64 v[13:14], v[21:22], v[10:11], v[13:14] v_add_f64 v[10:11], v[10:11], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[13:14], v[15:16], -v[13:14] s_waitcnt vmcnt(0) v_fma_f64 v[13:14], v[31:32], v[13:14], v[33:34] global_store_b64 v[8:9], v[13:14], off global_load_b128 v[13:16], v[6:7], off s_clause 0x1 global_load_b64 v[17:18], v[2:3], off offset:8 global_load_b64 v[19:20], v[2:3], off s_waitcnt vmcnt(1) v_mul_f64 v[21:22], v[15:16], v[17:18] v_mul_f64 v[17:18], v[13:14], v[17:18] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[13:14], v[13:14], v[19:20], -v[21:22] v_fma_f64 v[15:16], v[19:20], v[15:16], v[17:18] global_store_b128 v[6:7], v[13:16], off s_cbranch_scc1 .LBB1_145 .LBB1_146: ; %.loopexit v_lshlrev_b64 v[0:1], 3, v[56:57] s_mov_b32 s1, 0x400921fb s_mov_b32 s0, 0x54442d18 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[4:5], v[4:5], s[0:1] v_add_co_u32 v0, vcc_lo, s2, v0 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo global_load_b64 v[2:3], v[0:1], off s_waitcnt vmcnt(0) v_mul_f64 v[2:3], v[4:5], v[2:3] global_store_b64 v[0:1], v[2:3], off s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel CUDAlogkernel .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 8 .amdhsa_kernarg_size 312 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 1 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 117 .amdhsa_next_free_sgpr 54 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size CUDAlogkernel, .Lfunc_end1-CUDAlogkernel ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 11000 ; NumSgprs: 56 ; NumVgprs: 117 ; ScratchSize: 8 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 6 ; VGPRBlocks: 14 ; NumSGPRsForWavesPerEU: 56 ; NumVGPRsForWavesPerEU: 117 ; Occupancy: 12 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .type __unnamed_1,@object ; @0 .section .rodata,"a",@progbits .p2align 2, 0x0 __unnamed_1: .long 130054 ; 0x1fc06 .long 129546 ; 0x1fa0a .long 110114 ; 0x1ae22 .long 16288 ; 0x3fa0 .long 6 ; 0x6 .long 256 ; 0x100 .long 0 ; 0x0 .long 4195 ; 0x1063 .long 86927 ; 0x1538f .long 86758 ; 0x152e6 .long 73744 ; 0x12010 .long 10904 ; 0x2a98 .long 399 ; 0x18f .long 512 ; 0x200 .long 0 ; 0x0 .long 2804 ; 0xaf4 .long 65280 ; 0xff00 .long 64770 ; 0xfd02 .long 55054 ; 0xd70e .long 8192 ; 0x2000 .long 0 ; 0x0 .long 128 ; 0x80 .long 0 ; 0x0 .long 2107 ; 0x83b .long 43576 ; 0xaa38 .long 43406 ; 0xa98e .long 36895 ; 0x901f .long 5504 ; 0x1580 .long 56 ; 0x38 .long 256 ; 0x100 .long 0 ; 0x0 .long 1405 ; 0x57d .long 32703 ; 0x7fbf .long 32193 ; 0x7dc1 .long 27364 ; 0x6ae4 .long 4160 ; 0x1040 .long 63 ; 0x3f .long 64 ; 0x40 .long 0 ; 0x0 .long 1054 ; 0x41e .long 21816 ; 0x5538 .long 21646 ; 0x548e .long 18399 ; 0x47df .long 2816 ; 0xb00 .long 56 ; 0x38 .long 128 ; 0x80 .long 0 ; 0x0 .long 703 ; 0x2bf .long 16367 ; 0x3fef .long 15856 ; 0x3df0 .long 13477 ; 0x34a5 .long 2176 ; 0x880 .long 15 ; 0xf .long 32 ; 0x20 .long 32768 ; 0x8000 .long 527 ; 0x20f .long 10915 ; 0x2aa3 .long 10745 ; 0x29f9 .long 9133 ; 0x23ad .long 1472 ; 0x5c0 .long 35 ; 0x23 .long 64 ; 0x40 .long 0 ; 0x0 .long 352 ; 0x160 .long 8187 ; 0x1ffb .long 7676 ; 0x1dfc .long 6524 ; 0x197c .long 1280 ; 0x500 .long 11 ; 0xb .long 16 ; 0x10 .long 134219776 ; 0x8000800 .long 265 ; 0x109 .long 5459 ; 0x1553 .long 5289 ; 0x14a9 .long 4495 ; 0x118f .long 896 ; 0x380 .long 19 ; 0x13 .long 32 ; 0x20 .long 524288 ; 0x80000 .long 176 ; 0xb0 .long 4094 ; 0xffe .long 3583 ; 0xdff .long 3045 ; 0xbe5 .long 1024 ; 0x400 .long 6 ; 0x6 .long 8 ; 0x8 .long 1077952576 ; 0x40404040 .long 133 ; 0x85 .long 2730 ; 0xaaa .long 2560 ; 0xa00 .long 2176 ; 0x880 .long 512 ; 0x200 .long 10 ; 0xa .long 16 ; 0x10 .long 67109888 ; 0x4000400 .long 89 ; 0x59 .long 2047 ; 0x7ff .long 1536 ; 0x600 .long 1305 ; 0x519 .long 1024 ; 0x400 .long 3 ; 0x3 .long 4 ; 0x4 .long 2290649224 ; 0x88888888 .long 66 ; 0x42 .long 1365 ; 0x555 .long 1195 ; 0x4ab .long 1015 ; 0x3f7 .long 512 ; 0x200 .long 5 ; 0x5 .long 8 ; 0x8 .long 538976288 ; 0x20202020 .long 44 ; 0x2c .long 1023 ; 0x3ff .long 512 ; 0x200 .long 435 ; 0x1b3 .long 2048 ; 0x800 .long 1 ; 0x1 .long 2 ; 0x2 .long 2863311530 ; 0xaaaaaaaa .long 34 ; 0x22 .long 682 ; 0x2aa .long 512 ; 0x200 .long 435 ; 0x1b3 .long 2048 ; 0x800 .long 2 ; 0x2 .long 4 ; 0x4 .long 1145324612 ; 0x44444444 .long 35 ; 0x23 .size __unnamed_1, 512 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 8 .value_kind: by_value - .offset: 8 .size: 8 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .offset: 56 .size: 4 .value_kind: hidden_block_count_x - .offset: 60 .size: 4 .value_kind: hidden_block_count_y - .offset: 64 .size: 4 .value_kind: hidden_block_count_z - .offset: 68 .size: 2 .value_kind: hidden_group_size_x - .offset: 70 .size: 2 .value_kind: hidden_group_size_y - .offset: 72 .size: 2 .value_kind: hidden_group_size_z - .offset: 74 .size: 2 .value_kind: hidden_remainder_x - .offset: 76 .size: 2 .value_kind: hidden_remainder_y - .offset: 78 .size: 2 .value_kind: hidden_remainder_z - .offset: 96 .size: 8 .value_kind: hidden_global_offset_x - .offset: 104 .size: 8 .value_kind: hidden_global_offset_y - .offset: 112 .size: 8 .value_kind: hidden_global_offset_z - .offset: 120 .size: 2 .value_kind: hidden_grid_dims - .offset: 136 .size: 8 .value_kind: hidden_hostcall_buffer - .offset: 152 .size: 8 .value_kind: hidden_heap_v1 .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 312 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: CUDAlogkernel .private_segment_fixed_size: 8 .sgpr_count: 56 .sgpr_spill_count: 0 .symbol: CUDAlogkernel.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 117 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "3e69da85b16b9ef21dcc56e5ab86beaedb5d3b43.hip" .globl __device_stub__CUDAlogkernel # -- Begin function __device_stub__CUDAlogkernel .p2align 4, 0x90 .type __device_stub__CUDAlogkernel,@function __device_stub__CUDAlogkernel: # @__device_stub__CUDAlogkernel .cfi_startproc # %bb.0: subq $168, %rsp .cfi_def_cfa_offset 176 movsd %xmm0, 104(%rsp) movsd %xmm1, 96(%rsp) movl %edi, 12(%rsp) movq %rsi, 88(%rsp) movq %rdx, 80(%rsp) movq %rcx, 72(%rsp) movq %r8, 64(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) leaq 88(%rsp), %rax movq %rax, 136(%rsp) leaq 80(%rsp), %rax movq %rax, 144(%rsp) leaq 72(%rsp), %rax movq %rax, 152(%rsp) leaq 64(%rsp), %rax movq %rax, 160(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 112(%rsp), %r9 movl $CUDAlogkernel, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $184, %rsp .cfi_adjust_cfa_offset -184 retq .Lfunc_end0: .size __device_stub__CUDAlogkernel, .Lfunc_end0-__device_stub__CUDAlogkernel .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $CUDAlogkernel, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type CUDAlogkernel,@object # @CUDAlogkernel .section .rodata,"a",@progbits .globl CUDAlogkernel .p2align 3, 0x0 CUDAlogkernel: .quad __device_stub__CUDAlogkernel .size CUDAlogkernel, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "CUDAlogkernel" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __device_stub__CUDAlogkernel .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym CUDAlogkernel .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
45,840
6,760
170,628
1,814
115
code for sm_80 Function : _Z13heattransfer2PdS_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x174], PT ; @!P0 EXIT ; S2R R7, SR_CTAID.X ; IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x174] ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; S2R R0, SR_TID.X ; IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; ISETP.GT.U32.AND P0, PT, R15, 0x1, PT ; SHF.R.S32.HI R3, RZ, 0x1f, R15 ; LEA.HI R2, R4, c[0x0][0x170], RZ, 0x1 ; ISETP.GT.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; SHF.R.S32.HI R2, RZ, 0x1, R2 ; SEL R15, R15, 0x1, P0 ; SEL R33, R3, RZ, P0 ; IMAD R8, R2, c[0x0][0x170], R2 ; IADD3 R5, P2, R15, -0x1, RZ ; IMAD.WIDE R8, R8, R17, c[0x0][0x168] ; ISETP.GE.U32.AND P1, PT, R5, 0x3, PT ; IADD3 R5, R2, -0x1, RZ ; IMAD R3, R7, R4, c[0x0][0x170] ; IADD3.X R4, R33, -0x1, RZ, P2, !PT ; IMAD R0, R0, c[0x0][0x174], RZ ; IMAD R5, R5, c[0x0][0x170], R2 ; ISETP.GE.U32.AND.EX P0, PT, R4, RZ, PT, P1 ; IMAD R12, R7, c[0x0][0x170], R0 ; LOP3.LUT R4, R15, 0x3, RZ, 0xc0, !PT ; IMAD.IADD R14, R0, 0x1, R3 ; IMAD.WIDE R12, R12, R17, c[0x0][0x160] ; IMAD.WIDE R10, R14, R17, c[0x0][0x168] ; IMAD.WIDE R6, R5, R17, c[0x0][0x168] ; @!P0 BRA 0xe50 ; IADD3 R32, P0, R4, -R15, RZ ; IMAD.WIDE R14, R14, R17, c[0x0][0x160] ; IADD3 R16, R0, c[0x0][0x170], R3 ; IMAD.X R33, RZ, RZ, ~R33, P0 ; IMAD.WIDE R16, R16, R17, c[0x0][0x160] ; LDG.E.64 R30, [R12.64+0x8] ; LDG.E.64 R34, [R12.64] ; LDG.E.64 R26, [R12.64+0x10] ; LDG.E.64 R28, [R14.64] ; LDG.E.64 R2, [R14.64+0x8] ; LDG.E.64 R18, [R14.64+0x10] ; LDG.E.64 R20, [R16.64] ; LDG.E.64 R22, [R16.64+0x8] ; LDG.E.64 R24, [R16.64+0x10] ; BSSY B0, 0x4d0 ; DADD R34, R30, R34 ; MUFU.RCP64H R31, 9 ; IMAD.MOV.U32 R30, RZ, RZ, 0x1 ; DADD R26, R34, R26 ; DADD R28, R26, R28 ; IMAD.MOV.U32 R26, RZ, RZ, 0x0 ; IMAD.MOV.U32 R27, RZ, RZ, 0x40220000 ; DADD R2, R28, R2 ; DFMA R28, R30, -R26, 1 ; DADD R2, R2, R18 ; DFMA R28, R28, R28, R28 ; DADD R2, R2, R20 ; DFMA R28, R30, R28, R30 ; DADD R2, R2, R22 ; DFMA R26, R28, -R26, 1 ; DADD R22, R2, R24 ; DFMA R26, R28, R26, R28 ; DMUL R2, R22, R26 ; FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; DFMA R18, R2, -9, R22 ; DFMA R20, R26, R18, R2 ; FFMA R0, RZ, 2.53125, R21 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x4c0 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; MOV R0, 0x4c0 ; IMAD.MOV.U32 R21, RZ, RZ, 0x40220000 ; CALL.REL.NOINC 0x1230 ; BSYNC B0 ; IMAD.MOV.U32 R36, RZ, RZ, 0x0 ; STG.E.64 [R10.64+0x8], R20 ; IMAD.MOV.U32 R37, RZ, RZ, 0x408f4000 ; STG.E.64 [R6.64+-0x8], R36 ; STG.E.64 [R8.64+-0x8], R36 ; STG.E.64 [R6.64], R36 ; STG.E.64 [R8.64], R36 ; LDG.E.64 R30, [R12.64+0x8] ; LDG.E.64 R34, [R12.64] ; LDG.E.64 R26, [R12.64+0x10] ; LDG.E.64 R28, [R14.64] ; LDG.E.64 R2, [R14.64+0x8] ; LDG.E.64 R18, [R14.64+0x10] ; LDG.E.64 R20, [R16.64] ; LDG.E.64 R22, [R16.64+0x8] ; LDG.E.64 R24, [R16.64+0x10] ; BSSY B0, 0x7b0 ; DADD R34, R30, R34 ; MUFU.RCP64H R31, 9 ; IMAD.MOV.U32 R30, RZ, RZ, 0x1 ; DADD R26, R34, R26 ; DADD R28, R26, R28 ; IMAD.MOV.U32 R26, RZ, RZ, 0x0 ; MOV R27, 0x40220000 ; DADD R2, R28, R2 ; DFMA R28, R30, -R26, 1 ; DADD R2, R2, R18 ; DFMA R28, R28, R28, R28 ; DADD R2, R2, R20 ; DFMA R28, R30, R28, R30 ; DADD R2, R2, R22 ; DFMA R26, R28, -R26, 1 ; DADD R22, R2, R24 ; DFMA R26, R28, R26, R28 ; DMUL R2, R26, R22 ; FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; DFMA R18, R2, -9, R22 ; DFMA R20, R26, R18, R2 ; FFMA R0, RZ, 2.53125, R21 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7a0 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; MOV R0, 0x7a0 ; IMAD.MOV.U32 R21, RZ, RZ, 0x40220000 ; CALL.REL.NOINC 0x1230 ; BSYNC B0 ; IMAD.MOV.U32 R36, RZ, RZ, 0x0 ; STG.E.64 [R10.64+0x8], R20 ; IMAD.MOV.U32 R37, RZ, RZ, 0x408f4000 ; STG.E.64 [R6.64+-0x8], R36 ; STG.E.64 [R8.64+-0x8], R36 ; STG.E.64 [R6.64], R36 ; STG.E.64 [R8.64], R36 ; LDG.E.64 R30, [R12.64+0x8] ; LDG.E.64 R34, [R12.64] ; LDG.E.64 R26, [R12.64+0x10] ; LDG.E.64 R28, [R14.64] ; LDG.E.64 R2, [R14.64+0x8] ; LDG.E.64 R18, [R14.64+0x10] ; LDG.E.64 R20, [R16.64] ; LDG.E.64 R22, [R16.64+0x8] ; LDG.E.64 R24, [R16.64+0x10] ; BSSY B0, 0xa90 ; DADD R34, R30, R34 ; MUFU.RCP64H R31, 9 ; IMAD.MOV.U32 R30, RZ, RZ, 0x1 ; DADD R26, R34, R26 ; DADD R28, R26, R28 ; IMAD.MOV.U32 R26, RZ, RZ, 0x0 ; IMAD.MOV.U32 R27, RZ, RZ, 0x40220000 ; DADD R2, R28, R2 ; DFMA R28, R30, -R26, 1 ; DADD R2, R2, R18 ; DFMA R28, R28, R28, R28 ; DADD R2, R2, R20 ; DFMA R28, R30, R28, R30 ; DADD R2, R2, R22 ; DFMA R26, R28, -R26, 1 ; DADD R22, R2, R24 ; DFMA R26, R28, R26, R28 ; DMUL R2, R26, R22 ; FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; DFMA R18, R2, -9, R22 ; DFMA R20, R26, R18, R2 ; FFMA R0, RZ, 2.53125, R21 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xa80 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; MOV R0, 0xa80 ; IMAD.MOV.U32 R21, RZ, RZ, 0x40220000 ; CALL.REL.NOINC 0x1230 ; BSYNC B0 ; IMAD.MOV.U32 R36, RZ, RZ, 0x0 ; MOV R37, 0x408f4000 ; STG.E.64 [R10.64+0x8], R20 ; STG.E.64 [R6.64+-0x8], R36 ; STG.E.64 [R8.64+-0x8], R36 ; STG.E.64 [R6.64], R36 ; STG.E.64 [R8.64], R36 ; LDG.E.64 R30, [R12.64+0x8] ; LDG.E.64 R34, [R12.64] ; LDG.E.64 R26, [R12.64+0x10] ; LDG.E.64 R28, [R14.64] ; LDG.E.64 R2, [R14.64+0x8] ; LDG.E.64 R18, [R14.64+0x10] ; LDG.E.64 R20, [R16.64] ; LDG.E.64 R22, [R16.64+0x8] ; LDG.E.64 R24, [R16.64+0x10] ; BSSY B0, 0xd90 ; DADD R34, R30, R34 ; MUFU.RCP64H R31, 9 ; IMAD.MOV.U32 R30, RZ, RZ, 0x1 ; DADD R26, R34, R26 ; DADD R28, R26, R28 ; IMAD.MOV.U32 R26, RZ, RZ, 0x0 ; IMAD.MOV.U32 R27, RZ, RZ, 0x40220000 ; DADD R2, R28, R2 ; DFMA R28, R30, -R26, 1 ; DADD R2, R2, R18 ; DFMA R28, R28, R28, R28 ; DADD R2, R2, R20 ; DFMA R28, R30, R28, R30 ; DADD R2, R2, R22 ; DFMA R26, R28, -R26, 1 ; DADD R22, R2, R24 ; DFMA R26, R28, R26, R28 ; DMUL R2, R26, R22 ; FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; DFMA R18, R2, -9, R22 ; DFMA R2, R26, R18, R2 ; FFMA R0, RZ, 2.53125, R3 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xd80 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; MOV R0, 0xd60 ; IMAD.MOV.U32 R21, RZ, RZ, 0x40220000 ; CALL.REL.NOINC 0x1230 ; IMAD.MOV.U32 R2, RZ, RZ, R20 ; IMAD.MOV.U32 R3, RZ, RZ, R21 ; BSYNC B0 ; IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; IADD3 R32, P0, R32, 0x4, RZ ; IMAD.MOV.U32 R19, RZ, RZ, 0x408f4000 ; STG.E.64 [R10.64+0x8], R2 ; IMAD.X R33, RZ, RZ, R33, P0 ; STG.E.64 [R6.64+-0x8], R18 ; ISETP.NE.U32.AND P0, PT, R32, RZ, PT ; STG.E.64 [R8.64+-0x8], R18 ; ISETP.NE.AND.EX P0, PT, R33, RZ, PT, P0 ; STG.E.64 [R6.64], R18 ; STG.E.64 [R8.64], R18 ; @P0 BRA 0x260 ; ISETP.NE.U32.AND P0, PT, R4, RZ, PT ; ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; @!P0 EXIT ; IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; IADD3 R4, P0, RZ, -R4, RZ ; IMAD.WIDE R32, R15, c[0x0][0x170], R12 ; IADD3.X R16, RZ, -0x1, RZ, P0, !PT ; IMAD.WIDE R14, R15, c[0x0][0x170], R32 ; LDG.E.64 R30, [R12.64+0x8] ; LDG.E.64 R34, [R12.64] ; LDG.E.64 R28, [R12.64+0x10] ; LDG.E.64 R2, [R32.64] ; LDG.E.64 R18, [R32.64+0x8] ; LDG.E.64 R20, [R32.64+0x10] ; LDG.E.64 R22, [R14.64] ; LDG.E.64 R24, [R14.64+0x8] ; LDG.E.64 R26, [R14.64+0x10] ; BSSY B0, 0x1160 ; DADD R34, R30, R34 ; MUFU.RCP64H R31, 9 ; IMAD.MOV.U32 R30, RZ, RZ, 0x1 ; DADD R34, R34, R28 ; IMAD.MOV.U32 R28, RZ, RZ, 0x0 ; IMAD.MOV.U32 R29, RZ, RZ, 0x40220000 ; DADD R2, R34, R2 ; DFMA R34, R30, -R28, 1 ; DADD R2, R2, R18 ; DFMA R34, R34, R34, R34 ; DADD R2, R2, R20 ; DFMA R34, R30, R34, R30 ; DADD R2, R2, R22 ; DFMA R28, R34, -R28, 1 ; DADD R2, R2, R24 ; DFMA R28, R34, R28, R34 ; DADD R22, R2, R26 ; DMUL R2, R28, R22 ; FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; DFMA R18, R2, -9, R22 ; DFMA R2, R28, R18, R2 ; FFMA R0, RZ, 2.53125, R3 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1150 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; MOV R0, 0x1130 ; IMAD.MOV.U32 R21, RZ, RZ, 0x40220000 ; CALL.REL.NOINC 0x1230 ; IMAD.MOV.U32 R2, RZ, RZ, R20 ; IMAD.MOV.U32 R3, RZ, RZ, R21 ; BSYNC B0 ; IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; IADD3 R4, P0, R4, 0x1, RZ ; IMAD.MOV.U32 R19, RZ, RZ, 0x408f4000 ; STG.E.64 [R10.64+0x8], R2 ; IMAD.X R16, RZ, RZ, R16, P0 ; STG.E.64 [R6.64+-0x8], R18 ; ISETP.NE.U32.AND P0, PT, R4, RZ, PT ; STG.E.64 [R8.64+-0x8], R18 ; ISETP.NE.AND.EX P0, PT, R16, RZ, PT, P0 ; STG.E.64 [R6.64], R18 ; STG.E.64 [R8.64], R18 ; @P0 BRA 0xed0 ; EXIT ; FSETP.GEU.AND P0, PT, |R21|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R24, RZ, RZ, R22 ; LOP3.LUT R18, R21, 0x800fffff, RZ, 0xc0, !PT ; BSSY B1, 0x17c0 ; FSETP.GEU.AND P2, PT, |R23|, 1.469367938527859385e-39, PT ; LOP3.LUT R19, R18, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R18, RZ, RZ, R20 ; MOV R30, 0x1 ; LOP3.LUT R2, R23, 0x7ff00000, RZ, 0xc0, !PT ; LOP3.LUT R5, R21, 0x7ff00000, RZ, 0xc0, !PT ; @!P0 DMUL R18, R20, 8.98846567431157953865e+307 ; ISETP.GE.U32.AND P1, PT, R2.reuse, R5, PT ; @!P2 LOP3.LUT R3, R21, 0x7ff00000, RZ, 0xc0, !PT ; MUFU.RCP64H R31, R19 ; @!P2 ISETP.GE.U32.AND P3, PT, R2, R3, PT ; IMAD.MOV.U32 R3, RZ, RZ, 0x1ca00000 ; @!P0 LOP3.LUT R5, R19, 0x7ff00000, RZ, 0xc0, !PT ; @!P2 SEL R25, R3.reuse, 0x63400000, !P3 ; SEL R29, R3, 0x63400000, !P1 ; DFMA R26, R30, -R18, 1 ; DFMA R26, R26, R26, R26 ; DFMA R26, R30, R26, R30 ; @!P2 LOP3.LUT R30, R25, 0x80000000, R23.reuse, 0xf8, !PT ; LOP3.LUT R25, R29, 0x800fffff, R23, 0xf8, !PT ; @!P2 LOP3.LUT R31, R30, 0x100000, RZ, 0xfc, !PT ; DFMA R28, R26, -R18, 1 ; @!P2 IMAD.MOV.U32 R30, RZ, RZ, RZ ; DFMA R26, R26, R28, R26 ; @!P2 DFMA R24, R24, 2, -R30 ; DMUL R28, R26, R24 ; DFMA R30, R28, -R18, R24 ; DFMA R30, R26, R30, R28 ; IMAD.MOV.U32 R26, RZ, RZ, R2 ; @!P2 LOP3.LUT R26, R25, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R28, R5, -0x1, RZ ; IADD3 R27, R26, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R27, 0x7feffffe, PT ; ISETP.GT.U32.OR P0, PT, R28, 0x7feffffe, P0 ; @P0 BRA 0x1660 ; LOP3.LUT R23, R21, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R22, RZ, RZ, RZ ; ISETP.GE.U32.AND P0, PT, R2.reuse, R23, PT ; IMAD.IADD R5, R2, 0x1, -R23 ; SEL R2, R3, 0x63400000, !P0 ; IMNMX R5, R5, -0x46a00000, !PT ; IMNMX R5, R5, 0x46a00000, PT ; IMAD.IADD R5, R5, 0x1, -R2 ; IADD3 R23, R5, 0x7fe00000, RZ ; DMUL R2, R30, R22 ; FSETP.GTU.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; @P0 BRA 0x17b0 ; DFMA R18, R30, -R18, R24 ; IMAD.MOV.U32 R22, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R19.reuse, RZ, PT ; LOP3.LUT R21, R19, 0x80000000, R21, 0x48, !PT ; LOP3.LUT R23, R21, R23, RZ, 0xfc, !PT ; @!P0 BRA 0x17b0 ; IMAD.MOV R19, RZ, RZ, -R5 ; DMUL.RP R22, R30, R22 ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; IADD3 R5, -R5, -0x43300000, RZ ; DFMA R18, R2, -R18, R30 ; LOP3.LUT R21, R23, R21, RZ, 0x3c, !PT ; FSETP.NEU.AND P0, PT, |R19|, R5, PT ; FSEL R2, R22, R2, !P0 ; FSEL R3, R21, R3, !P0 ; BRA 0x17b0 ; DSETP.NAN.AND P0, PT, R22, R22, PT ; @P0 BRA 0x1790 ; DSETP.NAN.AND P0, PT, R20, R20, PT ; @P0 BRA 0x1760 ; ISETP.NE.AND P0, PT, R26, R5, PT ; IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; MOV R3, 0xfff80000 ; @!P0 BRA 0x17b0 ; ISETP.NE.AND P0, PT, R26, 0x7ff00000, PT ; LOP3.LUT R3, R23, 0x80000000, R21, 0x48, !PT ; ISETP.EQ.OR P0, PT, R5, RZ, !P0 ; @P0 LOP3.LUT R5, R3, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R2, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R2, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R3, RZ, RZ, R5 ; BRA 0x17b0 ; LOP3.LUT R3, R21, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R2, RZ, RZ, R20 ; BRA 0x17b0 ; LOP3.LUT R3, R23, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R2, RZ, RZ, R22 ; BSYNC B1 ; IMAD.MOV.U32 R20, RZ, RZ, R2 ; IMAD.MOV.U32 R21, RZ, RZ, R3 ; IMAD.MOV.U32 R2, RZ, RZ, R0 ; IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; RET.REL.NODEC R2 0x0 ; BRA 0x1810; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z12heattransferPdS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R5, SR_CTAID.X ; IMAD.MOV.U32 R23, RZ, RZ, 0x8 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R4, SR_TID.X ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; IMAD R22, R5, c[0x0][0x170], R4 ; IMAD.WIDE R22, R22, R23, c[0x0][0x160] ; LDG.E.64 R20, [R22.64] ; LDG.E.64 R18, [R22.64+0x8] ; IMAD.WIDE R24, R0, 0x8, R22 ; LDG.E.64 R14, [R22.64+0x10] ; LDG.E.64 R10, [R24.64] ; LDG.E.64 R16, [R24.64+0x8] ; IMAD.WIDE R26, R0, 0x8, R24 ; LDG.E.64 R12, [R24.64+0x10] ; LDG.E.64 R8, [R26.64] ; LDG.E.64 R6, [R26.64+0x8] ; LDG.E.64 R2, [R26.64+0x10] ; IMAD R5, R5, R0, c[0x0][0x170] ; BSSY B0, 0x330 ; IMAD.IADD R4, R5, 0x1, R4 ; DADD R20, R20, R18 ; MUFU.RCP64H R19, 9 ; IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; DADD R20, R20, R14 ; IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; IMAD.MOV.U32 R15, RZ, RZ, 0x40220000 ; DADD R10, R20, R10 ; DFMA R20, R18, -R14, 1 ; DADD R10, R10, R16 ; DFMA R20, R20, R20, R20 ; DADD R10, R10, R12 ; DFMA R20, R18, R20, R18 ; DADD R8, R10, R8 ; DFMA R14, R20, -R14, 1 ; DADD R6, R8, R6 ; DFMA R14, R20, R14, R20 ; DADD R6, R6, R2 ; DMUL R2, R6, R14 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; DFMA R8, R2, -9, R6 ; DFMA R2, R14, R8, R2 ; FFMA R8, RZ, 2.53125, R3 ; FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x320 ; MOV R0, 0x300 ; CALL.REL.NOINC 0x450 ; IMAD.MOV.U32 R2, RZ, RZ, R12 ; MOV R3, R13 ; BSYNC B0 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; LEA.HI R0, R0, c[0x0][0x170], RZ, 0x1 ; IMAD.MOV.U32 R11, RZ, RZ, 0x408f4000 ; SHF.R.S32.HI R0, RZ, 0x1, R0 ; IADD3 R5, R0.reuse, -0x1, RZ ; IMAD R8, R0, c[0x0][0x170], R0 ; IMAD R6, R5, c[0x0][0x170], R0 ; IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; IMAD.WIDE R6, R6, R9.reuse, c[0x0][0x168] ; STG.E.64 [R4.64+0x8], R2 ; IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; STG.E.64 [R6.64+-0x8], R10 ; STG.E.64 [R8.64+-0x8], R10 ; STG.E.64 [R6.64], R10 ; STG.E.64 [R8.64], R10 ; EXIT ; IMAD.MOV.U32 R3, RZ, RZ, 0x3ff20000 ; HFMA2.MMA R8, -RZ, RZ, 0, 5.9604644775390625e-08 ; IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; FSETP.GEU.AND P1, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; MUFU.RCP64H R9, R3 ; LOP3.LUT R5, R7, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; BSSY B1, 0x910 ; IMAD.MOV.U32 R19, RZ, RZ, 0x40200000 ; ISETP.GE.U32.AND P0, PT, R5, 0x40200000, PT ; IMAD.MOV.U32 R18, RZ, RZ, R5 ; SEL R13, R13, 0x63400000, !P0 ; IADD3 R20, R19, -0x1, RZ ; @!P1 LOP3.LUT R12, R13, 0x80000000, R7, 0xf8, !PT ; DFMA R10, R8, -R2, 1 ; DFMA R10, R10, R10, R10 ; DFMA R14, R8, R10, R8 ; LOP3.LUT R9, R13, 0x800fffff, R7, 0xf8, !PT ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; @!P1 LOP3.LUT R11, R12, 0x100000, RZ, 0xfc, !PT ; @!P1 IMAD.MOV.U32 R10, RZ, RZ, RZ ; DFMA R16, R14, -R2, 1 ; @!P1 DFMA R8, R8, 2, -R10 ; DFMA R16, R14, R16, R14 ; @!P1 LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; DMUL R10, R16, R8 ; IADD3 R12, R18, -0x1, RZ ; DFMA R14, R10, -R2, R8 ; ISETP.GT.U32.AND P0, PT, R12, 0x7feffffe, PT ; ISETP.GT.U32.OR P0, PT, R20, 0x7feffffe, P0 ; DFMA R10, R16, R14, R10 ; @P0 BRA 0x7f0 ; IADD3 R5, R5, -0x40200000, RZ ; IMNMX R5, R5, -0x46a00000, !PT ; IMNMX R6, R5, 0x46a00000, PT ; IMAD.IADD R5, R6, 0x1, -R13 ; MOV R6, RZ ; IADD3 R7, R5, 0x7fe00000, RZ ; DMUL R12, R10, R6 ; FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; @P0 BRA 0x900 ; DFMA R2, R10, -R2, R8 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; LOP3.LUT R2, R3, 0x40220000, RZ, 0x3c, !PT ; LOP3.LUT R9, R2, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; @!P0 BRA 0x900 ; IMAD.MOV R3, RZ, RZ, -R5 ; DMUL.RP R6, R10, R6 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IADD3 R5, -R5, -0x43300000, RZ ; DFMA R2, R12, -R2, R10 ; LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; FSETP.NEU.AND P0, PT, |R3|, R5, PT ; FSEL R12, R6, R12, !P0 ; FSEL R13, R9, R13, !P0 ; BRA 0x900 ; DSETP.NAN.AND P0, PT, R6, R6, PT ; @P0 BRA 0x8e0 ; ISETP.NE.AND P0, PT, R18, R19, PT ; IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; @!P0 BRA 0x900 ; ISETP.NE.AND P0, PT, R18, 0x7ff00000, PT ; LOP3.LUT R6, R7, 0x40220000, RZ, 0x3c, !PT ; ISETP.EQ.OR P0, PT, R19, RZ, !P0 ; LOP3.LUT R13, R6, 0x80000000, RZ, 0xc0, !PT ; @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; @P0 MOV R12, RZ ; @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; BRA 0x900 ; LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R12, RZ, RZ, R6 ; BSYNC B1 ; IMAD.MOV.U32 R2, RZ, RZ, R0 ; IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; RET.REL.NODEC R2 0x0 ; BRA 0x940; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0006fab8_00000000-6_87985bde40e8cd79a2616bbc317207b4e2bb41d8.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3953: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3953: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z13array_processPdS_ii .type _Z13array_processPdS_ii, @function _Z13array_processPdS_ii: .LFB3949: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 movl %ecx, -28(%rsp) testl %ecx, %ecx jle .L3 movq %rsi, %r8 movl %edx, %r10d movl %edx, %eax shrl $31, %eax addl %edx, %eax sarl %eax leal -1(%rax), %ecx movl %ecx, %edx imull %r10d, %edx leal (%rcx,%rdx), %r13d movslq %r13d, %r13 salq $3, %r13 leal (%rdx,%r10), %esi addl %esi, %ecx movslq %ecx, %rcx leaq 0(,%rcx,8), %r14 addl %eax, %edx movslq %edx, %rdx leaq 0(,%rdx,8), %r15 addl %esi, %eax cltq salq $3, %rax movq %rax, -40(%rsp) movslq %r10d, %rbp leaq 0(,%rbp,8), %r11 leal -3(%r10), %eax salq $4, %rbp movl $0, %edx leaq 8(,%rax,8), %rax movq %rax, -8(%rsp) leal -1(%r10), %r12d movsd .LC0(%rip), %xmm1 movsd .LC1(%rip), %xmm2 movq %r13, -24(%rsp) movq %r14, -16(%rsp) movl %r10d, %ebx jmp .L5 .L8: leaq (%rax,%rbp), %r14 leaq (%rax,%r13), %rcx movq %r14, %rsi .L6: movsd (%rax), %xmm0 addsd 8(%rax), %xmm0 addsd 16(%rax), %xmm0 addsd (%rdi,%rcx), %xmm0 addsd 8(%rdi,%rcx), %xmm0 addsd 16(%rdi,%rcx), %xmm0 addsd (%rsi), %xmm0 addsd 8(%rsi), %xmm0 addsd 16(%rsi), %xmm0 divsd %xmm1, %xmm0 movsd %xmm0, 8(%r8,%rcx) addq $8, %rax addq $8, %rsi addq $8, %rcx cmpq %r9, %rax jne .L6 addl $1, %r10d movq %r14, %rax subq %r11, %rax addq %r11, %r9 cmpl %r12d, %r10d jne .L8 .L7: movq -24(%rsp), %rax movsd %xmm2, (%r8,%rax) movq -16(%rsp), %rax movsd %xmm2, (%r8,%rax) movsd %xmm2, (%r8,%r15) movq -40(%rsp), %rax movsd %xmm2, (%r8,%rax) addl $1, %edx movq %r8, %rax movq %rdi, %r8 cmpl %edx, -28(%rsp) je .L3 movq %rax, %rdi .L5: cmpl $2, %ebx jle .L7 movq %rdi, %rax movq -8(%rsp), %rsi leaq (%rsi,%rdi), %r9 movq %r11, %r13 subq %rdi, %r13 movl $1, %r10d jmp .L8 .L3: popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3949: .size _Z13array_processPdS_ii, .-_Z13array_processPdS_ii .globl _Z35__device_stub__Z12heattransferPdS_iPdS_i .type _Z35__device_stub__Z12heattransferPdS_iPdS_i, @function _Z35__device_stub__Z12heattransferPdS_iPdS_i: .LFB3975: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L16 .L12: movq 120(%rsp), %rax subq %fs:40, %rax jne .L17 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L16: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z12heattransferPdS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L12 .L17: call __stack_chk_fail@PLT .cfi_endproc .LFE3975: .size _Z35__device_stub__Z12heattransferPdS_iPdS_i, .-_Z35__device_stub__Z12heattransferPdS_iPdS_i .globl _Z12heattransferPdS_i .type _Z12heattransferPdS_i, @function _Z12heattransferPdS_i: .LFB3976: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z12heattransferPdS_iPdS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3976: .size _Z12heattransferPdS_i, .-_Z12heattransferPdS_i .section .rodata.str1.1,"aMS",@progbits,1 .LC2: .string "Host to Device MemCpy takes " .LC4: .string "s" .LC5: .string "Computation takes " .LC6: .string "Device to Host MemCpy takes " .text .globl _Z17GPU_array_processPdS_ii .type _Z17GPU_array_processPdS_ii, @function _Z17GPU_array_processPdS_ii: .LFB3950: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $120, %rsp .cfi_def_cfa_offset 176 movq %rdi, %r12 movq %rsi, 8(%rsp) movl %edx, %ebp movl %ecx, %r14d movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 16(%rsp), %rdi call cudaEventCreate@PLT leaq 24(%rsp), %rdi call cudaEventCreate@PLT leaq 48(%rsp), %rdi call cudaEventCreate@PLT leaq 56(%rsp), %rdi call cudaEventCreate@PLT leaq 32(%rsp), %rdi call cudaEventCreate@PLT leaq 40(%rsp), %rdi call cudaEventCreate@PLT movl %ebp, %ebx imull %ebp, %ebx movslq %ebx, %rbx salq $3, %rbx leaq 64(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT testl %eax, %eax je .L46 .L20: movq 104(%rsp), %rax subq %fs:40, %rax jne .L47 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L46: .cfi_restore_state leaq 72(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT testl %eax, %eax jne .L48 movl $0, %esi movq 16(%rsp), %rdi call cudaEventRecord@PLT movl $1, %ecx movq %rbx, %rdx movq %r12, %rsi movq 64(%rsp), %rdi call cudaMemcpy@PLT testl %eax, %eax jne .L49 movl $0, %esi movq 24(%rsp), %rdi call cudaEventRecord@PLT movq 24(%rsp), %rdi call cudaEventSynchronize@PLT movl $0, %esi movq 32(%rsp), %rdi call cudaEventRecord@PLT movslq %r14d, %r15 testl %r14d, %r14d je .L24 leal -2(%rbp), %r13d movl $0, %r12d jmp .L26 .L48: movq 64(%rsp), %rdi call cudaFree@PLT jmp .L20 .L49: movq 64(%rsp), %rdi call cudaFree@PLT movq 72(%rsp), %rdi call cudaFree@PLT jmp .L20 .L25: movq 64(%rsp), %rax movq 72(%rsp), %rdx movq %rdx, 64(%rsp) movq %rax, 72(%rsp) addq $1, %r12 cmpq %r15, %r12 je .L50 .L26: movl %r13d, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) movl %r13d, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $0, %r9d movl $0, %r8d movq 92(%rsp), %rdx movl $1, %ecx movq 80(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L25 movl %ebp, %edx movq 72(%rsp), %rsi movq 64(%rsp), %rdi call _Z35__device_stub__Z12heattransferPdS_iPdS_i jmp .L25 .L50: movl $0, %esi movq 40(%rsp), %rdi call cudaEventRecord@PLT movq 40(%rsp), %rdi call cudaEventSynchronize@PLT movl $0, %esi movq 48(%rsp), %rdi call cudaEventRecord@PLT testb $1, %r14b je .L42 movl $2, %ecx movq %rbx, %rdx movq 72(%rsp), %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT jmp .L28 .L54: movq 104(%rsp), %rax subq %fs:40, %rax jne .L51 call _ZSt16__throw_bad_castv@PLT .L51: call __stack_chk_fail@PLT .L31: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L32 .L55: movq 104(%rsp), %rax subq %fs:40, %rax jne .L52 call _ZSt16__throw_bad_castv@PLT .L52: call __stack_chk_fail@PLT .L35: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L36 .L56: movq 104(%rsp), %rax subq %fs:40, %rax jne .L53 call _ZSt16__throw_bad_castv@PLT .L53: call __stack_chk_fail@PLT .L39: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L40 .L24: movl $0, %esi movq 40(%rsp), %rdi call cudaEventRecord@PLT movq 40(%rsp), %rdi call cudaEventSynchronize@PLT movl $0, %esi movq 48(%rsp), %rdi call cudaEventRecord@PLT .L42: movl $2, %ecx movq %rbx, %rdx movq 64(%rsp), %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT .L28: movl $0, %esi movq 56(%rsp), %rdi call cudaEventRecord@PLT movq 56(%rsp), %rdi call cudaEventSynchronize@PLT movq 64(%rsp), %rdi call cudaFree@PLT movq 72(%rsp), %rdi call cudaFree@PLT leaq 92(%rsp), %rdi movq 24(%rsp), %rdx movq 16(%rsp), %rsi call cudaEventElapsedTime@PLT movl $28, %edx leaq .LC2(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq $4, 8(%rbx,%rax) movss 92(%rsp), %xmm0 divss .LC3(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movq %rbx, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rbx movl $1, %edx leaq .LC4(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L54 cmpb $0, 56(%rbp) je .L31 movzbl 67(%rbp), %esi .L32: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT leaq 92(%rsp), %rdi movq 40(%rsp), %rdx movq 32(%rsp), %rsi call cudaEventElapsedTime@PLT movl $18, %edx leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq $4, 8(%rbx,%rax) movss 92(%rsp), %xmm0 divss .LC3(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movq %rbx, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rbx movl $1, %edx leaq .LC4(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L55 cmpb $0, 56(%rbp) je .L35 movzbl 67(%rbp), %esi .L36: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT leaq 92(%rsp), %rdi movq 56(%rsp), %rdx movq 48(%rsp), %rsi call cudaEventElapsedTime@PLT movl $28, %edx leaq .LC6(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq $4, 8(%rbx,%rax) movss 92(%rsp), %xmm0 divss .LC3(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movq %rbx, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rbx movl $1, %edx leaq .LC4(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L56 cmpb $0, 56(%rbp) je .L39 movzbl 67(%rbp), %esi .L40: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT jmp .L20 .L47: call __stack_chk_fail@PLT .cfi_endproc .LFE3950: .size _Z17GPU_array_processPdS_ii, .-_Z17GPU_array_processPdS_ii .globl _Z37__device_stub__Z13heattransfer2PdS_iiPdS_ii .type _Z37__device_stub__Z13heattransfer2PdS_iiPdS_ii, @function _Z37__device_stub__Z13heattransfer2PdS_iiPdS_ii: .LFB3977: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L61 .L57: movq 136(%rsp), %rax subq %fs:40, %rax jne .L62 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L61: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z13heattransfer2PdS_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L57 .L62: call __stack_chk_fail@PLT .cfi_endproc .LFE3977: .size _Z37__device_stub__Z13heattransfer2PdS_iiPdS_ii, .-_Z37__device_stub__Z13heattransfer2PdS_iiPdS_ii .globl _Z13heattransfer2PdS_ii .type _Z13heattransfer2PdS_ii, @function _Z13heattransfer2PdS_ii: .LFB3978: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z37__device_stub__Z13heattransfer2PdS_iiPdS_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3978: .size _Z13heattransfer2PdS_ii, .-_Z13heattransfer2PdS_ii .section .rodata.str1.1 .LC7: .string "_Z13heattransfer2PdS_ii" .LC8: .string "_Z12heattransferPdS_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3980: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _Z13heattransfer2PdS_ii(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC8(%rip), %rdx movq %rdx, %rcx leaq _Z12heattransferPdS_i(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3980: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC0: .long 0 .long 1075970048 .align 8 .LC1: .long 0 .long 1083129856 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC3: .long 1148846080 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z12heattransferPdS_i ; -- Begin function _Z12heattransferPdS_i .globl _Z12heattransferPdS_i .p2align 8 .type _Z12heattransferPdS_i,@function _Z12heattransferPdS_i: ; @_Z12heattransferPdS_i ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x10 s_load_b128 s[0:3], s[0:1], 0x0 v_add_nc_u32_e32 v17, 1, v0 s_mov_b32 s9, 0x408f4000 s_mov_b32 s8, 0 v_add_nc_u32_e32 v19, 2, v0 s_waitcnt lgkmcnt(0) s_mul_i32 s5, s15, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1) v_add_nc_u32_e32 v1, s5, v0 v_add_nc_u32_e32 v3, s5, v17 v_add_nc_u32_e32 v5, s5, v19 s_add_i32 s5, s15, 1 s_mul_i32 s5, s5, s4 v_ashrrev_i32_e32 v2, 31, v1 v_ashrrev_i32_e32 v4, 31, v3 v_ashrrev_i32_e32 v6, 31, v5 v_add_nc_u32_e32 v7, s5, v0 v_add_nc_u32_e32 v9, s5, v17 v_lshlrev_b64 v[1:2], 3, v[1:2] v_lshlrev_b64 v[3:4], 3, v[3:4] v_lshlrev_b64 v[5:6], 3, v[5:6] v_ashrrev_i32_e32 v8, 31, v7 v_ashrrev_i32_e32 v10, 31, v9 v_add_nc_u32_e32 v13, s5, v19 v_add_co_u32 v1, vcc_lo, s0, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo v_add_co_u32 v3, vcc_lo, s0, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo s_clause 0x1 global_load_b64 v[1:2], v[1:2], off global_load_b64 v[3:4], v[3:4], off v_add_co_u32 v5, vcc_lo, s0, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo v_lshlrev_b64 v[7:8], 3, v[7:8] v_lshlrev_b64 v[9:10], 3, v[9:10] v_ashrrev_i32_e32 v14, 31, v13 global_load_b64 v[5:6], v[5:6], off s_add_i32 s5, s15, 2 v_add_co_u32 v7, vcc_lo, s0, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo v_add_co_u32 v11, vcc_lo, s0, v9 v_add_co_ci_u32_e32 v12, vcc_lo, s1, v10, vcc_lo global_load_b64 v[7:8], v[7:8], off v_lshlrev_b64 v[13:14], 3, v[13:14] s_mul_i32 s5, s5, s4 global_load_b64 v[11:12], v[11:12], off v_add_nc_u32_e32 v15, s5, v0 v_add_nc_u32_e32 v17, s5, v17 v_add_nc_u32_e32 v19, s5, v19 v_add_co_u32 v13, vcc_lo, s0, v13 v_add_co_ci_u32_e32 v14, vcc_lo, s1, v14, vcc_lo v_ashrrev_i32_e32 v16, 31, v15 v_ashrrev_i32_e32 v18, 31, v17 v_ashrrev_i32_e32 v20, 31, v19 global_load_b64 v[13:14], v[13:14], off v_lshlrev_b64 v[15:16], 3, v[15:16] v_lshlrev_b64 v[17:18], 3, v[17:18] v_lshlrev_b64 v[19:20], 3, v[19:20] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v15, vcc_lo, s0, v15 v_add_co_ci_u32_e32 v16, vcc_lo, s1, v16, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v17, vcc_lo, s0, v17 v_add_co_ci_u32_e32 v18, vcc_lo, s1, v18, vcc_lo global_load_b64 v[15:16], v[15:16], off v_add_co_u32 v19, vcc_lo, s0, v19 global_load_b64 v[17:18], v[17:18], off v_add_co_ci_u32_e32 v20, vcc_lo, s1, v20, vcc_lo s_lshr_b32 s0, s4, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_add_i32 s0, s4, s0 global_load_b64 v[19:20], v[19:20], off s_ashr_i32 s10, s0, 1 s_add_i32 s5, s10, -1 s_mul_i32 s11, s10, s4 s_mul_i32 s6, s5, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s0, s6, s5 s_ashr_i32 s1, s0, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[0:1], s[0:1], 3 s_add_u32 s0, s2, s0 s_addc_u32 s1, s3, s1 s_add_i32 s4, s11, s5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_ashr_i32 s5, s4, 31 s_lshl_b64 s[4:5], s[4:5], 3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_add_u32 s4, s2, s4 s_addc_u32 s5, s3, s5 s_add_i32 s6, s6, s10 s_ashr_i32 s7, s6, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[6:7], s[6:7], 3 s_add_u32 s6, s2, s6 s_addc_u32 s7, s3, s7 s_add_i32 s10, s11, s10 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_ashr_i32 s11, s10, 31 s_waitcnt vmcnt(7) v_add_f64 v[0:1], v[1:2], v[3:4] s_waitcnt vmcnt(6) v_add_f64 v[0:1], v[0:1], v[5:6] s_waitcnt vmcnt(5) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[0:1], v[0:1], v[7:8] s_waitcnt vmcnt(4) v_add_f64 v[0:1], v[0:1], v[11:12] s_waitcnt vmcnt(3) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[0:1], v[0:1], v[13:14] s_waitcnt vmcnt(2) v_add_f64 v[0:1], v[0:1], v[15:16] s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[0:1], v[0:1], v[17:18] s_waitcnt vmcnt(0) v_add_f64 v[0:1], v[0:1], v[19:20] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f64 v[2:3], null, 0x40220000, 0x40220000, v[0:1] v_div_scale_f64 v[11:12], vcc_lo, v[0:1], 0x40220000, v[0:1] v_rcp_f64_e32 v[4:5], v[2:3] s_waitcnt_depctr 0xfff v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] v_mul_f64 v[6:7], v[11:12], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[2:3], -v[2:3], v[6:7], v[11:12] v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] v_add_co_u32 v4, vcc_lo, s2, v9 v_add_co_ci_u32_e32 v5, vcc_lo, s3, v10, vcc_lo v_mov_b32_e32 v6, 0 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_div_fixup_f64 v[0:1], v[2:3], 0x40220000, v[0:1] v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9 s_lshl_b64 s[8:9], s[10:11], 3 s_add_u32 s2, s2, s8 s_addc_u32 s3, s3, s9 s_clause 0x4 global_store_b64 v[4:5], v[0:1], off global_store_b64 v6, v[2:3], s[0:1] global_store_b64 v6, v[2:3], s[4:5] global_store_b64 v6, v[2:3], s[6:7] global_store_b64 v6, v[2:3], s[2:3] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12heattransferPdS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 20 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 21 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z12heattransferPdS_i, .Lfunc_end0-_Z12heattransferPdS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 844 ; NumSgprs: 18 ; NumVgprs: 21 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 21 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z13heattransfer2PdS_ii ; -- Begin function _Z13heattransfer2PdS_ii .globl _Z13heattransfer2PdS_ii .p2align 8 .type _Z13heattransfer2PdS_ii,@function _Z13heattransfer2PdS_ii: ; @_Z13heattransfer2PdS_ii ; %bb.0: s_load_b32 s4, s[0:1], 0x14 s_mov_b32 s6, 0 s_waitcnt lgkmcnt(0) s_cmp_eq_u32 s4, 0 s_cbranch_scc1 .LBB1_3 ; %bb.1: ; %.lr.ph s_load_b32 s7, s[0:1], 0x10 v_mul_lo_u32 v12, v0, s4 s_load_b128 s[0:3], s[0:1], 0x0 s_add_i32 s8, s15, 1 s_ashr_i32 s5, s4, 31 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v20, 0 :: v_dual_add_nc_u32 v13, 1, v12 v_add_nc_u32_e32 v16, 2, v12 s_waitcnt lgkmcnt(0) s_mul_i32 s9, s15, s7 s_mul_i32 s8, s8, s7 v_add_nc_u32_e32 v0, s9, v12 v_add_nc_u32_e32 v2, s9, v13 v_add_nc_u32_e32 v4, s9, v16 v_add_nc_u32_e32 v6, s8, v12 v_add_nc_u32_e32 v8, s8, v13 v_ashrrev_i32_e32 v1, 31, v0 v_ashrrev_i32_e32 v3, 31, v2 v_add_nc_u32_e32 v10, s8, v16 s_lshr_b32 s8, s7, 31 v_ashrrev_i32_e32 v5, 31, v4 v_lshlrev_b64 v[0:1], 3, v[0:1] s_add_i32 s8, s7, s8 v_lshlrev_b64 v[2:3], 3, v[2:3] v_ashrrev_i32_e32 v7, 31, v6 s_add_i32 s9, s15, 2 s_ashr_i32 s14, s8, 1 v_lshlrev_b64 v[4:5], 3, v[4:5] v_add_co_u32 v0, vcc_lo, s0, v0 s_mul_i32 s10, s9, s7 s_add_i32 s11, s14, -1 v_ashrrev_i32_e32 v9, 31, v8 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo v_add_nc_u32_e32 v12, s10, v12 s_mul_i32 s12, s11, s7 v_lshlrev_b64 v[6:7], 3, v[6:7] v_add_co_u32 v2, vcc_lo, s0, v2 v_ashrrev_i32_e32 v11, 31, v10 s_add_i32 s8, s12, s11 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo v_add_nc_u32_e32 v14, s10, v13 v_lshlrev_b64 v[18:19], 3, v[8:9] v_add_co_u32 v4, vcc_lo, s0, v4 s_ashr_i32 s9, s8, 31 v_ashrrev_i32_e32 v13, 31, v12 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo s_lshl_b64 s[8:9], s[8:9], 3 v_add_nc_u32_e32 v16, s10, v16 v_add_co_u32 v6, vcc_lo, s0, v6 v_lshlrev_b64 v[10:11], 3, v[10:11] s_mul_i32 s7, s14, s7 v_ashrrev_i32_e32 v15, 31, v14 s_add_u32 s8, s2, s8 v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo s_addc_u32 s9, s3, s9 s_add_i32 s10, s7, s11 v_add_co_u32 v8, vcc_lo, s0, v18 v_lshlrev_b64 v[12:13], 3, v[12:13] s_ashr_i32 s11, s10, 31 v_ashrrev_i32_e32 v17, 31, v16 v_add_co_ci_u32_e32 v9, vcc_lo, s1, v19, vcc_lo v_add_co_u32 v10, vcc_lo, s0, v10 v_lshlrev_b64 v[14:15], 3, v[14:15] s_lshl_b64 s[10:11], s[10:11], 3 v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo s_add_u32 s10, s2, s10 s_addc_u32 s11, s3, s11 s_add_i32 s12, s12, s14 v_add_co_u32 v12, vcc_lo, s0, v12 v_lshlrev_b64 v[16:17], 3, v[16:17] v_add_co_ci_u32_e32 v13, vcc_lo, s1, v13, vcc_lo s_ashr_i32 s13, s12, 31 v_add_co_u32 v14, vcc_lo, s0, v14 s_lshl_b64 s[12:13], s[12:13], 3 v_add_co_ci_u32_e32 v15, vcc_lo, s1, v15, vcc_lo s_add_u32 s12, s2, s12 v_add_co_u32 v16, vcc_lo, s0, v16 s_addc_u32 s13, s3, s13 s_add_i32 s14, s7, s14 v_add_co_ci_u32_e32 v17, vcc_lo, s1, v17, vcc_lo s_ashr_i32 s15, s14, 31 v_add_co_u32 v18, vcc_lo, s2, v18 v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo s_lshl_b64 s[0:1], s[14:15], 3 s_mov_b32 s7, 0x408f4000 s_add_u32 s0, s2, s0 s_addc_u32 s1, s3, s1 .LBB1_2: ; =>This Inner Loop Header: Depth=1 s_clause 0x8 global_load_b64 v[21:22], v[0:1], off global_load_b64 v[23:24], v[2:3], off global_load_b64 v[25:26], v[4:5], off global_load_b64 v[27:28], v[6:7], off global_load_b64 v[29:30], v[8:9], off global_load_b64 v[31:32], v[10:11], off global_load_b64 v[33:34], v[12:13], off global_load_b64 v[35:36], v[14:15], off global_load_b64 v[37:38], v[16:17], off s_add_u32 s4, s4, -1 s_addc_u32 s5, s5, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_cmp_eq_u64 s[4:5], 0 s_waitcnt vmcnt(7) v_add_f64 v[21:22], v[21:22], v[23:24] s_waitcnt vmcnt(6) v_add_f64 v[21:22], v[21:22], v[25:26] s_waitcnt vmcnt(5) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[21:22], v[21:22], v[27:28] s_waitcnt vmcnt(4) v_add_f64 v[21:22], v[21:22], v[29:30] s_waitcnt vmcnt(3) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[21:22], v[21:22], v[31:32] s_waitcnt vmcnt(2) v_add_f64 v[21:22], v[21:22], v[33:34] s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[21:22], v[21:22], v[35:36] s_waitcnt vmcnt(0) v_add_f64 v[21:22], v[21:22], v[37:38] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f64 v[23:24], null, 0x40220000, 0x40220000, v[21:22] v_div_scale_f64 v[29:30], vcc_lo, v[21:22], 0x40220000, v[21:22] v_rcp_f64_e32 v[25:26], v[23:24] s_waitcnt_depctr 0xfff v_fma_f64 v[27:28], -v[23:24], v[25:26], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[25:26], v[25:26], v[27:28], v[25:26] v_fma_f64 v[27:28], -v[23:24], v[25:26], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[25:26], v[25:26], v[27:28], v[25:26] v_mul_f64 v[27:28], v[29:30], v[25:26] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], -v[23:24], v[27:28], v[29:30] v_div_fmas_f64 v[23:24], v[23:24], v[25:26], v[27:28] s_delay_alu instid0(VALU_DEP_1) v_div_fixup_f64 v[21:22], v[23:24], 0x40220000, v[21:22] v_dual_mov_b32 v24, s7 :: v_dual_mov_b32 v23, s6 s_clause 0x4 global_store_b64 v[18:19], v[21:22], off global_store_b64 v20, v[23:24], s[8:9] global_store_b64 v20, v[23:24], s[10:11] global_store_b64 v20, v[23:24], s[12:13] global_store_b64 v20, v[23:24], s[0:1] s_cbranch_scc0 .LBB1_2 .LBB1_3: ; %._crit_edge s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13heattransfer2PdS_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 39 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z13heattransfer2PdS_ii, .Lfunc_end1-_Z13heattransfer2PdS_ii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 856 ; NumSgprs: 18 ; NumVgprs: 39 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 4 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 39 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 20 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12heattransferPdS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z12heattransferPdS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 21 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13heattransfer2PdS_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13heattransfer2PdS_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 39 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "87985bde40e8cd79a2616bbc317207b4e2bb41d8.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function _Z13array_processPdS_ii .LCPI0_0: .quad 0x4022000000000000 # double 9 .text .globl _Z13array_processPdS_ii .p2align 4, 0x90 .type _Z13array_processPdS_ii,@function _Z13array_processPdS_ii: # @_Z13array_processPdS_ii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 # kill: def $edx killed $edx def $rdx movq %rdx, -48(%rsp) # 8-byte Spill movl %ecx, -52(%rsp) # 4-byte Spill testl %ecx, %ecx jle .LBB0_8 # %bb.1: # %.preheader72.lr.ph movq -48(%rsp), %r10 # 8-byte Reload leal -1(%r10), %eax movl %r10d, %ecx shrl $31, %ecx addl %r10d, %ecx sarl %ecx leal -1(%rcx), %edx imull %r10d, %edx leal (%rdx,%rcx), %r8d decl %r8d movslq %r8d, %r8 movq %r8, -8(%rsp) # 8-byte Spill movl %ecx, %r8d imull %r10d, %r8d leal (%r8,%rcx), %r9d decl %r9d movslq %r9d, %r9 movq %r9, -16(%rsp) # 8-byte Spill addl %ecx, %edx movslq %edx, %rdx addl %ecx, %r8d movslq %r8d, %r11 movslq %r10d, %rcx leaq (,%rcx,8), %rbx leaq 8(,%rcx,8), %r8 movq %r8, -24(%rsp) # 8-byte Spill leaq 16(,%rcx,8), %r8 movq %r8, -32(%rsp) # 8-byte Spill shlq $4, %rcx addq $16, %rcx movq %rcx, -40(%rsp) # 8-byte Spill leaq -8(,%rax,8), %r13 xorl %ebp, %ebp movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero movabsq $4652007308841189376, %r14 # imm = 0x408F400000000000 jmp .LBB0_2 .p2align 4, 0x90 .LBB0_7: # %._crit_edge75 # in Loop: Header=BB0_2 Depth=1 movq -8(%rsp), %rcx # 8-byte Reload movq %r14, (%rsi,%rcx,8) movq -16(%rsp), %rcx # 8-byte Reload movq %r14, (%rsi,%rcx,8) movq %r14, (%rsi,%rdx,8) movq %r14, (%rsi,%r11,8) incl %ebp movq %rsi, %rdi movq %r15, %rsi cmpl -52(%rsp), %ebp # 4-byte Folded Reload je .LBB0_8 .LBB0_2: # %.preheader72 # =>This Loop Header: Depth=1 # Child Loop BB0_4 Depth 2 # Child Loop BB0_5 Depth 3 movq %rdi, %r15 cmpl $3, -48(%rsp) # 4-byte Folded Reload jl .LBB0_7 # %bb.3: # %.preheader.preheader # in Loop: Header=BB0_2 Depth=1 movq -40(%rsp), %rcx # 8-byte Reload leaq (%r15,%rcx), %rdi movq -24(%rsp), %rcx # 8-byte Reload leaq (%rsi,%rcx), %r12 movq -32(%rsp), %rcx # 8-byte Reload leaq (%r15,%rcx), %r8 leaq 16(%r15), %rcx movl $1, %r9d .p2align 4, 0x90 .LBB0_4: # %.preheader # Parent Loop BB0_2 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB0_5 Depth 3 incq %r9 xorl %r10d, %r10d .p2align 4, 0x90 .LBB0_5: # Parent Loop BB0_2 Depth=1 # Parent Loop BB0_4 Depth=2 # => This Inner Loop Header: Depth=3 movsd -16(%rcx,%r10), %xmm1 # xmm1 = mem[0],zero addsd -8(%rcx,%r10), %xmm1 addsd (%rcx,%r10), %xmm1 addsd -16(%r8,%r10), %xmm1 addsd -8(%r8,%r10), %xmm1 addsd (%r8,%r10), %xmm1 addsd -16(%rdi,%r10), %xmm1 addsd -8(%rdi,%r10), %xmm1 addsd (%rdi,%r10), %xmm1 divsd %xmm0, %xmm1 movsd %xmm1, (%r12,%r10) addq $8, %r10 cmpq %r10, %r13 jne .LBB0_5 # %bb.6: # %._crit_edge # in Loop: Header=BB0_4 Depth=2 addq %rbx, %rdi addq %rbx, %r12 addq %rbx, %r8 addq %rbx, %rcx cmpq %rax, %r9 jne .LBB0_4 jmp .LBB0_7 .LBB0_8: # %._crit_edge79 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z13array_processPdS_ii, .Lfunc_end0-_Z13array_processPdS_ii .cfi_endproc # -- End function .globl _Z27__device_stub__heattransferPdS_i # -- Begin function _Z27__device_stub__heattransferPdS_i .p2align 4, 0x90 .type _Z27__device_stub__heattransferPdS_i,@function _Z27__device_stub__heattransferPdS_i: # @_Z27__device_stub__heattransferPdS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z12heattransferPdS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end1: .size _Z27__device_stub__heattransferPdS_i, .Lfunc_end1-_Z27__device_stub__heattransferPdS_i .cfi_endproc # -- End function .globl _Z28__device_stub__heattransfer2PdS_ii # -- Begin function _Z28__device_stub__heattransfer2PdS_ii .p2align 4, 0x90 .type _Z28__device_stub__heattransfer2PdS_ii,@function _Z28__device_stub__heattransfer2PdS_ii: # @_Z28__device_stub__heattransfer2PdS_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z13heattransfer2PdS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end2: .size _Z28__device_stub__heattransfer2PdS_ii, .Lfunc_end2-_Z28__device_stub__heattransfer2PdS_ii .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function _Z17GPU_array_processPdS_ii .LCPI3_0: .long 0x447a0000 # float 1000 .text .globl _Z17GPU_array_processPdS_ii .p2align 4, 0x90 .type _Z17GPU_array_processPdS_ii,@function _Z17GPU_array_processPdS_ii: # @_Z17GPU_array_processPdS_ii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $184, %rsp .cfi_def_cfa_offset 240 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %ecx, %r13d movl %edx, %r14d movq %rsi, %rbp movq %rdi, %rbx leaq 104(%rsp), %rdi callq hipEventCreate leaq 48(%rsp), %rdi callq hipEventCreate leaq 88(%rsp), %rdi callq hipEventCreate leaq 32(%rsp), %rdi callq hipEventCreate leaq 96(%rsp), %rdi callq hipEventCreate leaq 40(%rsp), %rdi callq hipEventCreate movl %r14d, %r15d imull %r15d, %r15d shlq $3, %r15 leaq 8(%rsp), %r12 movq %r12, %rdi movq %r15, %rsi callq hipMalloc testl %eax, %eax jne .LBB3_23 # %bb.1: movl %r13d, 20(%rsp) # 4-byte Spill leaq 24(%rsp), %r13 movq %r13, %rdi movq %r15, %rsi callq hipMalloc testl %eax, %eax je .LBB3_3 # %bb.2: movq 8(%rsp), %rdi callq hipFree jmp .LBB3_23 .LBB3_3: movq 104(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 8(%rsp), %rdi movq %rbx, %rsi movq %r15, %rdx movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB3_5 # %bb.4: movq 8(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree jmp .LBB3_23 .LBB3_5: movq %rbp, 112(%rsp) # 8-byte Spill movq 48(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 48(%rsp), %rdi callq hipEventSynchronize movq 96(%rsp), %rdi xorl %esi, %esi callq hipEventRecord cmpl $0, 20(%rsp) # 4-byte Folded Reload je .LBB3_10 # %bb.6: # %.lr.ph leal -2(%r14), %eax movslq 20(%rsp), %rbp # 4-byte Folded Reload movl %eax, %eax movabsq $4294967296, %rbx # imm = 0x100000000 orq %rax, %rbx jmp .LBB3_7 .p2align 4, 0x90 .LBB3_9: # in Loop: Header=BB3_7 Depth=1 movq 8(%rsp), %rax movq 24(%rsp), %rcx movq %rcx, 8(%rsp) movq %rax, 24(%rsp) decq %rbp je .LBB3_10 .LBB3_7: # =>This Inner Loop Header: Depth=1 movq %rbx, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_9 # %bb.8: # in Loop: Header=BB3_7 Depth=1 movq 8(%rsp), %rax movq 24(%rsp), %rcx movq %rax, 176(%rsp) movq %rcx, 168(%rsp) movl %r14d, 60(%rsp) leaq 176(%rsp), %rax movq %rax, 64(%rsp) leaq 168(%rsp), %rax movq %rax, 72(%rsp) leaq 60(%rsp), %rax movq %rax, 80(%rsp) leaq 152(%rsp), %rdi leaq 136(%rsp), %rsi leaq 128(%rsp), %rdx leaq 120(%rsp), %rcx callq __hipPopCallConfiguration movq 152(%rsp), %rsi movl 160(%rsp), %edx movq 136(%rsp), %rcx movl 144(%rsp), %r8d movl $_Z12heattransferPdS_i, %edi leaq 64(%rsp), %r9 pushq 120(%rsp) .cfi_adjust_cfa_offset 8 pushq 136(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 jmp .LBB3_9 .LBB3_10: # %._crit_edge movq 40(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 40(%rsp), %rdi callq hipEventSynchronize movq 88(%rsp), %rdi xorl %esi, %esi callq hipEventRecord testb $1, 20(%rsp) # 1-byte Folded Reload cmoveq %r12, %r13 movq (%r13), %rsi movq 112(%rsp), %rdi # 8-byte Reload movq %r15, %rdx movl $2, %ecx callq hipMemcpy movq 32(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 32(%rsp), %rdi callq hipEventSynchronize movq 8(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 104(%rsp), %rsi movq 48(%rsp), %rdx leaq 64(%rsp), %rdi callq hipEventElapsedTime movl $_ZSt4cout, %edi movl $.L.str, %esi movl $28, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq $4, _ZSt4cout+8(%rax) movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero divss .LCPI3_0(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB3_24 # %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r14) je .LBB3_13 # %bb.12: movzbl 67(%r14), %eax jmp .LBB3_14 .LBB3_13: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 96(%rsp), %rsi movq 40(%rsp), %rdx leaq 64(%rsp), %rdi callq hipEventElapsedTime movl $_ZSt4cout, %edi movl $.L.str.2, %esi movl $18, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq $4, _ZSt4cout+8(%rax) movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero divss .LCPI3_0(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB3_24 # %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30 cmpb $0, 56(%r14) je .LBB3_17 # %bb.16: movzbl 67(%r14), %eax jmp .LBB3_18 .LBB3_17: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB3_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33 movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 88(%rsp), %rsi movq 32(%rsp), %rdx leaq 64(%rsp), %rdi callq hipEventElapsedTime movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $28, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq $4, _ZSt4cout+8(%rax) movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero divss .LCPI3_0(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB3_24 # %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i35 cmpb $0, 56(%r14) je .LBB3_21 # %bb.20: movzbl 67(%r14), %eax jmp .LBB3_22 .LBB3_21: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB3_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit38 movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB3_23: addq $184, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB3_24: .cfi_def_cfa_offset 240 callq _ZSt16__throw_bad_castv .Lfunc_end3: .size _Z17GPU_array_processPdS_ii, .Lfunc_end3-_Z17GPU_array_processPdS_ii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12heattransferPdS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13heattransfer2PdS_ii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z12heattransferPdS_i,@object # @_Z12heattransferPdS_i .section .rodata,"a",@progbits .globl _Z12heattransferPdS_i .p2align 3, 0x0 _Z12heattransferPdS_i: .quad _Z27__device_stub__heattransferPdS_i .size _Z12heattransferPdS_i, 8 .type _Z13heattransfer2PdS_ii,@object # @_Z13heattransfer2PdS_ii .globl _Z13heattransfer2PdS_ii .p2align 3, 0x0 _Z13heattransfer2PdS_ii: .quad _Z28__device_stub__heattransfer2PdS_ii .size _Z13heattransfer2PdS_ii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Host to Device MemCpy takes " .size .L.str, 29 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "s" .size .L.str.1, 2 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Computation takes " .size .L.str.2, 19 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Device to Host MemCpy takes " .size .L.str.3, 29 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z12heattransferPdS_i" .size .L__unnamed_1, 22 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z13heattransfer2PdS_ii" .size .L__unnamed_2, 24 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__heattransferPdS_i .addrsig_sym _Z28__device_stub__heattransfer2PdS_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12heattransferPdS_i .addrsig_sym _Z13heattransfer2PdS_ii .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
14,393
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code for sm_80 Function : _Z6reducePKfPfi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R5, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], RZ ; IMAD R9, R2.reuse, c[0x0][0x170], R5.reuse ; IADD3 R0, R2.reuse, c[0x0][0x0], RZ ; IMAD.IADD R3, R2, 0x1, R5 ; IMAD R0, R0, c[0x0][0x170], RZ ; IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; ISETP.GE.AND P0, PT, R9, R0, PT ; STG.E [R2.64], RZ ; @P0 EXIT ; I2F.U32.RP R10, c[0x0][0x0] ; LOP3.LUT R8, RZ, R5, RZ, 0x33, !PT ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; BSSY B0, 0x360 ; IMAD.MOV.U32 R15, RZ, RZ, R9 ; IMAD R8, R5, c[0x0][0x170], R8 ; IMAD.MOV.U32 R17, RZ, RZ, RZ ; MUFU.RCP R10, R10 ; IADD3 R6, R10, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IADD3 R11, RZ, -R7, RZ ; IMAD R11, R11, c[0x0][0x0], RZ ; IMAD.HI.U32 R7, R7, R11, R6 ; IMAD.HI.U32 R7, R7, R8, RZ ; IADD3 R11, -R7, RZ, RZ ; IMAD R8, R11, c[0x0][0x0], R8 ; ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x0], PT ; @P0 IADD3 R8, R8, -c[0x0][0x0], RZ ; @P0 IADD3 R7, R7, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R8, c[0x0][0x0], PT ; @P1 IADD3 R7, R7, 0x1, RZ ; @!P2 LOP3.LUT R7, RZ, c[0x0][0x0], RZ, 0x33, !PT ; IADD3 R6, R7.reuse, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R7, 0x3, PT ; LOP3.LUT P0, R6, R6, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0x350 ; MOV R8, R6 ; IMAD.MOV.U32 R17, RZ, RZ, RZ ; IMAD.WIDE R6, R15, R4, c[0x0][0x160] ; LDG.E R10, [R6.64] ; IADD3 R8, R8, -0x1, RZ ; IADD3 R15, R15, c[0x0][0x0], RZ ; ISETP.NE.AND P0, PT, R8, RZ, PT ; IMAD.WIDE R6, R5, 0x4, R6 ; FMNMX R17, R10, R17, !PT ; STG.E [R2.64], R17 ; @P0 BRA 0x2d0 ; BSYNC B0 ; @!P1 EXIT ; IMAD.WIDE R6, R15, R4, c[0x0][0x160] ; LDG.E R8, [R6.64] ; FMNMX R19, R8, R17, !PT ; IMAD.WIDE R8, R5, 0x4, R6 ; STG.E [R2.64], R19 ; LDG.E R10, [R8.64] ; FMNMX R21, R19, R10, !PT ; IMAD.WIDE R10, R5, 0x4, R8 ; STG.E [R2.64], R21 ; LDG.E R12, [R10.64] ; FMNMX R23, R21, R12, !PT ; IMAD.WIDE R12, R5, 0x4, R10 ; STG.E [R2.64], R23 ; LDG.E R12, [R12.64] ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; MOV R8, c[0x0][0x0] ; IMAD R15, R6, 0x2, R15 ; LEA R15, R8, R15, 0x1 ; ISETP.GE.AND P0, PT, R15, R0, PT ; FMNMX R17, R23, R12, !PT ; STG.E [R2.64], R17 ; @!P0 BRA 0x370 ; EXIT ; BRA 0x4e0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0008b7c4_00000000-6_a636bad67381c759763e42292de994660ede06b7.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z29__device_stub__Z6reducePKfPfiPKfPfi .type _Z29__device_stub__Z6reducePKfPfiPKfPfi, @function _Z29__device_stub__Z6reducePKfPfiPKfPfi: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6reducePKfPfi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z29__device_stub__Z6reducePKfPfiPKfPfi, .-_Z29__device_stub__Z6reducePKfPfiPKfPfi .globl _Z6reducePKfPfi .type _Z6reducePKfPfi, @function _Z6reducePKfPfi: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z29__device_stub__Z6reducePKfPfiPKfPfi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z6reducePKfPfi, .-_Z6reducePKfPfi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z6reducePKfPfi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z6reducePKfPfi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6reducePKfPfi ; -- Begin function _Z6reducePKfPfi .globl _Z6reducePKfPfi .p2align 8 .type _Z6reducePKfPfi,@function _Z6reducePKfPfi: ; @_Z6reducePKfPfi ; %bb.0: s_clause 0x2 s_load_b32 s2, s[0:1], 0x24 s_load_b32 s3, s[0:1], 0x10 s_load_b64 s[6:7], s[0:1], 0x8 s_add_i32 s5, s15, 1 v_mov_b32_e32 v3, 0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_mul_i32 s5, s5, s3 s_mul_i32 s4, s15, s2 s_delay_alu instid0(SALU_CYCLE_1) v_add_nc_u32_e32 v1, s4, v0 s_mul_i32 s4, s4, s3 s_mul_i32 s3, s5, s2 v_add_nc_u32_e32 v5, s4, v0 s_mov_b32 s5, exec_lo v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v1, vcc_lo, s6, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo global_store_b32 v[1:2], v3, off v_cmpx_gt_i32_e64 s3, v5 s_cbranch_execz .LBB0_3 ; %bb.1: ; %.lr.ph global_load_b32 v6, v[1:2], off s_load_b64 s[0:1], s[0:1], 0x0 s_ashr_i32 s5, s4, 31 v_add_co_u32 v3, s4, s4, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v4, null, s5, 0, s4 s_lshl_b32 s4, s2, 2 v_lshlrev_b64 v[3:4], 2, v[3:4] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s0, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo s_mov_b32 s1, 0 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s5, s1 .LBB0_2: ; =>This Inner Loop Header: Depth=1 global_load_b32 v0, v[3:4], off s_waitcnt vmcnt(1) v_dual_max_f32 v6, v6, v6 :: v_dual_add_nc_u32 v5, s2, v5 v_add_co_u32 v3, vcc_lo, v3, s4 v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_i32_e64 s0, s3, v5 s_or_b32 s5, s0, s5 s_waitcnt vmcnt(0) v_max_f32_e32 v0, v0, v0 s_delay_alu instid0(VALU_DEP_1) v_max_f32_e32 v6, v6, v0 global_store_b32 v[1:2], v6, off s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_2 .LBB0_3: ; %Flow33 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6reducePKfPfi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6reducePKfPfi, .Lfunc_end0-_Z6reducePKfPfi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 308 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6reducePKfPfi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6reducePKfPfi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "a636bad67381c759763e42292de994660ede06b7.hip" .globl _Z21__device_stub__reducePKfPfi # -- Begin function _Z21__device_stub__reducePKfPfi .p2align 4, 0x90 .type _Z21__device_stub__reducePKfPfi,@function _Z21__device_stub__reducePKfPfi: # @_Z21__device_stub__reducePKfPfi .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6reducePKfPfi, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z21__device_stub__reducePKfPfi, .Lfunc_end0-_Z21__device_stub__reducePKfPfi .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6reducePKfPfi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z6reducePKfPfi,@object # @_Z6reducePKfPfi .section .rodata,"a",@progbits .globl _Z6reducePKfPfi .p2align 3, 0x0 _Z6reducePKfPfi: .quad _Z21__device_stub__reducePKfPfi .size _Z6reducePKfPfi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z6reducePKfPfi" .size .L__unnamed_1, 16 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__reducePKfPfi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z6reducePKfPfi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z6commonPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_CTAID.Y ; S2R R2, SR_TID.Y ; S2R R0, SR_CTAID.X ; S2R R5, SR_TID.X ; IMAD R3, R3, c[0x0][0x4], R2 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; IMAD R0, R0, c[0x0][0x0], R5 ; ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; @P0 EXIT ; MOV R2, c[0x0][0x178] ; ULDC.64 UR4, c[0x0][0x118] ; HFMA2.MMA R28, -RZ, RZ, 0, 0 ; IMAD R3, R3, c[0x0][0x178], RZ ; ISETP.GE.AND P0, PT, R2, 0x1, PT ; @!P0 BRA 0xbf0 ; IADD3 R4, R2.reuse, -0x1, RZ ; LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; MOV R4, RZ ; MOV R28, RZ ; @!P0 BRA 0xaf0 ; IADD3 R6, -R5, c[0x0][0x178], RZ ; HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR6, c[0x0][0x160] ; MOV R4, RZ ; ISETP.GT.AND P0, PT, R6, RZ, PT ; IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; @!P0 BRA 0x960 ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x6a0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; MOV R12, UR6 ; LDG.E R29, [R24.64] ; MOV R13, UR7 ; IMAD.WIDE R12, R3, 0x4, R12 ; LDG.E R27, [R12.64] ; IMAD.WIDE R10, R2, 0x4, R24 ; LDG.E R17, [R12.64+0x4] ; IMAD.WIDE R18, R2.reuse, 0x4, R10 ; LDG.E R16, [R10.64] ; LDG.E R7, [R12.64+0xc] ; IMAD.WIDE R14, R2, 0x4, R18 ; LDG.E R18, [R18.64] ; IMAD.WIDE R20, R2.reuse, 0x4, R14 ; LDG.E R26, [R14.64] ; LDG.E R9, [R12.64+0x10] ; LDG.E R19, [R12.64+0x8] ; IMAD.WIDE R14, R2, 0x4, R20 ; LDG.E R20, [R20.64] ; IMAD.WIDE R22, R2.reuse, 0x4, R14 ; LDG.E R8, [R14.64] ; LDG.E R11, [R12.64+0x14] ; IMAD.WIDE R24, R2, 0x4, R22 ; LDG.E R10, [R22.64] ; LDG.E R21, [R12.64+0x18] ; IMAD R29, R29, R27, R28 ; LDG.E R27, [R12.64+0x1c] ; LDG.E R28, [R24.64] ; IMAD.WIDE R14, R2, 0x4, R24 ; IMAD R29, R16, R17, R29 ; IMAD.WIDE R16, R2, 0x4, R14 ; LDG.E R14, [R14.64] ; IMAD R29, R18, R19, R29 ; IMAD.WIDE R18, R2, 0x4, R16 ; LDG.E R16, [R16.64] ; IMAD R26, R26, R7, R29 ; IMAD.WIDE R22, R2.reuse, 0x4, R18 ; LDG.E R7, [R12.64+0x20] ; LDG.E R29, [R12.64+0x24] ; IMAD.WIDE R24, R2, 0x4, R22 ; LDG.E R18, [R18.64] ; IMAD R9, R20, R9, R26 ; LDG.E R26, [R12.64+0x28] ; IMAD R11, R8, R11, R9 ; IMAD.WIDE R8, R2, 0x4, R24 ; LDG.E R22, [R22.64] ; LDG.E R17, [R12.64+0x2c] ; IMAD R21, R10, R21, R11 ; LDG.E R15, [R24.64] ; IMAD.WIDE R10, R2, 0x4, R8 ; LDG.E R19, [R8.64] ; LDG.E R23, [R10.64] ; LDG.E R24, [R12.64+0x30] ; LDG.E R25, [R12.64+0x38] ; LDG.E R8, [R12.64+0x3c] ; IMAD R9, R28, R27, R21 ; LDG.E R28, [R12.64+0x34] ; IMAD.WIDE R20, R2, 0x4, R10 ; LDG.E R27, [R20.64] ; IADD3 R6, R6, -0x10, RZ ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; IMAD R7, R14, R7, R9 ; IMAD R7, R16, R29, R7 ; IMAD R7, R18, R26, R7 ; IMAD R7, R22, R17, R7 ; UIADD3 UR6, UP0, UR6, 0x40, URZ ; IADD3 R4, R4, 0x10, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD R7, R15, R24, R7 ; IMAD R28, R19, R28, R7 ; IMAD R28, R23, R25, R28 ; IMAD.WIDE R24, R2, 0x4, R20 ; IMAD R28, R27, R8, R28 ; @P1 BRA 0x210 ; ISETP.GT.AND P1, PT, R6, 0x4, PT ; @!P1 BRA 0x940 ; IMAD.WIDE R16, R2, 0x4, R24 ; MOV R8, UR6 ; LDG.E R7, [R24.64] ; MOV R9, UR7 ; IMAD.WIDE R12, R2.reuse, 0x4, R16 ; LDG.E R21, [R16.64] ; IMAD.WIDE R8, R3, 0x4, R8 ; LDG.E R23, [R12.64] ; IMAD.WIDE R14, R2.reuse, 0x4, R12 ; LDG.E R20, [R8.64] ; LDG.E R22, [R8.64+0x4] ; IMAD.WIDE R10, R2, 0x4, R14 ; LDG.E R26, [R8.64+0x8] ; IMAD.WIDE R16, R2.reuse, 0x4, R10 ; LDG.E R14, [R14.64] ; LDG.E R27, [R8.64+0xc] ; IMAD.WIDE R18, R2, 0x4, R16 ; LDG.E R10, [R10.64] ; LDG.E R25, [R8.64+0x10] ; IMAD.WIDE R12, R2, 0x4, R18 ; LDG.E R16, [R16.64] ; LDG.E R29, [R8.64+0x14] ; LDG.E R24, [R18.64] ; LDG.E R11, [R8.64+0x18] ; LDG.E R15, [R12.64] ; LDG.E R18, [R8.64+0x1c] ; UIADD3 UR6, UP0, UR6, 0x20, URZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R4, R4, 0x8, RZ ; IADD3 R6, R6, -0x8, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD R7, R7, R20, R28 ; IMAD R7, R21, R22, R7 ; IMAD R7, R23, R26, R7 ; IMAD R7, R14, R27, R7 ; IMAD R7, R10, R25, R7 ; IMAD R7, R16, R29, R7 ; IMAD R7, R24, R11, R7 ; IMAD.WIDE R24, R2, 0x4, R12 ; IMAD R28, R15, R18, R7 ; ISETP.NE.OR P0, PT, R6, RZ, P0 ; @!P0 BRA 0xaf0 ; MOV R8, UR6 ; IMAD.WIDE R14, R2, 0x4, R24 ; MOV R9, UR7 ; LDG.E R25, [R24.64] ; IMAD.WIDE R8, R3, 0x4, R8 ; IMAD.WIDE R12, R2.reuse, 0x4, R14 ; LDG.E R7, [R8.64] ; LDG.E R14, [R14.64] ; IMAD.WIDE R10, R2, 0x4, R12 ; LDG.E R16, [R8.64+0x4] ; LDG.E R18, [R12.64] ; LDG.E R17, [R8.64+0x8] ; LDG.E R19, [R8.64+0xc] ; LDG.E R20, [R10.64] ; IADD3 R6, R6, -0x4, RZ ; ISETP.NE.AND P0, PT, R6, RZ, PT ; UIADD3 UR6, UP0, UR6, 0x10, URZ ; IADD3 R4, R4, 0x4, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD R7, R25, R7, R28 ; IMAD R7, R14, R16, R7 ; IMAD.WIDE R24, R2, 0x4, R10 ; IMAD R7, R18, R17, R7 ; IMAD R28, R20, R19, R7 ; @P0 BRA 0x960 ; ISETP.NE.AND P0, PT, R5, RZ, PT ; @!P0 BRA 0xbf0 ; HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; IADD3 R6, R3, R4, RZ ; IMAD R4, R4, c[0x0][0x178], R0 ; IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; LDG.E R11, [R8.64] ; LDG.E R4, [R6.64] ; IADD3 R5, R5, -0x1, RZ ; ISETP.NE.AND P0, PT, R5, RZ, PT ; IMAD.WIDE R8, R2, 0x4, R8 ; IADD3 R6, P1, R6, 0x4, RZ ; IADD3.X R7, RZ, R7, RZ, P1, !PT ; IMAD R28, R11, R4, R28 ; @P0 BRA 0xb60 ; IADD3 R3, R0, R3, RZ ; MOV R2, 0x4 ; IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; LDG.E R5, [R2.64] ; IADD3 R5, R5, R28, RZ ; STG.E [R2.64], R5 ; EXIT ; BRA 0xc60; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z5naivePiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R5, SR_CTAID.Y ; S2R R2, SR_TID.Y ; S2R R9, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R5, R5, c[0x0][0x4], R2 ; ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; IMAD R9, R9, c[0x0][0x0], R0 ; MOV R0, c[0x0][0x178] ; ISETP.GE.OR P0, PT, R9, c[0x0][0x178], P0 ; ISETP.LT.OR P0, PT, R0, 0x1, P0 ; @P0 EXIT ; IADD3 R2, R0, -0x1, RZ ; IMAD R9, R9, c[0x0][0x178], RZ ; HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; IADD3 R3, R5, R9, RZ ; LOP3.LUT R4, R0, 0x3, RZ, 0xc0, !PT ; MOV R10, RZ ; IMAD.WIDE R2, R3, R8, c[0x0][0x170] ; @!P0 BRA 0xcb0 ; IADD3 R11, -R4, c[0x0][0x178], RZ ; LDG.E R15, [R2.64] ; ULDC.64 UR6, c[0x0][0x160] ; MOV R10, RZ ; IMAD.WIDE R12, R5, R8, c[0x0][0x168] ; ISETP.GT.AND P0, PT, R11, RZ, PT ; @!P0 BRA 0xae0 ; ISETP.GT.AND P1, PT, R11, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x7a0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; MOV R6, UR6 ; LDG.E R14, [R12.64] ; MOV R7, UR7 ; IMAD.WIDE R6, R9, 0x4, R6 ; LDG.E R16, [R6.64] ; IMAD R19, R14, R16, R15 ; IMAD.WIDE R14, R0, 0x4, R12 ; STG.E [R2.64], R19 ; LDG.E R16, [R14.64] ; LDG.E R17, [R6.64+0x4] ; IMAD R21, R16, R17, R19 ; IMAD.WIDE R16, R0, 0x4, R14 ; STG.E [R2.64], R21 ; LDG.E R18, [R16.64] ; LDG.E R12, [R6.64+0x8] ; IMAD R23, R18, R12, R21 ; IMAD.WIDE R12, R0, 0x4, R16 ; STG.E [R2.64], R23 ; LDG.E R18, [R12.64] ; LDG.E R14, [R6.64+0xc] ; IMAD R19, R18, R14, R23 ; IMAD.WIDE R14, R0, 0x4, R12 ; STG.E [R2.64], R19 ; LDG.E R18, [R14.64] ; LDG.E R16, [R6.64+0x10] ; IMAD R21, R18, R16, R19 ; IMAD.WIDE R16, R0, 0x4, R14 ; STG.E [R2.64], R21 ; LDG.E R18, [R16.64] ; LDG.E R12, [R6.64+0x14] ; IMAD R23, R18, R12, R21 ; IMAD.WIDE R12, R0, 0x4, R16 ; STG.E [R2.64], R23 ; LDG.E R18, [R12.64] ; LDG.E R14, [R6.64+0x18] ; IMAD R19, R18, R14, R23 ; IMAD.WIDE R14, R0, 0x4, R12 ; STG.E [R2.64], R19 ; LDG.E R18, [R14.64] ; LDG.E R16, [R6.64+0x1c] ; IMAD R21, R18, R16, R19 ; IMAD.WIDE R16, R0, 0x4, R14 ; STG.E [R2.64], R21 ; LDG.E R18, [R16.64] ; LDG.E R12, [R6.64+0x20] ; IMAD R23, R18, R12, R21 ; IMAD.WIDE R12, R0, 0x4, R16 ; STG.E [R2.64], R23 ; LDG.E R18, [R12.64] ; LDG.E R14, [R6.64+0x24] ; IMAD R19, R18, R14, R23 ; IMAD.WIDE R14, R0, 0x4, R12 ; STG.E [R2.64], R19 ; LDG.E R18, [R14.64] ; LDG.E R16, [R6.64+0x28] ; IMAD R21, R18, R16, R19 ; IMAD.WIDE R16, R0, 0x4, R14 ; STG.E [R2.64], R21 ; LDG.E R18, [R16.64] ; LDG.E R12, [R6.64+0x2c] ; IMAD R23, R18, R12, R21 ; IMAD.WIDE R12, R0, 0x4, R16 ; STG.E [R2.64], R23 ; LDG.E R18, [R12.64] ; LDG.E R14, [R6.64+0x30] ; IMAD R25, R18, R14, R23 ; IMAD.WIDE R14, R0, 0x4, R12 ; STG.E [R2.64], R25 ; LDG.E R18, [R14.64] ; LDG.E R16, [R6.64+0x34] ; IMAD R21, R18, R16, R25 ; IMAD.WIDE R16, R0, 0x4, R14 ; STG.E [R2.64], R21 ; LDG.E R18, [R16.64] ; LDG.E R12, [R6.64+0x38] ; IADD3 R11, R11, -0x10, RZ ; IMAD R23, R18, R12, R21 ; IMAD.WIDE R18, R0, 0x4, R16 ; STG.E [R2.64], R23 ; LDG.E R13, [R6.64+0x3c] ; LDG.E R12, [R18.64] ; ISETP.GT.AND P1, PT, R11, 0xc, PT ; UIADD3 UR6, UP0, UR6, 0x40, URZ ; IADD3 R10, R10, 0x10, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD R15, R12, R13, R23 ; IMAD.WIDE R12, R0, 0x4, R18 ; STG.E [R2.64], R15 ; @P1 BRA 0x210 ; ISETP.GT.AND P1, PT, R11, 0x4, PT ; @!P1 BRA 0xac0 ; MOV R6, UR6 ; LDG.E R14, [R12.64] ; MOV R7, UR7 ; IMAD.WIDE R6, R9, 0x4, R6 ; LDG.E R16, [R6.64] ; IMAD R19, R14, R16, R15 ; IMAD.WIDE R14, R0, 0x4, R12 ; STG.E [R2.64], R19 ; LDG.E R16, [R14.64] ; LDG.E R17, [R6.64+0x4] ; IMAD R21, R16, R17, R19 ; IMAD.WIDE R16, R0, 0x4, R14 ; STG.E [R2.64], R21 ; LDG.E R18, [R16.64] ; LDG.E R12, [R6.64+0x8] ; IMAD R23, R18, R12, R21 ; IMAD.WIDE R12, R0, 0x4, R16 ; STG.E [R2.64], R23 ; LDG.E R18, [R12.64] ; LDG.E R14, [R6.64+0xc] ; IMAD R19, R18, R14, R23 ; IMAD.WIDE R14, R0, 0x4, R12 ; STG.E [R2.64], R19 ; LDG.E R18, [R14.64] ; LDG.E R16, [R6.64+0x10] ; IMAD R21, R18, R16, R19 ; IMAD.WIDE R16, R0, 0x4, R14 ; STG.E [R2.64], R21 ; LDG.E R18, [R16.64] ; LDG.E R12, [R6.64+0x14] ; IMAD R23, R18, R12, R21 ; IMAD.WIDE R12, R0, 0x4, R16 ; STG.E [R2.64], R23 ; LDG.E R18, [R12.64] ; LDG.E R14, [R6.64+0x18] ; IMAD R25, R18, R14, R23 ; IMAD.WIDE R18, R0, 0x4, R12 ; STG.E [R2.64], R25 ; LDG.E R15, [R6.64+0x1c] ; LDG.E R14, [R18.64] ; UIADD3 UR6, UP0, UR6, 0x20, URZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.WIDE R12, R0, 0x4, R18 ; IADD3 R10, R10, 0x8, RZ ; IADD3 R11, R11, -0x8, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD R15, R14, R15, R25 ; STG.E [R2.64], R15 ; ISETP.NE.OR P0, PT, R11, RZ, P0 ; @!P0 BRA 0xcb0 ; MOV R6, UR6 ; LDG.E R14, [R12.64] ; MOV R7, UR7 ; IMAD.WIDE R6, R9, 0x4, R6 ; LDG.E R16, [R6.64] ; IMAD R21, R14, R16, R15 ; IMAD.WIDE R14, R0, 0x4, R12 ; STG.E [R2.64], R21 ; LDG.E R16, [R14.64] ; LDG.E R17, [R6.64+0x4] ; IMAD R23, R16, R17, R21 ; IMAD.WIDE R16, R0, 0x4, R14 ; STG.E [R2.64], R23 ; LDG.E R18, [R16.64] ; LDG.E R12, [R6.64+0x8] ; IADD3 R11, R11, -0x4, RZ ; IMAD R25, R18, R12, R23 ; IMAD.WIDE R18, R0, 0x4, R16 ; STG.E [R2.64], R25 ; LDG.E R13, [R6.64+0xc] ; LDG.E R12, [R18.64] ; ISETP.NE.AND P0, PT, R11, RZ, PT ; UIADD3 UR6, UP0, UR6, 0x10, URZ ; IADD3 R10, R10, 0x4, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD R15, R12, R13, R25 ; IMAD.WIDE R12, R0, 0x4, R18 ; STG.E [R2.64], R15 ; @P0 BRA 0xae0 ; ISETP.NE.AND P0, PT, R4, RZ, PT ; @!P0 EXIT ; LDG.E R11, [R2.64] ; IADD3 R7, R9, R10, RZ ; IMAD R5, R10, c[0x0][0x178], R5 ; IMAD.WIDE R6, R7, R8, c[0x0][0x160] ; IMAD.WIDE R8, R5, R8, c[0x0][0x168] ; LDG.E R10, [R8.64] ; LDG.E R5, [R6.64] ; IADD3 R4, R4, -0x1, RZ ; ISETP.NE.AND P0, PT, R4, RZ, PT ; IMAD.WIDE R8, R0, 0x4, R8 ; IADD3 R6, P1, R6, 0x4, RZ ; IADD3.X R7, RZ, R7, RZ, P1, !PT ; IMAD R11, R10, R5, R11 ; STG.E [R2.64], R11 ; @P0 BRA 0xd20 ; EXIT ; BRA 0xdd0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z15memsetGPUKernelPii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_CTAID.Y ; S2R R2, SR_TID.Y ; S2R R0, SR_CTAID.X ; S2R R5, SR_TID.X ; IMAD R3, R3, c[0x0][0x4], R2 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x168], PT ; IMAD R0, R0, c[0x0][0x0], R5 ; ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; @P0 EXIT ; HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD R3, R3, c[0x0][0x168], R0 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; STG.E [R2.64], RZ ; EXIT ; BRA 0x100; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0010b768_00000000-6_71e7238e6d9064f7c180337b24396d93dc4a276a.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2067: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2067: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z10matrixMultPiS_S_i .type _Z10matrixMultPiS_S_i, @function _Z10matrixMultPiS_S_i: .LFB2057: .cfi_startproc endbr64 testl %ecx, %ecx jle .L11 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 movq %rdi, %r8 movq %rsi, %r12 movq %rdx, %rbp movl %ecx, %ebx movslq %ecx, %rdi salq $2, %rdi movq %r8, %r11 addq %rdi, %r8 movl $0, %r13d movl $0, %r14d jmp .L5 .L7: leal 1(%r13), %eax addq %rdi, %r11 addq %rdi, %r8 addq %rdi, %rbp cmpl %r10d, %r13d je .L3 movl %eax, %r13d .L5: movq %r12, %r9 movq %rbp, %rsi movl %r14d, %r10d .L8: movq %r9, %rcx movq %r11, %rax .L6: movl (%rax), %edx imull (%rcx), %edx addl %edx, (%rsi) addq $4, %rax addq %rdi, %rcx cmpq %r8, %rax jne .L6 leal 1(%r10), %eax addq $4, %r9 addq $4, %rsi cmpl %eax, %ebx je .L7 movl %eax, %r10d jmp .L8 .L3: popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L11: .cfi_restore 3 .cfi_restore 6 .cfi_restore 12 .cfi_restore 13 .cfi_restore 14 ret .cfi_endproc .LFE2057: .size _Z10matrixMultPiS_S_i, .-_Z10matrixMultPiS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%d " .LC1: .string "\n" .text .globl _Z11printMatrixPKii .type _Z11printMatrixPKii, @function _Z11printMatrixPKii: .LFB2058: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $24, %rsp .cfi_def_cfa_offset 80 movl %esi, 12(%rsp) testl %esi, %esi jle .L15 movslq %esi, %r14 leaq 0(,%r14,4), %r15 leaq (%rdi,%r15), %rbp negq %r14 salq $2, %r14 movl $0, %r13d leaq .LC0(%rip), %r12 .L16: leaq 0(%rbp,%r14), %rbx .L17: movl (%rbx), %edx movq %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L17 leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addl $1, %r13d addq %r15, %rbp cmpl %r13d, 12(%rsp) jne .L16 .L15: leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z11printMatrixPKii, .-_Z11printMatrixPKii .globl _Z4initPii .type _Z4initPii, @function _Z4initPii: .LFB2059: .cfi_startproc endbr64 testl %esi, %esi jle .L26 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $8, %rsp .cfi_def_cfa_offset 64 movl %esi, %r14d movslq %esi, %r13 leaq 0(,%r13,4), %r15 leaq (%rdi,%r15), %rbp negq %r13 salq $2, %r13 movl $0, %r12d .L22: leaq 0(%rbp,%r13), %rbx .L23: call rand@PLT movslq %eax, %rdx imulq $1717986919, %rdx, %rdx sarq $34, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx leal (%rdx,%rdx,4), %edx addl %edx, %edx subl %edx, %eax movl %eax, (%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L23 addl $1, %r12d addq %r15, %rbp cmpl %r12d, %r14d jne .L22 addq $8, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L26: .cfi_restore 3 .cfi_restore 6 .cfi_restore 12 .cfi_restore 13 .cfi_restore 14 .cfi_restore 15 ret .cfi_endproc .LFE2059: .size _Z4initPii, .-_Z4initPii .globl _Z8validatePKiS0_i .type _Z8validatePKiS0_i, @function _Z8validatePKiS0_i: .LFB2060: .cfi_startproc endbr64 testl %edx, %edx jle .L33 movslq %edx, %rax leaq 0(,%rax,4), %r10 negq %rax leaq 0(,%rax,4), %r8 movq %r10, %rcx movl $0, %r9d .L31: leaq (%rcx,%r8), %rax .L32: movl (%rsi,%rax), %r11d cmpl %r11d, (%rdi,%rax) jne .L34 addq $4, %rax cmpq %rcx, %rax jne .L32 addl $1, %r9d addq %r10, %rcx cmpl %r9d, %edx jne .L31 movl $1, %eax ret .L33: movl $1, %eax ret .L34: movl $0, %eax ret .cfi_endproc .LFE2060: .size _Z8validatePKiS0_i, .-_Z8validatePKiS0_i .section .rodata.str1.1 .LC2: .string "%s\n" .text .globl _Z8cuAssert9cudaError .type _Z8cuAssert9cudaError, @function _Z8cuAssert9cudaError: .LFB2061: .cfi_startproc endbr64 testl %edi, %edi jne .L42 ret .L42: subq $8, %rsp .cfi_def_cfa_offset 16 call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %edi call exit@PLT .cfi_endproc .LFE2061: .size _Z8cuAssert9cudaError, .-_Z8cuAssert9cudaError .section .rodata.str1.1 .LC4: .string "%s %.5f seconds\n" .text .globl _Z9printTimePc8timespecS0_ .type _Z9printTimePc8timespecS0_, @function _Z9printTimePc8timespecS0_: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 pxor %xmm0, %xmm0 cvtsi2sdq %r8, %xmm0 movsd .LC3(%rip), %xmm2 mulsd %xmm2, %xmm0 pxor %xmm1, %xmm1 cvtsi2sdq %rcx, %xmm1 addsd %xmm1, %xmm0 pxor %xmm1, %xmm1 cvtsi2sdq %rdx, %xmm1 mulsd %xmm2, %xmm1 pxor %xmm2, %xmm2 cvtsi2sdq %rsi, %xmm2 addsd %xmm2, %xmm1 subsd %xmm1, %xmm0 movq %rdi, %rdx leaq .LC4(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _Z9printTimePc8timespecS0_, .-_Z9printTimePc8timespecS0_ .globl _Z36__device_stub__Z15memsetGPUKernelPiiPii .type _Z36__device_stub__Z15memsetGPUKernelPiiPii, @function _Z36__device_stub__Z15memsetGPUKernelPiiPii: .LFB2089: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L49 .L45: movq 104(%rsp), %rax subq %fs:40, %rax jne .L50 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L49: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z15memsetGPUKernelPii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L45 .L50: call __stack_chk_fail@PLT .cfi_endproc .LFE2089: .size _Z36__device_stub__Z15memsetGPUKernelPiiPii, .-_Z36__device_stub__Z15memsetGPUKernelPiiPii .globl _Z15memsetGPUKernelPii .type _Z15memsetGPUKernelPii, @function _Z15memsetGPUKernelPii: .LFB2090: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z15memsetGPUKernelPiiPii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2090: .size _Z15memsetGPUKernelPii, .-_Z15memsetGPUKernelPii .globl _Z9memsetGPUPii .type _Z9memsetGPUPii, @function _Z9memsetGPUPii: .LFB2063: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $40, %rsp .cfi_def_cfa_offset 64 movq %rdi, %rbp movl %esi, %ebx leal 30(%rsi), %eax movl %esi, %edx addl $15, %edx cmovns %edx, %eax sarl $4, %eax movl %eax, 8(%rsp) movl %eax, 12(%rsp) movl $16, 20(%rsp) movl $16, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L56 .L54: call cudaGetLastError@PLT movl %eax, %edi call _Z8cuAssert9cudaError addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L56: .cfi_restore_state movl %ebx, %esi movq %rbp, %rdi call _Z36__device_stub__Z15memsetGPUKernelPiiPii jmp .L54 .cfi_endproc .LFE2063: .size _Z9memsetGPUPii, .-_Z9memsetGPUPii .globl _Z29__device_stub__Z5naivePiS_S_iPiS_S_i .type _Z29__device_stub__Z5naivePiS_S_iPiS_S_i, @function _Z29__device_stub__Z5naivePiS_S_iPiS_S_i: .LFB2091: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L61 .L57: movq 136(%rsp), %rax subq %fs:40, %rax jne .L62 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L61: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z5naivePiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L57 .L62: call __stack_chk_fail@PLT .cfi_endproc .LFE2091: .size _Z29__device_stub__Z5naivePiS_S_iPiS_S_i, .-_Z29__device_stub__Z5naivePiS_S_iPiS_S_i .globl _Z5naivePiS_S_i .type _Z5naivePiS_S_i, @function _Z5naivePiS_S_i: .LFB2092: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z29__device_stub__Z5naivePiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2092: .size _Z5naivePiS_S_i, .-_Z5naivePiS_S_i .globl _Z30__device_stub__Z6commonPiS_S_iPiS_S_i .type _Z30__device_stub__Z6commonPiS_S_iPiS_S_i, @function _Z30__device_stub__Z6commonPiS_S_iPiS_S_i: .LFB2093: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L69 .L65: movq 136(%rsp), %rax subq %fs:40, %rax jne .L70 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L69: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6commonPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L65 .L70: call __stack_chk_fail@PLT .cfi_endproc .LFE2093: .size _Z30__device_stub__Z6commonPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6commonPiS_S_iPiS_S_i .globl _Z6commonPiS_S_i .type _Z6commonPiS_S_i, @function _Z6commonPiS_S_i: .LFB2094: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z6commonPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2094: .size _Z6commonPiS_S_i, .-_Z6commonPiS_S_i .section .rodata.str1.1 .LC5: .string "true" .LC6: .string "false" .LC7: .string "Matrix size %d*%d\n" .LC8: .string "GPU 01x01/v1" .LC9: .string "GPU 32x32/v1" .LC10: .string "GPU 16x16/v1" .LC11: .string "GPU 16x16/v2" .LC12: .string "CPU " .LC13: .string "validate 01x01/v1 / cpu = %s\n" .LC14: .string "validate 32x32/v1 / cpu = %s\n" .LC15: .string "validate 16x16/v1 / cpu = %s\n" .LC16: .string "validate 16x16/v2 / cpu = %s\n" .text .globl main .type main, @function main: .LFB2064: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $120, %rsp .cfi_def_cfa_offset 176 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movl $0, %edi call time@PLT movl %eax, %edi call srand@PLT movq $0, 64(%rsp) movq $0, 72(%rsp) movq $0, 80(%rsp) movq $0, 88(%rsp) movl $1000, %ecx movl $1000, %edx leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $4000000, %edi call malloc@PLT movq %rax, %r15 movl $4000000, %edi call malloc@PLT movq %rax, %r14 movl $4000000, %edi call malloc@PLT movq %rax, %r13 movl $4000000, %edi call malloc@PLT movq %rax, %r12 movl $4000000, %edi call malloc@PLT movq %rax, %rbp movl $4000000, %edi call malloc@PLT movq %rax, (%rsp) movl $4000000, %edi call malloc@PLT movq %rax, %rbx movl $1000, %esi movq %r15, %rdi call _Z4initPii movl $1000, %esi movq %r14, %rdi call _Z4initPii movl $4000000, %edx movl $0, %esi movq %r13, %rdi call memset@PLT movl $4000000, %edx movl $0, %esi movq %r12, %rdi call memset@PLT movl $4000000, %edx movl $0, %esi movq %rbp, %rdi call memset@PLT movl $4000000, %edx movl $0, %esi movq (%rsp), %rdi call memset@PLT movl $4000000, %edx movl $0, %esi movq %rbx, %rdi call memset@PLT movq $0, 16(%rsp) movq $0, 24(%rsp) movq $0, 32(%rsp) leaq 16(%rsp), %rdi movl $4000000, %esi call cudaMalloc@PLT movl %eax, %edi call _Z8cuAssert9cudaError leaq 24(%rsp), %rdi movl $4000000, %esi call cudaMalloc@PLT movl %eax, %edi call _Z8cuAssert9cudaError leaq 32(%rsp), %rdi movl $4000000, %esi call cudaMalloc@PLT movl %eax, %edi call _Z8cuAssert9cudaError movl $1, %ecx movl $4000000, %edx movq %r15, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %edi call _Z8cuAssert9cudaError movl $1, %ecx movl $4000000, %edx movq %r14, %rsi movq 24(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %edi call _Z8cuAssert9cudaError movl $1000, %esi movq 32(%rsp), %rdi call _Z9memsetGPUPii movl $1000, 40(%rsp) movl $1000, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) leaq 64(%rsp), %rsi movl $1, %edi call clock_gettime@PLT movl 60(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 52(%rsp), %rdx movq 40(%rsp), %rdi movl 48(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L88 .L74: call cudaDeviceSynchronize@PLT movl %eax, %edi call _Z8cuAssert9cudaError leaq 80(%rsp), %rsi movl $1, %edi call clock_gettime@PLT movq 80(%rsp), %rcx movq 88(%rsp), %r8 movq 64(%rsp), %rsi movq 72(%rsp), %rdx leaq .LC8(%rip), %rdi call _Z9printTimePc8timespecS0_ call cudaGetLastError@PLT movl %eax, %edi call _Z8cuAssert9cudaError movl $2, %ecx movl $4000000, %edx movq 32(%rsp), %rsi movq %r13, %rdi call cudaMemcpy@PLT movl %eax, %edi call _Z8cuAssert9cudaError movl $1000, %esi movq 32(%rsp), %rdi call _Z9memsetGPUPii movl $32, 52(%rsp) movl $32, 56(%rsp) movl $32, 40(%rsp) movl $32, 44(%rsp) leaq 64(%rsp), %rsi movl $1, %edi call clock_gettime@PLT movl 60(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 52(%rsp), %rdx movq 40(%rsp), %rdi movl 48(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L89 .L75: call cudaDeviceSynchronize@PLT movl %eax, %edi call _Z8cuAssert9cudaError leaq 80(%rsp), %rsi movl $1, %edi call clock_gettime@PLT movq 80(%rsp), %rcx movq 88(%rsp), %r8 movq 64(%rsp), %rsi movq 72(%rsp), %rdx leaq .LC9(%rip), %rdi call _Z9printTimePc8timespecS0_ movl $2, %ecx movl $4000000, %edx movq 32(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT movl %eax, %edi call _Z8cuAssert9cudaError movl $1000, %esi movq 32(%rsp), %rdi call _Z9memsetGPUPii movl $16, 52(%rsp) movl $16, 56(%rsp) movl $63, 40(%rsp) movl $63, 44(%rsp) leaq 64(%rsp), %rsi movl $1, %edi call clock_gettime@PLT movl 60(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 52(%rsp), %rdx movq 40(%rsp), %rdi movl 48(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L90 .L76: call cudaDeviceSynchronize@PLT movl %eax, %edi call _Z8cuAssert9cudaError leaq 80(%rsp), %rsi movl $1, %edi call clock_gettime@PLT movq 80(%rsp), %rcx movq 88(%rsp), %r8 movq 64(%rsp), %rsi movq 72(%rsp), %rdx leaq .LC10(%rip), %rdi call _Z9printTimePc8timespecS0_ movl $2, %ecx movl $4000000, %edx movq 32(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT movl %eax, %edi call _Z8cuAssert9cudaError movl $1000, %esi movq 32(%rsp), %rdi call _Z9memsetGPUPii leaq 64(%rsp), %rsi movl $1, %edi call clock_gettime@PLT movl 60(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 52(%rsp), %rdx movq 40(%rsp), %rdi movl 48(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L91 .L77: call cudaDeviceSynchronize@PLT movl %eax, %edi call _Z8cuAssert9cudaError leaq 80(%rsp), %rax movq %rax, 8(%rsp) movq %rax, %rsi movl $1, %edi call clock_gettime@PLT movq 80(%rsp), %rcx movq 88(%rsp), %r8 movq 64(%rsp), %rsi movq 72(%rsp), %rdx leaq .LC11(%rip), %rdi call _Z9printTimePc8timespecS0_ movl $2, %ecx movl $4000000, %edx movq 32(%rsp), %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl %eax, %edi call _Z8cuAssert9cudaError movl $1000, %esi movq 32(%rsp), %rdi call _Z9memsetGPUPii movq 16(%rsp), %rdi call cudaFree@PLT movl %eax, %edi call _Z8cuAssert9cudaError movq 24(%rsp), %rdi call cudaFree@PLT movl %eax, %edi call _Z8cuAssert9cudaError movq 32(%rsp), %rdi call cudaFree@PLT movl %eax, %edi call _Z8cuAssert9cudaError leaq 64(%rsp), %rsi movl $1, %edi call clock_gettime@PLT movl $1000, %ecx movq %rbx, %rdx movq %r14, %rsi movq %r15, %rdi call _Z10matrixMultPiS_S_i movq 8(%rsp), %rsi movl $1, %edi call clock_gettime@PLT movq 80(%rsp), %rcx movq 88(%rsp), %r8 movq 64(%rsp), %rsi movq 72(%rsp), %rdx leaq .LC12(%rip), %rdi call _Z9printTimePc8timespecS0_ movl $1000, %edx movq %rbx, %rsi movq %r13, %rdi call _Z8validatePKiS0_i testb %al, %al leaq .LC6(%rip), %rdx leaq .LC5(%rip), %rax cmovne %rax, %rdx leaq .LC13(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1000, %edx movq %rbx, %rsi movq %r12, %rdi call _Z8validatePKiS0_i testb %al, %al leaq .LC6(%rip), %rdx leaq .LC5(%rip), %rax cmovne %rax, %rdx leaq .LC14(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1000, %edx movq %rbx, %rsi movq %rbp, %rdi call _Z8validatePKiS0_i testb %al, %al leaq .LC6(%rip), %rdx leaq .LC5(%rip), %rax cmovne %rax, %rdx leaq .LC15(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1000, %edx movq %rbx, %rsi movq (%rsp), %rdi call _Z8validatePKiS0_i testb %al, %al leaq .LC6(%rip), %rdx leaq .LC5(%rip), %rax cmovne %rax, %rdx leaq .LC16(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %r15, %rdi call free@PLT movq %r14, %rdi call free@PLT movq %r13, %rdi call free@PLT movq %r12, %rdi call free@PLT movq %rbp, %rdi call free@PLT movq 104(%rsp), %rax subq %fs:40, %rax jne .L92 movl $0, %eax addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L88: .cfi_restore_state movl $1000, %ecx movq 32(%rsp), %rdx movq 24(%rsp), %rsi movq 16(%rsp), %rdi call _Z29__device_stub__Z5naivePiS_S_iPiS_S_i jmp .L74 .L89: movl $1000, %ecx movq 32(%rsp), %rdx movq 24(%rsp), %rsi movq 16(%rsp), %rdi call _Z29__device_stub__Z5naivePiS_S_iPiS_S_i jmp .L75 .L90: movl $1000, %ecx movq 32(%rsp), %rdx movq 24(%rsp), %rsi movq 16(%rsp), %rdi call _Z29__device_stub__Z5naivePiS_S_iPiS_S_i jmp .L76 .L91: movl $1000, %ecx movq 32(%rsp), %rdx movq 24(%rsp), %rsi movq 16(%rsp), %rdi call _Z30__device_stub__Z6commonPiS_S_iPiS_S_i jmp .L77 .L92: call __stack_chk_fail@PLT .cfi_endproc .LFE2064: .size main, .-main .section .rodata.str1.1 .LC17: .string "_Z6commonPiS_S_i" .LC18: .string "_Z5naivePiS_S_i" .LC19: .string "_Z15memsetGPUKernelPii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2096: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC17(%rip), %rdx movq %rdx, %rcx leaq _Z6commonPiS_S_i(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC18(%rip), %rdx movq %rdx, %rcx leaq _Z5naivePiS_S_i(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC19(%rip), %rdx movq %rdx, %rcx leaq _Z15memsetGPUKernelPii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2096: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC3: .long -400107883 .long 1041313291 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15memsetGPUKernelPii ; -- Begin function _Z15memsetGPUKernelPii .globl _Z15memsetGPUKernelPii .p2align 8 .type _Z15memsetGPUKernelPii,@function _Z15memsetGPUKernelPii: ; @_Z15memsetGPUKernelPii ; %bb.0: s_clause 0x1 s_load_b32 s3, s[0:1], 0x1c s_load_b32 s2, s[0:1], 0x8 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s4, s3, 0xffff s_lshr_b32 s3, s3, 16 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4] s_mov_b32 s3, exec_lo v_max_i32_e32 v2, v0, v1 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s2, v2 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b64 s[0:1], s[0:1], 0x0 v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[0:1], 2, v[2:3] v_mov_b32_e32 v2, 0 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15memsetGPUKernelPii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15memsetGPUKernelPii, .Lfunc_end0-_Z15memsetGPUKernelPii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 172 ; NumSgprs: 18 ; NumVgprs: 5 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 5 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .protected _Z5naivePiS_S_i ; -- Begin function _Z5naivePiS_S_i .globl _Z5naivePiS_S_i .p2align 8 .type _Z5naivePiS_S_i,@function _Z5naivePiS_S_i: ; @_Z5naivePiS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s4, s[0:1], 0x18 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v4, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s3, s2, 0xffff s_lshr_b32 s2, s2, 16 v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2] v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5] s_mov_b32 s2, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_max3_i32 v1, v2, v0, 0 v_cmpx_gt_i32_e64 s4, v1 s_cbranch_execz .LBB1_3 ; %bb.1: ; %.lr.ph v_mul_lo_u32 v4, v2, s4 s_load_b64 s[2:3], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v1, v4, v0 v_ashrrev_i32_e32 v5, 31, v4 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[4:5], 2, v[4:5] v_lshlrev_b64 v[2:3], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo s_load_b128 s[0:3], s[0:1], 0x0 global_load_b32 v6, v[2:3], off s_waitcnt lgkmcnt(0) v_add_co_u32 v4, vcc_lo, s0, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo s_mov_b32 s0, s4 .p2align 6 .LBB1_2: ; =>This Inner Loop Header: Depth=1 v_ashrrev_i32_e32 v1, 31, v0 s_add_i32 s0, s0, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_cmp_lg_u32 s0, 0 v_lshlrev_b64 v[7:8], 2, v[0:1] v_add_nc_u32_e32 v0, s4, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v7, vcc_lo, s2, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo global_load_b32 v1, v[4:5], off global_load_b32 v9, v[7:8], off v_add_co_u32 v4, vcc_lo, v4, 4 v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo s_waitcnt vmcnt(0) v_mad_u64_u32 v[7:8], null, v9, v1, v[6:7] s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v6, v7 global_store_b32 v[2:3], v7, off s_cbranch_scc1 .LBB1_2 .LBB1_3: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5naivePiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z5naivePiS_S_i, .Lfunc_end1-_Z5naivePiS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 320 ; NumSgprs: 18 ; NumVgprs: 10 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 10 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .protected _Z6commonPiS_S_i ; -- Begin function _Z6commonPiS_S_i .globl _Z6commonPiS_S_i .p2align 8 .type _Z6commonPiS_S_i,@function _Z6commonPiS_S_i: ; @_Z6commonPiS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s3, s[0:1], 0x2c s_load_b32 s2, s[0:1], 0x18 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s4, s3, 0xffff s_lshr_b32 s3, s3, 16 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4] s_mov_b32 s3, exec_lo v_max_i32_e32 v2, v0, v1 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s2, v2 s_cbranch_execz .LBB2_6 ; %bb.1: ; %.preheader s_cmp_lt_i32 s2, 1 s_cbranch_scc1 .LBB2_4 ; %bb.2: ; %.lr.ph s_load_b128 s[4:7], s[0:1], 0x0 v_mul_lo_u32 v2, v1, s2 s_mov_b32 s3, s2 v_mov_b32_e32 v5, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[3:4], 2, v[2:3] v_mov_b32_e32 v2, 0 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v3, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo .p2align 6 .LBB2_3: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_ashrrev_i32_e32 v6, 31, v5 s_add_i32 s3, s3, -1 s_cmp_eq_u32 s3, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 2, v[5:6] v_add_co_u32 v6, vcc_lo, s6, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo global_load_b32 v8, v[3:4], off global_load_b32 v9, v[6:7], off s_waitcnt vmcnt(0) v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3] v_add_co_u32 v3, vcc_lo, v3, 4 v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5 s_cbranch_scc0 .LBB2_3 s_branch .LBB2_5 .LBB2_4: v_mov_b32_e32 v2, 0 .LBB2_5: ; %Flow41 s_load_b64 s[0:1], s[0:1], 0x10 v_mad_u64_u32 v[3:4], null, v1, s2, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[0:1], 2, v[3:4] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b32 v3, v[0:1], off s_waitcnt vmcnt(0) v_add_nc_u32_e32 v2, v3, v2 global_store_b32 v[0:1], v2, off .LBB2_6: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6commonPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z6commonPiS_S_i, .Lfunc_end2-_Z6commonPiS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 364 ; NumSgprs: 18 ; NumVgprs: 10 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 10 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15memsetGPUKernelPii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15memsetGPUKernelPii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5naivePiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z5naivePiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6commonPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6commonPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "71e7238e6d9064f7c180337b24396d93dc4a276a.hip" .globl _Z10matrixMultPiS_S_i # -- Begin function _Z10matrixMultPiS_S_i .p2align 4, 0x90 .type _Z10matrixMultPiS_S_i,@function _Z10matrixMultPiS_S_i: # @_Z10matrixMultPiS_S_i .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdx, -8(%rsp) # 8-byte Spill testl %ecx, %ecx jle .LBB0_7 # %bb.1: # %.preheader23.lr.ph movl %ecx, %eax leaq (,%rax,4), %r8 xorl %edx, %edx xorl %r10d, %r10d .p2align 4, 0x90 .LBB0_2: # %.preheader23 # =>This Loop Header: Depth=1 # Child Loop BB0_3 Depth 2 # Child Loop BB0_4 Depth 3 movl %edx, %r11d leaq (%rdi,%r11,4), %r11 movq %r10, %rbx imulq %rax, %rbx movq -8(%rsp), %r9 # 8-byte Reload leaq (%r9,%rbx,4), %rbx movq %rsi, %r14 xorl %r15d, %r15d .p2align 4, 0x90 .LBB0_3: # %.preheader # Parent Loop BB0_2 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB0_4 Depth 3 movl (%rbx,%r15,4), %ebp movq %r14, %r12 xorl %r13d, %r13d .p2align 4, 0x90 .LBB0_4: # Parent Loop BB0_2 Depth=1 # Parent Loop BB0_3 Depth=2 # => This Inner Loop Header: Depth=3 movl (%r12), %r9d imull (%r11,%r13,4), %r9d addl %r9d, %ebp movl %ebp, (%rbx,%r15,4) incq %r13 addq %r8, %r12 cmpq %r13, %rax jne .LBB0_4 # %bb.5: # %._crit_edge # in Loop: Header=BB0_3 Depth=2 incq %r15 addq $4, %r14 cmpq %rax, %r15 jne .LBB0_3 # %bb.6: # %._crit_edge26 # in Loop: Header=BB0_2 Depth=1 incq %r10 addl %ecx, %edx cmpq %rax, %r10 jne .LBB0_2 .LBB0_7: # %._crit_edge28 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z10matrixMultPiS_S_i, .Lfunc_end0-_Z10matrixMultPiS_S_i .cfi_endproc # -- End function .globl _Z11printMatrixPKii # -- Begin function _Z11printMatrixPKii .p2align 4, 0x90 .type _Z11printMatrixPKii,@function _Z11printMatrixPKii: # @_Z11printMatrixPKii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 pushq %rax .cfi_def_cfa_offset 64 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdi, (%rsp) # 8-byte Spill testl %esi, %esi jle .LBB1_5 # %bb.1: # %.preheader.lr.ph movl %esi, %ebx movl %esi, %r15d xorl %ebp, %ebp xorl %r12d, %r12d .p2align 4, 0x90 .LBB1_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_3 Depth 2 movl %ebp, %eax movq (%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %r13 xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_3: # Parent Loop BB1_2 Depth=1 # => This Inner Loop Header: Depth=2 movl (%r13,%r14,4), %esi movl $.L.str, %edi xorl %eax, %eax callq printf incq %r14 cmpq %r14, %r15 jne .LBB1_3 # %bb.4: # %._crit_edge # in Loop: Header=BB1_2 Depth=1 movl $10, %edi callq putchar@PLT incq %r12 addl %ebx, %ebp cmpq %r15, %r12 jne .LBB1_2 .LBB1_5: # %._crit_edge14 movl $10, %edi addq $8, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 jmp putchar@PLT # TAILCALL .Lfunc_end1: .size _Z11printMatrixPKii, .Lfunc_end1-_Z11printMatrixPKii .cfi_endproc # -- End function .globl _Z4initPii # -- Begin function _Z4initPii .p2align 4, 0x90 .type _Z4initPii,@function _Z4initPii: # @_Z4initPii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 pushq %rax .cfi_def_cfa_offset 64 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdi, (%rsp) # 8-byte Spill testl %esi, %esi jle .LBB2_5 # %bb.1: # %.preheader.lr.ph movl %esi, %ebx movl %esi, %r15d xorl %r12d, %r12d xorl %r13d, %r13d .p2align 4, 0x90 .LBB2_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB2_3 Depth 2 movl %r12d, %eax movq (%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %rbp xorl %r14d, %r14d .p2align 4, 0x90 .LBB2_3: # Parent Loop BB2_2 Depth=1 # => This Inner Loop Header: Depth=2 callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx subl %ecx, %eax movl %eax, (%rbp,%r14,4) incq %r14 cmpq %r14, %r15 jne .LBB2_3 # %bb.4: # %._crit_edge # in Loop: Header=BB2_2 Depth=1 incq %r13 addl %ebx, %r12d cmpq %r15, %r13 jne .LBB2_2 .LBB2_5: # %._crit_edge13 addq $8, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z4initPii, .Lfunc_end2-_Z4initPii .cfi_endproc # -- End function .globl _Z8validatePKiS0_i # -- Begin function _Z8validatePKiS0_i .p2align 4, 0x90 .type _Z8validatePKiS0_i,@function _Z8validatePKiS0_i: # @_Z8validatePKiS0_i .cfi_startproc # %bb.0: testl %edx, %edx setle %al jle .LBB3_9 # %bb.1: # %.preheader.lr.ph pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movl %edx, %ecx leaq 4(%rdi), %rdx leaq (,%rcx,4), %r8 leaq 4(%rsi), %r9 leaq -1(%rcx), %r10 xorl %r11d, %r11d jmp .LBB3_2 .p2align 4, 0x90 .LBB3_7: # %.critedge # in Loop: Header=BB3_2 Depth=1 incq %r11 cmpq %rcx, %r11 setae %al addq %r8, %rdx addq %r8, %r9 cmpq %rcx, %r11 je .LBB3_8 .LBB3_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB3_4 Depth 2 movq %r11, %rbx imulq %rcx, %rbx movl (%rdi,%rbx,4), %ebp cmpl (%rsi,%rbx,4), %ebp jne .LBB3_8 # %bb.3: # %.lr.ph.preheader # in Loop: Header=BB3_2 Depth=1 xorl %ebx, %ebx .p2align 4, 0x90 .LBB3_4: # %.lr.ph # Parent Loop BB3_2 Depth=1 # => This Inner Loop Header: Depth=2 cmpq %rbx, %r10 je .LBB3_7 # %bb.5: # in Loop: Header=BB3_4 Depth=2 movl (%rdx,%rbx,4), %ebp leaq 1(%rbx), %r14 cmpl (%r9,%rbx,4), %ebp movq %r14, %rbx je .LBB3_4 # %bb.6: # %._crit_edge38 # in Loop: Header=BB3_2 Depth=1 cmpq %rcx, %r14 jae .LBB3_7 .LBB3_8: popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 .cfi_restore %rbx .cfi_restore %r14 .cfi_restore %rbp .LBB3_9: # %._crit_edge andb $1, %al retq .Lfunc_end3: .size _Z8validatePKiS0_i, .Lfunc_end3-_Z8validatePKiS0_i .cfi_endproc # -- End function .globl _Z8cuAssert10hipError_t # -- Begin function _Z8cuAssert10hipError_t .p2align 4, 0x90 .type _Z8cuAssert10hipError_t,@function _Z8cuAssert10hipError_t: # @_Z8cuAssert10hipError_t .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB4_2 # %bb.1: retq .LBB4_2: pushq %rax .cfi_def_cfa_offset 16 callq hipGetErrorString movq %rax, %rdi callq puts@PLT xorl %edi, %edi callq exit .Lfunc_end4: .size _Z8cuAssert10hipError_t, .Lfunc_end4-_Z8cuAssert10hipError_t .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function _Z9printTimePc8timespecS0_ .LCPI5_0: .quad 0x3e112e0be826d695 # double 1.0000000000000001E-9 .text .globl _Z9printTimePc8timespecS0_ .p2align 4, 0x90 .type _Z9printTimePc8timespecS0_,@function _Z9printTimePc8timespecS0_: # @_Z9printTimePc8timespecS0_ .cfi_startproc # %bb.0: movq %rdi, %rax cvtsi2sd %rcx, %xmm1 cvtsi2sd %r8, %xmm0 movsd .LCPI5_0(%rip), %xmm2 # xmm2 = mem[0],zero mulsd %xmm2, %xmm0 cvtsi2sd %rsi, %xmm3 cvtsi2sd %rdx, %xmm4 addsd %xmm1, %xmm0 mulsd %xmm2, %xmm4 addsd %xmm3, %xmm4 subsd %xmm4, %xmm0 movl $.L.str.3, %edi movq %rax, %rsi movb $1, %al jmp printf # TAILCALL .Lfunc_end5: .size _Z9printTimePc8timespecS0_, .Lfunc_end5-_Z9printTimePc8timespecS0_ .cfi_endproc # -- End function .globl _Z30__device_stub__memsetGPUKernelPii # -- Begin function _Z30__device_stub__memsetGPUKernelPii .p2align 4, 0x90 .type _Z30__device_stub__memsetGPUKernelPii,@function _Z30__device_stub__memsetGPUKernelPii: # @_Z30__device_stub__memsetGPUKernelPii .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z15memsetGPUKernelPii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end6: .size _Z30__device_stub__memsetGPUKernelPii, .Lfunc_end6-_Z30__device_stub__memsetGPUKernelPii .cfi_endproc # -- End function .globl _Z9memsetGPUPii # -- Begin function _Z9memsetGPUPii .p2align 4, 0x90 .type _Z9memsetGPUPii,@function _Z9memsetGPUPii: # @_Z9memsetGPUPii .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $88, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movl %esi, %ebx movq %rdi, %r14 leal 15(%rbx), %eax leal 30(%rbx), %ecx testl %eax, %eax cmovnsl %eax, %ecx sarl $4, %ecx movq %rcx, %rdi shlq $32, %rdi orq %rcx, %rdi movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB7_2 # %bb.1: movq %r14, 56(%rsp) movl %ebx, 4(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z15memsetGPUKernelPii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB7_2: callq hipGetLastError testl %eax, %eax jne .LBB7_4 # %bb.3: # %_Z8cuAssert10hipError_t.exit addq $88, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB7_4: .cfi_def_cfa_offset 112 movl %eax, %edi callq hipGetErrorString movq %rax, %rdi callq puts@PLT xorl %edi, %edi callq exit .Lfunc_end7: .size _Z9memsetGPUPii, .Lfunc_end7-_Z9memsetGPUPii .cfi_endproc # -- End function .globl _Z20__device_stub__naivePiS_S_i # -- Begin function _Z20__device_stub__naivePiS_S_i .p2align 4, 0x90 .type _Z20__device_stub__naivePiS_S_i,@function _Z20__device_stub__naivePiS_S_i: # @_Z20__device_stub__naivePiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z5naivePiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end8: .size _Z20__device_stub__naivePiS_S_i, .Lfunc_end8-_Z20__device_stub__naivePiS_S_i .cfi_endproc # -- End function .globl _Z21__device_stub__commonPiS_S_i # -- Begin function _Z21__device_stub__commonPiS_S_i .p2align 4, 0x90 .type _Z21__device_stub__commonPiS_S_i,@function _Z21__device_stub__commonPiS_S_i: # @_Z21__device_stub__commonPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6commonPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end9: .size _Z21__device_stub__commonPiS_S_i, .Lfunc_end9-_Z21__device_stub__commonPiS_S_i .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI10_0: .quad 0x3e112e0be826d695 # double 1.0000000000000001E-9 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $200, %rsp .cfi_def_cfa_offset 256 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 xorl %r15d, %r15d xorl %edi, %edi callq time movl %eax, %edi callq srand xorpd %xmm0, %xmm0 movapd %xmm0, 32(%rsp) movapd %xmm0, 16(%rsp) movl $.L.str.4, %edi movl $1000, %esi # imm = 0x3E8 movl $1000, %edx # imm = 0x3E8 xorl %eax, %eax callq printf movl $4000000, %edi # imm = 0x3D0900 callq malloc movq %rax, %rbp movl $4000000, %edi # imm = 0x3D0900 callq malloc movq %rax, %r14 movl $4000000, %edi # imm = 0x3D0900 callq malloc movq %rax, 192(%rsp) # 8-byte Spill movl $4000000, %edi # imm = 0x3D0900 callq malloc movq %rax, 184(%rsp) # 8-byte Spill movl $4000000, %edi # imm = 0x3D0900 callq malloc movq %rax, 136(%rsp) # 8-byte Spill movl $4000000, %edi # imm = 0x3D0900 callq malloc movq %rax, 176(%rsp) # 8-byte Spill movl $4000000, %edi # imm = 0x3D0900 callq malloc movq %rax, %rbx movq %rbp, %r13 .p2align 4, 0x90 .LBB10_1: # %.preheader.i # =>This Loop Header: Depth=1 # Child Loop BB10_2 Depth 2 xorl %r12d, %r12d .p2align 4, 0x90 .LBB10_2: # Parent Loop BB10_1 Depth=1 # => This Inner Loop Header: Depth=2 callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx subl %ecx, %eax movl %eax, (%rbp,%r12,4) incq %r12 cmpq $1000, %r12 # imm = 0x3E8 jne .LBB10_2 # %bb.3: # %._crit_edge.i # in Loop: Header=BB10_1 Depth=1 incq %r15 addq $4000, %rbp # imm = 0xFA0 cmpq $1000, %r15 # imm = 0x3E8 jne .LBB10_1 # %bb.4: # %.preheader.i120.preheader xorl %r15d, %r15d movq %r14, %rbp .p2align 4, 0x90 .LBB10_5: # %.preheader.i120 # =>This Loop Header: Depth=1 # Child Loop BB10_6 Depth 2 xorl %r12d, %r12d .p2align 4, 0x90 .LBB10_6: # Parent Loop BB10_5 Depth=1 # => This Inner Loop Header: Depth=2 callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx subl %ecx, %eax movl %eax, (%rbp,%r12,4) incq %r12 cmpq $1000, %r12 # imm = 0x3E8 jne .LBB10_6 # %bb.7: # %._crit_edge.i125 # in Loop: Header=BB10_5 Depth=1 incq %r15 addq $4000, %rbp # imm = 0xFA0 cmpq $1000, %r15 # imm = 0x3E8 jne .LBB10_5 # %bb.8: # %_Z4initPii.exit128 movl $4000000, %edx # imm = 0x3D0900 movq 192(%rsp), %r15 # 8-byte Reload movq %r15, %rdi xorl %esi, %esi callq memset@PLT movl $4000000, %edx # imm = 0x3D0900 movq 184(%rsp), %rbp # 8-byte Reload movq %rbp, %rdi xorl %esi, %esi callq memset@PLT movl $4000000, %edx # imm = 0x3D0900 movq 136(%rsp), %rdi # 8-byte Reload xorl %esi, %esi callq memset@PLT movl $4000000, %edx # imm = 0x3D0900 movq 176(%rsp), %rdi # 8-byte Reload xorl %esi, %esi callq memset@PLT movl $4000000, %edx # imm = 0x3D0900 movq %rbx, %rdi xorl %esi, %esi callq memset@PLT movq $0, 56(%rsp) movq $0, 48(%rsp) movq $0, (%rsp) leaq 56(%rsp), %rdi movl $4000000, %esi # imm = 0x3D0900 callq hipMalloc testl %eax, %eax jne .LBB10_64 # %bb.9: # %_Z8cuAssert10hipError_t.exit leaq 48(%rsp), %rdi movl $4000000, %esi # imm = 0x3D0900 callq hipMalloc testl %eax, %eax jne .LBB10_64 # %bb.10: # %_Z8cuAssert10hipError_t.exit131 movq %r13, %r12 movq %rsp, %rdi movl $4000000, %esi # imm = 0x3D0900 callq hipMalloc testl %eax, %eax jne .LBB10_64 # %bb.11: # %_Z8cuAssert10hipError_t.exit134 movq 56(%rsp), %rdi movl $4000000, %edx # imm = 0x3D0900 movq %r12, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax jne .LBB10_64 # %bb.12: # %_Z8cuAssert10hipError_t.exit137 movq 48(%rsp), %rdi movl $4000000, %edx # imm = 0x3D0900 movq %r14, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax jne .LBB10_64 # %bb.13: # %_Z8cuAssert10hipError_t.exit140 movq (%rsp), %rdi movl $1000, %esi # imm = 0x3E8 callq _Z9memsetGPUPii leaq 32(%rsp), %rsi movl $1, %edi callq clock_gettime movabsq $4294967297000, %rdi # imm = 0x3E8000003E8 movabsq $4294967297, %rdx # imm = 0x100000001 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_15 # %bb.14: movq 56(%rsp), %rax movq 48(%rsp), %rcx movq (%rsp), %rdx movq %rax, 128(%rsp) movq %rcx, 120(%rsp) movq %rdx, 112(%rsp) movl $1000, 12(%rsp) # imm = 0x3E8 leaq 128(%rsp), %rax movq %rax, 144(%rsp) leaq 120(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 12(%rsp), %rax movq %rax, 168(%rsp) leaq 96(%rsp), %rdi leaq 80(%rsp), %rsi leaq 72(%rsp), %rdx leaq 64(%rsp), %rcx callq __hipPopCallConfiguration movq 96(%rsp), %rsi movl 104(%rsp), %edx movq 80(%rsp), %rcx movl 88(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z5naivePiS_S_i, %edi pushq 64(%rsp) .cfi_adjust_cfa_offset 8 pushq 80(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_15: callq hipDeviceSynchronize testl %eax, %eax jne .LBB10_64 # %bb.16: # %_Z8cuAssert10hipError_t.exit143 leaq 16(%rsp), %rsi movl $1, %edi callq clock_gettime cvtsi2sdq 16(%rsp), %xmm1 cvtsi2sdq 24(%rsp), %xmm0 movsd .LCPI10_0(%rip), %xmm4 # xmm4 = mem[0],zero mulsd %xmm4, %xmm0 cvtsi2sdq 32(%rsp), %xmm2 cvtsi2sdq 40(%rsp), %xmm3 addsd %xmm1, %xmm0 mulsd %xmm4, %xmm3 addsd %xmm2, %xmm3 subsd %xmm3, %xmm0 movl $.L.str.3, %edi movl $.L.str.5, %esi movb $1, %al callq printf callq hipGetLastError testl %eax, %eax jne .LBB10_64 # %bb.17: # %_Z8cuAssert10hipError_t.exit146 movq (%rsp), %rsi movl $4000000, %edx # imm = 0x3D0900 movq %r15, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax jne .LBB10_64 # %bb.18: # %_Z8cuAssert10hipError_t.exit149 movq (%rsp), %rdi movl $1000, %esi # imm = 0x3E8 callq _Z9memsetGPUPii leaq 32(%rsp), %rsi movl $1, %edi callq clock_gettime movabsq $137438953504, %rdi # imm = 0x2000000020 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_20 # %bb.19: movq 56(%rsp), %rax movq 48(%rsp), %rcx movq (%rsp), %rdx movq %rax, 128(%rsp) movq %rcx, 120(%rsp) movq %rdx, 112(%rsp) movl $1000, 12(%rsp) # imm = 0x3E8 leaq 128(%rsp), %rax movq %rax, 144(%rsp) leaq 120(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 12(%rsp), %rax movq %rax, 168(%rsp) leaq 96(%rsp), %rdi leaq 80(%rsp), %rsi leaq 72(%rsp), %rdx leaq 64(%rsp), %rcx callq __hipPopCallConfiguration movq 96(%rsp), %rsi movl 104(%rsp), %edx movq 80(%rsp), %rcx movl 88(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z5naivePiS_S_i, %edi pushq 64(%rsp) .cfi_adjust_cfa_offset 8 pushq 80(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_20: callq hipDeviceSynchronize testl %eax, %eax jne .LBB10_64 # %bb.21: # %_Z8cuAssert10hipError_t.exit158 leaq 16(%rsp), %rsi movl $1, %edi callq clock_gettime xorps %xmm1, %xmm1 cvtsi2sdq 16(%rsp), %xmm1 xorps %xmm0, %xmm0 cvtsi2sdq 24(%rsp), %xmm0 movsd .LCPI10_0(%rip), %xmm4 # xmm4 = mem[0],zero mulsd %xmm4, %xmm0 xorps %xmm2, %xmm2 cvtsi2sdq 32(%rsp), %xmm2 xorps %xmm3, %xmm3 cvtsi2sdq 40(%rsp), %xmm3 addsd %xmm1, %xmm0 mulsd %xmm4, %xmm3 addsd %xmm2, %xmm3 subsd %xmm3, %xmm0 movl $.L.str.3, %edi movl $.L.str.6, %esi movb $1, %al callq printf movq (%rsp), %rsi movl $4000000, %edx # imm = 0x3D0900 movq %rbp, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax jne .LBB10_64 # %bb.22: # %_Z8cuAssert10hipError_t.exit161 movabsq $270582939711, %r15 # imm = 0x3F0000003F movabsq $68719476752, %rbp # imm = 0x1000000010 movq (%rsp), %rdi movl $1000, %esi # imm = 0x3E8 callq _Z9memsetGPUPii leaq 32(%rsp), %rsi movl $1, %edi callq clock_gettime movq %r15, %rdi movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_24 # %bb.23: movq 56(%rsp), %rax movq 48(%rsp), %rcx movq (%rsp), %rdx movq %rax, 128(%rsp) movq %rcx, 120(%rsp) movq %rdx, 112(%rsp) movl $1000, 12(%rsp) # imm = 0x3E8 leaq 128(%rsp), %rax movq %rax, 144(%rsp) leaq 120(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 12(%rsp), %rax movq %rax, 168(%rsp) leaq 96(%rsp), %rdi leaq 80(%rsp), %rsi leaq 72(%rsp), %rdx leaq 64(%rsp), %rcx callq __hipPopCallConfiguration movq 96(%rsp), %rsi movl 104(%rsp), %edx movq 80(%rsp), %rcx movl 88(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z5naivePiS_S_i, %edi pushq 64(%rsp) .cfi_adjust_cfa_offset 8 pushq 80(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_24: callq hipDeviceSynchronize testl %eax, %eax jne .LBB10_64 # %bb.25: # %_Z8cuAssert10hipError_t.exit170 leaq 16(%rsp), %rsi movl $1, %edi callq clock_gettime xorps %xmm1, %xmm1 cvtsi2sdq 16(%rsp), %xmm1 xorps %xmm0, %xmm0 cvtsi2sdq 24(%rsp), %xmm0 movsd .LCPI10_0(%rip), %xmm4 # xmm4 = mem[0],zero mulsd %xmm4, %xmm0 xorps %xmm2, %xmm2 cvtsi2sdq 32(%rsp), %xmm2 xorps %xmm3, %xmm3 cvtsi2sdq 40(%rsp), %xmm3 addsd %xmm1, %xmm0 mulsd %xmm4, %xmm3 addsd %xmm2, %xmm3 subsd %xmm3, %xmm0 movl $.L.str.3, %edi movl $.L.str.7, %esi movb $1, %al callq printf movq (%rsp), %rsi movl $4000000, %edx # imm = 0x3D0900 movq 136(%rsp), %rdi # 8-byte Reload movl $2, %ecx callq hipMemcpy testl %eax, %eax jne .LBB10_64 # %bb.26: # %_Z8cuAssert10hipError_t.exit173 movq (%rsp), %rdi movl $1000, %esi # imm = 0x3E8 callq _Z9memsetGPUPii leaq 32(%rsp), %rsi movl $1, %edi callq clock_gettime movq %r15, %rdi movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_28 # %bb.27: movq 56(%rsp), %rax movq 48(%rsp), %rcx movq (%rsp), %rdx movq %rax, 128(%rsp) movq %rcx, 120(%rsp) movq %rdx, 112(%rsp) movl $1000, 12(%rsp) # imm = 0x3E8 leaq 128(%rsp), %rax movq %rax, 144(%rsp) leaq 120(%rsp), %rax movq %rax, 152(%rsp) leaq 112(%rsp), %rax movq %rax, 160(%rsp) leaq 12(%rsp), %rax movq %rax, 168(%rsp) leaq 96(%rsp), %rdi leaq 80(%rsp), %rsi leaq 72(%rsp), %rdx leaq 64(%rsp), %rcx callq __hipPopCallConfiguration movq 96(%rsp), %rsi movl 104(%rsp), %edx movq 80(%rsp), %rcx movl 88(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z6commonPiS_S_i, %edi pushq 64(%rsp) .cfi_adjust_cfa_offset 8 pushq 80(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_28: callq hipDeviceSynchronize testl %eax, %eax movq 192(%rsp), %r13 # 8-byte Reload movq 184(%rsp), %rbp # 8-byte Reload jne .LBB10_64 # %bb.29: # %_Z8cuAssert10hipError_t.exit182 leaq 16(%rsp), %rsi movl $1, %edi callq clock_gettime xorps %xmm1, %xmm1 cvtsi2sdq 16(%rsp), %xmm1 xorps %xmm0, %xmm0 cvtsi2sdq 24(%rsp), %xmm0 movsd .LCPI10_0(%rip), %xmm4 # xmm4 = mem[0],zero mulsd %xmm4, %xmm0 xorps %xmm2, %xmm2 cvtsi2sdq 32(%rsp), %xmm2 xorps %xmm3, %xmm3 cvtsi2sdq 40(%rsp), %xmm3 addsd %xmm1, %xmm0 mulsd %xmm4, %xmm3 addsd %xmm2, %xmm3 subsd %xmm3, %xmm0 movl $.L.str.3, %edi movl $.L.str.8, %esi movb $1, %al callq printf movq (%rsp), %rsi movl $4000000, %edx # imm = 0x3D0900 movq 176(%rsp), %rdi # 8-byte Reload movl $2, %ecx callq hipMemcpy testl %eax, %eax jne .LBB10_64 # %bb.30: # %_Z8cuAssert10hipError_t.exit185 movq (%rsp), %rdi movl $1000, %esi # imm = 0x3E8 callq _Z9memsetGPUPii movq 56(%rsp), %rdi callq hipFree testl %eax, %eax jne .LBB10_64 # %bb.31: # %_Z8cuAssert10hipError_t.exit188 movq 48(%rsp), %rdi callq hipFree testl %eax, %eax jne .LBB10_64 # %bb.32: # %_Z8cuAssert10hipError_t.exit191 movq (%rsp), %rdi callq hipFree testl %eax, %eax jne .LBB10_64 # %bb.33: # %_Z8cuAssert10hipError_t.exit194 leaq 32(%rsp), %rsi movl $1, %edi callq clock_gettime xorl %eax, %eax movq %r12, %rcx .p2align 4, 0x90 .LBB10_34: # %.preheader23.i # =>This Loop Header: Depth=1 # Child Loop BB10_35 Depth 2 # Child Loop BB10_36 Depth 3 imulq $4000, %rax, %rdx # imm = 0xFA0 addq %rbx, %rdx movq %r14, %rsi xorl %edi, %edi .p2align 4, 0x90 .LBB10_35: # %.preheader.i195 # Parent Loop BB10_34 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB10_36 Depth 3 movl (%rdx,%rdi,4), %r8d movq %rsi, %r9 xorl %r10d, %r10d .p2align 4, 0x90 .LBB10_36: # Parent Loop BB10_34 Depth=1 # Parent Loop BB10_35 Depth=2 # => This Inner Loop Header: Depth=3 movl (%r9), %r11d imull (%rcx,%r10,4), %r11d addl %r11d, %r8d incq %r10 addq $4000, %r9 # imm = 0xFA0 cmpq $1000, %r10 # imm = 0x3E8 jne .LBB10_36 # %bb.37: # %._crit_edge.i199 # in Loop: Header=BB10_35 Depth=2 movl %r8d, (%rdx,%rdi,4) incq %rdi addq $4, %rsi cmpq $1000, %rdi # imm = 0x3E8 jne .LBB10_35 # %bb.38: # %._crit_edge26.i # in Loop: Header=BB10_34 Depth=1 incq %rax addq $4000, %rcx # imm = 0xFA0 cmpq $1000, %rax # imm = 0x3E8 jne .LBB10_34 # %bb.39: # %_Z10matrixMultPiS_S_i.exit leaq 16(%rsp), %rsi movl $1, %edi callq clock_gettime cvtsi2sdq 16(%rsp), %xmm1 xorps %xmm0, %xmm0 cvtsi2sdq 24(%rsp), %xmm0 movsd .LCPI10_0(%rip), %xmm4 # xmm4 = mem[0],zero mulsd %xmm4, %xmm0 cvtsi2sdq 32(%rsp), %xmm2 cvtsi2sdq 40(%rsp), %xmm3 addsd %xmm1, %xmm0 mulsd %xmm4, %xmm3 addsd %xmm2, %xmm3 subsd %xmm3, %xmm0 movl $.L.str.3, %edi movl $.L.str.9, %esi movb $1, %al callq printf leaq 4(%rbx), %rax movq %r13, %rcx addq $4, %rcx xorl %esi, %esi xorl %edx, %edx .LBB10_40: # %.preheader.i200 # =>This Loop Header: Depth=1 # Child Loop BB10_42 Depth 2 imulq $4000, %rsi, %rdi # imm = 0xFA0 movl (%r13,%rdi), %r8d cmpl (%rbx,%rdi), %r8d jne .LBB10_45 # %bb.41: # %.lr.ph.preheader # in Loop: Header=BB10_40 Depth=1 xorl %edi, %edi .p2align 4, 0x90 .LBB10_42: # %.lr.ph # Parent Loop BB10_40 Depth=1 # => This Inner Loop Header: Depth=2 cmpq $999, %rdi # imm = 0x3E7 je .LBB10_44 # %bb.43: # in Loop: Header=BB10_42 Depth=2 movl (%rcx,%rdi,4), %r8d leaq 1(%rdi), %r9 cmpl (%rax,%rdi,4), %r8d movq %r9, %rdi je .LBB10_42 jmp .LBB10_45 .p2align 4, 0x90 .LBB10_44: # %.critedge.i # in Loop: Header=BB10_40 Depth=1 cmpq $999, %rsi # imm = 0x3E7 leaq 1(%rsi), %rdi setae %dl addq $4000, %rax # imm = 0xFA0 addq $4000, %rcx # imm = 0xFA0 movq %rdi, %rsi cmpq $1000, %rdi # imm = 0x3E8 jne .LBB10_40 .LBB10_45: # %_Z8validatePKiS0_i.exit movl $.L.str.11, %eax movl $.L.str.12, %esi testb $1, %dl cmovneq %rax, %rsi xorl %r15d, %r15d movl $.L.str.10, %edi xorl %eax, %eax callq printf leaq 4(%rbx), %rax movq %rbp, %rcx addq $4, %rcx xorl %edx, %edx .LBB10_46: # %.preheader.i206 # =>This Loop Header: Depth=1 # Child Loop BB10_48 Depth 2 imulq $4000, %r15, %rsi # imm = 0xFA0 movl (%rbp,%rsi), %edi cmpl (%rbx,%rsi), %edi jne .LBB10_51 # %bb.47: # %.lr.ph314.preheader # in Loop: Header=BB10_46 Depth=1 xorl %esi, %esi .p2align 4, 0x90 .LBB10_48: # %.lr.ph314 # Parent Loop BB10_46 Depth=1 # => This Inner Loop Header: Depth=2 cmpq $999, %rsi # imm = 0x3E7 je .LBB10_50 # %bb.49: # in Loop: Header=BB10_48 Depth=2 movl (%rcx,%rsi,4), %edi leaq 1(%rsi), %r8 cmpl (%rax,%rsi,4), %edi movq %r8, %rsi je .LBB10_48 jmp .LBB10_51 .p2align 4, 0x90 .LBB10_50: # %.critedge.i211 # in Loop: Header=BB10_46 Depth=1 cmpq $999, %r15 # imm = 0x3E7 leaq 1(%r15), %rsi setae %dl addq $4000, %rax # imm = 0xFA0 addq $4000, %rcx # imm = 0xFA0 movq %rsi, %r15 cmpq $1000, %rsi # imm = 0x3E8 jne .LBB10_46 .LBB10_51: # %_Z8validatePKiS0_i.exit219 movl $.L.str.11, %eax movl $.L.str.12, %esi testb $1, %dl cmovneq %rax, %rsi xorl %r15d, %r15d movl $.L.str.13, %edi xorl %eax, %eax callq printf leaq 4(%rbx), %rax movq 136(%rsp), %rcx # 8-byte Reload addq $4, %rcx xorl %edx, %edx .LBB10_52: # %.preheader.i220 # =>This Loop Header: Depth=1 # Child Loop BB10_54 Depth 2 imulq $4000, %r15, %rsi # imm = 0xFA0 movq 136(%rsp), %rdi # 8-byte Reload movl (%rdi,%rsi), %edi cmpl (%rbx,%rsi), %edi jne .LBB10_57 # %bb.53: # %.lr.ph319.preheader # in Loop: Header=BB10_52 Depth=1 xorl %esi, %esi .p2align 4, 0x90 .LBB10_54: # %.lr.ph319 # Parent Loop BB10_52 Depth=1 # => This Inner Loop Header: Depth=2 cmpq $999, %rsi # imm = 0x3E7 je .LBB10_56 # %bb.55: # in Loop: Header=BB10_54 Depth=2 movl (%rcx,%rsi,4), %edi leaq 1(%rsi), %r8 cmpl (%rax,%rsi,4), %edi movq %r8, %rsi je .LBB10_54 jmp .LBB10_57 .p2align 4, 0x90 .LBB10_56: # %.critedge.i225 # in Loop: Header=BB10_52 Depth=1 cmpq $999, %r15 # imm = 0x3E7 leaq 1(%r15), %rsi setae %dl addq $4000, %rax # imm = 0xFA0 addq $4000, %rcx # imm = 0xFA0 movq %rsi, %r15 cmpq $1000, %rsi # imm = 0x3E8 jne .LBB10_52 .LBB10_57: # %_Z8validatePKiS0_i.exit233 movl $.L.str.11, %eax movl $.L.str.12, %esi testb $1, %dl cmovneq %rax, %rsi xorl %r15d, %r15d movl $.L.str.14, %edi xorl %eax, %eax callq printf movq %rbx, %rax addq $4, %rax movq 176(%rsp), %r9 # 8-byte Reload movq %r9, %rcx addq $4, %rcx xorl %edx, %edx .LBB10_58: # %.preheader.i234 # =>This Loop Header: Depth=1 # Child Loop BB10_60 Depth 2 imulq $4000, %r15, %rsi # imm = 0xFA0 movl (%r9,%rsi), %edi cmpl (%rbx,%rsi), %edi jne .LBB10_63 # %bb.59: # %.lr.ph324.preheader # in Loop: Header=BB10_58 Depth=1 xorl %esi, %esi .p2align 4, 0x90 .LBB10_60: # %.lr.ph324 # Parent Loop BB10_58 Depth=1 # => This Inner Loop Header: Depth=2 cmpq $999, %rsi # imm = 0x3E7 je .LBB10_62 # %bb.61: # in Loop: Header=BB10_60 Depth=2 movl (%rcx,%rsi,4), %edi leaq 1(%rsi), %r8 cmpl (%rax,%rsi,4), %edi movq %r8, %rsi je .LBB10_60 jmp .LBB10_63 .p2align 4, 0x90 .LBB10_62: # %.critedge.i239 # in Loop: Header=BB10_58 Depth=1 cmpq $999, %r15 # imm = 0x3E7 leaq 1(%r15), %rsi setae %dl addq $4000, %rax # imm = 0xFA0 addq $4000, %rcx # imm = 0xFA0 movq %rsi, %r15 cmpq $1000, %rsi # imm = 0x3E8 jne .LBB10_58 .LBB10_63: # %_Z8validatePKiS0_i.exit247 movl $.L.str.11, %eax movl $.L.str.12, %esi testb $1, %dl cmovneq %rax, %rsi movl $.L.str.15, %edi xorl %eax, %eax callq printf movq %r12, %rdi callq free movq %r14, %rdi callq free movq %r13, %rdi callq free movq %rbp, %rdi callq free movq 136(%rsp), %rdi # 8-byte Reload callq free xorl %eax, %eax addq $200, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB10_64: .cfi_def_cfa_offset 256 movl %eax, %edi callq hipGetErrorString movq %rax, %rdi callq puts@PLT xorl %edi, %edi callq exit .Lfunc_end10: .size main, .Lfunc_end10-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB11_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB11_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15memsetGPUKernelPii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5naivePiS_S_i, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6commonPiS_S_i, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end11: .size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB12_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB12_2: retq .Lfunc_end12: .size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%d " .size .L.str, 4 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "%s %.5f seconds\n" .size .L.str.3, 17 .type _Z15memsetGPUKernelPii,@object # @_Z15memsetGPUKernelPii .section .rodata,"a",@progbits .globl _Z15memsetGPUKernelPii .p2align 3, 0x0 _Z15memsetGPUKernelPii: .quad _Z30__device_stub__memsetGPUKernelPii .size _Z15memsetGPUKernelPii, 8 .type _Z5naivePiS_S_i,@object # @_Z5naivePiS_S_i .globl _Z5naivePiS_S_i .p2align 3, 0x0 _Z5naivePiS_S_i: .quad _Z20__device_stub__naivePiS_S_i .size _Z5naivePiS_S_i, 8 .type _Z6commonPiS_S_i,@object # @_Z6commonPiS_S_i .globl _Z6commonPiS_S_i .p2align 3, 0x0 _Z6commonPiS_S_i: .quad _Z21__device_stub__commonPiS_S_i .size _Z6commonPiS_S_i, 8 .type .L.str.4,@object # @.str.4 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.4: .asciz "Matrix size %d*%d\n" .size .L.str.4, 19 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "GPU 01x01/v1" .size .L.str.5, 13 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "GPU 32x32/v1" .size .L.str.6, 13 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "GPU 16x16/v1" .size .L.str.7, 13 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "GPU 16x16/v2" .size .L.str.8, 13 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "CPU " .size .L.str.9, 13 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "validate 01x01/v1 / cpu = %s\n" .size .L.str.10, 30 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "true" .size .L.str.11, 5 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz "false" .size .L.str.12, 6 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz "validate 32x32/v1 / cpu = %s\n" .size .L.str.13, 30 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz "validate 16x16/v1 / cpu = %s\n" .size .L.str.14, 30 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "validate 16x16/v2 / cpu = %s\n" .size .L.str.15, 30 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15memsetGPUKernelPii" .size .L__unnamed_1, 23 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z5naivePiS_S_i" .size .L__unnamed_2, 16 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z6commonPiS_S_i" .size .L__unnamed_3, 17 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__memsetGPUKernelPii .addrsig_sym _Z20__device_stub__naivePiS_S_i .addrsig_sym _Z21__device_stub__commonPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15memsetGPUKernelPii .addrsig_sym _Z5naivePiS_S_i .addrsig_sym _Z6commonPiS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
9,905
12,694
8,340
20,753
118
code for sm_80 Function : _Z13blurImgKernelP6uchar3iiPfiS0_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.Y ; S2R R3, SR_TID.Y ; S2R R11, SR_CTAID.X ; S2R R2, SR_TID.X ; IMAD R0, R0, c[0x0][0x4], R3 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; IMAD R11, R11, c[0x0][0x0], R2 ; ISETP.GE.OR P0, PT, R11, c[0x0][0x168], P0 ; @P0 EXIT ; IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x178] ; ULDC.64 UR8, c[0x0][0x118] ; HFMA2.MMA R20, -RZ, RZ, 0, 0 ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; MOV R24, RZ ; ISETP.GE.AND P0, PT, R13, 0x1, PT ; @!P0 BRA 0xae0 ; LEA.HI R2, R13.reuse, c[0x0][0x178], RZ, 0x1 ; UMOV UR5, 0x1 ; IADD3 R25, R13.reuse, -0x1, RZ ; ULDC.64 UR6, c[0x0][0x168] ; SHF.R.S32.HI R2, RZ, 0x1, R2 ; IMAD.MOV.U32 R24, RZ, RZ, RZ ; LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; MOV R14, RZ ; IMAD.IADD R17, R0, 0x1, -R2 ; MOV R20, RZ ; UIADD3 UR4, -UR5, UR7, URZ ; IADD3 R15, -R13, c[0x0][0x178], RZ ; UIADD3 UR5, -UR5, UR6, URZ ; IADD3 R19, R11, -R2, RZ ; IMAD.IADD R2, R17, 0x1, R14 ; ISETP.GE.U32.AND P3, PT, R25, 0x3, PT ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; MOV R21, R14 ; IMNMX R2, RZ, R2, !PT ; IADD3 R14, R14, 0x1, RZ ; ISETP.GE.AND P2, PT, R2.reuse, c[0x0][0x16c], PT ; ISETP.NE.AND P0, PT, R13, RZ, PT ; SEL R16, R2, UR4, !P2 ; ISETP.GE.AND P1, PT, R14, c[0x0][0x178], PT ; @!P3 BRA 0x750 ; HFMA2.MMA R10, -RZ, RZ, 0, 0 ; IMAD.MOV.U32 R12, RZ, RZ, R15 ; IADD3 R9, R19, R10, RZ ; IMAD.MOV.U32 R8, RZ, RZ, 0x3 ; IMNMX R2, RZ, R9, !PT ; ISETP.GE.AND P2, PT, R2, c[0x0][0x168], PT ; SEL R3, R2, UR5, !P2 ; IMAD R3, R16, c[0x0][0x168], R3 ; IMAD.WIDE R6, R3, R8, c[0x0][0x160] ; LDG.E.U8 R4, [R6.64] ; MOV R3, 0x4 ; IMAD R2, R21, c[0x0][0x178], R10 ; IADD3 R5, R9, 0x1, RZ ; LDG.E.U8 R29, [R6.64+0x1] ; IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; LDG.E.U8 R26, [R6.64+0x2] ; LDG.E R27, [R2.64] ; IMNMX R5, RZ, R5, !PT ; LDG.E R23, [R2.64+0x4] ; ISETP.GE.AND P2, PT, R5, c[0x0][0x168], PT ; SEL R5, R5, UR5, !P2 ; IMAD R5, R16, c[0x0][0x168], R5 ; I2F.U16 R22, R4 ; IMAD.WIDE R4, R5, R8, c[0x0][0x160] ; LDG.E.U8 R28, [R4.64] ; FFMA R24, R22, R27, R24 ; LDG.E.U8 R22, [R4.64+0x1] ; IADD3 R6, R9.reuse, 0x2, RZ ; IADD3 R9, R9, 0x3, RZ ; IMNMX R6, RZ, R6, !PT ; I2F.U16 R29, R29 ; IMNMX R9, RZ, R9, !PT ; ISETP.GE.AND P2, PT, R6.reuse, c[0x0][0x168], PT ; LDG.E.U8 R4, [R4.64+0x2] ; SEL R7, R6, UR5, !P2 ; I2F.U16 R26, R26 ; ISETP.GE.AND P2, PT, R9, c[0x0][0x168], PT ; SEL R9, R9, UR5, !P2 ; IMAD R7, R16.reuse, c[0x0][0x168], R7 ; LDG.E R5, [R2.64+0xc] ; IMAD R9, R16, c[0x0][0x168], R9 ; IMAD.WIDE R6, R7, R8, c[0x0][0x160] ; FFMA R18, R27, R29, R18 ; IMAD.WIDE R8, R9, R8, c[0x0][0x160] ; LDG.E R29, [R2.64+0x8] ; FFMA R20, R27, R26, R20 ; LDG.E.U8 R26, [R6.64] ; LDG.E.U8 R27, [R6.64+0x1] ; LDG.E.U8 R2, [R8.64] ; I2F.U16 R28, R28 ; I2F.U16 R22, R22 ; FFMA R24, R28, R23, R24 ; LDG.E.U8 R28, [R6.64+0x2] ; FFMA R18, R23, R22, R18 ; LDG.E.U8 R22, [R8.64+0x1] ; LDG.E.U8 R8, [R8.64+0x2] ; I2F.U16 R4, R4 ; IADD3 R12, R12, -0x4, RZ ; I2F.U16 R26, R26 ; ISETP.NE.AND P2, PT, R12, RZ, PT ; I2F.U16 R27, R27 ; I2F.U16 R7, R2 ; FFMA R20, R23, R4, R20 ; FFMA R24, R26, R29, R24 ; IADD3 R10, R10, 0x4, RZ ; FFMA R18, R29, R27, R18 ; FFMA R24, R7, R5, R24 ; I2F.U16 R28, R28 ; I2F.U16 R22, R22 ; I2F.U16 R6, R8 ; FFMA R20, R29, R28, R20 ; FFMA R18, R5.reuse, R22, R18 ; FFMA R20, R5, R6, R20 ; @P2 BRA 0x2d0 ; @!P0 BRA 0xad0 ; IMAD.IADD R7, R19, 0x1, R10 ; MOV R6, 0x3 ; IMNMX R2, RZ, R7, !PT ; ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; SEL R3, R2, UR5, !P0 ; IMAD R3, R16, c[0x0][0x168], R3 ; IMAD.WIDE R2, R3, R6, c[0x0][0x160] ; LDG.E.U8 R8, [R2.64] ; LDG.E.U8 R12, [R2.64+0x1] ; LDG.E.U8 R22, [R2.64+0x2] ; IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; IMAD R4, R21, c[0x0][0x178], R10 ; IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; LDG.E R21, [R4.64] ; ISETP.NE.AND P0, PT, R13, 0x1, PT ; I2F.U16 R9, R8 ; I2F.U16 R12, R12 ; I2F.U16 R22, R22 ; FFMA R24, R9, R21, R24 ; FFMA R18, R21.reuse, R12, R18 ; FFMA R20, R21, R22, R20 ; @!P0 BRA 0xad0 ; ISETP.NE.AND P2, PT, R13, 0x2, PT ; LDG.E R21, [R4.64+0x4] ; IADD3 R2, R7, 0x1, RZ ; IMNMX R2, RZ, R2, !PT ; ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; @P2 IADD3 R7, R7, 0x2, RZ ; @P2 LDG.E R27, [R4.64+0x8] ; SEL R3, R2, UR5, !P0 ; @P2 IMNMX R7, RZ, R7, !PT ; IMAD R3, R16, c[0x0][0x168], R3 ; @P2 ISETP.GE.AND P3, PT, R7, c[0x0][0x168], PT ; IMAD.WIDE R2, R3, R6, c[0x0][0x160] ; @P2 SEL R7, R7, UR5, !P3 ; LDG.E.U8 R8, [R2.64] ; @P2 IMAD R7, R16, c[0x0][0x168], R7 ; LDG.E.U8 R10, [R2.64+0x1] ; @P2 IMAD.WIDE R6, R7, R6, c[0x0][0x160] ; LDG.E.U8 R12, [R2.64+0x2] ; @P2 LDG.E.U8 R16, [R6.64] ; @P2 LDG.E.U8 R22, [R6.64+0x1] ; @P2 LDG.E.U8 R26, [R6.64+0x2] ; I2F.U16 R9, R8 ; I2F.U16 R10, R10 ; I2F.U16 R12, R12 ; @P2 I2F.U16 R23, R16 ; @P2 I2F.U16 R22, R22 ; @P2 I2F.U16 R26, R26 ; FFMA R24, R9, R21, R24 ; FFMA R18, R21.reuse, R10, R18 ; FFMA R20, R21, R12, R20 ; @P2 FFMA R24, R23, R27, R24 ; @P2 FFMA R18, R27.reuse, R22, R18 ; @P2 FFMA R20, R27, R26, R20 ; @!P1 BRA 0x200 ; F2I.U32.TRUNC.NTZ R5, R24 ; MOV R3, 0x3 ; IMAD R2, R0, c[0x0][0x168], R11 ; IMAD.WIDE R2, R2, R3, c[0x0][0x180] ; F2I.U32.TRUNC.NTZ R7, R18 ; F2I.U32.TRUNC.NTZ R9, R20 ; STG.E.U8 [R2.64], R5 ; STG.E.U8 [R2.64+0x1], R7 ; STG.E.U8 [R2.64+0x2], R9 ; EXIT ; BRA 0xb80; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0003524c_00000000-6_e242fabb7ad2b0f310afe5f576785cf6a98722d2.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2074: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2074: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "r" .LC1: .string "Cannot read %s\n" .LC2: .string "%s" .LC3: .string "P3" .LC4: .string "%i" .LC5: .string "%hhu%hhu%hhu" .text .globl _Z7readPnmPcRiS0_RP6uchar3 .type _Z7readPnmPcRiS0_RP6uchar3, @function _Z7readPnmPcRiS0_RP6uchar3: .LFB2066: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $24, %rsp .cfi_def_cfa_offset 80 movq %rdi, %rbx movq %rsi, %r12 movq %rdx, %r13 movq %rcx, %r14 movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax leaq .LC0(%rip), %rsi call fopen@PLT testq %rax, %rax je .L12 movq %rax, %rbp leaq 5(%rsp), %r15 movq %r15, %rdx leaq .LC2(%rip), %rsi movq %rax, %rdi movl $0, %eax call __isoc23_fscanf@PLT leaq .LC3(%rip), %rsi movq %r15, %rdi call strcmp@PLT testl %eax, %eax jne .L13 movq %r12, %rdx leaq .LC4(%rip), %r15 movq %r15, %rsi movq %rbp, %rdi movl $0, %eax call __isoc23_fscanf@PLT movq %r13, %rdx movq %r15, %rsi movq %rbp, %rdi movl $0, %eax call __isoc23_fscanf@PLT movq %rsp, %rdx movq %r15, %rsi movq %rbp, %rdi movl $0, %eax call __isoc23_fscanf@PLT cmpl $255, (%rsp) jg .L14 movl (%r12), %eax imull 0(%r13), %eax cltq leaq (%rax,%rax,2), %rdi call malloc@PLT movq %rax, (%r14) movl (%r12), %eax imull 0(%r13), %eax testl %eax, %eax jle .L7 movl $0, %ebx leaq .LC5(%rip), %r15 .L8: leaq (%rbx,%rbx,2), %rdx addq (%r14), %rdx leaq 1(%rdx), %rcx leaq 2(%rdx), %r8 movq %r15, %rsi movq %rbp, %rdi movl $0, %eax call __isoc23_fscanf@PLT addq $1, %rbx movl (%r12), %eax imull 0(%r13), %eax cmpl %ebx, %eax jg .L8 .L7: movq %rbp, %rdi call fclose@PLT movq 8(%rsp), %rax subq %fs:40, %rax jne .L15 addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L12: .cfi_restore_state movq %rbx, %rdx leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %edi call exit@PLT .L13: movq %rbp, %rdi call fclose@PLT movq %rbx, %rdx leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %edi call exit@PLT .L14: movq %rbp, %rdi call fclose@PLT movq %rbx, %rdx leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %edi call exit@PLT .L15: call __stack_chk_fail@PLT .cfi_endproc .LFE2066: .size _Z7readPnmPcRiS0_RP6uchar3, .-_Z7readPnmPcRiS0_RP6uchar3 .section .rodata.str1.1 .LC6: .string "w" .LC7: .string "Cannot write %s\n" .LC8: .string "P3\n%i\n%i\n255\n" .LC9: .string "%hhu\n%hhu\n%hhu\n" .text .globl _Z8writePnmP6uchar3iiPc .type _Z8writePnmP6uchar3iiPc, @function _Z8writePnmP6uchar3iiPc: .LFB2067: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 movq %rdi, %r12 movl %esi, %ebx movl %edx, %r13d movq %rcx, %r14 leaq .LC6(%rip), %rsi movq %rcx, %rdi call fopen@PLT testq %rax, %rax je .L22 movq %rax, %rbp movl %r13d, %r8d movl %ebx, %ecx leaq .LC8(%rip), %rdx movl $2, %esi movq %rax, %rdi movl $0, %eax call __fprintf_chk@PLT imull %r13d, %ebx movl %ebx, %r8d testl %ebx, %ebx jle .L18 movq %r12, %rbx movslq %r8d, %r8 leaq (%r8,%r8,2), %rax addq %rax, %r12 leaq .LC9(%rip), %r13 .L19: movzbl (%rbx), %ecx movzbl 2(%rbx), %r9d movzbl 1(%rbx), %r8d movq %r13, %rdx movl $2, %esi movq %rbp, %rdi movl $0, %eax call __fprintf_chk@PLT addq $3, %rbx cmpq %r12, %rbx jne .L19 .L18: movq %rbp, %rdi call fclose@PLT popq %rbx .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L22: .cfi_restore_state movq %r14, %rdx leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %edi call exit@PLT .cfi_endproc .LFE2067: .size _Z8writePnmP6uchar3iiPc, .-_Z8writePnmP6uchar3iiPc .globl _Z12computeErrorP6uchar3S0_i .type _Z12computeErrorP6uchar3S0_i, @function _Z12computeErrorP6uchar3S0_i: .LFB2069: .cfi_startproc endbr64 movl %edx, %r8d testl %edx, %edx jle .L26 movq %rdi, %rax movslq %edx, %rdx leaq (%rdx,%rdx,2), %rdx addq %rdx, %rdi pxor %xmm0, %xmm0 .L25: movzbl (%rax), %edx movzbl (%rsi), %ecx subl %ecx, %edx movl %edx, %ecx negl %ecx cmovns %ecx, %edx pxor %xmm1, %xmm1 cvtsi2ssl %edx, %xmm1 addss %xmm1, %xmm0 movzbl 1(%rax), %edx movzbl 1(%rsi), %ecx subl %ecx, %edx movl %edx, %ecx negl %ecx cmovns %ecx, %edx pxor %xmm1, %xmm1 cvtsi2ssl %edx, %xmm1 addss %xmm0, %xmm1 movzbl 2(%rax), %edx movzbl 2(%rsi), %ecx subl %ecx, %edx movl %edx, %ecx negl %ecx cmovns %ecx, %edx pxor %xmm0, %xmm0 cvtsi2ssl %edx, %xmm0 addss %xmm1, %xmm0 addq $3, %rax addq $3, %rsi cmpq %rdi, %rax jne .L25 .L24: leal (%r8,%r8,2), %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 divss %xmm1, %xmm0 ret .L26: pxor %xmm0, %xmm0 jmp .L24 .cfi_endproc .LFE2069: .size _Z12computeErrorP6uchar3S0_i, .-_Z12computeErrorP6uchar3S0_i .globl _Z9concatStrPKcS0_ .type _Z9concatStrPKcS0_, @function _Z9concatStrPKcS0_: .LFB2070: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $8, %rsp .cfi_def_cfa_offset 48 movq %rdi, %r12 movq %rsi, %rbp call strlen@PLT movq %rax, %rbx movq %rbp, %rdi call strlen@PLT leaq 1(%rbx,%rax), %r13 movq %r13, %rdi call malloc@PLT movq %rax, %rbx movq %r13, %rdx movq %r12, %rsi movq %rax, %rdi call __strcpy_chk@PLT movq %r13, %rdx movq %rbp, %rsi movq %rbx, %rdi call __strcat_chk@PLT addq $8, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2070: .size _Z9concatStrPKcS0_, .-_Z9concatStrPKcS0_ .globl _Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_ .type _Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_, @function _Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_: .LFB2096: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 40(%rsp) movl %esi, 36(%rsp) movl %edx, 32(%rsp) movq %rcx, 24(%rsp) movl %r8d, 20(%rsp) movq %r9, 8(%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 36(%rsp), %rax movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 20(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L34 .L30: movq 168(%rsp), %rax subq %fs:40, %rax jne .L35 addq $184, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L34: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 200 pushq 56(%rsp) .cfi_def_cfa_offset 208 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z13blurImgKernelP6uchar3iiPfiS0_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L30 .L35: call __stack_chk_fail@PLT .cfi_endproc .LFE2096: .size _Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_, .-_Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_ .globl _Z13blurImgKernelP6uchar3iiPfiS0_ .type _Z13blurImgKernelP6uchar3iiPfiS0_, @function _Z13blurImgKernelP6uchar3iiPfiS0_: .LFB2097: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2097: .size _Z13blurImgKernelP6uchar3iiPfiS0_, .-_Z13blurImgKernelP6uchar3iiPfiS0_ .section .rodata.str1.1 .LC11: .string "use device" .LC12: .string "use host" .LC13: .string "GPU name: %s\n" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC14: .string "GPU compute capability: %d.%d\n" .align 8 .LC15: .string "/home/ubuntu/Datasets/Stack_v2_cuda-hip/train/e242fabb7ad2b0f310afe5f576785cf6a98722d2.cu" .section .rodata.str1.1 .LC16: .string "Error: %s:%d, " .LC17: .string "code: %d, reason: %s\n" .LC18: .string "Sync kernel error: %s\n" .LC19: .string "Async kernel error: %s\n" .LC20: .string "Processing time (%s): %f ms\n" .text .globl _Z7blurImgP6uchar3iiPfiS0_b4dim3 .type _Z7blurImgP6uchar3iiPfiS0_b4dim3, @function _Z7blurImgP6uchar3iiPfiS0_b4dim3: .LFB2068: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA2068 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $1176, %rsp .cfi_def_cfa_offset 1232 movq %rdi, %rbp movl %esi, %ebx movl %edx, %r14d movq %rcx, 24(%rsp) movl %r8d, %r15d movl %r8d, 16(%rsp) movq %r9, 32(%rsp) movl 1232(%rsp), %r13d movl %r13d, 48(%rsp) movq %fs:40, %rax movq %rax, 1160(%rsp) xorl %eax, %eax leaq 112(%rsp), %rdi .LEHB0: call cudaEventCreate@PLT leaq 120(%rsp), %rdi call cudaEventCreate@PLT .LEHE0: movl $0, %esi movq 112(%rsp), %rdi .LEHB1: call cudaEventRecord@PLT testb %r13b, %r13b jne .L39 movl %r15d, %ecx shrl $31, %ecx movl %ecx, %eax movl %r15d, %ecx addl %r15d, %eax sarl %eax movl %eax, %edx testl %r14d, %r14d jle .L40 subl %eax, %ecx movl %ecx, %r12d movl %ecx, 44(%rsp) movl %r14d, %eax subl %edx, %eax movl %r15d, %ecx leal (%rax,%r15), %edi movslq %r15d, %r13 salq $2, %r13 movl $0, %esi movl %ebx, %eax subl %edx, %eax leal -1(%r14), %r15d leal -1(%rbx), %r9d movl %eax, 40(%rsp) jmp .L41 .L47: movslq %esi, %rax leaq (%rax,%rax,2), %rax movq 32(%rsp), %r10 addq %r10, %rax movl %edx, %r11d negl %r11d movl 44(%rsp), %r8d movl %esi, 52(%rsp) movl %edi, 56(%rsp) movl %edx, 60(%rsp) .L46: testl %ecx, %ecx jle .L65 movl %r12d, %esi subl %ecx, %esi movq 24(%rsp), %r10 pxor %xmm2, %xmm2 movaps %xmm2, %xmm3 movaps %xmm2, %xmm4 movq %rax, 8(%rsp) movl %r11d, %edi movl %ecx, 20(%rsp) .L43: testl %esi, %esi movl $0, %r11d cmovns %esi, %r11d cmpl %r11d, %r14d cmovle %r15d, %r11d imull %ebx, %r11d movq %r10, %rcx movl %edi, %edx movl %esi, 16(%rsp) .L45: testl %edx, %edx movl $0, %eax cmovns %edx, %eax cmpl %eax, %ebx cmovle %r9d, %eax movss (%rcx), %xmm1 addl %r11d, %eax cltq leaq (%rax,%rax,2), %rax addq %rbp, %rax movzbl (%rax), %esi pxor %xmm0, %xmm0 cvtsi2ssl %esi, %xmm0 mulss %xmm1, %xmm0 addss %xmm0, %xmm4 movzbl 1(%rax), %esi pxor %xmm0, %xmm0 cvtsi2ssl %esi, %xmm0 mulss %xmm1, %xmm0 addss %xmm0, %xmm3 movzbl 2(%rax), %eax pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 mulss %xmm1, %xmm0 addss %xmm0, %xmm2 addl $1, %edx addq $4, %rcx cmpl %r8d, %edx jne .L45 movl 16(%rsp), %esi addl $1, %esi addq %r13, %r10 cmpl %r12d, %esi jne .L43 movq 8(%rsp), %rax movl %edi, %r11d movl 20(%rsp), %ecx .L42: cvttss2sil %xmm4, %edx movb %dl, (%rax) cvttss2sil %xmm3, %edx movb %dl, 1(%rax) cvttss2sil %xmm2, %edx movb %dl, 2(%rax) addq $3, %rax addl $1, %r8d addl $1, %r11d movl 40(%rsp), %edi cmpl %edi, %r11d jne .L46 movl 52(%rsp), %esi movl 56(%rsp), %edi movl 60(%rsp), %edx .L48: addl %ebx, %esi addl $1, %r12d cmpl %edi, %r12d je .L40 .L41: testl %ebx, %ebx jg .L47 jmp .L48 .L65: pxor %xmm2, %xmm2 movaps %xmm2, %xmm3 movaps %xmm2, %xmm4 jmp .L42 .L39: leaq 128(%rsp), %rdi movl $0, %esi call cudaGetDeviceProperties_v2@PLT leaq 128(%rsp), %rdx leaq .LC13(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl 492(%rsp), %ecx movl 488(%rsp), %edx leaq .LC14(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl %r14d, %eax imull %ebx, %eax cltq leaq (%rax,%rax,2), %r15 leaq 72(%rsp), %rdi movq %r15, %rsi call cudaMalloc@PLT movl %eax, %r12d testl %eax, %eax jne .L73 leaq 80(%rsp), %rdi movq %r15, %rsi call cudaMalloc@PLT jmp .L74 .L73: movl $206, %r8d leaq .LC15(%rip), %rcx leaq .LC16(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl %r12d, %edi call cudaGetErrorString@PLT movq %rax, %r8 movl %r12d, %ecx leaq .LC17(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L74: movl %eax, %r12d testl %eax, %eax jne .L75 movl 16(%rsp), %eax movl %eax, %r12d imull %eax, %r12d movslq %r12d, %r12 salq $2, %r12 leaq 88(%rsp), %rdi movq %r12, %rsi call cudaMalloc@PLT jmp .L76 .L75: movl $207, %r8d leaq .LC15(%rip), %rcx leaq .LC16(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl %r12d, %edi call cudaGetErrorString@PLT movq %rax, %r8 movl %r12d, %ecx leaq .LC17(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L76: movl %eax, %r13d testl %eax, %eax jne .L77 movl $1, %ecx movq %r15, %rdx movq %rbp, %rsi movq 72(%rsp), %rdi call cudaMemcpy@PLT jmp .L78 .L77: movl $208, %r8d leaq .LC15(%rip), %rcx leaq .LC16(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl %r13d, %edi call cudaGetErrorString@PLT movq %rax, %r8 movl %r13d, %ecx leaq .LC17(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L78: movl %eax, %ebp testl %eax, %eax jne .L79 movl $1, %ecx movq %r12, %rdx movq 24(%rsp), %rsi movq 88(%rsp), %rdi call cudaMemcpy@PLT jmp .L80 .L79: movl $211, %r8d leaq .LC15(%rip), %rcx leaq .LC16(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl %ebp, %edi call cudaGetErrorString@PLT movq %rax, %r8 movl %ebp, %ecx leaq .LC17(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L80: movl %eax, %ebp testl %eax, %eax jne .L81 leal -1(%r14), %eax movl $0, %edx divl 1244(%rsp) leal 1(%rax), %ecx leal -1(%rbx), %eax movl $0, %edx divl 1240(%rsp) addl $1, %eax movl %eax, 100(%rsp) movl %ecx, 104(%rsp) movl $1, 108(%rsp) movl 1248(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 1240(%rsp), %rdx movq 100(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT jmp .L82 .L81: movl $212, %r8d leaq .LC15(%rip), %rcx leaq .LC16(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl %ebp, %edi call cudaGetErrorString@PLT movq %rax, %r8 movl %ebp, %ecx leaq .LC17(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L82: testl %eax, %eax jne .L54 movq 80(%rsp), %r9 movl 16(%rsp), %r8d movq 88(%rsp), %rcx movl %r14d, %edx movl %ebx, %esi movq 72(%rsp), %rdi call _Z47__device_stub__Z13blurImgKernelP6uchar3iiPfiS0_P6uchar3iiPfiS0_ .L54: call cudaGetLastError@PLT movl %eax, %ebp call cudaDeviceSynchronize@PLT movl %eax, %ebx testl %ebp, %ebp jne .L83 .L55: testl %ebx, %ebx je .L56 movl %ebx, %edi call cudaGetErrorString@PLT jmp .L84 .L83: movl %ebp, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC18(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L55 .L84: movq %rax, %rdx leaq .LC19(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L56: movl $2, %ecx movq %r15, %rdx movq 80(%rsp), %rsi movq 32(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %ebx testl %eax, %eax jne .L85 movq 72(%rsp), %rdi call cudaFree@PLT jmp .L86 .L85: movl $225, %r8d leaq .LC15(%rip), %rcx leaq .LC16(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl %ebx, %edi call cudaGetErrorString@PLT movq %rax, %r8 movl %ebx, %ecx leaq .LC17(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L86: movl %eax, %ebx testl %eax, %eax jne .L87 movq 88(%rsp), %rdi call cudaFree@PLT jmp .L88 .L87: movl $228, %r8d leaq .LC15(%rip), %rcx leaq .LC16(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl %ebx, %edi call cudaGetErrorString@PLT movq %rax, %r8 movl %ebx, %ecx leaq .LC17(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L88: movl %eax, %ebx testl %eax, %eax jne .L89 movq 80(%rsp), %rdi call cudaFree@PLT jmp .L90 .L89: movl $229, %r8d leaq .LC15(%rip), %rcx leaq .LC16(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl %ebx, %edi call cudaGetErrorString@PLT movq %rax, %r8 movl %ebx, %ecx leaq .LC17(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L90: movl %eax, %ebx testl %eax, %eax jne .L91 .L40: movl $0, %esi movq 120(%rsp), %rdi call cudaEventRecord@PLT jmp .L92 .L91: movl $230, %r8d leaq .LC15(%rip), %rcx leaq .LC16(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl %ebx, %edi call cudaGetErrorString@PLT movq %rax, %r8 movl %ebx, %ecx leaq .LC17(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L92: movq 120(%rsp), %rdi call cudaEventSynchronize@PLT leaq 100(%rsp), %rdi movq 120(%rsp), %rdx movq 112(%rsp), %rsi call cudaEventElapsedTime@PLT pxor %xmm0, %xmm0 cvtss2sd 100(%rsp), %xmm0 cmpb $0, 48(%rsp) leaq .LC12(%rip), %rdx leaq .LC11(%rip), %rax cmovne %rax, %rdx leaq .LC20(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT .LEHE1: movq 112(%rsp), %rdi call cudaEventDestroy@PLT movq 120(%rsp), %rdi call cudaEventDestroy@PLT movq 1160(%rsp), %rax subq %fs:40, %rax jne .L93 addq $1176, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L67: .cfi_restore_state endbr64 movq %rax, %rbx movq 112(%rsp), %rdi call cudaEventDestroy@PLT movq 120(%rsp), %rdi call cudaEventDestroy@PLT movq 1160(%rsp), %rax subq %fs:40, %rax je .L63 call __stack_chk_fail@PLT .L63: movq %rbx, %rdi .LEHB2: call _Unwind_Resume@PLT .LEHE2: .L93: call __stack_chk_fail@PLT .cfi_endproc .LFE2068: .globl __gxx_personality_v0 .section .gcc_except_table,"a",@progbits .LLSDA2068: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE2068-.LLSDACSB2068 .LLSDACSB2068: .uleb128 .LEHB0-.LFB2068 .uleb128 .LEHE0-.LEHB0 .uleb128 0 .uleb128 0 .uleb128 .LEHB1-.LFB2068 .uleb128 .LEHE1-.LEHB1 .uleb128 .L67-.LFB2068 .uleb128 0 .uleb128 .LEHB2-.LFB2068 .uleb128 .LEHE2-.LEHB2 .uleb128 0 .uleb128 0 .LLSDACSE2068: .text .size _Z7blurImgP6uchar3iiPfiS0_b4dim3, .-_Z7blurImgP6uchar3iiPfiS0_b4dim3 .section .rodata.str1.8 .align 8 .LC21: .string "The number of arguments is invalid\n" .align 8 .LC22: .string "Image size (width x height): %i x %i\n\n" .align 8 .LC23: .string "The shape of the correct output image is invalid\n" .section .rodata.str1.1 .LC25: .string "Error: %f\n\n" .LC26: .string "." .LC27: .string "_host.pnm" .LC28: .string "_device.pnm" .text .globl main .type main, @function main: .LFB2071: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $88, %rsp .cfi_def_cfa_offset 144 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl %edi, %eax andl $-3, %eax cmpl $4, %eax jne .L106 movl %edi, %ebp movq %rsi, %rbx leaq 40(%rsp), %rcx leaq 28(%rsp), %rdx leaq 24(%rsp), %rsi movq 8(%rbx), %rdi call _Z7readPnmPcRiS0_RP6uchar3 movl 28(%rsp), %ecx movl 24(%rsp), %edx leaq .LC22(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 48(%rsp), %rcx leaq 36(%rsp), %rdx leaq 32(%rsp), %rsi movq 24(%rbx), %rdi call _Z7readPnmPcRiS0_RP6uchar3 movl 24(%rsp), %r12d cmpl %r12d, 32(%rsp) jne .L97 movl 28(%rsp), %r14d cmpl %r14d, 36(%rsp) je .L98 .L97: leaq .LC23(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %eax .L94: movq 72(%rsp), %rdx subq %fs:40, %rdx jne .L107 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L106: .cfi_restore_state leaq .LC21(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %eax jmp .L94 .L98: movl $324, %edi call malloc@PLT movq %rax, %r13 leaq 36(%rax), %rdx leaq 360(%rax), %rcx movss .LC24(%rip), %xmm0 .L99: leaq -36(%rdx), %rax .L100: movss %xmm0, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L100 addq $36, %rdx cmpq %rcx, %rdx jne .L99 movl %r12d, %edi imull %r14d, %edi movslq %edi, %rdi imulq $3, %rdi, %rdi call malloc@PLT movq %rax, %rcx movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movq 40(%rsp), %r15 subq $24, %rsp .cfi_def_cfa_offset 168 movq 84(%rsp), %rax movq %rax, (%rsp) movl $1, 8(%rsp) pushq $0 .cfi_def_cfa_offset 176 movq %rcx, 40(%rsp) movq %rcx, %r9 movl $9, %r8d movq %r13, %rcx movl %r14d, %edx movl %r12d, %esi movq %r15, %rdi call _Z7blurImgP6uchar3iiPfiS0_b4dim3 movq 80(%rsp), %r12 addq $32, %rsp .cfi_def_cfa_offset 144 movl 24(%rsp), %edx imull 28(%rsp), %edx movq %r12, %rsi movq 8(%rsp), %rdi call _Z12computeErrorP6uchar3S0_i cvtss2sd %xmm0, %xmm0 leaq .LC25(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl 24(%rsp), %edi imull 28(%rsp), %edi movslq %edi, %rdi imulq $3, %rdi, %rdi call malloc@PLT movq %rax, %r14 movl $32, 60(%rsp) movl $32, 64(%rsp) movl $1, 68(%rsp) cmpl $6, %ebp je .L108 .L102: subq $24, %rsp .cfi_def_cfa_offset 168 movq 84(%rsp), %rax movq %rax, (%rsp) movl 92(%rsp), %eax movl %eax, 8(%rsp) pushq $1 .cfi_def_cfa_offset 176 movq %r14, %r9 movl $9, %r8d movq %r13, %rcx movl 60(%rsp), %edx movl 56(%rsp), %esi movq %r15, %rdi call _Z7blurImgP6uchar3iiPfiS0_b4dim3 addq $32, %rsp .cfi_def_cfa_offset 144 movl 24(%rsp), %edx imull 28(%rsp), %edx movq %r12, %rsi movq %r14, %rdi call _Z12computeErrorP6uchar3S0_i cvtss2sd %xmm0, %xmm0 leaq .LC25(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq 16(%rbx), %rdi leaq .LC26(%rip), %rsi call strtok@PLT movq %rax, %rbx leaq .LC27(%rip), %rsi movq %rax, %rdi call _Z9concatStrPKcS0_ movq %rax, %rcx movl 28(%rsp), %edx movl 24(%rsp), %esi movq 8(%rsp), %rbp movq %rbp, %rdi call _Z8writePnmP6uchar3iiPc leaq .LC28(%rip), %rsi movq %rbx, %rdi call _Z9concatStrPKcS0_ movq %rax, %rcx movl 28(%rsp), %edx movl 24(%rsp), %esi movq %r14, %rdi call _Z8writePnmP6uchar3iiPc movq %r15, %rdi call free@PLT movq %r12, %rdi call free@PLT movq %rbp, %rdi call free@PLT movq %r14, %rdi call free@PLT movq %r13, %rdi call free@PLT movl $0, %eax jmp .L94 .L108: movq 32(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl %eax, 60(%rsp) movq 40(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl %eax, 64(%rsp) jmp .L102 .L107: call __stack_chk_fail@PLT .cfi_endproc .LFE2071: .size main, .-main .section .rodata.str1.8 .align 8 .LC29: .string "_Z13blurImgKernelP6uchar3iiPfiS0_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2099: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC29(%rip), %rdx movq %rdx, %rcx leaq _Z13blurImgKernelP6uchar3iiPfiS0_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2099: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC24: .long 1011500424 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ ; -- Begin function _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ .globl _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ .p2align 8 .type _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_,@function _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_: ; @_Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x34 s_load_b64 s[4:5], s[0:1], 0x8 v_and_b32_e32 v3, 0x3ff, v0 v_bfe_u32 v2, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s3, s2, 0xffff s_lshr_b32 s2, s2, 16 s_mul_i32 s14, s14, s3 v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3] v_add_nc_u32_e32 v1, s14, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_gt_i32_e32 vcc_lo, s4, v1 v_cmp_gt_i32_e64 s2, s5, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_8 ; %bb.1: s_load_b32 s12, s[0:1], 0x18 v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0 v_mov_b32_e32 v4, 0 s_mov_b32 s3, 0 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s12, 1 s_cbranch_scc1 .LBB0_7 ; %bb.2: ; %.preheader.lr.ph s_clause 0x1 s_load_b64 s[6:7], s[0:1], 0x0 s_load_b64 s[8:9], s[0:1], 0x10 s_lshr_b32 s2, s12, 1 v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, 0 v_subrev_nc_u32_e32 v2, s2, v0 v_subrev_nc_u32_e32 v4, s2, v1 v_mov_b32_e32 v5, 0 s_add_i32 s13, s5, -1 s_add_i32 s14, s4, -1 s_mov_b32 s2, s3 s_mov_b32 s15, s3 s_set_inst_prefetch_distance 0x1 .p2align 6 .LBB0_3: ; %.preheader ; =>This Loop Header: Depth=1 ; Child Loop BB0_4 Depth 2 v_add_nc_u32_e32 v7, s15, v2 s_lshl_b64 s[10:11], s[2:3], 2 s_mov_b32 s16, 0 s_waitcnt lgkmcnt(0) s_add_u32 s10, s8, s10 s_addc_u32 s11, s9, s11 v_max_i32_e32 v7, 0, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_i32_e32 vcc_lo, s5, v7 v_cndmask_b32_e32 v7, s13, v7, vcc_lo v_mul_lo_u32 v7, v7, s4 .p2align 6 .LBB0_4: ; Parent Loop BB0_3 Depth=1 ; => This Inner Loop Header: Depth=2 v_add_nc_u32_e32 v8, s16, v4 s_add_i32 s16, s16, 1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_max_i32_e32 v8, 0, v8 v_cmp_gt_i32_e32 vcc_lo, s4, v8 v_cndmask_b32_e32 v8, s14, v8, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v10, v8, v7 v_mad_i64_i32 v[8:9], null, v10, 3, s[6:7] s_clause 0x2 global_load_u8 v10, v[8:9], off global_load_u8 v11, v[8:9], off offset:1 global_load_u8 v8, v[8:9], off offset:2 s_load_b32 s17, s[10:11], 0x0 s_add_u32 s10, s10, 4 s_addc_u32 s11, s11, 0 s_cmp_eq_u32 s12, s16 s_waitcnt vmcnt(2) v_cvt_f32_ubyte0_e32 v9, v10 s_waitcnt vmcnt(1) v_cvt_f32_ubyte0_e32 v10, v11 s_waitcnt vmcnt(0) v_cvt_f32_ubyte0_e32 v8, v8 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_fmac_f32 v3, s17, v9 :: v_dual_fmac_f32 v6, s17, v10 v_fmac_f32_e32 v5, s17, v8 s_cbranch_scc0 .LBB0_4 ; %bb.5: ; %._crit_edge ; in Loop: Header=BB0_3 Depth=1 s_add_i32 s15, s15, 1 s_add_i32 s2, s2, s12 s_cmp_eq_u32 s15, s12 s_cbranch_scc0 .LBB0_3 ; %bb.6: ; %._crit_edge82.loopexit s_set_inst_prefetch_distance 0x2 v_cvt_i32_f32_e32 v2, v3 v_cvt_i32_f32_e32 v3, v6 v_cvt_i32_f32_e32 v4, v5 .LBB0_7: ; %._crit_edge82 s_load_b64 s[0:1], s[0:1], 0x20 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v0, s4, v[1:2] s_waitcnt lgkmcnt(0) v_mad_i64_i32 v[0:1], null, v5, 3, s[0:1] s_clause 0x2 global_store_b8 v[0:1], v2, off global_store_b8 v[0:1], v3, off offset:1 global_store_b8 v[0:1], v4, off offset:2 .LBB0_8: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 18 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_, .Lfunc_end0-_Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 488 ; NumSgprs: 20 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 20 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ .private_segment_fixed_size: 0 .sgpr_count: 20 .sgpr_spill_count: 0 .symbol: _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "e242fabb7ad2b0f310afe5f576785cf6a98722d2.hip" .globl _Z7readPnmPcRiS0_RP15HIP_vector_typeIhLj3EE # -- Begin function _Z7readPnmPcRiS0_RP15HIP_vector_typeIhLj3EE .p2align 4, 0x90 .type _Z7readPnmPcRiS0_RP15HIP_vector_typeIhLj3EE,@function _Z7readPnmPcRiS0_RP15HIP_vector_typeIhLj3EE: # @_Z7readPnmPcRiS0_RP15HIP_vector_typeIhLj3EE .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 pushq %rax .cfi_def_cfa_offset 64 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rcx, %rbx movq %rdx, %r14 movq %rsi, %r15 movq %rdi, %r13 movl $.L.str, %esi callq fopen testq %rax, %rax je .LBB0_3 # %bb.1: movq %rax, %r12 leaq 1(%rsp), %rdx movl $.L.str.2, %esi movq %rax, %rdi xorl %eax, %eax callq __isoc23_fscanf movzwl 1(%rsp), %eax xorl $13136, %eax # imm = 0x3350 movzbl 3(%rsp), %ecx orw %ax, %cx jne .LBB0_2 # %bb.4: movl $.L.str.4, %esi movq %r12, %rdi movq %r15, %rdx xorl %eax, %eax callq __isoc23_fscanf movl $.L.str.4, %esi movq %r12, %rdi movq %r14, %rdx xorl %eax, %eax callq __isoc23_fscanf leaq 4(%rsp), %rdx movl $.L.str.4, %esi movq %r12, %rdi xorl %eax, %eax callq __isoc23_fscanf cmpl $256, 4(%rsp) # imm = 0x100 jge .LBB0_2 # %bb.5: movslq (%r15), %rax movslq (%r14), %rcx imulq %rax, %rcx leaq (%rcx,%rcx,2), %rdi callq malloc movq %rax, (%rbx) movl (%r14), %eax imull (%r15), %eax testl %eax, %eax jle .LBB0_8 # %bb.6: # %.lr.ph.preheader movl $2, %r13d xorl %ebp, %ebp .p2align 4, 0x90 .LBB0_7: # %.lr.ph # =>This Inner Loop Header: Depth=1 movq (%rbx), %rax leaq (%rax,%r13), %r8 leaq (%rax,%r13), %rdx addq $-2, %rdx leaq (%rax,%r13), %rcx decq %rcx movl $.L.str.5, %esi movq %r12, %rdi xorl %eax, %eax callq __isoc23_fscanf incq %rbp movslq (%r15), %rax movslq (%r14), %rcx imulq %rax, %rcx addq $3, %r13 cmpq %rcx, %rbp jl .LBB0_7 .LBB0_8: # %._crit_edge movq %r12, %rdi callq fclose addq $8, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB0_2: .cfi_def_cfa_offset 64 movq %r12, %rdi callq fclose .LBB0_3: movl $.L.str.1, %edi movq %r13, %rsi xorl %eax, %eax callq printf movl $1, %edi callq exit .Lfunc_end0: .size _Z7readPnmPcRiS0_RP15HIP_vector_typeIhLj3EE, .Lfunc_end0-_Z7readPnmPcRiS0_RP15HIP_vector_typeIhLj3EE .cfi_endproc # -- End function .globl _Z8writePnmP15HIP_vector_typeIhLj3EEiiPc # -- Begin function _Z8writePnmP15HIP_vector_typeIhLj3EEiiPc .p2align 4, 0x90 .type _Z8writePnmP15HIP_vector_typeIhLj3EEiiPc,@function _Z8writePnmP15HIP_vector_typeIhLj3EEiiPc: # @_Z8writePnmP15HIP_vector_typeIhLj3EEiiPc .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rcx, %r12 movl %edx, %ebp movl %esi, %r15d movq %rdi, %rbx movl $.L.str.6, %esi movq %rcx, %rdi callq fopen testq %rax, %rax je .LBB1_5 # %bb.1: movq %rax, %r14 movl $.L.str.8, %esi movq %rax, %rdi movl %r15d, %edx movl %ebp, %ecx xorl %eax, %eax callq fprintf imull %r15d, %ebp testl %ebp, %ebp jle .LBB1_4 # %bb.2: # %.lr.ph.preheader movl %ebp, %eax leaq (%rax,%rax,2), %r15 xorl %r12d, %r12d .p2align 4, 0x90 .LBB1_3: # %.lr.ph # =>This Inner Loop Header: Depth=1 movzbl (%rbx,%r12), %edx movzbl 1(%rbx,%r12), %ecx movzbl 2(%rbx,%r12), %r8d movl $.L.str.9, %esi movq %r14, %rdi xorl %eax, %eax callq fprintf addq $3, %r12 cmpq %r12, %r15 jne .LBB1_3 .LBB1_4: # %._crit_edge movq %r14, %rdi popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 jmp fclose # TAILCALL .LBB1_5: .cfi_def_cfa_offset 48 movl $.L.str.7, %edi movq %r12, %rsi xorl %eax, %eax callq printf movl $1, %edi callq exit .Lfunc_end1: .size _Z8writePnmP15HIP_vector_typeIhLj3EEiiPc, .Lfunc_end1-_Z8writePnmP15HIP_vector_typeIhLj3EEiiPc .cfi_endproc # -- End function .globl _Z28__device_stub__blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ # -- Begin function _Z28__device_stub__blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ .p2align 4, 0x90 .type _Z28__device_stub__blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_,@function _Z28__device_stub__blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_: # @_Z28__device_stub__blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 88(%rsp) movl %esi, 20(%rsp) movl %edx, 16(%rsp) movq %rcx, 80(%rsp) movl %r8d, 12(%rsp) movq %r9, 72(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 20(%rsp), %rax movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 80(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) leaq 72(%rsp), %rax movq %rax, 136(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end2: .size _Z28__device_stub__blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_, .Lfunc_end2-_Z28__device_stub__blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ .cfi_endproc # -- End function .globl _Z7blurImgP15HIP_vector_typeIhLj3EEiiPfiS1_b4dim3 # -- Begin function _Z7blurImgP15HIP_vector_typeIhLj3EEiiPfiS1_b4dim3 .p2align 4, 0x90 .type _Z7blurImgP15HIP_vector_typeIhLj3EEiiPfiS1_b4dim3,@function _Z7blurImgP15HIP_vector_typeIhLj3EEiiPfiS1_b4dim3: # @_Z7blurImgP15HIP_vector_typeIhLj3EEiiPfiS1_b4dim3 .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $1736, %rsp # imm = 0x6C8 .cfi_def_cfa_offset 1792 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r9, 80(%rsp) # 8-byte Spill movl %r8d, 4(%rsp) # 4-byte Spill movq %rcx, %r12 # kill: def $edx killed $edx def $rdx movq %rdx, 8(%rsp) # 8-byte Spill movl %esi, %r15d movq %rdi, %r13 .cfi_escape 0x2e, 0x00 leaq 16(%rsp), %rdi callq hipEventCreate leaq 24(%rsp), %rdi .cfi_escape 0x2e, 0x00 callq hipEventCreate movq 16(%rsp), %rdi .Ltmp0: .cfi_escape 0x2e, 0x00 xorl %esi, %esi callq hipEventRecord .Ltmp1: # %bb.1: # %_ZN8GpuTimer5StartEv.exit cmpb $0, 1792(%rsp) je .LBB3_2 # %bb.21: .Ltmp2: .cfi_escape 0x2e, 0x00 leaq 264(%rsp), %rdi xorl %esi, %esi callq hipGetDevicePropertiesR0600 .Ltmp3: # %bb.22: .cfi_escape 0x2e, 0x00 leaq 264(%rsp), %rsi movl $.L.str.10, %edi xorl %eax, %eax callq printf movl 624(%rsp), %esi movl 628(%rsp), %edx .cfi_escape 0x2e, 0x00 movl $.L.str.11, %edi xorl %eax, %eax callq printf movq 8(%rsp), %rax # 8-byte Reload # kill: def $eax killed $eax killed $rax imull %r15d, %eax cltq leaq (%rax,%rax,2), %r14 .Ltmp5: .cfi_escape 0x2e, 0x00 leaq 56(%rsp), %rdi movq %r14, %rsi callq hipMalloc .Ltmp6: # %bb.23: # %_ZL9hipMallocI15HIP_vector_typeIhLj3EEE10hipError_tPPT_m.exit testl %eax, %eax jne .LBB3_24 # %bb.29: .Ltmp10: .cfi_escape 0x2e, 0x00 leaq 48(%rsp), %rdi movq %r14, %rsi callq hipMalloc .Ltmp11: # %bb.30: # %_ZL9hipMallocI15HIP_vector_typeIhLj3EEE10hipError_tPPT_m.exit179 testl %eax, %eax jne .LBB3_31 # %bb.34: movl 4(%rsp), %eax # 4-byte Reload movl %eax, %ebx imull %ebx, %ebx shlq $2, %rbx .Ltmp15: .cfi_escape 0x2e, 0x00 leaq 40(%rsp), %rdi movq %rbx, %rsi callq hipMalloc .Ltmp16: # %bb.35: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit movl %eax, %ebp testl %eax, %eax jne .LBB3_36 # %bb.39: movq 56(%rsp), %rdi .Ltmp20: .cfi_escape 0x2e, 0x00 movq %r13, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy .Ltmp21: # %bb.40: testl %eax, %eax jne .LBB3_41 # %bb.44: movq 40(%rsp), %rdi .Ltmp25: .cfi_escape 0x2e, 0x00 movq %r12, %rsi movq %rbx, %rdx movl $1, %ecx callq hipMemcpy .Ltmp26: # %bb.45: testl %eax, %eax jne .LBB3_46 # %bb.49: leaq 1800(%rsp), %rcx leal -1(%r15), %eax xorl %edx, %edx divl (%rcx) # kill: def $eax killed $eax def $rax leal 1(%rax), %edi movq 8(%rsp), %rax # 8-byte Reload decl %eax xorl %edx, %edx divl 4(%rcx) # kill: def $eax killed $eax def $rax incl %eax shlq $32, %rax orq %rax, %rdi movq (%rcx), %rdx movl 8(%rcx), %ecx .Ltmp30: .cfi_escape 0x2e, 0x00 movl $1, %esi xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration .Ltmp31: # %bb.50: testl %eax, %eax jne .LBB3_53 # %bb.51: movq 56(%rsp), %rax movq 40(%rsp), %rcx movq 48(%rsp), %rdx movq %rax, 200(%rsp) movl %r15d, 76(%rsp) movq 8(%rsp), %rax # 8-byte Reload movl %eax, 72(%rsp) movq %rcx, 192(%rsp) movl 4(%rsp), %eax # 4-byte Reload movl %eax, 68(%rsp) movq %rdx, 184(%rsp) leaq 200(%rsp), %rax movq %rax, 208(%rsp) leaq 76(%rsp), %rax movq %rax, 216(%rsp) leaq 72(%rsp), %rax movq %rax, 224(%rsp) leaq 192(%rsp), %rax movq %rax, 232(%rsp) leaq 68(%rsp), %rax movq %rax, 240(%rsp) leaq 184(%rsp), %rax movq %rax, 248(%rsp) .Ltmp32: .cfi_escape 0x2e, 0x00 leaq 168(%rsp), %rdi leaq 152(%rsp), %rsi leaq 144(%rsp), %rdx leaq 136(%rsp), %rcx callq __hipPopCallConfiguration .Ltmp33: # %bb.52: # %.noexc movq 168(%rsp), %rsi movl 176(%rsp), %edx movq 152(%rsp), %rcx movl 160(%rsp), %r8d .Ltmp34: .cfi_escape 0x2e, 0x10 leaq 208(%rsp), %r9 movl $_Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_, %edi pushq 136(%rsp) .cfi_adjust_cfa_offset 8 pushq 152(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .Ltmp35: .LBB3_53: .Ltmp37: .cfi_escape 0x2e, 0x00 callq hipGetLastError .Ltmp38: # %bb.54: .Ltmp40: movl %eax, %ebp .cfi_escape 0x2e, 0x00 callq hipDeviceSynchronize .Ltmp41: # %bb.55: movl %eax, %ebx testl %ebp, %ebp je .LBB3_58 # %bb.56: .Ltmp42: .cfi_escape 0x2e, 0x00 movl %ebp, %edi callq hipGetErrorString .Ltmp43: # %bb.57: .cfi_escape 0x2e, 0x00 movl $.L.str.15, %edi movq %rax, %rsi xorl %eax, %eax callq printf .LBB3_58: testl %ebx, %ebx je .LBB3_61 # %bb.59: .Ltmp44: .cfi_escape 0x2e, 0x00 movl %ebx, %edi callq hipGetErrorString .Ltmp45: # %bb.60: .cfi_escape 0x2e, 0x00 movl $.L.str.16, %edi movq %rax, %rsi xorl %eax, %eax callq printf .LBB3_61: movq 48(%rsp), %rsi .Ltmp47: .cfi_escape 0x2e, 0x00 movq 80(%rsp), %rdi # 8-byte Reload movq %r14, %rdx movl $2, %ecx callq hipMemcpy .Ltmp48: # %bb.62: testl %eax, %eax jne .LBB3_63 # %bb.68: movq 56(%rsp), %rdi .Ltmp52: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp53: # %bb.69: testl %eax, %eax jne .LBB3_70 # %bb.73: movq 40(%rsp), %rdi .Ltmp57: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp58: # %bb.74: testl %eax, %eax jne .LBB3_75 # %bb.78: movq 48(%rsp), %rdi .Ltmp62: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp63: # %bb.79: testl %eax, %eax je .LBB3_10 # %bb.80: movq stderr(%rip), %rdi .cfi_escape 0x2e, 0x00 movl $.L.str.12, %esi movl $.L.str.13, %edx movl $232, %ecx movl %eax, %ebp xorl %eax, %eax callq fprintf movq stderr(%rip), %rbx .Ltmp64: .cfi_escape 0x2e, 0x00 movl %ebp, %edi callq hipGetErrorString .Ltmp65: # %bb.81: .cfi_escape 0x2e, 0x00 jmp .LBB3_26 .LBB3_2: cmpl $0, 8(%rsp) # 4-byte Folded Reload jle .LBB3_10 # %bb.3: # %.preheader185.lr.ph movl 4(%rsp), %eax # 4-byte Reload movl %eax, %edi shrl $31, %edi addl %eax, %edi sarl %edi negl %edi movq 8(%rsp), %rsi # 8-byte Reload leal -1(%rsi), %ecx leal -1(%r15), %edx movl %esi, %esi movq %rsi, 104(%rsp) # 8-byte Spill movl %r15d, %esi movq %rsi, 112(%rsp) # 8-byte Spill movl %eax, %r8d movq %rdi, 96(%rsp) # 8-byte Spill movl %edi, %eax movq %rax, 88(%rsp) # 8-byte Spill xorl %eax, %eax movq %rax, 32(%rsp) # 8-byte Spill jmp .LBB3_4 .p2align 4, 0x90 .LBB3_9: # %._crit_edge202 # in Loop: Header=BB3_4 Depth=1 movq 32(%rsp), %rsi # 8-byte Reload incq %rsi movq %rsi, %rax movq %rsi, 32(%rsp) # 8-byte Spill cmpq 104(%rsp), %rsi # 8-byte Folded Reload je .LBB3_10 .LBB3_4: # %.preheader185 # =>This Loop Header: Depth=1 # Child Loop BB3_6 Depth 2 # Child Loop BB3_18 Depth 3 # Child Loop BB3_19 Depth 4 testl %r15d, %r15d jle .LBB3_9 # %bb.5: # %.lr.ph201 # in Loop: Header=BB3_4 Depth=1 movq 96(%rsp), %rax # 8-byte Reload movq 32(%rsp), %rsi # 8-byte Reload leal (%rax,%rsi), %r11d movl %esi, %eax imull %r15d, %eax leaq (%rax,%rax,2), %rax addq 80(%rsp), %rax # 8-byte Folded Reload movq %rax, 120(%rsp) # 8-byte Spill movq 88(%rsp), %r9 # 8-byte Reload xorl %ebx, %ebx jmp .LBB3_6 .p2align 4, 0x90 .LBB3_7: # in Loop: Header=BB3_6 Depth=2 xorps %xmm0, %xmm0 xorps %xmm2, %xmm2 xorps %xmm1, %xmm1 .LBB3_8: # %._crit_edge196 # in Loop: Header=BB3_6 Depth=2 cvttss2si %xmm1, %esi movq 128(%rsp), %rbx # 8-byte Reload leaq (%rbx,%rbx,2), %rdi cvttss2si %xmm2, %r10d movq 120(%rsp), %rax # 8-byte Reload movb %sil, (%rax,%rdi) movb %r10b, 1(%rax,%rdi) cvttss2si %xmm0, %esi movb %sil, 2(%rax,%rdi) incq %rbx incq %r9 cmpq 112(%rsp), %rbx # 8-byte Folded Reload je .LBB3_9 .LBB3_6: # Parent Loop BB3_4 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB3_18 Depth 3 # Child Loop BB3_19 Depth 4 movq %rbx, 128(%rsp) # 8-byte Spill cmpl $0, 4(%rsp) # 4-byte Folded Reload jle .LBB3_7 # %bb.17: # %.preheader.lr.ph # in Loop: Header=BB3_6 Depth=2 xorps %xmm1, %xmm1 xorl %esi, %esi xorl %r10d, %r10d xorps %xmm2, %xmm2 xorps %xmm0, %xmm0 .p2align 4, 0x90 .LBB3_18: # %.preheader # Parent Loop BB3_4 Depth=1 # Parent Loop BB3_6 Depth=2 # => This Loop Header: Depth=3 # Child Loop BB3_19 Depth 4 movl %esi, %edi leaq (%r12,%rdi,4), %rdi leal (%r11,%r10), %r14d testl %r14d, %r14d movl $0, %ebx cmovgl %r14d, %ebx cmpl 8(%rsp), %r14d # 4-byte Folded Reload cmovgel %ecx, %ebx imull %r15d, %ebx xorl %r14d, %r14d .p2align 4, 0x90 .LBB3_19: # Parent Loop BB3_4 Depth=1 # Parent Loop BB3_6 Depth=2 # Parent Loop BB3_18 Depth=3 # => This Inner Loop Header: Depth=4 leal (%r9,%r14), %eax testl %eax, %eax movl $0, %ebp cmovgl %eax, %ebp cmpl %r15d, %eax cmovgel %edx, %ebp addl %ebx, %ebp movss (%rdi,%r14,4), %xmm3 # xmm3 = mem[0],zero,zero,zero movslq %ebp, %rax leaq (%rax,%rax,2), %rax movzbl (%r13,%rax), %ebp xorps %xmm4, %xmm4 cvtsi2ss %ebp, %xmm4 movzbl 1(%r13,%rax), %ebp xorps %xmm5, %xmm5 cvtsi2ss %ebp, %xmm5 mulss %xmm3, %xmm4 addss %xmm4, %xmm1 mulss %xmm3, %xmm5 addss %xmm5, %xmm2 movzbl 2(%r13,%rax), %eax xorps %xmm4, %xmm4 cvtsi2ss %eax, %xmm4 mulss %xmm3, %xmm4 addss %xmm4, %xmm0 incq %r14 cmpq %r14, %r8 jne .LBB3_19 # %bb.20: # %._crit_edge # in Loop: Header=BB3_18 Depth=3 incq %r10 addl 4(%rsp), %esi # 4-byte Folded Reload cmpq %r8, %r10 jne .LBB3_18 jmp .LBB3_8 .LBB3_10: # %.loopexit movq 24(%rsp), %rdi .Ltmp67: .cfi_escape 0x2e, 0x00 xorl %esi, %esi callq hipEventRecord .Ltmp68: # %bb.11: # %_ZN8GpuTimer4StopEv.exit movq 24(%rsp), %rdi .Ltmp70: .cfi_escape 0x2e, 0x00 callq hipEventSynchronize .Ltmp71: movzbl 1792(%rsp), %ebx # %bb.12: # %.noexc182 movq 16(%rsp), %rsi movq 24(%rsp), %rdx .Ltmp72: .cfi_escape 0x2e, 0x00 leaq 264(%rsp), %rdi callq hipEventElapsedTime .Ltmp73: # %bb.13: # %_ZN8GpuTimer7ElapsedEv.exit movss 264(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero movl $.L.str.18, %eax movl $.L.str.19, %esi testb %bl, %bl cmovneq %rax, %rsi cvtss2sd %xmm0, %xmm0 .cfi_escape 0x2e, 0x00 movl $.L.str.17, %edi movb $1, %al callq printf movq 16(%rsp), %rdi .Ltmp80: .cfi_escape 0x2e, 0x00 callq hipEventDestroy .Ltmp81: # %bb.14: movq 24(%rsp), %rdi .Ltmp82: .cfi_escape 0x2e, 0x00 callq hipEventDestroy .Ltmp83: # %bb.15: # %_ZN8GpuTimerD2Ev.exit addq $1736, %rsp # imm = 0x6C8 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB3_24: .cfi_def_cfa_offset 1792 movq stderr(%rip), %rdi .cfi_escape 0x2e, 0x00 movl $.L.str.12, %esi movl $.L.str.13, %edx movl $208, %ecx movl %eax, %ebp xorl %eax, %eax callq fprintf movq stderr(%rip), %rbx .Ltmp7: .cfi_escape 0x2e, 0x00 movl %ebp, %edi callq hipGetErrorString .Ltmp8: # %bb.25: .cfi_escape 0x2e, 0x00 jmp .LBB3_26 .LBB3_31: movq stderr(%rip), %rdi .cfi_escape 0x2e, 0x00 movl $.L.str.12, %esi movl $.L.str.13, %edx movl $209, %ecx movl %eax, %ebp xorl %eax, %eax callq fprintf movq stderr(%rip), %rbx .Ltmp12: .cfi_escape 0x2e, 0x00 movl %ebp, %edi callq hipGetErrorString .Ltmp13: # %bb.32: .cfi_escape 0x2e, 0x00 jmp .LBB3_26 .LBB3_36: movq stderr(%rip), %rdi .cfi_escape 0x2e, 0x00 movl $.L.str.12, %esi movl $.L.str.13, %edx movl $210, %ecx xorl %eax, %eax callq fprintf movq stderr(%rip), %rbx .Ltmp17: .cfi_escape 0x2e, 0x00 movl %ebp, %edi callq hipGetErrorString .Ltmp18: # %bb.37: .cfi_escape 0x2e, 0x00 jmp .LBB3_26 .LBB3_41: movq stderr(%rip), %rdi .cfi_escape 0x2e, 0x00 movl $.L.str.12, %esi movl $.L.str.13, %edx movl $213, %ecx movl %eax, %ebp xorl %eax, %eax callq fprintf movq stderr(%rip), %rbx .Ltmp22: .cfi_escape 0x2e, 0x00 movl %ebp, %edi callq hipGetErrorString .Ltmp23: # %bb.42: .cfi_escape 0x2e, 0x00 jmp .LBB3_26 .LBB3_46: movq stderr(%rip), %rdi .cfi_escape 0x2e, 0x00 movl $.L.str.12, %esi movl $.L.str.13, %edx movl $214, %ecx movl %eax, %ebp xorl %eax, %eax callq fprintf movq stderr(%rip), %rbx .Ltmp27: .cfi_escape 0x2e, 0x00 movl %ebp, %edi callq hipGetErrorString .Ltmp28: # %bb.47: .cfi_escape 0x2e, 0x00 jmp .LBB3_26 .LBB3_63: movq stderr(%rip), %rdi .cfi_escape 0x2e, 0x00 movl $.L.str.12, %esi movl $.L.str.13, %edx movl $227, %ecx movl %eax, %ebp xorl %eax, %eax callq fprintf movq stderr(%rip), %rbx .Ltmp49: .cfi_escape 0x2e, 0x00 movl %ebp, %edi callq hipGetErrorString .Ltmp50: # %bb.64: .cfi_escape 0x2e, 0x00 jmp .LBB3_26 .LBB3_70: movq stderr(%rip), %rdi .cfi_escape 0x2e, 0x00 movl $.L.str.12, %esi movl $.L.str.13, %edx movl $230, %ecx movl %eax, %ebp xorl %eax, %eax callq fprintf movq stderr(%rip), %rbx .Ltmp54: .cfi_escape 0x2e, 0x00 movl %ebp, %edi callq hipGetErrorString .Ltmp55: # %bb.71: .cfi_escape 0x2e, 0x00 jmp .LBB3_26 .LBB3_75: movq stderr(%rip), %rdi .cfi_escape 0x2e, 0x00 movl $.L.str.12, %esi movl $.L.str.13, %edx movl $231, %ecx movl %eax, %ebp xorl %eax, %eax callq fprintf movq stderr(%rip), %rbx .Ltmp59: .cfi_escape 0x2e, 0x00 movl %ebp, %edi callq hipGetErrorString .Ltmp60: # %bb.76: .cfi_escape 0x2e, 0x00 .LBB3_26: movl $.L.str.14, %esi movq %rbx, %rdi movl %ebp, %edx movq %rax, %rcx xorl %eax, %eax callq fprintf .cfi_escape 0x2e, 0x00 movl $1, %edi callq exit .LBB3_65: .Ltmp39: jmp .LBB3_85 .LBB3_27: .Ltmp4: jmp .LBB3_85 .LBB3_88: .Ltmp36: jmp .LBB3_85 .LBB3_66: .Ltmp46: jmp .LBB3_85 .LBB3_83: .Ltmp84: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq __clang_call_terminate .LBB3_84: .Ltmp74: jmp .LBB3_85 .LBB3_16: .Ltmp69: jmp .LBB3_85 .LBB3_82: .Ltmp66: jmp .LBB3_85 .LBB3_77: .Ltmp61: jmp .LBB3_85 .LBB3_72: .Ltmp56: jmp .LBB3_85 .LBB3_67: .Ltmp51: jmp .LBB3_85 .LBB3_48: .Ltmp29: jmp .LBB3_85 .LBB3_43: .Ltmp24: jmp .LBB3_85 .LBB3_38: .Ltmp19: jmp .LBB3_85 .LBB3_33: .Ltmp14: jmp .LBB3_85 .LBB3_28: .Ltmp9: .LBB3_85: movq %rax, %rbx movq 16(%rsp), %rdi .Ltmp75: .cfi_escape 0x2e, 0x00 callq hipEventDestroy .Ltmp76: # %bb.86: movq 24(%rsp), %rdi .Ltmp77: .cfi_escape 0x2e, 0x00 callq hipEventDestroy .Ltmp78: # %bb.87: # %_ZN8GpuTimerD2Ev.exit184 .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _Unwind_Resume@PLT .LBB3_89: .Ltmp79: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq __clang_call_terminate .Lfunc_end3: .size _Z7blurImgP15HIP_vector_typeIhLj3EEiiPfiS1_b4dim3, .Lfunc_end3-_Z7blurImgP15HIP_vector_typeIhLj3EEiiPfiS1_b4dim3 .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table3: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase0-.Lttbaseref0 .Lttbaseref0: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1 .uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69 .byte 0 # On action: cleanup .uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp3-.Ltmp2 # Call between .Ltmp2 and .Ltmp3 .uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4 .byte 0 # On action: cleanup .uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6 .uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9 .byte 0 # On action: cleanup .uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11 .uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14 .byte 0 # On action: cleanup .uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16 .uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19 .byte 0 # On action: cleanup .uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 7 << .uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21 .uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24 .byte 0 # On action: cleanup .uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 8 << .uleb128 .Ltmp26-.Ltmp25 # Call between .Ltmp25 and .Ltmp26 .uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29 .byte 0 # On action: cleanup .uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 9 << .uleb128 .Ltmp35-.Ltmp30 # Call between .Ltmp30 and .Ltmp35 .uleb128 .Ltmp36-.Lfunc_begin0 # jumps to .Ltmp36 .byte 0 # On action: cleanup .uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 10 << .uleb128 .Ltmp38-.Ltmp37 # Call between .Ltmp37 and .Ltmp38 .uleb128 .Ltmp39-.Lfunc_begin0 # jumps to .Ltmp39 .byte 0 # On action: cleanup .uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 11 << .uleb128 .Ltmp45-.Ltmp40 # Call between .Ltmp40 and .Ltmp45 .uleb128 .Ltmp46-.Lfunc_begin0 # jumps to .Ltmp46 .byte 0 # On action: cleanup .uleb128 .Ltmp47-.Lfunc_begin0 # >> Call Site 12 << .uleb128 .Ltmp48-.Ltmp47 # Call between .Ltmp47 and .Ltmp48 .uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51 .byte 0 # On action: cleanup .uleb128 .Ltmp52-.Lfunc_begin0 # >> Call Site 13 << .uleb128 .Ltmp53-.Ltmp52 # Call between .Ltmp52 and .Ltmp53 .uleb128 .Ltmp56-.Lfunc_begin0 # jumps to .Ltmp56 .byte 0 # On action: cleanup .uleb128 .Ltmp57-.Lfunc_begin0 # >> Call Site 14 << .uleb128 .Ltmp58-.Ltmp57 # Call between .Ltmp57 and .Ltmp58 .uleb128 .Ltmp61-.Lfunc_begin0 # jumps to .Ltmp61 .byte 0 # On action: cleanup .uleb128 .Ltmp62-.Lfunc_begin0 # >> Call Site 15 << .uleb128 .Ltmp65-.Ltmp62 # Call between .Ltmp62 and .Ltmp65 .uleb128 .Ltmp66-.Lfunc_begin0 # jumps to .Ltmp66 .byte 0 # On action: cleanup .uleb128 .Ltmp67-.Lfunc_begin0 # >> Call Site 16 << .uleb128 .Ltmp68-.Ltmp67 # Call between .Ltmp67 and .Ltmp68 .uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69 .byte 0 # On action: cleanup .uleb128 .Ltmp70-.Lfunc_begin0 # >> Call Site 17 << .uleb128 .Ltmp73-.Ltmp70 # Call between .Ltmp70 and .Ltmp73 .uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74 .byte 0 # On action: cleanup .uleb128 .Ltmp80-.Lfunc_begin0 # >> Call Site 18 << .uleb128 .Ltmp83-.Ltmp80 # Call between .Ltmp80 and .Ltmp83 .uleb128 .Ltmp84-.Lfunc_begin0 # jumps to .Ltmp84 .byte 1 # On action: 1 .uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 19 << .uleb128 .Ltmp8-.Ltmp7 # Call between .Ltmp7 and .Ltmp8 .uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9 .byte 0 # On action: cleanup .uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 20 << .uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13 .uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14 .byte 0 # On action: cleanup .uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 21 << .uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18 .uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19 .byte 0 # On action: cleanup .uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 22 << .uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23 .uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24 .byte 0 # On action: cleanup .uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 23 << .uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28 .uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29 .byte 0 # On action: cleanup .uleb128 .Ltmp49-.Lfunc_begin0 # >> Call Site 24 << .uleb128 .Ltmp50-.Ltmp49 # Call between .Ltmp49 and .Ltmp50 .uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51 .byte 0 # On action: cleanup .uleb128 .Ltmp54-.Lfunc_begin0 # >> Call Site 25 << .uleb128 .Ltmp55-.Ltmp54 # Call between .Ltmp54 and .Ltmp55 .uleb128 .Ltmp56-.Lfunc_begin0 # jumps to .Ltmp56 .byte 0 # On action: cleanup .uleb128 .Ltmp59-.Lfunc_begin0 # >> Call Site 26 << .uleb128 .Ltmp60-.Ltmp59 # Call between .Ltmp59 and .Ltmp60 .uleb128 .Ltmp61-.Lfunc_begin0 # jumps to .Ltmp61 .byte 0 # On action: cleanup .uleb128 .Ltmp75-.Lfunc_begin0 # >> Call Site 27 << .uleb128 .Ltmp78-.Ltmp75 # Call between .Ltmp75 and .Ltmp78 .uleb128 .Ltmp79-.Lfunc_begin0 # jumps to .Ltmp79 .byte 1 # On action: 1 .uleb128 .Ltmp78-.Lfunc_begin0 # >> Call Site 28 << .uleb128 .Lfunc_end3-.Ltmp78 # Call between .Ltmp78 and .Lfunc_end3 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase0: .p2align 2, 0x0 # -- End function .text .globl _Z12computeErrorP15HIP_vector_typeIhLj3EES1_i # -- Begin function _Z12computeErrorP15HIP_vector_typeIhLj3EES1_i .p2align 4, 0x90 .type _Z12computeErrorP15HIP_vector_typeIhLj3EES1_i,@function _Z12computeErrorP15HIP_vector_typeIhLj3EES1_i: # @_Z12computeErrorP15HIP_vector_typeIhLj3EES1_i .cfi_startproc # %bb.0: # kill: def $edx killed $edx def $rdx testl %edx, %edx jle .LBB4_1 # %bb.3: # %.lr.ph.preheader movl %edx, %eax leaq (%rax,%rax,2), %rax xorps %xmm0, %xmm0 xorl %ecx, %ecx .p2align 4, 0x90 .LBB4_4: # %.lr.ph # =>This Inner Loop Header: Depth=1 movzbl (%rdi,%rcx), %r8d movzbl (%rsi,%rcx), %r9d subl %r9d, %r8d movl %r8d, %r9d negl %r9d cmovsl %r8d, %r9d movzbl %r9b, %r8d xorps %xmm1, %xmm1 cvtsi2ss %r8d, %xmm1 movzbl 1(%rdi,%rcx), %r8d movzbl 1(%rsi,%rcx), %r9d subl %r9d, %r8d movl %r8d, %r9d negl %r9d cmovsl %r8d, %r9d movzbl %r9b, %r8d xorps %xmm2, %xmm2 cvtsi2ss %r8d, %xmm2 addss %xmm0, %xmm1 movzbl 2(%rdi,%rcx), %r8d movzbl 2(%rsi,%rcx), %r9d subl %r9d, %r8d movl %r8d, %r9d negl %r9d cmovsl %r8d, %r9d movzbl %r9b, %r8d xorps %xmm0, %xmm0 cvtsi2ss %r8d, %xmm0 addss %xmm1, %xmm2 addss %xmm2, %xmm0 addq $3, %rcx cmpq %rcx, %rax jne .LBB4_4 jmp .LBB4_2 .LBB4_1: xorps %xmm0, %xmm0 .LBB4_2: # %._crit_edge leal (%rdx,%rdx,2), %eax xorps %xmm1, %xmm1 cvtsi2ss %eax, %xmm1 divss %xmm1, %xmm0 retq .Lfunc_end4: .size _Z12computeErrorP15HIP_vector_typeIhLj3EES1_i, .Lfunc_end4-_Z12computeErrorP15HIP_vector_typeIhLj3EES1_i .cfi_endproc # -- End function .globl _Z9concatStrPKcS0_ # -- Begin function _Z9concatStrPKcS0_ .p2align 4, 0x90 .type _Z9concatStrPKcS0_,@function _Z9concatStrPKcS0_: # @_Z9concatStrPKcS0_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rsi, %rbx movq %rdi, %r14 callq strlen movq %rax, %r15 movq %rbx, %rdi callq strlen leaq (%r15,%rax), %rdi incq %rdi callq malloc movq %rax, %r15 movq %rax, %rdi movq %r14, %rsi callq strcpy movq %r15, %rdi movq %rbx, %rsi popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 jmp strcat # TAILCALL .Lfunc_end5: .size _Z9concatStrPKcS0_, .Lfunc_end5-_Z9concatStrPKcS0_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $88, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %edi, %eax andl $-3, %eax cmpl $4, %eax jne .LBB6_1 # %bb.3: movq %rsi, %r14 movl %edi, %r12d movq 8(%rsi), %rdi leaq 8(%rsp), %rsi leaq 4(%rsp), %rdx leaq 80(%rsp), %rcx callq _Z7readPnmPcRiS0_RP15HIP_vector_typeIhLj3EE movl 8(%rsp), %esi movl 4(%rsp), %edx movl $.L.str.21, %edi xorl %eax, %eax callq printf movq 24(%r14), %rdi leaq 28(%rsp), %rsi leaq 24(%rsp), %rdx leaq 72(%rsp), %rcx callq _Z7readPnmPcRiS0_RP15HIP_vector_typeIhLj3EE movl 8(%rsp), %ebp cmpl %ebp, 28(%rsp) jne .LBB6_5 # %bb.4: movl 4(%rsp), %r13d cmpl %r13d, 24(%rsp) jne .LBB6_5 # %bb.6: movl $324, %edi # imm = 0x144 callq malloc movq %rax, %rcx xorl %eax, %eax movq %rcx, 16(%rsp) # 8-byte Spill .p2align 4, 0x90 .LBB6_7: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB6_8 Depth 2 xorl %edx, %edx .p2align 4, 0x90 .LBB6_8: # Parent Loop BB6_7 Depth=1 # => This Inner Loop Header: Depth=2 movl $1011500424, (%rcx,%rdx,4) # imm = 0x3C4A4588 incq %rdx cmpq $9, %rdx jne .LBB6_8 # %bb.9: # in Loop: Header=BB6_7 Depth=1 incq %rax addq $36, %rcx cmpq $9, %rax jne .LBB6_7 # %bb.10: movl %r13d, %eax imull %ebp, %eax cltq leaq (%rax,%rax,2), %rdi callq malloc movq %rax, %r15 movq 80(%rsp), %rdi movabsq $4294967297, %rax # imm = 0x100000001 movq %rax, 56(%rsp) movl $1, 64(%rsp) subq $8, %rsp .cfi_adjust_cfa_offset 8 movq 64(%rsp), %rax movq %rdi, 40(%rsp) # 8-byte Spill movl %ebp, %esi movl %r13d, %edx movq 24(%rsp), %rcx # 8-byte Reload movl $9, %r8d movq %r15, %r9 pushq $1 .cfi_adjust_cfa_offset 8 pushq %rax .cfi_adjust_cfa_offset 8 pushq $0 .cfi_adjust_cfa_offset 8 callq _Z7blurImgP15HIP_vector_typeIhLj3EEiiPfiS1_b4dim3 addq $32, %rsp .cfi_adjust_cfa_offset -32 movq 72(%rsp), %r13 movl 4(%rsp), %eax imull 8(%rsp), %eax testl %eax, %eax jle .LBB6_11 # %bb.12: # %.lr.ph.preheader.i movl %eax, %ecx leaq (%rcx,%rcx,2), %rcx xorps %xmm0, %xmm0 xorl %edx, %edx .p2align 4, 0x90 .LBB6_13: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 movzbl (%r15,%rdx), %esi movzbl (%r13,%rdx), %edi subl %edi, %esi movl %esi, %edi negl %edi cmovsl %esi, %edi movzbl %dil, %esi xorps %xmm1, %xmm1 cvtsi2ss %esi, %xmm1 movzbl 1(%r15,%rdx), %esi movzbl 1(%r13,%rdx), %edi subl %edi, %esi movl %esi, %edi negl %edi cmovsl %esi, %edi movzbl %dil, %esi xorps %xmm2, %xmm2 cvtsi2ss %esi, %xmm2 addss %xmm0, %xmm1 movzbl 2(%r15,%rdx), %esi movzbl 2(%r13,%rdx), %edi subl %edi, %esi movl %esi, %edi negl %edi cmovsl %esi, %edi movzbl %dil, %esi xorps %xmm0, %xmm0 cvtsi2ss %esi, %xmm0 addss %xmm1, %xmm2 addss %xmm2, %xmm0 addq $3, %rdx cmpq %rdx, %rcx jne .LBB6_13 jmp .LBB6_14 .LBB6_1: movl $.Lstr.1, %edi jmp .LBB6_2 .LBB6_5: movl $.Lstr, %edi .LBB6_2: callq puts@PLT movl $1, %eax .LBB6_21: addq $88, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB6_11: .cfi_def_cfa_offset 144 xorps %xmm0, %xmm0 .LBB6_14: # %_Z12computeErrorP15HIP_vector_typeIhLj3EES1_i.exit leal (%rax,%rax,2), %eax xorps %xmm1, %xmm1 cvtsi2ss %eax, %xmm1 divss %xmm1, %xmm0 cvtss2sd %xmm0, %xmm0 movl $.L.str.23, %edi movb $1, %al callq printf movslq 8(%rsp), %rax movslq 4(%rsp), %rcx imulq %rax, %rcx leaq (%rcx,%rcx,2), %rdi callq malloc movq %rax, %rbp movl $32, %eax movl $32, %ebx cmpl $6, %r12d jne .LBB6_16 # %bb.15: movq 32(%r14), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %rbx movq 40(%r14), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol .LBB6_16: movl 8(%rsp), %esi movl 4(%rsp), %edx movl %ebx, 40(%rsp) movl %eax, 44(%rsp) movl $1, 48(%rsp) subq $8, %rsp .cfi_adjust_cfa_offset 8 movq 48(%rsp), %rax movq 40(%rsp), %rdi # 8-byte Reload movq 24(%rsp), %rcx # 8-byte Reload movl $9, %r8d movq %rbp, %r9 pushq $1 .cfi_adjust_cfa_offset 8 pushq %rax .cfi_adjust_cfa_offset 8 pushq $1 .cfi_adjust_cfa_offset 8 callq _Z7blurImgP15HIP_vector_typeIhLj3EEiiPfiS1_b4dim3 addq $32, %rsp .cfi_adjust_cfa_offset -32 movl 4(%rsp), %eax imull 8(%rsp), %eax testl %eax, %eax jle .LBB6_17 # %bb.18: # %.lr.ph.preheader.i45 movl %eax, %ecx leaq (%rcx,%rcx,2), %rcx xorps %xmm0, %xmm0 xorl %edx, %edx .p2align 4, 0x90 .LBB6_19: # %.lr.ph.i47 # =>This Inner Loop Header: Depth=1 movzbl (%rbp,%rdx), %esi movzbl (%r13,%rdx), %edi subl %edi, %esi movl %esi, %edi negl %edi cmovsl %esi, %edi movzbl %dil, %esi xorps %xmm1, %xmm1 cvtsi2ss %esi, %xmm1 movzbl 1(%rbp,%rdx), %esi movzbl 1(%r13,%rdx), %edi subl %edi, %esi movl %esi, %edi negl %edi cmovsl %esi, %edi movzbl %dil, %esi xorps %xmm2, %xmm2 cvtsi2ss %esi, %xmm2 addss %xmm0, %xmm1 movzbl 2(%rbp,%rdx), %esi movzbl 2(%r13,%rdx), %edi subl %edi, %esi movl %esi, %edi negl %edi cmovsl %esi, %edi movzbl %dil, %esi xorps %xmm0, %xmm0 cvtsi2ss %esi, %xmm0 addss %xmm1, %xmm2 addss %xmm2, %xmm0 addq $3, %rdx cmpq %rdx, %rcx jne .LBB6_19 jmp .LBB6_20 .LBB6_17: xorps %xmm0, %xmm0 .LBB6_20: # %_Z12computeErrorP15HIP_vector_typeIhLj3EES1_i.exit52 leal (%rax,%rax,2), %eax xorps %xmm1, %xmm1 cvtsi2ss %eax, %xmm1 divss %xmm1, %xmm0 cvtss2sd %xmm0, %xmm0 movl $.L.str.23, %edi movb $1, %al callq printf movq 16(%r14), %rdi movl $.L.str.24, %esi callq strtok movq %rax, %r14 movl 8(%rsp), %eax movl %eax, 12(%rsp) # 4-byte Spill movl 4(%rsp), %r12d movq %r14, %rdi callq strlen leaq 10(%rax), %rdi callq malloc movq %rax, %rbx movq %rax, %rdi movq %r14, %rsi callq strcpy movq %rbx, %rdi callq strlen movabsq $7957911619251431519, %rcx # imm = 0x6E702E74736F685F movq %rcx, (%rbx,%rax) movw $109, 8(%rbx,%rax) movq %r15, %rdi movl 12(%rsp), %esi # 4-byte Reload movl %r12d, %edx movq %rbx, %rcx callq _Z8writePnmP15HIP_vector_typeIhLj3EEiiPc movl 8(%rsp), %eax movl %eax, 12(%rsp) # 4-byte Spill movl 4(%rsp), %r12d movq %r14, %rdi callq strlen leaq 12(%rax), %rdi callq malloc movq %rax, %rbx movq %rax, %rdi movq %r14, %rsi callq strcpy movq %rbx, %rdi callq strlen movabsq $3343187603001533535, %rcx # imm = 0x2E6563697665645F movq %rcx, (%rbx,%rax) movl $7171696, 8(%rbx,%rax) # imm = 0x6D6E70 movq %rbp, %rdi movl 12(%rsp), %esi # 4-byte Reload movl %r12d, %edx movq %rbx, %rcx callq _Z8writePnmP15HIP_vector_typeIhLj3EEiiPc movq 32(%rsp), %rdi # 8-byte Reload callq free movq %r13, %rdi callq free movq %r15, %rdi callq free movq %rbp, %rdi callq free movq 16(%rsp), %rdi # 8-byte Reload callq free xorl %eax, %eax jmp .LBB6_21 .Lfunc_end6: .size main, .Lfunc_end6-main .cfi_endproc # -- End function .section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat .hidden __clang_call_terminate # -- Begin function __clang_call_terminate .weak __clang_call_terminate .p2align 4, 0x90 .type __clang_call_terminate,@function __clang_call_terminate: # @__clang_call_terminate .cfi_startproc # %bb.0: pushq %rax .cfi_def_cfa_offset 16 callq __cxa_begin_catch callq _ZSt9terminatev .Lfunc_end7: .size __clang_call_terminate, .Lfunc_end7-__clang_call_terminate .cfi_endproc # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB8_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB8_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end8: .size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB9_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB9_2: retq .Lfunc_end9: .size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "r" .size .L.str, 2 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Cannot read %s\n" .size .L.str.1, 16 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "%s" .size .L.str.2, 3 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "P3" .size .L.str.3, 3 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "%i" .size .L.str.4, 3 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "%hhu%hhu%hhu" .size .L.str.5, 13 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "w" .size .L.str.6, 2 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Cannot write %s\n" .size .L.str.7, 17 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "P3\n%i\n%i\n255\n" .size .L.str.8, 14 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "%hhu\n%hhu\n%hhu\n" .size .L.str.9, 16 .type _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_,@object # @_Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ .section .rodata,"a",@progbits .globl _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ .p2align 3, 0x0 _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_: .quad _Z28__device_stub__blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ .size _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_, 8 .type .L.str.10,@object # @.str.10 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.10: .asciz "GPU name: %s\n" .size .L.str.10, 14 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "GPU compute capability: %d.%d\n" .size .L.str.11, 31 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz "Error: %s:%d, " .size .L.str.12, 15 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz "/home/ubuntu/Datasets/Stack_v2_cuda-hip-as/e242fabb7ad2b0f310afe5f576785cf6a98722d2.hip" .size .L.str.13, 88 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz "code: %d, reason: %s\n" .size .L.str.14, 22 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "Sync kernel error: %s\n" .size .L.str.15, 23 .type .L.str.16,@object # @.str.16 .L.str.16: .asciz "Async kernel error: %s\n" .size .L.str.16, 24 .type .L.str.17,@object # @.str.17 .L.str.17: .asciz "Processing time (%s): %f ms\n" .size .L.str.17, 29 .type .L.str.18,@object # @.str.18 .L.str.18: .asciz "use device" .size .L.str.18, 11 .type .L.str.19,@object # @.str.19 .L.str.19: .asciz "use host" .size .L.str.19, 9 .type .L.str.21,@object # @.str.21 .L.str.21: .asciz "Image size (width x height): %i x %i\n\n" .size .L.str.21, 39 .type .L.str.23,@object # @.str.23 .L.str.23: .asciz "Error: %f\n\n" .size .L.str.23, 12 .type .L.str.24,@object # @.str.24 .L.str.24: .asciz "." .size .L.str.24, 2 .type .L.str.25,@object # @.str.25 .L.str.25: .asciz "_host.pnm" .size .L.str.25, 10 .type .L.str.26,@object # @.str.26 .L.str.26: .asciz "_device.pnm" .size .L.str.26, 12 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_" .size .L__unnamed_1, 51 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "The shape of the correct output image is invalid" .size .Lstr, 49 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "The number of arguments is invalid" .size .Lstr.1, 35 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ .addrsig_sym __gxx_personality_v0 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Unwind_Resume .addrsig_sym _Z13blurImgKernelP15HIP_vector_typeIhLj3EEiiPfiS1_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
4,403
14,856
4,105
22,645
119
code for sm_80 Function : _Z5helloPcPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_TID.X ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IADD3 R4, P0, R2.reuse, c[0x0][0x160], RZ ; IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; IADD3.X R5, RZ, c[0x0][0x164], RZ, P0, !PT ; LDG.E.U8 R3, [R2.64] ; LDG.E.U8 R0, [R4.64] ; IADD3 R7, R0, R3, RZ ; STG.E.U8 [R4.64], R7 ; EXIT ; BRA 0xc0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00087f7d_00000000-6_9d9a1002b4dca62d18c3fd09bf166d289330587e.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z26__device_stub__Z5helloPcPiPcPi .type _Z26__device_stub__Z5helloPcPiPcPi, @function _Z26__device_stub__Z5helloPcPiPcPi: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z5helloPcPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z26__device_stub__Z5helloPcPiPcPi, .-_Z26__device_stub__Z5helloPcPiPcPi .globl _Z5helloPcPi .type _Z5helloPcPi, @function _Z5helloPcPi: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z5helloPcPiPcPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z5helloPcPi, .-_Z5helloPcPi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%s" .LC1: .string "%s\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 subq $144, %rsp .cfi_def_cfa_offset 160 movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax movabsq $35662932501832, %rax movl $0, %edx movq %rax, 112(%rsp) movq %rdx, 120(%rsp) movl $15, 48(%rsp) movl $10, 52(%rsp) movl $6, 56(%rsp) movl $0, 60(%rsp) movl $-11, 64(%rsp) movl $1, 68(%rsp) movl $0, 72(%rsp) movl $0, 76(%rsp) movl $0, 80(%rsp) movl $0, 84(%rsp) movl $0, 88(%rsp) movl $0, 92(%rsp) movl $0, 96(%rsp) movl $0, 100(%rsp) movl $0, 104(%rsp) movl $0, 108(%rsp) leaq 112(%rsp), %rbx movq %rbx, %rdx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 8(%rsp), %rdi movl $16, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $64, %esi call cudaMalloc@PLT movl $1, %ecx movl $16, %edx movq %rbx, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT leaq 48(%rsp), %rsi movl $1, %ecx movl $64, %edx movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $16, 24(%rsp) movl $1, 28(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $0, %r9d movl $0, %r8d movq 24(%rsp), %rdx movl $1, %ecx movq 36(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L15 .L12: leaq 112(%rsp), %rbx movl $2, %ecx movl $16, %edx movq 8(%rsp), %rsi movq %rbx, %rdi call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdx leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 136(%rsp), %rax subq %fs:40, %rax jne .L16 movl $0, %eax addq $144, %rsp .cfi_remember_state .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z26__device_stub__Z5helloPcPiPcPi jmp .L12 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC2: .string "_Z5helloPcPi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z5helloPcPi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z5helloPcPi ; -- Begin function _Z5helloPcPi .globl _Z5helloPcPi .p2align 8 .type _Z5helloPcPi,@function _Z5helloPcPi: ; @_Z5helloPcPi ; %bb.0: s_load_b128 s[0:3], s[0:1], 0x0 v_lshlrev_b32_e32 v1, 2, v0 s_waitcnt lgkmcnt(0) global_load_b32 v1, v1, s[2:3] global_load_u8 v2, v0, s[0:1] s_waitcnt vmcnt(0) v_add_nc_u16 v1, v2, v1 global_store_b8 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5helloPcPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 4 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z5helloPcPi, .Lfunc_end0-_Z5helloPcPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 64 ; NumSgprs: 4 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 4 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5helloPcPi .private_segment_fixed_size: 0 .sgpr_count: 4 .sgpr_spill_count: 0 .symbol: _Z5helloPcPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "9d9a1002b4dca62d18c3fd09bf166d289330587e.hip" .globl _Z20__device_stub__helloPcPi # -- Begin function _Z20__device_stub__helloPcPi .p2align 4, 0x90 .type _Z20__device_stub__helloPcPi,@function _Z20__device_stub__helloPcPi: # @_Z20__device_stub__helloPcPi .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z5helloPcPi, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z20__device_stub__helloPcPi, .Lfunc_end0-_Z20__device_stub__helloPcPi .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $176, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -16 movl $1819043144, 16(%rsp) # imm = 0x6C6C6548 movw $8303, 20(%rsp) # imm = 0x206F movq $0, 22(%rsp) movw $0, 30(%rsp) xorps %xmm0, %xmm0 movaps %xmm0, 112(%rsp) movaps %xmm0, 128(%rsp) movaps %xmm0, 160(%rsp) movaps %xmm0, 144(%rsp) movabsq $42949672975, %rax # imm = 0xA0000000F movq %rax, 112(%rsp) movl $6, 120(%rsp) movabsq $8589934581, %rax # imm = 0x1FFFFFFF5 movq %rax, 128(%rsp) leaq 16(%rsp), %rbx movl $.L.str, %edi movq %rbx, %rsi xorl %eax, %eax callq printf movq %rsp, %rdi movl $16, %esi callq hipMalloc leaq 8(%rsp), %rdi movl $64, %esi callq hipMalloc movq (%rsp), %rdi movl $16, %edx movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi leaq 112(%rsp), %rsi movl $64, %edx movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 15(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq (%rsp), %rax movq 8(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z5helloPcPi, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq (%rsp), %rsi leaq 16(%rsp), %rbx movl $16, %edx movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movq (%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq puts@PLT xorl %eax, %eax addq $176, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5helloPcPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z5helloPcPi,@object # @_Z5helloPcPi .section .rodata,"a",@progbits .globl _Z5helloPcPi .p2align 3, 0x0 _Z5helloPcPi: .quad _Z20__device_stub__helloPcPi .size _Z5helloPcPi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%s" .size .L.str, 3 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z5helloPcPi" .size .L__unnamed_1, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z20__device_stub__helloPcPi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z5helloPcPi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
427
2,893
1,686
2,894
120
code for sm_80 Function : _Z4normPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2UR UR4, SR_CTAID.X ; S2R R0, SR_TID.X ; ULDC UR5, c[0x0][0x0] ; UIMAD UR4, UR4, UR5, URZ ; IADD3 R0, R0, UR4, RZ ; ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; @P0 EXIT ; IABS R8, c[0x0][0x178] ; S2UR UR5, SR_CTAID.Y ; S2R R7, SR_TID.Y ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; I2F.RP R4, R8 ; ULDC UR6, c[0x0][0x4] ; MUFU.RCP R4, R4 ; UIMAD UR5, UR5, UR6, URZ ; IADD3 R7, R7, UR5, RZ ; IADD3 R2, R4, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.MOV R5, RZ, RZ, -R3 ; IMAD R5, R5, R8, RZ ; IMAD.HI.U32 R3, R3, R5, R2 ; LOP3.LUT R2, R6, 0x640000, RZ, 0x3c, !PT ; ISETP.GE.AND P2, PT, R2, RZ, PT ; IMAD.HI.U32 R3, R3, 0x640000, RZ ; IMAD.MOV R5, RZ, RZ, -R3 ; IMAD R5, R8, R5, 0x640000 ; ISETP.GT.U32.AND P1, PT, R8, R5, PT ; @!P1 IMAD.IADD R5, R5, 0x1, -R8 ; @!P1 IADD3 R3, R3, 0x1, RZ ; ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; ISETP.GE.U32.AND P0, PT, R5, R8, PT ; @P0 IADD3 R3, R3, 0x1, RZ ; @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; @!P1 LOP3.LUT R3, RZ, c[0x0][0x178], RZ, 0x33, !PT ; ISETP.GE.AND P0, PT, R7, R3, PT ; @P0 EXIT ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; ULDC.64 UR8, c[0x0][0x118] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; LDG.E R8, [R2.64] ; LDG.E R9, [R2.64+0x4] ; LDG.E R10, [R2.64+0x8] ; LDG.E R11, [R2.64+0xc] ; LDG.E R12, [R2.64+0x10] ; LDG.E R13, [R2.64+0x14] ; LDG.E R14, [R2.64+0x18] ; LDG.E R15, [R2.64+0x1c] ; LDG.E R16, [R2.64+0x20] ; LDG.E R17, [R2.64+0x24] ; LDG.E R18, [R2.64+0x28] ; LDG.E R19, [R2.64+0x2c] ; LDG.E R20, [R2.64+0x30] ; LDG.E R21, [R2.64+0x34] ; LDG.E R22, [R2.64+0x38] ; LDG.E R23, [R2.64+0x3c] ; UIADD3 UR6, UR4, 0x1, URZ ; IMAD.MOV.U32 R29, RZ, RZ, RZ ; ULDC UR7, c[0x0][0x178] ; IMAD.MOV.U32 R24, RZ, RZ, RZ ; UIMAD UR6, UR6, UR7, UR5 ; UIMAD UR4, UR4, UR7, UR5 ; IMAD.U32 R25, RZ, RZ, UR6 ; IMAD.U32 R27, RZ, RZ, UR4 ; IMAD.MOV.U32 R26, RZ, RZ, 0x4 ; IMAD.WIDE R2, R27, R26, c[0x0][0x160] ; LDG.E R4, [R2.64] ; LDG.E R33, [R2.64+0x4] ; LDG.E R34, [R2.64+0x8] ; LDG.E R28, [R2.64+0xc] ; LDG.E R31, [R2.64+0x10] ; LDG.E R30, [R2.64+0x14] ; LDG.E R5, [R2.64+0x18] ; LDG.E R32, [R2.64+0x1c] ; LDG.E R35, [R2.64+0x20] ; FFMA R4, R8, R4, R29 ; LDG.E R29, [R2.64+0x28] ; FFMA R33, R9, R33, R4 ; LDG.E R4, [R2.64+0x24] ; FFMA R33, R10, R34, R33 ; FFMA R28, R11, R28, R33 ; LDG.E R33, [R2.64+0x38] ; FFMA R31, R12, R31, R28 ; LDG.E R28, [R2.64+0x2c] ; FFMA R30, R13, R30, R31 ; LDG.E R31, [R2.64+0x30] ; FFMA R5, R14, R5, R30 ; LDG.E R30, [R2.64+0x34] ; FFMA R5, R15, R32, R5 ; LDG.E R32, [R2.64+0x3c] ; FFMA R5, R16, R35, R5 ; FFMA R34, R17, R4, R5 ; IMAD.WIDE R4, R25, R26, c[0x0][0x160] ; FFMA R34, R18, R29, R34 ; LDG.E R36, [R4.64+0xc] ; LDG.E R29, [R4.64] ; FFMA R28, R19, R28, R34 ; LDG.E R34, [R4.64+0x4] ; FFMA R28, R20, R31, R28 ; LDG.E R31, [R4.64+0x8] ; FFMA R28, R21, R30, R28 ; LDG.E R2, [R4.64+0x14] ; FFMA R28, R22, R33, R28 ; LDG.E R33, [R4.64+0x10] ; LDG.E R3, [R4.64+0x18] ; FFMA R28, R23, R32, R28 ; LDG.E R30, [R4.64+0x24] ; LDG.E R32, [R4.64+0x2c] ; FFMA R29, R8, R29, R28 ; LDG.E R28, [R4.64+0x1c] ; FFMA R34, R9, R34, R29 ; LDG.E R29, [R4.64+0x20] ; FFMA R31, R10, R31, R34 ; LDG.E R34, [R4.64+0x3c] ; FFMA R36, R11, R36, R31 ; LDG.E R31, [R4.64+0x28] ; FFMA R33, R12, R33, R36 ; FFMA R2, R13, R2, R33 ; LDG.E R33, [R4.64+0x30] ; FFMA R35, R14, R3, R2 ; LDG.E R2, [R4.64+0x34] ; LDG.E R3, [R4.64+0x38] ; IADD3 R24, R24, 0x2, RZ ; ISETP.NE.AND P0, PT, R24, 0x10, PT ; IMAD R27, R6.reuse, 0x2, R27 ; IMAD R25, R6, 0x2, R25 ; FFMA R28, R15, R28, R35 ; FFMA R28, R16, R29, R28 ; FFMA R28, R17, R30, R28 ; FFMA R28, R18, R31, R28 ; FFMA R28, R19, R32, R28 ; FFMA R28, R20, R33, R28 ; FFMA R2, R21, R2, R28 ; FFMA R2, R22, R3, R2 ; FFMA R29, R23, R34, R2 ; @P0 BRA 0x410 ; LOP3.LUT R2, R7, 0x1, RZ, 0xc0, !PT ; IMAD R27, R0.reuse, c[0x0][0x178], R7 ; LOP3.LUT R3, R0, 0x1, RZ, 0xc0, !PT ; ISETP.NE.U32.AND P1, PT, R2, 0x1, PT ; ISETP.EQ.U32.OR P0, PT, R3, 0x1, !P1 ; IMAD.WIDE R2, R27, R26, c[0x0][0x168] ; IMAD.WIDE R26, R27, R26, c[0x0][0x160] ; @!P0 BRA 0xc80 ; LEA.HI R4, R0, R0, RZ, 0x1 ; LOP3.LUT R5, R4, 0xfffffffe, RZ, 0xc0, !PT ; IMAD.IADD R5, R0, 0x1, -R5 ; ISETP.EQ.AND P0, PT, R5, 0x1, PT ; @P1 BRA P0, 0xb80 ; ISETP.NE.AND P0, PT, R5, 0x1, PT ; @!P0 LEA.HI R0, R7, R7, RZ, 0x1 ; @!P0 LOP3.LUT R0, R0, 0xfffffffe, RZ, 0xc0, !PT ; @!P0 IMAD.IADD R0, R7, 0x1, -R0 ; ISETP.EQ.AND P0, PT, R0, 0x1, !P0 ; @!P0 STG.E [R2.64], RZ ; @!P0 EXIT ; LDG.E R26, [R26.64] ; F2F.F64.F32 R12, R29 ; IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; BSSY B0, 0xb50 ; MUFU.RCP64H R5, R13 ; DFMA R6, -R12, R4, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R4, R6, R4 ; DFMA R8, -R12, R6, 1 ; DFMA R8, R6, R8, R6 ; F2F.F64.F32 R4, R26 ; DMUL R6, R4, -R8 ; DFMA R10, -R12, R6, -R4 ; DADD R4, -RZ, -R4 ; DFMA R6, R8, R10, R6 ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; FFMA R0, RZ, R13, R7 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xb40 ; IMAD.MOV.U32 R8, RZ, RZ, R4 ; MOV R0, 0xb40 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; CALL.REL.NOINC 0xe30 ; BSYNC B0 ; F2F.F32.F64 R7, R6 ; STG.E [R2.64], R7 ; EXIT ; LDG.E R26, [R26.64] ; MUFU.RCP R0, R29 ; BSSY B0, 0xc60 ; FFMA R5, -R29, R0, 1 ; FFMA R5, R0, R5, R0 ; FCHK P0, R26, R29 ; FFMA R0, R26, R5, RZ ; FFMA R4, -R29, R0, R26 ; FFMA R5, R5, R4, R0 ; @!P0 BRA 0xc50 ; MOV R0, 0xc40 ; CALL.REL.NOINC 0x1430 ; IMAD.MOV.U32 R5, RZ, RZ, R6 ; BSYNC B0 ; STG.E [R2.64], R5 ; EXIT ; LDG.E R26, [R26.64] ; F2F.F64.F32 R12, R29 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B0, 0xe00 ; MUFU.RCP64H R7, R13 ; DFMA R4, -R12, R6, 1 ; DFMA R8, R4, R4, R4 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R12, R8, 1 ; DFMA R6, R8, R6, R8 ; F2F.F64.F32 R4, R26 ; DADD R4, R4, R4 ; DMUL R8, R4, R6 ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; DFMA R10, -R12, R8, R4 ; DFMA R6, R6, R10, R8 ; FFMA R0, RZ, R13, R7 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xdf0 ; IMAD.MOV.U32 R8, RZ, RZ, R4 ; MOV R0, 0xdf0 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; CALL.REL.NOINC 0xe30 ; BSYNC B0 ; F2F.F32.F64 R7, R6 ; STG.E [R2.64], R7 ; EXIT ; FSETP.GEU.AND P0, PT, |R13|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R6, RZ, RZ, R12.reuse ; LOP3.LUT R4, R13, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R7, RZ, RZ, R13 ; FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R4, RZ, RZ, R12 ; LOP3.LUT R12, R9, 0x7ff00000, RZ, 0xc0, !PT ; BSSY B1, 0x13e0 ; LOP3.LUT R20, R13, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; ISETP.GE.U32.AND P1, PT, R12, R20, PT ; @!P2 LOP3.LUT R11, R7, 0x7ff00000, RZ, 0xc0, !PT ; @!P2 IMAD.MOV.U32 R14, RZ, RZ, RZ ; MUFU.RCP64H R17, R5 ; SEL R15, R13, 0x63400000, !P1 ; @!P2 ISETP.GE.U32.AND P3, PT, R12, R11, PT ; @!P0 LOP3.LUT R20, R5, 0x7ff00000, RZ, 0xc0, !PT ; @!P2 SEL R21, R13, 0x63400000, !P3 ; IADD3 R22, R20, -0x1, RZ ; @!P2 LOP3.LUT R21, R21, 0x80000000, R9, 0xf8, !PT ; DFMA R10, R16, -R4, 1 ; DFMA R18, R10, R10, R10 ; LOP3.LUT R11, R15, 0x800fffff, R9, 0xf8, !PT ; IMAD.MOV.U32 R10, RZ, RZ, R8 ; @!P2 LOP3.LUT R15, R21, 0x100000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R21, RZ, RZ, R12 ; DFMA R18, R16, R18, R16 ; @!P2 DFMA R10, R10, 2, -R14 ; DFMA R14, R18, -R4, 1 ; @!P2 LOP3.LUT R21, R11, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R14, R18, R14, R18 ; IADD3 R18, R21, -0x1, RZ ; DMUL R16, R14, R10 ; ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ; ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; DFMA R18, R16, -R4, R10 ; DFMA R14, R14, R18, R16 ; @P0 BRA 0x1280 ; LOP3.LUT R9, R7, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R12.reuse, R9, PT ; IMAD.IADD R8, R12, 0x1, -R9 ; SEL R13, R13, 0x63400000, !P0 ; IMNMX R8, R8, -0x46a00000, !PT ; IMNMX R8, R8, 0x46a00000, PT ; IMAD.IADD R16, R8, 0x1, -R13 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; IADD3 R9, R16, 0x7fe00000, RZ ; DMUL R12, R14, R8 ; FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; @P0 BRA 0x13d0 ; DFMA R4, R14, -R4, R10 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; LOP3.LUT R7, R5, 0x80000000, R7, 0x48, !PT ; LOP3.LUT R9, R7, R9, RZ, 0xfc, !PT ; @!P0 BRA 0x13d0 ; IMAD.MOV R5, RZ, RZ, -R16 ; DMUL.RP R8, R14, R8 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; DFMA R4, R12, -R4, R14 ; LOP3.LUT R7, R9, R7, RZ, 0x3c, !PT ; IADD3 R4, -R16, -0x43300000, RZ ; FSETP.NEU.AND P0, PT, |R5|, R4, PT ; FSEL R12, R8, R12, !P0 ; FSEL R13, R7, R13, !P0 ; BRA 0x13d0 ; DSETP.NAN.AND P0, PT, R8, R8, PT ; @P0 BRA 0x13b0 ; DSETP.NAN.AND P0, PT, R6, R6, PT ; @P0 BRA 0x1380 ; ISETP.NE.AND P0, PT, R21, R20, PT ; IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; @!P0 BRA 0x13d0 ; ISETP.NE.AND P0, PT, R21, 0x7ff00000, PT ; LOP3.LUT R13, R9, 0x80000000, R7, 0x48, !PT ; ISETP.EQ.OR P0, PT, R20, RZ, !P0 ; @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; BRA 0x13d0 ; LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R12, RZ, RZ, R6 ; BRA 0x13d0 ; LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R12, RZ, RZ, R8 ; BSYNC B1 ; IMAD.MOV.U32 R4, RZ, RZ, R0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; IMAD.MOV.U32 R6, RZ, RZ, R12 ; IMAD.MOV.U32 R7, RZ, RZ, R13 ; RET.REL.NODEC R4 0x0 ; SHF.R.U32.HI R5, RZ, 0x17, R29.reuse ; BSSY B1, 0x1a90 ; SHF.R.U32.HI R4, RZ, 0x17, R26.reuse ; IMAD.MOV.U32 R6, RZ, RZ, R29 ; LOP3.LUT R13, R5, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R5, RZ, RZ, R26 ; LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; IADD3 R9, R13, -0x1, RZ ; IADD3 R8, R4, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R9, 0xfd, PT ; ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ; @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; @!P0 BRA 0x1670 ; FSETP.GTU.FTZ.AND P0, PT, |R26|, +INF , PT ; FSETP.GTU.FTZ.AND P1, PT, |R29|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0x1a70 ; LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; @!P0 BRA 0x1a50 ; FSETP.NEU.FTZ.AND P1, PT, |R26|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P2, PT, |R29|, +INF , PT ; FSETP.NEU.FTZ.AND P0, PT, |R26|, +INF , PT ; @!P2 BRA !P1, 0x1a50 ; LOP3.LUT P1, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P1, PT, P2, P1, PT, 0x2a, 0x0 ; @P1 BRA 0x1a30 ; LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; @P0 BRA 0x1a00 ; ISETP.GE.AND P0, PT, R8, RZ, PT ; ISETP.GE.AND P1, PT, R9, RZ, PT ; @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; @!P0 FFMA R5, R26, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R6, R29, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R7, R7, 0x40, RZ ; LEA R9, R13, 0xc0800000, 0x17 ; BSSY B2, 0x19f0 ; IADD3 R4, R4, -0x7f, RZ ; IMAD.IADD R9, R6, 0x1, -R9 ; IMAD R5, R4, -0x800000, R5 ; MUFU.RCP R6, R9 ; FADD.FTZ R8, -R9, -RZ ; FFMA R11, R6, R8, 1 ; FFMA R10, R6, R11, R6 ; FFMA R6, R5, R10, RZ ; FFMA R11, R8, R6, R5 ; FFMA R11, R10, R11, R6 ; IADD3 R6, R4, 0x7f, -R13 ; FFMA R8, R8, R11, R5 ; IMAD.IADD R6, R6, 0x1, R7 ; FFMA R5, R10, R8, R11 ; SHF.R.U32.HI R4, RZ, 0x17, R5 ; LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; IMAD.IADD R12, R4, 0x1, R6 ; IADD3 R4, R12, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; @!P0 BRA 0x19d0 ; ISETP.GT.AND P0, PT, R12, 0xfe, PT ; @P0 BRA 0x19a0 ; ISETP.GE.AND P0, PT, R12, 0x1, PT ; @P0 BRA 0x19e0 ; ISETP.GE.AND P0, PT, R12, -0x18, PT ; LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0x19e0 ; FFMA.RZ R4, R10, R8.reuse, R11.reuse ; IADD3 R9, R12, 0x20, RZ ; FFMA.RM R7, R10, R8.reuse, R11.reuse ; ISETP.NE.AND P2, PT, R12, RZ, PT ; LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; FFMA.RP R4, R10, R8, R11 ; ISETP.NE.AND P1, PT, R12, RZ, PT ; IMAD.MOV R8, RZ, RZ, -R12 ; LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; FSETP.NEU.FTZ.AND P0, PT, R4, R7, PT ; SHF.L.U32 R9, R6, R9, RZ ; SEL R7, R8, RZ, P2 ; ISETP.NE.AND P1, PT, R9, RZ, P1 ; SHF.R.U32.HI R7, RZ, R7, R6 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R9, RZ, 0x1, R7 ; SEL R4, RZ, 0x1, !P0 ; LOP3.LUT R4, R4, 0x1, R9, 0xf8, !PT ; LOP3.LUT R4, R4, R7, RZ, 0xc0, !PT ; IMAD.IADD R4, R9, 0x1, R4 ; LOP3.LUT R5, R4, R5, RZ, 0xfc, !PT ; BRA 0x19e0 ; LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x19e0 ; IMAD R5, R6, 0x800000, R5 ; BSYNC B2 ; BRA 0x1a80 ; LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x1a80 ; LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; BRA 0x1a80 ; MUFU.RSQ R5, -QNAN ; BRA 0x1a80 ; FADD.FTZ R5, R26, R29 ; BSYNC B1 ; IMAD.MOV.U32 R6, RZ, RZ, R5 ; IMAD.MOV.U32 R4, RZ, RZ, R0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; RET.REL.NODEC R4 0x0 ; BRA 0x1ad0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000e2a3c_00000000-6_0107933563b079f2d27773ec71b3934cea183122.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC4: .string "results checking failed at %d ref %f out %f\n" .section .rodata.str1.1,"aMS",@progbits,1 .LC5: .string "results checking passed!\n" .text .globl _Z11checkresultPfS_S_S_i .type _Z11checkresultPfS_S_S_i, @function _Z11checkresultPfS_S_S_i: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $40, %rsp .cfi_def_cfa_offset 96 movq %rdi, %r9 movq %rsi, %r11 movq %rdx, %rsi movq %r11, %r14 movl %r8d, %edx sall $4, %edx movslq %edx, %rax leaq 0(,%rax,4), %r13 movslq %r8d, %rax salq $2, %rax movl $0, %r10d movl $0, %ebx movq .LC1(%rip), %xmm3 movl %ebx, %r12d movl %r10d, %ebp movq %rsi, %r15 movl %edx, %esi jmp .L4 .L31: movslq %edi, %rdx pxor %xmm0, %xmm0 cvtss2sd (%r11,%rdx,4), %xmm0 addsd %xmm0, %xmm0 pxor %xmm2, %xmm2 cvtss2sd %xmm1, %xmm2 divsd %xmm2, %xmm0 cvtsd2ss %xmm0, %xmm0 movss %xmm0, (%r9,%rdx,4) jmp .L9 .L11: cmpl $1, %r14d je .L29 .L10: movslq %edi, %rdx movl $0x00000000, (%r9,%rdx,4) .L9: addl $1, %eax addl %r8d, %edi cmpl $16, %eax je .L30 .L12: movl %r13d, %edx orl %eax, %edx testb $1, %dl je .L31 movl %eax, %r10d shrl $31, %r10d leal (%rax,%r10), %edx andl $1, %edx subl %r10d, %edx cmpl $1, %edx jne .L10 testl %r15d, %r15d jne .L11 movslq %edi, %rdx movss (%r11,%rdx,4), %xmm0 divss %xmm1, %xmm0 movss %xmm0, (%r9,%rdx,4) jmp .L9 .L29: movslq %edi, %rdx pxor %xmm0, %xmm0 cvtss2sd (%r11,%rdx,4), %xmm0 xorpd %xmm3, %xmm0 pxor %xmm2, %xmm2 cvtss2sd %xmm1, %xmm2 divsd %xmm2, %xmm0 cvtsd2ss %xmm0, %xmm0 movss %xmm0, (%r9,%rdx,4) jmp .L9 .L30: addl $1, %r13d cmpl $16, %r13d je .L32 .L7: movl %r13d, %eax shrl $31, %eax leal 0(%r13,%rax), %r14d andl $1, %r14d subl %eax, %r14d movl 4(%rsp), %eax leal 0(%r13,%rax), %edi movl $0, %eax movl %r13d, %r15d andl $1, %r15d jmp .L12 .L32: movq 8(%rsp), %rax movl 16(%rsp), %edx movl 4(%rsp), %r10d movq %rbx, %rdi movl 20(%rsp), %ebx addl $16, %edx addl %ebx, %r10d addq %rsi, %rdi cmpl $2560, %edx je .L33 .L14: movq %rdi, %r14 movl $16, %r15d pxor %xmm1, %xmm1 .L5: movl $0, %r13d .L6: movss (%r14,%r13), %xmm0 mulss (%rcx,%r13), %xmm0 addss %xmm0, %xmm1 addq $4, %r13 cmpq $64, %r13 jne .L6 addq %rax, %r14 subl $1, %r15d jne .L5 movl $0, %r13d movq %rax, 8(%rsp) movl %edx, 16(%rsp) movl %r10d, 4(%rsp) movl %ebx, 20(%rsp) movq %rdi, %rbx jmp .L7 .L33: movq %rsi, %r13 movl %ebx, %esi movq %r12, %r14 movl 24(%rsp), %r12d movq %rbp, %r15 movl 28(%rsp), %ebp addl $1, %r12d addl $16, %ebp addq $64, %r14 cmpl $160, %r12d je .L20 .L4: movq %r14, %rdi movl %ebp, %r10d movl $0, %edx movl %r12d, 24(%rsp) movl %esi, %ebx movq %r13, %rsi movl %ebp, 28(%rsp) movq %r14, %r12 movq %r15, %rbp jmp .L14 .L20: movq %r15, %rsi movl $0, %eax movss .LC2(%rip), %xmm3 .L15: movss (%r9,%rax,4), %xmm2 movss (%rsi,%rax,4), %xmm1 movaps %xmm2, %xmm0 subss %xmm1, %xmm0 andps %xmm3, %xmm0 cvtss2sd %xmm0, %xmm0 comisd .LC3(%rip), %xmm0 ja .L34 addq $1, %rax cmpq $6553600, %rax jne .L15 leaq .LC5(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L3 .L34: pxor %xmm0, %xmm0 cvtss2sd %xmm2, %xmm0 cvtss2sd %xmm1, %xmm1 movl %eax, %edx leaq .LC4(%rip), %rsi movl $2, %edi movl $2, %eax call __printf_chk@PLT .L3: addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z11checkresultPfS_S_S_i, .-_Z11checkresultPfS_S_S_i .globl _Z28__device_stub__Z4normPfS_S_iPfS_S_i .type _Z28__device_stub__Z4normPfS_S_iPfS_S_i, @function _Z28__device_stub__Z4normPfS_S_iPfS_S_i: .LFB2083: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L39 .L35: movq 136(%rsp), %rax subq %fs:40, %rax jne .L40 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L39: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z4normPfS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L35 .L40: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z28__device_stub__Z4normPfS_S_iPfS_S_i, .-_Z28__device_stub__Z4normPfS_S_iPfS_S_i .globl _Z4normPfS_S_i .type _Z4normPfS_S_i, @function _Z4normPfS_S_i: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z28__device_stub__Z4normPfS_S_iPfS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z4normPfS_S_i, .-_Z4normPfS_S_i .section .rodata.str1.1 .LC8: .string "kernel time %fs\n" .text .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $104, %rsp .cfi_def_cfa_offset 160 movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax movl $26214400, %edi call malloc@PLT movq %rax, %r12 movl $26214400, %edi call malloc@PLT movq %rax, %r14 movl $64, %edi call malloc@PLT movq %rax, %r13 movl $26214400, %edi call malloc@PLT movq %rax, %r15 movl $2016, %edi call srand@PLT movq %r12, %rbx leaq 26214400(%r12), %rbp .L44: call rand@PLT pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 mulss .LC6(%rip), %xmm0 movss %xmm0, (%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L44 movq %r13, %rbx leaq 64(%r13), %rbp .L45: call rand@PLT pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 mulss .LC6(%rip), %xmm0 movss %xmm0, (%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L45 movq %rsp, %rdi movl $26214400, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $26214400, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $64, %esi call cudaMalloc@PLT movl $1, %ecx movl $26214400, %edx movq %r12, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $64, %edx movq %r13, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $160, 24(%rsp) movl $160, 28(%rsp) movl $1, 32(%rsp) movl $16, 36(%rsp) movl $16, 40(%rsp) movl $1, 44(%rsp) call cudaDeviceSynchronize@PLT leaq 48(%rsp), %rsi movl $0, %edi call clock_gettime@PLT movl 44(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 36(%rsp), %rdx movq 24(%rsp), %rdi movl 32(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L51 .L46: call cudaDeviceSynchronize@PLT leaq 64(%rsp), %rsi movl $0, %edi call clock_gettime@PLT movq 72(%rsp), %rax subq 56(%rsp), %rax pxor %xmm0, %xmm0 cvtsi2sdq %rax, %xmm0 divsd .LC7(%rip), %xmm0 movq 64(%rsp), %rax subq 48(%rsp), %rax pxor %xmm1, %xmm1 cvtsi2sdq %rax, %xmm1 addsd %xmm1, %xmm0 leaq .LC8(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl $2, %ecx movl $26214400, %edx movq 8(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT movl $2560, %r8d movq %r13, %rcx movq %r14, %rdx movq %r12, %rsi movq %r15, %rdi call _Z11checkresultPfS_S_S_i movq 88(%rsp), %rax subq %fs:40, %rax jne .L52 movl $0, %eax addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L51: .cfi_restore_state movl $2560, %ecx movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z28__device_stub__Z4normPfS_S_iPfS_S_i jmp .L46 .L52: call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.1 .LC9: .string "_Z4normPfS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC9(%rip), %rdx movq %rdx, %rcx leaq _Z4normPfS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC1: .long 0 .long -2147483648 .long 0 .long 0 .align 16 .LC2: .long 2147483647 .long 0 .long 0 .long 0 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC3: .long -1598689907 .long 1051772663 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC6: .long 805306368 .section .rodata.cst8 .align 8 .LC7: .long 0 .long 1104006501 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z4normPfS_S_i ; -- Begin function _Z4normPfS_S_i .globl _Z4normPfS_S_i .p2align 8 .type _Z4normPfS_S_i,@function _Z4normPfS_S_i: ; @_Z4normPfS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x2c s_load_b32 s33, s[0:1], 0x18 v_and_b32_e32 v3, 0x3ff, v0 s_add_u32 s2, s0, 32 s_addc_u32 s3, s1, 0 s_waitcnt lgkmcnt(0) s_and_b32 s24, s4, 0xffff s_mov_b32 s4, exec_lo v_mad_u64_u32 v[1:2], null, s14, s24, v[3:4] s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s33, v1 s_cbranch_execz .LBB0_15 ; %bb.1: s_ashr_i32 s4, s33, 31 s_load_b32 s2, s[2:3], 0xc s_add_i32 s5, s33, s4 v_bfe_u32 v0, v0, 10, 10 s_xor_b32 s5, s5, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cvt_f32_u32_e32 v2, s5 s_sub_i32 s6, 0, s5 v_rcp_iflag_f32_e32 v2, v2 s_waitcnt lgkmcnt(0) s_lshr_b32 s2, s2, 16 s_waitcnt_depctr 0xfff v_mul_f32_e32 v2, 0x4f7ffffe, v2 s_mul_i32 s2, s15, s2 s_mov_b32 s15, 16 v_add_nc_u32_e32 v0, s2, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v2, v2 v_readfirstlane_b32 s3, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s6, s6, s3 s_mul_hi_u32 s6, s3, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s3, s3, s6 s_mul_hi_u32 s3, s3, 0x640000 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_mul_i32 s6, s3, s5 s_add_i32 s7, s3, 1 s_sub_i32 s6, 0x640000, s6 s_sub_i32 s8, s6, s5 s_cmp_ge_u32 s6, s5 s_cselect_b32 s3, s7, s3 s_cselect_b32 s6, s8, s6 s_add_i32 s7, s3, 1 s_cmp_ge_u32 s6, s5 s_cselect_b32 s3, s7, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_xor_b32 s3, s3, s4 s_sub_i32 s3, s3, s4 s_delay_alu instid0(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s3, v0 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_15 ; %bb.2: s_clause 0x1 s_load_b64 s[16:17], s[0:1], 0x10 s_load_b64 s[12:13], s[0:1], 0x0 s_mul_i32 s3, s14, s33 v_mov_b32_e32 v5, 0 s_mul_i32 s3, s3, s24 s_waitcnt lgkmcnt(0) s_clause 0x1 s_load_b256 s[4:11], s[16:17], 0x0 s_load_b256 s[16:23], s[16:17], 0x20 s_add_i32 s2, s3, s2 s_set_inst_prefetch_distance 0x1 .p2align 6 .LBB0_3: ; =>This Inner Loop Header: Depth=1 s_ashr_i32 s3, s2, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[24:25], s[2:3], 2 s_add_u32 s34, s12, s24 s_addc_u32 s35, s13, s25 s_add_i32 s15, s15, -1 s_clause 0x1 s_load_b256 s[24:31], s[34:35], 0x0 s_load_b256 s[36:43], s[34:35], 0x20 s_add_i32 s2, s2, s33 s_cmp_eq_u32 s15, 0 s_waitcnt lgkmcnt(0) v_fmac_f32_e64 v5, s24, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e64 v5, s25, s5 v_fmac_f32_e64 v5, s26, s6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e64 v5, s27, s7 v_fmac_f32_e64 v5, s28, s8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e64 v5, s29, s9 v_fmac_f32_e64 v5, s30, s10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e64 v5, s31, s11 v_fmac_f32_e64 v5, s36, s16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e64 v5, s37, s17 v_fmac_f32_e64 v5, s38, s18 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e64 v5, s39, s19 v_fmac_f32_e64 v5, s40, s20 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e64 v5, s41, s21 v_fmac_f32_e64 v5, s42, s22 s_delay_alu instid0(VALU_DEP_1) v_fmac_f32_e64 v5, s43, s23 s_cbranch_scc0 .LBB0_3 ; %bb.4: s_set_inst_prefetch_distance 0x2 v_lshrrev_b32_e32 v2, 31, v1 v_and_b32_e32 v7, 1, v0 ; implicit-def: $vgpr6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, v1, v2 v_and_b32_e32 v2, -2, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v2, v1, v2 v_or_b32_e32 v3, v7, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_ne_u32_e32 vcc_lo, 0, v3 ; implicit-def: $vgpr3_vgpr4 s_and_saveexec_b32 s2, vcc_lo s_xor_b32 s4, exec_lo, s2 s_cbranch_execz .LBB0_12 ; %bb.5: v_cmp_ne_u32_e64 s2, 0, v7 v_cmp_ne_u32_e64 s3, 1, v2 v_cmp_eq_u32_e32 vcc_lo, 1, v2 ; implicit-def: $vgpr6 ; implicit-def: $vgpr3_vgpr4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s2, s3, s2 s_and_saveexec_b32 s3, s2 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s3, exec_lo, s3 s_cbranch_execz .LBB0_9 ; %bb.6: v_mad_u64_u32 v[3:4], null, v1, s33, v[0:1] v_and_b32_e32 v0, 0x80000001, v0 v_mov_b32_e32 v6, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_eq_u32_e64 s2, 1, v0 v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s5, vcc_lo, s2 s_and_saveexec_b32 s2, s5 s_cbranch_execz .LBB0_8 ; %bb.7: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[3:4] v_add_co_u32 v0, vcc_lo, s12, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo global_load_b32 v2, v[0:1], off v_cvt_f64_f32_e32 v[0:1], v5 s_waitcnt vmcnt(0) v_cvt_f64_f32_e64 v[6:7], -v2 v_div_scale_f64 v[8:9], null, v[0:1], v[0:1], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[10:11], v[8:9] s_waitcnt_depctr 0xfff v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0 v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0 v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] v_div_scale_f64 v[12:13], vcc_lo, v[6:7], v[0:1], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[14:15], v[12:13], v[10:11] v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15] v_div_fixup_f64 v[0:1], v[8:9], v[0:1], v[6:7] s_delay_alu instid0(VALU_DEP_1) v_cvt_f32_f64_e32 v6, v[0:1] .LBB0_8: ; %Flow s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $vgpr0 ; implicit-def: $vgpr1_vgpr2 .LBB0_9: ; %Flow139 s_and_not1_saveexec_b32 s2, s3 s_cbranch_execz .LBB0_11 ; %bb.10: v_mad_u64_u32 v[3:4], null, v1, s33, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[0:1], 2, v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s12, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo global_load_b32 v0, v[0:1], off s_waitcnt vmcnt(0) v_div_scale_f32 v1, null, v5, v5, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f32_e32 v2, v1 s_waitcnt_depctr 0xfff v_fma_f32 v6, -v1, v2, 1.0 v_fmac_f32_e32 v2, v6, v2 v_div_scale_f32 v6, vcc_lo, v0, v5, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v7, v6, v2 v_fma_f32 v8, -v1, v7, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v7, v8, v2 v_fma_f32 v1, -v1, v7, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f32 v1, v1, v2, v7 v_div_fixup_f32 v6, v1, v5, v0 .LBB0_11: ; %Flow140 s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $vgpr0 ; implicit-def: $vgpr1_vgpr2 .LBB0_12: ; %Flow141 s_and_not1_saveexec_b32 s2, s4 s_cbranch_execz .LBB0_14 ; %bb.13: v_mad_u64_u32 v[3:4], null, v1, s33, v[0:1] v_cvt_f64_f32_e32 v[5:6], v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[0:1], 2, v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s12, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo global_load_b32 v0, v[0:1], off s_waitcnt vmcnt(0) v_cvt_f64_f32_e32 v[0:1], v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[0:1], v[0:1], v[0:1] v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[9:10], v[7:8] s_waitcnt_depctr 0xfff v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10] v_div_scale_f64 v[11:12], vcc_lo, v[0:1], v[5:6], v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[13:14], v[11:12], v[9:10] v_fma_f64 v[7:8], -v[7:8], v[13:14], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[13:14] v_div_fixup_f64 v[0:1], v[7:8], v[5:6], v[0:1] s_delay_alu instid0(VALU_DEP_1) v_cvt_f32_f64_e32 v6, v[0:1] .LBB0_14: ; %.sink.split s_or_b32 exec_lo, exec_lo, s2 s_load_b64 s[0:1], s[0:1], 0x8 v_lshlrev_b64 v[0:1], 2, v[3:4] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v6, off .LBB0_15: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z4normPfS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 16 .amdhsa_next_free_sgpr 44 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z4normPfS_S_i, .Lfunc_end0-_Z4normPfS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1280 ; NumSgprs: 46 ; NumVgprs: 16 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 5 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 46 ; NumVGPRsForWavesPerEU: 16 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z4normPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 46 .sgpr_spill_count: 0 .symbol: _Z4normPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 16 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "0107933563b079f2d27773ec71b3934cea183122.hip" .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function _Z11checkresultPfS_S_S_i .LCPI0_0: .quad 0x8000000000000000 # double -0 .quad 0x8000000000000000 # double -0 .LCPI0_1: .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI0_2: .quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7 .text .globl _Z11checkresultPfS_S_S_i .p2align 4, 0x90 .type _Z11checkresultPfS_S_S_i,@function _Z11checkresultPfS_S_S_i: # @_Z11checkresultPfS_S_S_i .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdx, 8(%rsp) # 8-byte Spill movl %r8d, %eax shll $4, %eax movl %r8d, %r9d xorl %ebx, %ebx movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [-0.0E+0,-0.0E+0] xorl %r11d, %r11d jmp .LBB0_1 .p2align 4, 0x90 .LBB0_10: # in Loop: Header=BB0_1 Depth=1 incl %r11d movq 16(%rsp), %rbx # 8-byte Reload addq $16, %rbx cmpl $160, %r11d je .LBB0_11 .LBB0_1: # %.preheader101 # =>This Loop Header: Depth=1 # Child Loop BB0_2 Depth 2 # Child Loop BB0_3 Depth 3 # Child Loop BB0_4 Depth 4 # Child Loop BB0_7 Depth 3 # Child Loop BB0_8 Depth 4 movq %rbx, 16(%rsp) # 8-byte Spill xorl %r14d, %r14d jmp .LBB0_2 .p2align 4, 0x90 .LBB0_18: # in Loop: Header=BB0_2 Depth=2 incq %r14 addq %rax, %rbx cmpq $160, %r14 je .LBB0_10 .LBB0_2: # Parent Loop BB0_1 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB0_3 Depth 3 # Child Loop BB0_4 Depth 4 # Child Loop BB0_7 Depth 3 # Child Loop BB0_8 Depth 4 xorps %xmm1, %xmm1 xorl %r10d, %r10d movq %rbx, %r15 .p2align 4, 0x90 .LBB0_3: # %.preheader99 # Parent Loop BB0_1 Depth=1 # Parent Loop BB0_2 Depth=2 # => This Loop Header: Depth=3 # Child Loop BB0_4 Depth 4 xorl %edx, %edx .p2align 4, 0x90 .LBB0_4: # Parent Loop BB0_1 Depth=1 # Parent Loop BB0_2 Depth=2 # Parent Loop BB0_3 Depth=3 # => This Inner Loop Header: Depth=4 leal (%r15,%rdx), %ebp movslq %ebp, %r12 movss (%rsi,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero mulss (%rcx,%rdx,4), %xmm2 addss %xmm2, %xmm1 incq %rdx cmpq $16, %rdx jne .LBB0_4 # %bb.5: # in Loop: Header=BB0_3 Depth=3 incl %r10d addq %r9, %r15 cmpl $16, %r10d jne .LBB0_3 # %bb.6: # %.preheader100 # in Loop: Header=BB0_2 Depth=2 xorps %xmm2, %xmm2 cvtss2sd %xmm1, %xmm2 xorl %ebp, %ebp movl %ebx, %r15d jmp .LBB0_7 .p2align 4, 0x90 .LBB0_17: # in Loop: Header=BB0_7 Depth=3 incl %ebp incl %r15d cmpl $16, %ebp je .LBB0_18 .LBB0_7: # %.preheader98 # Parent Loop BB0_1 Depth=1 # Parent Loop BB0_2 Depth=2 # => This Loop Header: Depth=3 # Child Loop BB0_8 Depth 4 movl %ebp, %r12d andl $1, %r12d movl %r15d, %r13d xorl %r10d, %r10d jmp .LBB0_8 .p2align 4, 0x90 .LBB0_9: # in Loop: Header=BB0_8 Depth=4 movslq %r13d, %rdx movss (%rsi,%rdx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero cvtss2sd %xmm3, %xmm3 addsd %xmm3, %xmm3 .LBB0_24: # in Loop: Header=BB0_8 Depth=4 divsd %xmm2, %xmm3 cvtsd2ss %xmm3, %xmm3 .LBB0_26: # in Loop: Header=BB0_8 Depth=4 movss %xmm3, (%rdi,%rdx,4) incq %r10 addl %r8d, %r13d cmpq $16, %r10 je .LBB0_17 .LBB0_8: # Parent Loop BB0_1 Depth=1 # Parent Loop BB0_2 Depth=2 # Parent Loop BB0_7 Depth=3 # => This Inner Loop Header: Depth=4 movl %ebp, %edx orl %r10d, %edx testb $1, %dl je .LBB0_9 # %bb.19: # in Loop: Header=BB0_8 Depth=4 testb $1, %bpl jne .LBB0_22 # %bb.20: # in Loop: Header=BB0_8 Depth=4 movl %r10d, %edx andl $1, %edx je .LBB0_22 # %bb.21: # in Loop: Header=BB0_8 Depth=4 movslq %r13d, %rdx movss (%rsi,%rdx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero divss %xmm1, %xmm3 jmp .LBB0_26 .p2align 4, 0x90 .LBB0_22: # in Loop: Header=BB0_8 Depth=4 movslq %r13d, %rdx testl %r10d, %r12d je .LBB0_25 # %bb.23: # in Loop: Header=BB0_8 Depth=4 movss (%rsi,%rdx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero cvtss2sd %xmm3, %xmm3 xorps %xmm0, %xmm3 jmp .LBB0_24 .LBB0_25: # in Loop: Header=BB0_8 Depth=4 xorps %xmm3, %xmm3 jmp .LBB0_26 .LBB0_11: # %.preheader.preheader movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero movq 8(%rsp), %rax # 8-byte Reload movss (%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero movaps %xmm0, %xmm2 subss %xmm1, %xmm2 andps .LCPI0_1(%rip), %xmm2 cvtss2sd %xmm2, %xmm2 ucomisd .LCPI0_2(%rip), %xmm2 jbe .LBB0_12 # %bb.27: # %.critedge151 cvtss2sd %xmm0, %xmm0 cvtss2sd %xmm1, %xmm1 movl $.L.str, %edi xorl %esi, %esi movb $2, %al addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 jmp printf # TAILCALL .LBB0_12: # %.lr.ph.preheader .cfi_def_cfa_offset 80 xorl %esi, %esi movaps .LCPI0_1(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN] movsd .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero .p2align 4, 0x90 .LBB0_13: # %.lr.ph # =>This Inner Loop Header: Depth=1 cmpq $6553599, %rsi # imm = 0x63FFFF je .LBB0_16 # %bb.14: # %.preheader # in Loop: Header=BB0_13 Depth=1 movss 4(%rdi,%rsi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero movss 4(%rax,%rsi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero movaps %xmm2, %xmm4 subss %xmm3, %xmm4 andps %xmm0, %xmm4 cvtss2sd %xmm4, %xmm4 incq %rsi ucomisd %xmm1, %xmm4 jbe .LBB0_13 # %bb.15: # %.preheader._crit_edge leaq -1(%rsi), %rbx xorps %xmm0, %xmm0 cvtss2sd %xmm2, %xmm0 xorps %xmm1, %xmm1 cvtss2sd %xmm3, %xmm1 movl $.L.str, %edi # kill: def $esi killed $esi killed $rsi movb $2, %al callq printf cmpq $6553598, %rbx # imm = 0x63FFFE jbe .LBB0_28 .LBB0_16: # %.critedge movl $.Lstr, %edi addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 jmp puts@PLT # TAILCALL .LBB0_28: .cfi_def_cfa_offset 80 addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z11checkresultPfS_S_S_i, .Lfunc_end0-_Z11checkresultPfS_S_S_i .cfi_endproc # -- End function .globl _Z19__device_stub__normPfS_S_i # -- Begin function _Z19__device_stub__normPfS_S_i .p2align 4, 0x90 .type _Z19__device_stub__normPfS_S_i,@function _Z19__device_stub__normPfS_S_i: # @_Z19__device_stub__normPfS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z4normPfS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end1: .size _Z19__device_stub__normPfS_S_i, .Lfunc_end1-_Z19__device_stub__normPfS_S_i .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI2_0: .long 0x30000000 # float 4.65661287E-10 .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI2_1: .quad 0x41cdcd6500000000 # double 1.0E+9 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $160, %rsp .cfi_def_cfa_offset 208 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $26214400, %edi # imm = 0x1900000 callq malloc movq %rax, %rbx movl $26214400, %edi # imm = 0x1900000 callq malloc movq %rax, %r14 movl $64, %edi callq malloc movq %rax, %r15 movl $26214400, %edi # imm = 0x1900000 callq malloc movq %rax, %r12 movl $2016, %edi # imm = 0x7E0 callq srand xorl %r13d, %r13d .p2align 4, 0x90 .LBB2_1: # =>This Inner Loop Header: Depth=1 callq rand movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss %xmm1, %xmm0 movss %xmm0, (%rbx,%r13,4) incq %r13 cmpq $6553600, %r13 # imm = 0x640000 jne .LBB2_1 # %bb.2: # %.preheader.preheader xorl %r13d, %r13d .p2align 4, 0x90 .LBB2_3: # %.preheader # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI2_0(%rip), %xmm0 movss %xmm0, (%r15,%r13,4) incq %r13 cmpq $16, %r13 jne .LBB2_3 # %bb.4: leaq 24(%rsp), %rdi movl $26214400, %esi # imm = 0x1900000 callq hipMalloc leaq 16(%rsp), %rdi movl $26214400, %esi # imm = 0x1900000 callq hipMalloc leaq 8(%rsp), %rdi movl $64, %esi callq hipMalloc movq 24(%rsp), %rdi movl $26214400, %edx # imm = 0x1900000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi movl $64, %edx movq %r15, %rsi movl $1, %ecx callq hipMemcpy callq hipDeviceSynchronize leaq 144(%rsp), %rsi xorl %edi, %edi callq clock_gettime movabsq $687194767520, %rdi # imm = 0xA0000000A0 movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_6 # %bb.5: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 136(%rsp) movq %rcx, 128(%rsp) movq %rdx, 120(%rsp) movl $2560, 4(%rsp) # imm = 0xA00 leaq 136(%rsp), %rax movq %rax, 32(%rsp) leaq 128(%rsp), %rax movq %rax, 40(%rsp) leaq 120(%rsp), %rax movq %rax, 48(%rsp) leaq 4(%rsp), %rax movq %rax, 56(%rsp) leaq 104(%rsp), %rdi leaq 88(%rsp), %rsi leaq 80(%rsp), %rdx leaq 72(%rsp), %rcx callq __hipPopCallConfiguration movq 104(%rsp), %rsi movl 112(%rsp), %edx movq 88(%rsp), %rcx movl 96(%rsp), %r8d leaq 32(%rsp), %r9 movl $_Z4normPfS_S_i, %edi pushq 72(%rsp) .cfi_adjust_cfa_offset 8 pushq 88(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_6: callq hipDeviceSynchronize leaq 32(%rsp), %rsi xorl %edi, %edi callq clock_gettime movq 32(%rsp), %rax movq 40(%rsp), %rcx subq 144(%rsp), %rax xorps %xmm1, %xmm1 cvtsi2sd %rax, %xmm1 subq 152(%rsp), %rcx xorps %xmm0, %xmm0 cvtsi2sd %rcx, %xmm0 divsd .LCPI2_1(%rip), %xmm0 addsd %xmm1, %xmm0 movl $.L.str.2, %edi movb $1, %al callq printf movq 16(%rsp), %rsi movl $26214400, %edx # imm = 0x1900000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy movq %r12, %rdi movq %rbx, %rsi movq %r14, %rdx movq %r15, %rcx movl $2560, %r8d # imm = 0xA00 callq _Z11checkresultPfS_S_S_i xorl %eax, %eax addq $160, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z4normPfS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "results checking failed at %d ref %f out %f\n" .size .L.str, 45 .type _Z4normPfS_S_i,@object # @_Z4normPfS_S_i .section .rodata,"a",@progbits .globl _Z4normPfS_S_i .p2align 3, 0x0 _Z4normPfS_S_i: .quad _Z19__device_stub__normPfS_S_i .size _Z4normPfS_S_i, 8 .type .L.str.2,@object # @.str.2 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.2: .asciz "kernel time %fs\n" .size .L.str.2, 17 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z4normPfS_S_i" .size .L__unnamed_1, 15 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "results checking passed!" .size .Lstr, 25 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z19__device_stub__normPfS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z4normPfS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80
.file "tmpxft_000ba9b2_00000000-6_a5223ace1a0755c50f678765967caf54542f3449.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2064: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2064: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata._Z12isCapableP2Pi.str1.1,"aMS",@progbits,1 .LC0: .string "not" .LC1: .string "is" .section .rodata._Z12isCapableP2Pi.str1.8,"aMS",@progbits,1 .align 8 .LC2: .string "> GPU%d: %s %s capable of Peer-to-Peer access\n" .align 8 .LC3: .string "> no enough device to run this application\n" .section .text._Z12isCapableP2Pi,"axG",@progbits,_Z12isCapableP2Pi,comdat .weak _Z12isCapableP2Pi .type _Z12isCapableP2Pi, @function _Z12isCapableP2Pi: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $8, %rsp .cfi_def_cfa_offset 64 movl %edi, %r13d movslq %edi, %rax movq %rax, %rdi salq $7, %rdi addq %rax, %rdi salq $3, %rdi call malloc@PLT testl %r13d, %r13d jle .L8 movq %rax, %rbx movl $0, %ebp movl $0, %r14d leaq .LC2(%rip), %r15 jmp .L6 .L12: addl $1, %r14d leaq .LC1(%rip), %r8 .L5: movq %r12, %rcx movl %ebp, %edx movq %r15, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addl $1, %ebp addq $1032, %rbx cmpl %ebp, %r13d je .L4 .L6: movq %rbx, %r12 movl %ebp, %esi movq %rbx, %rdi call cudaGetDeviceProperties_v2@PLT leaq .LC0(%rip), %r8 cmpl $1, 360(%rbx) jg .L12 jmp .L5 .L8: movl $0, %r14d .L4: cmpl %r14d, %r13d jne .L13 .L7: cmpl %r14d, %r13d sete %al addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L13: .cfi_restore_state leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L7 .cfi_endproc .LFE2057: .size _Z12isCapableP2Pi, .-_Z12isCapableP2Pi .section .rodata._Z9enableP2Pi.str1.8,"aMS",@progbits,1 .align 8 .LC4: .string "> GPU%d enabled direct access to GPU%d\n" .section .rodata._Z9enableP2Pi.str1.1,"aMS",@progbits,1 .LC5: .string "(%d, %d)\n" .section .text._Z9enableP2Pi,"axG",@progbits,_Z9enableP2Pi,comdat .weak _Z9enableP2Pi .type _Z9enableP2Pi, @function _Z9enableP2Pi: .LFB2058: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $24, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax testl %edi, %edi jle .L14 movl %edi, %r13d movl $0, %ebp movl $0, %r12d leaq .LC5(%rip), %r15 jmp .L20 .L17: movl %ebx, %ecx movl %ebp, %edx movq %r15, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L16: leal 1(%rbx), %eax cmpl %eax, %r13d je .L25 movl %eax, %ebx .L19: cmpl %ebx, %ebp je .L16 movl %r12d, 4(%rsp) movl %ebx, %edx movl %ebp, %esi movq %r14, %rdi call cudaDeviceCanAccessPeer@PLT cmpl $0, 4(%rsp) je .L17 movl %r12d, %esi movl %ebx, %edi call cudaDeviceEnablePeerAccess@PLT movl %ebx, %ecx movl %ebp, %edx leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L16 .L25: leal 1(%rbp), %eax cmpl %ebx, %ebp je .L14 movl %eax, %ebp .L20: movl %ebp, %edi call cudaSetDevice@PLT movl %r12d, %ebx leaq 4(%rsp), %r14 jmp .L19 .L14: movq 8(%rsp), %rax subq %fs:40, %rax jne .L26 addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L26: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size _Z9enableP2Pi, .-_Z9enableP2Pi .section .rodata._Z10disableP2Pi.str1.8,"aMS",@progbits,1 .align 8 .LC6: .string "> GPU%d disabled direct access to GPU%d\n" .section .text._Z10disableP2Pi,"axG",@progbits,_Z10disableP2Pi,comdat .weak _Z10disableP2Pi .type _Z10disableP2Pi, @function _Z10disableP2Pi: .LFB2059: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $24, %rsp .cfi_def_cfa_offset 64 movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax testl %edi, %edi jle .L27 movl %edi, %r12d movl $0, %ebp leaq .LC6(%rip), %r13 jmp .L32 .L29: leal 1(%rbx), %eax cmpl %eax, %r12d je .L37 movl %eax, %ebx .L31: cmpl %ebx, %ebp je .L29 movl $0, 4(%rsp) leaq 4(%rsp), %rdi movl %ebx, %edx movl %ebp, %esi call cudaDeviceCanAccessPeer@PLT cmpl $0, 4(%rsp) je .L29 movl %ebx, %edi call cudaDeviceDisablePeerAccess@PLT movl %ebx, %ecx movl %ebp, %edx movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L29 .L37: leal 1(%rbp), %eax cmpl %ebx, %ebp je .L27 movl %eax, %ebp .L32: movl %ebp, %edi call cudaSetDevice@PLT movl $0, %ebx jmp .L31 .L27: movq 8(%rsp), %rax subq %fs:40, %rax jne .L38 addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L38: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size _Z10disableP2Pi, .-_Z10disableP2Pi .text .globl _Z11initialDataPfi .type _Z11initialDataPfi, @function _Z11initialDataPfi: .LFB2060: .cfi_startproc endbr64 testl %esi, %esi jle .L44 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movslq %esi, %rsi leaq (%rdi,%rsi,4), %rbp .L41: call rand@PLT pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 mulss .LC7(%rip), %xmm0 movss %xmm0, (%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L41 addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L44: .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE2060: .size _Z11initialDataPfi, .-_Z11initialDataPfi .section .rodata.str1.1,"aMS",@progbits,1 .LC8: .string "ngpus %d \n" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC9: .string "\nAllocating buffers (%iMB on each GPU and CPU Host)...\n" .align 8 .LC12: .string "GPU%d->GPU%d: performance: %8.2f GB/s\n" .text .globl main .type main, @function main: .LFB2061: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $72, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movq 8(%rsi), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %rbx movl $3, %edi call _Z12isCapableP2Pi movl $3, %edx leaq .LC8(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $3, %edi call _Z9enableP2Pi sall $20, %ebx movslq %ebx, %rbx salq $2, %rbx movq %rbx, %rdx shrq $20, %rdx leaq .LC9(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $12, %edi call malloc@PLT movq %rax, %rbp movl $12, %edi call malloc@PLT movq %rax, %r14 movq %rax, 16(%rsp) movl $12, %edi call malloc@PLT movq %rax, %r13 movl $24, %edi call malloc@PLT movq %rax, %r12 movq %rax, 24(%rsp) movl $0, %edi call cudaSetDevice@PLT leaq 40(%rsp), %rdi call cudaEventCreate@PLT leaq 48(%rsp), %rdi call cudaEventCreate@PLT movq %rbp, %r15 movq %r12, 8(%rsp) movl $0, %r12d .L48: movl %r12d, %edi call cudaSetDevice@PLT movq %rbx, %rsi movq %r15, %rdi call cudaMalloc@PLT movq %rbx, %rsi movq %r14, %rdi call cudaMalloc@PLT movq %rbx, %rsi movq %r13, %rdi call cudaMallocHost@PLT movq 8(%rsp), %rdi call cudaStreamCreate@PLT addl $1, %r12d addq $8, %r15 addq $8, %r14 addq $8, %r13 addq $8, 8(%rsp) cmpl $3, %r12d jne .L48 movl $0, %edi call cudaSetDevice@PLT movl $0, %esi movq 40(%rsp), %rdi call cudaEventRecord@PLT movl $0, %r13d leaq 36(%rsp), %r15 leaq .LC12(%rip), %r14 jmp .L49 .L50: movq %rbx, %rax shrq %rax pxor %xmm0, %xmm0 cvtsi2ssq %rax, %xmm0 addss %xmm0, %xmm0 .L51: mulss .LC11(%rip), %xmm1 divss %xmm1, %xmm0 cvtss2sd %xmm0, %xmm0 movl %r12d, %ecx movl 8(%rsp), %edx movq %r14, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $1, %r12 cmpq $3, %r12 je .L60 .L52: movl $0, %esi movq 40(%rsp), %rdi call cudaEventRecord@PLT movq 0(%rbp,%r12,8), %rsi movq 0(%rbp,%r13,8), %rdi movl $3, %ecx movq %rbx, %rdx call cudaMemcpy@PLT movl $0, %esi movq 48(%rsp), %rdi call cudaEventRecord@PLT movq 48(%rsp), %rdi call cudaEventSynchronize@PLT movq 48(%rsp), %rdx movq 40(%rsp), %rsi movq %r15, %rdi call cudaEventElapsedTime@PLT movss 36(%rsp), %xmm1 divss .LC10(%rip), %xmm1 movss %xmm1, 36(%rsp) testq %rbx, %rbx js .L50 pxor %xmm0, %xmm0 cvtsi2ssq %rbx, %xmm0 jmp .L51 .L60: addq $1, %r13 cmpq $3, %r13 je .L53 .L49: movl %r13d, 8(%rsp) movl $0, %r12d jmp .L52 .L53: movl $0, %edi call cudaSetDevice@PLT movl $3, %edi call _Z10disableP2Pi movl $0, %edi call cudaSetDevice@PLT movl $0, %ebx .L54: movl %ebx, %edi call cudaSetDevice@PLT movq 0(%rbp,%rbx,8), %rdi call cudaFree@PLT movq 16(%rsp), %rax movq (%rax,%rbx,8), %rdi call cudaFree@PLT movq 24(%rsp), %rax movq (%rax,%rbx,8), %rdi call cudaStreamDestroy@PLT addq $1, %rbx cmpq $3, %rbx jne .L54 movl $0, %edi call exit@PLT .cfi_endproc .LFE2061: .size main, .-main .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC7: .long 805306368 .align 4 .LC10: .long 1120403456 .align 4 .LC11: .long 1232348160 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "a5223ace1a0755c50f678765967caf54542f3449.hip" .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function _Z11initialDataPfi .LCPI0_0: .long 0x30000000 # float 4.65661287E-10 .text .globl _Z11initialDataPfi .p2align 4, 0x90 .type _Z11initialDataPfi,@function _Z11initialDataPfi: # @_Z11initialDataPfi .cfi_startproc # %bb.0: testl %esi, %esi jle .LBB0_4 # %bb.1: # %.lr.ph.preheader pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx movl %esi, %r14d xorl %r15d, %r15d .p2align 4, 0x90 .LBB0_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI0_0(%rip), %xmm0 movss %xmm0, (%rbx,%r15,4) incq %r15 cmpq %r15, %r14 jne .LBB0_2 # %bb.3: popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 .cfi_restore %rbx .cfi_restore %r14 .cfi_restore %r15 .LBB0_4: # %._crit_edge retq .Lfunc_end0: .size _Z11initialDataPfi, .Lfunc_end0-_Z11initialDataPfi .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI1_0: .long 0x42c80000 # float 100 .LCPI1_1: .long 0x49742400 # float 1.0E+6 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $72, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq 8(%rsi), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %rbx movl $4416, %edi # imm = 0x1140 callq malloc movq %rax, %r14 movl $.L.str.4, %r12d xorl %r15d, %r15d xorl %ebp, %ebp .p2align 4, 0x90 .LBB1_1: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 movq %r14, %rdi movl %r15d, %esi callq hipGetDevicePropertiesR0600 xorl %eax, %eax cmpl $2, 360(%r14) setge %al movl $.L.str.5, %ecx cmovgeq %r12, %rcx addl %eax, %ebp movl $.L.str.3, %edi movl %r15d, %esi movq %r14, %rdx xorl %eax, %eax callq printf incq %r15 addq $1472, %r14 # imm = 0x5C0 cmpq $3, %r15 jne .LBB1_1 # %bb.2: # %._crit_edge.i cmpl $3, %ebp je .LBB1_4 # %bb.3: movl $.Lstr, %edi callq puts@PLT .LBB1_4: # %_Z12isCapableP2Pi.exit movl $.L.str, %edi movl $3, %esi xorl %eax, %eax callq printf leaq 8(%rsp), %r14 xorl %ebp, %ebp jmp .LBB1_5 .p2align 4, 0x90 .LBB1_12: # %._crit_edge.i57 # in Loop: Header=BB1_5 Depth=1 incl %ebp cmpl $3, %ebp je .LBB1_13 .LBB1_5: # %.lr.ph22.i # =>This Loop Header: Depth=1 # Child Loop BB1_6 Depth 2 movl %ebp, %edi callq hipSetDevice xorl %r15d, %r15d jmp .LBB1_6 .p2align 4, 0x90 .LBB1_9: # in Loop: Header=BB1_6 Depth=2 movl %r15d, %edi xorl %esi, %esi callq hipDeviceEnablePeerAccess movl $.L.str.7, %edi .LBB1_10: # in Loop: Header=BB1_6 Depth=2 movl %ebp, %esi movl %r15d, %edx xorl %eax, %eax callq printf .LBB1_11: # in Loop: Header=BB1_6 Depth=2 incl %r15d cmpl $3, %r15d je .LBB1_12 .LBB1_6: # %.lr.ph.i54 # Parent Loop BB1_5 Depth=1 # => This Inner Loop Header: Depth=2 cmpl %r15d, %ebp je .LBB1_11 # %bb.7: # in Loop: Header=BB1_6 Depth=2 movl $0, 8(%rsp) movq %r14, %rdi movl %ebp, %esi movl %r15d, %edx callq hipDeviceCanAccessPeer cmpl $0, 8(%rsp) jne .LBB1_9 # %bb.8: # in Loop: Header=BB1_6 Depth=2 movl $.L.str.8, %edi jmp .LBB1_10 .LBB1_13: # %_Z9enableP2Pi.exit shll $20, %ebx movslq %ebx, %rsi leaq (,%rsi,4), %r12 shrq $18, %rsi xorl %eax, %eax movq %rax, 16(%rsp) # 8-byte Spill movl $.L.str.1, %edi # kill: def $esi killed $esi killed $rsi xorl %eax, %eax callq printf movl $12, %edi callq malloc movq %rax, %rbx movl $12, %edi callq malloc movq %rax, %r15 movl $12, %edi callq malloc movq %rax, 40(%rsp) # 8-byte Spill movl $24, %edi callq malloc movq %rax, %r13 xorl %edi, %edi callq hipSetDevice leaq 8(%rsp), %rdi callq hipEventCreate leaq 32(%rsp), %rdi callq hipEventCreate movq %rbx, %r14 movq %r15, 56(%rsp) # 8-byte Spill movq %r13, 48(%rsp) # 8-byte Spill .p2align 4, 0x90 .LBB1_14: # =>This Inner Loop Header: Depth=1 movq %r14, 64(%rsp) # 8-byte Spill movq 16(%rsp), %rbp # 8-byte Reload movl %ebp, %edi callq hipSetDevice movq %r14, %rdi movq %r12, %rsi callq hipMalloc movq %r15, %rdi movq %r12, %rsi callq hipMalloc movq 40(%rsp), %r14 # 8-byte Reload movq %r14, %rdi movq %r12, %rsi xorl %edx, %edx callq hipHostMalloc movq %r13, %rdi callq hipStreamCreate incq %rbp addq $8, %r13 addq $8, %r14 movq %r14, 40(%rsp) # 8-byte Spill movq 64(%rsp), %r14 # 8-byte Reload addq $8, %r15 addq $8, %r14 movq %rbp, %rax movq %rbp, 16(%rsp) # 8-byte Spill cmpq $3, %rbp jne .LBB1_14 # %bb.15: xorl %r13d, %r13d xorl %edi, %edi callq hipSetDevice movq 8(%rsp), %rdi xorl %esi, %esi callq hipEventRecord testq %r12, %r12 js .LBB1_16 # %bb.17: cvtsi2ss %r12, %xmm0 jmp .LBB1_18 .LBB1_16: movq %r12, %rax shrq %rax movl %r12d, %ecx andl $1, %ecx orq %rax, %rcx cvtsi2ss %rcx, %xmm0 addss %xmm0, %xmm0 .LBB1_18: movss %xmm0, 16(%rsp) # 4-byte Spill leaq 24(%rsp), %rbp .p2align 4, 0x90 .LBB1_19: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_20 Depth 2 xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_20: # Parent Loop BB1_19 Depth=1 # => This Inner Loop Header: Depth=2 movq 8(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq (%rbx,%r13,8), %rdi movq (%rbx,%r14,8), %rsi movq %r12, %rdx movl $3, %ecx callq hipMemcpy movq 32(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 32(%rsp), %rdi callq hipEventSynchronize movq 8(%rsp), %rsi movq 32(%rsp), %rdx movq %rbp, %rdi callq hipEventElapsedTime movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero divss .LCPI1_0(%rip), %xmm0 movss %xmm0, 24(%rsp) mulss .LCPI1_1(%rip), %xmm0 movss 16(%rsp), %xmm1 # 4-byte Reload # xmm1 = mem[0],zero,zero,zero divss %xmm0, %xmm1 xorps %xmm0, %xmm0 cvtss2sd %xmm1, %xmm0 movl $.L.str.2, %edi movl %r13d, %esi movl %r14d, %edx movb $1, %al callq printf incq %r14 cmpq $3, %r14 jne .LBB1_20 # %bb.21: # in Loop: Header=BB1_19 Depth=1 incq %r13 cmpq $3, %r13 jne .LBB1_19 # %bb.22: xorl %edi, %edi callq hipSetDevice leaq 28(%rsp), %r14 xorl %ebp, %ebp movq 48(%rsp), %r12 # 8-byte Reload jmp .LBB1_23 .p2align 4, 0x90 .LBB1_28: # %._crit_edge.i61 # in Loop: Header=BB1_23 Depth=1 incl %ebp cmpl $3, %ebp je .LBB1_29 .LBB1_23: # %.lr.ph20.i # =>This Loop Header: Depth=1 # Child Loop BB1_24 Depth 2 movl %ebp, %edi callq hipSetDevice xorl %r15d, %r15d jmp .LBB1_24 .p2align 4, 0x90 .LBB1_27: # in Loop: Header=BB1_24 Depth=2 incl %r15d cmpl $3, %r15d je .LBB1_28 .LBB1_24: # %.lr.ph.i58 # Parent Loop BB1_23 Depth=1 # => This Inner Loop Header: Depth=2 cmpl %r15d, %ebp je .LBB1_27 # %bb.25: # in Loop: Header=BB1_24 Depth=2 movl $0, 28(%rsp) movq %r14, %rdi movl %ebp, %esi movl %r15d, %edx callq hipDeviceCanAccessPeer cmpl $0, 28(%rsp) je .LBB1_27 # %bb.26: # in Loop: Header=BB1_24 Depth=2 movl %r15d, %edi callq hipDeviceDisablePeerAccess movl $.L.str.9, %edi movl %ebp, %esi movl %r15d, %edx xorl %eax, %eax callq printf jmp .LBB1_27 .LBB1_29: # %_Z10disableP2Pi.exit xorl %r14d, %r14d xorl %edi, %edi callq hipSetDevice movq 56(%rsp), %r15 # 8-byte Reload .p2align 4, 0x90 .LBB1_30: # =>This Inner Loop Header: Depth=1 movl %r14d, %edi callq hipSetDevice movq (%rbx,%r14,8), %rdi callq hipFree movq (%r15,%r14,8), %rdi callq hipFree movq (%r12,%r14,8), %rdi callq hipStreamDestroy incq %r14 cmpq $3, %r14 jne .LBB1_30 # %bb.31: xorl %edi, %edi callq exit .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "ngpus %d \n" .size .L.str, 11 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "\nAllocating buffers (%iMB on each GPU and CPU Host)...\n" .size .L.str.1, 56 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "GPU%d->GPU%d: performance: %8.2f GB/s\n" .size .L.str.2, 39 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "> GPU%d: %s %s capable of Peer-to-Peer access\n" .size .L.str.3, 47 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "is" .size .L.str.4, 3 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "not" .size .L.str.5, 4 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "> GPU%d enabled direct access to GPU%d\n" .size .L.str.7, 40 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "(%d, %d)\n" .size .L.str.8, 10 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "> GPU%d disabled direct access to GPU%d\n" .size .L.str.9, 41 .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "> no enough device to run this application" .size .Lstr, 43 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
8
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code for sm_80 Function : _Z3addPiS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; MOV R5, c[0x0][0x16c] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; MOV R3, c[0x0][0x164] ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E R5, [R4.64] ; LDG.E R2, [R2.64] ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; MOV R7, c[0x0][0x174] ; IADD3 R9, R2, R5, RZ ; STG.E [R6.64], R9 ; EXIT ; BRA 0xd0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000ebc5a_00000000-6_50d9957b066db64a92d690de95c07e6beea9f64e.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z26__device_stub__Z3addPiS_S_PiS_S_ .type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function _Z26__device_stub__Z3addPiS_S_PiS_S_: .LFB3694: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z3addPiS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_ .globl _Z3addPiS_S_ .type _Z3addPiS_S_, @function _Z3addPiS_S_: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z3addPiS_S_PiS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z3addPiS_S_, .-_Z3addPiS_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string " " .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 subq $64, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leaq 8(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT movl $5, (%rsp) movl $10, 4(%rsp) movq %rsp, %rsi movl $1, %ecx movl $4, %edx movq 8(%rsp), %rdi call cudaMemcpy@PLT leaq 4(%rsp), %rsi movl $1, %ecx movl $4, %edx movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L15 .L12: leaq 44(%rsp), %rdi movl $2, %ecx movl $4, %edx movq 24(%rsp), %rsi call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movl (%rsp), %esi leaq _ZSt4cout(%rip), %rdi call _ZNSolsEi@PLT movq %rax, %rdi leaq .LC0(%rip), %rbx movq %rbx, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl 4(%rsp), %esi call _ZNSolsEi@PLT movq %rax, %rdi movq %rbx, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl 44(%rsp), %esi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L16 movl $0, %eax addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z26__device_stub__Z3addPiS_S_PiS_S_ jmp .L12 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1 .LC1: .string "_Z3addPiS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z3addPiS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z3addPiS_S_ ; -- Begin function _Z3addPiS_S_ .globl _Z3addPiS_S_ .p2align 8 .type _Z3addPiS_S_,@function _Z3addPiS_S_: ; @_Z3addPiS_S_ ; %bb.0: s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_load_b32 s2, s[4:5], 0x0 s_load_b32 s3, s[6:7], 0x0 s_waitcnt lgkmcnt(0) s_add_i32 s2, s3, s2 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z3addPiS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 8 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 80 ; NumSgprs: 8 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 8 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z3addPiS_S_ .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z3addPiS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "50d9957b066db64a92d690de95c07e6beea9f64e.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_ .p2align 4, 0x90 .type _Z18__device_stub__addPiS_S_,@function _Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3addPiS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $136, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 leaq 24(%rsp), %rdi movl $4, %esi callq hipMalloc leaq 16(%rsp), %rdi movl $4, %esi callq hipMalloc leaq 8(%rsp), %rdi movl $4, %esi callq hipMalloc movl $5, 4(%rsp) movl $10, (%rsp) movq 24(%rsp), %rdi leaq 4(%rsp), %rsi movl $4, %edx movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi movq %rsp, %rsi movl $4, %edx movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 128(%rsp) movq %rcx, 120(%rsp) movq %rdx, 112(%rsp) leaq 128(%rsp), %rax movq %rax, 32(%rsp) leaq 120(%rsp), %rax movq %rax, 40(%rsp) leaq 112(%rsp), %rax movq %rax, 48(%rsp) leaq 96(%rsp), %rdi leaq 80(%rsp), %rsi leaq 72(%rsp), %rdx leaq 64(%rsp), %rcx callq __hipPopCallConfiguration movq 96(%rsp), %rsi movl 104(%rsp), %edx movq 80(%rsp), %rcx movl 88(%rsp), %r8d leaq 32(%rsp), %r9 movl $_Z3addPiS_S_, %edi pushq 64(%rsp) .cfi_adjust_cfa_offset 8 pushq 80(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq 8(%rsp), %rsi leaq 32(%rsp), %rdi movl $4, %edx movl $2, %ecx callq hipMemcpy movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movl 4(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq %rax, %rbx movl $.L.str, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl (%rsp), %esi movq %rbx, %rdi callq _ZNSolsEi movq %rax, %rbx movl $.L.str, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 32(%rsp), %esi movq %rbx, %rdi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB1_7 # %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB1_5 # %bb.4: movzbl 67(%rbx), %ecx jmp .LBB1_6 .LBB1_5: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %eax, %eax addq $136, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB1_7: .cfi_def_cfa_offset 160 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3addPiS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z3addPiS_S_,@object # @_Z3addPiS_S_ .section .rodata,"a",@progbits .globl _Z3addPiS_S_ .p2align 3, 0x0 _Z3addPiS_S_: .quad _Z18__device_stub__addPiS_S_ .size _Z3addPiS_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz " " .size .L.str, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z3addPiS_S_" .size .L__unnamed_1, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__addPiS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3addPiS_S_ .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
435
2,905
1,778
3,434
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code for sm_80 Function : _Z12mandelKernelPiffffiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT ; ULDC.64 UR4, c[0x0][0x118] ; S2R R3, SR_TID.X ; S2R R2, SR_CTAID.Y ; S2R R5, SR_TID.Y ; IMAD R0, R0, c[0x0][0x0], R3 ; SHF.L.U32 R0, R0, 0x3, RZ ; IMAD R2, R2, c[0x0][0x4], R5 ; IADD3 R5, R0, 0x7, RZ ; IMAD.SHL.U32 R3, R2, 0x8, RZ ; IADD3 R7, R3, 0x1, RZ ; @P0 BRA 0x400 ; IADD3 R35, R3.reuse, 0x7, RZ ; IMAD R9, R2, c[0x0][0x178], RZ ; IADD3 R33, R3, 0x6, RZ ; IMAD R25, R7, c[0x0][0x178], R0.reuse ; IADD3 R31, R3, 0x5, RZ ; IMAD R2, R9, 0x8, R0.reuse ; IADD3 R29, R3, 0x4, RZ ; IMAD R4, R35, c[0x0][0x178], R0.reuse ; IADD3 R27, R3, 0x3, RZ ; IMAD R6, R33, c[0x0][0x178], R0.reuse ; IADD3 R37, R3, 0x2, RZ ; IMAD R24, R31, c[0x0][0x178], R0.reuse ; IADD3 R30, R0, -0x1, RZ ; IMAD R26, R29, c[0x0][0x178], R0.reuse ; MOV R8, c[0x0][0x160] ; IMAD R28, R27, c[0x0][0x178], R0.reuse ; MOV R21, c[0x0][0x164] ; IMAD R0, R37, c[0x0][0x178], R0 ; IADD3 R30, R30, 0x1, RZ ; MOV R9, R21 ; ISETP.GE.AND P0, PT, R30, c[0x0][0x178], PT ; ISETP.GE.OR P1, PT, R3, c[0x0][0x17c], P0 ; ISETP.GE.OR P6, PT, R7, c[0x0][0x17c], P0 ; ISETP.GE.OR P5, PT, R37, c[0x0][0x17c], P0 ; ISETP.GE.OR P4, PT, R27, c[0x0][0x17c], P0 ; ISETP.GE.OR P3, PT, R29, c[0x0][0x17c], P0 ; ISETP.GE.OR P2, PT, R31, c[0x0][0x17c], P0 ; @!P1 IMAD.WIDE R12, R2, 0x4, R8 ; @!P6 IMAD.WIDE R20, R25, 0x4, R8.reuse ; @!P1 STG.E [R12.64], RZ ; ISETP.GE.OR P1, PT, R33, c[0x0][0x17c], P0 ; @!P5 IMAD.WIDE R22, R0, 0x4, R8.reuse ; ISETP.GE.OR P0, PT, R35, c[0x0][0x17c], P0 ; @!P6 STG.E [R20.64], RZ ; @!P4 IMAD.WIDE R10, R28, 0x4, R8.reuse ; @!P5 STG.E [R22.64], RZ ; @!P3 IMAD.WIDE R12, R26, 0x4, R8 ; @!P4 STG.E [R10.64], RZ ; @!P2 IMAD.WIDE R14, R24, 0x4, R8.reuse ; @!P3 STG.E [R12.64], RZ ; @!P1 IMAD.WIDE R16, R6, 0x4, R8.reuse ; @!P2 STG.E [R14.64], RZ ; @!P0 IMAD.WIDE R18, R4, 0x4, R8 ; @!P1 STG.E [R16.64], RZ ; ISETP.GE.AND P1, PT, R30, R5, PT ; @!P0 STG.E [R18.64], RZ ; IADD3 R8, P0, R8, 0x4, RZ ; IADD3.X R21, RZ, R9, RZ, P0, !PT ; @!P1 BRA 0x200 ; EXIT ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x178] ; IADD3 R2, R3.reuse, 0x2, RZ ; I2F R12, R3 ; IADD3 R4, R3.reuse, 0x3, RZ ; IMAD R11, R3.reuse, R10, c[0x0][0x178] ; IADD3 R6, R3.reuse, 0x4, RZ ; IADD3 R8, R3.reuse, 0x5, RZ ; IADD3 R9, R3.reuse, 0x6, RZ ; I2F R14, R7 ; IADD3 R10, R3, 0x7, RZ ; IADD3 R13, R11, c[0x0][0x178], RZ ; MOV R21, c[0x0][0x174] ; IADD3 R15, R13, c[0x0][0x178], RZ ; I2F R16, R2 ; FFMA R12, R12, R21, c[0x0][0x16c] ; IADD3 R17, R15, c[0x0][0x178], RZ ; IADD3 R19, R17, c[0x0][0x178], RZ ; I2F R18, R4 ; FFMA R14, R14, R21, c[0x0][0x16c] ; IADD3 R23, R19, c[0x0][0x178], RZ ; IADD3 R27, R23, c[0x0][0x178], RZ ; I2F R22, R6 ; FFMA R16, R16, R21, c[0x0][0x16c] ; I2F R24, R8 ; FFMA R18, R18, R21, c[0x0][0x16c] ; I2F R25, R9 ; FFMA R22, R22, R21, c[0x0][0x16c] ; I2F R26, R10 ; FFMA R24, R24, R21.reuse, c[0x0][0x16c] ; FFMA R25, R25, R21.reuse, c[0x0][0x16c] ; FFMA R26, R26, R21, c[0x0][0x16c] ; ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; I2F R28, R0 ; MOV R21, c[0x0][0x170] ; BSSY B0, 0x7c0 ; ISETP.GE.OR P1, PT, R3, c[0x0][0x17c], P0 ; FFMA R28, R28, R21, c[0x0][0x168] ; @P1 BRA 0x7b0 ; BSSY B1, 0x770 ; IMAD.MOV.U32 R29, RZ, RZ, RZ ; MOV R21, R12 ; MOV R20, R28 ; FMUL R31, R21, R21 ; FMUL R30, R20, R20 ; FADD R32, R31, R30 ; FSETP.GT.AND P1, PT, R32, 4, PT ; @P1 BRA 0x760 ; IADD3 R29, R29, 0x1, RZ ; FADD R20, R20, R20 ; FADD R31, -R31, R30 ; ISETP.GE.AND P1, PT, R29, c[0x0][0x180], PT ; FFMA R21, R20, R21, R12 ; FADD R20, R28, R31 ; @!P1 BRA 0x6a0 ; BSYNC B1 ; IMAD.MOV.U32 R21, RZ, RZ, 0x4 ; IMAD R20, R3, c[0x0][0x178], R0 ; IMAD.WIDE R20, R20, R21, c[0x0][0x160] ; STG.E [R20.64], R29 ; BSYNC B0 ; ISETP.GE.OR P1, PT, R7, c[0x0][0x17c], P0 ; BSSY B0, 0x950 ; @P1 BRA 0x940 ; HFMA2.MMA R29, -RZ, RZ, 0, 0 ; BSSY B1, 0x900 ; MOV R21, R14 ; MOV R20, R28 ; FMUL R31, R21, R21 ; FMUL R30, R20, R20 ; FADD R32, R31, R30 ; FSETP.GT.AND P1, PT, R32, 4, PT ; @P1 BRA 0x8f0 ; IADD3 R29, R29, 0x1, RZ ; FADD R20, R20, R20 ; FADD R31, -R31, R30 ; ISETP.GE.AND P1, PT, R29, c[0x0][0x180], PT ; FFMA R21, R20, R21, R14 ; FADD R20, R28, R31 ; @!P1 BRA 0x830 ; BSYNC B1 ; HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD.IADD R20, R11, 0x1, R0 ; IMAD.WIDE R20, R20, R21, c[0x0][0x160] ; STG.E [R20.64], R29 ; BSYNC B0 ; ISETP.GE.OR P1, PT, R2, c[0x0][0x17c], P0 ; BSSY B0, 0xae0 ; @P1 BRA 0xad0 ; BSSY B1, 0xa90 ; MOV R29, RZ ; IMAD.MOV.U32 R20, RZ, RZ, R28 ; MOV R21, R16 ; FMUL R31, R21, R21 ; FMUL R30, R20, R20 ; FADD R32, R31, R30 ; FSETP.GT.AND P1, PT, R32, 4, PT ; @P1 BRA 0xa80 ; IADD3 R29, R29, 0x1, RZ ; FADD R20, R20, R20 ; FADD R31, -R31, R30 ; ISETP.GE.AND P1, PT, R29, c[0x0][0x180], PT ; FFMA R21, R20, R21, R16 ; FADD R20, R28, R31 ; @!P1 BRA 0x9c0 ; BSYNC B1 ; HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; IADD3 R20, R13, R0, RZ ; IMAD.WIDE R20, R20, R21, c[0x0][0x160] ; STG.E [R20.64], R29 ; BSYNC B0 ; ISETP.GE.OR P1, PT, R4, c[0x0][0x17c], P0 ; BSSY B0, 0xc70 ; @P1 BRA 0xc60 ; BSSY B1, 0xc20 ; MOV R29, RZ ; IMAD.MOV.U32 R21, RZ, RZ, R18 ; MOV R20, R28 ; FMUL R31, R21, R21 ; FMUL R30, R20, R20 ; FADD R32, R31, R30 ; FSETP.GT.AND P1, PT, R32, 4, PT ; @P1 BRA 0xc10 ; IADD3 R29, R29, 0x1, RZ ; FADD R20, R20, R20 ; FADD R31, -R31, R30 ; ISETP.GE.AND P1, PT, R29, c[0x0][0x180], PT ; FFMA R21, R20, R21, R18 ; FADD R20, R28, R31 ; @!P1 BRA 0xb50 ; BSYNC B1 ; HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; IADD3 R20, R15, R0, RZ ; IMAD.WIDE R20, R20, R21, c[0x0][0x160] ; STG.E [R20.64], R29 ; BSYNC B0 ; ISETP.GE.OR P1, PT, R6, c[0x0][0x17c], P0 ; BSSY B0, 0xe00 ; @P1 BRA 0xdf0 ; BSSY B1, 0xdb0 ; IMAD.MOV.U32 R29, RZ, RZ, RZ ; MOV R21, R22 ; MOV R20, R28 ; FMUL R31, R21, R21 ; FMUL R30, R20, R20 ; FADD R32, R31, R30 ; FSETP.GT.AND P1, PT, R32, 4, PT ; @P1 BRA 0xda0 ; IADD3 R29, R29, 0x1, RZ ; FADD R20, R20, R20 ; FADD R31, -R31, R30 ; ISETP.GE.AND P1, PT, R29, c[0x0][0x180], PT ; FFMA R21, R20, R21, R22 ; FADD R20, R28, R31 ; @!P1 BRA 0xce0 ; BSYNC B1 ; IADD3 R20, R17, R0, RZ ; IMAD.MOV.U32 R21, RZ, RZ, 0x4 ; IMAD.WIDE R20, R20, R21, c[0x0][0x160] ; STG.E [R20.64], R29 ; BSYNC B0 ; ISETP.GE.OR P1, PT, R8, c[0x0][0x17c], P0 ; BSSY B0, 0xf90 ; @P1 BRA 0xf80 ; HFMA2.MMA R29, -RZ, RZ, 0, 0 ; BSSY B1, 0xf40 ; MOV R21, R24 ; MOV R20, R28 ; FMUL R31, R21, R21 ; FMUL R30, R20, R20 ; FADD R32, R31, R30 ; FSETP.GT.AND P1, PT, R32, 4, PT ; @P1 BRA 0xf30 ; IADD3 R29, R29, 0x1, RZ ; FADD R20, R20, R20 ; FADD R31, -R31, R30 ; ISETP.GE.AND P1, PT, R29, c[0x0][0x180], PT ; FFMA R21, R20, R21, R24 ; FADD R20, R28, R31 ; @!P1 BRA 0xe70 ; BSYNC B1 ; HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD.IADD R20, R19, 0x1, R0 ; IMAD.WIDE R20, R20, R21, c[0x0][0x160] ; STG.E [R20.64], R29 ; BSYNC B0 ; ISETP.GE.OR P1, PT, R9, c[0x0][0x17c], P0 ; BSSY B0, 0x1120 ; @P1 BRA 0x1110 ; BSSY B1, 0x10d0 ; MOV R29, RZ ; IMAD.MOV.U32 R21, RZ, RZ, R28 ; MOV R20, R25 ; FMUL R31, R20, R20 ; FMUL R32, R21, R21 ; FADD R30, R31, R32 ; FSETP.GT.AND P1, PT, R30, 4, PT ; @P1 BRA 0x10c0 ; IADD3 R29, R29, 0x1, RZ ; FADD R30, R21, R21 ; FADD R21, -R31, R32 ; ISETP.GE.AND P1, PT, R29, c[0x0][0x180], PT ; FFMA R20, R30, R20, R25 ; FADD R21, R28, R21 ; @!P1 BRA 0x1000 ; BSYNC B1 ; HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; IADD3 R20, R23, R0, RZ ; IMAD.WIDE R20, R20, R21, c[0x0][0x160] ; STG.E [R20.64], R29 ; BSYNC B0 ; ISETP.GE.OR P0, PT, R10, c[0x0][0x17c], P0 ; BSSY B0, 0x12b0 ; @P0 BRA 0x12a0 ; BSSY B1, 0x1260 ; MOV R29, RZ ; IMAD.MOV.U32 R21, RZ, RZ, R26 ; MOV R20, R28 ; FMUL R31, R21, R21 ; FMUL R30, R20, R20 ; FADD R32, R31, R30 ; FSETP.GT.AND P0, PT, R32, 4, PT ; @P0 BRA 0x1250 ; IADD3 R29, R29, 0x1, RZ ; FADD R20, R20, R20 ; FADD R31, -R31, R30 ; ISETP.GE.AND P0, PT, R29, c[0x0][0x180], PT ; FFMA R21, R20, R21, R26 ; FADD R20, R28, R31 ; @!P0 BRA 0x1190 ; BSYNC B1 ; HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; IADD3 R20, R27, R0, RZ ; IMAD.WIDE R20, R20, R21, c[0x0][0x160] ; STG.E [R20.64], R29 ; BSYNC B0 ; ISETP.GE.AND P0, PT, R0.reuse, R5, PT ; IADD3 R0, R0, 0x1, RZ ; @P0 CALL.REL.NOINC 0x12f0 ; BRA 0x5f0 ; EXIT ; BRA 0x1300; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0005b5ee_00000000-6_878f1651401d9dbf66e865ca2e565ecf3beea19a.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z6mandelffi .type _Z6mandelffi, @function _Z6mandelffi: .LFB2057: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2057: .size _Z6mandelffi, .-_Z6mandelffi .globl _Z39__device_stub__Z12mandelKernelPiffffiiiPiffffiii .type _Z39__device_stub__Z12mandelKernelPiffffiiiPiffffiii, @function _Z39__device_stub__Z12mandelKernelPiffffiiiPiffffiii: .LFB2083: .cfi_startproc endbr64 subq $200, %rsp .cfi_def_cfa_offset 208 movq %rdi, 40(%rsp) movss %xmm0, 36(%rsp) movss %xmm1, 32(%rsp) movss %xmm2, 28(%rsp) movss %xmm3, 24(%rsp) movl %esi, 20(%rsp) movl %edx, 16(%rsp) movl %ecx, 12(%rsp) movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 36(%rsp), %rax movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 28(%rsp), %rax movq %rax, 136(%rsp) leaq 24(%rsp), %rax movq %rax, 144(%rsp) leaq 20(%rsp), %rax movq %rax, 152(%rsp) leaq 16(%rsp), %rax movq %rax, 160(%rsp) leaq 12(%rsp), %rax movq %rax, 168(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L9 .L5: movq 184(%rsp), %rax subq %fs:40, %rax jne .L10 addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L9: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 216 pushq 56(%rsp) .cfi_def_cfa_offset 224 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z12mandelKernelPiffffiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 208 jmp .L5 .L10: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z39__device_stub__Z12mandelKernelPiffffiiiPiffffiii, .-_Z39__device_stub__Z12mandelKernelPiffffiiiPiffffiii .globl _Z12mandelKernelPiffffiii .type _Z12mandelKernelPiffffiii, @function _Z12mandelKernelPiffffiii: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z39__device_stub__Z12mandelKernelPiffffiiiPiffffiii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z12mandelKernelPiffffiii, .-_Z12mandelKernelPiffffiii .globl _Z6hostFEffffPiiii .type _Z6hostFEffffPiiii, @function _Z6hostFEffffPiiii: .LFB2058: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $104, %rsp .cfi_def_cfa_offset 160 movss %xmm0, 12(%rsp) movss %xmm1, 16(%rsp) movss %xmm2, 20(%rsp) movss %xmm3, 24(%rsp) movq %rdi, %rbx movl %esi, %ebp movl %edx, %r12d movl %ecx, 28(%rsp) movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax movl $16, 64(%rsp) movl $16, 68(%rsp) movl $1, 72(%rsp) pxor %xmm0, %xmm0 cvtsi2sdl %edx, %xmm0 mulsd .LC0(%rip), %xmm0 movapd %xmm0, %xmm1 movsd .LC4(%rip), %xmm3 movapd %xmm0, %xmm2 andpd %xmm3, %xmm2 movsd .LC1(%rip), %xmm4 ucomisd %xmm2, %xmm4 jbe .L14 cvttsd2siq %xmm0, %rax pxor %xmm2, %xmm2 cvtsi2sdq %rax, %xmm2 cmpnlesd %xmm2, %xmm1 movsd .LC3(%rip), %xmm4 andpd %xmm4, %xmm1 addsd %xmm2, %xmm1 andnpd %xmm0, %xmm3 orpd %xmm3, %xmm1 .L14: pxor %xmm0, %xmm0 cvtsi2sdl %ebp, %xmm0 mulsd .LC0(%rip), %xmm0 movapd %xmm0, %xmm4 movsd .LC4(%rip), %xmm3 movapd %xmm0, %xmm2 andpd %xmm3, %xmm2 movsd .LC1(%rip), %xmm5 ucomisd %xmm2, %xmm5 jbe .L15 cvttsd2siq %xmm0, %rax pxor %xmm2, %xmm2 cvtsi2sdq %rax, %xmm2 cmpnlesd %xmm2, %xmm4 movsd .LC3(%rip), %xmm5 andpd %xmm5, %xmm4 addsd %xmm2, %xmm4 andnpd %xmm0, %xmm3 orpd %xmm3, %xmm4 .L15: cvttsd2sil %xmm4, %eax movl %eax, 76(%rsp) cvttsd2sil %xmm1, %eax movl %eax, 80(%rsp) movl $1, 84(%rsp) movslq %ebp, %r13 movslq %r12d, %r15 movq %r13, %r14 imulq %r15, %r14 salq $2, %r14 leaq 56(%rsp), %rdi movl $2, %edx movq %r14, %rsi call cudaHostAlloc@PLT leaq 0(,%r13,4), %rdx leaq 48(%rsp), %rsi leaq 40(%rsp), %rdi movq %r15, %rcx call cudaMallocPitch@PLT movl 72(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 64(%rsp), %rdx movq 76(%rsp), %rdi movl 84(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L25 .L16: call cudaDeviceSynchronize@PLT movl $2, %ecx movq %r14, %rdx movq 40(%rsp), %rsi movq 56(%rsp), %rdi call cudaMemcpy@PLT testl %r12d, %r12d jle .L17 movq 56(%rsp), %rsi movl $0, %r8d movl $0, %edi jmp .L18 .L25: movss 16(%rsp), %xmm3 movss 24(%rsp), %xmm6 subss %xmm6, %xmm3 pxor %xmm1, %xmm1 cvtsi2ssl %r12d, %xmm1 movss 12(%rsp), %xmm2 movss 20(%rsp), %xmm7 subss %xmm7, %xmm2 pxor %xmm0, %xmm0 cvtsi2ssl %ebp, %xmm0 movl 28(%rsp), %ecx movl %r12d, %edx movl %ebp, %esi divss %xmm1, %xmm3 divss %xmm0, %xmm2 movaps %xmm6, %xmm1 movaps %xmm7, %xmm0 movq 40(%rsp), %rdi call _Z39__device_stub__Z12mandelKernelPiffffiiiPiffffiii jmp .L16 .L20: movslq %r8d, %rcx leaq 0(,%rcx,4), %rax addq %r13, %rcx salq $2, %rcx .L19: movl (%rsi,%rax), %edx movl %edx, (%rbx,%rax) addq $4, %rax cmpq %rcx, %rax jne .L19 .L21: addl $1, %edi addl %ebp, %r8d cmpl %edi, %r12d je .L17 .L18: testl %ebp, %ebp jg .L20 jmp .L21 .L17: movq 40(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rdi call cudaFreeHost@PLT movq 88(%rsp), %rax subq %fs:40, %rax jne .L26 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L26: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size _Z6hostFEffffPiiii, .-_Z6hostFEffffPiiii .section .rodata.str1.1,"aMS",@progbits,1 .LC5: .string "_Z12mandelKernelPiffffiii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _Z12mandelKernelPiffffiii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC0: .long 0 .long 1065353216 .align 8 .LC1: .long 0 .long 1127219200 .align 8 .LC3: .long 0 .long 1072693248 .align 8 .LC4: .long -1 .long 2147483647 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z12mandelKernelPiffffiii ; -- Begin function _Z12mandelKernelPiffffiii .globl _Z12mandelKernelPiffffiii .p2align 8 .type _Z12mandelKernelPiffffiii,@function _Z12mandelKernelPiffffiii: ; @_Z12mandelKernelPiffffiii ; %bb.0: s_clause 0x2 s_load_b32 s3, s[0:1], 0x34 s_load_b32 s2, s[0:1], 0x20 s_load_b256 s[4:11], s[0:1], 0x0 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v0, v0, 10, 10 s_waitcnt lgkmcnt(0) s_lshr_b32 s0, s3, 16 s_and_b32 s1, s3, 0xffff s_mul_i32 s15, s15, s0 s_mul_i32 s14, s14, s1 v_add_lshl_u32 v1, s15, v0, 3 v_add_lshl_u32 v0, s14, v2, 3 s_cmp_gt_i32 s2, 0 s_mov_b32 s3, 0 s_cselect_b32 s1, -1, 0 v_or_b32_e32 v2, 7, v1 v_or_b32_e32 v3, 7, v0 s_branch .LBB0_2 .LBB0_1: ; in Loop: Header=BB0_2 Depth=1 s_or_b32 exec_lo, exec_lo, s12 v_add_nc_u32_e32 v4, 1, v0 v_cmp_eq_u32_e32 vcc_lo, v0, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_mov_b32_e32 v0, v4 s_or_b32 s3, vcc_lo, s3 s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execz .LBB0_13 .LBB0_2: ; %.preheader ; =>This Loop Header: Depth=1 ; Child Loop BB0_6 Depth 2 ; Child Loop BB0_10 Depth 3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_cvt_f32_i32_e32 v4, v0 v_cmp_gt_i32_e64 s0, s10, v0 v_mov_b32_e32 v5, v1 s_mov_b32 s12, 0 v_fma_f32 v4, v4, s8, s6 s_branch .LBB0_6 .LBB0_3: ; %Flow53 ; in Loop: Header=BB0_6 Depth=2 s_set_inst_prefetch_distance 0x2 s_or_b32 exec_lo, exec_lo, s14 .LBB0_4: ; %_Z6mandelffi.exit ; in Loop: Header=BB0_6 Depth=2 v_mad_u64_u32 v[6:7], null, v5, s10, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v7, 31, v6 v_lshlrev_b64 v[6:7], 2, v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, s4, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo global_store_b32 v[6:7], v8, off .LBB0_5: ; %Flow55 ; in Loop: Header=BB0_6 Depth=2 s_or_b32 exec_lo, exec_lo, s13 v_add_nc_u32_e32 v6, 1, v5 v_cmp_eq_u32_e32 vcc_lo, v5, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_mov_b32_e32 v5, v6 s_or_b32 s12, vcc_lo, s12 s_and_not1_b32 exec_lo, exec_lo, s12 s_cbranch_execz .LBB0_1 .LBB0_6: ; Parent Loop BB0_2 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB0_10 Depth 3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s11, v5 s_and_b32 s14, s0, vcc_lo s_and_saveexec_b32 s13, s14 s_cbranch_execz .LBB0_5 ; %bb.7: ; in Loop: Header=BB0_6 Depth=2 s_and_not1_b32 vcc_lo, exec_lo, s1 s_cbranch_vccnz .LBB0_12 ; %bb.8: ; %.lr.ph.i.preheader ; in Loop: Header=BB0_6 Depth=2 v_cvt_f32_i32_e32 v6, v5 v_mov_b32_e32 v9, v4 s_mov_b32 s14, 0 s_mov_b32 s15, 0 ; implicit-def: $sgpr16 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v6, v6, s9, s7 v_mov_b32_e32 v7, v6 s_set_inst_prefetch_distance 0x1 s_branch .LBB0_10 .p2align 6 .LBB0_9: ; %Flow ; in Loop: Header=BB0_10 Depth=3 s_or_b32 exec_lo, exec_lo, s17 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s17, exec_lo, s16 s_or_b32 s14, s17, s14 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s14 s_cbranch_execz .LBB0_3 .LBB0_10: ; %.lr.ph.i ; Parent Loop BB0_2 Depth=1 ; Parent Loop BB0_6 Depth=2 ; => This Inner Loop Header: Depth=3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mul_f32_e32 v10, v7, v7 s_or_b32 s16, s16, exec_lo v_fma_f32 v8, v9, v9, v10 s_delay_alu instid0(VALU_DEP_1) v_cmp_nlt_f32_e32 vcc_lo, 4.0, v8 v_mov_b32_e32 v8, s15 s_and_saveexec_b32 s17, vcc_lo s_cbranch_execz .LBB0_9 ; %bb.11: ; in Loop: Header=BB0_10 Depth=3 v_mul_f32_e32 v8, v9, v9 v_add_f32_e32 v9, v9, v9 s_add_i32 s15, s15, 1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) s_cmp_eq_u32 s2, s15 v_sub_f32_e32 v10, v8, v10 s_cselect_b32 s18, -1, 0 v_mov_b32_e32 v8, s2 v_fma_f32 v7, v7, v9, v6 s_and_not1_b32 s16, s16, exec_lo v_add_f32_e32 v9, v4, v10 s_and_b32 s18, s18, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s16, s16, s18 s_branch .LBB0_9 .LBB0_12: ; in Loop: Header=BB0_6 Depth=2 v_mov_b32_e32 v8, 0 s_branch .LBB0_4 .LBB0_13: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12mandelKernelPiffffiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 19 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z12mandelKernelPiffffiii, .Lfunc_end0-_Z12mandelKernelPiffffiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 484 ; NumSgprs: 21 ; NumVgprs: 11 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 21 ; NumVGPRsForWavesPerEU: 11 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12mandelKernelPiffffiii .private_segment_fixed_size: 0 .sgpr_count: 21 .sgpr_spill_count: 0 .symbol: _Z12mandelKernelPiffffiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "878f1651401d9dbf66e865ca2e565ecf3beea19a.hip" .globl _Z27__device_stub__mandelKernelPiffffiii # -- Begin function _Z27__device_stub__mandelKernelPiffffiii .p2align 4, 0x90 .type _Z27__device_stub__mandelKernelPiffffiii,@function _Z27__device_stub__mandelKernelPiffffiii: # @_Z27__device_stub__mandelKernelPiffffiii .cfi_startproc # %bb.0: subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 88(%rsp) movss %xmm0, 36(%rsp) movss %xmm1, 32(%rsp) movss %xmm2, 28(%rsp) movss %xmm3, 24(%rsp) movl %esi, 20(%rsp) movl %edx, 16(%rsp) movl %ecx, 12(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 36(%rsp), %rax movq %rax, 104(%rsp) leaq 32(%rsp), %rax movq %rax, 112(%rsp) leaq 28(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 20(%rsp), %rax movq %rax, 136(%rsp) leaq 16(%rsp), %rax movq %rax, 144(%rsp) leaq 12(%rsp), %rax movq %rax, 152(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z12mandelKernelPiffffiii, %edi pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $184, %rsp .cfi_adjust_cfa_offset -184 retq .Lfunc_end0: .size _Z27__device_stub__mandelKernelPiffffiii, .Lfunc_end0-_Z27__device_stub__mandelKernelPiffffiii .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function _Z6hostFEffffPiiii .LCPI1_0: .quad 0x3f80000000000000 # double 0.0078125 .text .globl _Z6hostFEffffPiiii .p2align 4, 0x90 .type _Z6hostFEffffPiiii,@function _Z6hostFEffffPiiii: # @_Z6hostFEffffPiiii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $200, %rsp .cfi_def_cfa_offset 256 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %ecx, 40(%rsp) # 4-byte Spill movl %edx, %ebp movl %esi, %ebx movq %rdi, %r14 movss %xmm3, 36(%rsp) # 4-byte Spill movss %xmm2, 28(%rsp) # 4-byte Spill movss %xmm1, 32(%rsp) # 4-byte Spill movss %xmm0, 24(%rsp) # 4-byte Spill xorps %xmm0, %xmm0 cvtsi2sd %esi, %xmm0 mulsd .LCPI1_0(%rip), %xmm0 callq ceil@PLT cvttsd2si %xmm0, %r15d xorps %xmm0, %xmm0 cvtsi2sd %ebp, %xmm0 mulsd .LCPI1_0(%rip), %xmm0 callq ceil@PLT cvttsd2si %xmm0, %r12d shlq $32, %r12 orq %r15, %r12 movslq %ebx, %r13 shlq $2, %r13 movslq %ebp, %r15 movq %r13, %rsi imulq %r15, %rsi leaq 8(%rsp), %rdi movl $2, %edx callq hipHostMalloc leaq 16(%rsp), %rdi leaq 192(%rsp), %rsi movq %r13, %rdx movq %r15, %rcx callq hipMallocPitch movabsq $68719476752, %rdx # imm = 0x1000000010 movq %r12, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: xorps %xmm0, %xmm0 cvtsi2ss %ebp, %xmm0 movss 36(%rsp), %xmm2 # 4-byte Reload # xmm2 = mem[0],zero,zero,zero movss 32(%rsp), %xmm3 # 4-byte Reload # xmm3 = mem[0],zero,zero,zero subss %xmm2, %xmm3 cvtsi2ss %ebx, %xmm1 divss %xmm0, %xmm3 movss 28(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss 24(%rsp), %xmm4 # 4-byte Reload # xmm4 = mem[0],zero,zero,zero subss %xmm0, %xmm4 divss %xmm1, %xmm4 movq 16(%rsp), %rax movq %rax, 120(%rsp) movss %xmm0, 68(%rsp) movss %xmm2, 64(%rsp) movss %xmm4, 60(%rsp) movss %xmm3, 56(%rsp) movl %ebx, 52(%rsp) movl %ebp, 48(%rsp) movl 40(%rsp), %eax # 4-byte Reload movl %eax, 44(%rsp) leaq 120(%rsp), %rax movq %rax, 128(%rsp) leaq 68(%rsp), %rax movq %rax, 136(%rsp) leaq 64(%rsp), %rax movq %rax, 144(%rsp) leaq 60(%rsp), %rax movq %rax, 152(%rsp) leaq 56(%rsp), %rax movq %rax, 160(%rsp) leaq 52(%rsp), %rax movq %rax, 168(%rsp) leaq 48(%rsp), %rax movq %rax, 176(%rsp) leaq 44(%rsp), %rax movq %rax, 184(%rsp) leaq 104(%rsp), %rdi leaq 88(%rsp), %rsi leaq 80(%rsp), %rdx leaq 72(%rsp), %rcx callq __hipPopCallConfiguration movq 104(%rsp), %rsi movl 112(%rsp), %edx movq 88(%rsp), %rcx movl 96(%rsp), %r8d leaq 128(%rsp), %r9 movl $_Z12mandelKernelPiffffiii, %edi pushq 72(%rsp) .cfi_adjust_cfa_offset 8 pushq 88(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: callq hipDeviceSynchronize movq 8(%rsp), %rdi movq 16(%rsp), %rsi movl %ebp, %eax imull %ebx, %eax movslq %eax, %rdx shlq $2, %rdx movl $2, %ecx callq hipMemcpy testl %ebp, %ebp jle .LBB1_8 # %bb.3: # %.preheader.lr.ph movq 8(%rsp), %rax movl %ebp, %ecx movl %ebx, %edx xorl %esi, %esi xorl %edi, %edi jmp .LBB1_4 .p2align 4, 0x90 .LBB1_7: # %._crit_edge # in Loop: Header=BB1_4 Depth=1 incq %rdi addl %ebx, %esi cmpq %rcx, %rdi je .LBB1_8 .LBB1_4: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_6 Depth 2 testl %ebx, %ebx jle .LBB1_7 # %bb.5: # %.lr.ph # in Loop: Header=BB1_4 Depth=1 movl %esi, %r9d leaq (%r14,%r9,4), %r8 leaq (%rax,%r9,4), %r9 xorl %r10d, %r10d .p2align 4, 0x90 .LBB1_6: # Parent Loop BB1_4 Depth=1 # => This Inner Loop Header: Depth=2 movl (%r9,%r10,4), %r11d movl %r11d, (%r8,%r10,4) incq %r10 cmpq %r10, %rdx jne .LBB1_6 jmp .LBB1_7 .LBB1_8: # %._crit_edge45 movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipHostFree addq $200, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z6hostFEffffPiiii, .Lfunc_end1-_Z6hostFEffffPiiii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12mandelKernelPiffffiii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z12mandelKernelPiffffiii,@object # @_Z12mandelKernelPiffffiii .section .rodata,"a",@progbits .globl _Z12mandelKernelPiffffiii .p2align 3, 0x0 _Z12mandelKernelPiffffiii: .quad _Z27__device_stub__mandelKernelPiffffiii .size _Z12mandelKernelPiffffiii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z12mandelKernelPiffffiii" .size .L__unnamed_1, 26 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__mandelKernelPiffffiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12mandelKernelPiffffiii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
6,856
4,425
4,334
4,430
124
code for sm_80 Function : _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; ULDC.64 UR4, c[0x0][0x160] ; UIMAD UR4, UR5, UR4, URZ ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, UR4, PT ; @P0 EXIT ; IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD R5, R0, 0x3, RZ ; IMAD.WIDE R6, R5, R2, c[0x0][0x178] ; LDG.E R3, [R6.64] ; LDG.E R4, [R6.64+0x4] ; LDG.E R11, [R6.64+0x8] ; IABS R13, c[0x0][0x164] ; I2F.RP R10, R13 ; IABS R6, R0 ; MUFU.RCP R10, R10 ; IADD3 R8, R10, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; IMAD.MOV R12, RZ, RZ, -R9 ; IMAD R15, R12, R13, RZ ; IMAD.HI.U32 R9, R9, R15, R8 ; IMAD.HI.U32 R9, R9, R6, RZ ; IMAD.MOV R7, RZ, RZ, -R9 ; IMAD R6, R13, R7, R6 ; ISETP.GT.U32.AND P1, PT, R13, R6, PT ; @!P1 IMAD.IADD R6, R6, 0x1, -R13 ; @!P1 IADD3 R9, R9, 0x1, RZ ; ISETP.NE.AND P1, PT, RZ, c[0x0][0x164], PT ; ISETP.GE.U32.AND P2, PT, R6, R13, PT ; LOP3.LUT R6, R0, c[0x0][0x164], RZ, 0x3c, !PT ; ISETP.GE.AND P3, PT, R6, RZ, PT ; @P2 IADD3 R9, R9, 0x1, RZ ; LOP3.LUT R7, R4, R3, RZ, 0xfc, !PT ; ISETP.GE.AND P0, PT, R7, RZ, PT ; ISETP.GE.OR P0, PT, R3, c[0x0][0x16c], !P0 ; ISETP.GE.OR P0, PT, R4, c[0x0][0x170], P0 ; ISETP.LT.OR P0, PT, R11, RZ, P0 ; ISETP.GE.OR P0, PT, R11, c[0x0][0x174], P0 ; @P0 EXIT ; SHF.R.S32.HI R8, RZ, 0x1f, R5 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; LEA R6, P0, R5.reuse, c[0x0][0x190], 0x2 ; MOV R9, c[0x0][0x168] ; @!P3 IMAD.MOV R11, RZ, RZ, -R11 ; LEA.HI.X R7, R5, c[0x0][0x194], R8, 0x2, P0 ; ISETP.GE.AND P0, PT, R9, 0x1, PT ; @!P1 LOP3.LUT R11, RZ, c[0x0][0x164], RZ, 0x33, !PT ; STG.E [R6.64+0x4], R4 ; STG.E [R6.64+0x8], R3 ; STG.E [R6.64], R11 ; @!P0 EXIT ; IADD3 R5, R9, -0x1, RZ ; IMAD R4, R11, c[0x0][0x170], R4 ; ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; LOP3.LUT R5, R9, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R9, RZ, RZ, RZ ; @!P0 BRA 0xc90 ; IMAD R6, R4, c[0x0][0x16c], R3 ; IADD3 R24, -R5, c[0x0][0x168], RZ ; ULDC.64 UR6, c[0x0][0x180] ; IMAD R7, R6, c[0x0][0x168], RZ ; ISETP.GT.AND P0, PT, R24, RZ, PT ; IMAD.WIDE R12, R7.reuse, R2.reuse, c[0x0][0x188] ; IADD3 R9, R7.reuse, 0x3, RZ ; IADD3 R21, R7.reuse, 0x2, RZ ; IADD3 R23, R7, 0x1, RZ ; IMAD.WIDE R6, R9, R2, c[0x0][0x188] ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; IMAD.WIDE R20, R21, R2, c[0x0][0x188] ; IMAD.WIDE R22, R23, R2, c[0x0][0x188] ; IMAD R6, R0, c[0x0][0x168], RZ ; IMAD.MOV.U32 R9, RZ, RZ, RZ ; @!P0 BRA 0xae0 ; ISETP.GT.AND P1, PT, R24, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x840 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.U32 R10, RZ, RZ, UR6 ; IMAD.U32 R11, RZ, RZ, UR7 ; IMAD.WIDE R10, R6, 0x4, R10 ; LDG.E R15, [R10.64] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64], R15 ; LDG.E R17, [R10.64+0x4] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64], R17 ; LDG.E R19, [R10.64+0x8] ; MOV R14, R8 ; IMAD.MOV.U32 R15, RZ, RZ, R7 ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64], R19 ; LDG.E R25, [R10.64+0xc] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64], R25 ; LDG.E R7, [R10.64+0x10] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64+0x10], R7 ; LDG.E R27, [R10.64+0x14] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64+0x10], R27 ; LDG.E R17, [R10.64+0x18] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64+0x10], R17 ; LDG.E R29, [R10.64+0x1c] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64+0x10], R29 ; LDG.E R19, [R10.64+0x20] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64+0x20], R19 ; LDG.E R25, [R10.64+0x24] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64+0x20], R25 ; LDG.E R7, [R10.64+0x28] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64+0x20], R7 ; LDG.E R27, [R10.64+0x2c] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64+0x20], R27 ; LDG.E R17, [R10.64+0x30] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64+0x30], R17 ; LDG.E R29, [R10.64+0x34] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64+0x30], R29 ; LDG.E R19, [R10.64+0x38] ; IADD3 R24, R24, -0x10, RZ ; ISETP.GT.AND P1, PT, R24, 0xc, PT ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64+0x30], R19 ; LDG.E R25, [R10.64+0x3c] ; UIADD3 UR6, UP0, UR6, 0x40, URZ ; IADD3 R8, P2, R14, 0x40, RZ ; IADD3 R22, P4, R22, 0x40, RZ ; IADD3 R12, P5, R12, 0x40, RZ ; IADD3 R20, P3, R20, 0x40, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD.X R7, RZ, RZ, R15, P2 ; IADD3 R9, R9, 0x10, RZ ; IMAD.X R23, RZ, RZ, R23, P4 ; IMAD.X R21, RZ, RZ, R21, P3 ; IMAD.X R13, RZ, RZ, R13, P5 ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64+0x30], R25 ; @P1 BRA 0x510 ; ISETP.GT.AND P1, PT, R24, 0x4, PT ; @!P1 BRA 0xac0 ; MOV R10, UR6 ; IMAD.U32 R11, RZ, RZ, UR7 ; IMAD.WIDE R10, R6, 0x4, R10 ; LDG.E R15, [R10.64] ; IMAD.MOV.U32 R14, RZ, RZ, R22 ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64], R15 ; LDG.E R17, [R10.64+0x4] ; IMAD.MOV.U32 R15, RZ, RZ, R23 ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64], R17 ; LDG.E R19, [R10.64+0x8] ; IMAD.MOV.U32 R16, RZ, RZ, R20 ; IMAD.MOV.U32 R17, RZ, RZ, R21 ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R16.64], R19 ; LDG.E R25, [R10.64+0xc] ; MOV R18, R8 ; IMAD.MOV.U32 R19, RZ, RZ, R7 ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R18.64], R25 ; LDG.E R27, [R10.64+0x10] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64+0x10], R27 ; LDG.E R29, [R10.64+0x14] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64+0x10], R29 ; LDG.E R26, [R10.64+0x18] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R16.64+0x10], R26 ; LDG.E R28, [R10.64+0x1c] ; IADD3 R8, P1, R8, 0x20, RZ ; IADD3 R20, P2, R20, 0x20, RZ ; IADD3 R22, P3, R22, 0x20, RZ ; IADD3 R12, P4, R12, 0x20, RZ ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R18.64+0x10], R28 ; UIADD3 UR6, UP0, UR6, 0x20, URZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.X R7, RZ, RZ, R7, P1 ; IADD3 R9, R9, 0x8, RZ ; IMAD.X R21, RZ, RZ, R21, P2 ; IADD3 R24, R24, -0x8, RZ ; IMAD.X R23, RZ, RZ, R23, P3 ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD.X R13, RZ, RZ, R13, P4 ; ISETP.NE.OR P0, PT, R24, RZ, P0 ; @!P0 BRA 0xc90 ; MOV R10, UR6 ; IMAD.U32 R11, RZ, RZ, UR7 ; IMAD.WIDE R10, R6, 0x4, R10 ; LDG.E R15, [R10.64] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64], R15 ; LDG.E R17, [R10.64+0x4] ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R22.64], R17 ; LDG.E R19, [R10.64+0x8] ; IADD3 R24, R24, -0x4, RZ ; ISETP.NE.AND P0, PT, R24, RZ, PT ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R20.64], R19 ; LDG.E R25, [R10.64+0xc] ; UIADD3 UR6, UP0, UR6, 0x10, URZ ; IADD3 R12, P4, R12, 0x10, RZ ; IADD3 R22, P3, R22, 0x10, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD.MOV.U32 R10, RZ, RZ, R8 ; IMAD.MOV.U32 R11, RZ, RZ, R7 ; IADD3 R8, P1, R8, 0x10, RZ ; IADD3 R20, P2, R20, 0x10, RZ ; IMAD.X R13, RZ, RZ, R13, P4 ; IADD3 R9, R9, 0x4, RZ ; IMAD.X R7, RZ, RZ, R7, P1 ; IADD3.X R23, RZ, R23, RZ, P3, !PT ; IMAD.X R21, RZ, RZ, R21, P2 ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R10.64], R25 ; @P0 BRA 0xae0 ; ISETP.NE.AND P0, PT, R5, RZ, PT ; @!P0 EXIT ; IMAD R4, R4, c[0x0][0x16c], R3 ; IMAD R7, R0, c[0x0][0x168], R9.reuse ; IMAD R3, R4, c[0x0][0x168], R9 ; IMAD.WIDE R6, R7, R2, c[0x0][0x180] ; IMAD.WIDE R2, R3, R2, c[0x0][0x188] ; IMAD.MOV.U32 R11, RZ, RZ, R7 ; IMAD.MOV.U32 R0, RZ, RZ, R2 ; IMAD.MOV.U32 R9, RZ, RZ, R3 ; IMAD.MOV.U32 R2, RZ, RZ, R6 ; MOV R3, R11 ; LDG.E R7, [R2.64] ; IADD3 R5, R5, -0x1, RZ ; ISETP.NE.AND P0, PT, R5, RZ, PT ; IADD3 R6, P1, R6, 0x4, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R0 ; IMAD.MOV.U32 R3, RZ, RZ, R9 ; IADD3 R0, P2, R0, 0x4, RZ ; IMAD.X R11, RZ, RZ, R11, P1 ; IMAD.X R9, RZ, RZ, R9, P2 ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R7 ; @P0 BRA 0xd30 ; EXIT ; BRA 0xe10; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000ab213_00000000-6_c16cd107331a7ea85cec940cc799372ceca017a9.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi .type _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi, @function _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi: .LFB2082: .cfi_startproc endbr64 subq $232, %rsp .cfi_def_cfa_offset 240 movl %edi, 60(%rsp) movl %esi, 56(%rsp) movl %edx, 52(%rsp) movl %ecx, 48(%rsp) movl %r8d, 44(%rsp) movl %r9d, 40(%rsp) movq 240(%rsp), %rax movq %rax, 32(%rsp) movq 248(%rsp), %rax movq %rax, 24(%rsp) movq 256(%rsp), %rax movq %rax, 16(%rsp) movq 264(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 216(%rsp) xorl %eax, %eax leaq 60(%rsp), %rax movq %rax, 128(%rsp) leaq 56(%rsp), %rax movq %rax, 136(%rsp) leaq 52(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 44(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 32(%rsp), %rax movq %rax, 176(%rsp) leaq 24(%rsp), %rax movq %rax, 184(%rsp) leaq 16(%rsp), %rax movq %rax, 192(%rsp) leaq 8(%rsp), %rax movq %rax, 200(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 216(%rsp), %rax subq %fs:40, %rax jne .L8 addq $232, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 248 pushq 72(%rsp) .cfi_def_cfa_offset 256 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 240 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi, .-_Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi .globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, @function _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 pushq 40(%rsp) .cfi_def_cfa_offset 24 pushq 40(%rsp) .cfi_def_cfa_offset 32 pushq 40(%rsp) .cfi_def_cfa_offset 40 pushq 40(%rsp) .cfi_def_cfa_offset 48 call _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi addq $40, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .-_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA kernel failed : %s\n" .text .globl _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st .type _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st, @function _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $40, %rsp .cfi_def_cfa_offset 96 movl %edi, %ebx movl %esi, %ebp movl %edx, %r12d movl %ecx, %r13d movl %r8d, %r14d movl %r9d, %r15d movl %edi, %edx imull %esi, %edx movl %edx, %ecx sarl $31, %ecx shrl $24, %ecx leal (%rdx,%rcx), %eax movzbl %al, %eax subl %ecx, %eax testl %eax, %eax setg %cl movzbl %cl, %ecx leal 255(%rdx), %eax testl %edx, %edx cmovns %edx, %eax sarl $8, %eax addl %ecx, %eax movl %eax, 8(%rsp) movl $1, 12(%rsp) movl $256, 20(%rsp) movl $1, 24(%rsp) movq 128(%rsp), %r9 movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L15 .L12: call cudaGetLastError@PLT testl %eax, %eax jne .L16 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 120(%rsp) .cfi_def_cfa_offset 104 pushq 120(%rsp) .cfi_def_cfa_offset 112 pushq 120(%rsp) .cfi_def_cfa_offset 120 pushq 120(%rsp) .cfi_def_cfa_offset 128 movl %r15d, %r9d movl %r14d, %r8d movl %r13d, %ecx movl %r12d, %edx movl %ebp, %esi movl %ebx, %edi call _Z62__device_stub__Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPiiiiiiiPKiPKfPfPi addq $32, %rsp .cfi_def_cfa_offset 96 jmp .L12 .L16: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC0(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $-1, %edi call exit@PLT .cfi_endproc .LFE2057: .size _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st, .-_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP11CUstream_st .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi ; -- Begin function _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .p2align 8 .type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@function _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi: ; @_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x44 s_load_b64 s[6:7], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mul_i32 s2, s7, s6 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s2, v1 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_9 ; %bb.1: s_load_b64 s[4:5], s[0:1], 0x18 v_lshl_add_u32 v3, v1, 1, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[5:6], 2, v[3:4] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s4, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo global_load_b32 v0, v[5:6], off s_waitcnt vmcnt(0) v_cmp_lt_i32_e32 vcc_lo, -1, v0 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_9 ; %bb.2: v_add_nc_u32_e32 v5, 1, v3 s_load_b32 s6, s[0:1], 0xc s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v6, 31, v5 v_lshlrev_b64 v[7:8], 2, v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v7, vcc_lo, s4, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo s_waitcnt lgkmcnt(0) v_cmp_gt_i32_e32 vcc_lo, s6, v0 global_load_b32 v2, v[7:8], off s_waitcnt vmcnt(0) v_cmp_lt_i32_e64 s2, -1, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_b32 exec_lo, exec_lo, s2 s_cbranch_execz .LBB0_9 ; %bb.3: v_add_nc_u32_e32 v7, 2, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v8, 31, v7 v_lshlrev_b64 v[7:8], 2, v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v9, vcc_lo, s4, v7 v_add_co_ci_u32_e32 v10, vcc_lo, s5, v8, vcc_lo s_load_b64 s[4:5], s[0:1], 0x10 global_load_b32 v9, v[9:10], off s_waitcnt lgkmcnt(0) v_cmp_gt_i32_e32 vcc_lo, s4, v2 s_waitcnt vmcnt(0) v_cmp_gt_i32_e64 s2, s5, v9 v_cmp_lt_i32_e64 s3, -1, v9 s_delay_alu instid0(VALU_DEP_2) s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_b32 s2, s2, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 exec_lo, exec_lo, s2 s_cbranch_execz .LBB0_9 ; %bb.4: s_ashr_i32 s8, s7, 31 v_ashrrev_i32_e32 v11, 31, v1 s_add_i32 s2, s7, s8 v_lshlrev_b64 v[3:4], 2, v[3:4] s_xor_b32 s7, s2, s8 v_lshlrev_b64 v[5:6], 2, v[5:6] v_cvt_f32_u32_e32 v9, s7 s_sub_i32 s2, 0, s7 v_add_nc_u32_e32 v12, v1, v11 s_load_b32 s5, s[0:1], 0x8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v9, v9 v_xor_b32_e32 v12, v12, v11 v_xor_b32_e32 v11, s8, v11 s_waitcnt_depctr 0xfff v_mul_f32_e32 v9, 0x4f7ffffe, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v9, v9 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s5, 1 v_mul_lo_u32 v10, s2, v9 s_load_b64 s[2:3], s[0:1], 0x30 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v10, v9, v10 v_add_nc_u32_e32 v13, v9, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[9:10], null, v12, v13, 0 v_mul_lo_u32 v9, v10, s7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v9, v12, v9 v_subrev_nc_u32_e32 v13, s7, v9 v_cmp_le_u32_e32 vcc_lo, s7, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v9, v9, v13 :: v_dual_add_nc_u32 v12, 1, v10 v_cndmask_b32_e32 v10, v10, v12, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_le_u32_e32 vcc_lo, s7, v9 v_add_nc_u32_e32 v12, 1, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v12, v10, v12, vcc_lo s_waitcnt lgkmcnt(0) v_add_co_u32 v9, vcc_lo, s2, v3 v_add_co_ci_u32_e32 v10, vcc_lo, s3, v4, vcc_lo v_xor_b32_e32 v3, v12, v11 v_add_co_u32 v4, vcc_lo, s2, v5 v_add_co_ci_u32_e32 v5, vcc_lo, s3, v6, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_sub_nc_u32_e32 v3, v3, v11 v_add_co_u32 v6, vcc_lo, s2, v7 v_add_co_ci_u32_e32 v7, vcc_lo, s3, v8, vcc_lo s_clause 0x2 global_store_b32 v[9:10], v3, off global_store_b32 v[4:5], v2, off global_store_b32 v[6:7], v0, off s_cbranch_scc1 .LBB0_9 ; %bb.5: ; %.lr.ph v_mad_u64_u32 v[4:5], null, v3, s4, v[2:3] s_load_b128 s[0:3], s[0:1], 0x20 v_mul_lo_u32 v5, v1, s5 s_mov_b32 s4, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v4, s6, v[0:1] v_mul_lo_u32 v4, v2, s5 .p2align 6 .LBB0_6: ; =>This Loop Header: Depth=1 ; Child Loop BB0_7 Depth 2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v0, s4, v5 v_add_nc_u32_e32 v2, s4, v4 s_mov_b32 s6, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v1, 31, v0 v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[0:1], 2, v[0:1] v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v0, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo global_load_b32 v6, v[6:7], off global_load_b32 v3, v[0:1], off .LBB0_7: ; %atomicrmw.start ; Parent Loop BB0_6 Depth=1 ; => This Inner Loop Header: Depth=2 s_waitcnt vmcnt(0) v_add_f32_e32 v2, v3, v6 global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, v2, v3 v_mov_b32_e32 v3, v2 s_or_b32 s6, vcc_lo, s6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s6 s_cbranch_execnz .LBB0_7 ; %bb.8: ; %atomicrmw.end ; in Loop: Header=BB0_6 Depth=1 s_or_b32 exec_lo, exec_lo, s6 s_add_i32 s4, s4, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u32 s4, s5 s_cbranch_scc1 .LBB0_6 .LBB0_9: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 312 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 14 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .Lfunc_end0-_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 844 ; NumSgprs: 18 ; NumVgprs: 14 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 14 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .offset: 56 .size: 4 .value_kind: hidden_block_count_x - .offset: 60 .size: 4 .value_kind: hidden_block_count_y - .offset: 64 .size: 4 .value_kind: hidden_block_count_z - .offset: 68 .size: 2 .value_kind: hidden_group_size_x - .offset: 70 .size: 2 .value_kind: hidden_group_size_y - .offset: 72 .size: 2 .value_kind: hidden_group_size_z - .offset: 74 .size: 2 .value_kind: hidden_remainder_x - .offset: 76 .size: 2 .value_kind: hidden_remainder_y - .offset: 78 .size: 2 .value_kind: hidden_remainder_z - .offset: 96 .size: 8 .value_kind: hidden_global_offset_x - .offset: 104 .size: 8 .value_kind: hidden_global_offset_y - .offset: 112 .size: 8 .value_kind: hidden_global_offset_z - .offset: 120 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 312 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 14 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "c16cd107331a7ea85cec940cc799372ceca017a9.hip" .globl _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi # -- Begin function _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .p2align 4, 0x90 .type _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@function _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi: # @_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .cfi_startproc # %bb.0: subq $168, %rsp .cfi_def_cfa_offset 176 movl %edi, 28(%rsp) movl %esi, 24(%rsp) movl %edx, 20(%rsp) movl %ecx, 16(%rsp) movl %r8d, 12(%rsp) movl %r9d, 8(%rsp) leaq 28(%rsp), %rax movq %rax, 80(%rsp) leaq 24(%rsp), %rax movq %rax, 88(%rsp) leaq 20(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 176(%rsp), %rax movq %rax, 128(%rsp) leaq 184(%rsp), %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $184, %rsp .cfi_adjust_cfa_offset -184 retq .Lfunc_end0: .size _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, .Lfunc_end0-_Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .cfi_endproc # -- End function .globl _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t # -- Begin function _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t .p2align 4, 0x90 .type _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t,@function _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t: # @_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $200, %rsp .cfi_def_cfa_offset 256 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %r9d, %ebx movl %r8d, %ebp movl %ecx, %r14d movl %edx, %r15d movl %esi, %r12d movl %edi, %r13d movq 288(%rsp), %r9 movl %esi, %eax imull %edi, %eax leal 255(%rax), %ecx testl %eax, %eax cmovnsl %eax, %ecx sarl $8, %ecx xorl %edi, %edi testl $-2147483393, %eax # imm = 0x800000FF setg %dil addl %ecx, %edi movabsq $4294967296, %rdx # imm = 0x100000000 orq %rdx, %rdi orq $256, %rdx # imm = 0x100 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 280(%rsp), %rax movq 272(%rsp), %rcx movq 264(%rsp), %rdx movq 256(%rsp), %rsi movl %r13d, 28(%rsp) movl %r12d, 24(%rsp) movl %r15d, 20(%rsp) movl %r14d, 16(%rsp) movl %ebp, 12(%rsp) movl %ebx, 8(%rsp) movq %rsi, 104(%rsp) movq %rdx, 96(%rsp) movq %rcx, 88(%rsp) movq %rax, 80(%rsp) leaq 28(%rsp), %rax movq %rax, 112(%rsp) leaq 24(%rsp), %rax movq %rax, 120(%rsp) leaq 20(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 12(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) leaq 104(%rsp), %rax movq %rax, 160(%rsp) leaq 96(%rsp), %rax movq %rax, 168(%rsp) leaq 88(%rsp), %rax movq %rax, 176(%rsp) leaq 80(%rsp), %rax movq %rax, 184(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: callq hipGetLastError testl %eax, %eax jne .LBB1_4 # %bb.3: addq $200, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_4: .cfi_def_cfa_offset 256 movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movq %rbx, %rdi movq %rax, %rdx xorl %eax, %eax callq fprintf movl $-1, %edi callq exit .Lfunc_end1: .size _Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t, .Lfunc_end1-_Z37voxel_pooling_forward_kernel_launcheriiiiiiPKiPKfPfPiP12ihipStream_t .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi,@object # @_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .section .rodata,"a",@progbits .globl _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .p2align 3, 0x0 _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi: .quad _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .size _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA kernel failed : %s\n" .size .L.str, 25 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi" .size .L__unnamed_1, 49 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z43__device_stub__voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
5,834
3,730
5,646
3,934
125
code for sm_80 Function : _Z8myKernelPlm .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; SHF.R.S32.HI R3, RZ, 0x1f, R0 ; ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; @P0 EXIT ; LEA R2, P0, R0, c[0x0][0x160], 0x3 ; ULDC.64 UR4, c[0x0][0x118] ; LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x3, P0 ; LDG.E.64 R4, [R2.64] ; IADD3 R4, P0, R4, 0x1, RZ ; IMAD.X R5, RZ, RZ, R5, P0 ; STG.E.64 [R2.64], R4 ; EXIT ; BRA 0x100; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00010b11_00000000-6_4a42326e113ed779afd4b6fb210027bfda512617.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z28__device_stub__Z8myKernelPlmPlm .type _Z28__device_stub__Z8myKernelPlmPlm, @function _Z28__device_stub__Z8myKernelPlmPlm: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z8myKernelPlm(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z28__device_stub__Z8myKernelPlmPlm, .-_Z28__device_stub__Z8myKernelPlmPlm .globl _Z8myKernelPlm .type _Z8myKernelPlm, @function _Z8myKernelPlm: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z28__device_stub__Z8myKernelPlmPlm addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z8myKernelPlm, .-_Z8myKernelPlm .globl kernel .type kernel, @function kernel: .LFB2057: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $40, %rsp .cfi_def_cfa_offset 64 movq %rdi, %rbp movq %rsi, %rbx movl $1024, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) testq %rsi, %rsi js .L12 pxor %xmm0, %xmm0 cvtsi2ssq %rsi, %xmm0 .L13: mulss .LC0(%rip), %xmm0 movaps %xmm0, %xmm3 movss .LC4(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC1(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L14 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC3(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L14: cvttss2siq %xmm3, %rax movl %eax, 8(%rsp) movl $1, 12(%rsp) movl 28(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L17 .L11: addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L12: .cfi_restore_state movq %rsi, %rax shrq %rax movq %rsi, %rdx andl $1, %edx orq %rdx, %rax pxor %xmm0, %xmm0 cvtsi2ssq %rax, %xmm0 addss %xmm0, %xmm0 jmp .L13 .L17: movq %rbx, %rsi movq %rbp, %rdi call _Z28__device_stub__Z8myKernelPlmPlm jmp .L11 .cfi_endproc .LFE2057: .size kernel, .-kernel .section .rodata.str1.1,"aMS",@progbits,1 .LC5: .string "_Z8myKernelPlm" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _Z8myKernelPlm(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 981467136 .align 4 .LC1: .long 1258291200 .align 4 .LC3: .long 1065353216 .align 4 .LC4: .long 2147483647 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z8myKernelPlm ; -- Begin function _Z8myKernelPlm .globl _Z8myKernelPlm .p2align 8 .type _Z8myKernelPlm,@function _Z8myKernelPlm: ; @_Z8myKernelPlm ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x1c s_load_b64 s[2:3], s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2] s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b64 s[0:1], s[0:1], 0x0 v_lshlrev_b64 v[0:1], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b64 v[2:3], v[0:1], off s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo global_store_b64 v[0:1], v[2:3], off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z8myKernelPlm .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z8myKernelPlm, .Lfunc_end0-_Z8myKernelPlm ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 144 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 8 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z8myKernelPlm .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z8myKernelPlm.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "4a42326e113ed779afd4b6fb210027bfda512617.hip" .globl _Z23__device_stub__myKernelPlm # -- Begin function _Z23__device_stub__myKernelPlm .p2align 4, 0x90 .type _Z23__device_stub__myKernelPlm,@function _Z23__device_stub__myKernelPlm: # @_Z23__device_stub__myKernelPlm .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z8myKernelPlm, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z23__device_stub__myKernelPlm, .Lfunc_end0-_Z23__device_stub__myKernelPlm .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function kernel .LCPI1_0: .long 0x3a800000 # float 9.765625E-4 .text .globl kernel .p2align 4, 0x90 .type kernel,@function kernel: # @kernel .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $88, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %rbx movq %rdi, %r14 testq %rsi, %rsi js .LBB1_1 # %bb.2: cvtsi2ss %rbx, %xmm0 jmp .LBB1_3 .LBB1_1: movq %rbx, %rax shrq %rax movl %ebx, %ecx andl $1, %ecx orq %rax, %rcx cvtsi2ss %rcx, %xmm0 addss %xmm0, %xmm0 .LBB1_3: mulss .LCPI1_0(%rip), %xmm0 callq ceilf@PLT cvttss2si %xmm0, %rax movl %eax, %edi movabsq $4294967296, %rdx # imm = 0x100000000 orq %rdx, %rdi orq $1024, %rdx # imm = 0x400 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_5 # %bb.4: movq %r14, 56(%rsp) movq %rbx, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z8myKernelPlm, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_5: addq $88, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size kernel, .Lfunc_end1-kernel .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z8myKernelPlm, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z8myKernelPlm,@object # @_Z8myKernelPlm .section .rodata,"a",@progbits .globl _Z8myKernelPlm .p2align 3, 0x0 _Z8myKernelPlm: .quad _Z23__device_stub__myKernelPlm .size _Z8myKernelPlm, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z8myKernelPlm" .size .L__unnamed_1, 15 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z23__device_stub__myKernelPlm .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z8myKernelPlm .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
569
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code for sm_80 Function : _Z7WupdatePfS_S_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_CTAID.Y ; S2R R2, SR_TID.Y ; S2R R0, SR_CTAID.X ; S2R R5, SR_TID.X ; IMAD R3, R3, c[0x0][0x4], R2 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; IMAD R0, R0, c[0x0][0x0], R5 ; ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; @P0 EXIT ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD R0, R3, c[0x0][0x178], R0 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; LDG.E R9, [R2.64] ; IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; STG.E [R4.64], R9 ; LDG.E R7, [R6.64] ; STG.E [R2.64], R7 ; EXIT ; BRA 0x150; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z10WcalculatePfS_S_fii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R4, SR_CTAID.X ; UMOV UR5, 0x1 ; ULDC UR4, c[0x0][0x17c] ; S2R R3, SR_TID.X ; UIADD3 UR4, -UR5, UR4, URZ ; S2R R0, SR_CTAID.Y ; S2R R5, SR_TID.Y ; IMAD R4, R4, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R4, UR4, PT ; ULDC UR4, c[0x0][0x180] ; IMAD R3, R0, c[0x0][0x4], R5 ; ISETP.LT.OR P0, PT, R4, 0x1, P0 ; UIADD3 UR4, -UR5, UR4, URZ ; ISETP.LT.OR P0, PT, R3, 0x1, P0 ; ISETP.GE.OR P0, PT, R3, UR4, P0 ; @P0 EXIT ; MOV R2, c[0x0][0x17c] ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; IADD3 R6, RZ, -c[0x0][0x17c], RZ ; IMAD R0, R3.reuse, c[0x0][0x17c], R4 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD R7, R3, R2, c[0x0][0x17c] ; LEA R9, R6, R7, 0x1 ; IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; IADD3 R8, R4.reuse, R7, RZ ; IADD3 R10, R4, R9, RZ ; LDG.E R12, [R2.64+-0x4] ; IMAD.WIDE R8, R8, R5, c[0x0][0x168] ; LDG.E R15, [R2.64+0x4] ; IMAD.WIDE R6, R0, R5, c[0x0][0x160] ; LDG.E R9, [R8.64] ; IMAD.WIDE R10, R10, R5, c[0x0][0x168] ; LDG.E R6, [R6.64] ; LDG.E R13, [R2.64] ; LDG.E R11, [R10.64] ; HFMA2.MMA R17, -RZ, RZ, 2.25, 0 ; MOV R4, c[0x0][0x178] ; FFMA R4, R4, -R17, 2 ; FADD R12, R12, R15 ; FADD R12, R12, R9 ; FFMA R13, R4, R13, -R6 ; FADD R12, R12, R11 ; IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; FFMA R13, R12, c[0x0][0x178], R13 ; STG.E [R4.64], R13 ; EXIT ; BRA 0x2f0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000f3da0_00000000-6_c1cd406dc1b9b96fbc88807b4502b2b95987acdc.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z37__device_stub__Z10WcalculatePfS_S_fiiPfS_S_fii .type _Z37__device_stub__Z10WcalculatePfS_S_fiiPfS_S_fii, @function _Z37__device_stub__Z10WcalculatePfS_S_fiiPfS_S_fii: .LFB2082: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movss %xmm0, 20(%rsp) movl %ecx, 16(%rsp) movl %r8d, 12(%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 20(%rsp), %rax movq %rax, 136(%rsp) leaq 16(%rsp), %rax movq %rax, 144(%rsp) leaq 12(%rsp), %rax movq %rax, 152(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 168(%rsp), %rax subq %fs:40, %rax jne .L8 addq $184, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 200 pushq 56(%rsp) .cfi_def_cfa_offset 208 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z10WcalculatePfS_S_fii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z37__device_stub__Z10WcalculatePfS_S_fiiPfS_S_fii, .-_Z37__device_stub__Z10WcalculatePfS_S_fiiPfS_S_fii .globl _Z10WcalculatePfS_S_fii .type _Z10WcalculatePfS_S_fii, @function _Z10WcalculatePfS_S_fii: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z37__device_stub__Z10WcalculatePfS_S_fiiPfS_S_fii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z10WcalculatePfS_S_fii, .-_Z10WcalculatePfS_S_fii .globl _Z32__device_stub__Z7WupdatePfS_S_iiPfS_S_ii .type _Z32__device_stub__Z7WupdatePfS_S_iiPfS_S_ii, @function _Z32__device_stub__Z7WupdatePfS_S_iiPfS_S_ii: .LFB2084: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 136(%rsp), %rax subq %fs:40, %rax jne .L16 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7WupdatePfS_S_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z32__device_stub__Z7WupdatePfS_S_iiPfS_S_ii, .-_Z32__device_stub__Z7WupdatePfS_S_iiPfS_S_ii .globl _Z7WupdatePfS_S_ii .type _Z7WupdatePfS_S_ii, @function _Z7WupdatePfS_S_ii: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z32__device_stub__Z7WupdatePfS_S_iiPfS_S_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z7WupdatePfS_S_ii, .-_Z7WupdatePfS_S_ii .section .rodata.str1.1,"aMS",@progbits,1 .LC6: .string "CPU time = %lf s\n" .LC7: .string "w" .LC8: .string "u_cu.dat" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $120, %rsp .cfi_def_cfa_offset 176 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movl $161604, %edi call malloc@PLT movq %rax, %r13 movq %rax, 16(%rsp) movl $161604, %edi call malloc@PLT movq %rax, %r12 movq %rax, 24(%rsp) movl $161604, %edi call malloc@PLT movq %rax, %r15 movq $0, 56(%rsp) leaq 56(%rsp), %rdi movl $161604, %esi call cudaMalloc@PLT movq $0, 64(%rsp) leaq 64(%rsp), %rdi movl $161604, %esi call cudaMalloc@PLT movq $0, 72(%rsp) leaq 72(%rsp), %rdi movl $161604, %esi call cudaMalloc@PLT movq %r15, %rbp movl $0, %r14d .L21: pxor %xmm0, %xmm0 cvtsi2ssl %r14d, %xmm0 mulss .LC0(%rip), %xmm0 subss .LC1(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 mulsd %xmm0, %xmm0 movsd %xmm0, 8(%rsp) movl $0, %ebx .L20: pxor %xmm0, %xmm0 cvtsi2ssl %ebx, %xmm0 mulss .LC0(%rip), %xmm0 subss .LC1(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 mulsd %xmm0, %xmm0 addsd 8(%rsp), %xmm0 mulsd .LC2(%rip), %xmm0 call exp@PLT cvtsd2ss %xmm0, %xmm0 movss %xmm0, 0(%r13,%rbx,4) movss %xmm0, (%r12,%rbx,4) movl $0x00000000, 0(%rbp,%rbx,4) addq $1, %rbx cmpq $201, %rbx jne .L20 addl $1, %r14d addq $804, %r13 addq $804, %r12 addq $804, %rbp cmpl $201, %r14d jne .L21 movl $1, %ecx movl $161604, %edx movq 16(%rsp), %rsi movq 56(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $161604, %edx movq 24(%rsp), %rsi movq 64(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $161604, %edx movq %r15, %rsi movq 72(%rsp), %rdi call cudaMemcpy@PLT leaq 40(%rsp), %rdi call cudaEventCreate@PLT leaq 48(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 40(%rsp), %rdi call cudaEventRecord@PLT movl $7, 80(%rsp) movl $7, 84(%rsp) movl $1, 88(%rsp) movl $32, 92(%rsp) movl $32, 96(%rsp) movl $1, 100(%rsp) movl $1000, %ebx jmp .L24 .L31: movl $201, %r8d movl $201, %ecx movss .LC4(%rip), %xmm0 movq 72(%rsp), %rdx movq 64(%rsp), %rsi movq 56(%rsp), %rdi call _Z37__device_stub__Z10WcalculatePfS_S_fiiPfS_S_fii jmp .L22 .L23: subl $1, %ebx je .L30 .L24: movl 100(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 92(%rsp), %rdx movq 80(%rsp), %rdi movl 88(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L31 .L22: movl 100(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 92(%rsp), %rdx movq 80(%rsp), %rdi movl 88(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L23 movl $201, %r8d movl $201, %ecx movq 72(%rsp), %rdx movq 64(%rsp), %rsi movq 56(%rsp), %rdi call _Z32__device_stub__Z7WupdatePfS_S_iiPfS_S_ii jmp .L23 .L30: movl $2, %ecx movl $161604, %edx movq 72(%rsp), %rsi movq %r15, %rdi call cudaMemcpy@PLT movl $0, %esi movq 48(%rsp), %rdi call cudaEventRecord@PLT movq 48(%rsp), %rdi call cudaEventSynchronize@PLT leaq 36(%rsp), %rdi movq 48(%rsp), %rdx movq 40(%rsp), %rsi call cudaEventElapsedTime@PLT pxor %xmm0, %xmm0 cvtss2sd 36(%rsp), %xmm0 mulsd .LC5(%rip), %xmm0 leaq .LC6(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT leaq .LC7(%rip), %rsi leaq .LC8(%rip), %rdi call fopen@PLT movq %rax, %rbx movq %rax, %rcx movl $40401, %edx movl $4, %esi movq %r15, %rdi call fwrite@PLT movq %rbx, %rdi call fclose@PLT movq 16(%rsp), %rdi call free@PLT movq 24(%rsp), %rdi call free@PLT movq %r15, %rdi call free@PLT movq 64(%rsp), %rdi call cudaFree@PLT movq 64(%rsp), %rdi call cudaFree@PLT movq 72(%rsp), %rdi call cudaFree@PLT movq 104(%rsp), %rax subq %fs:40, %rax jne .L32 movl $0, %eax addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L32: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC9: .string "_Z7WupdatePfS_S_ii" .LC10: .string "_Z10WcalculatePfS_S_fii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC9(%rip), %rdx movq %rdx, %rcx leaq _Z7WupdatePfS_S_ii(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC10(%rip), %rdx movq %rdx, %rcx leaq _Z10WcalculatePfS_S_fii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1000593162 .align 4 .LC1: .long 1056964608 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC2: .long 0 .long -1064353792 .section .rodata.cst4 .align 4 .LC4: .long 1056629066 .section .rodata.cst8 .align 8 .LC5: .long -755914244 .long 1062232653 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z10WcalculatePfS_S_fii ; -- Begin function _Z10WcalculatePfS_S_fii .globl _Z10WcalculatePfS_S_fii .p2align 8 .type _Z10WcalculatePfS_S_fii,@function _Z10WcalculatePfS_S_fii: ; @_Z10WcalculatePfS_S_fii ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x34 s_load_b64 s[8:9], s[0:1], 0x1c v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s3, s2, 0xffff s_lshr_b32 s2, s2, 16 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4] s_add_i32 s2, s8, -1 s_add_i32 s3, s9, -1 v_cmp_gt_i32_e32 vcc_lo, s2, v0 v_cmp_lt_i32_e64 s4, 0, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cmp_gt_i32_e64 s2, s3, v1 v_cmp_lt_i32_e64 s3, 0, v1 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_b32 s2, s2, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, s4, s2 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_2 ; %bb.1: v_mad_u64_u32 v[2:3], null, v1, s8, v[0:1] s_clause 0x2 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[2:3], s[0:1], 0x10 s_load_b32 s0, s[0:1], 0x18 v_add_nc_u32_e32 v12, -1, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_add_nc_u32_e32 v4, 1, v2 v_ashrrev_i32_e32 v3, 31, v2 v_add_nc_u32_e32 v6, -1, v2 v_add_nc_u32_e32 v1, s8, v2 v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[8:9], 2, v[2:3] v_ashrrev_i32_e32 v7, 31, v6 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_mad_u64_u32 v[10:11], null, v12, s8, v[0:1] v_lshlrev_b64 v[3:4], 2, v[4:5] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_4) v_lshlrev_b64 v[5:6], 2, v[6:7] s_waitcnt lgkmcnt(0) v_add_co_u32 v12, vcc_lo, s6, v8 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v9, vcc_lo v_add_co_u32 v3, vcc_lo, s6, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo v_add_co_u32 v5, vcc_lo, s6, v5 v_ashrrev_i32_e32 v11, 31, v10 v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo v_lshlrev_b64 v[0:1], 2, v[1:2] v_add_co_u32 v14, vcc_lo, s4, v8 s_clause 0x1 global_load_b32 v4, v[3:4], off global_load_b32 v5, v[5:6], off v_lshlrev_b64 v[2:3], 2, v[10:11] v_add_co_ci_u32_e32 v15, vcc_lo, s5, v9, vcc_lo v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v2, vcc_lo, s6, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo s_clause 0x1 global_load_b32 v0, v[0:1], off global_load_b32 v1, v[12:13], off global_load_b32 v6, v[14:15], off global_load_b32 v2, v[2:3], off s_waitcnt vmcnt(4) v_add_f32_e32 v3, v4, v5 v_fma_f32 v4, s0, -4.0, 2.0 s_waitcnt vmcnt(3) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f32_e32 v0, v3, v0 s_waitcnt vmcnt(1) v_fma_f32 v3, v4, v1, -v6 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v0, v0, v2 v_fmac_f32_e32 v3, s0, v0 v_add_co_u32 v0, vcc_lo, s2, v8 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo global_store_b32 v[0:1], v3, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10WcalculatePfS_S_fii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 16 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z10WcalculatePfS_S_fii, .Lfunc_end0-_Z10WcalculatePfS_S_fii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 500 ; NumSgprs: 18 ; NumVgprs: 16 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 16 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .protected _Z7WupdatePfS_S_ii ; -- Begin function _Z7WupdatePfS_S_ii .globl _Z7WupdatePfS_S_ii .p2align 8 .type _Z7WupdatePfS_S_ii,@function _Z7WupdatePfS_S_ii: ; @_Z7WupdatePfS_S_ii ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b64 s[4:5], s[0:1], 0x18 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s3, s2, 0xffff s_lshr_b32 s2, s2, 16 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4] v_cmp_gt_i32_e32 vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i32_e64 s2, s5, v1 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB1_2 ; %bb.1: s_load_b128 s[8:11], s[0:1], 0x0 v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1] s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[0:1], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s10, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s8, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo global_load_b32 v6, v[2:3], off v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) global_store_b32 v[4:5], v6, off global_load_b32 v0, v[0:1], off s_waitcnt vmcnt(0) global_store_b32 v[2:3], v0, off .LBB1_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z7WupdatePfS_S_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z7WupdatePfS_S_ii, .Lfunc_end1-_Z7WupdatePfS_S_ii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 240 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10WcalculatePfS_S_fii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z10WcalculatePfS_S_fii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 16 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z7WupdatePfS_S_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z7WupdatePfS_S_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "c1cd406dc1b9b96fbc88807b4502b2b95987acdc.hip" .globl _Z25__device_stub__WcalculatePfS_S_fii # -- Begin function _Z25__device_stub__WcalculatePfS_S_fii .p2align 4, 0x90 .type _Z25__device_stub__WcalculatePfS_S_fii,@function _Z25__device_stub__WcalculatePfS_S_fii: # @_Z25__device_stub__WcalculatePfS_S_fii .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movss %xmm0, 20(%rsp) movl %ecx, 16(%rsp) movl %r8d, 12(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 20(%rsp), %rax movq %rax, 120(%rsp) leaq 16(%rsp), %rax movq %rax, 128(%rsp) leaq 12(%rsp), %rax movq %rax, 136(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z10WcalculatePfS_S_fii, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end0: .size _Z25__device_stub__WcalculatePfS_S_fii, .Lfunc_end0-_Z25__device_stub__WcalculatePfS_S_fii .cfi_endproc # -- End function .globl _Z22__device_stub__WupdatePfS_S_ii # -- Begin function _Z22__device_stub__WupdatePfS_S_ii .p2align 4, 0x90 .type _Z22__device_stub__WupdatePfS_S_ii,@function _Z22__device_stub__WupdatePfS_S_ii: # @_Z22__device_stub__WupdatePfS_S_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %rsp, %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7WupdatePfS_S_ii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end1: .size _Z22__device_stub__WupdatePfS_S_ii, .Lfunc_end1-_Z22__device_stub__WupdatePfS_S_ii .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI2_0: .long 0x3ba3d70a # float 0.00499999989 .LCPI2_1: .long 0xbf000000 # float -0.5 .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI2_2: .quad 0xc08f400000000000 # double -1000 .LCPI2_3: .quad 0x3f50624dd2f1a9fc # double 0.001 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $216, %rsp .cfi_def_cfa_offset 272 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $161604, %edi # imm = 0x27744 callq malloc movq %rax, %rbp movl $161604, %edi # imm = 0x27744 callq malloc movq %rax, %r15 movl $161604, %edi # imm = 0x27744 callq malloc movq %rax, %r12 movq $0, 32(%rsp) leaq 32(%rsp), %rdi movl $161604, %esi # imm = 0x27744 callq hipMalloc movq $0, 24(%rsp) leaq 24(%rsp), %rdi movl $161604, %esi # imm = 0x27744 callq hipMalloc movq $0, 16(%rsp) leaq 16(%rsp), %rdi movl $161604, %esi # imm = 0x27744 callq hipMalloc xorl %ebx, %ebx movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero movss .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero movsd .LCPI2_2(%rip), %xmm3 # xmm3 = mem[0],zero movq %rbp, %r14 movq %r15, 128(%rsp) # 8-byte Spill movq %r12, 120(%rsp) # 8-byte Spill .p2align 4, 0x90 .LBB2_1: # =>This Loop Header: Depth=1 # Child Loop BB2_2 Depth 2 xorps %xmm0, %xmm0 cvtsi2ss %ebx, %xmm0 mulss %xmm1, %xmm0 addss %xmm2, %xmm0 cvtss2sd %xmm0, %xmm0 mulsd %xmm0, %xmm0 movsd %xmm0, 40(%rsp) # 8-byte Spill xorl %r13d, %r13d .p2align 4, 0x90 .LBB2_2: # Parent Loop BB2_1 Depth=1 # => This Inner Loop Header: Depth=2 xorps %xmm0, %xmm0 cvtsi2ss %r13d, %xmm0 mulss %xmm1, %xmm0 addss %xmm2, %xmm0 cvtss2sd %xmm0, %xmm0 mulsd %xmm0, %xmm0 addsd 40(%rsp), %xmm0 # 8-byte Folded Reload mulsd %xmm3, %xmm0 callq exp movsd .LCPI2_2(%rip), %xmm3 # xmm3 = mem[0],zero movss .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, (%r14,%r13,4) movss %xmm0, (%r15,%r13,4) movl $0, (%r12,%r13,4) incq %r13 cmpq $201, %r13 jne .LBB2_2 # %bb.3: # in Loop: Header=BB2_1 Depth=1 incq %rbx addq $804, %r12 # imm = 0x324 addq $804, %r15 # imm = 0x324 addq $804, %r14 # imm = 0x324 cmpq $201, %rbx jne .LBB2_1 # %bb.4: movabsq $137438953504, %r12 # imm = 0x2000000020 movabsq $30064771079, %r13 # imm = 0x700000007 movq 32(%rsp), %rdi movl $161604, %edx # imm = 0x27744 movq %rbp, 40(%rsp) # 8-byte Spill movq %rbp, %rsi movl $1, %ecx callq hipMemcpy movq 24(%rsp), %rdi movl $161604, %edx # imm = 0x27744 movq 128(%rsp), %rsi # 8-byte Reload movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi movl $161604, %edx # imm = 0x27744 movq 120(%rsp), %rsi # 8-byte Reload movl $1, %ecx callq hipMemcpy leaq 136(%rsp), %rdi callq hipEventCreate leaq 48(%rsp), %rdi callq hipEventCreate movq 136(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movl $1000, %ebx # imm = 0x3E8 leaq 152(%rsp), %r14 leaq 144(%rsp), %r15 leaq 160(%rsp), %rbp jmp .LBB2_5 .p2align 4, 0x90 .LBB2_9: # in Loop: Header=BB2_5 Depth=1 decl %ebx je .LBB2_10 .LBB2_5: # =>This Inner Loop Header: Depth=1 movq %r13, %rdi movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_7 # %bb.6: # in Loop: Header=BB2_5 Depth=1 movq 32(%rsp), %rax movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movl $1056629066, 12(%rsp) # imm = 0x3EFAE14A movl $201, 8(%rsp) movl $201, 116(%rsp) leaq 104(%rsp), %rax movq %rax, 160(%rsp) leaq 96(%rsp), %rax movq %rax, 168(%rsp) leaq 88(%rsp), %rax movq %rax, 176(%rsp) leaq 12(%rsp), %rax movq %rax, 184(%rsp) leaq 8(%rsp), %rax movq %rax, 192(%rsp) leaq 116(%rsp), %rax movq %rax, 200(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi movq %r14, %rdx movq %r15, %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d movl $_Z10WcalculatePfS_S_fii, %edi movq %rbp, %r9 pushq 144(%rsp) .cfi_adjust_cfa_offset 8 pushq 160(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_7: # in Loop: Header=BB2_5 Depth=1 movq %r13, %rdi movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_9 # %bb.8: # in Loop: Header=BB2_5 Depth=1 movq 32(%rsp), %rax movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movl $201, 12(%rsp) movl $201, 8(%rsp) leaq 104(%rsp), %rax movq %rax, 160(%rsp) leaq 96(%rsp), %rax movq %rax, 168(%rsp) leaq 88(%rsp), %rax movq %rax, 176(%rsp) leaq 12(%rsp), %rax movq %rax, 184(%rsp) leaq 8(%rsp), %rax movq %rax, 192(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi movq %r14, %rdx movq %r15, %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d movl $_Z7WupdatePfS_S_ii, %edi movq %rbp, %r9 pushq 144(%rsp) .cfi_adjust_cfa_offset 8 pushq 160(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 jmp .LBB2_9 .LBB2_10: movq 16(%rsp), %rsi movl $161604, %edx # imm = 0x27744 movq 120(%rsp), %r14 # 8-byte Reload movq %r14, %rdi movl $2, %ecx callq hipMemcpy movq 48(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 48(%rsp), %rdi callq hipEventSynchronize movq 136(%rsp), %rsi movq 48(%rsp), %rdx leaq 160(%rsp), %rdi callq hipEventElapsedTime movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 mulsd .LCPI2_3(%rip), %xmm0 movl $.L.str, %edi movb $1, %al callq printf movl $.L.str.1, %edi movl $.L.str.2, %esi callq fopen movq %rax, %rbx movl $4, %esi movl $40401, %edx # imm = 0x9DD1 movq %r14, %rdi movq %rax, %rcx callq fwrite movq %rbx, %rdi callq fclose movq 40(%rsp), %rdi # 8-byte Reload callq free movq 128(%rsp), %rdi # 8-byte Reload callq free movq %r14, %rdi callq free movq 24(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree xorl %eax, %eax addq $216, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10WcalculatePfS_S_fii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7WupdatePfS_S_ii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z10WcalculatePfS_S_fii,@object # @_Z10WcalculatePfS_S_fii .section .rodata,"a",@progbits .globl _Z10WcalculatePfS_S_fii .p2align 3, 0x0 _Z10WcalculatePfS_S_fii: .quad _Z25__device_stub__WcalculatePfS_S_fii .size _Z10WcalculatePfS_S_fii, 8 .type _Z7WupdatePfS_S_ii,@object # @_Z7WupdatePfS_S_ii .globl _Z7WupdatePfS_S_ii .p2align 3, 0x0 _Z7WupdatePfS_S_ii: .quad _Z22__device_stub__WupdatePfS_S_ii .size _Z7WupdatePfS_S_ii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CPU time = %lf s\n" .size .L.str, 18 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "u_cu.dat" .size .L.str.1, 9 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "w" .size .L.str.2, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z10WcalculatePfS_S_fii" .size .L__unnamed_1, 24 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z7WupdatePfS_S_ii" .size .L__unnamed_2, 19 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__WcalculatePfS_S_fii .addrsig_sym _Z22__device_stub__WupdatePfS_S_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10WcalculatePfS_S_fii .addrsig_sym _Z7WupdatePfS_S_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
1,793
5,840
6,388
6,924
127
code for sm_80 Function : _Z12VecAddKernelPfS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R6, SR_TID.X ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; LDG.E R2, [R2.64] ; LDG.E R5, [R4.64] ; IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; FADD R9, R2, R5 ; STG.E [R6.64], R9 ; EXIT ; BRA 0xc0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000691bc_00000000-6_83388837acf9b037b551702bbe1db427e4b327ed.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2063: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2063: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z7VecFillPfiff .type _Z7VecFillPfiff, @function _Z7VecFillPfiff: .LFB2058: .cfi_startproc endbr64 testl %esi, %esi jle .L3 movslq %esi, %rsi movl $0, %eax .L5: pxor %xmm2, %xmm2 cvtsi2ssl %eax, %xmm2 mulss %xmm1, %xmm2 addss %xmm0, %xmm2 movss %xmm2, (%rdi,%rax,4) addq $1, %rax cmpq %rsi, %rax jne .L5 .L3: ret .cfi_endproc .LFE2058: .size _Z7VecFillPfiff, .-_Z7VecFillPfiff .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%s : \n" .LC1: .string "[%d] : %f\n" .text .globl _Z8VecPrintPKfiPKc .type _Z8VecPrintPKfiPKc, @function _Z8VecPrintPKfiPKc: .LFB2059: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $8, %rsp .cfi_def_cfa_offset 48 movq %rdi, %r12 movl %esi, %ebp leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT testl %ebp, %ebp jle .L7 movslq %ebp, %rbp movl $0, %ebx leaq .LC1(%rip), %r13 .L9: pxor %xmm0, %xmm0 cvtss2sd (%r12,%rbx,4), %xmm0 movl %ebx, %edx movq %r13, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $1, %rbx cmpq %rbp, %rbx jne .L9 .L7: addq $8, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2059: .size _Z8VecPrintPKfiPKc, .-_Z8VecPrintPKfiPKc .globl _Z36__device_stub__Z12VecAddKernelPfS_S_PfS_S_ .type _Z36__device_stub__Z12VecAddKernelPfS_S_PfS_S_, @function _Z36__device_stub__Z12VecAddKernelPfS_S_PfS_S_: .LFB2085: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L16 .L12: movq 120(%rsp), %rax subq %fs:40, %rax jne .L17 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L16: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z12VecAddKernelPfS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L12 .L17: call __stack_chk_fail@PLT .cfi_endproc .LFE2085: .size _Z36__device_stub__Z12VecAddKernelPfS_S_PfS_S_, .-_Z36__device_stub__Z12VecAddKernelPfS_S_PfS_S_ .globl _Z12VecAddKernelPfS_S_ .type _Z12VecAddKernelPfS_S_, @function _Z12VecAddKernelPfS_S_: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z12VecAddKernelPfS_S_PfS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _Z12VecAddKernelPfS_S_, .-_Z12VecAddKernelPfS_S_ .globl _Z6VecAddPKfS0_Pfi .type _Z6VecAddPKfS0_Pfi, @function _Z6VecAddPKfS0_Pfi: .LFB2057: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $64, %rsp .cfi_def_cfa_offset 112 movq %rdi, %r14 movq %rsi, %r13 movq %rdx, %r12 movl %ecx, %ebp movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movslq %ecx, %rbx salq $2, %rbx leaq 8(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 16(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 24(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movl $1, %ecx movq %rbx, %rdx movq %r14, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq %r13, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $1, 32(%rsp) movl $1, 36(%rsp) movl %ebp, 44(%rsp) movl $1, 48(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L24 .L21: movl $2, %ecx movq %rbx, %rdx movq 24(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L25 addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L24: .cfi_restore_state movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z36__device_stub__Z12VecAddKernelPfS_S_PfS_S_ jmp .L21 .L25: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z6VecAddPKfS0_Pfi, .-_Z6VecAddPKfS0_Pfi .section .rodata.str1.1 .LC4: .string "A" .LC7: .string "B" .LC8: .string "A+B" .text .globl main .type main, @function main: .LFB2060: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movl $40, %edi call malloc@PLT movq %rax, %rbp movl $40, %edi call malloc@PLT movq %rax, %rbx movl $40, %edi call malloc@PLT movq %rax, %r12 movss .LC2(%rip), %xmm1 pxor %xmm0, %xmm0 movl $10, %esi movq %rbp, %rdi call _Z7VecFillPfiff leaq .LC4(%rip), %rdx movl $10, %esi movq %rbp, %rdi call _Z8VecPrintPKfiPKc movss .LC5(%rip), %xmm1 movss .LC6(%rip), %xmm0 movl $10, %esi movq %rbx, %rdi call _Z7VecFillPfiff leaq .LC7(%rip), %rdx movl $10, %esi movq %rbx, %rdi call _Z8VecPrintPKfiPKc movl $10, %ecx movq %r12, %rdx movq %rbx, %rsi movq %rbp, %rdi call _Z6VecAddPKfS0_Pfi leaq .LC8(%rip), %rdx movl $10, %esi movq %r12, %rdi call _Z8VecPrintPKfiPKc movq %rbp, %rdi call free@PLT movq %rbx, %rdi call free@PLT movq %r12, %rdi call free@PLT movl $0, %eax popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size main, .-main .section .rodata.str1.1 .LC9: .string "_Z12VecAddKernelPfS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2088: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC9(%rip), %rdx movq %rdx, %rcx leaq _Z12VecAddKernelPfS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2088: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC2: .long 1065353216 .align 4 .LC5: .long -1090519040 .align 4 .LC6: .long 1092616192 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z12VecAddKernelPfS_S_ ; -- Begin function _Z12VecAddKernelPfS_S_ .globl _Z12VecAddKernelPfS_S_ .p2align 8 .type _Z12VecAddKernelPfS_S_,@function _Z12VecAddKernelPfS_S_: ; @_Z12VecAddKernelPfS_S_ ; %bb.0: s_load_b128 s[4:7], s[0:1], 0x0 v_lshlrev_b32_e32 v0, 2, v0 s_load_b64 s[0:1], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b32 v1, v0, s[4:5] global_load_b32 v2, v0, s[6:7] s_waitcnt vmcnt(0) v_add_f32_e32 v1, v1, v2 global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12VecAddKernelPfS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 8 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z12VecAddKernelPfS_S_, .Lfunc_end0-_Z12VecAddKernelPfS_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 72 ; NumSgprs: 8 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 8 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12VecAddKernelPfS_S_ .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z12VecAddKernelPfS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "83388837acf9b037b551702bbe1db427e4b327ed.hip" .globl _Z27__device_stub__VecAddKernelPfS_S_ # -- Begin function _Z27__device_stub__VecAddKernelPfS_S_ .p2align 4, 0x90 .type _Z27__device_stub__VecAddKernelPfS_S_,@function _Z27__device_stub__VecAddKernelPfS_S_: # @_Z27__device_stub__VecAddKernelPfS_S_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z12VecAddKernelPfS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z27__device_stub__VecAddKernelPfS_S_, .Lfunc_end0-_Z27__device_stub__VecAddKernelPfS_S_ .cfi_endproc # -- End function .globl _Z6VecAddPKfS0_Pfi # -- Begin function _Z6VecAddPKfS0_Pfi .p2align 4, 0x90 .type _Z6VecAddPKfS0_Pfi,@function _Z6VecAddPKfS0_Pfi: # @_Z6VecAddPKfS0_Pfi .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $128, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdx, %rbx movq %rsi, %r15 movq %rdi, %r12 movslq %ecx, %r13 leaq (,%r13,4), %r14 leaq 16(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 8(%rsp), %rdi movq %r14, %rsi callq hipMalloc movq %rsp, %rdi movq %r14, %rsi callq hipMalloc movq 16(%rsp), %rdi movq %r12, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi movq %r15, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movl %r13d, %edx movabsq $4294967296, %rdi # imm = 0x100000000 orq %rdi, %rdx orq $1, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 16(%rsp), %rax movq 8(%rsp), %rcx movq (%rsp), %rdx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movq %rdx, 72(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z12VecAddKernelPfS_S_, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq (%rsp), %rsi movq %rbx, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree addq $128, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z6VecAddPKfS0_Pfi, .Lfunc_end1-_Z6VecAddPKfS0_Pfi .cfi_endproc # -- End function .globl _Z7VecFillPfiff # -- Begin function _Z7VecFillPfiff .p2align 4, 0x90 .type _Z7VecFillPfiff,@function _Z7VecFillPfiff: # @_Z7VecFillPfiff .cfi_startproc # %bb.0: testl %esi, %esi jle .LBB2_3 # %bb.1: # %.lr.ph.preheader movl %esi, %eax xorl %ecx, %ecx .p2align 4, 0x90 .LBB2_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 xorps %xmm2, %xmm2 cvtsi2ss %ecx, %xmm2 mulss %xmm1, %xmm2 addss %xmm0, %xmm2 movss %xmm2, (%rdi,%rcx,4) incq %rcx cmpq %rcx, %rax jne .LBB2_2 .LBB2_3: # %._crit_edge retq .Lfunc_end2: .size _Z7VecFillPfiff, .Lfunc_end2-_Z7VecFillPfiff .cfi_endproc # -- End function .globl _Z8VecPrintPKfiPKc # -- Begin function _Z8VecPrintPKfiPKc .p2align 4, 0x90 .type _Z8VecPrintPKfiPKc,@function _Z8VecPrintPKfiPKc: # @_Z8VecPrintPKfiPKc .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 pushq %rax .cfi_def_cfa_offset 48 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %esi, %ebp movq %rdi, %rbx movl $.L.str, %edi movq %rdx, %rsi xorl %eax, %eax callq printf testl %ebp, %ebp jle .LBB3_3 # %bb.1: # %.lr.ph.preheader movl %ebp, %r15d xorl %r14d, %r14d .p2align 4, 0x90 .LBB3_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.1, %edi movl %r14d, %esi movb $1, %al callq printf incq %r14 cmpq %r14, %r15 jne .LBB3_2 .LBB3_3: # %._crit_edge addq $8, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size _Z8VecPrintPKfiPKc, .Lfunc_end3-_Z8VecPrintPKfiPKc .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI4_0: .long 0xbf000000 # float -0.5 .LCPI4_1: .long 0x41200000 # float 10 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 pushq %rax .cfi_def_cfa_offset 48 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $40, %edi callq malloc movq %rax, %rbx movl $40, %edi callq malloc movq %rax, %r14 movl $40, %edi callq malloc movq %rax, %r15 xorl %eax, %eax .p2align 4, 0x90 .LBB4_1: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 movss %xmm0, (%rbx,%rax,4) incq %rax cmpq $10, %rax jne .LBB4_1 # %bb.2: # %_Z7VecFillPfiff.exit xorl %r12d, %r12d movl $.L.str, %edi movl $.L.str.2, %esi xorl %eax, %eax callq printf .p2align 4, 0x90 .LBB4_3: # %.lr.ph.i20 # =>This Inner Loop Header: Depth=1 movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.1, %edi movl %r12d, %esi movb $1, %al callq printf incq %r12 cmpq $10, %r12 jne .LBB4_3 # %bb.4: # %.lr.ph.i24.preheader xorl %eax, %eax movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movss .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero .p2align 4, 0x90 .LBB4_5: # %.lr.ph.i24 # =>This Inner Loop Header: Depth=1 xorps %xmm2, %xmm2 cvtsi2ss %eax, %xmm2 mulss %xmm0, %xmm2 addss %xmm1, %xmm2 movss %xmm2, (%r14,%rax,4) incq %rax cmpq $10, %rax jne .LBB4_5 # %bb.6: # %_Z7VecFillPfiff.exit28 xorl %r12d, %r12d movl $.L.str, %edi movl $.L.str.3, %esi xorl %eax, %eax callq printf .p2align 4, 0x90 .LBB4_7: # %.lr.ph.i29 # =>This Inner Loop Header: Depth=1 movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.1, %edi movl %r12d, %esi movb $1, %al callq printf incq %r12 cmpq $10, %r12 jne .LBB4_7 # %bb.8: # %_Z8VecPrintPKfiPKc.exit33 movq %rbx, %rdi movq %r14, %rsi movq %r15, %rdx movl $10, %ecx callq _Z6VecAddPKfS0_Pfi xorl %r12d, %r12d movl $.L.str, %edi movl $.L.str.4, %esi xorl %eax, %eax callq printf .p2align 4, 0x90 .LBB4_9: # %.lr.ph.i34 # =>This Inner Loop Header: Depth=1 movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.1, %edi movl %r12d, %esi movb $1, %al callq printf incq %r12 cmpq $10, %r12 jne .LBB4_9 # %bb.10: # %_Z8VecPrintPKfiPKc.exit38 movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free xorl %eax, %eax addq $8, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end4: .size main, .Lfunc_end4-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB5_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB5_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12VecAddKernelPfS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end5: .size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB6_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB6_2: retq .Lfunc_end6: .size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor .cfi_endproc # -- End function .type _Z12VecAddKernelPfS_S_,@object # @_Z12VecAddKernelPfS_S_ .section .rodata,"a",@progbits .globl _Z12VecAddKernelPfS_S_ .p2align 3, 0x0 _Z12VecAddKernelPfS_S_: .quad _Z27__device_stub__VecAddKernelPfS_S_ .size _Z12VecAddKernelPfS_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%s : \n" .size .L.str, 7 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "[%d] : %f\n" .size .L.str.1, 11 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "A" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "B" .size .L.str.3, 2 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "A+B" .size .L.str.4, 4 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z12VecAddKernelPfS_S_" .size .L__unnamed_1, 23 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__VecAddKernelPfS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12VecAddKernelPfS_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
425
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code for sm_80 Function : _Z5helloPcPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_TID.X ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IADD3 R4, P0, R2.reuse, c[0x0][0x160], RZ ; IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; IADD3.X R5, RZ, c[0x0][0x164], RZ, P0, !PT ; LDG.E.U8 R3, [R2.64] ; LDG.E.U8 R0, [R4.64] ; IADD3 R7, R0, R3, RZ ; STG.E.U8 [R4.64], R7 ; EXIT ; BRA 0xc0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000e6bb8_00000000-6_9a5079f81c2fbaaa545f188c991de2cc51bdf361.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z26__device_stub__Z5helloPcPiPcPi .type _Z26__device_stub__Z5helloPcPiPcPi, @function _Z26__device_stub__Z5helloPcPiPcPi: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z5helloPcPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z26__device_stub__Z5helloPcPiPcPi, .-_Z26__device_stub__Z5helloPcPiPcPi .globl _Z5helloPcPi .type _Z5helloPcPi, @function _Z5helloPcPi: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z5helloPcPiPcPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z5helloPcPi, .-_Z5helloPcPi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%s" .LC1: .string "%s\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 subq $96, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax movl $1819043144, 81(%rsp) movl $2125676, 84(%rsp) movl $15, 48(%rsp) movl $10, 52(%rsp) movl $6, 56(%rsp) movl $0, 60(%rsp) movl $-11, 64(%rsp) movl $1, 68(%rsp) movl $0, 72(%rsp) leaq 81(%rsp), %rbx movq %rbx, %rdx leaq .LC0(%rip), %rsi movl $2, %edi call __printf_chk@PLT leaq 8(%rsp), %rdi movl $7, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $28, %esi call cudaMalloc@PLT movl $1, %ecx movl $7, %edx movq %rbx, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT leaq 48(%rsp), %rsi movl $1, %ecx movl $28, %edx movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $7, 24(%rsp) movl $1, 28(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $0, %r9d movl $0, %r8d movq 24(%rsp), %rdx movl $1, %ecx movq 36(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L15 .L12: leaq 81(%rsp), %rbx movl $2, %ecx movl $7, %edx movq 8(%rsp), %rsi movq %rbx, %rdi call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdx leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 88(%rsp), %rax subq %fs:40, %rax jne .L16 movl $0, %eax addq $96, %rsp .cfi_remember_state .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z26__device_stub__Z5helloPcPiPcPi jmp .L12 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC2: .string "_Z5helloPcPi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z5helloPcPi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z5helloPcPi ; -- Begin function _Z5helloPcPi .globl _Z5helloPcPi .p2align 8 .type _Z5helloPcPi,@function _Z5helloPcPi: ; @_Z5helloPcPi ; %bb.0: s_load_b128 s[0:3], s[0:1], 0x0 v_lshlrev_b32_e32 v1, 2, v0 s_waitcnt lgkmcnt(0) global_load_b32 v1, v1, s[2:3] global_load_u8 v2, v0, s[0:1] s_waitcnt vmcnt(0) v_add_nc_u16 v1, v2, v1 global_store_b8 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5helloPcPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 4 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z5helloPcPi, .Lfunc_end0-_Z5helloPcPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 64 ; NumSgprs: 4 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 4 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5helloPcPi .private_segment_fixed_size: 0 .sgpr_count: 4 .sgpr_spill_count: 0 .symbol: _Z5helloPcPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "9a5079f81c2fbaaa545f188c991de2cc51bdf361.hip" .globl _Z20__device_stub__helloPcPi # -- Begin function _Z20__device_stub__helloPcPi .p2align 4, 0x90 .type _Z20__device_stub__helloPcPi,@function _Z20__device_stub__helloPcPi: # @_Z20__device_stub__helloPcPi .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z5helloPcPi, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z20__device_stub__helloPcPi, .Lfunc_end0-_Z20__device_stub__helloPcPi .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI1_0: .long 15 # 0xf .long 10 # 0xa .long 6 # 0x6 .long 0 # 0x0 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $144, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -16 movl $1819043144, 9(%rsp) # imm = 0x6C6C6548 movw $8303, 13(%rsp) # imm = 0x206F movb $0, 15(%rsp) movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [15,10,6,0] movaps %xmm0, 112(%rsp) movabsq $8589934581, %rax # imm = 0x1FFFFFFF5 movq %rax, 128(%rsp) movl $0, 136(%rsp) leaq 9(%rsp), %rbx movl $.L.str, %edi movq %rbx, %rsi xorl %eax, %eax callq printf leaq 16(%rsp), %rdi movl $7, %esi callq hipMalloc leaq 24(%rsp), %rdi movl $28, %esi callq hipMalloc movq 16(%rsp), %rdi movl $7, %edx movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 24(%rsp), %rdi leaq 112(%rsp), %rsi movl $28, %edx movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 6(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 16(%rsp), %rax movq 24(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z5helloPcPi, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq 16(%rsp), %rsi leaq 9(%rsp), %rbx movl $7, %edx movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movq 16(%rsp), %rdi callq hipFree movq %rbx, %rdi callq puts@PLT xorl %eax, %eax addq $144, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5helloPcPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z5helloPcPi,@object # @_Z5helloPcPi .section .rodata,"a",@progbits .globl _Z5helloPcPi .p2align 3, 0x0 _Z5helloPcPi: .quad _Z20__device_stub__helloPcPi .size _Z5helloPcPi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%s" .size .L.str, 3 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z5helloPcPi" .size .L__unnamed_1, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z20__device_stub__helloPcPi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z5helloPcPi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
427
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1,686
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code for sm_80 Function : _Z10cuda_agentP4int2Ps .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; LDG.E.64 R2, [R2.64] ; HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; MOV R5, c[0x0][0x16c] ; ISETP.NE.AND P1, PT, R2.reuse, 0x3, PT ; ISETP.GT.AND P0, PT, R2, 0x2, PT ; ISETP.GE.AND P2, PT, R3, 0x2, PT ; SEL R7, RZ, 0x1, !P0 ; @!P1 SEL R7, R0, 0x2, !P2 ; STG.E.U16 [R4.64], R7 ; EXIT ; BRA 0xf0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z9cuda_initv .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; EXIT ; BRA 0x20; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000233ec_00000000-6_agent-4.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2031: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2031: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z27__device_stub__Z9cuda_initvv .type _Z27__device_stub__Z9cuda_initvv, @function _Z27__device_stub__Z9cuda_initvv: .LFB2053: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 72(%rsp), %rax subq %fs:40, %rax jne .L8 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z9cuda_initv(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2053: .size _Z27__device_stub__Z9cuda_initvv, .-_Z27__device_stub__Z9cuda_initvv .globl _Z9cuda_initv .type _Z9cuda_initv, @function _Z9cuda_initv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z9cuda_initvv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _Z9cuda_initv, .-_Z9cuda_initv .globl _Z10agent_initv .type _Z10agent_initv, @function _Z10agent_initv: .LFB2027: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movslq size(%rip), %rsi leaq d_action(%rip), %rdi call cudaMalloc@PLT movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 8(%rsp) movl $1, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L14 .L11: addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L14: .cfi_restore_state call _Z27__device_stub__Z9cuda_initvv jmp .L11 .cfi_endproc .LFE2027: .size _Z10agent_initv, .-_Z10agent_initv .globl _Z36__device_stub__Z10cuda_agentP4int2PsP4int2Ps .type _Z36__device_stub__Z10cuda_agentP4int2PsP4int2Ps, @function _Z36__device_stub__Z10cuda_agentP4int2PsP4int2Ps: .LFB2055: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L19 .L15: movq 104(%rsp), %rax subq %fs:40, %rax jne .L20 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z10cuda_agentP4int2Ps(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L15 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE2055: .size _Z36__device_stub__Z10cuda_agentP4int2PsP4int2Ps, .-_Z36__device_stub__Z10cuda_agentP4int2PsP4int2Ps .globl _Z10cuda_agentP4int2Ps .type _Z10cuda_agentP4int2Ps, @function _Z10cuda_agentP4int2Ps: .LFB2056: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z10cuda_agentP4int2PsP4int2Ps addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2056: .size _Z10cuda_agentP4int2Ps, .-_Z10cuda_agentP4int2Ps .globl _Z12agent_actionP4int2 .type _Z12agent_actionP4int2, @function _Z12agent_actionP4int2: .LFB2028: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 subq $32, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbx movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 8(%rsp) movl $1, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L26 .L24: movq d_action(%rip), %rax addq $32, %rsp .cfi_remember_state .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 ret .L26: .cfi_restore_state movq d_action(%rip), %rsi movq %rbx, %rdi call _Z36__device_stub__Z10cuda_agentP4int2PsP4int2Ps jmp .L24 .cfi_endproc .LFE2028: .size _Z12agent_actionP4int2, .-_Z12agent_actionP4int2 .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z10cuda_agentP4int2Ps" .LC1: .string "_Z9cuda_initv" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2058: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z10cuda_agentP4int2Ps(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z9cuda_initv(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .globl size .data .align 4 .type size, @object .size size, 4 size: .long 4 .globl d_action .bss .align 8 .type d_action, @object .size d_action, 8 d_action: .zero 8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9cuda_initv ; -- Begin function _Z9cuda_initv .globl _Z9cuda_initv .p2align 8 .type _Z9cuda_initv,@function _Z9cuda_initv: ; @_Z9cuda_initv ; %bb.0: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9cuda_initv .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 0 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 0 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 1 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9cuda_initv, .Lfunc_end0-_Z9cuda_initv ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 4 ; NumSgprs: 0 ; NumVgprs: 0 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 1 ; NumVGPRsForWavesPerEU: 1 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs ; -- Begin function _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs .globl _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs .p2align 8 .type _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs,@function _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs: ; @_Z10cuda_agentP15HIP_vector_typeIiLj2EEPs ; %bb.0: s_load_b128 s[0:3], s[0:1], 0x0 v_mov_b32_e32 v1, 0 s_waitcnt lgkmcnt(0) s_load_b64 s[0:1], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_cmp_gt_i32 s0, 2 s_cselect_b32 s4, -1, 0 s_cmp_eq_u32 s1, 0 v_cndmask_b32_e64 v0, 0, 1, s4 s_cselect_b32 vcc_lo, -1, 0 s_cmp_lt_i32 s1, 2 s_cselect_b32 s1, 1, 2 s_delay_alu instid0(VALU_DEP_1) v_cndmask_b32_e32 v0, 0, v0, vcc_lo s_cmp_eq_u32 s0, 3 s_cselect_b32 s0, -1, 0 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_cndmask_b32_e64 v0, v0, s1, s0 global_store_b16 v1, v0, s[2:3] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 5 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs, .Lfunc_end1-_Z10cuda_agentP15HIP_vector_typeIiLj2EEPs ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 108 ; NumSgprs: 7 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 7 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: [] .group_segment_fixed_size: 0 .kernarg_segment_align: 4 .kernarg_segment_size: 0 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9cuda_initv .private_segment_fixed_size: 0 .sgpr_count: 0 .sgpr_spill_count: 0 .symbol: _Z9cuda_initv.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs .private_segment_fixed_size: 0 .sgpr_count: 7 .sgpr_spill_count: 0 .symbol: _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "agent-4.hip" .globl _Z24__device_stub__cuda_initv # -- Begin function _Z24__device_stub__cuda_initv .p2align 4, 0x90 .type _Z24__device_stub__cuda_initv,@function _Z24__device_stub__cuda_initv: # @_Z24__device_stub__cuda_initv .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z9cuda_initv, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end0: .size _Z24__device_stub__cuda_initv, .Lfunc_end0-_Z24__device_stub__cuda_initv .cfi_endproc # -- End function .globl _Z25__device_stub__cuda_agentP15HIP_vector_typeIiLj2EEPs # -- Begin function _Z25__device_stub__cuda_agentP15HIP_vector_typeIiLj2EEPs .p2align 4, 0x90 .type _Z25__device_stub__cuda_agentP15HIP_vector_typeIiLj2EEPs,@function _Z25__device_stub__cuda_agentP15HIP_vector_typeIiLj2EEPs: # @_Z25__device_stub__cuda_agentP15HIP_vector_typeIiLj2EEPs .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z10cuda_agentP15HIP_vector_typeIiLj2EEPs, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end1: .size _Z25__device_stub__cuda_agentP15HIP_vector_typeIiLj2EEPs, .Lfunc_end1-_Z25__device_stub__cuda_agentP15HIP_vector_typeIiLj2EEPs .cfi_endproc # -- End function .globl _Z10agent_initv # -- Begin function _Z10agent_initv .p2align 4, 0x90 .type _Z10agent_initv,@function _Z10agent_initv: # @_Z10agent_initv .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 movslq size(%rip), %rsi movl $d_action, %edi callq hipMalloc movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax je .LBB2_1 # %bb.2: addq $56, %rsp .cfi_def_cfa_offset 8 retq .LBB2_1: .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z9cuda_initv, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 addq $56, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z10agent_initv, .Lfunc_end2-_Z10agent_initv .cfi_endproc # -- End function .globl _Z12agent_actionP15HIP_vector_typeIiLj2EE # -- Begin function _Z12agent_actionP15HIP_vector_typeIiLj2EE .p2align 4, 0x90 .type _Z12agent_actionP15HIP_vector_typeIiLj2EE,@function _Z12agent_actionP15HIP_vector_typeIiLj2EE: # @_Z12agent_actionP15HIP_vector_typeIiLj2EE .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $80, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -16 movq %rdi, %rbx movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_2 # %bb.1: movq d_action(%rip), %rax movq %rbx, 56(%rsp) movq %rax, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z10cuda_agentP15HIP_vector_typeIiLj2EEPs, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_2: movq d_action(%rip), %rax addq $80, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size _Z12agent_actionP15HIP_vector_typeIiLj2EE, .Lfunc_end3-_Z12agent_actionP15HIP_vector_typeIiLj2EE .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9cuda_initv, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10cuda_agentP15HIP_vector_typeIiLj2EEPs, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type d_action,@object # @d_action .bss .globl d_action .p2align 3, 0x0 d_action: .quad 0 .size d_action, 8 .type size,@object # @size .data .globl size .p2align 2, 0x0 size: .long 4 # 0x4 .size size, 4 .type _Z9cuda_initv,@object # @_Z9cuda_initv .section .rodata,"a",@progbits .globl _Z9cuda_initv .p2align 3, 0x0 _Z9cuda_initv: .quad _Z24__device_stub__cuda_initv .size _Z9cuda_initv, 8 .type _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs,@object # @_Z10cuda_agentP15HIP_vector_typeIiLj2EEPs .globl _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs .p2align 3, 0x0 _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs: .quad _Z25__device_stub__cuda_agentP15HIP_vector_typeIiLj2EEPs .size _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z9cuda_initv" .size .L__unnamed_1, 14 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z10cuda_agentP15HIP_vector_typeIiLj2EEPs" .size .L__unnamed_2, 42 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__cuda_initv .addrsig_sym _Z25__device_stub__cuda_agentP15HIP_vector_typeIiLj2EEPs .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym d_action .addrsig_sym _Z9cuda_initv .addrsig_sym _Z10cuda_agentP15HIP_vector_typeIiLj2EEPs .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
680
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code for sm_80 Function : _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; HFMA2.MMA R3, -RZ, RZ, 0, 1.1920928955078125e-07 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R5, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R5 ; IMAD.WIDE R4, R0, R3, c[0x0][0x178] ; IMAD.WIDE R6, R0.reuse, R3.reuse, c[0x0][0x188] ; LDG.E.U16 R4, [R4.64] ; IMAD.WIDE R8, R0.reuse, R3.reuse, c[0x0][0x170] ; LDG.E.U16 R7, [R6.64] ; IMAD.WIDE R10, R0, R3, c[0x0][0x180] ; LDG.E.U16 R8, [R8.64] ; LDG.E.U16 R11, [R10.64] ; BAR.SYNC.DEFER_BLOCKING 0x0 ; CS2R.32 R2, SR_CLOCKLO ; PRMT R5, R8, 0x5410, R11 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; PRMT R4, R4, 0x5410, R7 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R5, R5, R4, R5 ; HFMA2.MMA R5, R5, R4, R5 ; HFMA2 R4, R5, R4, R5 ; CS2R.32 R11, SR_CLOCKLO ; MOV R7, 0x4 ; HADD2 R10, R4.H1_H1, R4.H0_H0 ; IMAD.WIDE R8, R0, R3, c[0x0][0x190] ; IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; STG.E [R4.64], R2 ; STG.E [R6.64], R11 ; STG.E.U16 [R8.64], R10 ; EXIT ; BRA 0x41d0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000fc100_00000000-6_0db270edf56855e2573862691fbbd10252360fec.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2435: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2435: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1 .LC0: .string "GPUassert: %s %s %d\n" .section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat .weak _Z9gpuAssert9cudaErrorPKcib .type _Z9gpuAssert9cudaErrorPKcib, @function _Z9gpuAssert9cudaErrorPKcib: .LFB2431: .cfi_startproc endbr64 testl %edi, %edi jne .L9 ret .L9: pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $8, %rsp .cfi_def_cfa_offset 48 movl %edi, %ebx movq %rsi, %r13 movl %edx, %r12d movl %ecx, %ebp call cudaGetErrorString@PLT movq %rax, %rcx movl %r12d, %r9d movq %r13, %r8 leaq .LC0(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT testb %bpl, %bpl jne .L10 addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L10: .cfi_restore_state movl %ebx, %edi call exit@PLT .cfi_endproc .LFE2431: .size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib .text .globl _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_ .type _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_, @function _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_: .LFB2457: .cfi_startproc endbr64 subq $200, %rsp .cfi_def_cfa_offset 208 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) movq %rdx, 40(%rsp) movq %rcx, 32(%rsp) movq %r8, 24(%rsp) movq %r9, 16(%rsp) movq 208(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) leaq 32(%rsp), %rax movq %rax, 152(%rsp) leaq 24(%rsp), %rax movq %rax, 160(%rsp) leaq 16(%rsp), %rax movq %rax, 168(%rsp) leaq 8(%rsp), %rax movq %rax, 176(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 184(%rsp), %rax subq %fs:40, %rax jne .L16 addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 216 pushq 72(%rsp) .cfi_def_cfa_offset 224 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 208 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2457: .size _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_, .-_Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_ .globl _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_ .type _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, @function _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_: .LFB2458: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 pushq 24(%rsp) .cfi_def_cfa_offset 32 call _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_ addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2458: .size _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, .-_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_ .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "/home/ubuntu/Datasets/Stack_v2_cuda-hip/train/0db270edf56855e2573862691fbbd10252360fec.cu" .align 8 .LC3: .string "FLOP per SM = %f (flop/clk/SM)\n" .section .rodata.str1.1,"aMS",@progbits,1 .LC4: .string "Total Clk number = %u \n" .text .globl main .type main, @function main: .LFB2432: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $88, %rsp .cfi_def_cfa_offset 144 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $4096, %edi call malloc@PLT movq %rax, %r12 movl $4096, %edi call malloc@PLT movq %rax, %r13 movl $2048, %edi call malloc@PLT movq %rax, %rbp movl $2048, %edi call malloc@PLT movq %rax, %rbx movl $2048, %edi call malloc@PLT movq %rax, %r14 movl $0, %esi movl $32767, %edi movl $126, %r8d jmp .L35 .L22: cmpl $1199566847, %eax jbe .L24 movl %r10d, %ecx orw $31743, %cx jmp .L25 .L24: cmpl $947912703, %eax jbe .L26 movl %eax, %r9d sall $19, %r9d leal -939524096(%rax), %ecx shrl $13, %ecx orl %r10d, %ecx .L27: cmpl $-2147483648, %r9d jbe .L49 .L25: addl $1, %ecx .L29: movw %cx, 0(%rbp,%rsi,2) cmpl $1199566847, %eax ja .L41 .L40: cmpl $947912703, %eax jbe .L32 movl %eax, %r9d sall $19, %r9d subl $939524096, %eax shrl $13, %eax orl %r10d, %eax .L33: cmpl $-2147483648, %r9d jbe .L50 .L31: addl $1, %eax .L34: movw %ax, (%rbx,%rsi,2) addq $1, %rsi cmpq $1024, %rsi je .L51 .L35: movl %esi, %eax pxor %xmm2, %xmm2 cvtsi2ssq %rax, %xmm2 movd %xmm2, %edx movl %edx, %eax andl $2147483647, %eax movl %edx, %r10d shrl $16, %r10d andl $32768, %r10d cmpl $2139095039, %eax jbe .L22 movl %r10d, %edx orb $124, %dh cmpl $2139095040, %eax cmovne %edi, %edx .L23: movw %dx, 0(%rbp,%rsi,2) cmpl $2139095039, %eax jbe .L30 orl $31744, %r10d cmpl $2139095040, %eax cmovne %edi, %r10d .L30: movl %r10d, %eax jmp .L34 .L26: cmpl $855638016, %eax jbe .L44 movl %eax, %r15d shrl $23, %r15d movl %edx, %r11d andl $8388607, %r11d orl $8388608, %r11d leal -94(%r15), %ecx movl %r11d, %r9d sall %cl, %r9d movl %r8d, %ecx subl %r15d, %ecx shrl %cl, %r11d movl %r11d, %ecx orl %r10d, %ecx jmp .L27 .L49: jne .L28 testb $1, %cl je .L29 jmp .L25 .L41: movl %r10d, %eax orw $31743, %ax jmp .L31 .L32: cmpl $855638016, %eax jbe .L30 shrl $23, %eax movl %eax, %r11d movl %edx, %eax andl $8388607, %eax orl $8388608, %eax leal -94(%r11), %ecx movl %eax, %r9d sall %cl, %r9d movl %r8d, %ecx subl %r11d, %ecx shrl %cl, %eax orl %r10d, %eax jmp .L33 .L50: jne .L34 testb $1, %al je .L34 jmp .L31 .L51: leaq 8(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT movl %eax, %edi movl $1, %ecx movl $74, %edx leaq .LC1(%rip), %r15 movq %r15, %rsi call _Z9gpuAssert9cudaErrorPKcib leaq 16(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT movl %eax, %edi movl $1, %ecx movl $75, %edx movq %r15, %rsi call _Z9gpuAssert9cudaErrorPKcib leaq 24(%rsp), %rdi movl $2048, %esi call cudaMalloc@PLT movl %eax, %edi movl $1, %ecx movl $76, %edx movq %r15, %rsi call _Z9gpuAssert9cudaErrorPKcib leaq 32(%rsp), %rdi movl $2048, %esi call cudaMalloc@PLT movl %eax, %edi movl $1, %ecx movl $77, %edx movq %r15, %rsi call _Z9gpuAssert9cudaErrorPKcib leaq 40(%rsp), %rdi movl $2048, %esi call cudaMalloc@PLT movl %eax, %edi movl $1, %ecx movl $78, %edx movq %r15, %rsi call _Z9gpuAssert9cudaErrorPKcib movl $1, %ecx movl $2048, %edx movq %rbp, %rsi movq 24(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %edi movl $1, %ecx movl $80, %edx movq %r15, %rsi call _Z9gpuAssert9cudaErrorPKcib movl $1, %ecx movl $2048, %edx movq %rbx, %rsi movq 32(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %edi movl $1, %ecx movl $81, %edx movq %r15, %rsi call _Z9gpuAssert9cudaErrorPKcib movl $1024, 60(%rsp) movl $1, 64(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $0, %r9d movl $0, %r8d movq 60(%rsp), %rdx movl $1, %ecx movq 48(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L52 .L36: call cudaPeekAtLastError@PLT movl %eax, %edi movl $1, %ecx movl $84, %edx leaq .LC1(%rip), %rbx movq %rbx, %rsi call _Z9gpuAssert9cudaErrorPKcib movl $2, %ecx movl $4096, %edx movq 8(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT movl %eax, %edi movl $1, %ecx movl $86, %edx movq %rbx, %rsi call _Z9gpuAssert9cudaErrorPKcib movl $2, %ecx movl $4096, %edx movq 16(%rsp), %rsi movq %r13, %rdi call cudaMemcpy@PLT movl %eax, %edi movl $1, %ecx movl $87, %edx movq %rbx, %rsi call _Z9gpuAssert9cudaErrorPKcib movl $2, %ecx movl $2048, %edx movq 40(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT movl %eax, %edi movl $1, %ecx movl $88, %edx movq %rbx, %rsi call _Z9gpuAssert9cudaErrorPKcib movl 0(%r13), %eax subl (%r12), %eax pxor %xmm1, %xmm1 cvtsi2ssq %rax, %xmm1 movss .LC2(%rip), %xmm0 divss %xmm1, %xmm0 cvtss2sd %xmm0, %xmm0 leaq .LC3(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl 0(%r13), %edx subl (%r12), %edx leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L53 movl $0, %eax addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L52: .cfi_restore_state movq 32(%rsp), %rcx movq 24(%rsp), %rdx subq $8, %rsp .cfi_def_cfa_offset 152 pushq 48(%rsp) .cfi_def_cfa_offset 160 movq %rcx, %r9 movq %rdx, %r8 movq 32(%rsp), %rsi movq 24(%rsp), %rdi call _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_ addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L36 .L44: movl %r10d, %edx jmp .L23 .L28: movw %cx, 0(%rbp,%rsi,2) jmp .L40 .L53: call __stack_chk_fail@PLT .cfi_endproc .LFE2432: .size main, .-main .section .rodata.str1.8 .align 8 .LC5: .string "_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2460: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2460: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC2: .long 1249902592 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_ ; -- Begin function _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_ .globl _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_ .p2align 8 .type _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_,@function _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_: ; @_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_ ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x44 s_load_b256 s[4:11], s[0:1], 0x10 s_movk_i32 s3, 0x400 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], 1, v[1:2] v_add_co_u32 v6, vcc_lo, s6, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo v_add_co_u32 v8, vcc_lo, s4, v4 v_add_co_ci_u32_e32 v9, vcc_lo, s5, v5, vcc_lo global_load_u16 v3, v[6:7], off global_load_u16 v0, v[8:9], off v_add_co_u32 v6, vcc_lo, s10, v4 v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo v_add_co_u32 v4, vcc_lo, s8, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo global_load_d16_hi_b16 v3, v[6:7], off global_load_d16_hi_b16 v0, v[4:5], off ;;#ASMSTART bar.sync 0; ;;#ASMEND ;;#ASMSTART mov.u32 s2, %clock; ;;#ASMEND .LBB0_1: ; =>This Inner Loop Header: Depth=1 s_waitcnt vmcnt(0) v_pk_fma_f16 v0, v0, v3, v0 s_add_i32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s3, 0 s_cbranch_scc0 .LBB0_1 ; %bb.2: s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x30 v_lshlrev_b64 v[3:4], 2, v[1:2] v_lshrrev_b32_e32 v5, 16, v0 v_lshlrev_b64 v[1:2], 1, v[1:2] ;;#ASMSTART bar.sync 0; ;;#ASMEND ;;#ASMSTART mov.u32 s3, %clock; ;;#ASMEND v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3 v_add_f16_e32 v9, v5, v0 s_waitcnt lgkmcnt(0) v_add_co_u32 v5, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo v_add_co_u32 v3, vcc_lo, s6, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v1 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo global_store_b32 v[5:6], v7, off global_store_b32 v[3:4], v8, off global_store_b16 v[0:1], v9, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 312 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, .Lfunc_end0-_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 384 ; NumSgprs: 18 ; NumVgprs: 10 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 10 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .offset: 56 .size: 4 .value_kind: hidden_block_count_x - .offset: 60 .size: 4 .value_kind: hidden_block_count_y - .offset: 64 .size: 4 .value_kind: hidden_block_count_z - .offset: 68 .size: 2 .value_kind: hidden_group_size_x - .offset: 70 .size: 2 .value_kind: hidden_group_size_y - .offset: 72 .size: 2 .value_kind: hidden_group_size_z - .offset: 74 .size: 2 .value_kind: hidden_remainder_x - .offset: 76 .size: 2 .value_kind: hidden_remainder_y - .offset: 78 .size: 2 .value_kind: hidden_remainder_z - .offset: 96 .size: 8 .value_kind: hidden_global_offset_x - .offset: 104 .size: 8 .value_kind: hidden_global_offset_y - .offset: 112 .size: 8 .value_kind: hidden_global_offset_z - .offset: 120 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 312 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "0db270edf56855e2573862691fbbd10252360fec.hip" .globl _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_ # -- Begin function _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_ .p2align 4, 0x90 .type _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_,@function _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_: # @_Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_ .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movq %r9, 48(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 160(%rsp), %rax movq %rax, 144(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end0: .size _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_, .Lfunc_end0-_Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_ .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI1_0: .long 0x4a800000 # float 4194304 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $200, %rsp .cfi_def_cfa_offset 256 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $4096, %edi # imm = 0x1000 callq malloc movq %rax, %rbx movl $4096, %edi # imm = 0x1000 callq malloc movq %rax, %r14 movl $2048, %edi # imm = 0x800 callq malloc movq %rax, %r13 movl $2048, %edi # imm = 0x800 callq malloc movq %rax, %r12 movl $2048, %edi # imm = 0x800 callq malloc movq %rax, %r15 xorl %ebp, %ebp .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl %ebp, %eax xorps %xmm0, %xmm0 cvtsi2ss %rax, %xmm0 callq __truncsfhf2@PLT pextrw $0, %xmm0, %eax movw %ax, (%r13,%rbp,2) movw %ax, (%r12,%rbp,2) incq %rbp cmpq $1024, %rbp # imm = 0x400 jne .LBB1_1 # %bb.2: leaq 32(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc testl %eax, %eax jne .LBB1_3 # %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit leaq 24(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc testl %eax, %eax jne .LBB1_6 # %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit20 leaq 16(%rsp), %rdi movl $2048, %esi # imm = 0x800 callq hipMalloc testl %eax, %eax jne .LBB1_8 # %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit22 leaq 8(%rsp), %rdi movl $2048, %esi # imm = 0x800 callq hipMalloc testl %eax, %eax jne .LBB1_10 # %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit24 movq %rsp, %rdi movl $2048, %esi # imm = 0x800 callq hipMalloc testl %eax, %eax jne .LBB1_12 # %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit26 movq 16(%rsp), %rdi movl $2048, %edx # imm = 0x800 movq %r13, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax jne .LBB1_14 # %bb.15: # %_Z9gpuAssert10hipError_tPKcib.exit28 movq 8(%rsp), %rdi movl $2048, %edx # imm = 0x800 movq %r12, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax jne .LBB1_16 # %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit30 movabsq $4294967297, %rdi # imm = 0x100000001 leaq 1023(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_19 # %bb.18: movq 32(%rsp), %rax movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi movq %rax, 136(%rsp) movq %rcx, 128(%rsp) movq %rdx, 120(%rsp) movq %rsi, 112(%rsp) movq %rdx, 104(%rsp) movq %rsi, 96(%rsp) movq %rdi, 88(%rsp) leaq 136(%rsp), %rax movq %rax, 144(%rsp) leaq 128(%rsp), %rax movq %rax, 152(%rsp) leaq 120(%rsp), %rax movq %rax, 160(%rsp) leaq 112(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 96(%rsp), %rax movq %rax, 184(%rsp) leaq 88(%rsp), %rax movq %rax, 192(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, %edi pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_19: callq hipPeekAtLastError testl %eax, %eax jne .LBB1_20 # %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit32 movq 32(%rsp), %rsi movl $4096, %edx # imm = 0x1000 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax jne .LBB1_22 # %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit34 movq 24(%rsp), %rsi movl $4096, %edx # imm = 0x1000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax jne .LBB1_24 # %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit36 movq (%rsp), %rsi movl $2048, %edx # imm = 0x800 movq %r15, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax jne .LBB1_26 # %bb.27: # %_Z9gpuAssert10hipError_tPKcib.exit38 movl (%r14), %eax subl (%rbx), %eax cvtsi2ss %rax, %xmm0 movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero divss %xmm0, %xmm1 xorps %xmm0, %xmm0 cvtss2sd %xmm1, %xmm0 movl $.L.str.1, %edi movb $1, %al callq printf movl (%r14), %esi subl (%rbx), %esi movl $.L.str.2, %edi xorl %eax, %eax callq printf xorl %eax, %eax addq $200, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_3: .cfi_def_cfa_offset 256 movq stderr(%rip), %rbx movl %eax, %edi movl %eax, %ebp callq hipGetErrorString movl $.L.str.3, %esi movl $.L.str, %ecx movq %rbx, %rdi movq %rax, %rdx movl $75, %r8d jmp .LBB1_4 .LBB1_6: movq stderr(%rip), %rbx movl %eax, %edi movl %eax, %ebp callq hipGetErrorString movl $.L.str.3, %esi movl $.L.str, %ecx movq %rbx, %rdi movq %rax, %rdx movl $76, %r8d jmp .LBB1_4 .LBB1_8: movq stderr(%rip), %rbx movl %eax, %edi movl %eax, %ebp callq hipGetErrorString movl $.L.str.3, %esi movl $.L.str, %ecx movq %rbx, %rdi movq %rax, %rdx movl $77, %r8d jmp .LBB1_4 .LBB1_10: movq stderr(%rip), %rbx movl %eax, %edi movl %eax, %ebp callq hipGetErrorString movl $.L.str.3, %esi movl $.L.str, %ecx movq %rbx, %rdi movq %rax, %rdx movl $78, %r8d jmp .LBB1_4 .LBB1_12: movq stderr(%rip), %rbx movl %eax, %edi movl %eax, %ebp callq hipGetErrorString movl $.L.str.3, %esi movl $.L.str, %ecx movq %rbx, %rdi movq %rax, %rdx movl $79, %r8d jmp .LBB1_4 .LBB1_14: movq stderr(%rip), %rbx movl %eax, %edi movl %eax, %ebp callq hipGetErrorString movl $.L.str.3, %esi movl $.L.str, %ecx movq %rbx, %rdi movq %rax, %rdx movl $81, %r8d jmp .LBB1_4 .LBB1_16: movq stderr(%rip), %rbx movl %eax, %edi movl %eax, %ebp callq hipGetErrorString movl $.L.str.3, %esi movl $.L.str, %ecx movq %rbx, %rdi movq %rax, %rdx movl $82, %r8d jmp .LBB1_4 .LBB1_20: movq stderr(%rip), %rbx movl %eax, %edi movl %eax, %ebp callq hipGetErrorString movl $.L.str.3, %esi movl $.L.str, %ecx movq %rbx, %rdi movq %rax, %rdx movl $85, %r8d jmp .LBB1_4 .LBB1_22: movq stderr(%rip), %rbx movl %eax, %edi movl %eax, %ebp callq hipGetErrorString movl $.L.str.3, %esi movl $.L.str, %ecx movq %rbx, %rdi movq %rax, %rdx movl $87, %r8d jmp .LBB1_4 .LBB1_24: movq stderr(%rip), %rbx movl %eax, %edi movl %eax, %ebp callq hipGetErrorString movl $.L.str.3, %esi movl $.L.str, %ecx movq %rbx, %rdi movq %rax, %rdx movl $88, %r8d jmp .LBB1_4 .LBB1_26: movq stderr(%rip), %rbx movl %eax, %edi movl %eax, %ebp callq hipGetErrorString movl $.L.str.3, %esi movl $.L.str, %ecx movq %rbx, %rdi movq %rax, %rdx movl $89, %r8d .LBB1_4: xorl %eax, %eax callq fprintf movl %ebp, %edi callq exit .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_,@object # @_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_ .section .rodata,"a",@progbits .globl _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_ .p2align 3, 0x0 _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_: .quad _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_ .size _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "/home/ubuntu/Datasets/Stack_v2_cuda-hip-as/0db270edf56855e2573862691fbbd10252360fec.hip" .size .L.str, 88 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "FLOP per SM = %f (flop/clk/SM)\n" .size .L.str.1, 32 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Total Clk number = %u \n" .size .L.str.2, 24 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "GPUassert: %s %s %d\n" .size .L.str.3, 21 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_" .size .L__unnamed_1, 37 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z3addPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R6, SR_TID.X ; S2R R3, SR_CTAID.X ; IMAD R6, R3, c[0x0][0x0], R6 ; ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; @P0 EXIT ; IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R6, R7, c[0x0][0x170] ; LDG.E R9, [R2.64] ; IMAD.WIDE R4, R6, R7, c[0x0][0x160] ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R9, R8, R10 ; IADD3 R9, R8, 0x1, RZ ; STG.E [R2.64], R9 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R9, R8, R10 ; IADD3 R11, R8, 0x1, RZ ; STG.E [R2.64], R11 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R11, R8, R10 ; IADD3 R13, R8, 0x1, RZ ; STG.E [R2.64], R13 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R13, R8, R9 ; IADD3 R9, R8, 0x1, RZ ; STG.E [R2.64], R9 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R9, R8, R10 ; IADD3 R11, R8, 0x1, RZ ; STG.E [R2.64], R11 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R11, R8, R10 ; IADD3 R13, R8, 0x1, RZ ; STG.E [R2.64], R13 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R13, R8, R9 ; IADD3 R9, R8, 0x1, RZ ; STG.E [R2.64], R9 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R9, R8, R10 ; IADD3 R11, R8, 0x1, RZ ; STG.E [R2.64], R11 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R11, R8, R10 ; IADD3 R13, R8, 0x1, RZ ; STG.E [R2.64], R13 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R13, R8, R9 ; IADD3 R9, R8, 0x1, RZ ; STG.E [R2.64], R9 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R9, R8, R10 ; IADD3 R11, R8, 0x1, RZ ; STG.E [R2.64], R11 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R11, R8, R10 ; IADD3 R13, R8, 0x1, RZ ; STG.E [R2.64], R13 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R13, R8, R9 ; IADD3 R9, R8, 0x1, RZ ; STG.E [R2.64], R9 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R9, R8, R10 ; IADD3 R11, R8, 0x1, RZ ; STG.E [R2.64], R11 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R11, R8, R10 ; IADD3 R13, R8, 0x1, RZ ; STG.E [R2.64], R13 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R13, R8, R9 ; IADD3 R9, R8, 0x1, RZ ; STG.E [R2.64], R9 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R9, R8, R10 ; IADD3 R11, R8, 0x1, RZ ; STG.E [R2.64], R11 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R11, R8, R10 ; IADD3 R13, R8, 0x1, RZ ; STG.E [R2.64], R13 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R13, R8, R9 ; IADD3 R9, R8, 0x1, RZ ; STG.E [R2.64], R9 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R9, R8, R10 ; IADD3 R11, R8, 0x1, RZ ; STG.E [R2.64], R11 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R11, R8, R10 ; IADD3 R13, R8, 0x1, RZ ; STG.E [R2.64], R13 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R13, R8, R9 ; IADD3 R9, R8, 0x1, RZ ; STG.E [R2.64], R9 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R9, R8, R10 ; IADD3 R11, R8, 0x1, RZ ; STG.E [R2.64], R11 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R11, R8, R10 ; IADD3 R13, R8, 0x1, RZ ; STG.E [R2.64], R13 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R13, R8, R9 ; IADD3 R9, R8, 0x1, RZ ; STG.E [R2.64], R9 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R9, R8, R10 ; IADD3 R11, R8, 0x1, RZ ; STG.E [R2.64], R11 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R11, R8, R10 ; IADD3 R13, R8, 0x1, RZ ; STG.E [R2.64], R13 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R13, R8, R9 ; IADD3 R9, R8, 0x1, RZ ; STG.E [R2.64], R9 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R9, R8, R10 ; IADD3 R11, R8, 0x1, RZ ; STG.E [R2.64], R11 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R11, R8, R10 ; IADD3 R13, R8, 0x1, RZ ; STG.E [R2.64], R13 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R13, R8, R9 ; IADD3 R15, R8, 0x1, RZ ; STG.E [R2.64], R15 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R15, R8, R9 ; IADD3 R17, R8, 0x1, RZ ; STG.E [R2.64], R17 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R17, R8, R9 ; IADD3 R9, R8, 0x1, RZ ; STG.E [R2.64], R9 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R9, R8, R10 ; IADD3 R11, R8, 0x1, RZ ; STG.E [R2.64], R11 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R11, R8, R10 ; IADD3 R13, R8, 0x1, RZ ; STG.E [R2.64], R13 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R13, R8, R9 ; IADD3 R9, R8, 0x1, RZ ; STG.E [R2.64], R9 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R9, R8, R10 ; IADD3 R11, R8, 0x1, RZ ; STG.E [R2.64], R11 ; LDG.E R8, [R4.64] ; LDG.E R10, [R6.64] ; IADD3 R8, R11, R8, R10 ; IADD3 R13, R8, 0x1, RZ ; STG.E [R2.64], R13 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R8, R13, R8, R9 ; IADD3 R15, R8, 0x1, RZ ; STG.E [R2.64], R15 ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R0, R0, 0x28, RZ ; ISETP.NE.AND P0, PT, R0, 0x3e8, PT ; IADD3 R9, R15, R8, R9 ; IADD3 R9, R9, 0x1, RZ ; STG.E [R2.64], R9 ; @P0 BRA 0xd0 ; EXIT ; BRA 0xd90; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0002f6e4_00000000-6_f7ae0d53a931d8566484cae1df70e76757f301e5.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i .type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function _Z27__device_stub__Z3addPiS_S_iPiS_S_i: .LFB2082: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z3addPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i .globl _Z3addPiS_S_i .type _Z3addPiS_S_i, @function _Z3addPiS_S_i: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z3addPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z3addPiS_S_i, .-_Z3addPiS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%d\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $64, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movl $40000, %edi call _Znam@PLT movq %rax, %rbp movl $40000, %edi call _Znam@PLT movq %rax, %rbx movl $40000, %edi call _Znam@PLT movq %rax, %r12 movl $0, %eax .L12: movl $1, 0(%rbp,%rax) movl $2, (%rbx,%rax) addq $4, %rax cmpq $40000, %rax jne .L12 leaq 8(%rsp), %rdi movl $40000, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $40000, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $40000, %esi call cudaMalloc@PLT movl $1, %ecx movl $40000, %edx movq %rbp, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $40000, %edx movq %rbx, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $1024, 44(%rsp) movl $1, 48(%rsp) movl $10, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L19 .L13: movl $2, %ecx movl $40000, %edx movq 24(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT movq %r12, %rbx leaq 40(%r12), %rbp leaq .LC0(%rip), %r12 .L14: movl (%rbx), %edx movq %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L14 movq 56(%rsp), %rax subq %fs:40, %rax jne .L20 movl $0, %eax addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state movl $10000, %ecx movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z27__device_stub__Z3addPiS_S_iPiS_S_i jmp .L13 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC1: .string "_Z3addPiS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z3addPiS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z3addPiS_S_i ; -- Begin function _Z3addPiS_S_i .globl _Z3addPiS_S_i .p2align 8 .type _Z3addPiS_S_i,@function _Z3addPiS_S_i: ; @_Z3addPiS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_3 ; %bb.1: ; %.preheader s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s4, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo v_add_co_u32 v2, vcc_lo, s6, v4 v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo v_add_co_u32 v4, vcc_lo, s0, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo s_movk_i32 s0, 0x3e8 .LBB0_2: ; =>This Inner Loop Header: Depth=1 global_load_b32 v6, v[0:1], off global_load_b32 v7, v[2:3], off global_load_b32 v8, v[4:5], off s_add_i32 s0, s0, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_cmp_lg_u32 s0, 0 s_waitcnt vmcnt(1) v_add_nc_u32_e32 v6, v6, v7 s_waitcnt vmcnt(0) v_add3_u32 v6, v6, v8, 1 global_store_b32 v[4:5], v6, off s_cbranch_scc1 .LBB0_2 .LBB0_3: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z3addPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 224 ; NumSgprs: 18 ; NumVgprs: 9 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 9 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z3addPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z3addPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "f7ae0d53a931d8566484cae1df70e76757f301e5.hip" .globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i .p2align 4, 0x90 .type _Z18__device_stub__addPiS_S_i,@function _Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3addPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $144, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $40000, %edi # imm = 0x9C40 callq _Znam movq %rax, %r15 movl $40000, %edi # imm = 0x9C40 callq _Znam movq %rax, %r14 movl $40000, %edi # imm = 0x9C40 callq _Znam movq %rax, %rbx xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1, (%r15,%rax,4) movl $2, (%r14,%rax,4) incq %rax cmpq $10000, %rax # imm = 0x2710 jne .LBB1_1 # %bb.2: leaq 32(%rsp), %rdi movl $40000, %esi # imm = 0x9C40 callq hipMalloc leaq 24(%rsp), %rdi movl $40000, %esi # imm = 0x9C40 callq hipMalloc leaq 16(%rsp), %rdi movl $40000, %esi # imm = 0x9C40 callq hipMalloc movq 32(%rsp), %rdi movl $40000, %edx # imm = 0x9C40 movq %r15, %rsi movl $1, %ecx callq hipMemcpy movq 24(%rsp), %rdi movl $40000, %edx # imm = 0x9C40 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967306, %rdi # imm = 0x10000000A leaq 1014(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 32(%rsp), %rax movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movl $10000, 12(%rsp) # imm = 0x2710 leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 12(%rsp), %rax movq %rax, 136(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z3addPiS_S_i, %edi pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: movq 16(%rsp), %rsi movl $40000, %edx # imm = 0x9C40 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 movl (%rbx,%r14,4), %esi movl $.L.str, %edi xorl %eax, %eax callq printf incq %r14 cmpq $10, %r14 jne .LBB1_5 # %bb.6: xorl %eax, %eax addq $144, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3addPiS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i .section .rodata,"a",@progbits .globl _Z3addPiS_S_i .p2align 3, 0x0 _Z3addPiS_S_i: .quad _Z18__device_stub__addPiS_S_i .size _Z3addPiS_S_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%d\n" .size .L.str, 4 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z3addPiS_S_i" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__addPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3addPiS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z21gen_matrix_from_linesPdS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2UR UR4, SR_CTAID.Y ; S2R R4, SR_TID.Y ; IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; HFMA2.MMA R0, -RZ, RZ, 0, 0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ; MOV R9, c[0x0][0x16c] ; ULOP3.LUT UR4, UR4, 0x3fffff, URZ, 0xc0, !UPT ; IADD3 R4, R4, UR4, RZ ; ULDC.64 UR4, c[0x0][0x118] ; SHF.L.U32 R2, R4, 0xa, RZ ; IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; IADD3 R10, P0, R2, 0x40, RZ ; IMAD.X R11, RZ, RZ, R3, P0 ; IMAD.MOV.U32 R2, RZ, RZ, R8 ; MOV R3, R9 ; LDG.E.64 R6, [R4.64] ; LDG.E.64 R8, [R2.64] ; DADD R8, R6, R8 ; IMAD.MOV.U32 R6, RZ, RZ, R10 ; MOV R7, R11 ; STG.E.64 [R6.64+-0x40], R8 ; LDG.E.64 R10, [R4.64] ; LDG.E.64 R12, [R2.64+0x8] ; DADD R10, R10, R12 ; STG.E.64 [R6.64+-0x38], R10 ; LDG.E.64 R12, [R4.64] ; LDG.E.64 R14, [R2.64+0x10] ; DADD R12, R12, R14 ; STG.E.64 [R6.64+-0x30], R12 ; LDG.E.64 R14, [R4.64] ; LDG.E.64 R16, [R2.64+0x18] ; DADD R14, R14, R16 ; STG.E.64 [R6.64+-0x28], R14 ; LDG.E.64 R8, [R4.64] ; LDG.E.64 R16, [R2.64+0x20] ; DADD R8, R8, R16 ; STG.E.64 [R6.64+-0x20], R8 ; LDG.E.64 R10, [R4.64] ; LDG.E.64 R16, [R2.64+0x28] ; DADD R10, R10, R16 ; STG.E.64 [R6.64+-0x18], R10 ; LDG.E.64 R12, [R4.64] ; LDG.E.64 R16, [R2.64+0x30] ; DADD R12, R12, R16 ; STG.E.64 [R6.64+-0x10], R12 ; LDG.E.64 R14, [R4.64] ; LDG.E.64 R16, [R2.64+0x38] ; DADD R14, R14, R16 ; STG.E.64 [R6.64+-0x8], R14 ; LDG.E.64 R8, [R4.64] ; LDG.E.64 R16, [R2.64+0x40] ; DADD R8, R8, R16 ; STG.E.64 [R6.64], R8 ; LDG.E.64 R10, [R4.64] ; LDG.E.64 R16, [R2.64+0x48] ; DADD R10, R10, R16 ; STG.E.64 [R6.64+0x8], R10 ; LDG.E.64 R12, [R4.64] ; LDG.E.64 R16, [R2.64+0x50] ; DADD R12, R12, R16 ; STG.E.64 [R6.64+0x10], R12 ; LDG.E.64 R14, [R4.64] ; LDG.E.64 R16, [R2.64+0x58] ; DADD R14, R14, R16 ; STG.E.64 [R6.64+0x18], R14 ; LDG.E.64 R8, [R4.64] ; LDG.E.64 R16, [R2.64+0x60] ; DADD R8, R8, R16 ; STG.E.64 [R6.64+0x20], R8 ; LDG.E.64 R10, [R4.64] ; LDG.E.64 R16, [R2.64+0x68] ; DADD R10, R10, R16 ; STG.E.64 [R6.64+0x28], R10 ; LDG.E.64 R12, [R4.64] ; LDG.E.64 R16, [R2.64+0x70] ; IADD3 R0, R0, 0x10, RZ ; DADD R12, R12, R16 ; STG.E.64 [R6.64+0x30], R12 ; LDG.E.64 R14, [R4.64] ; LDG.E.64 R16, [R2.64+0x78] ; ISETP.NE.AND P0, PT, R0, 0x400, PT ; IADD3 R10, P1, R6, 0x80, RZ ; IADD3 R8, P2, R2, 0x80, RZ ; IMAD.X R11, RZ, RZ, R7, P1 ; IADD3.X R9, RZ, R3, RZ, P2, !PT ; DADD R14, R14, R16 ; STG.E.64 [R6.64+0x38], R14 ; @P0 BRA 0xf0 ; EXIT ; BRA 0x5b0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z16sum_matrix_linesPdS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2UR UR4, SR_CTAID.Y ; S2R R0, SR_TID.Y ; IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; ULOP3.LUT UR4, UR4, 0x3fffff, URZ, 0xc0, !UPT ; IADD3 R0, R0, UR4, RZ ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; LDG.E.64 R6, [R2.64] ; SHF.L.U32 R4, R0, 0xa, RZ ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; IADD3 R8, P0, R4, 0x40, RZ ; IADD3.X R9, RZ, R5, RZ, P0, !PT ; IMAD.MOV.U32 R4, RZ, RZ, R8 ; MOV R5, R9 ; LDG.E.64 R8, [R4.64+-0x40] ; DADD R8, R8, R6 ; STG.E.64 [R2.64], R8 ; LDG.E.64 R6, [R4.64+-0x38] ; DADD R6, R8, R6 ; STG.E.64 [R2.64], R6 ; LDG.E.64 R10, [R4.64+-0x30] ; DADD R10, R6, R10 ; STG.E.64 [R2.64], R10 ; LDG.E.64 R12, [R4.64+-0x28] ; DADD R12, R10, R12 ; STG.E.64 [R2.64], R12 ; LDG.E.64 R14, [R4.64+-0x20] ; DADD R14, R12, R14 ; STG.E.64 [R2.64], R14 ; LDG.E.64 R8, [R4.64+-0x18] ; DADD R8, R14, R8 ; STG.E.64 [R2.64], R8 ; LDG.E.64 R6, [R4.64+-0x10] ; DADD R6, R8, R6 ; STG.E.64 [R2.64], R6 ; LDG.E.64 R10, [R4.64+-0x8] ; DADD R10, R6, R10 ; STG.E.64 [R2.64], R10 ; LDG.E.64 R12, [R4.64] ; DADD R12, R10, R12 ; STG.E.64 [R2.64], R12 ; LDG.E.64 R14, [R4.64+0x8] ; DADD R14, R12, R14 ; STG.E.64 [R2.64], R14 ; LDG.E.64 R8, [R4.64+0x10] ; DADD R8, R14, R8 ; STG.E.64 [R2.64], R8 ; LDG.E.64 R6, [R4.64+0x18] ; DADD R6, R8, R6 ; STG.E.64 [R2.64], R6 ; LDG.E.64 R10, [R4.64+0x20] ; DADD R10, R6, R10 ; STG.E.64 [R2.64], R10 ; LDG.E.64 R12, [R4.64+0x28] ; DADD R12, R10, R12 ; STG.E.64 [R2.64], R12 ; LDG.E.64 R14, [R4.64+0x30] ; DADD R14, R12, R14 ; STG.E.64 [R2.64], R14 ; LDG.E.64 R8, [R4.64+0x38] ; DADD R8, R14, R8 ; STG.E.64 [R2.64], R8 ; LDG.E.64 R6, [R4.64+0x40] ; DADD R6, R8, R6 ; STG.E.64 [R2.64], R6 ; LDG.E.64 R10, [R4.64+0x48] ; DADD R10, R6, R10 ; STG.E.64 [R2.64], R10 ; LDG.E.64 R12, [R4.64+0x50] ; DADD R12, R10, R12 ; STG.E.64 [R2.64], R12 ; LDG.E.64 R14, [R4.64+0x58] ; DADD R14, R12, R14 ; STG.E.64 [R2.64], R14 ; LDG.E.64 R8, [R4.64+0x60] ; DADD R8, R14, R8 ; STG.E.64 [R2.64], R8 ; LDG.E.64 R6, [R4.64+0x68] ; DADD R6, R8, R6 ; STG.E.64 [R2.64], R6 ; LDG.E.64 R10, [R4.64+0x70] ; DADD R10, R6, R10 ; STG.E.64 [R2.64], R10 ; LDG.E.64 R12, [R4.64+0x78] ; DADD R12, R10, R12 ; STG.E.64 [R2.64], R12 ; LDG.E.64 R14, [R4.64+0x80] ; DADD R14, R12, R14 ; STG.E.64 [R2.64], R14 ; LDG.E.64 R8, [R4.64+0x88] ; DADD R8, R14, R8 ; STG.E.64 [R2.64], R8 ; LDG.E.64 R6, [R4.64+0x90] ; DADD R6, R8, R6 ; STG.E.64 [R2.64], R6 ; LDG.E.64 R10, [R4.64+0x98] ; DADD R10, R6, R10 ; STG.E.64 [R2.64], R10 ; LDG.E.64 R12, [R4.64+0xa0] ; DADD R12, R10, R12 ; STG.E.64 [R2.64], R12 ; LDG.E.64 R14, [R4.64+0xa8] ; DADD R14, R12, R14 ; STG.E.64 [R2.64], R14 ; LDG.E.64 R8, [R4.64+0xb0] ; DADD R8, R14, R8 ; STG.E.64 [R2.64], R8 ; LDG.E.64 R6, [R4.64+0xb8] ; DADD R6, R8, R6 ; STG.E.64 [R2.64], R6 ; LDG.E.64 R10, [R4.64+0xc0] ; DADD R10, R6, R10 ; STG.E.64 [R2.64], R10 ; LDG.E.64 R12, [R4.64+0xc8] ; DADD R12, R10, R12 ; STG.E.64 [R2.64], R12 ; LDG.E.64 R14, [R4.64+0xd0] ; DADD R14, R12, R14 ; STG.E.64 [R2.64], R14 ; LDG.E.64 R8, [R4.64+0xd8] ; DADD R8, R14, R8 ; STG.E.64 [R2.64], R8 ; LDG.E.64 R6, [R4.64+0xe0] ; DADD R6, R8, R6 ; STG.E.64 [R2.64], R6 ; LDG.E.64 R10, [R4.64+0xe8] ; DADD R10, R6, R10 ; STG.E.64 [R2.64], R10 ; LDG.E.64 R12, [R4.64+0xf0] ; DADD R12, R10, R12 ; STG.E.64 [R2.64], R12 ; LDG.E.64 R14, [R4.64+0xf8] ; DADD R14, R12, R14 ; STG.E.64 [R2.64], R14 ; LDG.E.64 R8, [R4.64+0x100] ; DADD R8, R14, R8 ; STG.E.64 [R2.64], R8 ; LDG.E.64 R6, [R4.64+0x108] ; DADD R6, R8, R6 ; STG.E.64 [R2.64], R6 ; LDG.E.64 R10, [R4.64+0x110] ; DADD R10, R6, R10 ; STG.E.64 [R2.64], R10 ; LDG.E.64 R12, [R4.64+0x118] ; DADD R12, R10, R12 ; STG.E.64 [R2.64], R12 ; LDG.E.64 R14, [R4.64+0x120] ; DADD R14, R12, R14 ; STG.E.64 [R2.64], R14 ; LDG.E.64 R8, [R4.64+0x128] ; DADD R16, R14, R8 ; STG.E.64 [R2.64], R16 ; LDG.E.64 R6, [R4.64+0x130] ; DADD R18, R16, R6 ; STG.E.64 [R2.64], R18 ; LDG.E.64 R6, [R4.64+0x138] ; DADD R20, R18, R6 ; STG.E.64 [R2.64], R20 ; LDG.E.64 R6, [R4.64+0x140] ; DADD R6, R6, R20 ; STG.E.64 [R2.64], R6 ; LDG.E.64 R8, [R4.64+0x148] ; DADD R8, R6, R8 ; STG.E.64 [R2.64], R8 ; LDG.E.64 R10, [R4.64+0x150] ; DADD R10, R8, R10 ; STG.E.64 [R2.64], R10 ; LDG.E.64 R12, [R4.64+0x158] ; DADD R12, R10, R12 ; STG.E.64 [R2.64], R12 ; LDG.E.64 R14, [R4.64+0x160] ; DADD R14, R12, R14 ; STG.E.64 [R2.64], R14 ; LDG.E.64 R6, [R4.64+0x168] ; DADD R6, R14, R6 ; STG.E.64 [R2.64], R6 ; LDG.E.64 R8, [R4.64+0x170] ; DADD R8, R6, R8 ; STG.E.64 [R2.64], R8 ; LDG.E.64 R10, [R4.64+0x178] ; DADD R10, R8, R10 ; STG.E.64 [R2.64], R10 ; LDG.E.64 R12, [R4.64+0x180] ; DADD R12, R10, R12 ; STG.E.64 [R2.64], R12 ; LDG.E.64 R14, [R4.64+0x188] ; DADD R14, R12, R14 ; STG.E.64 [R2.64], R14 ; LDG.E.64 R6, [R4.64+0x190] ; DADD R6, R14, R6 ; STG.E.64 [R2.64], R6 ; LDG.E.64 R8, [R4.64+0x198] ; DADD R8, R6, R8 ; STG.E.64 [R2.64], R8 ; LDG.E.64 R10, [R4.64+0x1a0] ; DADD R10, R8, R10 ; STG.E.64 [R2.64], R10 ; LDG.E.64 R12, [R4.64+0x1a8] ; DADD R12, R10, R12 ; STG.E.64 [R2.64], R12 ; LDG.E.64 R14, [R4.64+0x1b0] ; IADD3 R0, R0, 0x40, RZ ; DADD R14, R12, R14 ; STG.E.64 [R2.64], R14 ; LDG.E.64 R6, [R4.64+0x1b8] ; ISETP.NE.AND P0, PT, R0, 0x400, PT ; IADD3 R8, P1, R4, 0x200, RZ ; IMAD.X R9, RZ, RZ, R5, P1 ; DADD R6, R14, R6 ; STG.E.64 [R2.64], R6 ; @P0 BRA 0xe0 ; EXIT ; BRA 0xd60; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0004a6f1_00000000-6_a2a69cb5e08f55e034e15b08cea2343ed039ba58.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z38__device_stub__Z16sum_matrix_linesPdS_PdS_ .type _Z38__device_stub__Z16sum_matrix_linesPdS_PdS_, @function _Z38__device_stub__Z16sum_matrix_linesPdS_PdS_: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z16sum_matrix_linesPdS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z38__device_stub__Z16sum_matrix_linesPdS_PdS_, .-_Z38__device_stub__Z16sum_matrix_linesPdS_PdS_ .globl _Z16sum_matrix_linesPdS_ .type _Z16sum_matrix_linesPdS_, @function _Z16sum_matrix_linesPdS_: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z38__device_stub__Z16sum_matrix_linesPdS_PdS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z16sum_matrix_linesPdS_, .-_Z16sum_matrix_linesPdS_ .globl _Z43__device_stub__Z21gen_matrix_from_linesPdS_PdS_ .type _Z43__device_stub__Z21gen_matrix_from_linesPdS_PdS_, @function _Z43__device_stub__Z21gen_matrix_from_linesPdS_PdS_: .LFB2084: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 104(%rsp), %rax subq %fs:40, %rax jne .L16 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z21gen_matrix_from_linesPdS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z43__device_stub__Z21gen_matrix_from_linesPdS_PdS_, .-_Z43__device_stub__Z21gen_matrix_from_linesPdS_PdS_ .globl _Z21gen_matrix_from_linesPdS_ .type _Z21gen_matrix_from_linesPdS_, @function _Z21gen_matrix_from_linesPdS_: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z43__device_stub__Z21gen_matrix_from_linesPdS_PdS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z21gen_matrix_from_linesPdS_, .-_Z21gen_matrix_from_linesPdS_ .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC3: .string "\320\235\320\243 \320\224\320\220 \320\235\320\243 \320\224\320\220, \320\237\320\236\320\250\320\201\320\233 \320\257 \320\235\320\220\320\245\320\225\320\240\n" .section .rodata.str1.1,"aMS",@progbits,1 .LC4: .string "%lf\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $80, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax leaq 8192+b(%rip), %rdx leaq 8388608(%rdx), %rcx movsd .LC0(%rip), %xmm0 .L20: leaq -8192(%rdx), %rax .L21: movsd %xmm0, (%rax) addq $8, %rax cmpq %rdx, %rax jne .L21 addq $8192, %rdx cmpq %rcx, %rdx jne .L20 call cudaDeviceReset@PLT leaq 24(%rsp), %rdi movl $8388608, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $8388608, %esi call cudaMalloc@PLT leaq 40(%rsp), %rdi movl $8192, %esi call cudaMalloc@PLT movl $1, %ecx movl $8388608, %edx leaq b(%rip), %rsi movq 32(%rsp), %rdi call cudaMemcpy@PLT movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1024, 64(%rsp) movl $1, 68(%rsp) movl $0, %r9d movl $0, %r8d movq 48(%rsp), %rdx movl $1, %ecx movq 60(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L41 .L23: call cudaDeviceSynchronize@PLT movl 56(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 48(%rsp), %rdx movq 60(%rsp), %rdi movl 68(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L42 .L24: call cudaDeviceSynchronize@PLT movl $2, %ecx movl $8388608, %edx movq 24(%rsp), %rsi leaq a(%rip), %rdi call cudaMemcpy@PLT movsd a(%rip), %xmm6 movsd %xmm6, 8(%rsp) leaq 8192+a(%rip), %rbx leaq 8388608(%rbx), %rbp leaq .LC3(%rip), %r12 jmp .L25 .L41: movq 40(%rsp), %rsi movq 32(%rsp), %rdi call _Z38__device_stub__Z16sum_matrix_linesPdS_PdS_ jmp .L23 .L42: movq 40(%rsp), %rsi movq 24(%rsp), %rdi call _Z43__device_stub__Z21gen_matrix_from_linesPdS_PdS_ jmp .L24 .L43: subsd %xmm1, %xmm2 ucomisd %xmm3, %xmm2 jp .L28 jne .L28 .L30: addq $8, %rax cmpq %rbx, %rax je .L32 .L33: movsd (%rax), %xmm1 movapd %xmm1, %xmm0 movsd 8(%rsp), %xmm2 subsd %xmm2, %xmm0 pxor %xmm3, %xmm3 comisd %xmm0, %xmm3 ja .L43 comisd .LC2(%rip), %xmm0 jbe .L30 .L28: movq %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L32: addq $8192, %rbx cmpq %rbp, %rbx je .L34 .L25: leaq -8192(%rbx), %rax jmp .L33 .L34: movsd a(%rip), %xmm0 leaq .LC4(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L44 movl $0, %eax addq $80, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L44: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC5: .string "_Z21gen_matrix_from_linesPdS_" .LC6: .string "_Z16sum_matrix_linesPdS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _Z21gen_matrix_from_linesPdS_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z16sum_matrix_linesPdS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .globl c .bss .align 32 .type c, @object .size c, 8192 c: .zero 8192 .globl b .align 32 .type b, @object .size b, 8388608 b: .zero 8388608 .globl a .align 32 .type a, @object .size a, 8388608 a: .zero 8388608 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC0: .long -687194767 .long 1077162147 .align 8 .LC2: .long -2127697391 .long 1030854553 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z16sum_matrix_linesPdS_ ; -- Begin function _Z16sum_matrix_linesPdS_ .globl _Z16sum_matrix_linesPdS_ .p2align 8 .type _Z16sum_matrix_linesPdS_,@function _Z16sum_matrix_linesPdS_: ; @_Z16sum_matrix_linesPdS_ ; %bb.0: s_load_b128 s[0:3], s[0:1], 0x0 v_bfe_u32 v2, v0, 10, 10 s_and_b32 s4, s15, 0x3fffff s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_add_lshl_u32 v6, s4, v2, 3 v_add_co_u32 v2, s4, v2, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v3, null, 0, 0, s4 v_lshlrev_b64 v[4:5], 13, v[2:3] s_waitcnt lgkmcnt(0) global_load_b64 v[0:1], v6, s[2:3] v_add_co_u32 v2, s2, s2, v6 v_add_co_u32 v4, vcc_lo, s0, v4 v_add_co_ci_u32_e64 v3, null, s3, 0, s2 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo s_mov_b64 s[0:1], 0 .LBB0_1: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1) v_add_co_u32 v6, vcc_lo, v4, s0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 s_cmpk_eq_i32 s0, 0x2000 global_load_b64 v[6:7], v[6:7], off s_waitcnt vmcnt(0) v_add_f64 v[0:1], v[6:7], v[0:1] global_store_b64 v[2:3], v[0:1], off s_cbranch_scc0 .LBB0_1 ; %bb.2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z16sum_matrix_linesPdS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z16sum_matrix_linesPdS_, .Lfunc_end0-_Z16sum_matrix_linesPdS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 184 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .protected _Z21gen_matrix_from_linesPdS_ ; -- Begin function _Z21gen_matrix_from_linesPdS_ .globl _Z21gen_matrix_from_linesPdS_ .p2align 8 .type _Z21gen_matrix_from_linesPdS_,@function _Z21gen_matrix_from_linesPdS_: ; @_Z21gen_matrix_from_linesPdS_ ; %bb.0: s_load_b128 s[0:3], s[0:1], 0x0 v_bfe_u32 v2, v0, 10, 10 s_and_b32 s4, s15, 0x3fffff s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_add_co_u32 v0, s5, v2, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_co_ci_u32_e64 v1, null, 0, 0, s5 v_add_lshl_u32 v4, s4, v2, 3 v_lshlrev_b64 v[2:3], 13, v[0:1] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, s4, s2, v4 v_add_co_u32 v2, vcc_lo, s0, v2 v_add_co_ci_u32_e64 v1, null, s3, 0, s4 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo v_mov_b32_e32 v4, 0 s_mov_b64 s[0:1], 0 .p2align 6 .LBB1_1: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s4, s2, s0 s_addc_u32 s5, s3, s1 s_clause 0x1 global_load_b64 v[5:6], v4, s[4:5] global_load_b64 v[7:8], v[0:1], off s_waitcnt vmcnt(0) v_add_f64 v[5:6], v[5:6], v[7:8] v_add_co_u32 v7, vcc_lo, v2, s0 v_add_co_ci_u32_e32 v8, vcc_lo, s1, v3, vcc_lo s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 s_cmpk_eq_i32 s0, 0x2000 global_store_b64 v[7:8], v[5:6], off s_cbranch_scc0 .LBB1_1 ; %bb.2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z21gen_matrix_from_linesPdS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z21gen_matrix_from_linesPdS_, .Lfunc_end1-_Z21gen_matrix_from_linesPdS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 204 ; NumSgprs: 18 ; NumVgprs: 9 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 9 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z16sum_matrix_linesPdS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z16sum_matrix_linesPdS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z21gen_matrix_from_linesPdS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z21gen_matrix_from_linesPdS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "a2a69cb5e08f55e034e15b08cea2343ed039ba58.hip" .globl _Z31__device_stub__sum_matrix_linesPdS_ # -- Begin function _Z31__device_stub__sum_matrix_linesPdS_ .p2align 4, 0x90 .type _Z31__device_stub__sum_matrix_linesPdS_,@function _Z31__device_stub__sum_matrix_linesPdS_: # @_Z31__device_stub__sum_matrix_linesPdS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z16sum_matrix_linesPdS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z31__device_stub__sum_matrix_linesPdS_, .Lfunc_end0-_Z31__device_stub__sum_matrix_linesPdS_ .cfi_endproc # -- End function .globl _Z36__device_stub__gen_matrix_from_linesPdS_ # -- Begin function _Z36__device_stub__gen_matrix_from_linesPdS_ .p2align 4, 0x90 .type _Z36__device_stub__gen_matrix_from_linesPdS_,@function _Z36__device_stub__gen_matrix_from_linesPdS_: # @_Z36__device_stub__gen_matrix_from_linesPdS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z21gen_matrix_from_linesPdS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end1: .size _Z36__device_stub__gen_matrix_from_linesPdS_, .Lfunc_end1-_Z36__device_stub__gen_matrix_from_linesPdS_ .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI2_0: .quad 0x3d719799812dea11 # double 9.9999999999999998E-13 .LCPI2_1: .quad 0x3ff0000000000000 # double 1 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $120, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movl $b, %eax xorl %ecx, %ecx movabsq $4626376197461917041, %rdx # imm = 0x403430A3D70A3D71 .p2align 4, 0x90 .LBB2_1: # %.preheader50 # =>This Loop Header: Depth=1 # Child Loop BB2_2 Depth 2 xorl %esi, %esi .p2align 4, 0x90 .LBB2_2: # Parent Loop BB2_1 Depth=1 # => This Inner Loop Header: Depth=2 movq %rdx, (%rax,%rsi,8) incq %rsi cmpq $1024, %rsi # imm = 0x400 jne .LBB2_2 # %bb.3: # in Loop: Header=BB2_1 Depth=1 incq %rcx addq $8192, %rax # imm = 0x2000 cmpq $1024, %rcx # imm = 0x400 jne .LBB2_1 # %bb.4: movabsq $4398046511105, %r14 # imm = 0x40000000001 movabsq $4294967297, %rbx # imm = 0x100000001 callq hipDeviceReset leaq 24(%rsp), %rdi movl $8388608, %esi # imm = 0x800000 callq hipMalloc leaq 16(%rsp), %rdi movl $8388608, %esi # imm = 0x800000 callq hipMalloc leaq 8(%rsp), %rdi movl $8192, %esi # imm = 0x2000 callq hipMalloc movq 16(%rsp), %rdi movl $b, %esi movl $8388608, %edx # imm = 0x800000 movl $1, %ecx callq hipMemcpy movq %r14, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_6 # %bb.5: movq 16(%rsp), %rax movq 8(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z16sum_matrix_linesPdS_, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_6: callq hipDeviceSynchronize movq %r14, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_8 # %bb.7: movq 24(%rsp), %rax movq 8(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z21gen_matrix_from_linesPdS_, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_8: callq hipDeviceSynchronize movq 24(%rsp), %rsi movl $a, %ebx movl $a, %edi movl $8388608, %edx # imm = 0x800000 movl $2, %ecx callq hipMemcpy xorl %r14d, %r14d movsd a(%rip), %xmm3 # xmm3 = mem[0],zero movsd .LCPI2_0(%rip), %xmm4 # xmm4 = mem[0],zero movsd .LCPI2_1(%rip), %xmm5 # xmm5 = mem[0],zero xorpd %xmm6, %xmm6 movsd %xmm3, 112(%rsp) # 8-byte Spill jmp .LBB2_9 .p2align 4, 0x90 .LBB2_12: # in Loop: Header=BB2_9 Depth=1 movl $.Lstr, %edi callq puts@PLT xorpd %xmm6, %xmm6 movsd .LCPI2_1(%rip), %xmm5 # xmm5 = mem[0],zero movsd .LCPI2_0(%rip), %xmm4 # xmm4 = mem[0],zero movsd 112(%rsp), %xmm3 # 8-byte Reload # xmm3 = mem[0],zero .LBB2_13: # %.loopexit # in Loop: Header=BB2_9 Depth=1 incq %r14 addq $8192, %rbx # imm = 0x2000 cmpq $1024, %r14 # imm = 0x400 je .LBB2_14 .LBB2_9: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB2_11 Depth 2 xorl %eax, %eax .p2align 4, 0x90 .LBB2_11: # Parent Loop BB2_9 Depth=1 # => This Inner Loop Header: Depth=2 movsd (%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero movapd %xmm3, %xmm1 subsd %xmm0, %xmm1 subsd %xmm3, %xmm0 movapd %xmm4, %xmm2 cmpltsd %xmm0, %xmm2 andpd %xmm5, %xmm2 cmpltsd %xmm6, %xmm0 andpd %xmm0, %xmm1 andnpd %xmm2, %xmm0 orpd %xmm1, %xmm0 ucomisd %xmm6, %xmm0 jne .LBB2_12 jp .LBB2_12 # %bb.10: # in Loop: Header=BB2_11 Depth=2 incq %rax cmpq $1024, %rax # imm = 0x400 jne .LBB2_11 jmp .LBB2_13 .LBB2_14: movsd a(%rip), %xmm0 # xmm0 = mem[0],zero movl $.L.str.1, %edi movb $1, %al callq printf movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax addq $120, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z16sum_matrix_linesPdS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z21gen_matrix_from_linesPdS_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type a,@object # @a .bss .globl a .p2align 4, 0x0 a: .zero 8388608 .size a, 8388608 .type b,@object # @b .globl b .p2align 4, 0x0 b: .zero 8388608 .size b, 8388608 .type c,@object # @c .globl c .p2align 4, 0x0 c: .zero 8192 .size c, 8192 .type _Z16sum_matrix_linesPdS_,@object # @_Z16sum_matrix_linesPdS_ .section .rodata,"a",@progbits .globl _Z16sum_matrix_linesPdS_ .p2align 3, 0x0 _Z16sum_matrix_linesPdS_: .quad _Z31__device_stub__sum_matrix_linesPdS_ .size _Z16sum_matrix_linesPdS_, 8 .type _Z21gen_matrix_from_linesPdS_,@object # @_Z21gen_matrix_from_linesPdS_ .globl _Z21gen_matrix_from_linesPdS_ .p2align 3, 0x0 _Z21gen_matrix_from_linesPdS_: .quad _Z36__device_stub__gen_matrix_from_linesPdS_ .size _Z21gen_matrix_from_linesPdS_, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "%lf\n" .size .L.str.1, 5 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z16sum_matrix_linesPdS_" .size .L__unnamed_1, 25 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z21gen_matrix_from_linesPdS_" .size .L__unnamed_2, 30 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz " , " .size .Lstr, 8 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z31__device_stub__sum_matrix_linesPdS_ .addrsig_sym _Z36__device_stub__gen_matrix_from_linesPdS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym a .addrsig_sym b .addrsig_sym _Z16sum_matrix_linesPdS_ .addrsig_sym _Z21gen_matrix_from_linesPdS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
6,959
4,888
4,126
5,529
133
code for sm_80 Function : _Z9kernelCSRiPdS_PiS0_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x160] ; ISETP.GE.AND P0, PT, R3, 0x1, PT ; @!P0 EXIT ; S2R R5, SR_TID.X ; HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R6, R5, R6, c[0x0][0x180] ; LDG.E R0, [R6.64] ; IADD3 R2, R3, -0x1, RZ ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; LOP3.LUT R2, R3, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R3, RZ, RZ, RZ ; @!P0 BRA 0x4a0 ; MOV R7, 0x8 ; IMAD R6, R5, c[0x0][0x160], RZ ; IADD3 R8, -R2, c[0x0][0x160], RZ ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; IMAD.MOV.U32 R16, RZ, RZ, R6 ; MOV R6, R16 ; LDG.E.64 R14, [R6.64] ; DSETP.NEU.AND P0, PT, R14, RZ, PT ; @P0 IMAD.IADD R12, R0, 0x1, R3 ; @P0 MOV R13, 0x4 ; @P0 IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; @P0 IMAD.WIDE R10, R12, R11, c[0x0][0x170] ; @P0 IMAD.WIDE R12, R12, R13, c[0x0][0x178] ; @P0 STG.E.64 [R10.64], R14 ; @P0 STG.E [R12.64], R4 ; LDG.E.64 R16, [R6.64+0x8] ; @P0 IADD3 R3, R3, 0x1, RZ ; DSETP.NEU.AND P1, PT, R16, RZ, PT ; @P1 IMAD.IADD R20, R0, 0x1, R3 ; @P1 MOV R21, 0x4 ; @P1 IMAD.MOV.U32 R19, RZ, RZ, 0x8 ; @P1 IADD3 R9, R4, 0x1, RZ ; @P1 IMAD.WIDE R18, R20, R19, c[0x0][0x170] ; @P1 IMAD.WIDE R20, R20, R21, c[0x0][0x178] ; @P1 STG.E.64 [R18.64], R16 ; @P1 STG.E [R20.64], R9 ; LDG.E.64 R12, [R6.64+0x10] ; @P1 IADD3 R3, R3, 0x1, RZ ; DSETP.NEU.AND P0, PT, R12, RZ, PT ; @P0 MOV R15, 0x8 ; @P0 IMAD.IADD R22, R0, 0x1, R3 ; @P0 IADD3 R25, R4, 0x2, RZ ; @P0 IMAD.MOV.U32 R23, RZ, RZ, 0x4 ; @P0 IMAD.WIDE R14, R22, R15, c[0x0][0x170] ; @P0 IMAD.WIDE R22, R22, R23, c[0x0][0x178] ; @P0 STG.E.64 [R14.64], R12 ; @P0 STG.E [R22.64], R25 ; LDG.E.64 R10, [R6.64+0x18] ; IADD3 R8, R8, -0x4, RZ ; BSSY B0, 0x470 ; IADD3 R16, P2, R6, 0x20, RZ ; ISETP.NE.AND P3, PT, R8, RZ, PT ; @P0 IADD3 R3, R3, 0x1, RZ ; DSETP.NEU.AND P1, PT, R10, RZ, PT ; @!P1 BRA 0x460 ; IADD3 R14, R0, R3, RZ ; IMAD.MOV.U32 R13, RZ, RZ, 0x8 ; MOV R15, 0x4 ; IADD3 R9, R4, 0x3, RZ ; IMAD.WIDE R12, R14, R13, c[0x0][0x170] ; IADD3 R3, R3, 0x1, RZ ; IMAD.WIDE R14, R14, R15, c[0x0][0x178] ; STG.E.64 [R12.64], R10 ; STG.E [R14.64], R9 ; BSYNC B0 ; IMAD.X R7, RZ, RZ, R7, P2 ; IADD3 R4, R4, 0x4, RZ ; @P3 BRA 0x150 ; ISETP.NE.AND P0, PT, R2, RZ, PT ; @!P0 EXIT ; MOV R7, 0x8 ; IMAD R6, R5, c[0x0][0x160], R4 ; IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; IMAD.MOV.U32 R5, RZ, RZ, R6 ; MOV R12, R7 ; IMAD.MOV.U32 R6, RZ, RZ, R5 ; MOV R7, R12 ; LDG.E.64 R6, [R6.64] ; IADD3 R2, R2, -0x1, RZ ; IADD3 R5, P2, R5, 0x8, RZ ; ISETP.NE.AND P1, PT, R2, RZ, PT ; IADD3.X R12, RZ, R12, RZ, P2, !PT ; DSETP.NEU.AND P0, PT, R6, RZ, PT ; @P0 MOV R9, 0x8 ; @P0 IMAD.IADD R10, R0, 0x1, R3 ; @P0 IADD3 R3, R3, 0x1, RZ ; @P0 IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; @P0 IMAD.WIDE R8, R10, R9, c[0x0][0x170] ; @P0 IMAD.WIDE R10, R10, R11, c[0x0][0x178] ; @P0 STG.E.64 [R8.64], R6 ; @P0 STG.E [R10.64], R4 ; IADD3 R4, R4, 0x1, RZ ; @P1 BRA 0x510 ; EXIT ; BRA 0x640; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z16kernelcount_nonziPdPiS0_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; @P0 EXIT ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; ISETP.GE.AND P0, PT, R2, 0x1, PT ; @!P0 BRA 0xaf0 ; IADD3 R3, R2.reuse, -0x1, RZ ; CS2R R4, SRZ ; LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; @!P0 BRA 0xa00 ; IADD3 R3, -R2, c[0x0][0x160], RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; IMAD R6, R0, c[0x0][0x160], RZ ; ISETP.GT.AND P0, PT, R3, RZ, PT ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; @!P0 BRA 0x8a0 ; ISETP.GT.AND P1, PT, R3, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x610 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E.64 R16, [R6.64] ; LDG.E.64 R18, [R6.64+0x8] ; LDG.E.64 R20, [R6.64+0x10] ; LDG.E.64 R22, [R6.64+0x18] ; LDG.E.64 R24, [R6.64+0x20] ; LDG.E.64 R8, [R6.64+0x28] ; LDG.E.64 R10, [R6.64+0x30] ; LDG.E.64 R12, [R6.64+0x38] ; LDG.E.64 R14, [R6.64+0x40] ; IADD3 R26, R4, 0x1, RZ ; DSETP.NEU.AND P6, PT, R16, RZ, PT ; LDG.E.64 R16, [R6.64+0x48] ; DSETP.NEU.AND P1, PT, R18, RZ, PT ; LDG.E.64 R18, [R6.64+0x50] ; DSETP.NEU.AND P2, PT, R20, RZ, PT ; LDG.E.64 R20, [R6.64+0x58] ; DSETP.NEU.AND P3, PT, R22, RZ, PT ; LDG.E.64 R22, [R6.64+0x60] ; DSETP.NEU.AND P4, PT, R24, RZ, PT ; LDG.E.64 R24, [R6.64+0x68] ; DSETP.NEU.AND P5, PT, R8, RZ, PT ; LDG.E.64 R8, [R6.64+0x70] ; @!P6 IMAD.MOV R26, RZ, RZ, R4 ; DSETP.NEU.AND P6, PT, R10, RZ, PT ; LDG.E.64 R10, [R6.64+0x78] ; IADD3 R3, R3, -0x10, RZ ; IADD3 R4, R26, 0x1, RZ ; @!P1 IMAD.MOV R4, RZ, RZ, R26 ; DSETP.NEU.AND P1, PT, R12, RZ, PT ; IADD3 R5, R5, 0x10, RZ ; IADD3 R26, R4, 0x1, RZ ; @!P2 IMAD.MOV R26, RZ, RZ, R4 ; DSETP.NEU.AND P2, PT, R14, RZ, PT ; IADD3 R4, R26, 0x1, RZ ; @!P3 IMAD.MOV R4, RZ, RZ, R26 ; IADD3 R6, P3, R6, 0x80, RZ ; IADD3 R26, R4, 0x1, RZ ; @!P4 IMAD.MOV R26, RZ, RZ, R4 ; IMAD.X R7, RZ, RZ, R7, P3 ; IADD3 R4, R26, 0x1, RZ ; @!P5 IMAD.MOV R4, RZ, RZ, R26 ; IADD3 R12, R4, 0x1, RZ ; @!P6 IMAD.MOV R12, RZ, RZ, R4 ; IADD3 R4, R12, 0x1, RZ ; @!P1 IMAD.MOV R4, RZ, RZ, R12 ; IADD3 R12, R4, 0x1, RZ ; @!P2 IMAD.MOV R12, RZ, RZ, R4 ; IADD3 R4, R12, 0x1, RZ ; DSETP.NEU.AND P1, PT, R16, RZ, PT ; DSETP.NEU.AND P2, PT, R18, RZ, PT ; @!P1 IMAD.MOV R4, RZ, RZ, R12 ; DSETP.NEU.AND P1, PT, R20, RZ, PT ; IADD3 R12, R4, 0x1, RZ ; @!P2 IMAD.MOV R12, RZ, RZ, R4 ; DSETP.NEU.AND P2, PT, R22, RZ, PT ; IADD3 R4, R12, 0x1, RZ ; @!P1 IMAD.MOV R4, RZ, RZ, R12 ; DSETP.NEU.AND P1, PT, R24, RZ, PT ; IADD3 R12, R4, 0x1, RZ ; @!P2 IMAD.MOV R12, RZ, RZ, R4 ; DSETP.NEU.AND P2, PT, R8, RZ, PT ; IADD3 R4, R12, 0x1, RZ ; @!P1 IMAD.MOV R4, RZ, RZ, R12 ; DSETP.NEU.AND P1, PT, R10, RZ, PT ; IADD3 R8, R4, 0x1, RZ ; @!P2 IMAD.MOV R8, RZ, RZ, R4 ; ISETP.GT.AND P2, PT, R3, 0xc, PT ; IADD3 R4, R8, 0x1, RZ ; @!P1 IMAD.MOV R4, RZ, RZ, R8 ; @P2 BRA 0x1b0 ; ISETP.GT.AND P1, PT, R3, 0x4, PT ; @!P1 BRA 0x880 ; LDG.E.64 R22, [R6.64] ; LDG.E.64 R20, [R6.64+0x8] ; LDG.E.64 R18, [R6.64+0x10] ; LDG.E.64 R16, [R6.64+0x18] ; LDG.E.64 R14, [R6.64+0x20] ; LDG.E.64 R12, [R6.64+0x28] ; LDG.E.64 R10, [R6.64+0x30] ; LDG.E.64 R8, [R6.64+0x38] ; IADD3 R5, R5, 0x8, RZ ; IADD3 R3, R3, -0x8, RZ ; IADD3 R6, P2, R6, 0x40, RZ ; IMAD.X R7, RZ, RZ, R7, P2 ; DSETP.NEU.AND P0, PT, R22, RZ, PT ; DSETP.NEU.AND P1, PT, R20, RZ, PT ; IADD3 R20, R4, 0x1, RZ ; @!P0 IMAD.MOV R20, RZ, RZ, R4 ; DSETP.NEU.AND P0, PT, R18, RZ, PT ; IADD3 R4, R20, 0x1, RZ ; @!P1 IMAD.MOV R4, RZ, RZ, R20 ; DSETP.NEU.AND P1, PT, R16, RZ, PT ; IADD3 R16, R4, 0x1, RZ ; @!P0 IMAD.MOV R16, RZ, RZ, R4 ; DSETP.NEU.AND P0, PT, R14, RZ, PT ; IADD3 R4, R16, 0x1, RZ ; @!P1 IMAD.MOV R4, RZ, RZ, R16 ; DSETP.NEU.AND P1, PT, R12, RZ, PT ; IADD3 R12, R4, 0x1, RZ ; @!P0 IMAD.MOV R12, RZ, RZ, R4 ; DSETP.NEU.AND P0, PT, R10, RZ, PT ; IADD3 R4, R12, 0x1, RZ ; @!P1 IMAD.MOV R4, RZ, RZ, R12 ; DSETP.NEU.AND P1, PT, R8, RZ, PT ; IADD3 R8, R4, 0x1, RZ ; @!P0 IMAD.MOV R8, RZ, RZ, R4 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R4, R8, 0x1, RZ ; @!P1 IMAD.MOV R4, RZ, RZ, R8 ; ISETP.NE.OR P0, PT, R3, RZ, P0 ; @!P0 BRA 0xa00 ; LDG.E.64 R14, [R6.64] ; LDG.E.64 R8, [R6.64+0x8] ; LDG.E.64 R10, [R6.64+0x10] ; LDG.E.64 R12, [R6.64+0x18] ; IADD3 R3, R3, -0x4, RZ ; IADD3 R5, R5, 0x4, RZ ; IADD3 R6, P2, R6, 0x20, RZ ; IMAD.X R7, RZ, RZ, R7, P2 ; DSETP.NEU.AND P0, PT, R14, RZ, PT ; DSETP.NEU.AND P1, PT, R8, RZ, PT ; IADD3 R8, R4, 0x1, RZ ; @!P0 IMAD.MOV R8, RZ, RZ, R4 ; DSETP.NEU.AND P0, PT, R10, RZ, PT ; IADD3 R4, R8, 0x1, RZ ; @!P1 IMAD.MOV R4, RZ, RZ, R8 ; DSETP.NEU.AND P1, PT, R12, RZ, PT ; IADD3 R8, R4, 0x1, RZ ; @!P0 IMAD.MOV R8, RZ, RZ, R4 ; ISETP.NE.AND P0, PT, R3, RZ, PT ; IADD3 R4, R8, 0x1, RZ ; @!P1 IMAD.MOV R4, RZ, RZ, R8 ; @P0 BRA 0x8a0 ; ISETP.NE.AND P0, PT, R2, RZ, PT ; @!P0 BRA 0xaf0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; IMAD R6, R0, c[0x0][0x160], R5 ; IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; LDG.E.64 R8, [R6.64] ; IADD3 R2, R2, -0x1, RZ ; IADD3 R3, R4, 0x1, RZ ; ISETP.NE.AND P1, PT, R2, RZ, PT ; IADD3 R6, P2, R6, 0x8, RZ ; IMAD.X R7, RZ, RZ, R7, P2 ; DSETP.NEU.AND P0, PT, R8, RZ, PT ; @!P0 IMAD.MOV R3, RZ, RZ, R4 ; IMAD.MOV.U32 R4, RZ, RZ, R3 ; @P1 BRA 0xa50 ; ISETP.GE.AND P0, PT, R0.reuse, RZ, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; BSSY B2, 0x12d0 ; IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; STG.E [R2.64], R4 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P0 BRA 0x12b0 ; ISETP.GE.U32.AND P0, PT, R0.reuse, 0x3, PT ; BSSY B1, 0x1150 ; IADD3 R7, R0, 0x1, RZ ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0x1140 ; IMAD.IADD R8, R0, 0x1, -R7 ; BSSY B0, 0x1060 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; ISETP.GT.AND P0, PT, R8, -0x1, PT ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; @!P0 BRA 0x1050 ; IADD3 R9, R8, 0x1, RZ ; BSSY B3, 0xea0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; ISETP.GT.AND P1, PT, R9, 0xc, PT ; @!P1 BRA 0xe90 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E R13, [R2.64] ; LDG.E R14, [R2.64+0x4] ; LDG.E R16, [R2.64+0x8] ; LDG.E R15, [R2.64+0xc] ; LDG.E R18, [R2.64+0x10] ; LDG.E R17, [R2.64+0x14] ; LDG.E R20, [R2.64+0x18] ; LDG.E R19, [R2.64+0x1c] ; LDG.E R22, [R2.64+0x20] ; LDG.E R21, [R2.64+0x24] ; LDG.E R24, [R2.64+0x28] ; LDG.E R23, [R2.64+0x2c] ; LDG.E R12, [R2.64+0x30] ; LDG.E R11, [R2.64+0x34] ; LDG.E R10, [R2.64+0x38] ; LDG.E R9, [R2.64+0x3c] ; IADD3 R8, R8, -0x10, RZ ; IADD3 R6, R6, 0x10, RZ ; ISETP.GT.AND P1, PT, R8, 0xb, PT ; IADD3 R13, R14, R13, R4 ; IADD3 R14, P2, R2, 0x40, RZ ; IMAD.X R3, RZ, RZ, R3, P2 ; IADD3 R13, R15, R16, R13 ; IMAD.MOV.U32 R2, RZ, RZ, R14 ; IADD3 R13, R17, R18, R13 ; IADD3 R13, R19, R20, R13 ; IADD3 R13, R21, R22, R13 ; IADD3 R13, R23, R24, R13 ; IADD3 R11, R11, R12, R13 ; IADD3 R4, R9, R10, R11 ; @P1 BRA 0xca0 ; BSYNC B3 ; IADD3 R9, R8, 0x1, RZ ; BSSY B3, 0x1020 ; ISETP.GT.AND P1, PT, R9, 0x4, PT ; @!P1 BRA 0x1010 ; LDG.E R9, [R2.64] ; LDG.E R10, [R2.64+0x4] ; LDG.E R12, [R2.64+0x8] ; LDG.E R11, [R2.64+0xc] ; LDG.E R14, [R2.64+0x10] ; LDG.E R13, [R2.64+0x14] ; LDG.E R16, [R2.64+0x18] ; LDG.E R15, [R2.64+0x1c] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R6, R6, 0x8, RZ ; IADD3 R8, R8, -0x8, RZ ; IADD3 R9, R10, R9, R4 ; IADD3 R10, P1, R2, 0x20, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R10 ; IADD3 R9, R11, R12, R9 ; IMAD.X R11, RZ, RZ, R3, P1 ; IMAD.MOV.U32 R3, RZ, RZ, R11 ; IADD3 R9, R13, R14, R9 ; IADD3 R4, R15, R16, R9 ; BSYNC B3 ; ISETP.NE.OR P0, PT, R8, -0x1, P0 ; @!P0 BREAK B0 ; @!P0 BRA 0x1140 ; BSYNC B0 ; LDG.E R9, [R2.64] ; LDG.E R10, [R2.64+0x4] ; LDG.E R11, [R2.64+0x8] ; LDG.E R12, [R2.64+0xc] ; IADD3 R8, R8, -0x4, RZ ; IADD3 R13, P1, R2, 0x10, RZ ; ISETP.NE.AND P0, PT, R8, -0x1, PT ; IADD3 R6, R6, 0x4, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R13 ; IADD3 R4, R10, R9, R4 ; IMAD.X R10, RZ, RZ, R3, P1 ; IMAD.MOV.U32 R3, RZ, RZ, R10 ; IADD3 R4, R12, R11, R4 ; @P0 BRA 0x1060 ; BSYNC B1 ; ISETP.NE.AND P0, PT, R7, RZ, PT ; BSSY B0, 0x12a0 ; @!P0 BRA 0x1290 ; IMAD.WIDE R2, R6, R5, c[0x0][0x170] ; LDG.E R9, [R2.64] ; IADD3 R7, R7, -0x1, RZ ; IADD3 R6, P1, R2, 0x4, RZ ; ISETP.NE.AND P0, PT, R7, RZ, PT ; IMAD.X R8, RZ, RZ, R3, P1 ; IMAD.IADD R4, R4, 0x1, R9 ; @!P0 BRA 0x1290 ; IMAD.MOV.U32 R3, RZ, RZ, R8 ; IMAD.MOV.U32 R2, RZ, RZ, R6 ; LDG.E R3, [R2.64] ; IADD3 R7, R7, -0x1, RZ ; IADD3 R6, P1, R6, 0x4, RZ ; ISETP.NE.AND P0, PT, R7, RZ, PT ; IMAD.X R8, RZ, RZ, R8, P1 ; IMAD.IADD R4, R3, 0x1, R4 ; @P0 BRA 0x1200 ; BSYNC B0 ; BRA 0x12c0 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; BSYNC B2 ; WARPSYNC 0xffffffff ; IADD3 R2, R0, 0x1, RZ ; IMAD.WIDE R2, R2, R5, c[0x0][0x178] ; STG.E [R2.64], R4 ; EXIT ; BRA 0x1320; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00058d13_00000000-6_4071e4c02ce830b22a9bd84c6e336ff383abdbd3.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z42__device_stub__Z16kernelcount_nonziPdPiS0_iPdPiS0_ .type _Z42__device_stub__Z16kernelcount_nonziPdPiS0_iPdPiS0_, @function _Z42__device_stub__Z16kernelcount_nonziPdPiS0_iPdPiS0_: .LFB2082: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 28(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %rcx, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z16kernelcount_nonziPdPiS0_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z42__device_stub__Z16kernelcount_nonziPdPiS0_iPdPiS0_, .-_Z42__device_stub__Z16kernelcount_nonziPdPiS0_iPdPiS0_ .globl _Z16kernelcount_nonziPdPiS0_ .type _Z16kernelcount_nonziPdPiS0_, @function _Z16kernelcount_nonziPdPiS0_: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z42__device_stub__Z16kernelcount_nonziPdPiS0_iPdPiS0_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z16kernelcount_nonziPdPiS0_, .-_Z16kernelcount_nonziPdPiS0_ .globl _Z36__device_stub__Z9kernelCSRiPdS_PiS0_iPdS_PiS0_ .type _Z36__device_stub__Z9kernelCSRiPdS_PiS0_iPdS_PiS0_, @function _Z36__device_stub__Z9kernelCSRiPdS_PiS0_iPdS_PiS0_: .LFB2084: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movl %edi, 44(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movq %r8, 8(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 44(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 152(%rsp), %rax subq %fs:40, %rax jne .L16 addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 184 pushq 56(%rsp) .cfi_def_cfa_offset 192 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z9kernelCSRiPdS_PiS0_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 176 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z36__device_stub__Z9kernelCSRiPdS_PiS0_iPdS_PiS0_, .-_Z36__device_stub__Z9kernelCSRiPdS_PiS0_iPdS_PiS0_ .globl _Z9kernelCSRiPdS_PiS0_ .type _Z9kernelCSRiPdS_PiS0_, @function _Z9kernelCSRiPdS_PiS0_: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z9kernelCSRiPdS_PiS0_iPdS_PiS0_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z9kernelCSRiPdS_PiS0_, .-_Z9kernelCSRiPdS_PiS0_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "What's your file name?\n" .LC1: .string "%s" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC2: .string "What is the size of the matrix A?\n" .section .rodata.str1.1 .LC3: .string "%d" .LC4: .string "r" .LC5: .string "Fail to open the file!\n" .LC6: .string "Success to open the file!\n\n" .section .rodata.str1.8 .align 8 .LC7: .string "Start to input the dense matrix...\n" .section .rodata.str1.1 .LC8: .string "%lf" .LC9: .string "Done!\n" .LC10: .string "Close the file!\n" .section .rodata.str1.8 .align 8 .LC11: .string "====================================\n\n" .align 8 .LC12: .string "Start to convert the dense matrix to sparse matrix with CSR!\n" .align 8 .LC13: .string "Global memory processing time: %f (ms)\n" .align 8 .LC14: .string "Successfully free the cuda memory\n" .section .rodata.str1.1 .LC15: .string "w" .LC16: .string "Start to write the file!\n" .LC17: .string "%f," .LC18: .string "%f\n" .LC19: .string "%d," .LC20: .string "%d\n" .section .rodata.str1.8 .align 8 .LC21: .string "Successfully free the memory\n\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $232, %rsp .cfi_def_cfa_offset 288 movq %fs:40, %rax movq %rax, 216(%rsp) xorl %eax, %eax leaq .LC0(%rip), %rsi movl $2, %edi call __printf_chk@PLT leaq 112(%rsp), %r12 movq %r12, %rsi leaq .LC1(%rip), %rdi movl $0, %eax call __isoc23_scanf@PLT leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 8(%rsp), %rsi leaq .LC3(%rip), %rdi movl $0, %eax call __isoc23_scanf@PLT movl 8(%rsp), %ebp movl %ebp, %edi imull %ebp, %edi movslq %edi, %rdi salq $3, %rdi call malloc@PLT movq %rax, %rbx leal 1(%rbp), %edi movslq %edi, %rdi salq $2, %rdi call malloc@PLT movq %rax, %rbp movl $0, (%rax) leaq .LC4(%rip), %rsi movq %r12, %rdi call fopen@PLT testq %rax, %rax je .L48 movq %rax, %r14 leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %r13d leaq .LC8(%rip), %r15 cmpl $0, 8(%rsp) jg .L22 .L23: leaq .LC9(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %r14, %rdi call fclose@PLT leaq .LC10(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC11(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC12(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 56(%rsp), %rdi call cudaEventCreate@PLT leaq 64(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 56(%rsp), %rdi call cudaEventRecord@PLT movl 8(%rsp), %eax imull %eax, %eax movslq %eax, %rsi salq $3, %rsi leaq 16(%rsp), %rdi call cudaMalloc@PLT movl 8(%rsp), %eax leal 1(%rax), %esi movslq %esi, %rsi salq $2, %rsi leaq 40(%rsp), %rdi call cudaMalloc@PLT movslq 8(%rsp), %rsi salq $2, %rsi leaq 48(%rsp), %rdi call cudaMalloc@PLT movl 8(%rsp), %eax imull %eax, %eax movslq %eax, %rdx salq $3, %rdx movl $1, %ecx movq %rbx, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl 8(%rsp), %eax leal 1(%rax), %edx movslq %edx, %rdx salq $2, %rdx movl $1, %ecx movq %rbp, %rsi movq 40(%rsp), %rdi call cudaMemcpy@PLT movl $1024, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl 8(%rsp), %edx leal 1023(%rdx), %eax testl %edx, %edx cmovns %edx, %eax sarl $10, %eax addl $1, %eax movl %eax, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $0, %r9d movl $0, %r8d movq 76(%rsp), %rdx movl $1, %ecx movq 88(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L49 .L26: movl 8(%rsp), %eax leal 1(%rax), %edx movslq %edx, %rdx salq $2, %rdx movl $2, %ecx movq 40(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT movslq 8(%rsp), %rax movslq 0(%rbp,%rax,4), %rsi salq $3, %rsi leaq 24(%rsp), %rdi call cudaMalloc@PLT movslq 8(%rsp), %rax movslq 0(%rbp,%rax,4), %rsi salq $2, %rsi leaq 32(%rsp), %rdi call cudaMalloc@PLT movl 84(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 76(%rsp), %rdx movq 88(%rsp), %rdi movl 96(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L50 .L27: movslq 8(%rsp), %rax movslq 0(%rbp,%rax,4), %r12 leaq 0(,%r12,8), %r13 movq %r13, %rdi call malloc@PLT movq %rax, %r15 leaq 0(,%r12,4), %rdi call malloc@PLT movq %rax, %r14 movl $2, %ecx movq %r13, %rdx movq 24(%rsp), %rsi movq %r15, %rdi call cudaMemcpy@PLT movslq 8(%rsp), %rax movslq 0(%rbp,%rax,4), %rdx salq $2, %rdx movl $2, %ecx movq 32(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT call cudaThreadSynchronize@PLT movl $0, %esi movq 64(%rsp), %rdi call cudaEventRecord@PLT movq 64(%rsp), %rdi call cudaEventSynchronize@PLT leaq 12(%rsp), %rdi movq 64(%rsp), %rdx movq 56(%rsp), %rsi call cudaEventElapsedTime@PLT pxor %xmm0, %xmm0 cvtss2sd 12(%rsp), %xmm0 leaq .LC13(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq 48(%rsp), %rdi call cudaFree@PLT leaq .LC14(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC11(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movabsq $3347705487303004995, %rax movq %rax, 100(%rsp) movl $7633012, 108(%rsp) leaq 100(%rsp), %rdi leaq .LC15(%rip), %rsi call fopen@PLT movq %rax, %r13 testq %rax, %rax je .L51 leaq .LC16(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movslq 8(%rsp), %rdx leaq 0(,%rdx,4), %rax cmpl $0, 0(%rbp,%rdx,4) jle .L29 movl $0, %r12d jmp .L32 .L48: leaq .LC5(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L21 .L24: imull %r13d, %eax addl %r12d, %eax cltq leaq (%rbx,%rax,8), %rdx movq %r15, %rsi movq %r14, %rdi movl $0, %eax call __isoc23_fscanf@PLT addl $1, %r12d movl 8(%rsp), %eax cmpl %r12d, %eax jg .L24 .L25: addl $1, %r13d cmpl %r13d, 8(%rsp) jle .L23 .L22: movl 8(%rsp), %eax movl $0, %r12d testl %eax, %eax jg .L24 jmp .L25 .L49: movq 40(%rsp), %rcx movq 48(%rsp), %rdx movq 16(%rsp), %rsi movl 8(%rsp), %edi call _Z42__device_stub__Z16kernelcount_nonziPdPiS0_iPdPiS0_ jmp .L26 .L50: movq 40(%rsp), %r8 movq 32(%rsp), %rcx movq 24(%rsp), %rdx movq 16(%rsp), %rsi movl 8(%rsp), %edi call _Z36__device_stub__Z9kernelCSRiPdS_PiS0_iPdS_PiS0_ jmp .L27 .L51: leaq .LC5(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L21 .L30: movsd (%r15,%r12,8), %xmm0 leaq .LC18(%rip), %rdx movl $2, %esi movq %r13, %rdi movl $1, %eax call __fprintf_chk@PLT .L31: movslq 8(%rsp), %rdx leaq 0(,%rdx,4), %rax movl 0(%rbp,%rdx,4), %edx addq $1, %r12 cmpl %r12d, %edx jle .L52 .L32: cmpl %r12d, -4(%rbp,%rax) jl .L30 movsd (%r15,%r12,8), %xmm0 leaq .LC17(%rip), %rdx movl $2, %esi movq %r13, %rdi movl $1, %eax call __fprintf_chk@PLT jmp .L31 .L52: testl %edx, %edx jle .L29 movl $0, %r12d jmp .L35 .L33: movl (%r14,%r12,4), %ecx leaq .LC20(%rip), %rdx movl $2, %esi movq %r13, %rdi movl $0, %eax call __fprintf_chk@PLT .L34: movslq 8(%rsp), %rdx leaq 0(,%rdx,4), %rax addq $1, %r12 cmpl %r12d, 0(%rbp,%rdx,4) jle .L29 .L35: cmpl %r12d, -4(%rbp,%rax) jl .L33 movl (%r14,%r12,4), %ecx leaq .LC19(%rip), %rdx movl $2, %esi movq %r13, %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L34 .L29: cmpl $0, 8(%rsp) js .L36 movl $0, %r12d .L37: movl 0(%rbp,%r12,4), %ecx leaq .LC19(%rip), %rdx movl $2, %esi movq %r13, %rdi movl $0, %eax call __fprintf_chk@PLT addq $1, %r12 cmpl %r12d, 8(%rsp) jge .L37 .L36: movq %r13, %rdi call fclose@PLT leaq .LC10(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %rbx, %rdi call free@PLT movq %r15, %rdi call free@PLT movq %r14, %rdi call free@PLT movq %rbp, %rdi call free@PLT leaq .LC21(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L21: movq 216(%rsp), %rax subq %fs:40, %rax jne .L53 movl $0, %eax addq $232, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L53: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC22: .string "_Z9kernelCSRiPdS_PiS0_" .LC23: .string "_Z16kernelcount_nonziPdPiS0_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC22(%rip), %rdx movq %rdx, %rcx leaq _Z9kernelCSRiPdS_PiS0_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC23(%rip), %rdx movq %rdx, %rcx leaq _Z16kernelcount_nonziPdPiS0_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z16kernelcount_nonziPdPiS0_ ; -- Begin function _Z16kernelcount_nonziPdPiS0_ .globl _Z16kernelcount_nonziPdPiS0_ .p2align 8 .type _Z16kernelcount_nonziPdPiS0_,@function _Z16kernelcount_nonziPdPiS0_: ; @_Z16kernelcount_nonziPdPiS0_ ; %bb.0: s_clause 0x1 s_load_b32 s3, s[0:1], 0x2c s_load_b32 s2, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_mul_i32 s15, s15, s3 s_mov_b32 s3, exec_lo v_add_nc_u32_e32 v1, s15, v0 v_cmpx_gt_i32_e64 s2, v1 s_cbranch_execz .LBB0_10 ; %bb.1: ; %.preheader s_cmp_lt_i32 s2, 1 s_cbranch_scc1 .LBB0_4 ; %bb.2: ; %.lr.ph s_load_b64 s[4:5], s[0:1], 0x8 v_mul_lo_u32 v2, v1, s2 v_mov_b32_e32 v4, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[2:3], 3, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo .LBB0_3: ; =>This Inner Loop Header: Depth=1 global_load_b64 v[5:6], v[2:3], off v_add_co_u32 v2, vcc_lo, v2, 8 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo s_add_i32 s2, s2, -1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s2, 0 s_waitcnt vmcnt(0) v_cmp_neq_f64_e32 vcc_lo, 0, v[5:6] v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo s_cbranch_scc0 .LBB0_3 s_branch .LBB0_5 .LBB0_4: v_mov_b32_e32 v4, 0 .LBB0_5: ; %._crit_edge s_load_b64 s[2:3], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 v_mov_b32_e32 v3, 0 s_mov_b32 s4, exec_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[5:6], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v5, vcc_lo, s2, v5 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo global_store_b32 v[5:6], v4, off s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv v_cmpx_lt_i32_e32 -1, v1 s_cbranch_execz .LBB0_9 ; %bb.6: ; %.lr.ph39.preheader v_add3_u32 v0, v0, s15, 1 v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0 s_mov_b32 s5, 0 .LBB0_7: ; %.lr.ph39 ; =>This Inner Loop Header: Depth=1 global_load_b32 v5, v4, s[2:3] v_add_nc_u32_e32 v0, -1, v0 s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v0 s_or_b32 s5, vcc_lo, s5 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v3, v5, v3 s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_7 ; %bb.8: ; %Flow s_or_b32 exec_lo, exec_lo, s5 .LBB0_9: ; %Flow56 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s4 s_load_b64 s[0:1], s[0:1], 0x18 v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v3, off offset:4 .LBB0_10: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z16kernelcount_nonziPdPiS0_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z16kernelcount_nonziPdPiS0_, .Lfunc_end0-_Z16kernelcount_nonziPdPiS0_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 400 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z9kernelCSRiPdS_PiS0_ ; -- Begin function _Z9kernelCSRiPdS_PiS0_ .globl _Z9kernelCSRiPdS_PiS0_ .p2align 8 .type _Z9kernelCSRiPdS_PiS0_,@function _Z9kernelCSRiPdS_PiS0_: ; @_Z9kernelCSRiPdS_PiS0_ ; %bb.0: s_load_b32 s8, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s8, 1 s_cbranch_scc1 .LBB1_5 ; %bb.1: ; %.lr.ph s_load_b256 s[0:7], s[0:1], 0x8 v_lshlrev_b32_e32 v1, 2, v0 v_mul_lo_u32 v0, v0, s8 v_mov_b32_e32 v5, 0 s_waitcnt lgkmcnt(0) global_load_b32 v4, v1, s[6:7] v_mov_b32_e32 v1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[0:1] v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_mov_b32 s0, 0 s_set_inst_prefetch_distance 0x1 s_branch .LBB1_3 .p2align 6 .LBB1_2: ; in Loop: Header=BB1_3 Depth=1 s_or_b32 exec_lo, exec_lo, s1 v_add_co_u32 v0, vcc_lo, v0, 8 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_add_i32 s0, s0, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s8, s0 s_cbranch_scc1 .LBB1_5 .LBB1_3: ; =>This Inner Loop Header: Depth=1 global_load_b64 v[2:3], v[0:1], off s_mov_b32 s1, exec_lo s_waitcnt vmcnt(0) v_cmpx_neq_f64_e32 0, v[2:3] s_cbranch_execz .LBB1_2 ; %bb.4: ; in Loop: Header=BB1_3 Depth=1 v_add_nc_u32_e32 v6, v5, v4 v_dual_mov_b32 v10, s0 :: v_dual_add_nc_u32 v5, 1, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v7, 31, v6 v_lshlrev_b64 v[8:9], 3, v[6:7] v_lshlrev_b64 v[6:7], 2, v[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v8, vcc_lo, s2, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v6, vcc_lo, s4, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo global_store_b64 v[8:9], v[2:3], off global_store_b32 v[6:7], v10, off s_branch .LBB1_2 .LBB1_5: ; %._crit_edge s_set_inst_prefetch_distance 0x2 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9kernelCSRiPdS_PiS0_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 40 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 9 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z9kernelCSRiPdS_PiS0_, .Lfunc_end1-_Z9kernelCSRiPdS_PiS0_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 260 ; NumSgprs: 11 ; NumVgprs: 11 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 11 ; NumVGPRsForWavesPerEU: 11 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z16kernelcount_nonziPdPiS0_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z16kernelcount_nonziPdPiS0_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 40 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9kernelCSRiPdS_PiS0_ .private_segment_fixed_size: 0 .sgpr_count: 11 .sgpr_spill_count: 0 .symbol: _Z9kernelCSRiPdS_PiS0_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "4071e4c02ce830b22a9bd84c6e336ff383abdbd3.hip" .globl _Z31__device_stub__kernelcount_nonziPdPiS0_ # -- Begin function _Z31__device_stub__kernelcount_nonziPdPiS0_ .p2align 4, 0x90 .type _Z31__device_stub__kernelcount_nonziPdPiS0_,@function _Z31__device_stub__kernelcount_nonziPdPiS0_: # @_Z31__device_stub__kernelcount_nonziPdPiS0_ .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 4(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) movq %rcx, 56(%rsp) leaq 4(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 56(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z16kernelcount_nonziPdPiS0_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z31__device_stub__kernelcount_nonziPdPiS0_, .Lfunc_end0-_Z31__device_stub__kernelcount_nonziPdPiS0_ .cfi_endproc # -- End function .globl _Z24__device_stub__kernelCSRiPdS_PiS0_ # -- Begin function _Z24__device_stub__kernelCSRiPdS_PiS0_ .p2align 4, 0x90 .type _Z24__device_stub__kernelCSRiPdS_PiS0_,@function _Z24__device_stub__kernelCSRiPdS_PiS0_: # @_Z24__device_stub__kernelCSRiPdS_PiS0_ .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movl %edi, 12(%rsp) movq %rsi, 88(%rsp) movq %rdx, 80(%rsp) movq %rcx, 72(%rsp) movq %r8, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 88(%rsp), %rax movq %rax, 104(%rsp) leaq 80(%rsp), %rax movq %rax, 112(%rsp) leaq 72(%rsp), %rax movq %rax, 120(%rsp) leaq 64(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z9kernelCSRiPdS_PiS0_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end1: .size _Z24__device_stub__kernelCSRiPdS_PiS0_, .Lfunc_end1-_Z24__device_stub__kernelCSRiPdS_PiS0_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $312, %rsp # imm = 0x138 .cfi_def_cfa_offset 368 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $.Lstr, %edi callq puts@PLT leaq 208(%rsp), %r15 movl $.L.str.1, %edi movq %r15, %rsi xorl %eax, %eax callq __isoc23_scanf movl $.Lstr.1, %edi callq puts@PLT leaq 12(%rsp), %rsi movl $.L.str.3, %edi xorl %eax, %eax callq __isoc23_scanf movslq 12(%rsp), %rbx movl %ebx, %edi imull %edi, %edi shlq $3, %rdi callq malloc movq %rax, %r14 leaq 4(,%rbx,4), %rdi callq malloc movq %rax, %rbx movl $0, (%rax) movl $.L.str.4, %esi movq %r15, %rdi callq fopen testq %rax, %rax je .LBB2_27 # %bb.1: movq %rax, %r12 movl $.Lstr.3, %edi callq puts@PLT movl $.Lstr.4, %edi callq puts@PLT cmpl $0, 12(%rsp) jle .LBB2_7 # %bb.2: # %.preheader114.preheader xorl %ebp, %ebp jmp .LBB2_4 .p2align 4, 0x90 .LBB2_3: # %._crit_edge # in Loop: Header=BB2_4 Depth=1 incl %ebp cmpl 12(%rsp), %ebp jge .LBB2_7 .LBB2_4: # %.preheader114 # =>This Loop Header: Depth=1 # Child Loop BB2_6 Depth 2 movl 12(%rsp), %eax testl %eax, %eax jle .LBB2_3 # %bb.5: # %.lr.ph.preheader # in Loop: Header=BB2_4 Depth=1 xorl %r15d, %r15d .p2align 4, 0x90 .LBB2_6: # %.lr.ph # Parent Loop BB2_4 Depth=1 # => This Inner Loop Header: Depth=2 imull %ebp, %eax cltq addq %r15, %rax leaq (%r14,%rax,8), %rdx movl $.L.str.8, %esi movq %r12, %rdi xorl %eax, %eax callq __isoc23_fscanf movl 12(%rsp), %eax incq %r15 cmpl %eax, %r15d jl .LBB2_6 jmp .LBB2_3 .LBB2_7: # %._crit_edge117 movabsq $4294968320, %r15 # imm = 0x100000400 movl $.Lstr.5, %edi callq puts@PLT movq %r12, %rdi callq fclose movl $.Lstr.13, %edi callq puts@PLT movl $.Lstr.10, %edi callq puts@PLT movl $.Lstr.8, %edi callq puts@PLT leaq 144(%rsp), %rdi callq hipEventCreate leaq 48(%rsp), %rdi callq hipEventCreate movq 144(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movl 12(%rsp), %esi imull %esi, %esi shlq $3, %rsi leaq 40(%rsp), %rdi callq hipMalloc movslq 12(%rsp), %rax leaq 4(,%rax,4), %rsi leaq 16(%rsp), %rdi callq hipMalloc movslq 12(%rsp), %rsi shlq $2, %rsi leaq 152(%rsp), %rdi callq hipMalloc movq 40(%rsp), %rdi movl 12(%rsp), %edx imull %edx, %edx shlq $3, %rdx movq %r14, %rsi movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi movslq 12(%rsp), %rax leaq 4(,%rax,4), %rdx movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movl 12(%rsp), %eax leal 1023(%rax), %ecx testl %eax, %eax cmovnsl %eax, %ecx sarl $10, %ecx incl %ecx leaq (%rcx,%r15), %r12 addq $-1024, %r12 # imm = 0xFC00 movq %r12, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_9 # %bb.8: movl 12(%rsp), %eax movq 40(%rsp), %rcx movq 152(%rsp), %rdx movq 16(%rsp), %rsi movl %eax, 72(%rsp) movq %rcx, 128(%rsp) movq %rdx, 120(%rsp) movq %rsi, 112(%rsp) leaq 72(%rsp), %rax movq %rax, 160(%rsp) leaq 128(%rsp), %rax movq %rax, 168(%rsp) leaq 120(%rsp), %rax movq %rax, 176(%rsp) leaq 112(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rdi leaq 88(%rsp), %rsi leaq 104(%rsp), %rdx leaq 80(%rsp), %rcx callq __hipPopCallConfiguration movq 24(%rsp), %rsi movl 32(%rsp), %edx movq 88(%rsp), %rcx movl 96(%rsp), %r8d leaq 160(%rsp), %r9 movl $_Z16kernelcount_nonziPdPiS0_, %edi pushq 80(%rsp) .cfi_adjust_cfa_offset 8 pushq 112(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_9: movq 16(%rsp), %rsi movslq 12(%rsp), %rax leaq 4(,%rax,4), %rdx movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movslq 12(%rsp), %rax movslq (%rbx,%rax,4), %rsi shlq $3, %rsi leaq 64(%rsp), %rdi callq hipMalloc movslq 12(%rsp), %rax movslq (%rbx,%rax,4), %rsi shlq $2, %rsi leaq 56(%rsp), %rdi callq hipMalloc movq %r12, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_11 # %bb.10: movl 12(%rsp), %eax movq 40(%rsp), %rcx movq 64(%rsp), %rdx movq 56(%rsp), %rsi movq 16(%rsp), %rdi movl %eax, 140(%rsp) movq %rcx, 128(%rsp) movq %rdx, 120(%rsp) movq %rsi, 112(%rsp) movq %rdi, 104(%rsp) leaq 140(%rsp), %rax movq %rax, 160(%rsp) leaq 128(%rsp), %rax movq %rax, 168(%rsp) leaq 120(%rsp), %rax movq %rax, 176(%rsp) leaq 112(%rsp), %rax movq %rax, 184(%rsp) leaq 104(%rsp), %rax movq %rax, 192(%rsp) leaq 24(%rsp), %rdi leaq 88(%rsp), %rsi leaq 80(%rsp), %rdx leaq 72(%rsp), %rcx callq __hipPopCallConfiguration movq 24(%rsp), %rsi movl 32(%rsp), %edx movq 88(%rsp), %rcx movl 96(%rsp), %r8d leaq 160(%rsp), %r9 movl $_Z9kernelCSRiPdS_PiS0_, %edi pushq 72(%rsp) .cfi_adjust_cfa_offset 8 pushq 88(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_11: movslq 12(%rsp), %rax movslq (%rbx,%rax,4), %r12 leaq (,%r12,8), %r13 movq %r13, %rdi callq malloc movq %rax, %r15 shlq $2, %r12 movq %r12, %rdi callq malloc movq %rax, %r12 movq 64(%rsp), %rsi movq %r15, %rdi movq %r13, %rdx movl $2, %ecx callq hipMemcpy movq 56(%rsp), %rsi movslq 12(%rsp), %rax movslq (%rbx,%rax,4), %rdx shlq $2, %rdx movq %r12, %rdi movl $2, %ecx callq hipMemcpy callq hipDeviceSynchronize movq 48(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 48(%rsp), %rdi callq hipEventSynchronize movq 144(%rsp), %rsi movq 48(%rsp), %rdx leaq 24(%rsp), %rdi callq hipEventElapsedTime movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.13, %edi movb $1, %al callq printf movq 40(%rsp), %rdi callq hipFree movq 64(%rsp), %rdi callq hipFree movq 56(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 152(%rsp), %rdi callq hipFree movl $.Lstr.9, %edi callq puts@PLT movl $.Lstr.10, %edi callq puts@PLT movabsq $3347705487303004995, %rax # imm = 0x2E7570675F525343 movq %rax, 160(%rsp) movl $7633012, 168(%rsp) # imm = 0x747874 leaq 160(%rsp), %rdi movl $.L.str.15, %esi callq fopen testq %rax, %rax je .LBB2_27 # %bb.12: movq %rax, %r13 movl $.Lstr.12, %edi callq puts@PLT movslq 12(%rsp), %rax cmpl $0, (%rbx,%rax,4) jle .LBB2_17 # %bb.13: # %.lr.ph120.preheader xorl %ebp, %ebp jmp .LBB2_15 .p2align 4, 0x90 .LBB2_14: # %.lr.ph120 # in Loop: Header=BB2_15 Depth=1 movsd (%r15,%rbp,8), %xmm0 # xmm0 = mem[0],zero movq %r13, %rdi movb $1, %al callq fprintf incq %rbp movslq 12(%rsp), %rax movslq (%rbx,%rax,4), %rcx cmpq %rcx, %rbp jge .LBB2_17 .LBB2_15: # %.lr.ph120 # =>This Inner Loop Header: Depth=1 movslq -4(%rbx,%rax,4), %rax movl $.L.str.18, %esi cmpq %rax, %rbp jg .LBB2_14 # %bb.16: # %.lr.ph120 # in Loop: Header=BB2_15 Depth=1 movl $.L.str.17, %esi jmp .LBB2_14 .LBB2_27: movl $.Lstr.11, %edi jmp .LBB2_28 .LBB2_17: # %.preheader113 movslq 12(%rsp), %rax cmpl $0, (%rbx,%rax,4) jle .LBB2_22 # %bb.18: # %.lr.ph122.preheader xorl %ebp, %ebp jmp .LBB2_20 .p2align 4, 0x90 .LBB2_19: # %.lr.ph122 # in Loop: Header=BB2_20 Depth=1 movl (%r12,%rbp,4), %edx movq %r13, %rdi xorl %eax, %eax callq fprintf incq %rbp movslq 12(%rsp), %rax movslq (%rbx,%rax,4), %rcx cmpq %rcx, %rbp jge .LBB2_22 .LBB2_20: # %.lr.ph122 # =>This Inner Loop Header: Depth=1 movslq -4(%rbx,%rax,4), %rax movl $.L.str.20, %esi cmpq %rax, %rbp jg .LBB2_19 # %bb.21: # %.lr.ph122 # in Loop: Header=BB2_20 Depth=1 movl $.L.str.19, %esi jmp .LBB2_19 .LBB2_22: # %.preheader cmpl $0, 12(%rsp) js .LBB2_25 # %bb.23: # %.lr.ph125.preheader movq $-1, %rbp .p2align 4, 0x90 .LBB2_24: # %.lr.ph125 # =>This Inner Loop Header: Depth=1 movl 4(%rbx,%rbp,4), %edx movl $.L.str.19, %esi movq %r13, %rdi xorl %eax, %eax callq fprintf movslq 12(%rsp), %rax incq %rbp cmpq %rax, %rbp jl .LBB2_24 .LBB2_25: # %._crit_edge126 movq %r13, %rdi callq fclose movl $.Lstr.13, %edi callq puts@PLT movq %r14, %rdi callq free movq %r15, %rdi callq free movq %r12, %rdi callq free movq %rbx, %rdi callq free movl $.Lstr.14, %edi .LBB2_28: callq puts@PLT xorl %eax, %eax addq $312, %rsp # imm = 0x138 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z16kernelcount_nonziPdPiS0_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9kernelCSRiPdS_PiS0_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z16kernelcount_nonziPdPiS0_,@object # @_Z16kernelcount_nonziPdPiS0_ .section .rodata,"a",@progbits .globl _Z16kernelcount_nonziPdPiS0_ .p2align 3, 0x0 _Z16kernelcount_nonziPdPiS0_: .quad _Z31__device_stub__kernelcount_nonziPdPiS0_ .size _Z16kernelcount_nonziPdPiS0_, 8 .type _Z9kernelCSRiPdS_PiS0_,@object # @_Z9kernelCSRiPdS_PiS0_ .globl _Z9kernelCSRiPdS_PiS0_ .p2align 3, 0x0 _Z9kernelCSRiPdS_PiS0_: .quad _Z24__device_stub__kernelCSRiPdS_PiS0_ .size _Z9kernelCSRiPdS_PiS0_, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "%s" .size .L.str.1, 3 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "%d" .size .L.str.3, 3 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "r" .size .L.str.4, 2 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "%lf" .size .L.str.8, 4 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz "Global memory processing time: %f (ms)\n" .size .L.str.13, 40 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "w" .size .L.str.15, 2 .type .L.str.17,@object # @.str.17 .L.str.17: .asciz "%f," .size .L.str.17, 4 .type .L.str.18,@object # @.str.18 .L.str.18: .asciz "%f\n" .size .L.str.18, 4 .type .L.str.19,@object # @.str.19 .L.str.19: .asciz "%d," .size .L.str.19, 4 .type .L.str.20,@object # @.str.20 .L.str.20: .asciz "%d\n" .size .L.str.20, 4 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z16kernelcount_nonziPdPiS0_" .size .L__unnamed_1, 29 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z9kernelCSRiPdS_PiS0_" .size .L__unnamed_2, 23 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "What's your file name?" .size .Lstr, 23 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "What is the size of the matrix A?" .size .Lstr.1, 34 .type .Lstr.3,@object # @str.3 .Lstr.3: .asciz "Success to open the file!\n" .size .Lstr.3, 27 .type .Lstr.4,@object # @str.4 .Lstr.4: .asciz "Start to input the dense matrix..." .size .Lstr.4, 35 .type .Lstr.5,@object # @str.5 .Lstr.5: .asciz "Done!" .size .Lstr.5, 6 .type .Lstr.8,@object # @str.8 .Lstr.8: .asciz "Start to convert the dense matrix to sparse matrix with CSR!" .size .Lstr.8, 61 .type .Lstr.9,@object # @str.9 .Lstr.9: .asciz "Successfully free the cuda memory" .size .Lstr.9, 34 .type .Lstr.10,@object # @str.10 .Lstr.10: .asciz "====================================\n" .size .Lstr.10, 38 .type .Lstr.11,@object # @str.11 .Lstr.11: .asciz "Fail to open the file!" .size .Lstr.11, 23 .type .Lstr.12,@object # @str.12 .Lstr.12: .asciz "Start to write the file!" .size .Lstr.12, 25 .type .Lstr.13,@object # @str.13 .Lstr.13: .asciz "Close the file!" .size .Lstr.13, 16 .type .Lstr.14,@object # @str.14 .Lstr.14: .asciz "Successfully free the memory\n" .size .Lstr.14, 30 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z31__device_stub__kernelcount_nonziPdPiS0_ .addrsig_sym _Z24__device_stub__kernelCSRiPdS_PiS0_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z16kernelcount_nonziPdPiS0_ .addrsig_sym _Z9kernelCSRiPdS_PiS0_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z5countPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; MOV R2, c[0x4][0x8] ; ULDC.64 UR4, c[0x0][0x118] ; MOV R3, c[0x4][0xc] ; LDG.E.64 R2, [R2.64] ; S2R R7, SR_CTAID.X ; S2R R0, SR_TID.X ; LDG.E.64 R4, [R2.64+0x8] ; IMAD R7, R7, c[0x0][0x0], R0 ; IMAD.WIDE R4, R7, 0x8, R4 ; LDG.E.64 R4, [R4.64] ; HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; LDG.E R9, [R4.64] ; IMAD.WIDE R6, R7, R6, c[0x0][0x160] ; STG.E [R6.64], R9 ; EXIT ; BRA 0x100; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0008214e_00000000-6_2530c75b466d9f6ce09d300c4fbe6a46920e0c79.cudafe1.cpp" .text #APP #NO_APP .type _ZL20__nv_init_managed_rtv, @function _ZL20__nv_init_managed_rtv: .LFB1: .cfi_startproc movzbl _ZL22__nv_inited_managed_rt(%rip), %eax testb %al, %al je .L7 movb %al, _ZL22__nv_inited_managed_rt(%rip) ret .L7: subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE1: .size _ZL20__nv_init_managed_rtv, .-_ZL20__nv_init_managed_rtv .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2067: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2067: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z8new_nodei .type _Z8new_nodei, @function _Z8new_nodei: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movl %edi, %ebx cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L16 .L11: movl $1, %edx movl $16, %esi movq _ZL7newnode(%rip), %rdi call cudaMallocManaged@PLT cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L17 .L12: movq _ZL7newnode(%rip), %rax movq (%rax), %rdi movl $-1, %ecx movl $5, %edx movl $16, %esi call cudaMemAdvise@PLT cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L18 .L13: movq _ZL7newnode(%rip), %rax movq (%rax), %rax movl %ebx, (%rax) cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L19 .L14: movq _ZL7newnode(%rip), %rax movq (%rax), %rax movq $0, 8(%rax) popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L16: .cfi_restore_state movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L11 .L17: movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L12 .L18: movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L13 .L19: movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L14 .cfi_endproc .LFE2057: .size _Z8new_nodei, .-_Z8new_nodei .globl _Z9new_graphi .type _Z9new_graphi, @function _Z9new_graphi: .LFB2058: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movl %edi, %ebx cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L30 .L21: movl $1, %edx movl $16, %esi movq _ZL8newgraph(%rip), %rdi call cudaMallocManaged@PLT cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L31 .L22: movq _ZL8newgraph(%rip), %rax movq (%rax), %rdi movl $-1, %ecx movl $5, %edx movl $16, %esi call cudaMemAdvise@PLT cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L32 .L23: movq _ZL8newgraph(%rip), %rax movq (%rax), %rax movl %ebx, (%rax) movslq %ebx, %rbp salq $3, %rbp movq %rbp, %rdi call malloc@PLT movq %rax, %r12 cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L33 .L24: movq _ZL8newgraph(%rip), %rax movq (%rax), %rax movq %r12, 8(%rax) testl %ebx, %ebx jle .L20 movl $0, %ebx jmp .L27 .L30: movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L21 .L31: movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L22 .L32: movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L23 .L33: movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L24 .L26: movq _ZL8newgraph(%rip), %rax movq (%rax), %rax movq 8(%rax), %rax movq $0, (%rax,%rbx) addq $8, %rbx cmpq %rbx, %rbp je .L20 .L27: cmpb $0, _ZL22__nv_inited_managed_rt(%rip) jne .L26 movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L26 .L20: popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z9new_graphi, .-_Z9new_graphi .globl _Z7addEdgeii .type _Z7addEdgeii, @function _Z7addEdgeii: .LFB2059: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $8, %rsp .cfi_def_cfa_offset 48 movl %edi, %ebp movl %esi, %ebx movl %esi, %edi call _Z8new_nodei cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L45 movslq %ebp, %rax leaq 0(,%rax,8), %r13 movq _ZL8newgraph(%rip), %rdx movq (%rdx), %rdx movq 8(%rdx), %rdx movq (%rdx,%rax,8), %r12 .L36: movq _ZL7newnode(%rip), %rax movq (%rax), %rdx movq %r12, 8(%rdx) cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L46 movq (%rax), %r12 .L38: movq _ZL8newgraph(%rip), %rax movq (%rax), %rax movq 8(%rax), %rax movq %r12, (%rax,%r13) movl %ebp, %edi call _Z8new_nodei cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L47 movslq %ebx, %rbx leaq 0(,%rbx,8), %rbp movq _ZL8newgraph(%rip), %rax movq (%rax), %rax movq 8(%rax), %rax movq (%rax,%rbx,8), %rbx .L40: movq _ZL7newnode(%rip), %rax movq (%rax), %rdx movq %rbx, 8(%rdx) cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L48 movq (%rax), %rbx .L42: movq _ZL8newgraph(%rip), %rax movq (%rax), %rax movq 8(%rax), %rax movq %rbx, (%rax,%rbp) addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L45: .cfi_restore_state movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) movslq %ebp, %rdx leaq 0(,%rdx,8), %r13 movq _ZL8newgraph(%rip), %rcx movq (%rcx), %rcx movq 8(%rcx), %rcx movq (%rcx,%rdx,8), %r12 testb %al, %al jne .L36 movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L36 .L46: movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) movq _ZL7newnode(%rip), %rdx movq (%rdx), %r12 testb %al, %al jne .L38 movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L38 .L47: movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) movslq %ebx, %rbx leaq 0(,%rbx,8), %rbp movq _ZL8newgraph(%rip), %rdx movq (%rdx), %rdx movq 8(%rdx), %rdx movq (%rdx,%rbx,8), %rbx testb %al, %al jne .L40 movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L40 .L48: movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) movq _ZL7newnode(%rip), %rdx movq (%rdx), %rbx testb %al, %al jne .L42 movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L42 .cfi_endproc .LFE2059: .size _Z7addEdgeii, .-_Z7addEdgeii .globl _Z8get_vertPc .type _Z8get_vertPc, @function _Z8get_vertPc: .LFB2060: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax movzbl (%rdi), %eax cmpb $10, %al je .L57 addq $1, %rdi movl $0, %ecx movl $0, %edx jmp .L54 .L62: addl $1, %edx cmpl $2, %edx je .L55 jle .L53 .L50: movslq %ecx, %rcx movb $0, (%rsp,%rcx) movq %rsp, %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT cltq movq 24(%rsp), %rdx subq %fs:40, %rdx jne .L61 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L55: .cfi_restore_state movslq %ecx, %rdx movb %al, (%rsp,%rdx) addl $1, %ecx movl $2, %edx .L53: addq $1, %rdi movzbl -1(%rdi), %eax cmpb $10, %al je .L50 .L54: cmpb $32, %al je .L62 cmpl $2, %edx jne .L53 jmp .L55 .L57: movl $0, %ecx jmp .L50 .L61: call __stack_chk_fail@PLT .cfi_endproc .LFE2060: .size _Z8get_vertPc, .-_Z8get_vertPc .globl _Z7get_srcPc .type _Z7get_srcPc, @function _Z7get_srcPc: .LFB2061: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax movzbl (%rdi), %eax cmpb $10, %al je .L68 movl $1, %edx leaq -1(%rsp), %rsi jmp .L66 .L68: movl $0, %edx jmp .L64 .L65: movb %al, (%rsi,%rdx) leaq 1(%rdx), %rcx movzbl -1(%rdi,%rcx), %eax cmpb $10, %al je .L64 movq %rcx, %rdx .L66: cmpb $32, %al jne .L65 subl $1, %edx .L64: movslq %edx, %rdx movb $0, (%rsp,%rdx) movq %rsp, %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq 24(%rsp), %rdx subq %fs:40, %rdx jne .L72 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L72: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2061: .size _Z7get_srcPc, .-_Z7get_srcPc .globl _Z7get_dstPc .type _Z7get_dstPc, @function _Z7get_dstPc: .LFB2062: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax movzbl (%rdi), %eax cmpb $10, %al je .L81 addq $1, %rdi movl $0, %ecx movl $0, %edx jmp .L78 .L86: addl $1, %edx cmpl $1, %edx je .L79 jle .L77 .L74: movslq %ecx, %rcx movb $0, (%rsp,%rcx) movq %rsp, %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq 24(%rsp), %rdx subq %fs:40, %rdx jne .L85 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L79: .cfi_restore_state movslq %ecx, %rdx movb %al, (%rsp,%rdx) addl $1, %ecx movl $1, %edx .L77: addq $1, %rdi movzbl -1(%rdi), %eax cmpb $10, %al je .L74 .L78: cmpb $32, %al je .L86 cmpl $1, %edx jne .L77 jmp .L79 .L81: movl $0, %ecx jmp .L74 .L85: call __stack_chk_fail@PLT .cfi_endproc .LFE2062: .size _Z7get_dstPc, .-_Z7get_dstPc .globl _Z7comparePKvS0_ .type _Z7comparePKvS0_, @function _Z7comparePKvS0_: .LFB2063: .cfi_startproc endbr64 movl (%rsi), %eax subl (%rdi), %eax ret .cfi_endproc .LFE2063: .size _Z7comparePKvS0_, .-_Z7comparePKvS0_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "r" .LC1: .string "dblp-co-authors.txt" .LC2: .string "Could not open file %s" .LC3: .string "Graph Created....\n" .LC4: .string "Counting....\n" .text .globl main .type main, @function main: .LFB2064: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $240, %rsp .cfi_def_cfa_offset 272 movq %fs:40, %rax movq %rax, 232(%rsp) xorl %eax, %eax leaq .LC0(%rip), %rsi leaq .LC1(%rip), %rdi call fopen@PLT testq %rax, %rax je .L101 movq %rax, %r12 leaq 32(%rsp), %rbx movq %rax, %rcx movl $200, %edx movl $200, %esi movq %rbx, %rdi call __fgets_chk@PLT movq %r12, %rcx movl $200, %edx movl $200, %esi movq %rbx, %rdi call __fgets_chk@PLT movq %r12, %rcx movl $200, %edx movl $200, %esi movq %rbx, %rdi call __fgets_chk@PLT movq %r12, %rcx movl $200, %edx movl $200, %esi movq %rbx, %rdi call __fgets_chk@PLT movq %r12, %rcx movl $200, %edx movl $200, %esi movq %rbx, %rdi call __fgets_chk@PLT movq %rbx, %rdi call _Z8get_vertPc movl %eax, %edi call _Z9new_graphi movq %rbx, %rbp jmp .L91 .L101: leaq .LC1(%rip), %rdx leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %eax jmp .L88 .L92: movq %rbp, %rdi call _Z7get_srcPc movl %eax, %ebx movq %rbp, %rdi call _Z7get_dstPc movl %eax, %esi movl %ebx, %edi call _Z7addEdgeii .L91: movq %r12, %rcx movl $200, %edx movl $200, %esi movq %rbp, %rdi call __fgets_chk@PLT testq %rax, %rax jne .L92 leaq .LC3(%rip), %rsi movl $2, %edi call __printf_chk@PLT cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L102 .L93: movq _ZL8newgraph(%rip), %rax movq (%rax), %rax movl (%rax), %ebx movl $0, %edi call cudaSetDevice@PLT leaq 16(%rsp), %rdi call cudaEventCreate@PLT leaq 24(%rsp), %rdi call cudaEventCreate@PLT movslq %ebx, %rdi movabsq $2305843009213693950, %rax cmpq %rdi, %rax jb .L94 salq $2, %rdi call _Znam@PLT movq %rax, %rbx leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %esi movq 16(%rsp), %rdi call cudaEventRecord@PLT movl $0, %esi movq 24(%rsp), %rdi call cudaEventRecord@PLT movq 24(%rsp), %rdi call cudaEventSynchronize@PLT leaq 12(%rsp), %rdi movq 24(%rsp), %rdx movq 16(%rsp), %rsi call cudaEventElapsedTime@PLT cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L103 .L95: movq _ZL8newgraph(%rip), %rax movq (%rax), %rdi call free@PLT movq %rbx, %rdi call free@PLT movl $0, %eax .L88: movq 232(%rsp), %rdx subq %fs:40, %rdx jne .L104 addq $240, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L102: .cfi_restore_state call _ZL20__nv_init_managed_rtv jmp .L93 .L94: movq 232(%rsp), %rax subq %fs:40, %rax je .L97 call __stack_chk_fail@PLT .L97: call __cxa_throw_bad_array_new_length@PLT .L103: call _ZL20__nv_init_managed_rtv jmp .L95 .L104: call __stack_chk_fail@PLT .cfi_endproc .LFE2064: .size main, .-main .globl _Z24__device_stub__Z5countPiPi .type _Z24__device_stub__Z5countPiPi, @function _Z24__device_stub__Z5countPiPi: .LFB2089: .cfi_startproc endbr64 subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 8(%rsp) movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L109 .L105: movq 88(%rsp), %rax subq %fs:40, %rax jne .L110 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L109: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 120 pushq 24(%rsp) .cfi_def_cfa_offset 128 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z5countPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 112 jmp .L105 .L110: call __stack_chk_fail@PLT .cfi_endproc .LFE2089: .size _Z24__device_stub__Z5countPiPi, .-_Z24__device_stub__Z5countPiPi .globl _Z5countPi .type _Z5countPi, @function _Z5countPi: .LFB2090: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z24__device_stub__Z5countPiPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2090: .size _Z5countPi, .-_Z5countPi .section .rodata.str1.1 .LC5: .string "_Z5countPi" .LC6: .string "newnode" .LC7: .string "newgraph" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2092: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) movq %rax, _ZL32__nv_fatbinhandle_for_managed_rt(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _Z5countPi(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $8, %r9d movl $1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _ZL7newnode(%rip), %rsi movq %rbx, %rdi call __cudaRegisterManagedVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $8, %r9d movl $1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _ZL8newgraph(%rip), %rsi movq %rbx, %rdi call __cudaRegisterManagedVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2092: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section __nv_managed_data__,"aw" .align 8 .type _ZL8newgraph, @object .size _ZL8newgraph, 8 _ZL8newgraph: .zero 8 .align 8 .type _ZL7newnode, @object .size _ZL7newnode, 8 _ZL7newnode: .zero 8 .local _ZL32__nv_fatbinhandle_for_managed_rt .comm _ZL32__nv_fatbinhandle_for_managed_rt,8,8 .local _ZL22__nv_inited_managed_rt .comm _ZL22__nv_inited_managed_rt,1,1 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z5countPi ; -- Begin function _Z5countPi .globl _Z5countPi .p2align 8 .type _Z5countPi,@function _Z5countPi: ; @_Z5countPi ; %bb.0: s_getpc_b64 s[2:3] s_add_u32 s2, s2, newgraph@rel32@lo+4 s_addc_u32 s3, s3, newgraph@rel32@hi+12 s_load_b64 s[2:3], s[2:3], 0x0 s_waitcnt lgkmcnt(0) s_load_b64 s[2:3], s[2:3], 0x0 s_waitcnt lgkmcnt(0) v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3 s_clause 0x1 s_load_b32 s2, s[0:1], 0x14 s_load_b64 s[0:1], s[0:1], 0x0 flat_load_b64 v[1:2], v[1:2] offset:8 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_waitcnt vmcnt(0) v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[5:6], 3, v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v1, v5 v_add_co_ci_u32_e32 v1, vcc_lo, v2, v6, vcc_lo flat_load_b64 v[0:1], v[0:1] s_waitcnt vmcnt(0) lgkmcnt(0) flat_load_b32 v2, v[0:1] v_lshlrev_b64 v[0:1], 2, v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) lgkmcnt(0) global_store_b32 v[0:1], v2, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5countPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 264 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z5countPi, .Lfunc_end0-_Z5countPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 204 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .protected newgraph .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: hidden_block_count_x - .offset: 12 .size: 4 .value_kind: hidden_block_count_y - .offset: 16 .size: 4 .value_kind: hidden_block_count_z - .offset: 20 .size: 2 .value_kind: hidden_group_size_x - .offset: 22 .size: 2 .value_kind: hidden_group_size_y - .offset: 24 .size: 2 .value_kind: hidden_group_size_z - .offset: 26 .size: 2 .value_kind: hidden_remainder_x - .offset: 28 .size: 2 .value_kind: hidden_remainder_y - .offset: 30 .size: 2 .value_kind: hidden_remainder_z - .offset: 48 .size: 8 .value_kind: hidden_global_offset_x - .offset: 56 .size: 8 .value_kind: hidden_global_offset_y - .offset: 64 .size: 8 .value_kind: hidden_global_offset_z - .offset: 72 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 264 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5countPi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z5countPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "2530c75b466d9f6ce09d300c4fbe6a46920e0c79.hip" .globl _Z8new_nodei # -- Begin function _Z8new_nodei .p2align 4, 0x90 .type _Z8new_nodei,@function _Z8new_nodei: # @_Z8new_nodei .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movl %edi, %ebx movq newnode(%rip), %rdi movl $16, %esi movl $1, %edx callq hipMallocManaged movq newnode(%rip), %rax movq (%rax), %rdi movl $16, %esi movl $5, %edx movl $-1, %ecx callq hipMemAdvise movq newnode(%rip), %rax movq (%rax), %rax movl %ebx, (%rax) movq newnode(%rip), %rax movq (%rax), %rax movq $0, 8(%rax) popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z8new_nodei, .Lfunc_end0-_Z8new_nodei .cfi_endproc # -- End function .globl _Z9new_graphi # -- Begin function _Z9new_graphi .p2align 4, 0x90 .type _Z9new_graphi,@function _Z9new_graphi: # @_Z9new_graphi .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movl %edi, %ebx movq newgraph(%rip), %rdi movl $16, %esi movl $1, %edx callq hipMallocManaged movq newgraph(%rip), %rax movq (%rax), %rdi movl $16, %esi movl $5, %edx movl $-1, %ecx callq hipMemAdvise movq newgraph(%rip), %rax movq (%rax), %rax movl %ebx, (%rax) movslq %ebx, %r14 leaq (,%r14,8), %rdi callq malloc movq newgraph(%rip), %rcx movq (%rcx), %rcx movq %rax, 8(%rcx) testl %r14d, %r14d jle .LBB1_3 # %bb.1: # %.lr.ph.preheader movl %ebx, %eax xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movq newgraph(%rip), %rdx movq (%rdx), %rdx movq 8(%rdx), %rdx movq $0, (%rdx,%rcx,8) incq %rcx cmpq %rcx, %rax jne .LBB1_2 .LBB1_3: # %._crit_edge addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z9new_graphi, .Lfunc_end1-_Z9new_graphi .cfi_endproc # -- End function .globl _Z7addEdgeii # -- Begin function _Z7addEdgeii .p2align 4, 0x90 .type _Z7addEdgeii,@function _Z7addEdgeii: # @_Z7addEdgeii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movl %esi, %ebx movl %edi, %ebp movq newnode(%rip), %rdi movl $16, %esi movl $1, %edx callq hipMallocManaged movq newnode(%rip), %rax movq (%rax), %rdi movl $16, %esi movl $5, %edx movl $-1, %ecx callq hipMemAdvise movq newnode(%rip), %rax movq (%rax), %rax movl %ebx, (%rax) movq newnode(%rip), %rax movq (%rax), %rcx movq $0, 8(%rcx) movq newgraph(%rip), %rcx movq (%rcx), %rdx movq 8(%rdx), %rdx movslq %ebp, %r14 movq (%rdx,%r14,8), %rdx movq (%rax), %rsi movq %rdx, 8(%rsi) movq (%rax), %rax movq (%rcx), %rcx movq 8(%rcx), %rcx movq %rax, (%rcx,%r14,8) movq newnode(%rip), %rdi movl $16, %esi movl $1, %edx callq hipMallocManaged movq newnode(%rip), %rax movq (%rax), %rdi movl $16, %esi movl $5, %edx movl $-1, %ecx callq hipMemAdvise movq newnode(%rip), %rax movq (%rax), %rax movl %r14d, (%rax) movq newnode(%rip), %rax movq (%rax), %rcx movq $0, 8(%rcx) movq newgraph(%rip), %rcx movq (%rcx), %rdx movq 8(%rdx), %rdx movslq %ebx, %rsi movq (%rdx,%rsi,8), %rdx movq (%rax), %rdi movq %rdx, 8(%rdi) movq (%rax), %rax movq (%rcx), %rcx movq 8(%rcx), %rcx movq %rax, (%rcx,%rsi,8) popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z7addEdgeii, .Lfunc_end2-_Z7addEdgeii .cfi_endproc # -- End function .globl _Z20__device_stub__countPi # -- Begin function _Z20__device_stub__countPi .p2align 4, 0x90 .type _Z20__device_stub__countPi,@function _Z20__device_stub__countPi: # @_Z20__device_stub__countPi .cfi_startproc # %bb.0: subq $72, %rsp .cfi_def_cfa_offset 80 movq %rdi, 64(%rsp) leaq 64(%rsp), %rax movq %rax, (%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d movq %rsp, %r9 movl $_Z5countPi, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $88, %rsp .cfi_adjust_cfa_offset -88 retq .Lfunc_end3: .size _Z20__device_stub__countPi, .Lfunc_end3-_Z20__device_stub__countPi .cfi_endproc # -- End function .globl _Z8get_vertPc # -- Begin function _Z8get_vertPc .p2align 4, 0x90 .type _Z8get_vertPc,@function _Z8get_vertPc: # @_Z8get_vertPc .cfi_startproc # %bb.0: subq $24, %rsp .cfi_def_cfa_offset 32 xorl %eax, %eax xorl %ecx, %ecx jmp .LBB4_1 .p2align 4, 0x90 .LBB4_6: # in Loop: Header=BB4_1 Depth=1 movslq %ecx, %rsi movb %dl, (%rsp,%rsi) incl %ecx incq %rdi .LBB4_1: # =>This Inner Loop Header: Depth=1 movzbl (%rdi), %edx cmpl $32, %edx je .LBB4_4 # %bb.2: # in Loop: Header=BB4_1 Depth=1 cmpl $10, %edx je .LBB4_3 # %bb.5: # in Loop: Header=BB4_1 Depth=1 cmpl $2, %eax je .LBB4_6 jmp .LBB4_7 .p2align 4, 0x90 .LBB4_4: # in Loop: Header=BB4_1 Depth=1 incl %eax cmpl $2, %eax je .LBB4_6 .LBB4_7: # in Loop: Header=BB4_1 Depth=1 jg .LBB4_3 # %bb.8: # in Loop: Header=BB4_1 Depth=1 incq %rdi jmp .LBB4_1 .LBB4_3: movslq %ecx, %rax movb $0, (%rsp,%rax) movq %rsp, %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol cltq addq $24, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end4: .size _Z8get_vertPc, .Lfunc_end4-_Z8get_vertPc .cfi_endproc # -- End function .globl _Z7get_srcPc # -- Begin function _Z7get_srcPc .p2align 4, 0x90 .type _Z7get_srcPc,@function _Z7get_srcPc: # @_Z7get_srcPc .cfi_startproc # %bb.0: subq $24, %rsp .cfi_def_cfa_offset 32 xorl %eax, %eax .p2align 4, 0x90 .LBB5_1: # =>This Inner Loop Header: Depth=1 movzbl (%rdi,%rax), %ecx cmpl $10, %ecx je .LBB5_4 # %bb.2: # in Loop: Header=BB5_1 Depth=1 cmpl $32, %ecx je .LBB5_4 # %bb.3: # in Loop: Header=BB5_1 Depth=1 movb %cl, (%rsp,%rax) incq %rax jmp .LBB5_1 .LBB5_4: movl %eax, %eax movb $0, (%rsp,%rax) movq %rsp, %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol # kill: def $eax killed $eax killed $rax addq $24, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end5: .size _Z7get_srcPc, .Lfunc_end5-_Z7get_srcPc .cfi_endproc # -- End function .globl _Z7get_dstPc # -- Begin function _Z7get_dstPc .p2align 4, 0x90 .type _Z7get_dstPc,@function _Z7get_dstPc: # @_Z7get_dstPc .cfi_startproc # %bb.0: subq $24, %rsp .cfi_def_cfa_offset 32 xorl %eax, %eax xorl %ecx, %ecx jmp .LBB6_1 .p2align 4, 0x90 .LBB6_6: # in Loop: Header=BB6_1 Depth=1 movslq %ecx, %rsi movb %dl, (%rsp,%rsi) incl %ecx incq %rdi .LBB6_1: # =>This Inner Loop Header: Depth=1 movzbl (%rdi), %edx cmpl $32, %edx je .LBB6_4 # %bb.2: # in Loop: Header=BB6_1 Depth=1 cmpl $10, %edx je .LBB6_3 # %bb.5: # in Loop: Header=BB6_1 Depth=1 cmpl $1, %eax je .LBB6_6 jmp .LBB6_7 .p2align 4, 0x90 .LBB6_4: # in Loop: Header=BB6_1 Depth=1 incl %eax cmpl $1, %eax je .LBB6_6 .LBB6_7: # in Loop: Header=BB6_1 Depth=1 jg .LBB6_3 # %bb.8: # in Loop: Header=BB6_1 Depth=1 incq %rdi jmp .LBB6_1 .LBB6_3: movslq %ecx, %rax movb $0, (%rsp,%rax) movq %rsp, %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol # kill: def $eax killed $eax killed $rax addq $24, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end6: .size _Z7get_dstPc, .Lfunc_end6-_Z7get_dstPc .cfi_endproc # -- End function .globl _Z7comparePKvS0_ # -- Begin function _Z7comparePKvS0_ .p2align 4, 0x90 .type _Z7comparePKvS0_,@function _Z7comparePKvS0_: # @_Z7comparePKvS0_ .cfi_startproc # %bb.0: movl (%rsi), %eax subl (%rdi), %eax retq .Lfunc_end7: .size _Z7comparePKvS0_, .Lfunc_end7-_Z7comparePKvS0_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $256, %rsp # imm = 0x100 .cfi_def_cfa_offset 304 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $.L.str, %edi movl $.L.str.1, %esi callq fopen testq %rax, %rax je .LBB8_1 # %bb.2: movq %rax, %rbx leaq 48(%rsp), %r14 movq %r14, %rdi movl $200, %esi movq %rax, %rdx callq fgets movq %r14, %rdi movl $200, %esi movq %rbx, %rdx callq fgets movq %r14, %rdi movl $200, %esi movq %rbx, %rdx callq fgets movq %r14, %rdi movl $200, %esi movq %rbx, %rdx callq fgets movq %r14, %rdi movl $200, %esi movq %rbx, %rdx callq fgets xorl %eax, %eax xorl %ecx, %ecx jmp .LBB8_3 .p2align 4, 0x90 .LBB8_16: # in Loop: Header=BB8_3 Depth=1 movslq %ecx, %rsi movb %dl, (%rsp,%rsi) incl %ecx incq %r14 .LBB8_3: # =>This Inner Loop Header: Depth=1 movzbl (%r14), %edx cmpl $32, %edx je .LBB8_14 # %bb.4: # in Loop: Header=BB8_3 Depth=1 cmpl $10, %edx je .LBB8_5 # %bb.15: # in Loop: Header=BB8_3 Depth=1 cmpl $2, %eax je .LBB8_16 jmp .LBB8_17 .p2align 4, 0x90 .LBB8_14: # in Loop: Header=BB8_3 Depth=1 incl %eax cmpl $2, %eax je .LBB8_16 .LBB8_17: # in Loop: Header=BB8_3 Depth=1 jg .LBB8_5 # %bb.18: # in Loop: Header=BB8_3 Depth=1 incq %r14 jmp .LBB8_3 .LBB8_5: # %_Z8get_vertPc.exit movslq %ecx, %rax movb $0, (%rsp,%rax) movq %rsp, %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r14 movq newgraph(%rip), %rdi movl $16, %esi movl $1, %edx callq hipMallocManaged movq newgraph(%rip), %rax movq (%rax), %rdi movl $16, %esi movl $5, %edx movl $-1, %ecx callq hipMemAdvise movq newgraph(%rip), %rax movq (%rax), %rax movl %r14d, (%rax) movslq %r14d, %r15 leaq (,%r15,8), %rdi callq malloc movq newgraph(%rip), %rcx movq (%rcx), %rcx movq %rax, 8(%rcx) testl %r15d, %r15d jle .LBB8_8 # %bb.6: # %.lr.ph.preheader.i movl %r14d, %eax xorl %ecx, %ecx .p2align 4, 0x90 .LBB8_7: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 movq newgraph(%rip), %rdx movq (%rdx), %rdx movq 8(%rdx), %rdx movq $0, (%rdx,%rcx,8) incq %rcx cmpq %rcx, %rax jne .LBB8_7 .LBB8_8: # %_Z9new_graphi.exit leaq 48(%rsp), %r14 movq %r14, %rdi movl $200, %esi movq %rbx, %rdx callq fgets testq %rax, %rax je .LBB8_23 # %bb.9: # %.lr.ph.preheader movq %rsp, %r15 jmp .LBB8_10 .p2align 4, 0x90 .LBB8_22: # %_Z7get_dstPc.exit # in Loop: Header=BB8_10 Depth=1 movslq %ecx, %rax movb $0, (%rsp,%rax) movq %r15, %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movl %r12d, %edi movl %eax, %esi callq _Z7addEdgeii movq %r14, %rdi movl $200, %esi movq %rbx, %rdx callq fgets testq %rax, %rax je .LBB8_23 .LBB8_10: # %.lr.ph # =>This Loop Header: Depth=1 # Child Loop BB8_11 Depth 2 # Child Loop BB8_20 Depth 2 xorl %eax, %eax .p2align 4, 0x90 .LBB8_11: # Parent Loop BB8_10 Depth=1 # => This Inner Loop Header: Depth=2 movzbl 48(%rsp,%rax), %ecx cmpl $10, %ecx je .LBB8_19 # %bb.12: # in Loop: Header=BB8_11 Depth=2 cmpl $32, %ecx je .LBB8_19 # %bb.13: # in Loop: Header=BB8_11 Depth=2 movb %cl, (%rsp,%rax) incq %rax jmp .LBB8_11 .p2align 4, 0x90 .LBB8_19: # %_Z7get_srcPc.exit # in Loop: Header=BB8_10 Depth=1 movl %eax, %eax movb $0, (%rsp,%rax) xorl %r13d, %r13d movq %r15, %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r12 movq %r14, %rax xorl %ecx, %ecx jmp .LBB8_20 .p2align 4, 0x90 .LBB8_27: # in Loop: Header=BB8_20 Depth=2 movslq %ecx, %rsi movb %dl, (%rsp,%rsi) incl %ecx incq %rax .LBB8_20: # Parent Loop BB8_10 Depth=1 # => This Inner Loop Header: Depth=2 movzbl (%rax), %edx cmpl $32, %edx je .LBB8_25 # %bb.21: # in Loop: Header=BB8_20 Depth=2 cmpl $10, %edx je .LBB8_22 # %bb.26: # in Loop: Header=BB8_20 Depth=2 cmpl $1, %r13d je .LBB8_27 jmp .LBB8_28 .p2align 4, 0x90 .LBB8_25: # in Loop: Header=BB8_20 Depth=2 incl %r13d cmpl $1, %r13d je .LBB8_27 .LBB8_28: # in Loop: Header=BB8_20 Depth=2 jg .LBB8_22 # %bb.29: # in Loop: Header=BB8_20 Depth=2 incq %rax jmp .LBB8_20 .LBB8_23: # %._crit_edge movl $.Lstr, %edi callq puts@PLT movq newgraph(%rip), %rax movq (%rax), %rax movslq (%rax), %r14 xorl %ebx, %ebx xorl %edi, %edi callq hipSetDevice movq %rsp, %rdi callq hipEventCreate leaq 32(%rsp), %rdi callq hipEventCreate leaq (,%r14,4), %rax testq %r14, %r14 movq $-1, %rdi cmovnsq %rax, %rdi callq _Znam movq %rax, %r14 movl $.Lstr.1, %edi callq puts@PLT movq (%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 32(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 32(%rsp), %rdi callq hipEventSynchronize movq (%rsp), %rsi movq 32(%rsp), %rdx leaq 44(%rsp), %rdi callq hipEventElapsedTime movq newgraph(%rip), %rax movq (%rax), %rdi callq free movq %r14, %rdi callq free jmp .LBB8_24 .LBB8_1: movl $.L.str.2, %edi movl $.L.str, %esi xorl %eax, %eax callq printf movl $1, %ebx .LBB8_24: movl %ebx, %eax addq $256, %rsp # imm = 0x100 .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end8: .size main, .Lfunc_end8-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB9_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB9_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5countPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end9: .size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB10_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB10_2: retq .Lfunc_end10: .size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor .cfi_endproc # -- End function .type _Z5countPi,@object # @_Z5countPi .section .rodata,"a",@progbits .globl _Z5countPi .p2align 3, 0x0 _Z5countPi: .quad _Z20__device_stub__countPi .size _Z5countPi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "dblp-co-authors.txt" .size .L.str, 20 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "r" .size .L.str.1, 2 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Could not open file %s" .size .L.str.2, 23 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z5countPi" .size .L__unnamed_1, 11 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Graph Created...." .size .Lstr, 18 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "Counting...." .size .Lstr.1, 13 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z20__device_stub__countPi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z5countPi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z3addPiS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R6, SR_TID.X ; ISETP.GT.AND P0, PT, R6, 0x9, PT ; @P0 EXIT ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; LDG.E R4, [R4.64] ; LDG.E R3, [R2.64] ; IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; IADD3 R9, R4, R3, RZ ; STG.E [R6.64], R9 ; EXIT ; BRA 0xe0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0009a6ed_00000000-6_744e787f0488a88a81816ad04359df176467398a.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z26__device_stub__Z3addPiS_S_PiS_S_ .type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function _Z26__device_stub__Z3addPiS_S_PiS_S_: .LFB2082: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z3addPiS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_ .globl _Z3addPiS_S_ .type _Z3addPiS_S_, @function _Z3addPiS_S_: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z3addPiS_S_PiS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z3addPiS_S_, .-_Z3addPiS_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%d + %d = %d\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $200, %rsp .cfi_def_cfa_offset 224 movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax movq %rsp, %rdi movl $40, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $40, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $40, %esi call cudaMalloc@PLT movl $0, %eax .L12: movl %eax, 48(%rsp,%rax,4) leal (%rax,%rax), %edx movl %edx, 96(%rsp,%rax,4) addq $1, %rax cmpq $10, %rax jne .L12 leaq 48(%rsp), %rsi movl $1, %ecx movl $40, %edx movq (%rsp), %rdi call cudaMemcpy@PLT leaq 96(%rsp), %rsi movl $1, %ecx movl $40, %edx movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $10, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $0, %r9d movl $0, %r8d movq 36(%rsp), %rdx movl $1, %ecx movq 24(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L19 .L13: leaq 144(%rsp), %rdi movl $2, %ecx movl $40, %edx movq 16(%rsp), %rsi call cudaMemcpy@PLT movl $0, %ebx leaq .LC0(%rip), %rbp .L14: movl 96(%rsp,%rbx), %ecx movl 48(%rsp,%rbx), %edx movl 144(%rsp,%rbx), %r8d movq %rbp, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq $40, %rbx jne .L14 movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 184(%rsp), %rax subq %fs:40, %rax jne .L20 movl $0, %eax addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z26__device_stub__Z3addPiS_S_PiS_S_ jmp .L13 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC1: .string "_Z3addPiS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z3addPiS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z3addPiS_S_ ; -- Begin function _Z3addPiS_S_ .globl _Z3addPiS_S_ .p2align 8 .type _Z3addPiS_S_,@function _Z3addPiS_S_: ; @_Z3addPiS_S_ ; %bb.0: s_mov_b32 s2, exec_lo v_cmpx_gt_u32_e32 10, v0 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x0 v_lshlrev_b32_e32 v0, 2, v0 s_load_b64 s[0:1], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b32 v1, v0, s[4:5] global_load_b32 v2, v0, s[6:7] s_waitcnt vmcnt(0) v_add_nc_u32_e32 v1, v2, v1 global_store_b32 v0, v1, s[0:1] .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z3addPiS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 8 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 84 ; NumSgprs: 8 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 8 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z3addPiS_S_ .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z3addPiS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "744e787f0488a88a81816ad04359df176467398a.hip" .globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_ .p2align 4, 0x90 .type _Z18__device_stub__addPiS_S_,@function _Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3addPiS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $240, %rsp .cfi_def_cfa_offset 256 .cfi_offset %rbx, -16 leaq 16(%rsp), %rdi movl $40, %esi callq hipMalloc leaq 8(%rsp), %rdi movl $40, %esi callq hipMalloc movq %rsp, %rdi movl $40, %esi callq hipMalloc xorl %eax, %eax xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl %ecx, 192(%rsp,%rcx,4) movl %eax, 144(%rsp,%rcx,4) incq %rcx addl $2, %eax cmpq $10, %rcx jne .LBB1_1 # %bb.2: movq 16(%rsp), %rdi leaq 192(%rsp), %rsi movl $40, %edx movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi leaq 144(%rsp), %rsi movl $40, %edx movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 9(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 16(%rsp), %rax movq 8(%rsp), %rcx movq (%rsp), %rdx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movq %rdx, 72(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z3addPiS_S_, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: movq (%rsp), %rsi leaq 96(%rsp), %rdi movl $40, %edx movl $2, %ecx callq hipMemcpy xorl %ebx, %ebx .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 movl 192(%rsp,%rbx,4), %esi movl 144(%rsp,%rbx,4), %edx movl 96(%rsp,%rbx,4), %ecx movl $.L.str, %edi xorl %eax, %eax callq printf incq %rbx cmpq $10, %rbx jne .LBB1_5 # %bb.6: movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree xorl %eax, %eax addq $240, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3addPiS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z3addPiS_S_,@object # @_Z3addPiS_S_ .section .rodata,"a",@progbits .globl _Z3addPiS_S_ .p2align 3, 0x0 _Z3addPiS_S_: .quad _Z18__device_stub__addPiS_S_ .size _Z3addPiS_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%d + %d = %d\n" .size .L.str, 14 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z3addPiS_S_" .size .L__unnamed_1, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__addPiS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3addPiS_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
446
2,909
1,810
2,996
136
code for sm_80 Function : _Z7computefiffffiffffffffffffffff .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; IADD3 R1, R1, -0x8, RZ ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x164] ; ULDC UR4, c[0x0][0x20] ; R2UR UR6, R1 ; ULDC UR7, c[0x0][0x24] ; ISETP.GE.AND P0, PT, R0, 0x1, PT ; MOV R0, c[0x0][0x160] ; UIADD3 UR6, UP0, UR6, UR4, URZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; @!P0 BRA 0x2070 ; HFMA2.MMA R4, -RZ, RZ, 35488, -0.059478759765625 ; ULDC UR4, c[0x0][0x174] ; IMAD.MOV.U32 R3, RZ, RZ, 0x6995b94 ; IMAD.U32 R5, RZ, RZ, UR4 ; FCHK P0, R5, -1.73349994020571478128e+34 ; FFMA R2, -R3, R4, 1 ; FFMA R2, R2, -R3, -5.7686765377004693013e-35 ; FFMA R3, R2, c[0x0][0x174], RZ ; FFMA R4, R3, R4, c[0x0][0x174] ; FFMA R2, R2, R4, R3 ; @!P0 BRA 0x1b0 ; MOV R23, c[0x0][0x174] ; IMAD.MOV.U32 R20, RZ, RZ, -0x7aa5463 ; MOV R2, 0x1a0 ; CALL.REL.NOINC 0x2300 ; MOV R2, R19 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x170] ; MOV R7, 0x3c80f082 ; FADD R2, R2, 1.90939998424437076423e+36 ; IMAD.MOV.U32 R5, RZ, RZ, 0x3f800000 ; FFMA R2, R3, 1.6815581571897804851e-44, R2 ; FMUL R3, |R2|.reuse, 2.8853900432586669922 ; FSETP.GE.AND P1, PT, |R2|.reuse, 0.60000002384185791016, PT ; FMUL R6, R2.reuse, R2 ; FSETP.GE.AND P0, PT, |R2|, 9.010913848876953125, PT ; MUFU.EX2 R3, R3 ; FFMA R7, R6, R7, -0.052303962409496307373 ; FFMA R7, R6, R7, 0.1331529766321182251 ; FFMA R7, R6, R7, -0.33332768082618713379 ; FFMA R7, R6, R7, RZ ; FADD R4, R3, 1 ; MUFU.RCP R4, R4 ; FFMA R5, R4, -2, R5 ; FSEL R5, R5, 1, !P0 ; LOP3.LUT R5, R5, 0x80000000, R2.reuse, 0xf8, !PT ; @!P1 FFMA R5, R2, R7, R2 ; FADD R3, -R5, -1.2611686178923353638e-44 ; MUFU.RSQ R4, R3 ; IADD3 R2, R3, -0xd000000, RZ ; ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ; @!P0 BRA 0x380 ; MOV R19, 0x360 ; CALL.REL.NOINC 0x2180 ; MOV R2, R17 ; BRA 0x3c0 ; FMUL.FTZ R2, R3, R4 ; FMUL.FTZ R4, R4, 0.5 ; FFMA R3, -R2, R2, R3 ; FFMA R2, R3, R4, R2 ; FMUL R20, R2, c[0x0][0x16c] ; UMOV UR4, 0x78378ede ; IMAD.U32 R7, RZ, RZ, UR4 ; MUFU.RCP R2, R20 ; FCHK P0, -R7, R20 ; FFMA R3, -R20, R2, 1 ; FFMA R3, R2, R3, R2 ; FFMA R2, R3, -1.48920002488698462485e+34, RZ ; FFMA R4, -R20, R2, -1.48920002488698462485e+34 ; FFMA R5, R3, R4, R2 ; @!P0 BRA 0x4b0 ; HFMA2.MMA R23, -RZ, RZ, -34528, -0.000419139862060546875 ; MOV R2, 0x4a0 ; CALL.REL.NOINC 0x2300 ; IMAD.MOV.U32 R5, RZ, RZ, R19 ; ULDC UR4, c[0x0][0x184] ; MOV R3, 0x7976a83c ; IMAD.MOV.U32 R6, RZ, RZ, 0x584d92e ; MOV R8, UR4 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x188] ; MOV R7, 0x41c7cc3 ; FFMA R2, -R3, R6, 1 ; FCHK P0, R8, -1.2492999562111356012e-35 ; FADD R5, R5, c[0x0][0x168] ; FFMA R2, R2, -R3, -8.00448266064207458194e+34 ; FFMA R4, R4, -R7, 1.1215999724371566312e-35 ; FFMA R3, R2, c[0x0][0x184], RZ ; FFMA R6, R3, R6, c[0x0][0x184] ; FFMA R3, R2, R6, R3 ; @!P0 BRA 0x5f0 ; HFMA2.MMA R20, -RZ, RZ, -8.41617584228515625e-05, -165.75 ; IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x184] ; MOV R2, 0x5e0 ; CALL.REL.NOINC 0x2300 ; IMAD.MOV.U32 R3, RZ, RZ, R19 ; MOV R2, c[0x0][0x194] ; FADD R4, R4, R3 ; UMOV UR4, 0x79c26159 ; IMAD.MOV.U32 R3, RZ, RZ, 0x35a80a64 ; MOV R11, UR4 ; FMUL R2, R2, -1.0537764451722624373e-42 ; FADD R4, R4, -1.1630777253895981689e-43 ; FFMA R10, R2, R3, c[0x0][0x190] ; FSETP.GEU.AND P1, PT, R4.reuse, 1.175494350822287508e-38, PT ; MUFU.RCP R3, R10 ; FCHK P0, -R11, R10 ; @!P1 FMUL R4, R4, 8388608 ; FFMA R6, -R10, R3, 1 ; IADD3 R2, R4, -0x3f2aaaab, RZ ; FFMA R7, R3, R6, R3 ; LOP3.LUT R3, R2, 0xff800000, RZ, 0xc0, !PT ; FFMA R2, R7, -1.26160004449221817687e+35, RZ ; I2F R6, R3 ; IMAD.IADD R8, R4, 0x1, -R3 ; FFMA R9, -R10, R2, -1.26160004449221817687e+35 ; FADD R8, R8, -1 ; FFMA R7, R7, R9, R2 ; FSEL R9, RZ, -23, P1 ; @!P0 BRA 0x7c0 ; MOV R20, R10 ; IMAD.MOV.U32 R23, RZ, RZ, -0x63d9ea7 ; MOV R2, 0x7b0 ; CALL.REL.NOINC 0x2300 ; MOV R7, R19 ; MUFU.RCP R2, c[0x0][0x19c] ; ULDC UR4, c[0x0][0x198] ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x19c] ; MOV R12, UR4 ; FCHK P0, R12, c[0x0][0x19c] ; FFMA R3, R2, -R11, 1 ; FFMA R3, R2, R3, R2 ; FFMA R10, R3, c[0x0][0x198], RZ ; FFMA R2, R10, -R11, c[0x0][0x198] ; FFMA R10, R3, R2, R10 ; @!P0 BRA 0x8c0 ; IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x198] ; MOV R20, c[0x0][0x19c] ; MOV R2, 0x8b0 ; CALL.REL.NOINC 0x2300 ; IMAD.MOV.U32 R10, RZ, RZ, R19 ; MUFU.RCP R2, c[0x0][0x1b4] ; ULDC UR4, c[0x0][0x1b0] ; MOV R11, c[0x0][0x1b4] ; IMAD.U32 R12, RZ, RZ, UR4 ; FCHK P0, R12, c[0x0][0x1b4] ; FFMA R3, R2, -R11, 1 ; FFMA R3, R2, R3, R2 ; FFMA R2, R3, c[0x0][0x1b0], RZ ; FFMA R11, R2, -R11, c[0x0][0x1b0] ; FFMA R2, R3, R11, R2 ; @!P0 BRA 0x9c0 ; MOV R23, c[0x0][0x1b0] ; IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x1b4] ; MOV R2, 0x9b0 ; CALL.REL.NOINC 0x2300 ; MOV R2, R19 ; MUFU.RCP R3, c[0x0][0x1b8] ; IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x1b8] ; FCHK P0, R2, c[0x0][0x1b8] ; FFMA R12, R3, -R12, 1 ; FFMA R3, R3, R12, R3 ; FFMA R11, R3, R2, RZ ; FFMA R12, R11, -c[0x0][0x1b8], R2 ; FFMA R3, R3, R12, R11 ; @!P0 BRA 0xaa0 ; MOV R23, R2 ; IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x1b8] ; MOV R2, 0xa90 ; CALL.REL.NOINC 0x2300 ; MOV R3, R19 ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x1a8] ; UMOV UR4, 0x6b0cb413 ; MOV R13, UR4 ; FFMA R20, R2, c[0x0][0x1ac], R3 ; MUFU.RCP R2, R20 ; FCHK P0, R13, R20 ; FFMA R3, -R20, R2, 1 ; FFMA R3, R2, R3, R2 ; FFMA R2, R3, 1.70099991201102021079e+26, RZ ; FFMA R11, -R20, R2, 1.70099991201102021079e+26 ; FFMA R11, R3, R11, R2 ; @!P0 BRA 0xba0 ; IMAD.MOV.U32 R23, RZ, RZ, 0x6b0cb413 ; MOV R2, 0xb90 ; CALL.REL.NOINC 0x2300 ; MOV R11, R19 ; FADD R12, R7, R7 ; ULDC UR4, c[0x0][0x178] ; LOP3.LUT R13, R11.reuse, 0x80000000, RZ, 0xc0, !PT ; ULOP3.LUT UR9, UR4, 0x3, URZ, 0xc0, !UPT ; FMUL R14, R11, R11 ; LOP3.LUT R15, R12, 0x7f800000, RZ, 0x3c, !PT ; IMAD.MOV.U32 R21, RZ, RZ, RZ ; UIADD3 UR8, UR4, -0x1, URZ ; UIADD3 UR4, -UR9, UR4, URZ ; FSETP.GTU.AND P0, PT, R0, R5, PT ; IADD3 R21, R21, 0x1, RZ ; ISETP.GE.AND P1, PT, R21, c[0x0][0x164], PT ; @P0 BRA 0x2050 ; HFMA2.MMA R3, -RZ, RZ, 1.5048828125, 33.21875 ; ISETP.GE.U32.AND P0, PT, R4, 0x7f800000, PT ; FFMA R2, R6, 1.1920928955078125e-07, R9 ; ULDC UR5, c[0x0][0x17c] ; IMAD.U32 R19, RZ, RZ, UR5 ; FFMA R3, R8, -R3, 0.14084610342979431152 ; FFMA R3, R8.reuse, R3, -0.12148627638816833496 ; @P0 IMAD.MOV.U32 R17, RZ, RZ, 0x7f800000 ; FFMA R3, R8, R3, 0.13980610668659210205 ; FFMA R3, R8, R3, -0.16684235632419586182 ; FFMA R3, R8, R3, 0.20012299716472625732 ; FFMA R3, R8, R3, -0.24999669194221496582 ; FFMA R3, R8, R3, 0.33333182334899902344 ; FFMA R3, R8, R3, -0.5 ; FMUL R3, R8, R3 ; FFMA R3, R8, R3, R8 ; FFMA R2, R2, 0.69314718246459960938, R3 ; MOV R3, c[0x0][0x180] ; @P0 FFMA R2, R4.reuse, R17, +INF ; FSETP.NEU.AND P0, PT, R4, RZ, PT ; FSEL R2, R2, -INF , P0 ; FFMA R20, -R2, R3, -1.2620999769036642102e-36 ; MUFU.RCP R2, R20 ; FCHK P0, R19, R20 ; FFMA R3, -R20, R2, 1 ; FFMA R3, R2, R3, R2 ; FFMA R2, R3, c[0x0][0x17c], RZ ; FFMA R17, -R20, R2, c[0x0][0x17c] ; FFMA R3, R3, R17, R2 ; @!P0 BRA 0xe90 ; MOV R23, c[0x0][0x17c] ; MOV R2, 0xe80 ; CALL.REL.NOINC 0x2300 ; IMAD.MOV.U32 R3, RZ, RZ, R19 ; MOV R2, c[0x0][0x178] ; FADD R0, R0, R3 ; ISETP.GE.AND P0, PT, R2, 0x1, PT ; @!P0 BRA 0x2050 ; FMUL R0, |R11|.reuse, 2.8853900432586669922 ; HFMA2.MMA R3, -RZ, RZ, 1.875, 0 ; IMAD.MOV.U32 R17, RZ, RZ, 0x3c80f082 ; FSETP.GE.AND P2, PT, |R11|, 0.60000002384185791016, PT ; FMUL R20, |R7|, 16777216 ; FSETP.GE.AND P0, PT, |R11|, 9.010913848876953125, PT ; MUFU.EX2 R0, R0 ; FFMA R17, R14.reuse, R17, -0.052303962409496307373 ; FSETP.GEU.AND P3, PT, |R7|, 1.175494350822287508e-38, PT ; HFMA2.MMA R25, -RZ, RZ, 0.771484375, 0.21533203125 ; FFMA R17, R14, R17, 0.1331529766321182251 ; FSEL R20, R20, |R7|, !P3 ; FFMA R17, R14, R17, -0.33332768082618713379 ; FADD R2, R0, 1 ; FFMA R0, R14, R17, RZ ; MOV R17, 0x3f000000 ; MUFU.RCP R2, R2 ; FFMA R3, R2, -2, R3 ; FSEL R18, R3, 1, !P0 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1a4] ; LOP3.LUT R18, R13, R18, RZ, 0xfc, !PT ; @!P2 FFMA R18, R0, R11, R11 ; FFMA R0, R18, R3, c[0x0][0x1a0] ; FFMA R2, -|R0|.reuse, R17, 0.5 ; FSETP.NEU.AND P2, PT, |R0|.reuse, 1, PT ; FSETP.GT.AND P0, PT, |R0|, 0.56000000238418579102, PT ; MUFU.RSQ R3, R2 ; FMUL R17, R2, R3 ; IADD3 R2, R20, -0x3f3504f3, RZ ; FMUL R18, R3, 0.5 ; LOP3.LUT R23, R2, 0xff800000, RZ, 0xc0, !PT ; FFMA R18, -R17, R18, 0.5 ; IADD3 R19, R20, -R23, RZ ; FFMA R18, R17, R18, R17 ; I2F R22, R23 ; FADD R24, R19, 1 ; FSEL R3, R18, RZ, P2 ; IMAD.MOV.U32 R18, RZ, RZ, 0x3d4dd2f7 ; FSEL R3, R3, |R0|, P0 ; LOP3.LUT R0, R0, 0x80000000, RZ, 0xc0, !PT ; FMUL R17, R3, R3 ; FFMA R2, R17, R18, 0.018773360177874565125 ; FFMA R2, R17, R2, 0.046769052743911743164 ; FFMA R18, R17.reuse, R2, 0.074823014438152313232 ; MUFU.RCP R2, R24 ; FFMA R18, R17, R18, 0.16667181253433227539 ; FMUL R20, R17, R18 ; FADD R18, R19, -1 ; FFMA R17, R3, R20, R3 ; IMAD.MOV.U32 R20, RZ, RZ, 0x3fd774eb ; FMUL R19, R17, -2 ; FADD R3, R18, R18 ; @P0 FFMA R17, R20, 0.93318945169448852539, R19 ; FSEL R19, RZ, -24, P3 ; FMUL R3, R2, R3 ; FSETP.GTU.AND P0, PT, R17, +INF , PT ; FADD R24, R18, -R3 ; FFMA R22, R22, 1.1920928955078125e-07, R19 ; FMUL R20, R3.reuse, R3 ; FADD R24, R24, R24 ; FFMA R19, R3, 1.4426950216293334961, R22 ; FFMA R25, R20, R25, 0.0032181653659790754318 ; FFMA R23, R18, -R3, R24 ; @!P0 LOP3.LUT R17, R0, R17, RZ, 0xfc, !PT ; FADD R22, R22, -R19 ; FFMA R25, R20, R25, 0.018033718690276145935 ; FMUL R2, R2, R23 ; FFMA R23, R3, 1.4426950216293334961, R22 ; FFMA R25, R20, R25, 0.12022458761930465698 ; FADD R0, -R17, R10 ; FFMA R18, R2, 1.4426950216293334961, R23 ; FMUL R20, R20, R25 ; FFMA R17, R3, 1.9251366722983220825e-08, R18 ; FRND.FLOOR R0, R0 ; FMUL R18, R20, 3 ; FFMA R17, R2, R18, R17 ; FFMA R20, R3, R20, R17 ; FADD R17, R19, R20 ; FMUL R3, R0.reuse, R17.reuse ; FADD R19, -R19, R17 ; FRND R2, R3 ; FFMA R17, R0, R17, -R3 ; FSETP.GT.AND P2, PT, |R3|.reuse, 152, PT ; FADD R19, R20, -R19 ; FSETP.GEU.AND P3, PT, R3, RZ, PT ; IMAD.MOV.U32 R20, RZ, RZ, 0x391fcb8e ; FFMA R17, R0, R19, R17 ; F2I.NTZ R19, R3 ; FADD R18, R3, -R2 ; FSETP.GT.AND P0, PT, R2, RZ, PT ; FMUL R2, R0, 0.5 ; FADD R17, R17, R18 ; FFMA R18, R17.reuse, R20, 0.0013391353422775864601 ; SEL R20, RZ, 0x83000000, P0 ; FRND.TRUNC R2, R2 ; FSETP.NEU.AND P0, PT, R0, RZ, PT ; FFMA R18, R17, R18, 0.0096188392490148544312 ; FSETP.EQ.OR P0, PT, R7, 1, !P0 ; FFMA R18, R17, R18, 0.055503588169813156128 ; FFMA R18, R17, R18, 0.24022644758224487305 ; FFMA R18, R17.reuse, R18, 0.69314718246459960938 ; FADD R3, R2, R2 ; FFMA R18, R17, R18, 1 ; IADD3 R17, R20, 0x7f000000, RZ ; LEA R20, R19, -R20, 0x17 ; FMUL R17, R18, R17 ; FMUL R17, R17, R20 ; @P2 FSEL R17, RZ, +INF , !P3 ; @P0 BRA 0x1e10 ; FSETP.GTU.AND P0, PT, |R7|, +INF , PT ; @P0 BRA 0x1da0 ; FSETP.NEU.AND P0, PT, |R7|.reuse, +INF , PT ; FADD R3, R0.reuse, -R3 ; FSETP.GEU.AND P3, PT, R0, RZ, PT ; FSETP.EQ.OR P0, PT, R7, RZ, !P0 ; FSETP.NEU.AND P2, PT, |R3|, 1, PT ; SEL R2, R15, R12, !P3 ; @P2 LOP3.LUT R2, R2, 0x7fffffff, RZ, 0xc0, !PT ; @P0 BRA 0x1a40 ; UISETP.GE.U32.AND UP0, UPT, UR8, 0x3, UPT ; FSEL R2, -R17, R17, !P2 ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; @!P0 BRA 0x1790 ; FSETP.NEU.AND P0, PT, |R0|.reuse, +INF , PT ; UMOV UR5, UR4 ; FSETP.GTU.AND P3, PT, |R0|, +INF , PT ; FSETP.EQ.AND P0, PT, R7, -1, !P0 ; FSETP.GEU.OR P2, PT, R7, RZ, P0 ; FSEL R18, R17, 1, !P0 ; UIADD3 UR5, UR5, -0x4, URZ ; ISETP.NE.AND P4, PT, RZ, UR5, PT ; @P3 BRA 0x1770 ; IMAD.MOV.U32 R16, RZ, RZ, R18 ; @P2 BRA 0x1780 ; FRND.FLOOR R3, R0 ; FSETP.NEU.AND P0, PT, R3, R0, PT ; FSEL R16, R2, +QNAN , !P0 ; BRA 0x1780 ; FADD R16, R0, R7 ; @P4 BRA 0x16e0 ; ISETP.NE.AND P0, PT, RZ, UR9, PT ; @!P0 BRA 0x1f70 ; FSETP.GTU.AND P2, PT, |R0|, +INF , PT ; @P2 BRA 0x1860 ; FSETP.NEU.AND P0, PT, |R0|, +INF , PT ; FSETP.EQ.AND P0, PT, R7, -1, !P0 ; FSETP.GEU.OR P3, PT, R7, RZ, P0 ; FSEL R16, R17, 1, !P0 ; @P3 BRA 0x1870 ; FRND.FLOOR R3, R0 ; FSETP.NEU.AND P0, PT, R3, R0, PT ; FSEL R16, R2, +QNAN , !P0 ; BRA 0x1870 ; FADD R16, R0, R7 ; UISETP.NE.AND UP0, UPT, UR9, 0x1, UPT ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; @!P0 BRA 0x1f70 ; @P2 BRA 0x1940 ; FSETP.NEU.AND P0, PT, |R0|, +INF , PT ; FSETP.EQ.AND P0, PT, R7, -1, !P0 ; FSETP.GEU.OR P3, PT, R7, RZ, P0 ; FSEL R16, R17, 1, !P0 ; @P3 BRA 0x1950 ; FRND.FLOOR R3, R0 ; FSETP.NEU.AND P0, PT, R3, R0, PT ; FSEL R16, R2, +QNAN , !P0 ; BRA 0x1950 ; FADD R16, R0, R7 ; UISETP.NE.AND UP0, UPT, UR9, 0x2, UPT ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; @!P0 BRA 0x1f70 ; @P2 BRA 0x1a20 ; FSETP.NEU.AND P0, PT, |R0|, +INF , PT ; FSETP.EQ.AND P0, PT, R7, -1, !P0 ; FSETP.GEU.OR P2, PT, R7, RZ, P0 ; FSEL R16, R17, 1, !P0 ; @P2 BRA 0x1f70 ; FRND.FLOOR R3, R0 ; FSETP.NEU.AND P0, PT, R3, R0, PT ; FSEL R16, R2, +QNAN , !P0 ; BRA 0x1f70 ; FADD R16, R0, R7 ; BRA 0x1f70 ; UISETP.GE.U32.AND UP0, UPT, UR8, 0x3, UPT ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; @!P0 BRA 0x1c90 ; ISETP.LT.AND P0, PT, RZ, UR4, PT ; UMOV UR5, UR4 ; @!P0 BRA 0x1c20 ; UISETP.GT.AND UP0, UPT, UR5, 0xc, UPT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; PLOP3.LUT P2, PT, PT, PT, UP0, 0x80, 0x0 ; @!P2 BRA 0x1b70 ; FSETP.GTU.AND P2, PT, |R0|, +INF , PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; @P2 FADD R3, R0, R7 ; UIADD3 UR5, UR5, -0x10, URZ ; MOV R16, R2 ; @P2 IMAD.MOV.U32 R16, RZ, RZ, R3 ; UISETP.GT.AND UP0, UPT, UR5, 0xc, UPT ; PLOP3.LUT P3, PT, PT, PT, UP0, 0x80, 0x0 ; @P3 BRA 0x1b10 ; UISETP.GT.AND UP0, UPT, UR5, 0x4, UPT ; PLOP3.LUT P2, PT, PT, PT, UP0, 0x80, 0x0 ; @!P2 BRA 0x1c00 ; FSETP.GTU.AND P2, PT, |R0|, +INF , PT ; UIADD3 UR5, UR5, -0x4, URZ ; MOV R16, R2 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; UIADD3 UR5, UR5, -0x4, URZ ; @P2 FADD R16, R0, R7 ; ISETP.NE.OR P0, PT, RZ, UR5, P0 ; @!P0 BRA 0x1c90 ; FSETP.GTU.AND P2, PT, |R0|, +INF , PT ; @P2 FADD R3, R0, R7 ; UIADD3 UR5, UR5, -0x4, URZ ; IMAD.MOV.U32 R16, RZ, RZ, R2 ; @P2 MOV R16, R3 ; ISETP.NE.AND P0, PT, RZ, UR5, PT ; @P0 BRA 0x1c40 ; ISETP.NE.AND P0, PT, RZ, UR9, PT ; @!P0 BRA 0x1f70 ; UISETP.NE.AND UP0, UPT, UR9, 0x1, UPT ; FSETP.GTU.AND P2, PT, |R0|, +INF , PT ; IMAD.MOV.U32 R16, RZ, RZ, R2 ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; @P2 FADD R16, R0, R7 ; @!P0 BRA 0x1f70 ; MOV R16, UR9 ; IMAD.MOV.U32 R3, RZ, RZ, R2 ; @P2 FADD R3, R0, R7 ; ISETP.NE.AND P3, PT, R16, 0x2, PT ; FSETP.LE.OR P0, PT, |R0|, +INF , !P3 ; FSEL R16, R3, R2, !P3 ; @P0 BRA 0x1f70 ; FADD R16, R0, R7 ; BRA 0x1f70 ; UISETP.GE.U32.AND UP0, UPT, UR8, 0x3, UPT ; ISETP.NE.AND P0, PT, RZ, UR9, PT ; PLOP3.LUT P2, PT, PT, PT, UP0, 0x80, 0x0 ; @P2 FADD R16, R0, R7 ; @!P0 BRA 0x1f70 ; FADD R16, R0, R7 ; BRA 0x1f70 ; UISETP.GE.U32.AND UP0, UPT, UR8, 0x3, UPT ; MOV R16, 0x3f800000 ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; @!P0 BRA 0x1f70 ; ISETP.LT.AND P0, PT, RZ, UR4, PT ; IMAD.U32 R0, RZ, RZ, UR4 ; @!P0 BRA 0x1f60 ; ISETP.GT.AND P2, PT, R0, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0x1f00 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R0, R0, -0x10, RZ ; ISETP.GT.AND P2, PT, R0, 0xc, PT ; @P2 BRA 0x1ec0 ; HFMA2.MMA R16, -RZ, RZ, 1.875, 0 ; ISETP.GT.AND P2, PT, R0, 0x4, PT ; @P2 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; @P2 IMAD.MOV.U32 R16, RZ, RZ, 0x3f800000 ; @P2 IADD3 R0, R0, -0x8, RZ ; ISETP.NE.OR P0, PT, R0, RZ, P0 ; @!P0 BRA 0x1f70 ; MOV R16, 0x3f800000 ; FADD R3, R16, c[0x0][0x18c] ; MUFU.RSQ R2, R3 ; IADD3 R0, R3, -0xd000000, RZ ; ISETP.GT.U32.AND P0, PT, R0, 0x727fffff, PT ; @!P0 BRA 0x2000 ; MOV R19, 0x1fe0 ; CALL.REL.NOINC 0x2180 ; IMAD.MOV.U32 R0, RZ, RZ, R17 ; BRA 0x2040 ; FMUL.FTZ R0, R3, R2 ; FMUL.FTZ R2, R2, 0.5 ; FFMA R3, -R0, R0, R3 ; FFMA R0, R3, R2, R0 ; FADD R0, R0, -3.3133384409614677346e-14 ; @P1 CALL.REL.NOINC 0x2070 ; BRA 0xc30 ; F2F.F64.F32 R2, R0 ; MOV R8, 0x0 ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; MOV R4, c[0x4][0x8] ; IMAD.U32 R7, RZ, RZ, UR7 ; MOV R6, UR6 ; LDC.64 R8, c[0x4][R8] ; STL.64 [R1], R2 ; LEPC R2 ; MOV R11, 0x2170 ; MOV R20, 0x20f0 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R11, R2 ; IADD3.X R21, ~R0, R21, R3, P0, P1 ; CALL.ABS.NOINC R8 ; EXIT ; LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; @!P0 MOV R2, R3 ; @!P0 BRA 0x22c0 ; FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; @!P0 IMAD.MOV.U32 R2, RZ, RZ, 0x7fffffff ; @!P0 BRA 0x22c0 ; FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; @P0 FADD.FTZ R2, R3, 1 ; @P0 BRA 0x22c0 ; FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; @!P0 MOV R2, R3 ; @!P0 BRA 0x22c0 ; FFMA R3, R3, 1.84467440737095516160e+19, RZ ; MUFU.RSQ R2, R3 ; FMUL.FTZ R18, R3, R2 ; FMUL.FTZ R2, R2, 0.5 ; FADD.FTZ R17, -R18, -RZ ; FFMA R17, R18, R17, R3 ; FFMA R2, R17, R2, R18 ; FMUL.FTZ R2, R2, 2.3283064365386962891e-10 ; IMAD.MOV.U32 R17, RZ, RZ, R2 ; MOV R2, R19 ; IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; RET.REL.NODEC R2 0x0 ; SHF.R.U32.HI R3, RZ, 0x17, R20 ; SHF.R.U32.HI R18, RZ, 0x17, R23 ; LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; LOP3.LUT R18, R18, 0xff, RZ, 0xc0, !PT ; IADD3 R22, R3, -0x1, RZ ; IADD3 R19, R18, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R22, 0xfd, PT ; ISETP.GT.U32.OR P0, PT, R19, 0xfd, P0 ; @!P0 MOV R17, RZ ; @!P0 BRA 0x2510 ; FSETP.GTU.FTZ.AND P0, PT, |R23|, +INF , PT ; FSETP.GTU.FTZ.AND P2, PT, |R20|, +INF , PT ; PLOP3.LUT P0, PT, P0, P2, PT, 0xa8, 0x0 ; @P0 BRA 0x28f0 ; LOP3.LUT P0, RZ, R20, 0x7fffffff, R23, 0xc8, !PT ; @!P0 BRA 0x28d0 ; FSETP.NEU.FTZ.AND P2, PT, |R23|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P3, PT, |R20|, +INF , PT ; FSETP.NEU.FTZ.AND P0, PT, |R23|, +INF , PT ; @!P3 BRA !P2, 0x28d0 ; LOP3.LUT P2, RZ, R23, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P2, PT, P3, P2, PT, 0x2a, 0x0 ; @P2 BRA 0x28b0 ; LOP3.LUT P2, RZ, R20, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P2, PT, 0x2a, 0x0 ; @P0 BRA 0x2880 ; ISETP.GE.AND P0, PT, R19, RZ, PT ; ISETP.GE.AND P2, PT, R22, RZ, PT ; @P0 IMAD.MOV.U32 R17, RZ, RZ, RZ ; @!P0 MOV R17, 0xffffffc0 ; @!P0 FFMA R23, R23, 1.84467440737095516160e+19, RZ ; @!P2 FFMA R20, R20, 1.84467440737095516160e+19, RZ ; @!P2 IADD3 R17, R17, 0x40, RZ ; LEA R19, R3, 0xc0800000, 0x17 ; IADD3 R18, R18, -0x7f, RZ ; IMAD.IADD R24, R20, 0x1, -R19 ; IMAD R22, R18.reuse, -0x800000, R23 ; IADD3 R18, R18, 0x7f, -R3 ; MUFU.RCP R20, R24 ; FADD.FTZ R19, -R24, -RZ ; IADD3 R18, R18, R17, RZ ; FFMA R25, R20, R19, 1 ; FFMA R20, R20, R25, R20 ; FFMA R23, R22, R20, RZ ; FFMA R25, R19, R23, R22 ; FFMA R23, R20, R25, R23 ; FFMA R22, R19, R23, R22 ; FFMA R19, R20, R22, R23 ; SHF.R.U32.HI R3, RZ, 0x17, R19 ; LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; IMAD.IADD R3, R3, 0x1, R18 ; IADD3 R17, R3, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R17, 0xfe, PT ; @!P0 BRA 0x2860 ; ISETP.GT.AND P0, PT, R3, 0xfe, PT ; @P0 BRA 0x2830 ; ISETP.GE.AND P0, PT, R3, 0x1, PT ; @P0 BRA 0x2900 ; ISETP.GE.AND P0, PT, R3, -0x18, PT ; LOP3.LUT R19, R19, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0x2900 ; FFMA.RZ R17, R20.reuse, R22.reuse, R23.reuse ; ISETP.NE.AND P3, PT, R3.reuse, RZ, PT ; ISETP.NE.AND P2, PT, R3, RZ, PT ; LOP3.LUT R18, R17, 0x7fffff, RZ, 0xc0, !PT ; FFMA.RP R17, R20.reuse, R22.reuse, R23.reuse ; FFMA.RM R20, R20, R22, R23 ; IADD3 R23, R3, 0x20, RZ ; LOP3.LUT R18, R18, 0x800000, RZ, 0xfc, !PT ; IADD3 R3, -R3, RZ, RZ ; SHF.L.U32 R23, R18, R23, RZ ; FSETP.NEU.FTZ.AND P0, PT, R17, R20, PT ; SEL R3, R3, RZ, P3 ; ISETP.NE.AND P2, PT, R23, RZ, P2 ; SHF.R.U32.HI R3, RZ, R3, R18 ; PLOP3.LUT P0, PT, P0, P2, PT, 0xa8, 0x0 ; SHF.R.U32.HI R18, RZ, 0x1, R3 ; SEL R17, RZ, 0x1, !P0 ; LOP3.LUT R20, R17, 0x1, R18, 0xf8, !PT ; LOP3.LUT R3, R20, R3, RZ, 0xc0, !PT ; IMAD.IADD R18, R18, 0x1, R3 ; LOP3.LUT R19, R18, R19, RZ, 0xfc, !PT ; BRA 0x2900 ; LOP3.LUT R19, R19, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R19, R19, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x2900 ; LEA R19, R18, R19, 0x17 ; BRA 0x2900 ; LOP3.LUT R19, R20, 0x80000000, R23, 0x48, !PT ; LOP3.LUT R19, R19, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x2900 ; LOP3.LUT R19, R20, 0x80000000, R23, 0x48, !PT ; BRA 0x2900 ; MUFU.RSQ R19, -QNAN ; BRA 0x2900 ; FADD.FTZ R19, R23, R20 ; HFMA2.MMA R3, -RZ, RZ, 0, 0 ; RET.REL.NODEC R2 0x0 ; BRA 0x2920; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0006d3a5_00000000-6_71896bd9be10e0e0786f071665952c91ef3cd5b9.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z11initPointerf .type _Z11initPointerf, @function _Z11initPointerf: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movd %xmm0, %ebx movl $40, %edi call malloc@PLT movq %rax, %rdx leaq 40(%rax), %rcx .L4: movl %ebx, (%rdx) addq $4, %rdx cmpq %rcx, %rdx jne .L4 popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z11initPointerf, .-_Z11initPointerf .globl _Z47__device_stub__Z7computefiffffifffffffffffffffffiffffiffffffffffffffff .type _Z47__device_stub__Z7computefiffffifffffffffffffffffiffffiffffffffffffffff, @function _Z47__device_stub__Z7computefiffffifffffffffffffffffiffffiffffffffffffffff: .LFB2083: .cfi_startproc endbr64 subq $312, %rsp .cfi_def_cfa_offset 320 movss %xmm0, 44(%rsp) movl %edi, 40(%rsp) movss %xmm1, 36(%rsp) movss %xmm2, 32(%rsp) movss %xmm3, 28(%rsp) movss %xmm4, 24(%rsp) movl %esi, 20(%rsp) movss %xmm5, 16(%rsp) movss %xmm6, 12(%rsp) movss %xmm7, 8(%rsp) movq %fs:40, %rax movq %rax, 296(%rsp) xorl %eax, %eax leaq 44(%rsp), %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rax movq %rax, 120(%rsp) leaq 36(%rsp), %rax movq %rax, 128(%rsp) leaq 32(%rsp), %rax movq %rax, 136(%rsp) leaq 28(%rsp), %rax movq %rax, 144(%rsp) leaq 24(%rsp), %rax movq %rax, 152(%rsp) leaq 20(%rsp), %rax movq %rax, 160(%rsp) leaq 16(%rsp), %rax movq %rax, 168(%rsp) leaq 12(%rsp), %rax movq %rax, 176(%rsp) leaq 8(%rsp), %rax movq %rax, 184(%rsp) leaq 320(%rsp), %rax movq %rax, 192(%rsp) leaq 328(%rsp), %rax movq %rax, 200(%rsp) leaq 336(%rsp), %rax movq %rax, 208(%rsp) leaq 344(%rsp), %rax movq %rax, 216(%rsp) leaq 352(%rsp), %rax movq %rax, 224(%rsp) leaq 360(%rsp), %rax movq %rax, 232(%rsp) leaq 368(%rsp), %rax movq %rax, 240(%rsp) leaq 376(%rsp), %rax movq %rax, 248(%rsp) leaq 384(%rsp), %rax movq %rax, 256(%rsp) leaq 392(%rsp), %rax movq %rax, 264(%rsp) leaq 400(%rsp), %rax movq %rax, 272(%rsp) leaq 408(%rsp), %rax movq %rax, 280(%rsp) leaq 416(%rsp), %rax movq %rax, 288(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 296(%rsp), %rax subq %fs:40, %rax jne .L12 addq $312, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 328 pushq 56(%rsp) .cfi_def_cfa_offset 336 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z7computefiffffiffffffffffffffff(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 320 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z47__device_stub__Z7computefiffffifffffffffffffffffiffffiffffffffffffffff, .-_Z47__device_stub__Z7computefiffffifffffffffffffffffiffffiffffffffffffffff .globl _Z7computefiffffiffffffffffffffff .type _Z7computefiffffiffffffffffffffff, @function _Z7computefiffffiffffffffffffffff: .LFB2084: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movss 224(%rsp), %xmm8 movss %xmm8, 96(%rsp) movss 216(%rsp), %xmm8 movss %xmm8, 88(%rsp) movss 208(%rsp), %xmm8 movss %xmm8, 80(%rsp) movss 200(%rsp), %xmm8 movss %xmm8, 72(%rsp) movss 192(%rsp), %xmm8 movss %xmm8, 64(%rsp) movss 184(%rsp), %xmm8 movss %xmm8, 56(%rsp) movss 176(%rsp), %xmm8 movss %xmm8, 48(%rsp) movss 168(%rsp), %xmm8 movss %xmm8, 40(%rsp) movss 160(%rsp), %xmm8 movss %xmm8, 32(%rsp) movss 152(%rsp), %xmm8 movss %xmm8, 24(%rsp) movss 144(%rsp), %xmm8 movss %xmm8, 16(%rsp) movss 136(%rsp), %xmm8 movss %xmm8, 8(%rsp) movss 128(%rsp), %xmm8 movss %xmm8, (%rsp) call _Z47__device_stub__Z7computefiffffifffffffffffffffffiffffiffffffffffffffff addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z7computefiffffiffffffffffffffff, .-_Z7computefiffffiffffffffffffffff .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $208, %rsp .cfi_def_cfa_offset 240 movq %rsi, %rbx movq 8(%rsi), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 168(%rsp) movq 16(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %r12 movq 24(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 160(%rsp) movq 32(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 152(%rsp) movq 40(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 144(%rsp) movq 48(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 136(%rsp) movq 56(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %rbp movq 64(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 128(%rsp) movq 72(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 120(%rsp) movq 80(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 112(%rsp) movq 88(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 104(%rsp) movq 96(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 96(%rsp) movq 104(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 88(%rsp) movq 112(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 80(%rsp) movq 120(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 72(%rsp) movq 128(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 64(%rsp) movq 136(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 56(%rsp) movq 144(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 48(%rsp) movq 152(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 40(%rsp) movq 160(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 32(%rsp) movq 168(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 24(%rsp) movq 176(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 16(%rsp) movq 184(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 8(%rsp) movl $1, 196(%rsp) movl $1, 200(%rsp) movl $1, 184(%rsp) movl $1, 188(%rsp) movl $0, %r9d movl $0, %r8d movq 196(%rsp), %rdx movl $1, %ecx movq 184(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L18 .L16: call cudaDeviceSynchronize@PLT movl $0, %eax addq $208, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L18: .cfi_restore_state pxor %xmm0, %xmm0 cvtsd2ss 168(%rsp), %xmm0 subq $112, %rsp .cfi_def_cfa_offset 352 pxor %xmm1, %xmm1 cvtsd2ss 120(%rsp), %xmm1 movss %xmm1, 96(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 128(%rsp), %xmm1 movss %xmm1, 88(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 136(%rsp), %xmm1 movss %xmm1, 80(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 144(%rsp), %xmm1 movss %xmm1, 72(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 152(%rsp), %xmm1 movss %xmm1, 64(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 160(%rsp), %xmm1 movss %xmm1, 56(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 168(%rsp), %xmm1 movss %xmm1, 48(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 176(%rsp), %xmm1 movss %xmm1, 40(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 184(%rsp), %xmm1 movss %xmm1, 32(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 192(%rsp), %xmm1 movss %xmm1, 24(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 200(%rsp), %xmm1 movss %xmm1, 16(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 208(%rsp), %xmm1 movss %xmm1, 8(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 216(%rsp), %xmm1 movss %xmm1, (%rsp) pxor %xmm7, %xmm7 cvtsd2ss 224(%rsp), %xmm7 pxor %xmm6, %xmm6 cvtsd2ss 232(%rsp), %xmm6 pxor %xmm5, %xmm5 cvtsd2ss 240(%rsp), %xmm5 movl %ebp, %esi pxor %xmm4, %xmm4 cvtsd2ss 248(%rsp), %xmm4 pxor %xmm3, %xmm3 cvtsd2ss 256(%rsp), %xmm3 pxor %xmm2, %xmm2 cvtsd2ss 264(%rsp), %xmm2 pxor %xmm1, %xmm1 cvtsd2ss 272(%rsp), %xmm1 movl %r12d, %edi call _Z47__device_stub__Z7computefiffffifffffffffffffffffiffffiffffffffffffffff addq $112, %rsp .cfi_def_cfa_offset 240 jmp .L16 .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z7computefiffffiffffffffffffffff" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z7computefiffffiffffffffffffffff(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z7computefiffffiffffffffffffffff ; -- Begin function _Z7computefiffffiffffffffffffffff .globl _Z7computefiffffiffffffffffffffff .p2align 8 .type _Z7computefiffffiffffffffffffffff,@function _Z7computefiffffiffffffffffffffff: ; @_Z7computefiffffiffffffffffffffff ; %bb.0: s_load_b64 s[24:25], s[0:1], 0x0 s_waitcnt lgkmcnt(0) v_mov_b32_e32 v29, s24 s_cmp_lt_i32 s25, 1 s_cbranch_scc1 .LBB0_3 ; %bb.1: ; %.lr.ph409 s_load_b256 s[8:15], s[0:1], 0x8 s_mov_b32 s2, 0xf855ab9d s_mov_b32 s3, 0x8584d92e s_clause 0x1 s_load_b256 s[16:23], s[0:1], 0x28 s_load_b128 s[4:7], s[0:1], 0x48 v_mov_b32_e32 v29, s24 s_waitcnt lgkmcnt(0) v_div_scale_f32 v0, null, s2, s2, s11 v_div_scale_f32 v1, null, s3, s3, s15 s_load_b32 s3, s[0:1], 0x58 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_rcp_f32_e32 v2, v0 v_div_scale_f32 v6, vcc_lo, s11, 0xf855ab9d, s11 v_rcp_f32_e32 v3, v1 s_cmp_gt_i32 s12, 0 s_waitcnt_depctr 0xfff v_fma_f32 v4, -v0, v2, 1.0 v_fma_f32 v5, -v1, v3, 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fmac_f32_e32 v2, v4, v2 v_div_scale_f32 v4, s2, s15, 0x8584d92e, s15 v_fmac_f32_e32 v3, v5, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f32_e32 v5, v6, v2 v_mul_f32_e32 v7, v4, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v8, -v0, v5, v6 v_fma_f32 v9, -v1, v7, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmac_f32_e32 v5, v8, v2 v_fmac_f32_e32 v7, v9, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f32 v0, -v0, v5, v6 v_mov_b32_e32 v6, 0x841c7cc3 v_fma_f32 v1, -v1, v7, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fmas_f32 v2, v0, v2, v5 s_mov_b32 vcc_lo, s2 v_div_fmas_f32 v0, v1, v3, v7 v_fmaak_f32 v1, s16, v6, 0x56e89b6 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_div_fixup_f32 v2, v2, 0xf855ab9d, s11 v_div_fixup_f32 v0, v0, 0x8584d92e, s15 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v0, v1, v0 v_add_f32_e32 v0, 0x80000053, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo v_mul_f32_e32 v0, v0, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_log_f32_e32 v0, v0 s_waitcnt_depctr 0xfff v_mul_f32_e32 v1, 0x3f317217, v0 v_fma_f32 v3, v0, 0x3f317217, -v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v3, v0, 0x3377d1cf, v3 v_add_f32_e32 v1, v1, v3 v_cndmask_b32_e64 v3, 0, 0x41b17218, vcc_lo v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v0, v0, v1, vcc_lo v_sub_f32_e32 v0, v0, v3 v_div_scale_f32 v3, null, s7, s7, s6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v0, -v0, s14, 0x83d6bc35 v_rcp_f32_e32 v5, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f32 v1, null, v0, v0, s13 v_div_scale_f32 v8, vcc_lo, s13, v0, s13 v_rcp_f32_e32 v4, v1 s_waitcnt_depctr 0xfff v_fma_f32 v7, -v3, v5, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fmac_f32_e32 v5, v7, v5 v_fma_f32 v6, -v1, v4, 1.0 v_fmac_f32_e32 v4, v6, v4 v_div_scale_f32 v6, s2, s6, s7, s6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f32_e32 v7, v8, v4 v_mul_f32_e32 v9, v6, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v10, -v1, v7, v8 v_fma_f32 v11, -v3, v9, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmac_f32_e32 v7, v10, v4 v_fmac_f32_e32 v9, v11, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v1, -v1, v7, v8 v_fma_f32 v3, -v3, v9, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_div_fmas_f32 v1, v1, v4, v7 s_mov_b32 vcc_lo, s2 s_mov_b32 s2, 0x3d1c21a7 v_div_fmas_f32 v3, v3, v5, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_fixup_f32 v0, v1, v0, s13 v_div_fixup_f32 v3, v3, s7, s6 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f32 v4, null, s3, s3, v3 v_div_scale_f32 v7, vcc_lo, v3, s3, v3 v_rcp_f32_e32 v5, v4 s_waitcnt_depctr 0xfff v_fma_f32 v6, -v4, v5, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v5, v6, v5 v_mul_f32_e32 v6, v7, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v8, -v4, v6, v7 v_fmac_f32_e32 v6, v8, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v4, -v4, v6, v7 v_div_fmas_f32 v4, v4, v5, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f32 v3, v4, s3, v3 s_mov_b32 s3, 0xbbbac73d v_fmac_f32_e64 v3, s4, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f32 v4, null, v3, v3, 0x6b0cb413 v_div_scale_f32 v7, vcc_lo, 0x6b0cb413, v3, 0x6b0cb413 v_rcp_f32_e32 v5, v4 s_waitcnt_depctr 0xfff v_fma_f32 v6, -v4, v5, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v5, v6, v5 v_mul_f32_e32 v6, v7, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v8, -v4, v6, v7 v_fmac_f32_e32 v6, v8, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v4, -v4, v6, v7 v_div_fmas_f32 v4, v4, v5, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fixup_f32 v3, v4, v3, 0x6b0cb413 v_add_f32_e64 v4, |v3|, |v3| s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f32_e32 v5, 0x3fb8aa3b, v4 v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4 v_fma_f32 v6, v4, 0x3fb8aa3b, -v5 v_rndne_f32_e32 v7, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_fmac_f32 v6, 0x32a5705f, v4 :: v_dual_sub_f32 v5, v5, v7 v_add_f32_e32 v5, v5, v6 v_cvt_i32_f32_e32 v6, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_exp_f32_e32 v5, v5 s_waitcnt_depctr 0xfff v_ldexp_f32 v5, v5, v6 v_cndmask_b32_e32 v5, 0, v5, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v4, 0x7f800000, v5, vcc_lo v_cmp_gt_f32_e64 vcc_lo, 0x3f200000, |v3| v_add_f32_e32 v4, 1.0, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_rcp_f32_e32 v4, v4 s_waitcnt_depctr 0xfff v_fma_f32 v4, v4, -2.0, 1.0 v_mul_f32_e32 v7, v3, v3 v_fmaak_f32 v6, s3, v7, 0x3ca908c9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmaak_f32 v6, v7, v6, 0xbd5c1c4e v_fmaak_f32 v5, v7, v6, 0x3e088382 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmaak_f32 v5, v7, v5, 0xbeaaaa99 v_mul_f32_e64 v5, |v3|, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f32 v5, v7, v5, |v3| v_div_scale_f32 v7, null, s21, s21, s20 v_dual_cndmask_b32 v4, v4, v5 :: v_dual_mov_b32 v5, s18 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_bfi_b32 v3, 0x7fffffff, v4, v3 v_mul_f32_e64 v4, 0x800002f0, s19 v_fma_f32 v3, v3, s23, s22 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_mul_f32_e32 v6, v3, v3 v_cmp_ge_f32_e64 vcc_lo, |v3|, 0.5 v_fmamk_f32 v4, v4, 0x35a80a64, v5 v_fma_f32 v5, |v3|, -0.5, 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v5, v6, v5, vcc_lo v_div_scale_f32 v8, null, v4, v4, 0xf9c26159 v_rcp_f32_e32 v6, v7 v_div_scale_f32 v14, vcc_lo, 0xf9c26159, v4, 0xf9c26159 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3) v_rcp_f32_e32 v9, v8 v_fmaak_f32 v10, s2, v5, 0x3c5fc5da v_div_scale_f32 v11, s2, s20, s21, s20 v_sqrt_f32_e32 v15, v5 v_fma_f32 v12, -v7, v6, 1.0 s_waitcnt_depctr 0xfff v_fma_f32 v13, -v8, v9, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_fmac_f32 v6, v12, v6 :: v_dual_fmac_f32 v9, v13, v9 v_fmaak_f32 v10, v5, v10, 0x3d034c3c v_dual_mul_f32 v12, v11, v6 :: v_dual_mul_f32 v13, v14, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v17, -v7, v12, v11 v_fma_f32 v16, -v8, v13, v14 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmaak_f32 v10, v5, v10, 0x3d3641b1 v_dual_fmac_f32 v12, v17, v6 :: v_dual_fmac_f32 v13, v16, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmaak_f32 v10, v5, v10, 0x3d999bc8 v_fma_f32 v7, -v7, v12, v11 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f32 v8, -v8, v13, v14 v_fmaak_f32 v10, v5, v10, 0x3e2aaaac s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_div_fmas_f32 v8, v8, v9, v13 s_mov_b32 vcc_lo, s2 s_mov_b32 s2, 0x3e76c4e1 v_mul_f32_e32 v5, v5, v10 v_div_fmas_f32 v6, v7, v6, v12 v_cmp_lt_f32_e64 vcc_lo, |v3|, 0.5 v_div_fixup_f32 v4, v8, v4, 0xf9c26159 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fmac_f32_e32 v15, v15, v5 v_fma_f32 v5, |v3|, v5, |v3| v_div_fixup_f32 v6, v6, s21, s20 v_add_f32_e32 v10, v15, v15 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v9, 0x3fc90fdb, v10 v_cndmask_b32_e32 v5, v9, v5, vcc_lo v_cmp_neq_f32_e32 vcc_lo, 1.0, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_bfi_b32 v3, 0x7fffffff, v5, v3 v_sub_f32_e32 v3, v6, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_floor_f32_e32 v3, v3 v_cndmask_b32_e32 v3, 1.0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_neq_f32_e32 vcc_lo, 0, v3 v_cndmask_b32_e32 v4, 1.0, v4, vcc_lo v_frexp_mant_f32_e64 v5, |v4| v_cmp_lt_f32_e64 s11, |v4|, 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5 v_cndmask_b32_e64 v6, 0, 1, vcc_lo v_ldexp_f32 v5, v5, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v6, 1.0, v5 v_rcp_f32_e32 v7, v6 v_add_f32_e32 v10, -1.0, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_dual_add_f32 v8, -1.0, v5 :: v_dual_sub_f32 v5, v5, v10 s_waitcnt_depctr 0xfff v_mul_f32_e32 v9, v8, v7 v_mul_f32_e32 v11, v6, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v6, v9, v6, -v11 v_fmac_f32_e32 v6, v9, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v5, v11, v6 v_dual_sub_f32 v10, v8, v5 :: v_dual_sub_f32 v11, v5, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v8, v8, v10 v_dual_sub_f32 v6, v11, v6 :: v_dual_sub_f32 v5, v8, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v5, v6, v5 v_add_f32_e32 v5, v10, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v5, v7, v5 v_add_f32_e32 v6, v9, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v7, v6, v9 v_dual_mul_f32 v8, v6, v6 :: v_dual_sub_f32 v5, v5, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v7, v6, v6, -v8 v_add_f32_e32 v9, v5, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v7, v6, v9 v_add_f32_e32 v9, v8, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_fmaak_f32 v10, s2, v9, 0x3e91f4c4 v_sub_f32_e32 v8, v9, v8 s_cselect_b32 s2, -1, 0 v_dual_fmaak_f32 v10, v9, v10, 0x3ecccdef :: v_dual_sub_f32 v7, v7, v8 v_mul_f32_e32 v13, v6, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f32_e32 v11, v9, v10 v_fma_f32 v14, v9, v6, -v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v8, v9, v10, -v11 v_fmac_f32_e32 v8, v7, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v10, v11, v8 v_dual_sub_f32 v11, v10, v11 :: v_dual_add_f32 v12, 0x3f2aaaaa, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v8, v8, v11 v_add_f32_e32 v8, 0x31739010, v8 v_fmac_f32_e32 v14, v9, v5 v_ldexp_f32 v5, v5, 1 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fmac_f32_e32 v14, v7, v6 v_ldexp_f32 v6, v6, 1 v_add_f32_e32 v9, v13, v14 v_add_f32_e32 v11, 0xbf2aaaaa, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v10, v10, v11 v_add_f32_e32 v8, v8, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v7, v12, v8 v_sub_f32_e32 v10, v12, v7 v_sub_f32_e32 v12, v9, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f32_e32 v8, v8, v10 v_dual_sub_f32 v12, v14, v12 :: v_dual_mul_f32 v11, v9, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v10, v9, v7, -v11 v_fmac_f32_e32 v10, v9, v8 v_frexp_exp_i32_f32_e32 v8, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmac_f32_e32 v10, v12, v7 v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f32_e32 v8, v11, v10 v_cvt_f32_i32_e32 v7, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f32_e32 v9, v6, v8 v_dual_sub_f32 v11, v8, v11 :: v_dual_add_f32 v2, 0x7bb7de58, v2 v_sub_f32_e32 v10, v10, v11 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f32_e32 v12, 0x3f317218, v7 v_fmac_f32_e64 v2, s10, 12 v_cmp_neq_f32_e64 s10, v3, |v3| s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f32_e32 v5, v5, v10 v_fma_f32 v11, v7, 0x3f317218, -v12 v_sub_f32_e32 v6, v9, v6 v_add_f32_e64 v13, |v2|, |v2| s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_fmamk_f32 v7, v7, 0xb102e308, v11 :: v_dual_sub_f32 v6, v8, v6 v_mul_f32_e32 v15, 0x3fb8aa3b, v13 v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v13 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_add_f32 v5, v5, v6 :: v_dual_add_f32 v6, v12, v7 v_sub_f32_e32 v12, v6, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v7, v7, v12 :: v_dual_add_f32 v8, v9, v5 v_add_f32_e32 v10, v6, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_sub_f32_e32 v11, v10, v6 v_sub_f32_e32 v9, v8, v9 v_dual_sub_f32 v5, v5, v9 :: v_dual_sub_f32 v14, v10, v11 v_fma_f32 v9, v13, 0x3fb8aa3b, -v15 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f32_e32 v12, v7, v5 v_dual_sub_f32 v6, v6, v14 :: v_dual_fmac_f32 v9, 0x32a5705f, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_sub_f32_e32 v14, v12, v7 v_sub_f32_e32 v8, v8, v11 v_rndne_f32_e32 v11, v15 v_sub_f32_e32 v5, v5, v14 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f32_e32 v6, v8, v6 v_sub_f32_e32 v8, v15, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f32_e32 v8, v8, v9 v_sub_f32_e32 v9, v12, v14 v_exp_f32_e32 v8, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v7, v7, v9 v_add_f32_e32 v5, v5, v7 v_mul_f32_e32 v7, v2, v2 v_add_f32_e32 v6, v12, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v12, v10, v6 v_sub_f32_e32 v9, v12, v10 v_cvt_i32_f32_e32 v10, v11 s_delay_alu instid0(VALU_DEP_2) v_sub_f32_e32 v6, v6, v9 s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_2) v_ldexp_f32 v8, v8, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_add_f32 v5, v5, v6 :: v_dual_fmaak_f32 v6, s3, v7, 0x3ca908c9 v_cndmask_b32_e32 v8, 0, v8, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v13 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_add_f32 v9, v12, v5 :: v_dual_fmaak_f32 v6, v7, v6, 0xbd5c1c4e v_cndmask_b32_e32 v8, 0x7f800000, v8, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_sub_f32 v10, v9, v12 :: v_dual_mul_f32 v11, v3, v9 v_fmaak_f32 v6, v7, v6, 0x3e088382 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_add_f32 v8, 1.0, v8 :: v_dual_sub_f32 v5, v5, v10 v_fma_f32 v9, v3, v9, -v11 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fmaak_f32 v6, v7, v6, 0xbeaaaa99 v_rcp_f32_e32 v8, v8 v_cmp_class_f32_e64 vcc_lo, v11, 0x204 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fmac_f32_e32 v9, v3, v5 v_mul_f32_e64 v5, |v2|, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f32_e32 v6, v11, v9 v_fma_f32 v5, v7, v5, |v2| s_waitcnt_depctr 0xfff v_fma_f32 v7, v8, -2.0, 1.0 v_cndmask_b32_e32 v8, v6, v11, vcc_lo v_cmp_gt_f32_e64 vcc_lo, 0x3f200000, |v2| v_sub_f32_e32 v6, v6, v11 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_cmp_neq_f32_e64 s3, 0x7f800000, |v8| v_cndmask_b32_e32 v5, v7, v5, vcc_lo v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v8 v_sub_f32_e32 v6, v9, v6 v_trunc_f32_e32 v9, v3 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_bfi_b32 v2, 0x7fffffff, v5, v2 v_cndmask_b32_e64 v7, 0, 0x37000000, vcc_lo v_cndmask_b32_e64 v6, 0, v6, s3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_sub_f32 v2, 0x80000009, v2 :: v_dual_sub_f32 v5, v8, v7 v_add_f32_e32 v6, v7, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f32_e32 v12, 0x4f800000, v2 v_mul_f32_e32 v10, 0x3fb8aa3b, v5 v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2 v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v5 v_cmp_nlt_f32_e64 s4, 0x42b17218, v5 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f32 v13, v5, 0x3fb8aa3b, -v10 v_rndne_f32_e32 v14, v10 v_dual_cndmask_b32 v2, v2, v12 :: v_dual_fmac_f32 v13, 0x32a5705f, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_sub_f32_e32 v10, v10, v14 v_cvt_i32_f32_e32 v11, v14 v_sqrt_f32_e32 v12, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v10, v10, v13 v_exp_f32_e32 v10, v10 s_waitcnt_depctr 0xfff v_add_nc_u32_e32 v13, -1, v12 v_add_nc_u32_e32 v15, 1, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v14, -v13, v12, v2 v_fma_f32 v16, -v15, v12, v2 v_ldexp_f32 v10, v10, v11 v_mul_f32_e32 v11, 0.5, v3 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_ge_f32_e64 s5, 0, v14 v_cmp_lt_f32_e64 s7, 0, v16 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v8, 0, v10, s3 v_trunc_f32_e32 v10, v11 v_cmp_eq_f32_e64 s3, v9, v3 v_cndmask_b32_e64 v7, v12, v13, s5 v_cmp_gt_f32_e64 s5, 0, v3 v_cndmask_b32_e64 v5, 0x7f800000, v8, s4 v_cmp_neq_f32_e64 s4, v10, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f32 v6, v5, v6, v5 v_cmp_eq_f32_e64 s6, 0x7f800000, v5 s_and_b32 s4, s3, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v8, 1.0, v4, s4 v_cndmask_b32_e64 v10, 0, v4, s4 v_cndmask_b32_e64 v5, v6, v5, s6 v_cndmask_b32_e64 v6, v7, v15, s7 s_xor_b32 s7, s10, s11 v_cmp_eq_f32_e64 s6, 0, v4 v_cndmask_b32_e64 v7, |v3|, 0, s7 v_bfi_b32 v5, 0x7fffffff, v5, v8 v_cmp_class_f32_e64 s4, v4, 0x204 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) s_xor_b32 s5, s5, s6 v_cndmask_b32_e64 v9, 0x7fc00000, v5, s3 v_cmp_eq_f32_e64 s3, |v4|, 1.0 v_cndmask_b32_e64 v8, 0x7f800000, 0, s5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v7, v7, |v4|, s3 v_cmp_gt_f32_e64 s3, 0, v4 v_bfi_b32 v8, 0x7fffffff, v8, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v5, v5, v9, s3 v_cmp_class_f32_e64 s3, v3, 0x204 v_mul_f32_e32 v9, 0x37800000, v6 v_cndmask_b32_e64 v5, v5, v7, s3 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v6, v6, v9, vcc_lo s_or_b32 vcc_lo, s6, s4 v_cndmask_b32_e32 v5, v5, v8, vcc_lo v_cmp_class_f32_e64 vcc_lo, v2, 0x260 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v2, v6, v2, vcc_lo v_cmp_o_f32_e32 vcc_lo, v4, v3 v_mul_f32_e32 v2, s9, v2 v_cndmask_b32_e32 v3, 0x7fc00000, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_scale_f32 v4, null, v2, v2, 0xf8378ede v_add_f32_e32 v3, s17, v3 v_div_scale_f32 v8, vcc_lo, 0xf8378ede, v2, 0xf8378ede s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_rcp_f32_e32 v6, v4 v_mul_f32_e32 v5, 0x4f800000, v3 v_cmp_gt_f32_e64 s3, 0xf800000, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v3, v3, v5, s3 s_waitcnt_depctr 0xfff v_fma_f32 v7, -v4, v6, 1.0 v_sqrt_f32_e32 v5, v3 v_fmac_f32_e32 v6, v7, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) v_mul_f32_e32 v9, v8, v6 s_waitcnt_depctr 0xfff v_add_nc_u32_e32 v7, -1, v5 v_add_nc_u32_e32 v10, 1, v5 v_fma_f32 v12, -v4, v9, v8 v_fma_f32 v11, -v7, v5, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f32 v13, -v10, v5, v3 v_fmac_f32_e32 v9, v12, v6 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_ge_f32_e64 s4, 0, v11 v_fma_f32 v4, -v4, v9, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v5, v5, v7, s4 v_cmp_lt_f32_e64 s4, 0, v13 v_div_fmas_f32 v4, v4, v6, v9 v_cmp_class_f32_e64 vcc_lo, v3, 0x260 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v5, v5, v10, s4 v_div_fixup_f32 v2, v4, v2, 0xf8378ede s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f32_e32 v7, 0x37800000, v5 v_add_f32_e32 v1, s8, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v5, v5, v7, s3 v_cndmask_b32_e32 v3, v5, v3, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v2, 0xa9153831, v3 .LBB0_2: ; %_ZL5tanhff.exit ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_f32_e32 v3, v0, v29 v_cmp_nle_f32_e32 vcc_lo, v29, v1 s_add_i32 s25, s25, -1 s_cmp_eq_u32 s25, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v3, v3, v2, s2 v_cndmask_b32_e32 v29, v3, v29, vcc_lo s_cbranch_scc0 .LBB0_2 .LBB0_3: ; %._crit_edge s_load_b64 s[2:3], s[0:1], 0xb0 v_mbcnt_lo_u32_b32 v20, -1, 0 v_mov_b32_e32 v6, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20 ;;#ASMSTART ;;#ASMEND v_readfirstlane_b32 s0, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s0, s0, v4 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_9 ; %bb.4: v_mov_b32_e32 v0, 0 s_mov_b32 s4, exec_lo s_waitcnt lgkmcnt(0) global_load_b64 v[8:9], v0, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[5:6], v0, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB0_8 ; %bb.5: ; %.preheader3.i.i.i.preheader s_mov_b32 s5, 0 .p2align 6 .LBB0_6: ; %.preheader3.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[10:11], v0, s[2:3] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_6 ; %bb.7: ; %Flow724 s_or_b32 exec_lo, exec_lo, s5 .LBB0_8: ; %Flow726 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB0_9: ; %.loopexit4.i.i.i s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s4, v6 v_readfirstlane_b32 s5, v7 s_mov_b32 s8, exec_lo s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[8:9], v5, s[2:3] offset:40 global_load_b128 v[0:3], v5, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_11 ; %bb.10: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB0_11: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 v_lshlrev_b64 v[4:5], 6, v[4:5] s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v2, s8 v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo v_mov_b32_e32 v3, 0 s_mov_b32 s8, 0 s_delay_alu instid0(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, v2, v4 v_mov_b32_e32 v2, 33 s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v4, v3 v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8 v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10 v_mov_b32_e32 v11, s11 s_clause 0x3 global_store_b128 v[6:7], v[2:5], off global_store_b128 v[6:7], v[8:11], off offset:16 global_store_b128 v[6:7], v[8:11], off offset:32 global_store_b128 v[6:7], v[8:11], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_19 ; %bb.12: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4 v_mov_b32_e32 v12, s5 s_clause 0x1 global_load_b64 v[13:14], v10, s[2:3] offset:32 glc global_load_b64 v[2:3], v10, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 v_readfirstlane_b32 s9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v8, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[13:14] s_cbranch_execz .LBB0_15 ; %bb.13: ; %.preheader1.i.i.i.preheader s_mov_b32 s9, 0 .LBB0_14: ; %.preheader1.i.i.i ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 s_sleep 1 global_store_b64 v[8:9], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB0_14 .LBB0_15: ; %Flow722 s_or_b32 exec_lo, exec_lo, s8 v_mov_b32_e32 v2, 0 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v4, s9, 0 global_load_b64 v[2:3], v2, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB0_17 ; %bb.16: s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB0_17: s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB0_19 ; %bb.18: global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_19: ; %Flow723 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_23 .p2align 6 .LBB0_20: ; in Loop: Header=BB0_23 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_22 ; %bb.21: ; in Loop: Header=BB0_23 Depth=1 s_sleep 1 s_cbranch_execnz .LBB0_23 s_branch .LBB0_25 .p2align 6 .LBB0_22: s_branch .LBB0_25 .LBB0_23: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_20 ; %bb.24: ; in Loop: Header=BB0_23 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_20 .LBB0_25: global_load_b64 v[21:22], v[6:7], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_29 ; %bb.26: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[2:3] offset:40 global_load_b64 v[7:8], v6, s[2:3] offset:24 glc global_load_b64 v[4:5], v6, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s4 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_29 ; %bb.27: ; %.preheader.i.i.i.preheader s_mov_b32 s0, 0 .LBB0_28: ; %.preheader.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_28 .LBB0_29: ; %__ockl_printf_begin.exit s_or_b32 exec_lo, exec_lo, s1 s_getpc_b64 s[4:5] s_add_u32 s4, s4, .str@rel32@lo+4 s_addc_u32 s5, s5, .str@rel32@hi+12 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u64 s[4:5], 0 s_cbranch_scc0 .LBB0_107 ; %bb.30: s_waitcnt vmcnt(0) v_dual_mov_b32 v24, 0 :: v_dual_and_b32 v23, 2, v21 v_and_b32_e32 v0, -3, v21 s_mov_b64 s[6:7], 7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_mov_b32 v1, v22 :: v_dual_mov_b32 v26, v24 v_mov_b32_e32 v25, v23 s_branch .LBB0_32 .LBB0_31: ; %__ockl_hostcall_preview.exit20.i ; in Loop: Header=BB0_32 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_sub_u32 s6, s6, s8 s_subb_u32 s7, s7, s9 s_add_u32 s4, s4, s8 s_addc_u32 s5, s5, s9 s_cmp_lg_u64 s[6:7], 0 s_cbranch_scc0 .LBB0_108 .LBB0_32: ; =>This Loop Header: Depth=1 ; Child Loop BB0_35 Depth 2 ; Child Loop BB0_42 Depth 2 ; Child Loop BB0_49 Depth 2 ; Child Loop BB0_56 Depth 2 ; Child Loop BB0_63 Depth 2 ; Child Loop BB0_70 Depth 2 ; Child Loop BB0_77 Depth 2 ; Child Loop BB0_84 Depth 2 ; Child Loop BB0_92 Depth 2 ; Child Loop BB0_101 Depth 2 ; Child Loop BB0_106 Depth 2 v_cmp_lt_u64_e64 s0, s[6:7], 56 ; implicit-def: $vgpr2_vgpr3 ; implicit-def: $sgpr15 s_delay_alu instid0(VALU_DEP_1) s_and_b32 s0, s0, exec_lo s_cselect_b32 s8, s6, 56 s_cselect_b32 s9, s7, 0 s_cmp_gt_u32 s8, 7 s_mov_b32 s0, -1 s_cbranch_scc1 .LBB0_37 ; %bb.33: ; in Loop: Header=BB0_32 Depth=1 v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 s_cmp_eq_u32 s8, 0 s_cbranch_scc1 .LBB0_36 ; %bb.34: ; %.preheader31.i.preheader ; in Loop: Header=BB0_32 Depth=1 s_lshl_b64 s[0:1], s[8:9], 3 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], s[4:5] .LBB0_35: ; %.preheader31.i ; Parent Loop BB0_32 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v4, v24, s[12:13] s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v4 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[4:5], s10, v[23:24] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_add_u32 s12, s12, 1 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s0, s10 v_or_b32_e32 v2, v4, v2 v_or_b32_e32 v3, v5, v3 s_cbranch_scc1 .LBB0_35 .LBB0_36: ; %Flow693 ; in Loop: Header=BB0_32 Depth=1 s_mov_b32 s0, 0 s_mov_b32 s15, 0 .LBB0_37: ; %Flow695 ; in Loop: Header=BB0_32 Depth=1 s_and_not1_b32 vcc_lo, exec_lo, s0 s_mov_b64 s[0:1], s[4:5] s_cbranch_vccnz .LBB0_39 ; %bb.38: ; in Loop: Header=BB0_32 Depth=1 global_load_b64 v[2:3], v24, s[4:5] s_add_i32 s15, s8, -8 s_add_u32 s0, s4, 8 s_addc_u32 s1, s5, 0 .LBB0_39: ; %.loopexit32.i ; in Loop: Header=BB0_32 Depth=1 s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB0_44 ; %bb.40: ; in Loop: Header=BB0_32 Depth=1 v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB0_43 ; %bb.41: ; %.preheader29.i.preheader ; in Loop: Header=BB0_32 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_42: ; %.preheader29.i ; Parent Loop BB0_32 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v6, v24, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], s10, v[23:24] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v4, v6, v4 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v5, v7, v5 s_cbranch_scc1 .LBB0_42 .LBB0_43: ; %Flow688 ; in Loop: Header=BB0_32 Depth=1 s_mov_b32 s14, 0 s_cbranch_execz .LBB0_45 s_branch .LBB0_46 .LBB0_44: ; in Loop: Header=BB0_32 Depth=1 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $sgpr14 .LBB0_45: ; in Loop: Header=BB0_32 Depth=1 global_load_b64 v[4:5], v24, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_46: ; %.loopexit30.i ; in Loop: Header=BB0_32 Depth=1 s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB0_51 ; %bb.47: ; in Loop: Header=BB0_32 Depth=1 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB0_50 ; %bb.48: ; %.preheader27.i.preheader ; in Loop: Header=BB0_32 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_49: ; %.preheader27.i ; Parent Loop BB0_32 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v8, v24, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], s10, v[23:24] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s14, s12 v_or_b32_e32 v6, v8, v6 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v7, v9, v7 s_cbranch_scc1 .LBB0_49 .LBB0_50: ; %Flow683 ; in Loop: Header=BB0_32 Depth=1 s_mov_b32 s15, 0 s_cbranch_execz .LBB0_52 s_branch .LBB0_53 .LBB0_51: ; in Loop: Header=BB0_32 Depth=1 ; implicit-def: $sgpr15 .LBB0_52: ; in Loop: Header=BB0_32 Depth=1 global_load_b64 v[6:7], v24, s[0:1] s_add_i32 s15, s14, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_53: ; %.loopexit28.i ; in Loop: Header=BB0_32 Depth=1 s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB0_58 ; %bb.54: ; in Loop: Header=BB0_32 Depth=1 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB0_57 ; %bb.55: ; %.preheader25.i.preheader ; in Loop: Header=BB0_32 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_56: ; %.preheader25.i ; Parent Loop BB0_32 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v10, v24, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[10:11], s10, v[23:24] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v8, v10, v8 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v9, v11, v9 s_cbranch_scc1 .LBB0_56 .LBB0_57: ; %Flow678 ; in Loop: Header=BB0_32 Depth=1 s_mov_b32 s14, 0 s_cbranch_execz .LBB0_59 s_branch .LBB0_60 .LBB0_58: ; in Loop: Header=BB0_32 Depth=1 ; implicit-def: $vgpr8_vgpr9 ; implicit-def: $sgpr14 .LBB0_59: ; in Loop: Header=BB0_32 Depth=1 global_load_b64 v[8:9], v24, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_60: ; %.loopexit26.i ; in Loop: Header=BB0_32 Depth=1 s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB0_65 ; %bb.61: ; in Loop: Header=BB0_32 Depth=1 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB0_64 ; %bb.62: ; %.preheader23.i.preheader ; in Loop: Header=BB0_32 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_63: ; %.preheader23.i ; Parent Loop BB0_32 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v12, v24, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[12:13], s10, v[23:24] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s14, s12 v_or_b32_e32 v10, v12, v10 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v11, v13, v11 s_cbranch_scc1 .LBB0_63 .LBB0_64: ; %Flow673 ; in Loop: Header=BB0_32 Depth=1 s_mov_b32 s15, 0 s_cbranch_execz .LBB0_66 s_branch .LBB0_67 .LBB0_65: ; in Loop: Header=BB0_32 Depth=1 ; implicit-def: $sgpr15 .LBB0_66: ; in Loop: Header=BB0_32 Depth=1 global_load_b64 v[10:11], v24, s[0:1] s_add_i32 s15, s14, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_67: ; %.loopexit24.i ; in Loop: Header=BB0_32 Depth=1 s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB0_72 ; %bb.68: ; in Loop: Header=BB0_32 Depth=1 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB0_71 ; %bb.69: ; %.preheader21.i.preheader ; in Loop: Header=BB0_32 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_70: ; %.preheader21.i ; Parent Loop BB0_32 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v14, v24, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[14:15], s10, v[23:24] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v12, v14, v12 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v13, v15, v13 s_cbranch_scc1 .LBB0_70 .LBB0_71: ; %Flow668 ; in Loop: Header=BB0_32 Depth=1 s_mov_b32 s14, 0 s_cbranch_execz .LBB0_73 s_branch .LBB0_74 .LBB0_72: ; in Loop: Header=BB0_32 Depth=1 ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $sgpr14 .LBB0_73: ; in Loop: Header=BB0_32 Depth=1 global_load_b64 v[12:13], v24, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_74: ; %.loopexit22.i ; in Loop: Header=BB0_32 Depth=1 s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB0_79 ; %bb.75: ; in Loop: Header=BB0_32 Depth=1 v_mov_b32_e32 v14, 0 v_mov_b32_e32 v15, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB0_78 ; %bb.76: ; %.preheader.i.preheader ; in Loop: Header=BB0_32 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], s[0:1] .LBB0_77: ; %.preheader.i ; Parent Loop BB0_32 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v16, v24, s[12:13] s_add_i32 s14, s14, -1 s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v16 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[16:17], s10, v[23:24] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_add_u32 s12, s12, 1 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s14, 0 v_or_b32_e32 v14, v16, v14 v_or_b32_e32 v15, v17, v15 s_cbranch_scc1 .LBB0_77 .LBB0_78: ; %Flow663 ; in Loop: Header=BB0_32 Depth=1 s_cbranch_execz .LBB0_80 s_branch .LBB0_81 .LBB0_79: ; in Loop: Header=BB0_32 Depth=1 .LBB0_80: ; in Loop: Header=BB0_32 Depth=1 global_load_b64 v[14:15], v24, s[0:1] .LBB0_81: ; %.loopexit.i ; in Loop: Header=BB0_32 Depth=1 v_mov_b32_e32 v23, v20 v_mov_b32_e32 v27, 0 v_mov_b32_e32 v28, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v23 v_cmp_eq_u32_e64 s0, s0, v23 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_87 ; %bb.82: ; in Loop: Header=BB0_32 Depth=1 global_load_b64 v[18:19], v24, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[16:17], v24, s[2:3] offset:40 global_load_b64 v[27:28], v24, s[2:3] s_mov_b32 s10, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v17, v17, v19 v_and_b32_e32 v16, v16, v18 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v17, v17, 24 v_mul_hi_u32 v30, v16, 24 v_mul_lo_u32 v16, v16, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v17, v30, v17 s_waitcnt vmcnt(0) v_add_co_u32 v16, vcc_lo, v27, v16 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v17, vcc_lo, v28, v17, vcc_lo global_load_b64 v[16:17], v[16:17], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[27:28], v24, v[16:19], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[27:28], v[18:19] s_cbranch_execz .LBB0_86 ; %bb.83: ; %.preheader3.i.i19.i.preheader ; in Loop: Header=BB0_32 Depth=1 s_mov_b32 s11, 0 .p2align 6 .LBB0_84: ; %.preheader3.i.i19.i ; Parent Loop BB0_32 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 s_clause 0x1 global_load_b64 v[16:17], v24, s[2:3] offset:40 global_load_b64 v[30:31], v24, s[2:3] v_dual_mov_b32 v18, v27 :: v_dual_mov_b32 v19, v28 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v16, v16, v18 s_waitcnt vmcnt(0) v_mad_u64_u32 v[27:28], null, v16, 24, v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v16, v28 :: v_dual_and_b32 v17, v17, v19 v_mad_u64_u32 v[30:31], null, v17, 24, v[16:17] s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v28, v30 global_load_b64 v[16:17], v[27:28], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[27:28], v24, v[16:19], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[27:28], v[18:19] s_or_b32 s11, vcc_lo, s11 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s11 s_cbranch_execnz .LBB0_84 ; %bb.85: ; %Flow658 ; in Loop: Header=BB0_32 Depth=1 s_or_b32 exec_lo, exec_lo, s11 .LBB0_86: ; %Flow660 ; in Loop: Header=BB0_32 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s10 .LBB0_87: ; %.loopexit4.i.i14.i ; in Loop: Header=BB0_32 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_clause 0x1 global_load_b64 v[30:31], v24, s[2:3] offset:40 global_load_b128 v[16:19], v24, s[2:3] v_readfirstlane_b32 s10, v27 v_readfirstlane_b32 s11, v28 s_mov_b32 s14, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s12, v30 v_readfirstlane_b32 s13, v31 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[12:13], s[10:11], s[12:13] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_89 ; %bb.88: ; in Loop: Header=BB0_32 Depth=1 v_dual_mov_b32 v30, s14 :: v_dual_mov_b32 v31, 0 s_mul_i32 s14, s13, 24 s_mul_hi_u32 s15, s12, 24 v_dual_mov_b32 v32, 2 :: v_dual_mov_b32 v33, 1 s_add_i32 s15, s15, s14 s_mul_i32 s14, s12, 24 s_waitcnt vmcnt(0) v_add_co_u32 v27, vcc_lo, v16, s14 v_add_co_ci_u32_e32 v28, vcc_lo, s15, v17, vcc_lo global_store_b128 v[27:28], v[30:33], off offset:8 .LBB0_89: ; in Loop: Header=BB0_32 Depth=1 s_or_b32 exec_lo, exec_lo, s1 v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56 v_or_b32_e32 v27, v1, v26 v_or_b32_e32 v28, v0, v25 s_lshl_b64 s[14:15], s[12:13], 12 s_lshl_b32 s1, s8, 2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_add_i32 s1, s1, 28 v_dual_cndmask_b32 v1, v27, v1 :: v_dual_cndmask_b32 v0, v28, v0 v_lshlrev_b64 v[27:28], 6, v[23:24] s_waitcnt vmcnt(0) v_add_co_u32 v18, vcc_lo, v18, s14 v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo s_and_b32 s1, s1, 0x1e0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v18, vcc_lo, v18, v27 v_and_or_b32 v0, v0, 0xffffff1f, s1 v_add_co_ci_u32_e32 v19, vcc_lo, v19, v28, vcc_lo s_clause 0x3 global_store_b128 v[18:19], v[0:3], off global_store_b128 v[18:19], v[4:7], off offset:16 global_store_b128 v[18:19], v[8:11], off offset:32 global_store_b128 v[18:19], v[12:15], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_97 ; %bb.90: ; in Loop: Header=BB0_32 Depth=1 s_clause 0x1 global_load_b64 v[8:9], v24, s[2:3] offset:32 glc global_load_b64 v[0:1], v24, s[2:3] offset:40 v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11 s_waitcnt vmcnt(0) v_readfirstlane_b32 s14, v0 v_readfirstlane_b32 s15, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[14:15], s[14:15], s[10:11] s_mul_i32 s15, s15, 24 s_mul_hi_u32 s16, s14, 24 s_mul_i32 s14, s14, 24 s_add_i32 s16, s16, s15 v_add_co_u32 v4, vcc_lo, v16, s14 v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo s_mov_b32 s14, exec_lo global_store_b64 v[4:5], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v24, v[6:9], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[8:9] s_cbranch_execz .LBB0_93 ; %bb.91: ; %.preheader1.i.i17.i.preheader ; in Loop: Header=BB0_32 Depth=1 s_mov_b32 s15, 0 .LBB0_92: ; %.preheader1.i.i17.i ; Parent Loop BB0_32 Depth=1 ; => This Inner Loop Header: Depth=2 v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v24, v[0:3], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s15, vcc_lo, s15 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s15 s_cbranch_execnz .LBB0_92 .LBB0_93: ; %Flow656 ; in Loop: Header=BB0_32 Depth=1 s_or_b32 exec_lo, exec_lo, s14 global_load_b64 v[0:1], v24, s[2:3] offset:16 s_mov_b32 s15, exec_lo s_mov_b32 s14, exec_lo v_mbcnt_lo_u32_b32 v2, s15, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB0_95 ; %bb.94: ; in Loop: Header=BB0_32 Depth=1 s_bcnt1_i32_b32 s15, s15 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB0_95: ; in Loop: Header=BB0_32 Depth=1 s_or_b32 exec_lo, exec_lo, s14 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB0_97 ; %bb.96: ; in Loop: Header=BB0_32 Depth=1 global_load_b32 v23, v[0:1], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s14, v23 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[23:24], off s_and_b32 m0, s14, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_97: ; %Flow657 ; in Loop: Header=BB0_32 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s13, 24 s_mul_hi_u32 s13, s12, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s13, s13, s1 s_mul_i32 s1, s12, 24 v_add_co_u32 v0, vcc_lo, v16, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_101 .p2align 6 .LBB0_98: ; in Loop: Header=BB0_101 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_100 ; %bb.99: ; in Loop: Header=BB0_101 Depth=2 s_sleep 1 s_cbranch_execnz .LBB0_101 s_branch .LBB0_103 .p2align 6 .LBB0_100: ; in Loop: Header=BB0_32 Depth=1 s_branch .LBB0_103 .LBB0_101: ; Parent Loop BB0_32 Depth=1 ; => This Inner Loop Header: Depth=2 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_98 ; %bb.102: ; in Loop: Header=BB0_101 Depth=2 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_98 .LBB0_103: ; in Loop: Header=BB0_32 Depth=1 global_load_b64 v[0:1], v[18:19], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_31 ; %bb.104: ; in Loop: Header=BB0_32 Depth=1 s_clause 0x2 global_load_b64 v[4:5], v24, s[2:3] offset:40 global_load_b64 v[8:9], v24, s[2:3] offset:24 glc global_load_b64 v[6:7], v24, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v10, vcc_lo, v4, 1 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, v10, s10 v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10 v_and_b32_e32 v5, v3, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v4, v2, v4 v_mul_hi_u32 v10, v4, 24 v_mul_lo_u32 v4, v4, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v6, vcc_lo, v6, v4 v_mov_b32_e32 v4, v8 v_mul_lo_u32 v5, v5, 24 v_add_nc_u32_e32 v5, v10, v5 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v5, v9 global_store_b64 v[6:7], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v24, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_31 ; %bb.105: ; %.preheader.i.i16.i.preheader ; in Loop: Header=BB0_32 Depth=1 s_mov_b32 s0, 0 .LBB0_106: ; %.preheader.i.i16.i ; Parent Loop BB0_32 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v24, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5] v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_106 s_branch .LBB0_31 .LBB0_107: ; implicit-def: $vgpr0_vgpr1 s_cbranch_execnz .LBB0_109 s_branch .LBB0_136 .LBB0_108: ; %Flow696 s_branch .LBB0_136 .LBB0_109: v_mov_b32_e32 v4, v20 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v4 v_cmp_eq_u32_e64 s0, s0, v4 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_115 ; %bb.110: s_waitcnt vmcnt(0) v_mov_b32_e32 v0, 0 s_mov_b32 s4, exec_lo global_load_b64 v[8:9], v0, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[5:6], v0, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB0_114 ; %bb.111: ; %.preheader3.i.i.i37.preheader s_mov_b32 s5, 0 .p2align 6 .LBB0_112: ; %.preheader3.i.i.i37 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[10:11], v0, s[2:3] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_112 ; %bb.113: ; %Flow708 s_or_b32 exec_lo, exec_lo, s5 .LBB0_114: ; %Flow710 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB0_115: ; %.loopexit4.i.i.i32 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s4, v6 v_readfirstlane_b32 s5, v7 s_mov_b32 s8, exec_lo s_clause 0x1 global_load_b64 v[8:9], v5, s[2:3] offset:40 global_load_b128 v[0:3], v5, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_117 ; %bb.116: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB0_117: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 v_and_or_b32 v21, v21, 0xffffff1f, 32 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v2, s8 v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo v_lshlrev_b64 v[2:3], 6, v[4:5] s_mov_b32 s8, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_add_co_u32 v6, vcc_lo, v6, v2 v_mov_b32_e32 v8, 0 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11 v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10 s_delay_alu instid0(VALU_DEP_4) v_mov_b32_e32 v9, v8 s_clause 0x4 global_store_b64 v[6:7], v[21:22], off global_store_b128 v[6:7], v[2:5], off offset:8 global_store_b128 v[6:7], v[2:5], off offset:24 global_store_b128 v[6:7], v[2:5], off offset:40 global_store_b64 v[6:7], v[8:9], off offset:56 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_125 ; %bb.118: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4 v_mov_b32_e32 v12, s5 s_clause 0x1 global_load_b64 v[13:14], v10, s[2:3] offset:32 glc global_load_b64 v[2:3], v10, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 v_readfirstlane_b32 s9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v8, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[13:14] s_cbranch_execz .LBB0_121 ; %bb.119: ; %.preheader1.i.i.i35.preheader s_mov_b32 s9, 0 .LBB0_120: ; %.preheader1.i.i.i35 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 s_sleep 1 global_store_b64 v[8:9], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB0_120 .LBB0_121: ; %Flow706 s_or_b32 exec_lo, exec_lo, s8 v_mov_b32_e32 v2, 0 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v4, s9, 0 global_load_b64 v[2:3], v2, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB0_123 ; %bb.122: s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB0_123: s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB0_125 ; %bb.124: global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_125: ; %Flow707 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_129 .p2align 6 .LBB0_126: ; in Loop: Header=BB0_129 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_128 ; %bb.127: ; in Loop: Header=BB0_129 Depth=1 s_sleep 1 s_cbranch_execnz .LBB0_129 s_branch .LBB0_131 .p2align 6 .LBB0_128: s_branch .LBB0_131 .LBB0_129: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_126 ; %bb.130: ; in Loop: Header=BB0_129 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_126 .LBB0_131: global_load_b64 v[0:1], v[6:7], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_135 ; %bb.132: v_mov_b32_e32 v8, 0 s_clause 0x2 global_load_b64 v[4:5], v8, s[2:3] offset:40 global_load_b64 v[9:10], v8, s[2:3] offset:24 glc global_load_b64 v[6:7], v8, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v11, vcc_lo, v4, 1 v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, v11, s4 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11 v_and_b32_e32 v5, v3, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v4, v2, v4 v_mul_lo_u32 v5, v5, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v11, v4, 24 v_mul_lo_u32 v4, v4, 24 v_add_nc_u32_e32 v5, v11, v5 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, v6, v4 v_mov_b32_e32 v4, v9 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v5, v10 global_store_b64 v[6:7], v[9:10], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_135 ; %bb.133: ; %.preheader.i.i.i34.preheader s_mov_b32 s0, 0 .LBB0_134: ; %.preheader.i.i.i34 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5] v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_134 .LBB0_135: ; %__ockl_hostcall_preview.exit.i s_or_b32 exec_lo, exec_lo, s1 .LBB0_136: ; %__ockl_printf_append_string_n.exit ;;#ASMSTART ;;#ASMEND v_readfirstlane_b32 s0, v20 v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s0, s0, v20 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_142 ; %bb.137: v_mov_b32_e32 v4, 0 s_mov_b32 s4, exec_lo global_load_b64 v[7:8], v4, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[2:3], v4, s[2:3] offset:40 global_load_b64 v[5:6], v4, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v3, v3, v8 v_and_b32_e32 v2, v2, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v3, v3, 24 v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v5, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, v6, v3, vcc_lo global_load_b64 v[5:6], v[2:3], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[2:3], v4, v[5:8], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[2:3], v[7:8] s_cbranch_execz .LBB0_141 ; %bb.138: ; %.preheader3.i.i.i44.preheader s_mov_b32 s5, 0 .p2align 6 .LBB0_139: ; %.preheader3.i.i.i44 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[5:6], v4, s[2:3] offset:40 global_load_b64 v[9:10], v4, s[2:3] v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v5, v5, v7 s_waitcnt vmcnt(0) v_mad_u64_u32 v[2:3], null, v5, 24, v[9:10] v_and_b32_e32 v9, v6, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v9, 24, v[3:4] v_mov_b32_e32 v3, v5 global_load_b64 v[5:6], v[2:3], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[2:3], v4, v[5:8], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[7:8] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_139 ; %bb.140: ; %Flow644 s_or_b32 exec_lo, exec_lo, s5 .LBB0_141: ; %Flow646 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB0_142: ; %.loopexit4.i.i.i38 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_waitcnt vmcnt(0) v_mov_b32_e32 v21, 0 v_readfirstlane_b32 s4, v2 v_readfirstlane_b32 s5, v3 s_mov_b32 s8, exec_lo s_clause 0x1 global_load_b64 v[8:9], v21, s[2:3] offset:40 global_load_b128 v[4:7], v21, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_144 ; %bb.143: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v4, s8 v_add_co_ci_u32_e32 v3, vcc_lo, s9, v5, vcc_lo global_store_b128 v[2:3], v[8:11], off offset:8 .LBB0_144: s_or_b32 exec_lo, exec_lo, s1 v_cvt_f64_f32_e32 v[2:3], v29 s_lshl_b64 s[10:11], s[6:7], 12 v_lshlrev_b64 v[8:9], 6, v[20:21] s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v6, s10 v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo s_mov_b32 s8, 0 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v6, v8 s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_and_or_b32 v0, v0, 0xffffff1d, 34 v_add_co_ci_u32_e32 v11, vcc_lo, v7, v9, vcc_lo v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9 v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11 s_clause 0x3 global_store_b128 v[10:11], v[0:3], off global_store_b128 v[10:11], v[6:9], off offset:16 global_store_b128 v[10:11], v[6:9], off offset:32 global_store_b128 v[10:11], v[6:9], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_152 ; %bb.145: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4 v_mov_b32_e32 v10, s5 s_clause 0x1 global_load_b64 v[11:12], v8, s[2:3] offset:32 glc global_load_b64 v[0:1], v8, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v0 v_readfirstlane_b32 s9, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v6, vcc_lo, v4, s8 v_add_co_ci_u32_e32 v7, vcc_lo, s10, v5, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[6:7], v[11:12], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[11:12] s_cbranch_execz .LBB0_148 ; %bb.146: ; %.preheader1.i.i.i42.preheader s_mov_b32 s9, 0 .LBB0_147: ; %.preheader1.i.i.i42 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 s_sleep 1 global_store_b64 v[6:7], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB0_147 .LBB0_148: ; %Flow642 s_or_b32 exec_lo, exec_lo, s8 v_mov_b32_e32 v0, 0 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v2, s9, 0 global_load_b64 v[0:1], v0, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB0_150 ; %bb.149: s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB0_150: s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB0_152 ; %bb.151: global_load_b32 v0, v[0:1], off offset:24 v_mov_b32_e32 v1, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v0 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[0:1], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_152: ; %Flow643 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v0, vcc_lo, v4, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_156 .p2align 6 .LBB0_153: ; in Loop: Header=BB0_156 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_155 ; %bb.154: ; in Loop: Header=BB0_156 Depth=1 s_sleep 1 s_cbranch_execnz .LBB0_156 s_branch .LBB0_158 .p2align 6 .LBB0_155: s_branch .LBB0_158 .LBB0_156: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_153 ; %bb.157: ; in Loop: Header=BB0_156 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_153 .LBB0_158: s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_162 ; %bb.159: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[2:3] offset:40 global_load_b64 v[7:8], v6, s[2:3] offset:24 glc global_load_b64 v[4:5], v6, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s4 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_162 ; %bb.160: ; %.preheader.i.i.i41.preheader s_mov_b32 s0, 0 .LBB0_161: ; %.preheader.i.i.i41 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_161 .LBB0_162: ; %__ockl_printf_append_args.exit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z7computefiffffiffffffffffffffff .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 352 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 34 .amdhsa_next_free_sgpr 26 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z7computefiffffiffffffffffffffff, .Lfunc_end0-_Z7computefiffffiffffffffffffffff ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 9988 ; NumSgprs: 28 ; NumVgprs: 34 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 3 ; VGPRBlocks: 4 ; NumSGPRsForWavesPerEU: 28 ; NumVGPRsForWavesPerEU: 34 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type .str,@object ; @.str .section .rodata.str1.1,"aMS",@progbits,1 .str: .asciz "%.17g\n" .size .str, 7 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: by_value - .offset: 44 .size: 4 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: by_value - .offset: 52 .size: 4 .value_kind: by_value - .offset: 56 .size: 4 .value_kind: by_value - .offset: 60 .size: 4 .value_kind: by_value - .offset: 64 .size: 4 .value_kind: by_value - .offset: 68 .size: 4 .value_kind: by_value - .offset: 72 .size: 4 .value_kind: by_value - .offset: 76 .size: 4 .value_kind: by_value - .offset: 80 .size: 4 .value_kind: by_value - .offset: 84 .size: 4 .value_kind: by_value - .offset: 88 .size: 4 .value_kind: by_value - .offset: 96 .size: 4 .value_kind: hidden_block_count_x - .offset: 100 .size: 4 .value_kind: hidden_block_count_y - .offset: 104 .size: 4 .value_kind: hidden_block_count_z - .offset: 108 .size: 2 .value_kind: hidden_group_size_x - .offset: 110 .size: 2 .value_kind: hidden_group_size_y - .offset: 112 .size: 2 .value_kind: hidden_group_size_z - .offset: 114 .size: 2 .value_kind: hidden_remainder_x - .offset: 116 .size: 2 .value_kind: hidden_remainder_y - .offset: 118 .size: 2 .value_kind: hidden_remainder_z - .offset: 136 .size: 8 .value_kind: hidden_global_offset_x - .offset: 144 .size: 8 .value_kind: hidden_global_offset_y - .offset: 152 .size: 8 .value_kind: hidden_global_offset_z - .offset: 160 .size: 2 .value_kind: hidden_grid_dims - .offset: 176 .size: 8 .value_kind: hidden_hostcall_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 352 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z7computefiffffiffffffffffffffff .private_segment_fixed_size: 0 .sgpr_count: 28 .sgpr_spill_count: 0 .symbol: _Z7computefiffffiffffffffffffffff.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 34 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "71896bd9be10e0e0786f071665952c91ef3cd5b9.hip" .globl _Z22__device_stub__computefiffffiffffffffffffffff # -- Begin function _Z22__device_stub__computefiffffiffffffffffffffff .p2align 4, 0x90 .type _Z22__device_stub__computefiffffiffffffffffffffff,@function _Z22__device_stub__computefiffffiffffffffffffffff: # @_Z22__device_stub__computefiffffiffffffffffffffff .cfi_startproc # %bb.0: subq $280, %rsp # imm = 0x118 .cfi_def_cfa_offset 288 movss %xmm0, 44(%rsp) movl %edi, 40(%rsp) movss %xmm1, 36(%rsp) movss %xmm2, 32(%rsp) movss %xmm3, 28(%rsp) movss %xmm4, 24(%rsp) movl %esi, 20(%rsp) movss %xmm5, 16(%rsp) movss %xmm6, 12(%rsp) movss %xmm7, 8(%rsp) leaq 44(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rax movq %rax, 104(%rsp) leaq 36(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 28(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 20(%rsp), %rax movq %rax, 144(%rsp) leaq 16(%rsp), %rax movq %rax, 152(%rsp) leaq 12(%rsp), %rax movq %rax, 160(%rsp) leaq 8(%rsp), %rax movq %rax, 168(%rsp) leaq 288(%rsp), %rax movq %rax, 176(%rsp) leaq 296(%rsp), %rax movq %rax, 184(%rsp) leaq 304(%rsp), %rax movq %rax, 192(%rsp) leaq 312(%rsp), %rax movq %rax, 200(%rsp) leaq 320(%rsp), %rax movq %rax, 208(%rsp) leaq 328(%rsp), %rax movq %rax, 216(%rsp) leaq 336(%rsp), %rax movq %rax, 224(%rsp) leaq 344(%rsp), %rax movq %rax, 232(%rsp) leaq 352(%rsp), %rax movq %rax, 240(%rsp) leaq 360(%rsp), %rax movq %rax, 248(%rsp) leaq 368(%rsp), %rax movq %rax, 256(%rsp) leaq 376(%rsp), %rax movq %rax, 264(%rsp) leaq 384(%rsp), %rax movq %rax, 272(%rsp) leaq 80(%rsp), %rdi leaq 64(%rsp), %rsi leaq 56(%rsp), %rdx leaq 48(%rsp), %rcx callq __hipPopCallConfiguration movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 64(%rsp), %rcx movl 72(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z7computefiffffiffffffffffffffff, %edi pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $296, %rsp # imm = 0x128 .cfi_adjust_cfa_offset -296 retq .Lfunc_end0: .size _Z22__device_stub__computefiffffiffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiffffiffffffffffffffff .cfi_endproc # -- End function .globl _Z11initPointerf # -- Begin function _Z11initPointerf .p2align 4, 0x90 .type _Z11initPointerf,@function _Z11initPointerf: # @_Z11initPointerf .cfi_startproc # %bb.0: pushq %rax .cfi_def_cfa_offset 16 movss %xmm0, 4(%rsp) # 4-byte Spill movl $40, %edi callq malloc movss 4(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movss %xmm0, (%rax,%rcx,4) incq %rcx cmpq $10, %rcx jne .LBB1_1 # %bb.2: popq %rcx .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $272, %rsp # imm = 0x110 .cfi_def_cfa_offset 304 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rsi, %r15 movq 8(%rsi), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 264(%rsp) # 8-byte Spill movq 16(%r15), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %rbx movq 24(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 256(%rsp) # 8-byte Spill movq 32(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 248(%rsp) # 8-byte Spill movq 40(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 240(%rsp) # 8-byte Spill movq 48(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 136(%rsp) # 8-byte Spill movq 56(%r15), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r14 movq 64(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 128(%rsp) # 8-byte Spill movq 72(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 120(%rsp) # 8-byte Spill movq 80(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 112(%rsp) # 8-byte Spill movq 88(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 104(%rsp) # 8-byte Spill movq 96(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 232(%rsp) # 8-byte Spill movq 104(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 224(%rsp) # 8-byte Spill movq 112(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 216(%rsp) # 8-byte Spill movq 120(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 208(%rsp) # 8-byte Spill movq 128(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 200(%rsp) # 8-byte Spill movq 136(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 192(%rsp) # 8-byte Spill movq 144(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 184(%rsp) # 8-byte Spill movq 152(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 176(%rsp) # 8-byte Spill movq 160(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 168(%rsp) # 8-byte Spill movq 168(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 160(%rsp) # 8-byte Spill movq 176(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 152(%rsp) # 8-byte Spill movq 184(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 144(%rsp) # 8-byte Spill movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: movsd 144(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm8 movsd 152(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm9 movsd 160(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm10 movsd 168(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm11 movsd 176(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm12 movsd 184(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm13 movsd 192(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm14 movsd 200(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm15 movsd 208(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm4 movsd 216(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm5 movsd 224(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm6 movsd 232(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm7 movsd 104(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 104(%rsp) # 4-byte Spill movsd 112(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 112(%rsp) # 4-byte Spill movsd 120(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 120(%rsp) # 4-byte Spill movsd 128(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 128(%rsp) # 4-byte Spill movsd 136(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 136(%rsp) # 4-byte Spill movsd 240(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm3 movsd 248(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm2 movsd 256(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm1 movsd 264(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm8, 96(%rsp) movss %xmm9, 88(%rsp) movss %xmm10, 80(%rsp) movss %xmm11, 72(%rsp) movss %xmm12, 64(%rsp) movss %xmm13, 56(%rsp) movss %xmm14, 48(%rsp) movss %xmm15, 40(%rsp) movss %xmm4, 32(%rsp) movss %xmm5, 24(%rsp) movss %xmm6, 16(%rsp) movss %xmm7, 8(%rsp) movss 104(%rsp), %xmm4 # 4-byte Reload # xmm4 = mem[0],zero,zero,zero movss %xmm4, (%rsp) movl %ebx, %edi movss 136(%rsp), %xmm4 # 4-byte Reload # xmm4 = mem[0],zero,zero,zero movl %r14d, %esi movss 128(%rsp), %xmm5 # 4-byte Reload # xmm5 = mem[0],zero,zero,zero movss 120(%rsp), %xmm6 # 4-byte Reload # xmm6 = mem[0],zero,zero,zero movss 112(%rsp), %xmm7 # 4-byte Reload # xmm7 = mem[0],zero,zero,zero callq _Z22__device_stub__computefiffffiffffffffffffffff .LBB2_2: callq hipDeviceSynchronize xorl %eax, %eax addq $272, %rsp # imm = 0x110 .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7computefiffffiffffffffffffffff, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z7computefiffffiffffffffffffffff,@object # @_Z7computefiffffiffffffffffffffff .section .rodata,"a",@progbits .globl _Z7computefiffffiffffffffffffffff .p2align 3, 0x0 _Z7computefiffffiffffffffffffffff: .quad _Z22__device_stub__computefiffffiffffffffffffffff .size _Z7computefiffffiffffffffffffffff, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z7computefiffffiffffffffffffffff" .size .L__unnamed_1, 34 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__computefiffffiffffffffffffffff .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7computefiffffiffffffffffffffff .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
17,106
5,352
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5,779
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code for sm_80 Function : _Z12test_kernel2PmS_jPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; ULDC.64 UR36, c[0x0][0x118] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; IADD3 R1, R1, -0x10, RZ ; LDG.E R2, [R2.64] ; ISETP.NE.AND P0, PT, R2, RZ, PT ; @!P0 BRA 0xe0 ; MOV R20, 0xb0 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; CALL.REL.NOINC 0x180 ; IMAD.MOV.U32 R2, RZ, RZ, -0x66666667 ; IMAD.MOV.U32 R3, RZ, RZ, -0x66666667 ; BRA 0x110 ; MOV R18, 0x100 ; CALL.REL.NOINC 0x300 ; IMAD.MOV.U32 R2, RZ, RZ, R22 ; S2R R4, SR_TID.X ; IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; S2R R5, SR_CTAID.X ; IMAD R4, R5, c[0x0][0x0], R4 ; IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; STG.E.64 [R4.64], R2 ; EXIT ; IADD3 R1, R1, -0x10, RZ ; STL [R1+0x8], R21 ; STL [R1+0x4], R20 ; STL [R1], R2 ; MOV R0, 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; CS2R R6, SRZ ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; LDC.64 R2, c[0x4][R0] ; LEPC R8 ; MOV R11, 0x290 ; MOV R0, 0x210 ; MOV R13, 0x0 ; MOV R10, 0x0 ; IADD3 R20, P0, P1, -R0, R11, R8 ; IADD3.X R21, ~R10, R13, R9, P0, P1 ; CALL.ABS.NOINC R2 ; LDL R20, [R1+0x4] ; IMAD.MOV.U32 R4, RZ, RZ, -0x66666667 ; IMAD.MOV.U32 R5, RZ, RZ, -0x66666667 ; LDL R21, [R1+0x8] ; LDL R2, [R1] ; IADD3 R1, R1, 0x10, RZ ; RET.REL.NODEC R20 0x0 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; ISETP.NE.AND P0, PT, R0, 0x2, PT ; @P0 BRA 0x400 ; MOV R0, 0x8 ; IMAD.MOV.U32 R4, RZ, RZ, 0x40 ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; LDC.64 R2, c[0x4][R0] ; LEPC R6 ; MOV R9, 0x3f0 ; MOV R20, 0x370 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R9, R6 ; IADD3.X R21, ~R0, R21, R7, P0, P1 ; CALL.ABS.NOINC R2 ; STS.64 [RZ], R4 ; MOV R0, 0x8 ; IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; IADD3 R16, P0, R1, c[0x0][0x20], RZ ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; LDC.64 R6, c[0x4][R0] ; IMAD.X R2, RZ, RZ, c[0x0][0x24], P0 ; LEPC R8 ; MOV R3, 0x4e0 ; MOV R20, 0x460 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R8 ; IADD3.X R21, ~R0, R21, R9, P0, P1 ; CALL.ABS.NOINC R6 ; ULDC.64 UR4, c[0x4][0x10] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; UIADD3 UR4, UP0, UR4, 0x10, URZ ; MOV R17, 0x0 ; IMAD.MOV.U32 R22, RZ, RZ, R4 ; MOV R7, R2 ; UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; LDC.64 R8, c[0x4][R17] ; IMAD.U32 R12, RZ, RZ, UR4 ; IMAD.MOV.U32 R23, RZ, RZ, R5 ; IMAD.U32 R13, RZ, RZ, UR5 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; ST.E.64 [R4.64], R12 ; LDS.64 R10, [RZ] ; STL [R1], R0 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x20] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x24] ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x690 ; MOV R20, 0x610 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; IMAD.MOV.U32 R10, RZ, RZ, 0x28 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x28] ; STL.64 [R1+0x8], R10 ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x2c] ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; STL [R1], R0 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; LEPC R10 ; MOV R3, 0x7b0 ; MOV R20, 0x730 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; LDC.64 R8, c[0x4][R17] ; STL.64 [R1+0x8], R22 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x30] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x34] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; LEPC R10 ; MOV R3, 0x8b0 ; MOV R20, 0x830 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; S2R R0, SR_TID.X ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; BSSY B0, 0xce0 ; ISETP.NE.AND P0, PT, R0, 0x1, PT ; ISETP.NE.OR P0, PT, R3, 0x2, P0 ; ISETP.EQ.OR P0, PT, RZ, c[0x0][0x170], P0 ; @P0 BRA 0xcd0 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; IADD3 R3, R0.reuse, -0x1, RZ ; LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; IMAD.MOV.U32 R3, RZ, RZ, RZ ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P1 BRA 0xbc0 ; BSSY B1, 0xbc0 ; IADD3 R17, -R0, c[0x0][0x170], RZ ; IMAD.MOV.U32 R3, RZ, RZ, RZ ; IMAD.MOV.U32 R19, RZ, RZ, 0x10 ; IMAD.MOV.U32 R27, RZ, RZ, RZ ; IADD3 R4, P1, R19, c[0x0][0x168], RZ ; ULDC.64 UR4, c[0x0][0x118] ; LDS.64 R8, [RZ] ; IADD3.X R5, R27, c[0x0][0x16c], RZ, P1, !PT ; LDG.E.64 R6, [R4.64+-0x10] ; IADD3 R14, P1, R8, R19, RZ ; IADD3.X R15, R9, R27, RZ, P1, !PT ; ST.E.64 [R14.64+-0x10], R6 ; LDG.E.64 R8, [R4.64+-0x8] ; LDS.64 R10, [RZ] ; IADD3 R20, P1, R10, R19, RZ ; IMAD.X R21, R11, 0x1, R27, P1 ; ST.E.64 [R20.64+-0x8], R8 ; LDG.E.64 R10, [R4.64] ; LDS.64 R12, [RZ] ; IADD3 R24, P1, R12, R19, RZ ; IMAD.X R25, R13, 0x1, R27, P1 ; ST.E.64 [R24.64], R10 ; LDG.E.64 R6, [R4.64+0x8] ; IADD3 R17, R17, -0x4, RZ ; IADD3 R3, R3, 0x4, RZ ; LDS.64 R12, [RZ] ; IADD3 R12, P1, R12, R19, RZ ; IADD3 R19, P2, R19, 0x20, RZ ; IMAD.X R13, R13, 0x1, R27.reuse, P1 ; ISETP.NE.AND P1, PT, R17, RZ, PT ; IMAD.X R27, RZ, RZ, R27, P2 ; ST.E.64 [R12.64+0x8], R6 ; @P1 BRA 0x9e0 ; BSYNC B1 ; @!P0 BRA 0xcd0 ; IMAD.WIDE R4, R3, 0x8, RZ ; IMAD.MOV.U32 R3, RZ, RZ, R4 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; IADD3 R4, P0, R3, c[0x0][0x168], RZ ; ULDC.64 UR4, c[0x0][0x118] ; LDS.64 R6, [RZ] ; IADD3.X R5, R9, c[0x0][0x16c], RZ, P0, !PT ; LDG.E.64 R4, [R4.64] ; IADD3 R0, R0, -0x1, RZ ; IADD3 R6, P0, R6, R3, RZ ; IADD3 R3, P1, R3, 0x8, RZ ; IMAD.X R7, R7, 0x1, R9.reuse, P0 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; IMAD.X R9, RZ, RZ, R9, P1 ; ST.E.64 [R6.64], R4 ; @P0 BRA 0xc00 ; BSYNC B0 ; IMAD.MOV.U32 R4, RZ, RZ, R22 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; LDS.64 R6, [RZ] ; LD.E.64 R4, [R4.64] ; LD.E R0, [R6.64] ; LD.E R3, [R6.64+0x8] ; LD.E R10, [R6.64+0x10] ; LD.E R11, [R6.64+0x18] ; LD.E R12, [R6.64+0x20] ; LD.E R13, [R6.64+0x28] ; LD.E R14, [R6.64+0x30] ; LD.E R15, [R6.64+0x38] ; LD.E R8, [R4.64] ; BSSY B6, 0xec0 ; MOV R20, 0xeb0 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, R22 ; IMAD R3, R0, 0x21, R3 ; IMAD R10, R3, 0x21, R10 ; IMAD R11, R10, 0x21, R11 ; IMAD R12, R11, 0x21, R12 ; IMAD R13, R12, 0x21, R13 ; IMAD R0, R13, 0x21, R14 ; IMAD R0, R0, 0x21, R15 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; IADD3 R6, R0, 0x7bb34a05, RZ ; LDC.64 R8, c[0x2][R8] ; CALL.REL.NOINC R8 0x0 ; BSYNC B6 ; IMAD.MOV.U32 R12, RZ, RZ, R22 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R13, RZ, RZ, R23 ; LD.E.64 R8, [R12.64] ; LD.E R8, [R8.64+0x8] ; BSSY B6, 0xfa0 ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; MOV R20, 0xf90 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; IMAD.MOV.U32 R4, RZ, RZ, R22 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; LDC.64 R10, c[0x2][R8] ; CALL.REL.NOINC R10 0x0 ; BSYNC B6 ; MOV R12, R22 ; IMAD.MOV.U32 R13, RZ, RZ, R23 ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R8, [R12.64] ; LD.E R8, [R8.64+0x10] ; BSSY B6, 0x1080 ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; MOV R20, 0x1070 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; IMAD.MOV.U32 R4, RZ, RZ, R22 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; LDC.64 R10, c[0x2][R8] ; CALL.REL.NOINC R10 0x0 ; BSYNC B6 ; IMAD.MOV.U32 R12, RZ, RZ, R22 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R13, RZ, RZ, R23 ; LD.E.64 R8, [R12.64] ; LD.E R8, [R8.64+0x18] ; BSSY B6, 0x1160 ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; MOV R20, 0x1150 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; IMAD.MOV.U32 R4, RZ, RZ, R22 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; LDC.64 R10, c[0x2][R8] ; CALL.REL.NOINC R10 0x0 ; BSYNC B6 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; IMAD.MOV.U32 R22, RZ, RZ, R4 ; IMAD.MOV.U32 R19, RZ, RZ, R5 ; ISETP.NE.AND P0, PT, R0, 0x1, PT ; @P0 BRA 0x1ed0 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; MOV R17, 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; LDC.64 R8, c[0x4][R17] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x12f0 ; MOV R20, 0x1270 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x8] ; HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; STL [R1], R0 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1420 ; MOV R20, 0x13a0 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x10] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1550 ; MOV R20, 0x14d0 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x18] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1680 ; MOV R20, 0x1600 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x20] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x17b0 ; MOV R20, 0x1730 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x28] ; HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; STL [R1], R0 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x18e0 ; MOV R20, 0x1860 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x30] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1a10 ; MOV R20, 0x1990 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x38] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1b40 ; MOV R20, 0x1ac0 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x40] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1c70 ; MOV R20, 0x1bf0 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x48] ; HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; STL [R1], R0 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1da0 ; MOV R20, 0x1d20 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x50] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL [R1], R0 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL.64 [R1+0x8], R10 ; LEPC R2 ; MOV R11, 0x1ed0 ; MOV R20, 0x1e50 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R11, R2 ; IADD3.X R21, ~R0, R21, R3, P0, P1 ; CALL.ABS.NOINC R8 ; IMAD.MOV.U32 R3, RZ, RZ, R19 ; IMAD.MOV.U32 R19, RZ, RZ, 0x0 ; RET.REL.NODEC R18 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, R6 ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; RET.REL.NODEC R20 0x0 ; IMAD.SHL.U32 R4, R6, 0x2, RZ ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; RET.REL.NODEC R20 0x0 ; IMAD R4, R6, 0x3, RZ ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; RET.REL.NODEC R20 0x0 ; IMAD.SHL.U32 R4, R6, 0x4, RZ ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; RET.REL.NODEC R20 0x0 ; BRA 0x1fc0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z11test_kernelPmS_jPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; ULDC.64 UR36, c[0x0][0x118] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; IADD3 R1, R1, -0x10, RZ ; LDG.E R2, [R2.64] ; ISETP.NE.AND P0, PT, R2, RZ, PT ; @!P0 BRA 0xe0 ; MOV R20, 0xb0 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; CALL.REL.NOINC 0x180 ; IMAD.MOV.U32 R2, RZ, RZ, -0x66666667 ; IMAD.MOV.U32 R3, RZ, RZ, -0x66666667 ; BRA 0x110 ; MOV R18, 0x100 ; CALL.REL.NOINC 0x300 ; IMAD.MOV.U32 R2, RZ, RZ, R22 ; S2R R4, SR_TID.X ; IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; S2R R5, SR_CTAID.X ; IMAD R4, R5, c[0x0][0x0], R4 ; IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; STG.E.64 [R4.64], R2 ; EXIT ; IADD3 R1, R1, -0x10, RZ ; STL [R1+0x8], R21 ; STL [R1+0x4], R20 ; STL [R1], R2 ; MOV R0, 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; CS2R R6, SRZ ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; LDC.64 R2, c[0x4][R0] ; LEPC R8 ; MOV R11, 0x290 ; MOV R0, 0x210 ; MOV R13, 0x0 ; MOV R10, 0x0 ; IADD3 R20, P0, P1, -R0, R11, R8 ; IADD3.X R21, ~R10, R13, R9, P0, P1 ; CALL.ABS.NOINC R2 ; LDL R20, [R1+0x4] ; IMAD.MOV.U32 R4, RZ, RZ, -0x66666667 ; IMAD.MOV.U32 R5, RZ, RZ, -0x66666667 ; LDL R21, [R1+0x8] ; LDL R2, [R1] ; IADD3 R1, R1, 0x10, RZ ; RET.REL.NODEC R20 0x0 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; ISETP.NE.AND P0, PT, R0, 0x2, PT ; @P0 BRA 0x400 ; MOV R0, 0x8 ; IMAD.MOV.U32 R4, RZ, RZ, 0x40 ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; LDC.64 R2, c[0x4][R0] ; LEPC R6 ; MOV R9, 0x3f0 ; MOV R20, 0x370 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R9, R6 ; IADD3.X R21, ~R0, R21, R7, P0, P1 ; CALL.ABS.NOINC R2 ; STS.64 [RZ], R4 ; MOV R0, 0x8 ; IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; IADD3 R16, P0, R1, c[0x0][0x20], RZ ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; LDC.64 R6, c[0x4][R0] ; IMAD.X R2, RZ, RZ, c[0x0][0x24], P0 ; LEPC R8 ; MOV R3, 0x4e0 ; MOV R20, 0x460 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R8 ; IADD3.X R21, ~R0, R21, R9, P0, P1 ; CALL.ABS.NOINC R6 ; ULDC.64 UR4, c[0x4][0x10] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; UIADD3 UR4, UP0, UR4, 0x10, URZ ; MOV R17, 0x0 ; IMAD.MOV.U32 R22, RZ, RZ, R4 ; MOV R7, R2 ; UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; LDC.64 R8, c[0x4][R17] ; IMAD.U32 R12, RZ, RZ, UR4 ; IMAD.MOV.U32 R23, RZ, RZ, R5 ; IMAD.U32 R13, RZ, RZ, UR5 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; ST.E.64 [R4.64], R12 ; LDS.64 R10, [RZ] ; STL [R1], R0 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x20] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x24] ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x690 ; MOV R20, 0x610 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; IMAD.MOV.U32 R10, RZ, RZ, 0x28 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x28] ; STL.64 [R1+0x8], R10 ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x2c] ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; STL [R1], R0 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; LEPC R10 ; MOV R3, 0x7b0 ; MOV R20, 0x730 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; LDC.64 R8, c[0x4][R17] ; STL.64 [R1+0x8], R22 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x30] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x34] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; LEPC R10 ; MOV R3, 0x8b0 ; MOV R20, 0x830 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; S2R R0, SR_TID.X ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; BSSY B0, 0xce0 ; ISETP.NE.AND P0, PT, R0, 0x1, PT ; ISETP.NE.OR P0, PT, R3, 0x2, P0 ; ISETP.EQ.OR P0, PT, RZ, c[0x0][0x170], P0 ; @P0 BRA 0xcd0 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; IADD3 R3, R0.reuse, -0x1, RZ ; LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; IMAD.MOV.U32 R3, RZ, RZ, RZ ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P1 BRA 0xbc0 ; BSSY B1, 0xbc0 ; IADD3 R17, -R0, c[0x0][0x170], RZ ; IMAD.MOV.U32 R3, RZ, RZ, RZ ; IMAD.MOV.U32 R19, RZ, RZ, 0x10 ; IMAD.MOV.U32 R27, RZ, RZ, RZ ; IADD3 R4, P1, R19, c[0x0][0x168], RZ ; ULDC.64 UR4, c[0x0][0x118] ; LDS.64 R8, [RZ] ; IADD3.X R5, R27, c[0x0][0x16c], RZ, P1, !PT ; LDG.E.64 R6, [R4.64+-0x10] ; IADD3 R14, P1, R8, R19, RZ ; IADD3.X R15, R9, R27, RZ, P1, !PT ; ST.E.64 [R14.64+-0x10], R6 ; LDG.E.64 R8, [R4.64+-0x8] ; LDS.64 R10, [RZ] ; IADD3 R20, P1, R10, R19, RZ ; IMAD.X R21, R11, 0x1, R27, P1 ; ST.E.64 [R20.64+-0x8], R8 ; LDG.E.64 R10, [R4.64] ; LDS.64 R12, [RZ] ; IADD3 R24, P1, R12, R19, RZ ; IMAD.X R25, R13, 0x1, R27, P1 ; ST.E.64 [R24.64], R10 ; LDG.E.64 R6, [R4.64+0x8] ; IADD3 R17, R17, -0x4, RZ ; IADD3 R3, R3, 0x4, RZ ; LDS.64 R12, [RZ] ; IADD3 R12, P1, R12, R19, RZ ; IADD3 R19, P2, R19, 0x20, RZ ; IMAD.X R13, R13, 0x1, R27.reuse, P1 ; ISETP.NE.AND P1, PT, R17, RZ, PT ; IMAD.X R27, RZ, RZ, R27, P2 ; ST.E.64 [R12.64+0x8], R6 ; @P1 BRA 0x9e0 ; BSYNC B1 ; @!P0 BRA 0xcd0 ; IMAD.WIDE R4, R3, 0x8, RZ ; IMAD.MOV.U32 R3, RZ, RZ, R4 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; IADD3 R4, P0, R3, c[0x0][0x168], RZ ; ULDC.64 UR4, c[0x0][0x118] ; LDS.64 R6, [RZ] ; IADD3.X R5, R9, c[0x0][0x16c], RZ, P0, !PT ; LDG.E.64 R4, [R4.64] ; IADD3 R0, R0, -0x1, RZ ; IADD3 R6, P0, R6, R3, RZ ; IADD3 R3, P1, R3, 0x8, RZ ; IMAD.X R7, R7, 0x1, R9.reuse, P0 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; IMAD.X R9, RZ, RZ, R9, P1 ; ST.E.64 [R6.64], R4 ; @P0 BRA 0xc00 ; BSYNC B0 ; IMAD.MOV.U32 R4, RZ, RZ, R22 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; LDS.64 R6, [RZ] ; LD.E.64 R4, [R4.64] ; LD.E R0, [R6.64] ; LD.E R3, [R6.64+0x8] ; LD.E R10, [R6.64+0x10] ; LD.E R11, [R6.64+0x18] ; LD.E R12, [R6.64+0x20] ; LD.E R13, [R6.64+0x28] ; LD.E R14, [R6.64+0x30] ; LD.E R15, [R6.64+0x38] ; LD.E R8, [R4.64] ; BSSY B6, 0xec0 ; MOV R20, 0xeb0 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, R22 ; IMAD R3, R0, 0x21, R3 ; IMAD R10, R3, 0x21, R10 ; IMAD R11, R10, 0x21, R11 ; IMAD R12, R11, 0x21, R12 ; IMAD R13, R12, 0x21, R13 ; IMAD R0, R13, 0x21, R14 ; IMAD R0, R0, 0x21, R15 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; IADD3 R6, R0, 0x7bb34a05, RZ ; LDC.64 R8, c[0x2][R8] ; CALL.REL.NOINC R8 0x0 ; BSYNC B6 ; IMAD.MOV.U32 R12, RZ, RZ, R22 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R13, RZ, RZ, R23 ; LD.E.64 R8, [R12.64] ; LD.E R8, [R8.64+0x8] ; BSSY B6, 0xfa0 ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; MOV R20, 0xf90 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; IMAD.MOV.U32 R4, RZ, RZ, R22 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; LDC.64 R10, c[0x2][R8] ; CALL.REL.NOINC R10 0x0 ; BSYNC B6 ; MOV R12, R22 ; IMAD.MOV.U32 R13, RZ, RZ, R23 ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R8, [R12.64] ; LD.E R8, [R8.64+0x10] ; BSSY B6, 0x1080 ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; MOV R20, 0x1070 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; IMAD.MOV.U32 R4, RZ, RZ, R22 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; LDC.64 R10, c[0x2][R8] ; CALL.REL.NOINC R10 0x0 ; BSYNC B6 ; IMAD.MOV.U32 R12, RZ, RZ, R22 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R13, RZ, RZ, R23 ; LD.E.64 R8, [R12.64] ; LD.E R8, [R8.64+0x18] ; BSSY B6, 0x1160 ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; MOV R20, 0x1150 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; IMAD.MOV.U32 R4, RZ, RZ, R22 ; IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; LDC.64 R10, c[0x2][R8] ; CALL.REL.NOINC R10 0x0 ; BSYNC B6 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; IMAD.MOV.U32 R22, RZ, RZ, R4 ; IMAD.MOV.U32 R19, RZ, RZ, R5 ; ISETP.NE.AND P0, PT, R0, 0x1, PT ; @P0 BRA 0x1ed0 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; MOV R17, 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; LDC.64 R8, c[0x4][R17] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x12f0 ; MOV R20, 0x1270 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x8] ; HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; STL [R1], R0 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1420 ; MOV R20, 0x13a0 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x10] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1550 ; MOV R20, 0x14d0 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x18] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1680 ; MOV R20, 0x1600 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x20] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x17b0 ; MOV R20, 0x1730 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x28] ; HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; STL [R1], R0 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x18e0 ; MOV R20, 0x1860 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x30] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1a10 ; MOV R20, 0x1990 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x38] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1b40 ; MOV R20, 0x1ac0 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x40] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL [R1], R0 ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1c70 ; MOV R20, 0x1bf0 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x48] ; HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; STL [R1], R0 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL.64 [R1+0x8], R10 ; LEPC R10 ; MOV R3, 0x1da0 ; MOV R20, 0x1d20 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R3, R10 ; IADD3.X R21, ~R0, R21, R11, P0, P1 ; CALL.ABS.NOINC R8 ; LDS.64 R10, [RZ] ; ULDC.64 UR4, c[0x0][0x118] ; LD.E.64 R10, [R10.64+0x50] ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LDC.64 R8, c[0x4][R17] ; IMAD.MOV.U32 R6, RZ, RZ, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R2 ; STL [R1], R0 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x38] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x3c] ; STL.64 [R1+0x8], R10 ; LEPC R2 ; MOV R11, 0x1ed0 ; MOV R20, 0x1e50 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R11, R2 ; IADD3.X R21, ~R0, R21, R3, P0, P1 ; CALL.ABS.NOINC R8 ; IMAD.MOV.U32 R3, RZ, RZ, R19 ; IMAD.MOV.U32 R19, RZ, RZ, 0x0 ; RET.REL.NODEC R18 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, R6 ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; RET.REL.NODEC R20 0x0 ; IMAD.SHL.U32 R4, R6, 0x2, RZ ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; RET.REL.NODEC R20 0x0 ; IMAD R4, R6, 0x3, RZ ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; RET.REL.NODEC R20 0x0 ; IMAD.SHL.U32 R4, R6, 0x4, RZ ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; RET.REL.NODEC R20 0x0 ; BRA 0x1fc0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0002e5c9_00000000-6_4836af2626a3d02cbee1b44129c8c87ce99027fe.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .align 2 .globl _ZN1D2f1Ej .type _ZN1D2f1Ej, @function _ZN1D2f1Ej: .LFB3712: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE3712: .size _ZN1D2f1Ej, .-_ZN1D2f1Ej .align 2 .globl _ZN1D2f2Ej .type _ZN1D2f2Ej, @function _ZN1D2f2Ej: .LFB3713: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE3713: .size _ZN1D2f2Ej, .-_ZN1D2f2Ej .align 2 .globl _ZN1D2f3Ej .type _ZN1D2f3Ej, @function _ZN1D2f3Ej: .LFB3714: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE3714: .size _ZN1D2f3Ej, .-_ZN1D2f3Ej .align 2 .globl _ZN1D2f4Ej .type _ZN1D2f4Ej, @function _ZN1D2f4Ej: .LFB3715: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE3715: .size _ZN1D2f4Ej, .-_ZN1D2f4Ej .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string " returned " .LC1: .string "(" .LC2: .string ") at " .LC3: .string ":" .text .type _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, @function _ZL17CheckCudaErrorAuxPKcjS0_9cudaError: .LFB3719: .cfi_startproc testl %ecx, %ecx jne .L15 ret .L15: pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $8, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbp movl %esi, %r12d movl %ecx, %ebx movq %rdx, %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi leaq .LC0(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %r13 movl %ebx, %edi call cudaGetErrorString@PLT movq %rax, %rsi movq %r13, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi leaq .LC1(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl %ebx, %esi call _ZNSolsEi@PLT movq %rax, %rdi leaq .LC2(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq %rbp, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi leaq .LC3(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl %r12d, %esi call _ZNSo9_M_insertImEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %edi call exit@PLT .cfi_endproc .LFE3719: .size _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, .-_ZL17CheckCudaErrorAuxPKcjS0_9cudaError .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3722: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3722: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z6secretv .type _Z6secretv, @function _Z6secretv: .LFB3716: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE3716: .size _Z6secretv, .-_Z6secretv .globl _Z6unsafePmj .type _Z6unsafePmj, @function _Z6unsafePmj: .LFB3717: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE3717: .size _Z6unsafePmj, .-_Z6unsafePmj .globl _Z36__device_stub__Z11test_kernelPmS_jPiPmS_jPi .type _Z36__device_stub__Z11test_kernelPmS_jPiPmS_jPi, @function _Z36__device_stub__Z11test_kernelPmS_jPiPmS_jPi: .LFB3744: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %rcx, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L26 .L22: movq 136(%rsp), %rax subq %fs:40, %rax jne .L27 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L26: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z11test_kernelPmS_jPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L22 .L27: call __stack_chk_fail@PLT .cfi_endproc .LFE3744: .size _Z36__device_stub__Z11test_kernelPmS_jPiPmS_jPi, .-_Z36__device_stub__Z11test_kernelPmS_jPiPmS_jPi .globl _Z11test_kernelPmS_jPi .type _Z11test_kernelPmS_jPi, @function _Z11test_kernelPmS_jPi: .LFB3745: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z11test_kernelPmS_jPiPmS_jPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3745: .size _Z11test_kernelPmS_jPi, .-_Z11test_kernelPmS_jPi .globl _Z37__device_stub__Z12test_kernel2PmS_jPiPmS_jPi .type _Z37__device_stub__Z12test_kernel2PmS_jPiPmS_jPi, @function _Z37__device_stub__Z12test_kernel2PmS_jPiPmS_jPi: .LFB3746: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %rcx, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L34 .L30: movq 136(%rsp), %rax subq %fs:40, %rax jne .L35 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L34: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z12test_kernel2PmS_jPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L30 .L35: call __stack_chk_fail@PLT .cfi_endproc .LFE3746: .size _Z37__device_stub__Z12test_kernel2PmS_jPiPmS_jPi, .-_Z37__device_stub__Z12test_kernel2PmS_jPiPmS_jPi .globl _Z12test_kernel2PmS_jPi .type _Z12test_kernel2PmS_jPi, @function _Z12test_kernel2PmS_jPi: .LFB3747: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z37__device_stub__Z12test_kernel2PmS_jPiPmS_jPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3747: .size _Z12test_kernel2PmS_jPi, .-_Z12test_kernel2PmS_jPi .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC4: .string "cudaMalloc((void**)&dev_hashes,N*sizeof(unsigned long))" .align 8 .LC5: .string "/home/ubuntu/Datasets/Stack_v2_cuda-hip/train/4836af2626a3d02cbee1b44129c8c87ce99027fe.cu" .align 8 .LC6: .string "cudaMalloc((void**)&dev_hashes2,N*sizeof(unsigned long))" .align 8 .LC7: .string "cudaMalloc((void**)&dev_input,100*sizeof(unsigned long))" .align 8 .LC8: .string "cudaMalloc((void**)&dev_input2,100*sizeof(unsigned long))" .align 8 .LC9: .string "cudaMalloc((void**)&dev_admin,sizeof(int))" .align 8 .LC10: .string "cudaMemcpy(dev_input,input,100*sizeof(unsigned long),cudaMemcpyHostToDevice)" .align 8 .LC11: .string "cudaMemcpy(dev_input2,input2,100*sizeof(unsigned long),cudaMemcpyHostToDevice)" .align 8 .LC12: .string "cudaMemcpy(dev_admin,&admin,sizeof(int),cudaMemcpyHostToDevice)" .align 8 .LC13: .string "cudaMemcpy(&hashes,dev_hashes,N*sizeof(unsigned long),cudaMemcpyDeviceToHost)" .align 8 .LC14: .string "cudaMemcpy(&hashes2,dev_hashes2,N*sizeof(unsigned long),cudaMemcpyDeviceToHost)" .section .rodata.str1.1 .LC15: .string "%d, %lx\n" .text .globl main .type main, @function main: .LFB3718: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 subq $1728, %rsp .cfi_def_cfa_offset 1744 movq %fs:40, %rax movq %rax, 1720(%rsp) xorl %eax, %eax movl $0, 12(%rsp) movq $20, 112(%rsp) movq $20, 120(%rsp) movq $20, 128(%rsp) movq $20, 136(%rsp) leaq 144(%rsp), %rax leaq 592(%rsp), %rcx movabsq $21514942752, %rdx .L39: movq %rdx, (%rax) addq $8, %rax cmpq %rax, %rcx jne .L39 movq $20, 912(%rsp) movq $20, 920(%rsp) movq $20, 928(%rsp) movq $20, 936(%rsp) leaq 944(%rsp), %rax leaq 1232(%rsp), %rdx .L40: movq $69905, (%rax) addq $8, %rax cmpq %rdx, %rax jne .L40 leaq 16(%rsp), %rdi movl $16, %esi call cudaMalloc@PLT movl %eax, %ecx leaq .LC4(%rip), %rdx movl $124, %esi leaq .LC5(%rip), %rbx movq %rbx, %rdi call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError leaq 24(%rsp), %rdi movl $16, %esi call cudaMalloc@PLT movl %eax, %ecx leaq .LC6(%rip), %rdx movl $125, %esi movq %rbx, %rdi call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError leaq 32(%rsp), %rdi movl $800, %esi call cudaMalloc@PLT movl %eax, %ecx leaq .LC7(%rip), %rdx movl $126, %esi movq %rbx, %rdi call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError leaq 40(%rsp), %rdi movl $800, %esi call cudaMalloc@PLT movl %eax, %ecx leaq .LC8(%rip), %rdx movl $127, %esi movq %rbx, %rdi call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError leaq 48(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT movl %eax, %ecx leaq .LC9(%rip), %rdx movl $128, %esi movq %rbx, %rdi call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError leaq 112(%rsp), %rsi movl $1, %ecx movl $800, %edx movq 32(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %ecx leaq .LC10(%rip), %rdx movl $129, %esi movq %rbx, %rdi call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError leaq 912(%rsp), %rsi movl $1, %ecx movl $800, %edx movq 40(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %ecx leaq .LC11(%rip), %rdx movl $130, %esi movq %rbx, %rdi call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError leaq 12(%rsp), %rsi movl $1, %ecx movl $4, %edx movq 48(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %ecx leaq .LC12(%rip), %rdx movl $131, %esi movq %rbx, %rdi call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError movl $2, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $0, %r9d movl $0, %r8d movq 68(%rsp), %rdx movl $1, %ecx movq 56(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L47 .L41: movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $0, %r9d movl $0, %r8d movq 68(%rsp), %rdx movl $1, %ecx movq 56(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L48 .L42: leaq 80(%rsp), %rdi movl $2, %ecx movl $16, %edx movq 16(%rsp), %rsi call cudaMemcpy@PLT movl %eax, %ecx leaq .LC13(%rip), %rdx movl $139, %esi leaq .LC5(%rip), %rbx movq %rbx, %rdi call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError leaq 96(%rsp), %rdi movl $2, %ecx movl $16, %edx movq 24(%rsp), %rsi call cudaMemcpy@PLT movl %eax, %ecx leaq .LC14(%rip), %rdx movl $140, %esi movq %rbx, %rdi call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError movq 80(%rsp), %rcx movl $0, %edx leaq .LC15(%rip), %rbx movq %rbx, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 88(%rsp), %rcx movl $1, %edx movq %rbx, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 96(%rsp), %rcx movl $0, %edx movq %rbx, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 104(%rsp), %rcx movl $1, %edx movq %rbx, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq _ZSt4cout(%rip), %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 48(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 1720(%rsp), %rax subq %fs:40, %rax jne .L49 movl $0, %eax addq $1728, %rsp .cfi_remember_state .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 ret .L47: .cfi_restore_state movq 48(%rsp), %rcx movl $8, %edx movq 32(%rsp), %rsi movq 16(%rsp), %rdi call _Z36__device_stub__Z11test_kernelPmS_jPiPmS_jPi jmp .L41 .L48: movq 48(%rsp), %rcx movl $8, %edx movq 40(%rsp), %rsi movq 24(%rsp), %rdi call _Z37__device_stub__Z12test_kernel2PmS_jPiPmS_jPi jmp .L42 .L49: call __stack_chk_fail@PLT .cfi_endproc .LFE3718: .size main, .-main .section .rodata.str1.1 .LC16: .string "_Z12test_kernel2PmS_jPi" .LC17: .string "_Z11test_kernelPmS_jPi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3749: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC16(%rip), %rdx movq %rdx, %rcx leaq _Z12test_kernel2PmS_jPi(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC17(%rip), %rdx movq %rdx, %rcx leaq _Z11test_kernelPmS_jPi(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3749: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .weak _ZTS1B .section .rodata._ZTS1B,"aG",@progbits,_ZTS1B,comdat .type _ZTS1B, @object .size _ZTS1B, 3 _ZTS1B: .string "1B" .weak _ZTI1B .section .data.rel.ro._ZTI1B,"awG",@progbits,_ZTI1B,comdat .align 8 .type _ZTI1B, @object .size _ZTI1B, 16 _ZTI1B: .quad _ZTVN10__cxxabiv117__class_type_infoE+16 .quad _ZTS1B .weak _ZTS1D .section .rodata._ZTS1D,"aG",@progbits,_ZTS1D,comdat .type _ZTS1D, @object .size _ZTS1D, 3 _ZTS1D: .string "1D" .weak _ZTI1D .section .data.rel.ro._ZTI1D,"awG",@progbits,_ZTI1D,comdat .align 8 .type _ZTI1D, @object .size _ZTI1D, 24 _ZTI1D: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTS1D .quad _ZTI1B .weak _ZTV1D .section .data.rel.ro.local._ZTV1D,"awG",@progbits,_ZTV1D,comdat .align 8 .type _ZTV1D, @object .size _ZTV1D, 48 _ZTV1D: .quad 0 .quad _ZTI1D .quad _ZN1D2f1Ej .quad _ZN1D2f2Ej .quad _ZN1D2f3Ej .quad _ZN1D2f4Ej .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .p2align 2 ; -- Begin function _ZN1D2f1Ej .type _ZN1D2f1Ej,@function _ZN1D2f1Ej: ; @_ZN1D2f1Ej ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, 0 s_setpc_b64 s[30:31] .Lfunc_end0: .size _ZN1D2f1Ej, .Lfunc_end0-_ZN1D2f1Ej ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 16 ; NumSgprs: 32 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 .text .p2align 2 ; -- Begin function _ZN1D2f2Ej .type _ZN1D2f2Ej,@function _ZN1D2f2Ej: ; @_ZN1D2f2Ej ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 1, v2 s_setpc_b64 s[30:31] .Lfunc_end1: .size _ZN1D2f2Ej, .Lfunc_end1-_ZN1D2f2Ej ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 16 ; NumSgprs: 32 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 .text .p2align 2 ; -- Begin function _ZN1D2f3Ej .type _ZN1D2f3Ej,@function _ZN1D2f3Ej: ; @_ZN1D2f3Ej ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) v_lshl_add_u32 v0, v2, 1, v2 v_mov_b32_e32 v1, 0 s_setpc_b64 s[30:31] .Lfunc_end2: .size _ZN1D2f3Ej, .Lfunc_end2-_ZN1D2f3Ej ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 20 ; NumSgprs: 32 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 .text .p2align 2 ; -- Begin function _ZN1D2f4Ej .type _ZN1D2f4Ej,@function _ZN1D2f4Ej: ; @_ZN1D2f4Ej ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v2 s_setpc_b64 s[30:31] .Lfunc_end3: .size _ZN1D2f4Ej, .Lfunc_end3-_ZN1D2f4Ej ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 16 ; NumSgprs: 32 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 .text .p2align 2 ; -- Begin function _Z6secretv .type _Z6secretv,@function _Z6secretv: ; @_Z6secretv ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) s_load_b64 s[2:3], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v20, -1, 0 v_mov_b32_e32 v6, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20 ;;#ASMSTART ;;#ASMEND v_readfirstlane_b32 s0, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s0, s0, v4 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_6 ; %bb.1: v_mov_b32_e32 v0, 0 s_mov_b32 s4, exec_lo s_waitcnt lgkmcnt(0) global_load_b64 v[8:9], v0, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[5:6], v0, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB4_5 ; %bb.2: ; %.preheader3.i.i.i.preheader s_mov_b32 s5, 0 .p2align 6 .LBB4_3: ; %.preheader3.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[10:11], v0, s[2:3] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB4_3 ; %bb.4: ; %Flow240 s_or_b32 exec_lo, exec_lo, s5 .LBB4_5: ; %Flow242 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB4_6: ; %.loopexit4.i.i.i s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s4, v6 v_readfirstlane_b32 s5, v7 s_mov_b32 s8, exec_lo s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[8:9], v5, s[2:3] offset:40 global_load_b128 v[0:3], v5, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_8 ; %bb.7: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB4_8: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 v_lshlrev_b64 v[4:5], 6, v[4:5] s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v2, s8 v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo v_mov_b32_e32 v3, 0 s_mov_b32 s8, 0 s_delay_alu instid0(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, v2, v4 v_mov_b32_e32 v2, 33 s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v4, v3 v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8 v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10 v_mov_b32_e32 v11, s11 s_clause 0x3 global_store_b128 v[6:7], v[2:5], off global_store_b128 v[6:7], v[8:11], off offset:16 global_store_b128 v[6:7], v[8:11], off offset:32 global_store_b128 v[6:7], v[8:11], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_16 ; %bb.9: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4 v_mov_b32_e32 v12, s5 s_clause 0x1 global_load_b64 v[13:14], v10, s[2:3] offset:32 glc global_load_b64 v[2:3], v10, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 v_readfirstlane_b32 s9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v8, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[13:14] s_cbranch_execz .LBB4_12 ; %bb.10: ; %.preheader1.i.i.i.preheader s_mov_b32 s9, 0 .LBB4_11: ; %.preheader1.i.i.i ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 s_sleep 1 global_store_b64 v[8:9], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB4_11 .LBB4_12: ; %Flow238 s_or_b32 exec_lo, exec_lo, s8 v_mov_b32_e32 v2, 0 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v4, s9, 0 global_load_b64 v[2:3], v2, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB4_14 ; %bb.13: s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB4_14: s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB4_16 ; %bb.15: global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB4_16: ; %Flow239 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB4_20 .p2align 6 .LBB4_17: ; in Loop: Header=BB4_20 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB4_19 ; %bb.18: ; in Loop: Header=BB4_20 Depth=1 s_sleep 1 s_cbranch_execnz .LBB4_20 s_branch .LBB4_22 .p2align 6 .LBB4_19: s_branch .LBB4_22 .LBB4_20: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_17 ; %bb.21: ; in Loop: Header=BB4_20 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB4_17 .LBB4_22: global_load_b64 v[22:23], v[6:7], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_26 ; %bb.23: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[2:3] offset:40 global_load_b64 v[7:8], v6, s[2:3] offset:24 glc global_load_b64 v[4:5], v6, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s4 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB4_26 ; %bb.24: ; %.preheader.i.i.i.preheader s_mov_b32 s0, 0 .LBB4_25: ; %.preheader.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB4_25 .LBB4_26: ; %__ockl_printf_begin.exit s_or_b32 exec_lo, exec_lo, s1 s_getpc_b64 s[4:5] s_add_u32 s4, s4, .str@rel32@lo+4 s_addc_u32 s5, s5, .str@rel32@hi+12 s_mov_b32 s0, -1 s_cmp_lg_u64 s[4:5], 0 s_cbranch_scc0 .LBB4_105 ; %bb.27: s_waitcnt vmcnt(0) v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22 v_mov_b32_e32 v25, 0 s_mov_b64 s[6:7], 14 s_branch .LBB4_29 .LBB4_28: ; %__ockl_hostcall_preview.exit20.i ; in Loop: Header=BB4_29 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_sub_u32 s6, s6, s8 s_subb_u32 s7, s7, s9 s_add_u32 s4, s4, s8 s_addc_u32 s5, s5, s9 s_cmp_lg_u64 s[6:7], 0 s_cbranch_scc0 .LBB4_104 .LBB4_29: ; =>This Loop Header: Depth=1 ; Child Loop BB4_32 Depth 2 ; Child Loop BB4_39 Depth 2 ; Child Loop BB4_46 Depth 2 ; Child Loop BB4_53 Depth 2 ; Child Loop BB4_60 Depth 2 ; Child Loop BB4_67 Depth 2 ; Child Loop BB4_74 Depth 2 ; Child Loop BB4_81 Depth 2 ; Child Loop BB4_89 Depth 2 ; Child Loop BB4_98 Depth 2 ; Child Loop BB4_103 Depth 2 v_cmp_lt_u64_e64 s0, s[6:7], 56 ; implicit-def: $sgpr15 s_delay_alu instid0(VALU_DEP_1) s_and_b32 s0, s0, exec_lo s_cselect_b32 s8, s6, 56 s_cselect_b32 s9, s7, 0 s_cmp_gt_u32 s8, 7 s_mov_b32 s0, -1 s_cbranch_scc1 .LBB4_34 ; %bb.30: ; in Loop: Header=BB4_29 Depth=1 v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 s_cmp_eq_u32 s8, 0 s_cbranch_scc1 .LBB4_33 ; %bb.31: ; %.preheader31.i.preheader ; in Loop: Header=BB4_29 Depth=1 s_lshl_b64 s[0:1], s[8:9], 3 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], s[4:5] .LBB4_32: ; %.preheader31.i ; Parent Loop BB4_29 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v4, v25, s[12:13] s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v4 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[4:5], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_add_u32 s12, s12, 1 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s0, s10 v_or_b32_e32 v2, v4, v2 v_or_b32_e32 v3, v5, v3 s_cbranch_scc1 .LBB4_32 .LBB4_33: ; %Flow208 ; in Loop: Header=BB4_29 Depth=1 s_mov_b32 s0, 0 s_mov_b32 s15, 0 .LBB4_34: ; %Flow210 ; in Loop: Header=BB4_29 Depth=1 s_and_not1_b32 vcc_lo, exec_lo, s0 s_mov_b64 s[0:1], s[4:5] s_cbranch_vccnz .LBB4_36 ; %bb.35: ; in Loop: Header=BB4_29 Depth=1 global_load_b64 v[2:3], v25, s[4:5] s_add_i32 s15, s8, -8 s_add_u32 s0, s4, 8 s_addc_u32 s1, s5, 0 .LBB4_36: ; %.loopexit32.i ; in Loop: Header=BB4_29 Depth=1 s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB4_41 ; %bb.37: ; in Loop: Header=BB4_29 Depth=1 v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB4_40 ; %bb.38: ; %.preheader29.i.preheader ; in Loop: Header=BB4_29 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB4_39: ; %.preheader29.i ; Parent Loop BB4_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v6, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v4, v6, v4 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v5, v7, v5 s_cbranch_scc1 .LBB4_39 .LBB4_40: ; %Flow203 ; in Loop: Header=BB4_29 Depth=1 s_mov_b32 s14, 0 s_cbranch_execz .LBB4_42 s_branch .LBB4_43 .LBB4_41: ; in Loop: Header=BB4_29 Depth=1 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $sgpr14 .LBB4_42: ; in Loop: Header=BB4_29 Depth=1 global_load_b64 v[4:5], v25, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB4_43: ; %.loopexit30.i ; in Loop: Header=BB4_29 Depth=1 s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB4_48 ; %bb.44: ; in Loop: Header=BB4_29 Depth=1 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB4_47 ; %bb.45: ; %.preheader27.i.preheader ; in Loop: Header=BB4_29 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB4_46: ; %.preheader27.i ; Parent Loop BB4_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v8, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s14, s12 v_or_b32_e32 v6, v8, v6 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v7, v9, v7 s_cbranch_scc1 .LBB4_46 .LBB4_47: ; %Flow198 ; in Loop: Header=BB4_29 Depth=1 s_mov_b32 s15, 0 s_cbranch_execz .LBB4_49 s_branch .LBB4_50 .LBB4_48: ; in Loop: Header=BB4_29 Depth=1 ; implicit-def: $sgpr15 .LBB4_49: ; in Loop: Header=BB4_29 Depth=1 global_load_b64 v[6:7], v25, s[0:1] s_add_i32 s15, s14, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB4_50: ; %.loopexit28.i ; in Loop: Header=BB4_29 Depth=1 s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB4_55 ; %bb.51: ; in Loop: Header=BB4_29 Depth=1 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB4_54 ; %bb.52: ; %.preheader25.i.preheader ; in Loop: Header=BB4_29 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB4_53: ; %.preheader25.i ; Parent Loop BB4_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v10, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[10:11], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v8, v10, v8 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v9, v11, v9 s_cbranch_scc1 .LBB4_53 .LBB4_54: ; %Flow193 ; in Loop: Header=BB4_29 Depth=1 s_mov_b32 s14, 0 s_cbranch_execz .LBB4_56 s_branch .LBB4_57 .LBB4_55: ; in Loop: Header=BB4_29 Depth=1 ; implicit-def: $vgpr8_vgpr9 ; implicit-def: $sgpr14 .LBB4_56: ; in Loop: Header=BB4_29 Depth=1 global_load_b64 v[8:9], v25, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB4_57: ; %.loopexit26.i ; in Loop: Header=BB4_29 Depth=1 s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB4_62 ; %bb.58: ; in Loop: Header=BB4_29 Depth=1 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB4_61 ; %bb.59: ; %.preheader23.i.preheader ; in Loop: Header=BB4_29 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB4_60: ; %.preheader23.i ; Parent Loop BB4_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v12, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[12:13], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s14, s12 v_or_b32_e32 v10, v12, v10 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v11, v13, v11 s_cbranch_scc1 .LBB4_60 .LBB4_61: ; %Flow188 ; in Loop: Header=BB4_29 Depth=1 s_mov_b32 s15, 0 s_cbranch_execz .LBB4_63 s_branch .LBB4_64 .LBB4_62: ; in Loop: Header=BB4_29 Depth=1 ; implicit-def: $sgpr15 .LBB4_63: ; in Loop: Header=BB4_29 Depth=1 global_load_b64 v[10:11], v25, s[0:1] s_add_i32 s15, s14, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB4_64: ; %.loopexit24.i ; in Loop: Header=BB4_29 Depth=1 s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB4_69 ; %bb.65: ; in Loop: Header=BB4_29 Depth=1 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB4_68 ; %bb.66: ; %.preheader21.i.preheader ; in Loop: Header=BB4_29 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB4_67: ; %.preheader21.i ; Parent Loop BB4_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v14, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[14:15], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v12, v14, v12 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v13, v15, v13 s_cbranch_scc1 .LBB4_67 .LBB4_68: ; %Flow183 ; in Loop: Header=BB4_29 Depth=1 s_mov_b32 s14, 0 s_cbranch_execz .LBB4_70 s_branch .LBB4_71 .LBB4_69: ; in Loop: Header=BB4_29 Depth=1 ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $sgpr14 .LBB4_70: ; in Loop: Header=BB4_29 Depth=1 global_load_b64 v[12:13], v25, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB4_71: ; %.loopexit22.i ; in Loop: Header=BB4_29 Depth=1 s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB4_76 ; %bb.72: ; in Loop: Header=BB4_29 Depth=1 v_mov_b32_e32 v14, 0 v_mov_b32_e32 v15, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB4_75 ; %bb.73: ; %.preheader.i.preheader ; in Loop: Header=BB4_29 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], s[0:1] .LBB4_74: ; %.preheader.i ; Parent Loop BB4_29 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v16, v25, s[12:13] s_add_i32 s14, s14, -1 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v16 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[16:17], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_add_u32 s12, s12, 1 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s14, 0 v_or_b32_e32 v14, v16, v14 v_or_b32_e32 v15, v17, v15 s_cbranch_scc1 .LBB4_74 .LBB4_75: ; %Flow178 ; in Loop: Header=BB4_29 Depth=1 s_cbranch_execz .LBB4_77 s_branch .LBB4_78 .LBB4_76: ; in Loop: Header=BB4_29 Depth=1 .LBB4_77: ; in Loop: Header=BB4_29 Depth=1 global_load_b64 v[14:15], v25, s[0:1] .LBB4_78: ; %.loopexit.i ; in Loop: Header=BB4_29 Depth=1 v_mov_b32_e32 v24, v20 v_mov_b32_e32 v26, 0 v_mov_b32_e32 v27, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v24 v_cmp_eq_u32_e64 s0, s0, v24 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_84 ; %bb.79: ; in Loop: Header=BB4_29 Depth=1 global_load_b64 v[18:19], v25, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[16:17], v25, s[2:3] offset:40 global_load_b64 v[26:27], v25, s[2:3] s_mov_b32 s10, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v17, v17, v19 v_and_b32_e32 v16, v16, v18 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v17, v17, 24 v_mul_hi_u32 v21, v16, 24 v_mul_lo_u32 v16, v16, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v17, v21, v17 s_waitcnt vmcnt(0) v_add_co_u32 v16, vcc_lo, v26, v16 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo global_load_b64 v[16:17], v[16:17], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[26:27], v[18:19] s_cbranch_execz .LBB4_83 ; %bb.80: ; %.preheader3.i.i19.i.preheader ; in Loop: Header=BB4_29 Depth=1 s_mov_b32 s11, 0 .p2align 6 .LBB4_81: ; %.preheader3.i.i19.i ; Parent Loop BB4_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 s_clause 0x1 global_load_b64 v[16:17], v25, s[2:3] offset:40 global_load_b64 v[28:29], v25, s[2:3] v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v16, v16, v18 s_waitcnt vmcnt(0) v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19 v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17] global_load_b64 v[16:17], v[26:27], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19] s_or_b32 s11, vcc_lo, s11 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s11 s_cbranch_execnz .LBB4_81 ; %bb.82: ; %Flow173 ; in Loop: Header=BB4_29 Depth=1 s_or_b32 exec_lo, exec_lo, s11 .LBB4_83: ; %Flow175 ; in Loop: Header=BB4_29 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s10 .LBB4_84: ; %.loopexit4.i.i14.i ; in Loop: Header=BB4_29 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_clause 0x1 global_load_b64 v[28:29], v25, s[2:3] offset:40 global_load_b128 v[16:19], v25, s[2:3] v_readfirstlane_b32 s10, v26 v_readfirstlane_b32 s11, v27 s_mov_b32 s14, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s12, v28 v_readfirstlane_b32 s13, v29 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[12:13], s[10:11], s[12:13] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_86 ; %bb.85: ; in Loop: Header=BB4_29 Depth=1 v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0 s_mul_i32 s14, s13, 24 s_mul_hi_u32 s15, s12, 24 v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1 s_add_i32 s15, s15, s14 s_mul_i32 s14, s12, 24 s_waitcnt vmcnt(0) v_add_co_u32 v30, vcc_lo, v16, s14 v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo global_store_b128 v[30:31], v[26:29], off offset:8 .LBB4_86: ; in Loop: Header=BB4_29 Depth=1 s_or_b32 exec_lo, exec_lo, s1 v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56 v_or_b32_e32 v21, 2, v0 s_lshl_b64 s[14:15], s[12:13], 12 v_lshlrev_b64 v[26:27], 6, v[24:25] s_lshl_b32 s1, s8, 2 s_delay_alu instid0(SALU_CYCLE_1) s_add_i32 s1, s1, 28 v_cndmask_b32_e32 v0, v21, v0, vcc_lo s_waitcnt vmcnt(0) v_add_co_u32 v18, vcc_lo, v18, s14 v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo s_and_b32 s1, s1, 0x1e0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v18, vcc_lo, v18, v26 v_and_or_b32 v0, v0, 0xffffff1f, s1 v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo s_clause 0x3 global_store_b128 v[18:19], v[0:3], off global_store_b128 v[18:19], v[4:7], off offset:16 global_store_b128 v[18:19], v[8:11], off offset:32 global_store_b128 v[18:19], v[12:15], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_94 ; %bb.87: ; in Loop: Header=BB4_29 Depth=1 s_clause 0x1 global_load_b64 v[8:9], v25, s[2:3] offset:32 glc global_load_b64 v[0:1], v25, s[2:3] offset:40 v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11 s_waitcnt vmcnt(0) v_readfirstlane_b32 s14, v0 v_readfirstlane_b32 s15, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[14:15], s[14:15], s[10:11] s_mul_i32 s15, s15, 24 s_mul_hi_u32 s16, s14, 24 s_mul_i32 s14, s14, 24 s_add_i32 s16, s16, s15 v_add_co_u32 v4, vcc_lo, v16, s14 v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo s_mov_b32 s14, exec_lo global_store_b64 v[4:5], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[8:9] s_cbranch_execz .LBB4_90 ; %bb.88: ; %.preheader1.i.i17.i.preheader ; in Loop: Header=BB4_29 Depth=1 s_mov_b32 s15, 0 .LBB4_89: ; %.preheader1.i.i17.i ; Parent Loop BB4_29 Depth=1 ; => This Inner Loop Header: Depth=2 v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s15, vcc_lo, s15 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s15 s_cbranch_execnz .LBB4_89 .LBB4_90: ; %Flow171 ; in Loop: Header=BB4_29 Depth=1 s_or_b32 exec_lo, exec_lo, s14 global_load_b64 v[0:1], v25, s[2:3] offset:16 s_mov_b32 s15, exec_lo s_mov_b32 s14, exec_lo v_mbcnt_lo_u32_b32 v2, s15, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB4_92 ; %bb.91: ; in Loop: Header=BB4_29 Depth=1 s_bcnt1_i32_b32 s15, s15 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB4_92: ; in Loop: Header=BB4_29 Depth=1 s_or_b32 exec_lo, exec_lo, s14 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB4_94 ; %bb.93: ; in Loop: Header=BB4_29 Depth=1 global_load_b32 v24, v[0:1], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s14, v24 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[24:25], off s_and_b32 m0, s14, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB4_94: ; %Flow172 ; in Loop: Header=BB4_29 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s13, 24 s_mul_hi_u32 s13, s12, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s13, s13, s1 s_mul_i32 s1, s12, 24 v_add_co_u32 v0, vcc_lo, v16, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB4_98 .p2align 6 .LBB4_95: ; in Loop: Header=BB4_98 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB4_97 ; %bb.96: ; in Loop: Header=BB4_98 Depth=2 s_sleep 1 s_cbranch_execnz .LBB4_98 s_branch .LBB4_100 .p2align 6 .LBB4_97: ; in Loop: Header=BB4_29 Depth=1 s_branch .LBB4_100 .LBB4_98: ; Parent Loop BB4_29 Depth=1 ; => This Inner Loop Header: Depth=2 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_95 ; %bb.99: ; in Loop: Header=BB4_98 Depth=2 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB4_95 .LBB4_100: ; in Loop: Header=BB4_29 Depth=1 global_load_b64 v[0:1], v[18:19], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_28 ; %bb.101: ; in Loop: Header=BB4_29 Depth=1 s_clause 0x2 global_load_b64 v[4:5], v25, s[2:3] offset:40 global_load_b64 v[8:9], v25, s[2:3] offset:24 glc global_load_b64 v[6:7], v25, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v10, vcc_lo, v4, 1 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, v10, s10 v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10 v_and_b32_e32 v5, v3, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v4, v2, v4 v_mul_hi_u32 v10, v4, 24 v_mul_lo_u32 v4, v4, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v6, vcc_lo, v6, v4 v_mov_b32_e32 v4, v8 v_mul_lo_u32 v5, v5, 24 v_add_nc_u32_e32 v5, v10, v5 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v5, v9 global_store_b64 v[6:7], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB4_28 ; %bb.102: ; %.preheader.i.i16.i.preheader ; in Loop: Header=BB4_29 Depth=1 s_mov_b32 s0, 0 .LBB4_103: ; %.preheader.i.i16.i ; Parent Loop BB4_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5] v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB4_103 s_branch .LBB4_28 .LBB4_104: ; %Flow211 s_mov_b32 s0, 0 .LBB4_105: ; %Flow227 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s0 s_cbranch_vccz .LBB4_133 ; %bb.106: ;;#ASMSTART ;;#ASMEND v_readfirstlane_b32 s0, v20 v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s0, s0, v20 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_112 ; %bb.107: s_waitcnt vmcnt(0) v_mov_b32_e32 v0, 0 s_mov_b32 s4, exec_lo global_load_b64 v[6:7], v0, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[3:4], v0, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v6 v_and_b32_e32 v2, v2, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v5, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v5, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v3, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo global_load_b64 v[4:5], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[4:5], v[6:7] s_cbranch_execz .LBB4_111 ; %bb.108: ; %.preheader3.i.i.i6.preheader s_mov_b32 s5, 0 .p2align 6 .LBB4_109: ; %.preheader3.i.i.i6 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[8:9], v0, s[2:3] v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v1, v1, v6 s_waitcnt vmcnt(0) v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7 v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2] global_load_b64 v[4:5], v[3:4], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB4_109 ; %bb.110: ; %Flow224 s_or_b32 exec_lo, exec_lo, s5 .LBB4_111: ; %Flow226 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB4_112: ; %.loopexit4.i.i.i1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v21, 0 v_readfirstlane_b32 s4, v4 v_readfirstlane_b32 s5, v5 s_mov_b32 s8, exec_lo s_clause 0x1 global_load_b64 v[6:7], v21, s[2:3] offset:40 global_load_b128 v[0:3], v21, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v6 v_readfirstlane_b32 s7, v7 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_114 ; %bb.113: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v8, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo global_store_b128 v[8:9], v[4:7], off offset:8 .LBB4_114: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 v_and_or_b32 v22, v22, 0xffffff1d, 34 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v2, s8 v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo v_lshlrev_b64 v[2:3], 6, v[20:21] s_mov_b32 s8, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_add_co_u32 v8, vcc_lo, v4, v2 v_mov_b32_e32 v6, 0 v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11 v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10 s_delay_alu instid0(VALU_DEP_4) v_mov_b32_e32 v7, v6 s_clause 0x4 global_store_b64 v[8:9], v[22:23], off global_store_b128 v[8:9], v[2:5], off offset:8 global_store_b128 v[8:9], v[2:5], off offset:24 global_store_b128 v[8:9], v[2:5], off offset:40 global_store_b64 v[8:9], v[6:7], off offset:56 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_122 ; %bb.115: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4 v_mov_b32_e32 v10, s5 s_clause 0x1 global_load_b64 v[11:12], v8, s[2:3] offset:32 glc global_load_b64 v[2:3], v8, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 v_readfirstlane_b32 s9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v6, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[6:7], v[11:12], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[11:12] s_cbranch_execz .LBB4_118 ; %bb.116: ; %.preheader1.i.i.i4.preheader s_mov_b32 s9, 0 .LBB4_117: ; %.preheader1.i.i.i4 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB4_117 .LBB4_118: ; %Flow222 s_or_b32 exec_lo, exec_lo, s8 v_mov_b32_e32 v2, 0 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v4, s9, 0 global_load_b64 v[2:3], v2, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB4_120 ; %bb.119: s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB4_120: s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB4_122 ; %bb.121: global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB4_122: ; %Flow223 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB4_126 .p2align 6 .LBB4_123: ; in Loop: Header=BB4_126 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB4_125 ; %bb.124: ; in Loop: Header=BB4_126 Depth=1 s_sleep 1 s_cbranch_execnz .LBB4_126 s_branch .LBB4_128 .p2align 6 .LBB4_125: s_branch .LBB4_128 .LBB4_126: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_123 ; %bb.127: ; in Loop: Header=BB4_126 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB4_123 .LBB4_128: s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_132 ; %bb.129: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[2:3] offset:40 global_load_b64 v[7:8], v6, s[2:3] offset:24 glc global_load_b64 v[4:5], v6, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s4 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB4_132 ; %bb.130: ; %.preheader.i.i.i3.preheader s_mov_b32 s0, 0 .LBB4_131: ; %.preheader.i.i.i3 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB4_131 .LBB4_132: ; %Flow215 s_or_b32 exec_lo, exec_lo, s1 .LBB4_133: ; %__ockl_printf_append_string_n.exit s_waitcnt vmcnt(0) v_dual_mov_b32 v0, 0x99999999 :: v_dual_mov_b32 v1, 0x99999999 s_waitcnt lgkmcnt(0) s_setpc_b64 s[30:31] .Lfunc_end4: .size _Z6secretv, .Lfunc_end4-_Z6secretv ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 5264 ; NumSgprs: 34 ; NumVgprs: 32 ; ScratchSize: 0 ; MemoryBound: 0 .section .text.unlikely.,"ax",@progbits .p2align 2 ; -- Begin function __ockl_dm_alloc .type __ockl_dm_alloc,@function __ockl_dm_alloc: ; @__ockl_dm_alloc ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) s_or_saveexec_b32 s0, -1 scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill s_mov_b32 exec_lo, s0 v_writelane_b32 v40, s34, 0 v_writelane_b32 v40, s35, 1 v_writelane_b32 v40, s36, 2 v_writelane_b32 v40, s37, 3 v_writelane_b32 v40, s38, 4 v_writelane_b32 v40, s39, 5 v_writelane_b32 v40, s40, 6 v_writelane_b32 v40, s30, 7 v_writelane_b32 v40, s31, 8 v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 v_mov_b32_e32 v0, 0 v_mov_b32_e32 v1, 0 s_mov_b32 s24, exec_lo s_delay_alu instid0(VALU_DEP_3) v_cmpx_ne_u64_e32 0, v[2:3] s_cbranch_execz .LBB5_700 ; %bb.1: ; implicit-def: $vgpr0_vgpr1 s_mov_b32 s0, exec_lo v_cmpx_gt_u64_e32 0xc01, v[2:3] s_xor_b32 s25, exec_lo, s0 s_cbranch_execz .LBB5_666 ; %bb.2: v_max_u32_e32 v0, 16, v2 s_load_b64 s[10:11], s[8:9], 0x60 v_dual_mov_b32 v98, 1 :: v_dual_mov_b32 v39, 0x100 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_clz_i32_u32_e32 v1, v0 v_mov_b32_e32 v16, 0 v_not_b32_e32 v2, v1 v_lshlrev_b32_e32 v1, 1, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v3, v16 :: v_dual_and_b32 v2, 15, v2 v_lshlrev_b32_e64 v2, v2, 1 s_waitcnt lgkmcnt(0) s_add_u32 s12, s10, 0x1a800 s_addc_u32 s13, s11, 0 s_add_u32 s14, s10, 0x1a808 s_addc_u32 s15, s11, 0 v_lshrrev_b32_e32 v4, 1, v2 v_cmp_gt_u32_e32 vcc_lo, v0, v2 s_add_u32 s4, s10, 0x800 s_addc_u32 s5, s11, 0 s_getpc_b64 s[0:1] s_add_u32 s0, s0, __unnamed_1@rel32@lo+12 s_addc_u32 s1, s1, __unnamed_1@rel32@hi+20 v_or_b32_e32 v2, v4, v2 v_cndmask_b32_e64 v5, 0, 1, vcc_lo s_getpc_b64 s[2:3] s_add_u32 s2, s2, __unnamed_1@rel32@lo+4 s_addc_u32 s3, s3, __unnamed_1@rel32@hi+12 s_add_u32 s6, s10, 0x1000 s_addc_u32 s7, s11, 0 v_cmp_gt_u32_e32 vcc_lo, v0, v2 v_sub_nc_u32_e32 v1, v5, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v2, vcc_lo, 54, v1, vcc_lo v_lshlrev_b64 v[0:1], 7, v[2:3] v_lshlrev_b64 v[4:5], 5, v[2:3] v_lshrrev_b64 v[6:7], v2, 0xbf v_mov_b32_e32 v3, 0 s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v17, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v18, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v19, vcc_lo, s10, v0 v_add_co_ci_u32_e32 v20, vcc_lo, s11, v1, vcc_lo v_add_co_u32 v21, vcc_lo, v4, s0 v_add_co_ci_u32_e32 v22, vcc_lo, s1, v5, vcc_lo v_add_co_u32 v23, vcc_lo, v4, s2 v_add_co_ci_u32_e32 v24, vcc_lo, s3, v5, vcc_lo v_add_co_u32 v25, vcc_lo, s6, v0 s_add_u32 s0, s10, 0x2000 v_add_co_ci_u32_e32 v26, vcc_lo, s7, v1, vcc_lo s_addc_u32 s1, s11, 0 v_add_co_u32 v27, vcc_lo, s0, v0 s_add_u32 s2, s10, 0x1800 v_add_co_ci_u32_e32 v28, vcc_lo, s1, v1, vcc_lo s_addc_u32 s3, s11, 0 v_add_co_u32 v29, vcc_lo, s2, v0 s_getpc_b64 s[0:1] s_add_u32 s0, s0, __unnamed_1@rel32@lo+24 s_addc_u32 s1, s1, __unnamed_1@rel32@hi+32 v_add_co_ci_u32_e32 v30, vcc_lo, s3, v1, vcc_lo v_add_co_u32 v31, vcc_lo, v4, s0 v_and_b32_e32 v0, 1, v6 s_getpc_b64 s[2:3] s_add_u32 s2, s2, __unnamed_1@rel32@lo+20 s_addc_u32 s3, s3, __unnamed_1@rel32@hi+28 v_add_co_ci_u32_e32 v32, vcc_lo, s1, v5, vcc_lo v_add_co_u32 v33, vcc_lo, v4, s2 s_getpc_b64 s[4:5] s_add_u32 s4, s4, __unnamed_1@rel32@lo+28 s_addc_u32 s5, s5, __unnamed_1@rel32@hi+36 v_add_co_ci_u32_e32 v34, vcc_lo, s3, v5, vcc_lo v_add_co_u32 v35, vcc_lo, v4, s4 v_cmp_eq_u32_e64 s0, 1, v0 v_mov_b32_e32 v0, 0 v_add_co_ci_u32_e32 v36, vcc_lo, s5, v5, vcc_lo v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v1, 0 v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v6, 1 s_mov_b32 s4, 0 .LBB5_3: ; =>This Loop Header: Depth=1 ; Child Loop BB5_6 Depth 2 ; Child Loop BB5_11 Depth 3 ; Child Loop BB5_14 Depth 4 ; Child Loop BB5_43 Depth 4 ; Child Loop BB5_47 Depth 5 ; Child Loop BB5_74 Depth 5 ; Child Loop BB5_92 Depth 6 ; Child Loop BB5_100 Depth 6 ; Child Loop BB5_106 Depth 6 ; Child Loop BB5_115 Depth 6 ; Child Loop BB5_120 Depth 6 ; Child Loop BB5_122 Depth 6 ; Child Loop BB5_142 Depth 6 ; Child Loop BB5_150 Depth 6 ; Child Loop BB5_156 Depth 6 ; Child Loop BB5_165 Depth 6 ; Child Loop BB5_173 Depth 6 ; Child Loop BB5_176 Depth 6 ; Child Loop BB5_178 Depth 6 ; Child Loop BB5_180 Depth 6 ; Child Loop BB5_182 Depth 6 ; Child Loop BB5_184 Depth 6 ; Child Loop BB5_186 Depth 6 ; Child Loop BB5_208 Depth 6 ; Child Loop BB5_216 Depth 6 ; Child Loop BB5_222 Depth 6 ; Child Loop BB5_231 Depth 6 ; Child Loop BB5_238 Depth 6 ; Child Loop BB5_241 Depth 6 ; Child Loop BB5_246 Depth 6 ; Child Loop BB5_253 Depth 6 ; Child Loop BB5_286 Depth 6 ; Child Loop BB5_294 Depth 6 ; Child Loop BB5_300 Depth 6 ; Child Loop BB5_309 Depth 6 ; Child Loop BB5_318 Depth 5 ; Child Loop BB5_321 Depth 5 ; Child Loop BB5_323 Depth 5 ; Child Loop BB5_325 Depth 5 ; Child Loop BB5_327 Depth 5 ; Child Loop BB5_329 Depth 5 ; Child Loop BB5_331 Depth 5 ; Child Loop BB5_345 Depth 3 ; Child Loop BB5_349 Depth 4 ; Child Loop BB5_377 Depth 4 ; Child Loop BB5_395 Depth 5 ; Child Loop BB5_403 Depth 5 ; Child Loop BB5_409 Depth 5 ; Child Loop BB5_418 Depth 5 ; Child Loop BB5_423 Depth 5 ; Child Loop BB5_425 Depth 5 ; Child Loop BB5_445 Depth 5 ; Child Loop BB5_453 Depth 5 ; Child Loop BB5_459 Depth 5 ; Child Loop BB5_468 Depth 5 ; Child Loop BB5_476 Depth 5 ; Child Loop BB5_479 Depth 5 ; Child Loop BB5_481 Depth 5 ; Child Loop BB5_483 Depth 5 ; Child Loop BB5_485 Depth 5 ; Child Loop BB5_487 Depth 5 ; Child Loop BB5_489 Depth 5 ; Child Loop BB5_511 Depth 5 ; Child Loop BB5_519 Depth 5 ; Child Loop BB5_525 Depth 5 ; Child Loop BB5_534 Depth 5 ; Child Loop BB5_541 Depth 5 ; Child Loop BB5_544 Depth 5 ; Child Loop BB5_549 Depth 5 ; Child Loop BB5_556 Depth 5 ; Child Loop BB5_589 Depth 5 ; Child Loop BB5_597 Depth 5 ; Child Loop BB5_603 Depth 5 ; Child Loop BB5_612 Depth 5 ; Child Loop BB5_621 Depth 4 ; Child Loop BB5_624 Depth 4 ; Child Loop BB5_626 Depth 4 ; Child Loop BB5_628 Depth 4 ; Child Loop BB5_630 Depth 4 ; Child Loop BB5_632 Depth 4 ; Child Loop BB5_634 Depth 4 ; Child Loop BB5_647 Depth 3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_dual_mov_b32 v99, v6 :: v_dual_mov_b32 v6, 0 s_mov_b32 s26, exec_lo ;;#ASMSTART ;;#ASMEND v_cmpx_ne_u32_e32 0, v99 s_cbranch_execz .LBB5_664 ; %bb.4: ; in Loop: Header=BB5_3 Depth=1 v_readfirstlane_b32 s1, v2 s_mov_b32 s27, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e64 s1, v2 s_cbranch_execz .LBB5_663 ; %bb.5: ; %.preheader196.preheader ; in Loop: Header=BB5_3 Depth=1 v_mov_b32_e32 v6, 1 .LBB5_6: ; %.preheader196 ; Parent Loop BB5_3 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB5_11 Depth 3 ; Child Loop BB5_14 Depth 4 ; Child Loop BB5_43 Depth 4 ; Child Loop BB5_47 Depth 5 ; Child Loop BB5_74 Depth 5 ; Child Loop BB5_92 Depth 6 ; Child Loop BB5_100 Depth 6 ; Child Loop BB5_106 Depth 6 ; Child Loop BB5_115 Depth 6 ; Child Loop BB5_120 Depth 6 ; Child Loop BB5_122 Depth 6 ; Child Loop BB5_142 Depth 6 ; Child Loop BB5_150 Depth 6 ; Child Loop BB5_156 Depth 6 ; Child Loop BB5_165 Depth 6 ; Child Loop BB5_173 Depth 6 ; Child Loop BB5_176 Depth 6 ; Child Loop BB5_178 Depth 6 ; Child Loop BB5_180 Depth 6 ; Child Loop BB5_182 Depth 6 ; Child Loop BB5_184 Depth 6 ; Child Loop BB5_186 Depth 6 ; Child Loop BB5_208 Depth 6 ; Child Loop BB5_216 Depth 6 ; Child Loop BB5_222 Depth 6 ; Child Loop BB5_231 Depth 6 ; Child Loop BB5_238 Depth 6 ; Child Loop BB5_241 Depth 6 ; Child Loop BB5_246 Depth 6 ; Child Loop BB5_253 Depth 6 ; Child Loop BB5_286 Depth 6 ; Child Loop BB5_294 Depth 6 ; Child Loop BB5_300 Depth 6 ; Child Loop BB5_309 Depth 6 ; Child Loop BB5_318 Depth 5 ; Child Loop BB5_321 Depth 5 ; Child Loop BB5_323 Depth 5 ; Child Loop BB5_325 Depth 5 ; Child Loop BB5_327 Depth 5 ; Child Loop BB5_329 Depth 5 ; Child Loop BB5_331 Depth 5 ; Child Loop BB5_345 Depth 3 ; Child Loop BB5_349 Depth 4 ; Child Loop BB5_377 Depth 4 ; Child Loop BB5_395 Depth 5 ; Child Loop BB5_403 Depth 5 ; Child Loop BB5_409 Depth 5 ; Child Loop BB5_418 Depth 5 ; Child Loop BB5_423 Depth 5 ; Child Loop BB5_425 Depth 5 ; Child Loop BB5_445 Depth 5 ; Child Loop BB5_453 Depth 5 ; Child Loop BB5_459 Depth 5 ; Child Loop BB5_468 Depth 5 ; Child Loop BB5_476 Depth 5 ; Child Loop BB5_479 Depth 5 ; Child Loop BB5_481 Depth 5 ; Child Loop BB5_483 Depth 5 ; Child Loop BB5_485 Depth 5 ; Child Loop BB5_487 Depth 5 ; Child Loop BB5_489 Depth 5 ; Child Loop BB5_511 Depth 5 ; Child Loop BB5_519 Depth 5 ; Child Loop BB5_525 Depth 5 ; Child Loop BB5_534 Depth 5 ; Child Loop BB5_541 Depth 5 ; Child Loop BB5_544 Depth 5 ; Child Loop BB5_549 Depth 5 ; Child Loop BB5_556 Depth 5 ; Child Loop BB5_589 Depth 5 ; Child Loop BB5_597 Depth 5 ; Child Loop BB5_603 Depth 5 ; Child Loop BB5_612 Depth 5 ; Child Loop BB5_621 Depth 4 ; Child Loop BB5_624 Depth 4 ; Child Loop BB5_626 Depth 4 ; Child Loop BB5_628 Depth 4 ; Child Loop BB5_630 Depth 4 ; Child Loop BB5_632 Depth 4 ; Child Loop BB5_634 Depth 4 ; Child Loop BB5_647 Depth 3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_mov_b32_e32 v100, v6 v_mov_b32_e32 v6, 0 s_mov_b32 s28, exec_lo ;;#ASMSTART ;;#ASMEND v_cmpx_ne_u32_e32 0, v100 s_cbranch_execz .LBB5_662 ; %bb.7: ; in Loop: Header=BB5_6 Depth=2 v_mbcnt_lo_u32_b32 v6, exec_lo, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v6 v_mov_b32_e32 v6, 0 s_and_saveexec_b32 s1, vcc_lo s_cbranch_execz .LBB5_9 ; %bb.8: ; in Loop: Header=BB5_6 Depth=2 global_load_b32 v6, v[17:18], off glc .LBB5_9: ; in Loop: Header=BB5_6 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_waitcnt vmcnt(0) v_readfirstlane_b32 s29, v6 s_delay_alu instid0(VALU_DEP_1) s_cmp_gt_u32 s29, 0x100ff s_cbranch_scc0 .LBB5_342 ; %bb.10: ; in Loop: Header=BB5_6 Depth=2 v_mbcnt_lo_u32_b32 v101, exec_lo, 0 v_mov_b32_e32 v15, v2 s_mov_b32 s30, 0 s_bcnt1_i32_b32 s31, exec_lo ; implicit-def: $vgpr7_vgpr8 .LBB5_11: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; => This Loop Header: Depth=3 ; Child Loop BB5_14 Depth 4 ; Child Loop BB5_43 Depth 4 ; Child Loop BB5_47 Depth 5 ; Child Loop BB5_74 Depth 5 ; Child Loop BB5_92 Depth 6 ; Child Loop BB5_100 Depth 6 ; Child Loop BB5_106 Depth 6 ; Child Loop BB5_115 Depth 6 ; Child Loop BB5_120 Depth 6 ; Child Loop BB5_122 Depth 6 ; Child Loop BB5_142 Depth 6 ; Child Loop BB5_150 Depth 6 ; Child Loop BB5_156 Depth 6 ; Child Loop BB5_165 Depth 6 ; Child Loop BB5_173 Depth 6 ; Child Loop BB5_176 Depth 6 ; Child Loop BB5_178 Depth 6 ; Child Loop BB5_180 Depth 6 ; Child Loop BB5_182 Depth 6 ; Child Loop BB5_184 Depth 6 ; Child Loop BB5_186 Depth 6 ; Child Loop BB5_208 Depth 6 ; Child Loop BB5_216 Depth 6 ; Child Loop BB5_222 Depth 6 ; Child Loop BB5_231 Depth 6 ; Child Loop BB5_238 Depth 6 ; Child Loop BB5_241 Depth 6 ; Child Loop BB5_246 Depth 6 ; Child Loop BB5_253 Depth 6 ; Child Loop BB5_286 Depth 6 ; Child Loop BB5_294 Depth 6 ; Child Loop BB5_300 Depth 6 ; Child Loop BB5_309 Depth 6 ; Child Loop BB5_318 Depth 5 ; Child Loop BB5_321 Depth 5 ; Child Loop BB5_323 Depth 5 ; Child Loop BB5_325 Depth 5 ; Child Loop BB5_327 Depth 5 ; Child Loop BB5_329 Depth 5 ; Child Loop BB5_331 Depth 5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_lshlrev_b64 v[9:10], 7, v[15:16] ;;#ASMSTART ;;#ASMEND v_cmp_eq_u32_e64 s1, 0, v101 v_mov_b32_e32 v11, 0 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB5_13 ; %bb.12: ; in Loop: Header=BB5_11 Depth=3 v_add_co_u32 v11, vcc_lo, s10, v9 v_add_co_ci_u32_e32 v12, vcc_lo, s11, v10, vcc_lo global_load_b32 v11, v[11:12], off glc .LBB5_13: ; in Loop: Header=BB5_11 Depth=3 s_or_b32 exec_lo, exec_lo, s2 v_lshlrev_b64 v[12:13], 5, v[15:16] s_getpc_b64 s[2:3] s_add_u32 s2, s2, __unnamed_1@rel32@lo+8 s_addc_u32 s3, s3, __unnamed_1@rel32@hi+16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v12, vcc_lo, v12, s2 v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo s_waitcnt vmcnt(0) v_readfirstlane_b32 s2, v11 global_load_b32 v6, v[12:13], off v_add_nc_u32_e32 v11, s2, v101 s_mov_b32 s2, 0x10100 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v12, v11, 0xff00ff01 v_lshrrev_b32_e32 v12, 16, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_u32_u24_e32 v12, 0x10100, v12 v_sub_nc_u32_e32 v14, v11, v12 v_add_co_u32 v12, vcc_lo, s10, v9 v_add_co_ci_u32_e32 v13, vcc_lo, s11, v10, vcc_lo .LBB5_14: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; => This Inner Loop Header: Depth=4 s_mov_b32 s3, exec_lo ; implicit-def: $vgpr9_vgpr10 s_delay_alu instid0(VALU_DEP_3) v_cmpx_gt_u32_e32 0x100, v14 s_xor_b32 s3, exec_lo, s3 ; %bb.15: ; in Loop: Header=BB5_14 Depth=4 s_add_u32 s6, s10, 0x2800 s_addc_u32 s7, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[37:38], null, v15, 0x1800, s[6:7] v_mad_u64_u32 v[9:10], null, v14, 24, v[37:38] ; %bb.16: ; %Flow982 ; in Loop: Header=BB5_14 Depth=4 s_and_not1_saveexec_b32 s3, s3 s_cbranch_execz .LBB5_18 ; %bb.17: ; in Loop: Header=BB5_14 Depth=4 s_add_u32 s6, s10, 0x2800 v_add_nc_u32_e32 v11, 0xffffff00, v14 s_addc_u32 s7, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[9:10], null, v15, 0x1800, s[6:7] v_lshrrev_b32_e32 v11, 8, v11 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[37:38], null, v11, 24, v[9:10] v_and_b32_e32 v11, 0xff, v14 global_load_b64 v[37:38], v[37:38], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[9:10], null, v11, 24, v[37:38] .LBB5_18: ; in Loop: Header=BB5_14 Depth=4 s_or_b32 exec_lo, exec_lo, s3 global_load_b32 v9, v[9:10], off offset:16 glc s_waitcnt vmcnt(0) v_cmp_lt_u32_e32 vcc_lo, v9, v6 s_cbranch_vccz .LBB5_20 ; %bb.19: ; in Loop: Header=BB5_14 Depth=4 s_ctz_i32_b32 s3, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b32 s3, s3, 2 v_mov_b32_e32 v9, s3 ds_bpermute_b32 v9, v9, v14 s_branch .LBB5_21 .LBB5_20: ; in Loop: Header=BB5_14 Depth=4 v_mov_b32_e32 v9, -1 .LBB5_21: ; in Loop: Header=BB5_14 Depth=4 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v9 s_cmp_eq_u32 s5, -1 s_cselect_b32 s3, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s3 s_cbranch_vccnz .LBB5_24 ; %bb.22: ; in Loop: Header=BB5_14 Depth=4 s_cmpk_lt_u32 s5, 0x100 s_cbranch_scc0 .LBB5_25 ; %bb.23: ; in Loop: Header=BB5_14 Depth=4 s_add_u32 s6, s10, 0x2800 s_addc_u32 s7, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[37:38], null, v15, 0x1800, s[6:7] s_mov_b32 s6, 0 v_mad_u64_u32 v[10:11], null, s5, 24, v[37:38] s_branch .LBB5_26 .LBB5_24: ; in Loop: Header=BB5_14 Depth=4 s_mov_b32 s5, -1 ; implicit-def: $vgpr10_vgpr11 s_branch .LBB5_29 .LBB5_25: ; in Loop: Header=BB5_14 Depth=4 s_mov_b32 s6, -1 ; implicit-def: $vgpr10_vgpr11 .LBB5_26: ; %Flow975 ; in Loop: Header=BB5_14 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_28 ; %bb.27: ; in Loop: Header=BB5_14 Depth=4 s_add_i32 s6, s5, 0xffffff00 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) s_lshr_b32 s16, s6, 8 s_add_u32 s6, s10, 0x2800 s_addc_u32 s7, s11, 0 s_and_b32 s5, s5, 0xff v_mad_u64_u32 v[9:10], null, v15, 0x1800, s[6:7] v_mad_u64_u32 v[37:38], null, s16, 24, v[9:10] global_load_b64 v[37:38], v[37:38], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[10:11], null, s5, 24, v[37:38] .LBB5_28: ; %Flow976 ; in Loop: Header=BB5_14 Depth=4 s_mov_b32 s5, 0 .LBB5_29: ; %Flow978 ; in Loop: Header=BB5_14 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB5_33 ; %bb.30: ; in Loop: Header=BB5_14 Depth=4 v_add_nc_u32_e32 v9, s31, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v10, v9, 0xff00ff01 v_lshrrev_b32_e32 v10, 16, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_u32_u24_e32 v10, 0x10100, v10 v_sub_nc_u32_e32 v14, v9, v10 s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB5_32 ; %bb.31: ; in Loop: Header=BB5_14 Depth=4 global_store_b32 v[12:13], v14, off .LBB5_32: ; in Loop: Header=BB5_14 Depth=4 s_or_b32 exec_lo, exec_lo, s5 v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v10, v7 s_sub_i32 s2, s2, s31 .LBB5_33: ; in Loop: Header=BB5_14 Depth=4 s_and_not1_b32 vcc_lo, exec_lo, s3 s_cbranch_vccz .LBB5_35 ; %bb.34: ; in Loop: Header=BB5_14 Depth=4 s_mov_b32 s3, 0 s_mov_b32 s5, -1 s_mov_b32 s6, -1 ; implicit-def: $sgpr2 ; implicit-def: $vgpr14 s_branch .LBB5_36 .LBB5_35: ; in Loop: Header=BB5_14 Depth=4 s_cmp_lt_i32 s2, 1 s_mov_b32 s5, 0 s_cselect_b32 s6, -1, 0 ; implicit-def: $sgpr3 .LBB5_36: ; %Flow984 ; in Loop: Header=BB5_14 Depth=4 v_dual_mov_b32 v7, v10 :: v_dual_mov_b32 v8, v11 s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_14 ; %bb.37: ; %loop.exit.guard ; in Loop: Header=BB5_11 Depth=3 v_dual_mov_b32 v7, v10 :: v_dual_mov_b32 v8, v11 s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccz .LBB5_340 ; %bb.38: ; in Loop: Header=BB5_11 Depth=3 v_dual_mov_b32 v7, 0 :: v_dual_and_b32 v6, -2, v15 v_cmp_eq_u32_e32 vcc_lo, v15, v2 v_mov_b32_e32 v8, 0 s_mov_b32 s3, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u32_e64 s2, 14, v6 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s34, s2 s_cbranch_execz .LBB5_339 ; %bb.39: ; in Loop: Header=BB5_11 Depth=3 v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v6, 2, v6 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB5_41 ; %bb.40: ; in Loop: Header=BB5_11 Depth=3 v_mov_b32_e32 v7, v16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 7, v[6:7] v_add_co_u32 v7, vcc_lo, s10, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo global_load_b32 v7, v[7:8], off offset:2048 glc .LBB5_41: ; in Loop: Header=BB5_11 Depth=3 s_or_b32 exec_lo, exec_lo, s2 s_waitcnt vmcnt(0) v_readfirstlane_b32 s36, v7 s_mov_b32 s6, -1 s_delay_alu instid0(VALU_DEP_1) s_cmp_gt_u32 s36, 0x100ff s_cbranch_scc1 .LBB5_338 ; %bb.42: ; in Loop: Header=BB5_11 Depth=3 v_mov_b32_e32 v7, v16 s_bcnt1_i32_b32 s35, exec_lo s_getpc_b64 s[2:3] s_add_u32 s2, s2, __unnamed_1@rel32@lo+12 s_addc_u32 s3, s3, __unnamed_1@rel32@hi+20 s_getpc_b64 s[6:7] s_add_u32 s6, s6, __unnamed_1@rel32@lo+4 s_addc_u32 s7, s7, __unnamed_1@rel32@hi+12 s_add_u32 s1, s10, 0x800 v_lshlrev_b64 v[8:9], 7, v[6:7] v_lshlrev_b64 v[10:11], 5, v[6:7] v_lshrrev_b64 v[12:13], v6, 0xbf v_mbcnt_lo_u32_b32 v102, exec_lo, 0 ; implicit-def: $vgpr82_vgpr83 s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v37, vcc_lo, s10, v8 v_add_co_ci_u32_e32 v38, vcc_lo, s11, v9, vcc_lo v_add_co_u32 v48, vcc_lo, v10, s2 v_add_co_ci_u32_e32 v49, vcc_lo, s3, v11, vcc_lo v_add_co_u32 v50, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v51, vcc_lo, s7, v11, vcc_lo s_addc_u32 s2, s11, 0 v_add_co_u32 v52, vcc_lo, s1, v8 s_add_u32 s1, s10, 0x1000 v_add_co_ci_u32_e32 v53, vcc_lo, s2, v9, vcc_lo s_addc_u32 s2, s11, 0 v_add_co_u32 v54, vcc_lo, s1, v8 s_add_u32 s1, s10, 0x2000 v_add_co_ci_u32_e32 v55, vcc_lo, s2, v9, vcc_lo s_addc_u32 s2, s11, 0 v_add_co_u32 v64, vcc_lo, s1, v8 s_add_u32 s1, s10, 0x1800 v_add_co_ci_u32_e32 v65, vcc_lo, s2, v9, vcc_lo s_addc_u32 s5, s11, 0 v_add_co_u32 v66, vcc_lo, s1, v8 v_and_b32_e32 v7, 1, v12 s_getpc_b64 s[2:3] s_add_u32 s2, s2, __unnamed_1@rel32@lo+24 s_addc_u32 s3, s3, __unnamed_1@rel32@hi+32 v_add_co_ci_u32_e32 v67, vcc_lo, s5, v9, vcc_lo v_add_co_u32 v68, vcc_lo, v10, s2 s_getpc_b64 s[6:7] s_add_u32 s6, s6, __unnamed_1@rel32@lo+20 s_addc_u32 s7, s7, __unnamed_1@rel32@hi+28 v_add_co_ci_u32_e32 v69, vcc_lo, s3, v11, vcc_lo v_cmp_eq_u32_e64 s1, 1, v7 v_add_co_u32 v70, vcc_lo, v10, s6 v_mov_b32_e32 v7, 0 s_getpc_b64 s[2:3] s_add_u32 s2, s2, __unnamed_1@rel32@lo+28 s_addc_u32 s3, s3, __unnamed_1@rel32@hi+36 v_add_co_ci_u32_e32 v71, vcc_lo, s7, v11, vcc_lo v_add_co_u32 v80, vcc_lo, v10, s2 v_add_co_ci_u32_e32 v81, vcc_lo, s3, v11, vcc_lo v_mov_b32_e32 v8, v7 v_mov_b32_e32 v9, v7 .LBB5_43: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; => This Loop Header: Depth=4 ; Child Loop BB5_47 Depth 5 ; Child Loop BB5_74 Depth 5 ; Child Loop BB5_92 Depth 6 ; Child Loop BB5_100 Depth 6 ; Child Loop BB5_106 Depth 6 ; Child Loop BB5_115 Depth 6 ; Child Loop BB5_120 Depth 6 ; Child Loop BB5_122 Depth 6 ; Child Loop BB5_142 Depth 6 ; Child Loop BB5_150 Depth 6 ; Child Loop BB5_156 Depth 6 ; Child Loop BB5_165 Depth 6 ; Child Loop BB5_173 Depth 6 ; Child Loop BB5_176 Depth 6 ; Child Loop BB5_178 Depth 6 ; Child Loop BB5_180 Depth 6 ; Child Loop BB5_182 Depth 6 ; Child Loop BB5_184 Depth 6 ; Child Loop BB5_186 Depth 6 ; Child Loop BB5_208 Depth 6 ; Child Loop BB5_216 Depth 6 ; Child Loop BB5_222 Depth 6 ; Child Loop BB5_231 Depth 6 ; Child Loop BB5_238 Depth 6 ; Child Loop BB5_241 Depth 6 ; Child Loop BB5_246 Depth 6 ; Child Loop BB5_253 Depth 6 ; Child Loop BB5_286 Depth 6 ; Child Loop BB5_294 Depth 6 ; Child Loop BB5_300 Depth 6 ; Child Loop BB5_309 Depth 6 ; Child Loop BB5_318 Depth 5 ; Child Loop BB5_321 Depth 5 ; Child Loop BB5_323 Depth 5 ; Child Loop BB5_325 Depth 5 ; Child Loop BB5_327 Depth 5 ; Child Loop BB5_329 Depth 5 ; Child Loop BB5_331 Depth 5 s_cmp_eq_u32 s36, 0 s_mov_b32 s5, -1 ;;#ASMSTART ;;#ASMEND s_cbranch_scc1 .LBB5_71 ; %bb.44: ; in Loop: Header=BB5_43 Depth=4 v_cmp_eq_u32_e64 s2, 0, v102 v_mov_b32_e32 v10, 0 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB5_46 ; %bb.45: ; in Loop: Header=BB5_43 Depth=4 global_load_b32 v10, v[37:38], off glc .LBB5_46: ; in Loop: Header=BB5_43 Depth=4 s_or_b32 exec_lo, exec_lo, s3 global_load_b32 v12, v[48:49], off v_cvt_f32_u32_e32 v11, s36 s_sub_i32 s3, 0, s36 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v11, v11 s_waitcnt_depctr 0xfff v_mul_f32_e32 v11, 0x4f7ffffe, v11 v_cvt_u32_f32_e32 v11, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mul_lo_u32 v13, s3, v11 s_waitcnt vmcnt(1) v_readfirstlane_b32 s3, v10 v_add_nc_u32_e32 v10, s3, v102 s_mov_b32 s3, s36 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v13, v11, v13 v_add_nc_u32_e32 v13, v11, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v11, v10, v13 v_mul_lo_u32 v11, v11, s36 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v10, v10, v11 v_subrev_nc_u32_e32 v11, s36, v10 v_cmp_le_u32_e32 vcc_lo, s36, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v10, v10, v11, vcc_lo v_subrev_nc_u32_e32 v11, s36, v10 v_cmp_le_u32_e32 vcc_lo, s36, v10 s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e32 v14, v10, v11, vcc_lo .LBB5_47: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_mov_b32 s6, exec_lo ; implicit-def: $vgpr10_vgpr11 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_u32_e32 0x100, v14 s_xor_b32 s6, exec_lo, s6 ; %bb.48: ; in Loop: Header=BB5_47 Depth=5 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[84:85], null, v6, 0x1800, s[16:17] v_mad_u64_u32 v[10:11], null, v14, 24, v[84:85] ; %bb.49: ; %Flow799 ; in Loop: Header=BB5_47 Depth=5 s_and_not1_saveexec_b32 s6, s6 s_cbranch_execz .LBB5_51 ; %bb.50: ; in Loop: Header=BB5_47 Depth=5 s_add_u32 s16, s10, 0x2800 v_add_nc_u32_e32 v15, 0xffffff00, v14 s_addc_u32 s17, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[10:11], null, v6, 0x1800, s[16:17] v_lshrrev_b32_e32 v15, 8, v15 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[84:85], null, v15, 24, v[10:11] v_and_b32_e32 v15, 0xff, v14 global_load_b64 v[84:85], v[84:85], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[10:11], null, v15, 24, v[84:85] .LBB5_51: ; in Loop: Header=BB5_47 Depth=5 s_or_b32 exec_lo, exec_lo, s6 global_load_b32 v10, v[10:11], off offset:16 glc s_waitcnt vmcnt(0) v_cmp_lt_u32_e32 vcc_lo, v10, v12 s_cbranch_vccz .LBB5_53 ; %bb.52: ; in Loop: Header=BB5_47 Depth=5 s_ctz_i32_b32 s6, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b32 s6, s6, 2 v_mov_b32_e32 v10, s6 ds_bpermute_b32 v10, v10, v14 s_branch .LBB5_54 .LBB5_53: ; in Loop: Header=BB5_47 Depth=5 v_mov_b32_e32 v10, -1 .LBB5_54: ; in Loop: Header=BB5_47 Depth=5 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s7, v10 s_cmp_eq_u32 s7, -1 s_cselect_b32 s6, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_57 ; %bb.55: ; in Loop: Header=BB5_47 Depth=5 s_cmpk_lt_u32 s7, 0x100 s_cbranch_scc0 .LBB5_58 ; %bb.56: ; in Loop: Header=BB5_47 Depth=5 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[84:85], null, v6, 0x1800, s[16:17] s_mov_b32 s16, 0 v_mad_u64_u32 v[10:11], null, s7, 24, v[84:85] s_branch .LBB5_59 .LBB5_57: ; in Loop: Header=BB5_47 Depth=5 s_mov_b32 s7, -1 ; implicit-def: $vgpr10_vgpr11 s_branch .LBB5_62 .LBB5_58: ; in Loop: Header=BB5_47 Depth=5 s_mov_b32 s16, -1 ; implicit-def: $vgpr10_vgpr11 .LBB5_59: ; %Flow793 ; in Loop: Header=BB5_47 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB5_61 ; %bb.60: ; in Loop: Header=BB5_47 Depth=5 s_add_i32 s16, s7, 0xffffff00 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) s_lshr_b32 s18, s16, 8 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_and_b32 s7, s7, 0xff v_mad_u64_u32 v[10:11], null, v6, 0x1800, s[16:17] v_mad_u64_u32 v[84:85], null, s18, 24, v[10:11] global_load_b64 v[84:85], v[84:85], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[10:11], null, s7, 24, v[84:85] .LBB5_61: ; %Flow794 ; in Loop: Header=BB5_47 Depth=5 s_mov_b32 s7, 0 .LBB5_62: ; %Flow795 ; in Loop: Header=BB5_47 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s7 s_cbranch_vccnz .LBB5_66 ; %bb.63: ; in Loop: Header=BB5_47 Depth=5 v_add_nc_u32_e32 v10, s35, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v11, v10, v13 v_mul_lo_u32 v11, v11, s36 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v10, v10, v11 v_subrev_nc_u32_e32 v11, s36, v10 v_cmp_le_u32_e32 vcc_lo, s36, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v10, v10, v11, vcc_lo v_subrev_nc_u32_e32 v11, s36, v10 v_cmp_le_u32_e32 vcc_lo, s36, v10 s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e32 v14, v10, v11, vcc_lo s_and_saveexec_b32 s7, s2 s_cbranch_execz .LBB5_65 ; %bb.64: ; in Loop: Header=BB5_47 Depth=5 global_store_b32 v[37:38], v14, off .LBB5_65: ; in Loop: Header=BB5_47 Depth=5 s_or_b32 exec_lo, exec_lo, s7 v_dual_mov_b32 v10, v82 :: v_dual_mov_b32 v11, v83 s_sub_i32 s3, s3, s35 .LBB5_66: ; in Loop: Header=BB5_47 Depth=5 s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccz .LBB5_68 ; %bb.67: ; in Loop: Header=BB5_47 Depth=5 s_mov_b32 s6, 0 s_mov_b32 s7, -1 s_mov_b32 s16, -1 ; implicit-def: $sgpr3 ; implicit-def: $vgpr14 s_branch .LBB5_69 .LBB5_68: ; in Loop: Header=BB5_47 Depth=5 s_cmp_lt_i32 s3, 1 s_mov_b32 s7, 0 s_cselect_b32 s16, -1, 0 ; implicit-def: $sgpr6 .LBB5_69: ; %Flow801 ; in Loop: Header=BB5_47 Depth=5 v_dual_mov_b32 v83, v11 :: v_dual_mov_b32 v82, v10 s_and_not1_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB5_47 ; %bb.70: ; %loop.exit.guard750 ; in Loop: Header=BB5_43 Depth=4 s_xor_b32 s2, s7, -1 s_branch .LBB5_72 .LBB5_71: ; in Loop: Header=BB5_43 Depth=4 s_mov_b32 s2, -1 ; implicit-def: $vgpr10_vgpr11 ; implicit-def: $sgpr6 .LBB5_72: ; %Flow968 ; in Loop: Header=BB5_43 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s2 s_cbranch_vccz .LBB5_312 ; %bb.73: ; %.loopexit188 ; in Loop: Header=BB5_43 Depth=4 v_mbcnt_lo_u32_b32 v103, exec_lo, 0 ; implicit-def: $vgpr84_vgpr85 .LBB5_74: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; => This Loop Header: Depth=5 ; Child Loop BB5_92 Depth 6 ; Child Loop BB5_100 Depth 6 ; Child Loop BB5_106 Depth 6 ; Child Loop BB5_115 Depth 6 ; Child Loop BB5_120 Depth 6 ; Child Loop BB5_122 Depth 6 ; Child Loop BB5_142 Depth 6 ; Child Loop BB5_150 Depth 6 ; Child Loop BB5_156 Depth 6 ; Child Loop BB5_165 Depth 6 ; Child Loop BB5_173 Depth 6 ; Child Loop BB5_176 Depth 6 ; Child Loop BB5_178 Depth 6 ; Child Loop BB5_180 Depth 6 ; Child Loop BB5_182 Depth 6 ; Child Loop BB5_184 Depth 6 ; Child Loop BB5_186 Depth 6 ; Child Loop BB5_208 Depth 6 ; Child Loop BB5_216 Depth 6 ; Child Loop BB5_222 Depth 6 ; Child Loop BB5_231 Depth 6 ; Child Loop BB5_238 Depth 6 ; Child Loop BB5_241 Depth 6 ; Child Loop BB5_246 Depth 6 ; Child Loop BB5_253 Depth 6 ; Child Loop BB5_286 Depth 6 ; Child Loop BB5_294 Depth 6 ; Child Loop BB5_300 Depth 6 ; Child Loop BB5_309 Depth 6 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cmp_eq_u32_e64 s2, 0, v103 v_mov_b32_e32 v10, 0 s_mov_b32 s18, 0 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB5_76 ; %bb.75: ; in Loop: Header=BB5_74 Depth=5 global_load_b32 v10, v[52:53], off glc .LBB5_76: ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) v_readfirstlane_b32 s37, v10 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_delay_alu instid0(VALU_DEP_3) s_cmp_eq_u32 s37, 0x10100 s_cbranch_scc1 .LBB5_196 ; %bb.77: ; in Loop: Header=BB5_74 Depth=5 v_mov_b32_e32 v10, 0 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB5_79 ; %bb.78: ; in Loop: Header=BB5_74 Depth=5 v_dual_mov_b32 v10, 0x100 :: v_dual_mov_b32 v11, 0 global_atomic_cmpswap_b32 v10, v[54:55], v[10:11], off glc s_waitcnt vmcnt(0) v_cmp_ne_u32_e32 vcc_lo, 0, v10 v_cndmask_b32_e32 v10, 0x100, v10, vcc_lo .LBB5_79: ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s38, v10 s_cmp_lg_u32 s37, s38 s_cbranch_scc1 .LBB5_136 ; %bb.80: ; in Loop: Header=BB5_74 Depth=5 v_mbcnt_lo_u32_b32 v112, exec_lo, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v112 v_mov_b32_e32 v10, 0 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB5_82 ; %bb.81: ; in Loop: Header=BB5_74 Depth=5 global_load_b32 v10, v[54:55], off glc .LBB5_82: ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) v_readfirstlane_b32 s22, v10 s_mov_b32 s5, 2 s_delay_alu instid0(VALU_DEP_1) s_cmp_eq_u32 s22, 0x10100 s_cbranch_scc1 .LBB5_169 ; %bb.83: ; in Loop: Header=BB5_74 Depth=5 v_mov_b32_e32 v10, 1 s_and_saveexec_b32 s5, vcc_lo s_cbranch_execz .LBB5_87 ; %bb.84: ; in Loop: Header=BB5_74 Depth=5 global_load_b64 v[12:13], v[64:65], off glc s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v10, s3, s6, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_co_ci_u32_e64 v11, s3, s7, v13, s3 v_cmp_lt_u64_e64 s3, 0x752f, v[10:11] v_mov_b32_e32 v10, 1 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s16, s3 s_cbranch_execz .LBB5_86 ; %bb.85: ; in Loop: Header=BB5_74 Depth=5 v_dual_mov_b32 v10, s6 :: v_dual_mov_b32 v11, s7 global_atomic_cmpswap_b64 v[10:11], v[64:65], v[10:13], off glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e64 s3, v[10:11], v[12:13] s_delay_alu instid0(VALU_DEP_1) v_cndmask_b32_e64 v10, 1, 2, s3 .LBB5_86: ; %Flow957 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s16 .LBB5_87: ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s5 v_readfirstlane_b32 s39, v10 s_mov_b32 s5, 1 s_delay_alu instid0(VALU_DEP_1) s_cmp_eq_u32 s39, 1 s_cbranch_scc1 .LBB5_169 ; %bb.88: ; in Loop: Header=BB5_74 Depth=5 v_mov_b32_e32 v14, 0 v_mov_b32_e32 v15, 0 s_and_saveexec_b32 s23, vcc_lo s_cbranch_execz .LBB5_117 ; %bb.89: ; in Loop: Header=BB5_74 Depth=5 s_load_b64 s[16:17], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s3, v15 v_mov_b32_e32 v86, 0 v_mov_b32_e32 v87, 0 v_cmp_eq_u32_e64 s3, s3, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB5_95 ; %bb.90: ; in Loop: Header=BB5_74 Depth=5 s_waitcnt lgkmcnt(0) global_load_b64 v[12:13], v16, s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[10:11], v16, s[16:17] offset:40 global_load_b64 v[86:87], v16, s[16:17] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v11, v11, v13 v_and_b32_e32 v10, v10, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v11, v11, 24 v_mul_hi_u32 v14, v10, 24 v_mul_lo_u32 v10, v10, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v11, v14, v11 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v86, v10 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v11, vcc_lo, v87, v11, vcc_lo global_load_b64 v[10:11], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[86:87], v[12:13] s_cbranch_execz .LBB5_94 ; %bb.91: ; %.preheader3.i.i.i117.preheader ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s7, 0 .LBB5_92: ; %.preheader3.i.i.i117 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 s_clause 0x1 global_load_b64 v[10:11], v16, s[16:17] offset:40 global_load_b64 v[96:97], v16, s[16:17] v_dual_mov_b32 v12, v86 :: v_dual_mov_b32 v13, v87 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v10, v10, v12 v_and_b32_e32 v11, v11, v13 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[86:87], null, v10, 24, v[96:97] v_mov_b32_e32 v10, v87 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[96:97], null, v11, 24, v[10:11] v_mov_b32_e32 v87, v96 global_load_b64 v[10:11], v[86:87], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[86:87], v[12:13] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_92 ; %bb.93: ; %Flow951 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s7 .LBB5_94: ; %Flow953 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB5_95: ; %.loopexit4.i.i.i112 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[96:97], v16, s[16:17] offset:40 global_load_b128 v[10:13], v16, s[16:17] v_readfirstlane_b32 s18, v86 v_readfirstlane_b32 s19, v87 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s20, v96 v_readfirstlane_b32 s21, v97 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[20:21], s[18:19], s[20:21] s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB5_97 ; %bb.96: ; in Loop: Header=BB5_74 Depth=5 v_dual_mov_b32 v113, s6 :: v_dual_mov_b32 v114, 0 s_mul_i32 s6, s21, 24 s_mul_hi_u32 s7, s20, 24 v_dual_mov_b32 v115, 3 :: v_dual_mov_b32 v116, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s20, 24 s_waitcnt vmcnt(0) v_add_co_u32 v86, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v87, vcc_lo, s7, v11, vcc_lo global_store_b128 v[86:87], v[113:116], off offset:8 .LBB5_97: ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[20:21], 12 v_lshlrev_b64 v[14:15], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v86, vcc_lo, v12, s6 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo s_mov_b32 s5, s4 s_mov_b32 s6, s4 s_mov_b32 s7, s4 v_mov_b32_e32 v12, 0 v_add_co_u32 v86, vcc_lo, v86, v14 v_dual_mov_b32 v116, s7 :: v_dual_mov_b32 v113, s4 v_add_co_ci_u32_e32 v87, vcc_lo, v13, v15, vcc_lo v_dual_mov_b32 v115, s6 :: v_dual_mov_b32 v14, 0x1800 v_mov_b32_e32 v13, v12 v_dual_mov_b32 v15, v12 :: v_dual_mov_b32 v114, s5 s_clause 0x3 global_store_b128 v[86:87], v[12:15], off global_store_b128 v[86:87], v[113:116], off offset:16 global_store_b128 v[86:87], v[113:116], off offset:32 global_store_b128 v[86:87], v[113:116], off offset:48 s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB5_105 ; %bb.98: ; in Loop: Header=BB5_74 Depth=5 s_clause 0x1 global_load_b64 v[115:116], v16, s[16:17] offset:32 glc global_load_b64 v[12:13], v16, s[16:17] offset:40 v_dual_mov_b32 v113, s18 :: v_dual_mov_b32 v114, s19 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v12 v_readfirstlane_b32 s7, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[18:19] s_mul_i32 s7, s7, 24 s_mul_hi_u32 vcc_lo, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s7, vcc_lo, s7 v_add_co_u32 v96, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v97, vcc_lo, s7, v11, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[96:97], v[115:116], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v16, v[113:116], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[14:15], v[115:116] s_cbranch_execz .LBB5_101 ; %bb.99: ; %.preheader1.i.i.i115.preheader ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s7, 0 .LBB5_100: ; %.preheader1.i.i.i115 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_dual_mov_b32 v12, s18 :: v_dual_mov_b32 v13, s19 s_sleep 1 global_store_b64 v[96:97], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[12:15], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15] v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_100 .LBB5_101: ; %Flow949 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[12:13], v16, s[16:17] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v14, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v14 s_cbranch_execz .LBB5_103 ; %bb.102: ; in Loop: Header=BB5_74 Depth=5 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v14, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[12:13], v[14:15], off offset:8 .LBB5_103: ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[96:97], v[12:13], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[96:97] s_cbranch_vccnz .LBB5_105 ; %bb.104: ; in Loop: Header=BB5_74 Depth=5 global_load_b32 v15, v[12:13], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[96:97], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB5_105: ; %Flow950 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s21, 24 s_mul_hi_u32 s6, s20, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s20, 24 v_add_co_u32 v10, vcc_lo, v10, s5 v_add_co_ci_u32_e32 v11, vcc_lo, s6, v11, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v10, 20 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo .LBB5_106: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_mov_b32_e32 v12, 1 s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB5_108 ; %bb.107: ; in Loop: Header=BB5_106 Depth=6 global_load_b32 v12, v[10:11], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v12, 1, v12 .LBB5_108: ; in Loop: Header=BB5_106 Depth=6 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v12 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB5_110 ; %bb.109: ; in Loop: Header=BB5_106 Depth=6 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB5_111 .LBB5_110: ; in Loop: Header=BB5_106 Depth=6 s_mov_b32 s5, -1 .LBB5_111: ; %Flow944 ; in Loop: Header=BB5_106 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB5_106 ; %bb.112: ; in Loop: Header=BB5_74 Depth=5 global_load_b64 v[14:15], v[86:87], off s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB5_116 ; %bb.113: ; in Loop: Header=BB5_74 Depth=5 s_clause 0x2 global_load_b64 v[12:13], v16, s[16:17] offset:40 global_load_b64 v[96:97], v16, s[16:17] offset:24 glc global_load_b64 v[86:87], v16, s[16:17] s_waitcnt vmcnt(2) v_add_co_u32 v113, vcc_lo, v12, 1 v_add_co_ci_u32_e32 v114, vcc_lo, 0, v13, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v113, s18 v_add_co_ci_u32_e32 v11, vcc_lo, s19, v114, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] v_dual_cndmask_b32 v11, v11, v114 :: v_dual_cndmask_b32 v10, v10, v113 v_and_b32_e32 v13, v11, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v12, v10, v12 v_mul_hi_u32 v113, v12, 24 v_mul_lo_u32 v12, v12, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v86, vcc_lo, v86, v12 v_mov_b32_e32 v12, v96 v_mul_lo_u32 v13, v13, 24 v_add_nc_u32_e32 v13, v113, v13 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v87, vcc_lo, v87, v13, vcc_lo v_mov_b32_e32 v13, v97 global_store_b64 v[86:87], v[96:97], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[96:97] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_116 ; %bb.114: ; %.preheader.i.i.i114.preheader ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s3, 0 .LBB5_115: ; %.preheader.i.i.i114 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 global_store_b64 v[86:87], v[12:13], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[96:97], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[96:97], v[12:13] v_dual_mov_b32 v12, v96 :: v_dual_mov_b32 v13, v97 s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB5_115 .LBB5_116: ; %Flow942 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 .LBB5_117: ; %Flow954 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s23 s_waitcnt vmcnt(0) v_readfirstlane_b32 s18, v14 v_readfirstlane_b32 s19, v15 s_cmp_eq_u64 s[18:19], 0 s_cbranch_scc1 .LBB5_168 ; %bb.118: ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s3, exec_lo s_mov_b32 s5, exec_lo v_mbcnt_lo_u32_b32 v12, s3, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_u32_e32 0x300, v12 s_cbranch_execz .LBB5_121 ; %bb.119: ; %.preheader175.preheader ; in Loop: Header=BB5_74 Depth=5 v_lshlrev_b32_e32 v10, 3, v12 s_bcnt1_i32_b32 s6, s3 s_mov_b32 s16, s4 s_lshl_b32 s7, s6, 3 s_mov_b32 s17, 0 v_add_co_u32 v10, s3, s18, v10 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v11, null, s19, 0, s3 .LBB5_120: ; %.preheader175 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v12, s6, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mov_b32_e32 v14, v13 v_cmp_lt_u32_e32 vcc_lo, 0x2ff, v12 global_store_b64 v[10:11], v[13:14], off v_add_co_u32 v10, s3, v10, s7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e64 v11, s3, s16, v11, s3 s_or_b32 s17, vcc_lo, s17 s_and_not1_b32 exec_lo, exec_lo, s17 s_cbranch_execnz .LBB5_120 .LBB5_121: ; %Flow936 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 ; implicit-def: $sgpr5 .LBB5_122: ; %.loopexit176 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 ;;#ASMSTART ;;#ASMEND v_cmp_eq_u32_e32 vcc_lo, 0, v112 v_mov_b32_e32 v10, s22 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB5_124 ; %bb.123: ; in Loop: Header=BB5_122 Depth=6 global_load_b32 v10, v[54:55], off glc .LBB5_124: ; in Loop: Header=BB5_122 Depth=6 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) v_readfirstlane_b32 s22, v10 s_and_not1_b32 s3, s5, exec_lo s_and_b32 s5, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 s5, s3, s5 s_cmp_lg_u32 s22, 0x10100 s_cbranch_scc0 .LBB5_131 ; %bb.125: ; in Loop: Header=BB5_122 Depth=6 v_mov_b32_e32 v10, s39 s_and_saveexec_b32 s6, vcc_lo s_cbranch_execz .LBB5_129 ; %bb.126: ; in Loop: Header=BB5_122 Depth=6 s_add_i32 s3, s22, 0xffffff00 v_mov_b32_e32 v12, 0 s_lshr_b32 s3, s3, 8 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[10:11], null, v6, 0x1800, s[16:17] v_mad_u64_u32 v[14:15], null, s3, 24, v[10:11] v_dual_mov_b32 v11, s19 :: v_dual_mov_b32 v10, s18 v_mov_b32_e32 v13, v12 global_atomic_cmpswap_b64 v[10:11], v[14:15], v[10:13], off glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e64 s3, 0, v[10:11] v_mov_b32_e32 v10, s39 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s7, s3 s_cbranch_execz .LBB5_128 ; %bb.127: ; in Loop: Header=BB5_122 Depth=6 s_waitcnt_vscnt null, 0x0 global_atomic_add_u32 v[54:55], v39, off v_mov_b32_e32 v10, 0 .LBB5_128: ; %Flow929 ; in Loop: Header=BB5_122 Depth=6 s_or_b32 exec_lo, exec_lo, s7 .LBB5_129: ; in Loop: Header=BB5_122 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s6 v_readfirstlane_b32 s3, v10 s_delay_alu instid0(VALU_DEP_1) s_cmp_eq_u32 s3, 0 s_cbranch_scc1 .LBB5_132 ; %bb.130: ; in Loop: Header=BB5_122 Depth=6 s_mov_b32 s6, 0 s_and_not1_b32 vcc_lo, vcc_lo, exec_lo s_sleep 2 ; implicit-def: $sgpr39 s_branch .LBB5_133 .LBB5_131: ; in Loop: Header=BB5_122 Depth=6 s_mov_b32 s16, -1 s_mov_b32 s6, -1 ; implicit-def: $vgpr112 ; implicit-def: $sgpr22 ; implicit-def: $sgpr3 ; implicit-def: $sgpr7 s_branch .LBB5_134 .LBB5_132: ; in Loop: Header=BB5_122 Depth=6 s_mov_b32 s6, -1 ; implicit-def: $vgpr112 ; implicit-def: $sgpr22 ; implicit-def: $sgpr3 .LBB5_133: ; %Flow933 ; in Loop: Header=BB5_122 Depth=6 s_and_not1_b32 s5, s5, exec_lo s_and_b32 s17, vcc_lo, exec_lo s_mov_b32 s7, 0 s_mov_b32 s16, 0 s_or_b32 s5, s5, s17 .LBB5_134: ; %Flow932 ; in Loop: Header=BB5_122 Depth=6 s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_137 ; %bb.135: ; in Loop: Header=BB5_122 Depth=6 s_mov_b32 s39, s3 s_branch .LBB5_122 .LBB5_136: ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s3, -1 ; implicit-def: $sgpr18 s_branch .LBB5_189 .LBB5_137: ; %loop.exit.guard756 ; in Loop: Header=BB5_74 Depth=5 s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccz .LBB5_167 ; %bb.138: ; in Loop: Header=BB5_74 Depth=5 s_and_saveexec_b32 s40, s5 s_cbranch_execz .LBB5_166 ; %bb.139: ; in Loop: Header=BB5_74 Depth=5 s_load_b64 s[16:17], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s3, v15 v_mov_b32_e32 v86, 0 v_mov_b32_e32 v87, 0 v_cmp_eq_u32_e64 s3, s3, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB5_145 ; %bb.140: ; in Loop: Header=BB5_74 Depth=5 s_waitcnt lgkmcnt(0) global_load_b64 v[12:13], v16, s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[10:11], v16, s[16:17] offset:40 global_load_b64 v[86:87], v16, s[16:17] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v11, v11, v13 v_and_b32_e32 v10, v10, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v11, v11, 24 v_mul_hi_u32 v14, v10, 24 v_mul_lo_u32 v10, v10, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v11, v14, v11 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v86, v10 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v11, vcc_lo, v87, v11, vcc_lo global_load_b64 v[10:11], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[86:87], v[12:13] s_cbranch_execz .LBB5_144 ; %bb.141: ; %.preheader3.i.i.i124.preheader ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s7, 0 .LBB5_142: ; %.preheader3.i.i.i124 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 s_clause 0x1 global_load_b64 v[10:11], v16, s[16:17] offset:40 global_load_b64 v[96:97], v16, s[16:17] v_dual_mov_b32 v12, v86 :: v_dual_mov_b32 v13, v87 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v10, v10, v12 v_and_b32_e32 v11, v11, v13 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[86:87], null, v10, 24, v[96:97] v_mov_b32_e32 v10, v87 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[96:97], null, v11, 24, v[10:11] v_mov_b32_e32 v87, v96 global_load_b64 v[10:11], v[86:87], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[86:87], v[12:13] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_142 ; %bb.143: ; %Flow924 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s7 .LBB5_144: ; %Flow926 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB5_145: ; %.loopexit4.i.i.i119 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[96:97], v16, s[16:17] offset:40 global_load_b128 v[10:13], v16, s[16:17] v_readfirstlane_b32 s20, v86 v_readfirstlane_b32 s21, v87 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s22, v96 v_readfirstlane_b32 s23, v97 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[22:23], s[20:21], s[22:23] s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB5_147 ; %bb.146: ; in Loop: Header=BB5_74 Depth=5 v_dual_mov_b32 v112, s6 :: v_dual_mov_b32 v113, 0 s_mul_i32 s6, s23, 24 s_mul_hi_u32 s7, s22, 24 v_dual_mov_b32 v114, 3 :: v_dual_mov_b32 v115, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s22, 24 s_waitcnt vmcnt(0) v_add_co_u32 v86, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v87, vcc_lo, s7, v11, vcc_lo global_store_b128 v[86:87], v[112:115], off offset:8 .LBB5_147: ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[22:23], 12 v_lshlrev_b64 v[14:15], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v12, vcc_lo, v12, s6 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo s_mov_b32 s7, s4 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v86, vcc_lo, v12, v14 s_mov_b32 s5, s4 s_mov_b32 s6, s4 v_dual_mov_b32 v96, 0 :: v_dual_mov_b32 v113, s19 v_add_co_ci_u32_e32 v87, vcc_lo, v13, v15, vcc_lo v_dual_mov_b32 v112, s18 :: v_dual_mov_b32 v15, s7 v_dual_mov_b32 v14, s6 :: v_dual_mov_b32 v13, s5 s_delay_alu instid0(VALU_DEP_4) v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v97, v96 s_clause 0x4 global_store_b64 v[86:87], v[112:113], off global_store_b128 v[86:87], v[12:15], off offset:8 global_store_b128 v[86:87], v[12:15], off offset:24 global_store_b128 v[86:87], v[12:15], off offset:40 global_store_b64 v[86:87], v[96:97], off offset:56 s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB5_155 ; %bb.148: ; in Loop: Header=BB5_74 Depth=5 s_clause 0x1 global_load_b64 v[114:115], v16, s[16:17] offset:32 glc global_load_b64 v[12:13], v16, s[16:17] offset:40 v_dual_mov_b32 v112, s20 :: v_dual_mov_b32 v113, s21 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v12 v_readfirstlane_b32 s7, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[20:21] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s18, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s18, s18, s7 v_add_co_u32 v86, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v87, vcc_lo, s18, v11, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[86:87], v[114:115], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v16, v[112:115], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[14:15], v[114:115] s_cbranch_execz .LBB5_151 ; %bb.149: ; %.preheader1.i.i.i122.preheader ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s7, 0 .LBB5_150: ; %.preheader1.i.i.i122 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_dual_mov_b32 v12, s20 :: v_dual_mov_b32 v13, s21 s_sleep 1 global_store_b64 v[86:87], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[12:15], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15] v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_150 .LBB5_151: ; %Flow922 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[12:13], v16, s[16:17] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v14, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v14 s_cbranch_execz .LBB5_153 ; %bb.152: ; in Loop: Header=BB5_74 Depth=5 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v14, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[12:13], v[14:15], off offset:8 .LBB5_153: ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[86:87], v[12:13], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[86:87] s_cbranch_vccnz .LBB5_155 ; %bb.154: ; in Loop: Header=BB5_74 Depth=5 global_load_b32 v15, v[12:13], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[86:87], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB5_155: ; %Flow923 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s23, 24 s_mul_hi_u32 s6, s22, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s22, 24 v_add_co_u32 v10, vcc_lo, v10, s5 v_add_co_ci_u32_e32 v11, vcc_lo, s6, v11, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v10, 20 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo .LBB5_156: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_mov_b32_e32 v12, 1 s_and_saveexec_b32 s5, s3 s_cbranch_execz .LBB5_158 ; %bb.157: ; in Loop: Header=BB5_156 Depth=6 global_load_b32 v12, v[10:11], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v12, 1, v12 .LBB5_158: ; in Loop: Header=BB5_156 Depth=6 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v12 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB5_160 ; %bb.159: ; in Loop: Header=BB5_156 Depth=6 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB5_161 .LBB5_160: ; in Loop: Header=BB5_156 Depth=6 s_mov_b32 s5, -1 .LBB5_161: ; %Flow917 ; in Loop: Header=BB5_156 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB5_156 ; %bb.162: ; in Loop: Header=BB5_74 Depth=5 s_and_b32 exec_lo, exec_lo, s3 s_cbranch_execz .LBB5_166 ; %bb.163: ; in Loop: Header=BB5_74 Depth=5 s_clause 0x2 global_load_b64 v[12:13], v16, s[16:17] offset:40 global_load_b64 v[86:87], v16, s[16:17] offset:24 glc global_load_b64 v[14:15], v16, s[16:17] s_waitcnt vmcnt(2) v_add_co_u32 v96, vcc_lo, v12, 1 v_add_co_ci_u32_e32 v97, vcc_lo, 0, v13, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v96, s20 v_add_co_ci_u32_e32 v11, vcc_lo, s21, v97, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] v_dual_cndmask_b32 v11, v11, v97 :: v_dual_cndmask_b32 v10, v10, v96 v_and_b32_e32 v13, v11, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v12, v10, v12 v_mul_hi_u32 v96, v12, 24 v_mul_lo_u32 v12, v12, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v14, vcc_lo, v14, v12 v_mov_b32_e32 v12, v86 v_mul_lo_u32 v13, v13, 24 v_add_nc_u32_e32 v13, v96, v13 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v15, vcc_lo, v15, v13, vcc_lo v_mov_b32_e32 v13, v87 global_store_b64 v[14:15], v[86:87], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[86:87] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_166 ; %bb.164: ; %.preheader.i.i.i121.preheader ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s3, 0 .LBB5_165: ; %.preheader.i.i.i121 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 global_store_b64 v[14:15], v[12:13], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[86:87], v[12:13] v_dual_mov_b32 v12, v86 :: v_dual_mov_b32 v13, v87 s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB5_165 .LBB5_166: ; %Flow927 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s40 s_mov_b32 s7, s39 .LBB5_167: ; %Flow928 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s39, s7 .LBB5_168: ; %Flow938 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s5, s39 .LBB5_169: ; %__ockl_devmem_request.exit125 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_cmp_eq_u32 s5, 0 s_cselect_b32 s3, -1, 0 s_and_b32 vcc_lo, exec_lo, s3 s_cbranch_vccnz .LBB5_188 ; %bb.170: ; in Loop: Header=BB5_74 Depth=5 v_mbcnt_lo_u32_b32 v10, exec_lo, 0 s_mov_b32 s18, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB5_187 ; %bb.171: ; in Loop: Header=BB5_74 Depth=5 global_load_b64 v[10:11], v[64:65], off glc s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v10, vcc_lo, s6, v10 v_sub_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_u64_e32 vcc_lo, 0x7530, v[10:11] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_187 ; %bb.172: ; in Loop: Header=BB5_74 Depth=5 v_sub_nc_u32_e32 v10, 0x7530, v10 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) v_readfirstlane_b32 s6, v10 s_delay_alu instid0(VALU_DEP_1) s_ashr_i32 s7, s6, 31 s_waitcnt lgkmcnt(0) s_add_u32 s6, s16, s6 s_addc_u32 s7, s17, s7 .LBB5_173: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_waitcnt lgkmcnt(0) s_add_u32 s20, s16, 0x659 s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccnz .LBB5_176 ; %bb.174: ; %.preheader11.i138 ; in Loop: Header=BB5_173 Depth=6 s_sleep 0x7f s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) s_branch .LBB5_173 .LBB5_175: ; %.preheader9.i137 ; in Loop: Header=BB5_176 Depth=6 s_sleep 63 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_176: ; %Flow908 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_waitcnt lgkmcnt(0) s_add_u32 s20, s16, 0x326 s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccz .LBB5_175 ; %bb.177: ; %Flow905 ; in Loop: Header=BB5_74 Depth=5 s_add_u32 s20, s16, 0x18c s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccnz .LBB5_180 .LBB5_178: ; %.preheader7.i136 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 31 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) s_add_u32 s20, s16, 0x18c s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccnz .LBB5_178 s_branch .LBB5_180 .LBB5_179: ; %.preheader5.i135 ; in Loop: Header=BB5_180 Depth=6 s_sleep 15 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_180: ; %.loopexit8.i128 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_waitcnt lgkmcnt(0) s_add_u32 s20, s16, 0xc0 s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccz .LBB5_179 s_branch .LBB5_182 .LBB5_181: ; %.preheader3.i134 ; in Loop: Header=BB5_182 Depth=6 s_sleep 7 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_182: ; %Flow899 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_waitcnt lgkmcnt(0) s_add_u32 s20, s16, 0x59 s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccz .LBB5_181 s_branch .LBB5_184 .LBB5_183: ; %.preheader1.i133 ; in Loop: Header=BB5_184 Depth=6 s_sleep 3 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_184: ; %Flow896 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_waitcnt lgkmcnt(0) s_add_u32 s20, s16, 38 s_addc_u32 s21, s17, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s19, s[6:7], s[20:21] s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccz .LBB5_183 ; %bb.185: ; %Flow893 ; in Loop: Header=BB5_74 Depth=5 v_cmp_le_u64_e64 s16, s[6:7], s[16:17] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB5_187 .LBB5_186: ; %.preheader.i132 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) v_cmp_gt_u64_e64 s16, s[6:7], s[16:17] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB5_186 .LBB5_187: ; %__ockl_rtcwait_u32.exit139 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s18 s_cmp_lg_u32 s5, 2 v_mov_b32_e32 v85, s4 s_cselect_b32 s5, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) v_cndmask_b32_e64 v84, 0, 1, s5 .LBB5_188: ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s18, 0 .LBB5_189: ; %Flow960 ; in Loop: Header=BB5_74 Depth=5 s_and_b32 vcc_lo, exec_lo, s3 s_cbranch_vccz .LBB5_197 ; %bb.190: ; in Loop: Header=BB5_74 Depth=5 v_mov_b32_e32 v10, 1 v_mov_b32_e32 v11, 0 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB5_194 ; %bb.191: ; in Loop: Header=BB5_74 Depth=5 global_load_b64 v[12:13], v[66:67], off glc s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v10, vcc_lo, s6, v12 v_sub_co_ci_u32_e32 v11, vcc_lo, s7, v13, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_cmp_lt_u64_e32 vcc_lo, 0x4e1f, v[10:11] v_mov_b32_e32 v10, 1 v_mov_b32_e32 v11, 0 s_and_saveexec_b32 s5, vcc_lo s_cbranch_execz .LBB5_193 ; %bb.192: ; in Loop: Header=BB5_74 Depth=5 v_dual_mov_b32 v10, s6 :: v_dual_mov_b32 v11, s7 global_atomic_cmpswap_b64 v[10:11], v[66:67], v[10:13], off glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[12:13] v_mov_b32_e32 v11, s4 v_cndmask_b32_e64 v10, 0, 1, vcc_lo .LBB5_193: ; %Flow887 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 .LBB5_194: ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s3 v_readfirstlane_b32 s6, v10 v_readfirstlane_b32 s7, v11 s_mov_b32 s18, 0 s_delay_alu instid0(VALU_DEP_1) s_cmp_lg_u64 s[6:7], 0 s_cbranch_scc0 .LBB5_198 ; %bb.195: ; in Loop: Header=BB5_74 Depth=5 v_dual_mov_b32 v11, s7 :: v_dual_mov_b32 v10, s6 .LBB5_196: ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v85, v11 :: v_dual_mov_b32 v84, v10 .LBB5_197: ; %Flow963 ; in Loop: Header=BB5_74 Depth=5 s_xor_b32 s2, s18, -1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s2 s_cbranch_vccnz .LBB5_74 s_branch .LBB5_313 .LBB5_198: ; in Loop: Header=BB5_74 Depth=5 v_mov_b32_e32 v14, 0 v_mov_b32_e32 v15, 0 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB5_234 ; %bb.199: ; in Loop: Header=BB5_74 Depth=5 s_clause 0x1 global_load_b64 v[12:13], v16, s[12:13] glc global_load_b64 v[10:11], v16, s[14:15] s_waitcnt vmcnt(0) v_cmp_ge_u64_e32 vcc_lo, v[12:13], v[10:11] s_cbranch_vccnz .LBB5_203 ; %bb.200: ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s5, exec_lo s_mov_b32 s2, exec_lo v_mbcnt_lo_u32_b32 v86, s5, 0 ; implicit-def: $vgpr12_vgpr13 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v86 s_cbranch_execz .LBB5_202 ; %bb.201: ; in Loop: Header=BB5_74 Depth=5 s_bcnt1_i32_b32 s5, s5 v_mov_b32_e32 v13, 0 s_lshl_b32 s5, s5, 21 s_delay_alu instid0(SALU_CYCLE_1) v_mov_b32_e32 v12, s5 global_atomic_add_u64 v[12:13], v16, v[12:13], s[12:13] glc .LBB5_202: ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s2 s_waitcnt vmcnt(0) v_readfirstlane_b32 s7, v13 v_readfirstlane_b32 s6, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[14:15], null, v86, 0x200000, s[6:7] v_cmp_ge_u64_e64 s2, v[14:15], v[10:11] s_branch .LBB5_204 .LBB5_203: ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s2, -1 ; implicit-def: $vgpr14_vgpr15 .LBB5_204: ; %Flow884 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s22, s2 s_cbranch_execz .LBB5_233 ; %bb.205: ; in Loop: Header=BB5_74 Depth=5 s_load_b64 s[16:17], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s2, v15 v_mov_b32_e32 v86, 0 v_mov_b32_e32 v87, 0 v_cmp_eq_u32_e64 s2, s2, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_211 ; %bb.206: ; in Loop: Header=BB5_74 Depth=5 s_waitcnt lgkmcnt(0) global_load_b64 v[12:13], v16, s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[10:11], v16, s[16:17] offset:40 global_load_b64 v[86:87], v16, s[16:17] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v11, v11, v13 v_and_b32_e32 v10, v10, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v11, v11, 24 v_mul_hi_u32 v14, v10, 24 v_mul_lo_u32 v10, v10, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v11, v14, v11 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v86, v10 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v11, vcc_lo, v87, v11, vcc_lo global_load_b64 v[10:11], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[86:87], v[12:13] s_cbranch_execz .LBB5_210 ; %bb.207: ; %.preheader3.i.i.i145.preheader ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s7, 0 .LBB5_208: ; %.preheader3.i.i.i145 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 s_clause 0x1 global_load_b64 v[10:11], v16, s[16:17] offset:40 global_load_b64 v[96:97], v16, s[16:17] v_dual_mov_b32 v12, v86 :: v_dual_mov_b32 v13, v87 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v10, v10, v12 v_and_b32_e32 v11, v11, v13 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[86:87], null, v10, 24, v[96:97] v_mov_b32_e32 v10, v87 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[96:97], null, v11, 24, v[10:11] v_mov_b32_e32 v87, v96 global_load_b64 v[10:11], v[86:87], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[86:87], v[12:13] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_208 ; %bb.209: ; %Flow880 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s7 .LBB5_210: ; %Flow882 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB5_211: ; %.loopexit4.i.i.i140 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[96:97], v16, s[16:17] offset:40 global_load_b128 v[10:13], v16, s[16:17] v_readfirstlane_b32 s18, v86 v_readfirstlane_b32 s19, v87 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s20, v96 v_readfirstlane_b32 s21, v97 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[20:21], s[18:19], s[20:21] s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_213 ; %bb.212: ; in Loop: Header=BB5_74 Depth=5 v_dual_mov_b32 v112, s6 :: v_dual_mov_b32 v113, 0 s_mul_i32 s6, s21, 24 s_mul_hi_u32 s7, s20, 24 v_dual_mov_b32 v114, 3 :: v_dual_mov_b32 v115, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s20, 24 s_waitcnt vmcnt(0) v_add_co_u32 v86, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v87, vcc_lo, s7, v11, vcc_lo global_store_b128 v[86:87], v[112:115], off offset:8 .LBB5_213: ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[20:21], 12 v_lshlrev_b64 v[14:15], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v86, vcc_lo, v12, s6 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo s_mov_b32 s5, s4 s_mov_b32 s6, s4 s_mov_b32 s7, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v115, s7 v_add_co_u32 v86, vcc_lo, v86, v14 v_add_co_ci_u32_e32 v87, vcc_lo, v13, v15, vcc_lo v_dual_mov_b32 v14, 0x200000 :: v_dual_mov_b32 v13, v12 v_dual_mov_b32 v15, v12 :: v_dual_mov_b32 v114, s6 v_dual_mov_b32 v113, s5 :: v_dual_mov_b32 v112, s4 s_clause 0x3 global_store_b128 v[86:87], v[12:15], off global_store_b128 v[86:87], v[112:115], off offset:16 global_store_b128 v[86:87], v[112:115], off offset:32 global_store_b128 v[86:87], v[112:115], off offset:48 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_221 ; %bb.214: ; in Loop: Header=BB5_74 Depth=5 s_clause 0x1 global_load_b64 v[114:115], v16, s[16:17] offset:32 glc global_load_b64 v[12:13], v16, s[16:17] offset:40 v_dual_mov_b32 v112, s18 :: v_dual_mov_b32 v113, s19 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v12 v_readfirstlane_b32 s7, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[18:19] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s23, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s23, s23, s7 v_add_co_u32 v96, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v97, vcc_lo, s23, v11, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[96:97], v[114:115], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v16, v[112:115], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[14:15], v[114:115] s_cbranch_execz .LBB5_217 ; %bb.215: ; %.preheader1.i.i.i143.preheader ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s7, 0 .LBB5_216: ; %.preheader1.i.i.i143 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_dual_mov_b32 v12, s18 :: v_dual_mov_b32 v13, s19 s_sleep 1 global_store_b64 v[96:97], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[12:15], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15] v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_216 .LBB5_217: ; %Flow878 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[12:13], v16, s[16:17] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v14, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v14 s_cbranch_execz .LBB5_219 ; %bb.218: ; in Loop: Header=BB5_74 Depth=5 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v14, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[12:13], v[14:15], off offset:8 .LBB5_219: ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[96:97], v[12:13], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[96:97] s_cbranch_vccnz .LBB5_221 ; %bb.220: ; in Loop: Header=BB5_74 Depth=5 global_load_b32 v15, v[12:13], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[96:97], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB5_221: ; %Flow879 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s21, 24 s_mul_hi_u32 s6, s20, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s20, 24 v_add_co_u32 v10, vcc_lo, v10, s5 v_add_co_ci_u32_e32 v11, vcc_lo, s6, v11, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v10, 20 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo .LBB5_222: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_mov_b32_e32 v12, 1 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_224 ; %bb.223: ; in Loop: Header=BB5_222 Depth=6 global_load_b32 v12, v[10:11], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v12, 1, v12 .LBB5_224: ; in Loop: Header=BB5_222 Depth=6 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v12 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB5_226 ; %bb.225: ; in Loop: Header=BB5_222 Depth=6 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB5_227 .LBB5_226: ; in Loop: Header=BB5_222 Depth=6 s_mov_b32 s5, -1 .LBB5_227: ; %Flow873 ; in Loop: Header=BB5_222 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB5_222 ; %bb.228: ; in Loop: Header=BB5_74 Depth=5 global_load_b64 v[14:15], v[86:87], off s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_232 ; %bb.229: ; in Loop: Header=BB5_74 Depth=5 s_clause 0x2 global_load_b64 v[12:13], v16, s[16:17] offset:40 global_load_b64 v[96:97], v16, s[16:17] offset:24 glc global_load_b64 v[86:87], v16, s[16:17] s_waitcnt vmcnt(2) v_add_co_u32 v112, vcc_lo, v12, 1 v_add_co_ci_u32_e32 v113, vcc_lo, 0, v13, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v112, s18 v_add_co_ci_u32_e32 v11, vcc_lo, s19, v113, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] v_dual_cndmask_b32 v11, v11, v113 :: v_dual_cndmask_b32 v10, v10, v112 v_and_b32_e32 v13, v11, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v12, v10, v12 v_mul_hi_u32 v112, v12, 24 v_mul_lo_u32 v12, v12, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v86, vcc_lo, v86, v12 v_mov_b32_e32 v12, v96 v_mul_lo_u32 v13, v13, 24 v_add_nc_u32_e32 v13, v112, v13 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v87, vcc_lo, v87, v13, vcc_lo v_mov_b32_e32 v13, v97 global_store_b64 v[86:87], v[96:97], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[96:97] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_232 ; %bb.230: ; %.preheader.i.i.i142.preheader ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s2, 0 .LBB5_231: ; %.preheader.i.i.i142 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 global_store_b64 v[86:87], v[12:13], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[96:97], v16, v[10:13], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[96:97], v[12:13] v_dual_mov_b32 v12, v96 :: v_dual_mov_b32 v13, v97 s_or_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB5_231 .LBB5_232: ; %Flow871 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 .LBB5_233: ; %Flow885 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s22 .LBB5_234: ; %__ockl_devmem_request.exit146 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) v_readfirstlane_b32 s16, v14 v_readfirstlane_b32 s17, v15 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_delay_alu instid0(VALU_DEP_3) s_cmp_eq_u64 s[16:17], 0 s_cbranch_scc1 .LBB5_279 ; %bb.235: ; in Loop: Header=BB5_74 Depth=5 v_mbcnt_lo_u32_b32 v10, exec_lo, 0 ;;#ASMSTART ;;#ASMEND global_load_b32 v14, v[50:51], off s_bcnt1_i32_b32 s3, exec_lo s_add_u32 s6, s16, 16 s_addc_u32 s7, s17, 0 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v11, 31, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_lshrrev_b32_e32 v13, 5, v11 s_and_saveexec_b32 s2, s1 s_xor_b32 s5, exec_lo, s2 s_cbranch_execz .LBB5_243 ; %bb.236: ; in Loop: Header=BB5_74 Depth=5 global_load_b32 v15, v[68:69], off s_mov_b32 s18, exec_lo v_cmpx_lt_u32_e64 v10, v13 s_cbranch_execz .LBB5_239 ; %bb.237: ; %.preheader172.preheader ; in Loop: Header=BB5_74 Depth=5 v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v86, v10 s_add_u32 s2, s16, 16 s_addc_u32 s19, s17, 0 s_mov_b32 s20, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[11:12], 2, v[10:11] s_mov_b32 s21, 0 v_add_co_u32 v11, vcc_lo, s2, v11 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v12, vcc_lo, s19, v12, vcc_lo s_lshl_b32 s19, s3, 2 .LBB5_238: ; %.preheader172 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_add_nc_u32_e32 v86, s3, v86 global_store_b32 v[11:12], v16, off v_add_co_u32 v11, s2, v11, s19 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e64 v12, s2, s20, v12, s2 v_cmp_ge_u32_e32 vcc_lo, v86, v13 s_or_b32 s21, vcc_lo, s21 s_and_not1_b32 exec_lo, exec_lo, s21 s_cbranch_execnz .LBB5_238 .LBB5_239: ; %Flow860 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s18 global_load_b32 v86, v[70:71], off s_mov_b32 s2, exec_lo s_waitcnt vmcnt(0) v_mad_u64_u32 v[11:12], null, v15, v10, v[86:87] s_delay_alu instid0(VALU_DEP_1) v_cmpx_lt_u32_e64 v11, v14 s_cbranch_execz .LBB5_242 ; %bb.240: ; %.preheader170.preheader ; in Loop: Header=BB5_74 Depth=5 v_mul_lo_u32 v12, v15, s3 s_mov_b32 s18, 0 .LBB5_241: ; %.preheader170 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_lshlrev_b32_e64 v15, v11, 1 v_lshrrev_b32_e32 v86, 3, v11 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v11, v11, v12 v_and_b32_e32 v86, 0x1ffffffc, v86 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_ge_u32_e32 vcc_lo, v11, v14 global_store_b32 v86, v15, s[6:7] s_or_b32 s18, vcc_lo, s18 s_and_not1_b32 exec_lo, exec_lo, s18 s_cbranch_execnz .LBB5_241 .LBB5_242: ; %Flow857 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s2 .LBB5_243: ; %Flow865 ; in Loop: Header=BB5_74 Depth=5 s_and_not1_saveexec_b32 s5, s5 s_cbranch_execz .LBB5_248 ; %bb.244: ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s18, exec_lo v_cmpx_lt_u32_e64 v10, v13 s_cbranch_execz .LBB5_247 ; %bb.245: ; %.preheader.preheader ; in Loop: Header=BB5_74 Depth=5 global_load_b32 v15, v[80:81], off v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v86, v10 s_add_u32 s2, s16, 16 s_addc_u32 s19, s17, 0 s_mov_b32 s20, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[11:12], 2, v[10:11] s_mov_b32 s21, 0 v_add_co_u32 v11, vcc_lo, s2, v11 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v12, vcc_lo, s19, v12, vcc_lo s_lshl_b32 s19, s3, 2 .LBB5_246: ; %.preheader ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_add_nc_u32_e32 v86, s3, v86 s_waitcnt vmcnt(0) global_store_b32 v[11:12], v15, off v_add_co_u32 v11, s2, v11, s19 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e64 v12, s2, s20, v12, s2 v_cmp_ge_u32_e32 vcc_lo, v86, v13 s_or_b32 s21, vcc_lo, s21 s_and_not1_b32 exec_lo, exec_lo, s21 s_cbranch_execnz .LBB5_246 .LBB5_247: ; %Flow863 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s18 .LBB5_248: ; %.loopexit ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_mov_b32 s2, exec_lo v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB5_252 ; %bb.249: ; in Loop: Header=BB5_74 Depth=5 v_and_b32_e32 v10, 31, v14 s_mov_b32 s3, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_ne_u32_e32 0, v10 s_cbranch_execz .LBB5_251 ; %bb.250: ; in Loop: Header=BB5_74 Depth=5 v_add_nc_u32_e32 v15, -1, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[11:12], 2, v[15:16] v_add_co_u32 v11, vcc_lo, s6, v11 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo global_load_b32 v13, v[11:12], off s_waitcnt vmcnt(0) v_lshl_or_b32 v10, -1, v10, v13 global_store_b32 v[11:12], v10, off .LBB5_251: ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s3 global_store_b128 v16, v[6:9], s[16:17] .LBB5_252: ; %Flow854 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $sgpr5 .LBB5_253: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 ;;#ASMSTART ;;#ASMEND v_cmp_eq_u32_e64 s2, 0, v103 v_mov_b32_e32 v10, s37 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB5_255 ; %bb.254: ; in Loop: Header=BB5_253 Depth=6 global_load_b32 v10, v[52:53], off glc .LBB5_255: ; in Loop: Header=BB5_253 Depth=6 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) v_readfirstlane_b32 s37, v10 s_and_not1_b32 s3, s5, exec_lo s_and_b32 s5, s2, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 s5, s3, s5 s_cmp_eq_u32 s37, 0x10100 s_cbranch_scc1 .LBB5_262 ; %bb.256: ; in Loop: Header=BB5_253 Depth=6 v_mov_b32_e32 v10, s38 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB5_258 ; %bb.257: ; in Loop: Header=BB5_253 Depth=6 global_load_b32 v10, v[54:55], off glc .LBB5_258: ; in Loop: Header=BB5_253 Depth=6 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) v_readfirstlane_b32 s38, v10 s_delay_alu instid0(VALU_DEP_1) s_cmp_lg_u32 s37, s38 s_cbranch_scc0 .LBB5_263 ; %bb.259: ; in Loop: Header=BB5_253 Depth=6 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB5_270 ; %bb.260: ; in Loop: Header=BB5_253 Depth=6 s_cmpk_lt_u32 s37, 0x100 s_cbranch_scc0 .LBB5_264 ; %bb.261: ; in Loop: Header=BB5_253 Depth=6 s_add_u32 s6, s10, 0x2800 s_addc_u32 s7, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[12:13], null, v6, 0x1800, s[6:7] s_mov_b32 s6, 0 v_mad_u64_u32 v[10:11], null, s37, 24, v[12:13] s_branch .LBB5_265 .LBB5_262: ; in Loop: Header=BB5_253 Depth=6 s_mov_b64 s[2:3], 0 s_mov_b32 s20, -1 s_mov_b32 s18, 0 s_mov_b32 s19, -1 ; implicit-def: $sgpr37 ; implicit-def: $sgpr38 ; implicit-def: $sgpr6_sgpr7 s_branch .LBB5_275 .LBB5_263: ; in Loop: Header=BB5_253 Depth=6 s_mov_b32 s18, -1 s_mov_b32 s19, -1 ; implicit-def: $sgpr37 ; implicit-def: $sgpr38 ; implicit-def: $sgpr6_sgpr7 s_branch .LBB5_274 .LBB5_264: ; in Loop: Header=BB5_253 Depth=6 s_mov_b32 s6, -1 ; implicit-def: $vgpr10_vgpr11 .LBB5_265: ; %Flow846 ; in Loop: Header=BB5_253 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_267 ; %bb.266: ; in Loop: Header=BB5_253 Depth=6 s_add_i32 s6, s37, 0xffffff00 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_lshr_b32 s18, s6, 8 s_add_u32 s6, s10, 0x2800 s_addc_u32 s7, s11, 0 v_mad_u64_u32 v[10:11], null, v6, 0x1800, s[6:7] s_and_b32 s6, s37, 0xff s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[12:13], null, s18, 24, v[10:11] global_load_b64 v[12:13], v[12:13], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[10:11], null, s6, 24, v[12:13] .LBB5_267: ; in Loop: Header=BB5_253 Depth=6 v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v13, s17 v_mov_b32_e32 v86, s37 s_delay_alu instid0(VALU_DEP_2) v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v15, v14 global_store_b32 v16, v86, s[16:17] offset:4 global_atomic_cmpswap_b64 v[12:13], v[10:11], v[12:15], off offset:8 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13] v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_and_saveexec_b32 s6, vcc_lo s_cbranch_execz .LBB5_269 ; %bb.268: ; in Loop: Header=BB5_253 Depth=6 s_waitcnt_vscnt null, 0x0 global_atomic_add_u32 v[52:53], v98, off v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10 .LBB5_269: ; %Flow844 ; in Loop: Header=BB5_253 Depth=6 s_or_b32 exec_lo, exec_lo, s6 .LBB5_270: ; %Flow847 ; in Loop: Header=BB5_253 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s3 v_readfirstlane_b32 s6, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s7, v13 s_cmp_lg_u64 s[6:7], 0 s_cbranch_scc0 .LBB5_272 ; %bb.271: ; in Loop: Header=BB5_253 Depth=6 s_mov_b32 s19, -1 ; implicit-def: $sgpr37 ; implicit-def: $sgpr38 s_branch .LBB5_273 .LBB5_272: ; in Loop: Header=BB5_253 Depth=6 s_mov_b32 s19, 0 s_and_not1_b32 s2, s2, exec_lo s_sleep 2 .LBB5_273: ; %Flow852 ; in Loop: Header=BB5_253 Depth=6 s_mov_b32 s18, 0 .LBB5_274: ; %Flow851 ; in Loop: Header=BB5_253 Depth=6 s_and_not1_b32 s3, s5, exec_lo s_and_b32 s2, s2, exec_lo s_mov_b32 s20, 0 s_or_b32 s5, s3, s2 ; implicit-def: $sgpr2_sgpr3 .LBB5_275: ; %Flow850 ; in Loop: Header=BB5_253 Depth=6 s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccz .LBB5_253 ; %bb.276: ; %loop.exit.guard760 ; in Loop: Header=BB5_74 Depth=5 v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2 s_and_b32 vcc_lo, exec_lo, s20 s_cbranch_vccnz .LBB5_196 ; %bb.277: ; %loop.exit.guard761 ; in Loop: Header=BB5_74 Depth=5 s_xor_b32 s2, s18, -1 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s2 s_cbranch_vccz .LBB5_280 ; %bb.278: ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s18, 0 s_branch .LBB5_281 .LBB5_279: ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s18, 0 s_branch .LBB5_196 .LBB5_280: ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s18, -1 ; implicit-def: $sgpr6_sgpr7 .LBB5_281: ; %Flow841 ; in Loop: Header=BB5_74 Depth=5 v_dual_mov_b32 v11, s7 :: v_dual_mov_b32 v10, s6 s_and_not1_b32 vcc_lo, exec_lo, s18 s_cbranch_vccnz .LBB5_196 ; %bb.282: ; in Loop: Header=BB5_74 Depth=5 s_and_saveexec_b32 s3, s5 s_cbranch_execz .LBB5_311 ; %bb.283: ; in Loop: Header=BB5_74 Depth=5 s_load_b64 s[18:19], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s2, v15 v_mov_b32_e32 v86, 0 v_mov_b32_e32 v87, 0 v_cmp_eq_u32_e64 s2, s2, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_289 ; %bb.284: ; in Loop: Header=BB5_74 Depth=5 s_waitcnt lgkmcnt(0) global_load_b64 v[12:13], v16, s[18:19] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[10:11], v16, s[18:19] offset:40 global_load_b64 v[86:87], v16, s[18:19] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v11, v11, v13 v_and_b32_e32 v10, v10, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v11, v11, 24 v_mul_hi_u32 v14, v10, 24 v_mul_lo_u32 v10, v10, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v11, v14, v11 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v86, v10 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v11, vcc_lo, v87, v11, vcc_lo global_load_b64 v[10:11], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[18:19] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[86:87], v[12:13] s_cbranch_execz .LBB5_288 ; %bb.285: ; %.preheader3.i.i.i152.preheader ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s7, 0 .LBB5_286: ; %.preheader3.i.i.i152 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 s_clause 0x1 global_load_b64 v[10:11], v16, s[18:19] offset:40 global_load_b64 v[96:97], v16, s[18:19] v_dual_mov_b32 v12, v86 :: v_dual_mov_b32 v13, v87 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v10, v10, v12 v_and_b32_e32 v11, v11, v13 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[86:87], null, v10, 24, v[96:97] v_mov_b32_e32 v10, v87 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[96:97], null, v11, 24, v[10:11] v_mov_b32_e32 v87, v96 global_load_b64 v[10:11], v[86:87], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[18:19] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[86:87], v[12:13] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_286 ; %bb.287: ; %Flow837 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s7 .LBB5_288: ; %Flow839 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB5_289: ; %.loopexit4.i.i.i147 ; in Loop: Header=BB5_74 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[96:97], v16, s[18:19] offset:40 global_load_b128 v[10:13], v16, s[18:19] v_readfirstlane_b32 s20, v86 v_readfirstlane_b32 s21, v87 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s22, v96 v_readfirstlane_b32 s23, v97 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[22:23], s[20:21], s[22:23] s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_291 ; %bb.290: ; in Loop: Header=BB5_74 Depth=5 v_dual_mov_b32 v112, s6 :: v_dual_mov_b32 v113, 0 s_mul_i32 s6, s23, 24 s_mul_hi_u32 s7, s22, 24 v_dual_mov_b32 v114, 3 :: v_dual_mov_b32 v115, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s22, 24 s_waitcnt vmcnt(0) v_add_co_u32 v86, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v87, vcc_lo, s7, v11, vcc_lo global_store_b128 v[86:87], v[112:115], off offset:8 .LBB5_291: ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[22:23], 12 v_lshlrev_b64 v[14:15], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v12, vcc_lo, v12, s6 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo s_mov_b32 s7, s4 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v86, vcc_lo, v12, v14 s_mov_b32 s5, s4 s_mov_b32 s6, s4 v_dual_mov_b32 v96, 0 :: v_dual_mov_b32 v113, s17 v_add_co_ci_u32_e32 v87, vcc_lo, v13, v15, vcc_lo v_dual_mov_b32 v112, s16 :: v_dual_mov_b32 v15, s7 v_dual_mov_b32 v14, s6 :: v_dual_mov_b32 v13, s5 s_delay_alu instid0(VALU_DEP_4) v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v97, v96 s_clause 0x4 global_store_b64 v[86:87], v[112:113], off global_store_b128 v[86:87], v[12:15], off offset:8 global_store_b128 v[86:87], v[12:15], off offset:24 global_store_b128 v[86:87], v[12:15], off offset:40 global_store_b64 v[86:87], v[96:97], off offset:56 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_299 ; %bb.292: ; in Loop: Header=BB5_74 Depth=5 s_clause 0x1 global_load_b64 v[114:115], v16, s[18:19] offset:32 glc global_load_b64 v[12:13], v16, s[18:19] offset:40 v_dual_mov_b32 v112, s20 :: v_dual_mov_b32 v113, s21 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v12 v_readfirstlane_b32 s7, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[20:21] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s16, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s16, s16, s7 v_add_co_u32 v86, vcc_lo, v10, s6 v_add_co_ci_u32_e32 v87, vcc_lo, s16, v11, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[86:87], v[114:115], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v16, v[112:115], s[18:19] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[14:15], v[114:115] s_cbranch_execz .LBB5_295 ; %bb.293: ; %.preheader1.i.i.i150.preheader ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s7, 0 .LBB5_294: ; %.preheader1.i.i.i150 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_dual_mov_b32 v12, s20 :: v_dual_mov_b32 v13, s21 s_sleep 1 global_store_b64 v[86:87], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[12:15], s[18:19] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15] v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_294 .LBB5_295: ; %Flow835 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[12:13], v16, s[18:19] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v14, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v14 s_cbranch_execz .LBB5_297 ; %bb.296: ; in Loop: Header=BB5_74 Depth=5 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v14, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[12:13], v[14:15], off offset:8 .LBB5_297: ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[86:87], v[12:13], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[86:87] s_cbranch_vccnz .LBB5_299 ; %bb.298: ; in Loop: Header=BB5_74 Depth=5 global_load_b32 v15, v[12:13], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[86:87], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB5_299: ; %Flow836 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s23, 24 s_mul_hi_u32 s6, s22, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s22, 24 v_add_co_u32 v10, vcc_lo, v10, s5 v_add_co_ci_u32_e32 v11, vcc_lo, s6, v11, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v10, 20 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo .LBB5_300: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 v_mov_b32_e32 v12, 1 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_302 ; %bb.301: ; in Loop: Header=BB5_300 Depth=6 global_load_b32 v12, v[10:11], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v12, 1, v12 .LBB5_302: ; in Loop: Header=BB5_300 Depth=6 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v12 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB5_304 ; %bb.303: ; in Loop: Header=BB5_300 Depth=6 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB5_305 .LBB5_304: ; in Loop: Header=BB5_300 Depth=6 s_mov_b32 s5, -1 .LBB5_305: ; %Flow830 ; in Loop: Header=BB5_300 Depth=6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB5_300 ; %bb.306: ; in Loop: Header=BB5_74 Depth=5 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_310 ; %bb.307: ; in Loop: Header=BB5_74 Depth=5 s_clause 0x2 global_load_b64 v[12:13], v16, s[18:19] offset:40 global_load_b64 v[86:87], v16, s[18:19] offset:24 glc global_load_b64 v[14:15], v16, s[18:19] s_waitcnt vmcnt(2) v_add_co_u32 v96, vcc_lo, v12, 1 v_add_co_ci_u32_e32 v97, vcc_lo, 0, v13, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v96, s20 v_add_co_ci_u32_e32 v11, vcc_lo, s21, v97, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] v_dual_cndmask_b32 v11, v11, v97 :: v_dual_cndmask_b32 v10, v10, v96 v_and_b32_e32 v13, v11, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v12, v10, v12 v_mul_hi_u32 v96, v12, 24 v_mul_lo_u32 v12, v12, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v14, vcc_lo, v14, v12 v_mov_b32_e32 v12, v86 v_mul_lo_u32 v13, v13, 24 v_add_nc_u32_e32 v13, v96, v13 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v15, vcc_lo, v15, v13, vcc_lo v_mov_b32_e32 v13, v87 global_store_b64 v[14:15], v[86:87], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v16, v[10:13], s[18:19] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[86:87] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_310 ; %bb.308: ; %.preheader.i.i.i149.preheader ; in Loop: Header=BB5_74 Depth=5 s_mov_b32 s2, 0 .LBB5_309: ; %.preheader.i.i.i149 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; Parent Loop BB5_74 Depth=5 ; => This Inner Loop Header: Depth=6 s_sleep 1 global_store_b64 v[14:15], v[12:13], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[86:87], v16, v[10:13], s[18:19] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[86:87], v[12:13] v_dual_mov_b32 v12, v86 :: v_dual_mov_b32 v13, v87 s_or_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB5_309 .LBB5_310: ; %Flow828 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s5 v_mov_b32_e32 v103, 0 .LBB5_311: ; %Flow840 ; in Loop: Header=BB5_74 Depth=5 s_or_b32 exec_lo, exec_lo, s3 v_dual_mov_b32 v10, v84 :: v_dual_mov_b32 v11, v85 s_mov_b32 s18, -1 s_branch .LBB5_196 .LBB5_312: ; in Loop: Header=BB5_43 Depth=4 ; implicit-def: $vgpr82_vgpr83 ; implicit-def: $sgpr36 ; implicit-def: $vgpr102 s_branch .LBB5_336 .LBB5_313: ; in Loop: Header=BB5_43 Depth=4 v_cmp_ne_u64_e64 s5, 1, v[84:85] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s5 s_cbranch_vccz .LBB5_315 ; %bb.314: ; in Loop: Header=BB5_43 Depth=4 v_dual_mov_b32 v82, v84 :: v_dual_mov_b32 v83, v85 s_branch .LBB5_335 .LBB5_315: ; in Loop: Header=BB5_43 Depth=4 v_mbcnt_lo_u32_b32 v10, exec_lo, 0 s_mov_b32 s16, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB5_332 ; %bb.316: ; in Loop: Header=BB5_43 Depth=4 global_load_b64 v[10:11], v[66:67], off glc s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v10, vcc_lo, s2, v10 v_sub_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_u64_e32 vcc_lo, 0x4e20, v[10:11] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_332 ; %bb.317: ; in Loop: Header=BB5_43 Depth=4 v_sub_nc_u32_e32 v10, 0x4e20, v10 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) v_readfirstlane_b32 s2, v10 s_delay_alu instid0(VALU_DEP_1) s_ashr_i32 s3, s2, 31 s_waitcnt lgkmcnt(0) s_add_u32 s2, s6, s2 s_addc_u32 s3, s7, s3 .LBB5_318: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x659 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccnz .LBB5_321 ; %bb.319: ; %.preheader11.i166 ; in Loop: Header=BB5_318 Depth=5 s_sleep 0x7f s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_branch .LBB5_318 .LBB5_320: ; %.preheader9.i165 ; in Loop: Header=BB5_321 Depth=5 s_sleep 63 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_321: ; %Flow822 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x326 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccz .LBB5_320 ; %bb.322: ; %Flow819 ; in Loop: Header=BB5_43 Depth=4 s_add_u32 s18, s6, 0x18c s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccnz .LBB5_325 .LBB5_323: ; %.preheader7.i164 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 31 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x18c s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccnz .LBB5_323 s_branch .LBB5_325 .LBB5_324: ; %.preheader5.i163 ; in Loop: Header=BB5_325 Depth=5 s_sleep 15 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_325: ; %.loopexit8.i156 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0xc0 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccz .LBB5_324 s_branch .LBB5_327 .LBB5_326: ; %.preheader3.i162 ; in Loop: Header=BB5_327 Depth=5 s_sleep 7 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_327: ; %Flow813 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x59 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccz .LBB5_326 s_branch .LBB5_329 .LBB5_328: ; %.preheader1.i161 ; in Loop: Header=BB5_329 Depth=5 s_sleep 3 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_329: ; %Flow810 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 38 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s17, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s17 s_cbranch_vccz .LBB5_328 ; %bb.330: ; %Flow807 ; in Loop: Header=BB5_43 Depth=4 v_cmp_le_u64_e64 s6, s[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_332 .LBB5_331: ; %.preheader.i160 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_11 Depth=3 ; Parent Loop BB5_43 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) v_cmp_gt_u64_e64 s6, s[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_331 .LBB5_332: ; %__ockl_rtcwait_u32.exit167 ; in Loop: Header=BB5_43 Depth=4 s_or_b32 exec_lo, exec_lo, s16 v_mov_b32_e32 v10, s36 s_mov_b32 s2, exec_lo v_cmpx_eq_u32_e32 0, v102 s_cbranch_execz .LBB5_334 ; %bb.333: ; in Loop: Header=BB5_43 Depth=4 global_load_b32 v10, v[52:53], off glc .LBB5_334: ; in Loop: Header=BB5_43 Depth=4 s_or_b32 exec_lo, exec_lo, s2 s_waitcnt vmcnt(0) v_readfirstlane_b32 s36, v10 .LBB5_335: ; in Loop: Header=BB5_43 Depth=4 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v10, v82 :: v_dual_mov_b32 v11, v83 s_mov_b32 s6, 0 .LBB5_336: ; %Flow969 ; in Loop: Header=BB5_43 Depth=4 s_and_b32 vcc_lo, exec_lo, s5 s_cbranch_vccz .LBB5_43 ; %bb.337: ; %Flow970 ; in Loop: Header=BB5_11 Depth=3 v_mov_b32_e32 v6, v2 .LBB5_338: ; %Flow971 ; in Loop: Header=BB5_11 Depth=3 v_dual_mov_b32 v7, v10 :: v_dual_mov_b32 v8, v11 s_delay_alu instid0(VALU_DEP_2) v_mov_b32_e32 v15, v6 s_and_b32 s3, s6, exec_lo .LBB5_339: ; %Flow973 ; in Loop: Header=BB5_11 Depth=3 s_or_b32 exec_lo, exec_lo, s34 .LBB5_340: ; %.loopexit187 ; in Loop: Header=BB5_11 Depth=3 s_xor_b32 s1, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s1, exec_lo, s1 s_or_b32 s30, s1, s30 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s30 s_cbranch_execnz .LBB5_11 ; %bb.341: ; %Flow986 ; in Loop: Header=BB5_6 Depth=2 s_or_b32 exec_lo, exec_lo, s30 s_mov_b32 s1, 0 s_branch .LBB5_343 .LBB5_342: ; in Loop: Header=BB5_6 Depth=2 s_mov_b32 s1, -1 ; implicit-def: $vgpr7_vgpr8 .LBB5_343: ; %Flow1168 ; in Loop: Header=BB5_6 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s1 s_cbranch_vccz .LBB5_640 ; %bb.344: ; in Loop: Header=BB5_6 Depth=2 v_mbcnt_lo_u32_b32 v50, exec_lo, 0 s_bcnt1_i32_b32 s30, exec_lo ; implicit-def: $vgpr12_vgpr13 .LBB5_345: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; => This Loop Header: Depth=3 ; Child Loop BB5_349 Depth 4 ; Child Loop BB5_377 Depth 4 ; Child Loop BB5_395 Depth 5 ; Child Loop BB5_403 Depth 5 ; Child Loop BB5_409 Depth 5 ; Child Loop BB5_418 Depth 5 ; Child Loop BB5_423 Depth 5 ; Child Loop BB5_425 Depth 5 ; Child Loop BB5_445 Depth 5 ; Child Loop BB5_453 Depth 5 ; Child Loop BB5_459 Depth 5 ; Child Loop BB5_468 Depth 5 ; Child Loop BB5_476 Depth 5 ; Child Loop BB5_479 Depth 5 ; Child Loop BB5_481 Depth 5 ; Child Loop BB5_483 Depth 5 ; Child Loop BB5_485 Depth 5 ; Child Loop BB5_487 Depth 5 ; Child Loop BB5_489 Depth 5 ; Child Loop BB5_511 Depth 5 ; Child Loop BB5_519 Depth 5 ; Child Loop BB5_525 Depth 5 ; Child Loop BB5_534 Depth 5 ; Child Loop BB5_541 Depth 5 ; Child Loop BB5_544 Depth 5 ; Child Loop BB5_549 Depth 5 ; Child Loop BB5_556 Depth 5 ; Child Loop BB5_589 Depth 5 ; Child Loop BB5_597 Depth 5 ; Child Loop BB5_603 Depth 5 ; Child Loop BB5_612 Depth 5 ; Child Loop BB5_621 Depth 4 ; Child Loop BB5_624 Depth 4 ; Child Loop BB5_626 Depth 4 ; Child Loop BB5_628 Depth 4 ; Child Loop BB5_630 Depth 4 ; Child Loop BB5_632 Depth 4 ; Child Loop BB5_634 Depth 4 s_delay_alu instid0(VALU_DEP_2) s_cmp_eq_u32 s29, 0 s_mov_b32 s5, -1 ;;#ASMSTART ;;#ASMEND s_cbranch_scc1 .LBB5_374 ; %bb.346: ; in Loop: Header=BB5_345 Depth=3 v_cmp_eq_u32_e64 s1, 0, v50 v_mov_b32_e32 v6, 0 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB5_348 ; %bb.347: ; in Loop: Header=BB5_345 Depth=3 global_load_b32 v6, v[19:20], off glc .LBB5_348: ; in Loop: Header=BB5_345 Depth=3 s_or_b32 exec_lo, exec_lo, s2 global_load_b32 v9, v[21:22], off v_cvt_f32_u32_e32 v7, s29 s_sub_i32 s2, 0, s29 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v7, v7 s_waitcnt_depctr 0xfff v_mul_f32_e32 v7, 0x4f7ffffe, v7 v_cvt_u32_f32_e32 v7, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mul_lo_u32 v8, s2, v7 s_waitcnt vmcnt(1) v_readfirstlane_b32 s2, v6 v_add_nc_u32_e32 v6, s2, v50 s_mov_b32 s2, s29 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v8, v7, v8 v_add_nc_u32_e32 v10, v7, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v7, v6, v10 v_mul_lo_u32 v7, v7, s29 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v6, v6, v7 v_subrev_nc_u32_e32 v7, s29, v6 v_cmp_le_u32_e32 vcc_lo, s29, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v6, v6, v7, vcc_lo v_subrev_nc_u32_e32 v7, s29, v6 v_cmp_le_u32_e32 vcc_lo, s29, v6 s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e32 v11, v6, v7, vcc_lo .LBB5_349: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_mov_b32 s3, exec_lo ; implicit-def: $vgpr6_vgpr7 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_u32_e32 0x100, v11 s_xor_b32 s3, exec_lo, s3 ; %bb.350: ; in Loop: Header=BB5_349 Depth=4 s_add_u32 s6, s10, 0x2800 s_addc_u32 s7, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[14:15], null, v2, 0x1800, s[6:7] v_mad_u64_u32 v[6:7], null, v11, 24, v[14:15] ; %bb.351: ; %Flow995 ; in Loop: Header=BB5_349 Depth=4 s_and_not1_saveexec_b32 s3, s3 s_cbranch_execz .LBB5_353 ; %bb.352: ; in Loop: Header=BB5_349 Depth=4 s_add_u32 s6, s10, 0x2800 v_add_nc_u32_e32 v8, 0xffffff00, v11 s_addc_u32 s7, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[6:7], null, v2, 0x1800, s[6:7] v_lshrrev_b32_e32 v8, 8, v8 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[14:15], null, v8, 24, v[6:7] v_and_b32_e32 v8, 0xff, v11 global_load_b64 v[14:15], v[14:15], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[6:7], null, v8, 24, v[14:15] .LBB5_353: ; in Loop: Header=BB5_349 Depth=4 s_or_b32 exec_lo, exec_lo, s3 global_load_b32 v6, v[6:7], off offset:16 glc s_waitcnt vmcnt(0) v_cmp_lt_u32_e32 vcc_lo, v6, v9 s_cbranch_vccz .LBB5_355 ; %bb.354: ; in Loop: Header=BB5_349 Depth=4 s_ctz_i32_b32 s3, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b32 s3, s3, 2 v_mov_b32_e32 v6, s3 ds_bpermute_b32 v6, v6, v11 s_branch .LBB5_356 .LBB5_355: ; in Loop: Header=BB5_349 Depth=4 v_mov_b32_e32 v6, -1 .LBB5_356: ; in Loop: Header=BB5_349 Depth=4 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s6, v6 s_cmp_eq_u32 s6, -1 s_cselect_b32 s3, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s3 s_cbranch_vccnz .LBB5_359 ; %bb.357: ; in Loop: Header=BB5_349 Depth=4 s_cmpk_lt_u32 s6, 0x100 s_cbranch_scc0 .LBB5_360 ; %bb.358: ; in Loop: Header=BB5_349 Depth=4 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_mov_b32 s7, 0 v_mad_u64_u32 v[14:15], null, v2, 0x1800, s[16:17] s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[7:8], null, s6, 24, v[14:15] s_branch .LBB5_361 .LBB5_359: ; in Loop: Header=BB5_349 Depth=4 s_mov_b32 s6, -1 ; implicit-def: $vgpr7_vgpr8 s_branch .LBB5_364 .LBB5_360: ; in Loop: Header=BB5_349 Depth=4 s_mov_b32 s7, -1 ; implicit-def: $vgpr7_vgpr8 .LBB5_361: ; %Flow988 ; in Loop: Header=BB5_349 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s7 s_cbranch_vccnz .LBB5_363 ; %bb.362: ; in Loop: Header=BB5_349 Depth=4 s_add_i32 s7, s6, 0xffffff00 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) s_lshr_b32 s7, s7, 8 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_and_b32 s6, s6, 0xff v_mad_u64_u32 v[6:7], null, v2, 0x1800, s[16:17] v_mad_u64_u32 v[14:15], null, s7, 24, v[6:7] global_load_b64 v[14:15], v[14:15], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[7:8], null, s6, 24, v[14:15] .LBB5_363: ; %Flow989 ; in Loop: Header=BB5_349 Depth=4 s_mov_b32 s6, 0 .LBB5_364: ; %Flow991 ; in Loop: Header=BB5_349 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_368 ; %bb.365: ; in Loop: Header=BB5_349 Depth=4 v_add_nc_u32_e32 v6, s30, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v7, v6, v10 v_mul_lo_u32 v7, v7, s29 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v6, v6, v7 v_subrev_nc_u32_e32 v7, s29, v6 v_cmp_le_u32_e32 vcc_lo, s29, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v6, v6, v7, vcc_lo v_subrev_nc_u32_e32 v7, s29, v6 v_cmp_le_u32_e32 vcc_lo, s29, v6 s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e32 v11, v6, v7, vcc_lo s_and_saveexec_b32 s6, s1 s_cbranch_execz .LBB5_367 ; %bb.366: ; in Loop: Header=BB5_349 Depth=4 global_store_b32 v[19:20], v11, off .LBB5_367: ; in Loop: Header=BB5_349 Depth=4 s_or_b32 exec_lo, exec_lo, s6 v_dual_mov_b32 v7, v12 :: v_dual_mov_b32 v8, v13 s_sub_i32 s2, s2, s30 .LBB5_368: ; in Loop: Header=BB5_349 Depth=4 s_and_not1_b32 vcc_lo, exec_lo, s3 s_cbranch_vccz .LBB5_370 ; %bb.369: ; in Loop: Header=BB5_349 Depth=4 s_mov_b32 s3, -1 s_mov_b32 s6, -1 ; implicit-def: $sgpr2 ; implicit-def: $vgpr11 s_branch .LBB5_371 .LBB5_370: ; in Loop: Header=BB5_349 Depth=4 s_cmp_lt_i32 s2, 1 s_mov_b32 s3, 0 s_cselect_b32 s6, -1, 0 .LBB5_371: ; %Flow997 ; in Loop: Header=BB5_349 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccz .LBB5_373 ; %bb.372: ; in Loop: Header=BB5_349 Depth=4 v_dual_mov_b32 v13, v8 :: v_dual_mov_b32 v12, v7 s_branch .LBB5_349 .LBB5_373: ; %loop.exit.guard769 ; in Loop: Header=BB5_345 Depth=3 v_dual_mov_b32 v13, v8 :: v_dual_mov_b32 v12, v7 s_xor_b32 s1, s3, -1 s_branch .LBB5_375 .LBB5_374: ; in Loop: Header=BB5_345 Depth=3 s_mov_b32 s1, -1 ; implicit-def: $vgpr7_vgpr8 .LBB5_375: ; %Flow1164 ; in Loop: Header=BB5_345 Depth=3 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s1 s_cbranch_vccz .LBB5_615 ; %bb.376: ; %.loopexit190 ; in Loop: Header=BB5_345 Depth=3 v_mbcnt_lo_u32_b32 v51, exec_lo, 0 ; implicit-def: $vgpr37_vgpr38 .LBB5_377: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; => This Loop Header: Depth=4 ; Child Loop BB5_395 Depth 5 ; Child Loop BB5_403 Depth 5 ; Child Loop BB5_409 Depth 5 ; Child Loop BB5_418 Depth 5 ; Child Loop BB5_423 Depth 5 ; Child Loop BB5_425 Depth 5 ; Child Loop BB5_445 Depth 5 ; Child Loop BB5_453 Depth 5 ; Child Loop BB5_459 Depth 5 ; Child Loop BB5_468 Depth 5 ; Child Loop BB5_476 Depth 5 ; Child Loop BB5_479 Depth 5 ; Child Loop BB5_481 Depth 5 ; Child Loop BB5_483 Depth 5 ; Child Loop BB5_485 Depth 5 ; Child Loop BB5_487 Depth 5 ; Child Loop BB5_489 Depth 5 ; Child Loop BB5_511 Depth 5 ; Child Loop BB5_519 Depth 5 ; Child Loop BB5_525 Depth 5 ; Child Loop BB5_534 Depth 5 ; Child Loop BB5_541 Depth 5 ; Child Loop BB5_544 Depth 5 ; Child Loop BB5_549 Depth 5 ; Child Loop BB5_556 Depth 5 ; Child Loop BB5_589 Depth 5 ; Child Loop BB5_597 Depth 5 ; Child Loop BB5_603 Depth 5 ; Child Loop BB5_612 Depth 5 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cmp_eq_u32_e64 s1, 0, v51 v_mov_b32_e32 v6, 0 s_mov_b32 s18, 0 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB5_379 ; %bb.378: ; in Loop: Header=BB5_377 Depth=4 global_load_b32 v6, v[17:18], off glc .LBB5_379: ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s2 s_waitcnt vmcnt(0) v_readfirstlane_b32 s31, v6 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_delay_alu instid0(VALU_DEP_3) s_cmp_eq_u32 s31, 0x10100 s_cbranch_scc1 .LBB5_499 ; %bb.380: ; in Loop: Header=BB5_377 Depth=4 v_mov_b32_e32 v6, 0 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB5_382 ; %bb.381: ; in Loop: Header=BB5_377 Depth=4 v_dual_mov_b32 v6, 0x100 :: v_dual_mov_b32 v7, 0 global_atomic_cmpswap_b32 v6, v[25:26], v[6:7], off glc s_waitcnt vmcnt(0) v_cmp_ne_u32_e32 vcc_lo, 0, v6 v_cndmask_b32_e32 v6, 0x100, v6, vcc_lo .LBB5_382: ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s34, v6 s_cmp_lg_u32 s31, s34 s_cbranch_scc1 .LBB5_439 ; %bb.383: ; in Loop: Header=BB5_377 Depth=4 v_mbcnt_lo_u32_b32 v52, exec_lo, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v52 v_mov_b32_e32 v6, 0 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB5_385 ; %bb.384: ; in Loop: Header=BB5_377 Depth=4 global_load_b32 v6, v[25:26], off glc .LBB5_385: ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s2 s_waitcnt vmcnt(0) v_readfirstlane_b32 s22, v6 s_mov_b32 s16, 2 s_delay_alu instid0(VALU_DEP_1) s_cmp_eq_u32 s22, 0x10100 s_cbranch_scc1 .LBB5_472 ; %bb.386: ; in Loop: Header=BB5_377 Depth=4 v_mov_b32_e32 v6, 1 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB5_390 ; %bb.387: ; in Loop: Header=BB5_377 Depth=4 global_load_b64 v[8:9], v[27:28], off glc s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v6, s2, s6, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_co_ci_u32_e64 v7, s2, s7, v9, s2 v_cmp_lt_u64_e64 s2, 0x752f, v[6:7] v_mov_b32_e32 v6, 1 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_389 ; %bb.388: ; in Loop: Header=BB5_377 Depth=4 v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 global_atomic_cmpswap_b64 v[6:7], v[27:28], v[6:9], off glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e64 s2, v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) v_cndmask_b32_e64 v6, 1, 2, s2 .LBB5_389: ; %Flow1153 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 .LBB5_390: ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s3 v_readfirstlane_b32 s3, v6 s_mov_b32 s16, 1 s_delay_alu instid0(VALU_DEP_1) s_cmp_eq_u32 s3, 1 s_cbranch_scc1 .LBB5_472 ; %bb.391: ; in Loop: Header=BB5_377 Depth=4 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_and_saveexec_b32 s23, vcc_lo s_cbranch_execz .LBB5_420 ; %bb.392: ; in Loop: Header=BB5_377 Depth=4 s_load_b64 s[16:17], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s2, v15 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 v_cmp_eq_u32_e64 s2, s2, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_398 ; %bb.393: ; in Loop: Header=BB5_377 Depth=4 s_waitcnt lgkmcnt(0) global_load_b64 v[8:9], v16, s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[6:7], v16, s[16:17] offset:40 global_load_b64 v[10:11], v16, s[16:17] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v7, v7, v9 v_and_b32_e32 v6, v6, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v7, v7, 24 v_mul_hi_u32 v14, v6, 24 v_mul_lo_u32 v6, v6, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, v14, v7 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v10, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, v11, v7, vcc_lo global_load_b64 v[6:7], v[6:7], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[10:11], v[8:9] s_cbranch_execz .LBB5_397 ; %bb.394: ; %.preheader3.i.i.i75.preheader ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s7, 0 .LBB5_395: ; %.preheader3.i.i.i75 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 s_clause 0x1 global_load_b64 v[6:7], v16, s[16:17] offset:40 global_load_b64 v[48:49], v16, s[16:17] v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v6, v6, v8 v_and_b32_e32 v7, v7, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[10:11], null, v6, 24, v[48:49] v_mov_b32_e32 v6, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[48:49], null, v7, 24, v[6:7] v_mov_b32_e32 v11, v48 global_load_b64 v[6:7], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[8:9] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_395 ; %bb.396: ; %Flow1147 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s7 .LBB5_397: ; %Flow1149 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB5_398: ; %.loopexit4.i.i.i70 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[48:49], v16, s[16:17] offset:40 global_load_b128 v[6:9], v16, s[16:17] v_readfirstlane_b32 s18, v10 v_readfirstlane_b32 s19, v11 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s20, v48 v_readfirstlane_b32 s21, v49 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[20:21], s[18:19], s[20:21] s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_400 ; %bb.399: ; in Loop: Header=BB5_377 Depth=4 v_dual_mov_b32 v64, s6 :: v_dual_mov_b32 v65, 0 s_mul_i32 s6, s21, 24 s_mul_hi_u32 s7, s20, 24 v_dual_mov_b32 v66, 3 :: v_dual_mov_b32 v67, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s20, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v7, vcc_lo global_store_b128 v[10:11], v[64:67], off offset:8 .LBB5_400: ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[20:21], 12 v_lshlrev_b64 v[10:11], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v14, vcc_lo, v8, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo s_mov_b32 s5, s4 s_mov_b32 s6, s4 s_mov_b32 s7, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v67, s7 v_add_co_u32 v48, vcc_lo, v14, v10 v_add_co_ci_u32_e32 v49, vcc_lo, v9, v11, vcc_lo v_dual_mov_b32 v10, 0x1800 :: v_dual_mov_b32 v9, v8 v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v66, s6 v_dual_mov_b32 v65, s5 :: v_dual_mov_b32 v64, s4 s_clause 0x3 global_store_b128 v[48:49], v[8:11], off global_store_b128 v[48:49], v[64:67], off offset:16 global_store_b128 v[48:49], v[64:67], off offset:32 global_store_b128 v[48:49], v[64:67], off offset:48 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_408 ; %bb.401: ; in Loop: Header=BB5_377 Depth=4 s_clause 0x1 global_load_b64 v[66:67], v16, s[16:17] offset:32 glc global_load_b64 v[8:9], v16, s[16:17] offset:40 v_dual_mov_b32 v64, s18 :: v_dual_mov_b32 v65, s19 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[18:19] s_mul_i32 s7, s7, 24 s_mul_hi_u32 vcc_lo, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s7, vcc_lo, s7 v_add_co_u32 v14, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v15, vcc_lo, s7, v7, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[14:15], v[66:67], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v16, v[64:67], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[10:11], v[66:67] s_cbranch_execz .LBB5_404 ; %bb.402: ; %.preheader1.i.i.i73.preheader ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s7, 0 .LBB5_403: ; %.preheader1.i.i.i73 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_dual_mov_b32 v8, s18 :: v_dual_mov_b32 v9, s19 s_sleep 1 global_store_b64 v[14:15], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[8:11], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11] v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_403 .LBB5_404: ; %Flow1145 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[8:9], v16, s[16:17] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v10, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB5_406 ; %bb.405: ; in Loop: Header=BB5_377 Depth=4 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[8:9], v[10:11], off offset:8 .LBB5_406: ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[10:11], v[8:9], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] s_cbranch_vccnz .LBB5_408 ; %bb.407: ; in Loop: Header=BB5_377 Depth=4 global_load_b32 v15, v[8:9], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[10:11], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB5_408: ; %Flow1146 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s21, 24 s_mul_hi_u32 s6, s20, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s20, 24 v_add_co_u32 v6, vcc_lo, v6, s5 v_add_co_ci_u32_e32 v7, vcc_lo, s6, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v6, 20 v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo .LBB5_409: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_mov_b32_e32 v8, 1 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_411 ; %bb.410: ; in Loop: Header=BB5_409 Depth=5 global_load_b32 v8, v[6:7], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v8, 1, v8 .LBB5_411: ; in Loop: Header=BB5_409 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v8 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB5_413 ; %bb.412: ; in Loop: Header=BB5_409 Depth=5 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB5_414 .LBB5_413: ; in Loop: Header=BB5_409 Depth=5 s_mov_b32 s5, -1 .LBB5_414: ; %Flow1140 ; in Loop: Header=BB5_409 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB5_409 ; %bb.415: ; in Loop: Header=BB5_377 Depth=4 global_load_b64 v[10:11], v[48:49], off s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_419 ; %bb.416: ; in Loop: Header=BB5_377 Depth=4 s_clause 0x2 global_load_b64 v[8:9], v16, s[16:17] offset:40 global_load_b64 v[48:49], v16, s[16:17] offset:24 glc global_load_b64 v[14:15], v16, s[16:17] s_waitcnt vmcnt(2) v_add_co_u32 v53, vcc_lo, v8, 1 v_add_co_ci_u32_e32 v54, vcc_lo, 0, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v53, s18 v_add_co_ci_u32_e32 v7, vcc_lo, s19, v54, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7] v_dual_cndmask_b32 v7, v7, v54 :: v_dual_cndmask_b32 v6, v6, v53 v_and_b32_e32 v9, v7, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v8, v6, v8 v_mul_hi_u32 v53, v8, 24 v_mul_lo_u32 v8, v8, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v14, vcc_lo, v14, v8 v_mov_b32_e32 v8, v48 v_mul_lo_u32 v9, v9, 24 v_add_nc_u32_e32 v9, v53, v9 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v15, vcc_lo, v15, v9, vcc_lo v_mov_b32_e32 v9, v49 global_store_b64 v[14:15], v[48:49], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[8:9], v[48:49] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_419 ; %bb.417: ; %.preheader.i.i.i72.preheader ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s2, 0 .LBB5_418: ; %.preheader.i.i.i72 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 global_store_b64 v[14:15], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[48:49], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[48:49], v[8:9] v_dual_mov_b32 v8, v48 :: v_dual_mov_b32 v9, v49 s_or_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB5_418 .LBB5_419: ; %Flow1138 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 .LBB5_420: ; %Flow1150 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s23 s_waitcnt vmcnt(0) v_readfirstlane_b32 s18, v10 v_readfirstlane_b32 s19, v11 s_cmp_eq_u64 s[18:19], 0 s_cbranch_scc1 .LBB5_471 ; %bb.421: ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s2, exec_lo s_mov_b32 s5, exec_lo v_mbcnt_lo_u32_b32 v8, s2, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_u32_e32 0x300, v8 s_cbranch_execz .LBB5_424 ; %bb.422: ; %.preheader185.preheader ; in Loop: Header=BB5_377 Depth=4 v_lshlrev_b32_e32 v6, 3, v8 s_bcnt1_i32_b32 s6, s2 s_mov_b32 s16, s4 s_lshl_b32 s7, s6, 3 s_mov_b32 s17, 0 v_add_co_u32 v6, s2, s18, v6 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v7, null, s19, 0, s2 .LBB5_423: ; %.preheader185 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, s6, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mov_b32_e32 v10, v9 v_cmp_lt_u32_e32 vcc_lo, 0x2ff, v8 global_store_b64 v[6:7], v[9:10], off v_add_co_u32 v6, s2, v6, s7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e64 v7, s2, s16, v7, s2 s_or_b32 s17, vcc_lo, s17 s_and_not1_b32 exec_lo, exec_lo, s17 s_cbranch_execnz .LBB5_423 .LBB5_424: ; %Flow1132 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 ; implicit-def: $sgpr5 .LBB5_425: ; %.loopexit186 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 ;;#ASMSTART ;;#ASMEND v_cmp_eq_u32_e32 vcc_lo, 0, v52 v_mov_b32_e32 v6, s22 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB5_427 ; %bb.426: ; in Loop: Header=BB5_425 Depth=5 global_load_b32 v6, v[25:26], off glc .LBB5_427: ; in Loop: Header=BB5_425 Depth=5 s_or_b32 exec_lo, exec_lo, s2 s_waitcnt vmcnt(0) v_readfirstlane_b32 s22, v6 s_and_not1_b32 s2, s5, exec_lo s_and_b32 s5, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 s5, s2, s5 s_cmp_lg_u32 s22, 0x10100 s_cbranch_scc0 .LBB5_434 ; %bb.428: ; in Loop: Header=BB5_425 Depth=5 v_mov_b32_e32 v6, s3 s_and_saveexec_b32 s6, vcc_lo s_cbranch_execz .LBB5_432 ; %bb.429: ; in Loop: Header=BB5_425 Depth=5 s_add_i32 s2, s22, 0xffffff00 v_mov_b32_e32 v8, 0 s_lshr_b32 s2, s2, 8 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, v2, 0x1800, s[16:17] v_mad_u64_u32 v[10:11], null, s2, 24, v[6:7] v_dual_mov_b32 v7, s19 :: v_dual_mov_b32 v6, s18 v_mov_b32_e32 v9, v8 global_atomic_cmpswap_b64 v[6:7], v[10:11], v[6:9], off glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e64 s2, 0, v[6:7] v_mov_b32_e32 v6, s3 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s7, s2 s_cbranch_execz .LBB5_431 ; %bb.430: ; in Loop: Header=BB5_425 Depth=5 s_waitcnt_vscnt null, 0x0 global_atomic_add_u32 v[25:26], v39, off v_mov_b32_e32 v6, 0 .LBB5_431: ; %Flow1125 ; in Loop: Header=BB5_425 Depth=5 s_or_b32 exec_lo, exec_lo, s7 .LBB5_432: ; in Loop: Header=BB5_425 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s6 v_readfirstlane_b32 s2, v6 s_delay_alu instid0(VALU_DEP_1) s_cmp_eq_u32 s2, 0 s_cbranch_scc1 .LBB5_435 ; %bb.433: ; in Loop: Header=BB5_425 Depth=5 s_mov_b32 s6, 0 s_and_not1_b32 vcc_lo, vcc_lo, exec_lo s_sleep 2 ; implicit-def: $sgpr3 s_branch .LBB5_436 .LBB5_434: ; in Loop: Header=BB5_425 Depth=5 s_mov_b32 s16, -1 s_mov_b32 s6, -1 ; implicit-def: $vgpr52 ; implicit-def: $sgpr22 ; implicit-def: $sgpr2 ; implicit-def: $sgpr7 s_branch .LBB5_437 .LBB5_435: ; in Loop: Header=BB5_425 Depth=5 s_mov_b32 s6, -1 ; implicit-def: $vgpr52 ; implicit-def: $sgpr22 ; implicit-def: $sgpr2 .LBB5_436: ; %Flow1129 ; in Loop: Header=BB5_425 Depth=5 s_and_not1_b32 s5, s5, exec_lo s_and_b32 s17, vcc_lo, exec_lo s_mov_b32 s7, 0 s_mov_b32 s16, 0 s_or_b32 s5, s5, s17 .LBB5_437: ; %Flow1128 ; in Loop: Header=BB5_425 Depth=5 s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_440 ; %bb.438: ; in Loop: Header=BB5_425 Depth=5 s_mov_b32 s3, s2 s_branch .LBB5_425 .LBB5_439: ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s5, -1 ; implicit-def: $sgpr18 s_branch .LBB5_492 .LBB5_440: ; %loop.exit.guard772 ; in Loop: Header=BB5_377 Depth=4 s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccz .LBB5_470 ; %bb.441: ; in Loop: Header=BB5_377 Depth=4 s_and_saveexec_b32 s35, s5 s_cbranch_execz .LBB5_469 ; %bb.442: ; in Loop: Header=BB5_377 Depth=4 s_load_b64 s[16:17], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s2, v15 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 v_cmp_eq_u32_e64 s2, s2, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_448 ; %bb.443: ; in Loop: Header=BB5_377 Depth=4 s_waitcnt lgkmcnt(0) global_load_b64 v[8:9], v16, s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[6:7], v16, s[16:17] offset:40 global_load_b64 v[10:11], v16, s[16:17] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v7, v7, v9 v_and_b32_e32 v6, v6, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v7, v7, 24 v_mul_hi_u32 v14, v6, 24 v_mul_lo_u32 v6, v6, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, v14, v7 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v10, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, v11, v7, vcc_lo global_load_b64 v[6:7], v[6:7], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[10:11], v[8:9] s_cbranch_execz .LBB5_447 ; %bb.444: ; %.preheader3.i.i.i82.preheader ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s7, 0 .LBB5_445: ; %.preheader3.i.i.i82 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 s_clause 0x1 global_load_b64 v[6:7], v16, s[16:17] offset:40 global_load_b64 v[48:49], v16, s[16:17] v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v6, v6, v8 v_and_b32_e32 v7, v7, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[10:11], null, v6, 24, v[48:49] v_mov_b32_e32 v6, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[48:49], null, v7, 24, v[6:7] v_mov_b32_e32 v11, v48 global_load_b64 v[6:7], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[8:9] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_445 ; %bb.446: ; %Flow1120 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s7 .LBB5_447: ; %Flow1122 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB5_448: ; %.loopexit4.i.i.i77 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[48:49], v16, s[16:17] offset:40 global_load_b128 v[6:9], v16, s[16:17] v_readfirstlane_b32 s20, v10 v_readfirstlane_b32 s21, v11 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s22, v48 v_readfirstlane_b32 s23, v49 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[22:23], s[20:21], s[22:23] s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_450 ; %bb.449: ; in Loop: Header=BB5_377 Depth=4 v_dual_mov_b32 v52, s6 :: v_dual_mov_b32 v53, 0 s_mul_i32 s6, s23, 24 s_mul_hi_u32 s7, s22, 24 v_dual_mov_b32 v54, 3 :: v_dual_mov_b32 v55, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s22, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v7, vcc_lo global_store_b128 v[10:11], v[52:55], off offset:8 .LBB5_450: ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[22:23], 12 v_lshlrev_b64 v[10:11], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v8, vcc_lo, v8, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo s_mov_b32 s7, s4 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v14, vcc_lo, v8, v10 s_mov_b32 s5, s4 s_mov_b32 s6, s4 v_dual_mov_b32 v48, 0 :: v_dual_mov_b32 v53, s19 v_add_co_ci_u32_e32 v15, vcc_lo, v9, v11, vcc_lo v_dual_mov_b32 v52, s18 :: v_dual_mov_b32 v11, s7 v_dual_mov_b32 v10, s6 :: v_dual_mov_b32 v9, s5 s_delay_alu instid0(VALU_DEP_4) v_dual_mov_b32 v8, s4 :: v_dual_mov_b32 v49, v48 s_clause 0x4 global_store_b64 v[14:15], v[52:53], off global_store_b128 v[14:15], v[8:11], off offset:8 global_store_b128 v[14:15], v[8:11], off offset:24 global_store_b128 v[14:15], v[8:11], off offset:40 global_store_b64 v[14:15], v[48:49], off offset:56 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_458 ; %bb.451: ; in Loop: Header=BB5_377 Depth=4 s_clause 0x1 global_load_b64 v[54:55], v16, s[16:17] offset:32 glc global_load_b64 v[8:9], v16, s[16:17] offset:40 v_dual_mov_b32 v52, s20 :: v_dual_mov_b32 v53, s21 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[20:21] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s18, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s18, s18, s7 v_add_co_u32 v14, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v15, vcc_lo, s18, v7, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[14:15], v[54:55], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v16, v[52:55], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[10:11], v[54:55] s_cbranch_execz .LBB5_454 ; %bb.452: ; %.preheader1.i.i.i80.preheader ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s7, 0 .LBB5_453: ; %.preheader1.i.i.i80 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 s_sleep 1 global_store_b64 v[14:15], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[8:11], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11] v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_453 .LBB5_454: ; %Flow1118 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[8:9], v16, s[16:17] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v10, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB5_456 ; %bb.455: ; in Loop: Header=BB5_377 Depth=4 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[8:9], v[10:11], off offset:8 .LBB5_456: ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[10:11], v[8:9], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] s_cbranch_vccnz .LBB5_458 ; %bb.457: ; in Loop: Header=BB5_377 Depth=4 global_load_b32 v15, v[8:9], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[10:11], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB5_458: ; %Flow1119 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s23, 24 s_mul_hi_u32 s6, s22, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s22, 24 v_add_co_u32 v6, vcc_lo, v6, s5 v_add_co_ci_u32_e32 v7, vcc_lo, s6, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v6, 20 v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo .LBB5_459: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_mov_b32_e32 v8, 1 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB5_461 ; %bb.460: ; in Loop: Header=BB5_459 Depth=5 global_load_b32 v8, v[6:7], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v8, 1, v8 .LBB5_461: ; in Loop: Header=BB5_459 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v8 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB5_463 ; %bb.462: ; in Loop: Header=BB5_459 Depth=5 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB5_464 .LBB5_463: ; in Loop: Header=BB5_459 Depth=5 s_mov_b32 s5, -1 .LBB5_464: ; %Flow1113 ; in Loop: Header=BB5_459 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB5_459 ; %bb.465: ; in Loop: Header=BB5_377 Depth=4 s_and_b32 exec_lo, exec_lo, s2 s_cbranch_execz .LBB5_469 ; %bb.466: ; in Loop: Header=BB5_377 Depth=4 s_clause 0x2 global_load_b64 v[8:9], v16, s[16:17] offset:40 global_load_b64 v[14:15], v16, s[16:17] offset:24 glc global_load_b64 v[10:11], v16, s[16:17] s_waitcnt vmcnt(2) v_add_co_u32 v48, vcc_lo, v8, 1 v_add_co_ci_u32_e32 v49, vcc_lo, 0, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v48, s20 v_add_co_ci_u32_e32 v7, vcc_lo, s21, v49, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7] v_dual_cndmask_b32 v7, v7, v49 :: v_dual_cndmask_b32 v6, v6, v48 v_and_b32_e32 v9, v7, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v8, v6, v8 v_mul_hi_u32 v48, v8, 24 v_mul_lo_u32 v8, v8, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v10, vcc_lo, v10, v8 v_mov_b32_e32 v8, v14 v_mul_lo_u32 v9, v9, 24 v_add_nc_u32_e32 v9, v48, v9 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v11, vcc_lo, v11, v9, vcc_lo v_mov_b32_e32 v9, v15 global_store_b64 v[10:11], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[8:9], v[14:15] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_469 ; %bb.467: ; %.preheader.i.i.i79.preheader ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s2, 0 .LBB5_468: ; %.preheader.i.i.i79 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 global_store_b64 v[10:11], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[8:9] v_dual_mov_b32 v8, v14 :: v_dual_mov_b32 v9, v15 s_or_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB5_468 .LBB5_469: ; %Flow1123 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s35 s_mov_b32 s7, s3 .LBB5_470: ; %Flow1124 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s3, s7 .LBB5_471: ; %Flow1134 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s16, s3 .LBB5_472: ; %__ockl_devmem_request.exit83 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_cmp_eq_u32 s16, 0 s_cselect_b32 s5, -1, 0 s_and_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB5_491 ; %bb.473: ; in Loop: Header=BB5_377 Depth=4 v_mbcnt_lo_u32_b32 v6, exec_lo, 0 s_mov_b32 s17, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v6 s_cbranch_execz .LBB5_490 ; %bb.474: ; in Loop: Header=BB5_377 Depth=4 global_load_b64 v[6:7], v[27:28], off glc s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v6, vcc_lo, s2, v6 v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_u64_e32 vcc_lo, 0x7530, v[6:7] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_490 ; %bb.475: ; in Loop: Header=BB5_377 Depth=4 v_sub_nc_u32_e32 v6, 0x7530, v6 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) v_readfirstlane_b32 s2, v6 s_delay_alu instid0(VALU_DEP_1) s_ashr_i32 s3, s2, 31 s_waitcnt lgkmcnt(0) s_add_u32 s2, s6, s2 s_addc_u32 s3, s7, s3 .LBB5_476: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x659 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccnz .LBB5_479 ; %bb.477: ; %.preheader11.i ; in Loop: Header=BB5_476 Depth=5 s_sleep 0x7f s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_branch .LBB5_476 .LBB5_478: ; %.preheader9.i ; in Loop: Header=BB5_479 Depth=5 s_sleep 63 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_479: ; %Flow1104 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x326 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccz .LBB5_478 ; %bb.480: ; %Flow1101 ; in Loop: Header=BB5_377 Depth=4 s_add_u32 s18, s6, 0x18c s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccnz .LBB5_483 .LBB5_481: ; %.preheader7.i ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 31 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x18c s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccnz .LBB5_481 s_branch .LBB5_483 .LBB5_482: ; %.preheader5.i ; in Loop: Header=BB5_483 Depth=5 s_sleep 15 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_483: ; %.loopexit8.i ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0xc0 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccz .LBB5_482 s_branch .LBB5_485 .LBB5_484: ; %.preheader3.i ; in Loop: Header=BB5_485 Depth=5 s_sleep 7 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_485: ; %Flow1095 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 0x59 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccz .LBB5_484 s_branch .LBB5_487 .LBB5_486: ; %.preheader1.i ; in Loop: Header=BB5_487 Depth=5 s_sleep 3 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_487: ; %Flow1092 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_waitcnt lgkmcnt(0) s_add_u32 s18, s6, 38 s_addc_u32 s19, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s18, s[2:3], s[18:19] s_and_b32 vcc_lo, exec_lo, s18 s_cbranch_vccz .LBB5_486 ; %bb.488: ; %Flow1089 ; in Loop: Header=BB5_377 Depth=4 v_cmp_le_u64_e64 s6, s[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_490 .LBB5_489: ; %.preheader.i ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) v_cmp_gt_u64_e64 s6, s[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_489 .LBB5_490: ; %__ockl_rtcwait_u32.exit ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s17 s_cmp_lg_u32 s16, 2 v_mov_b32_e32 v38, s4 s_cselect_b32 s2, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) v_cndmask_b32_e64 v37, 0, 1, s2 .LBB5_491: ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s18, 0 .LBB5_492: ; %Flow1156 ; in Loop: Header=BB5_377 Depth=4 s_and_b32 vcc_lo, exec_lo, s5 s_cbranch_vccz .LBB5_500 ; %bb.493: ; in Loop: Header=BB5_377 Depth=4 v_mov_b32_e32 v6, 1 v_mov_b32_e32 v7, 0 s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB5_497 ; %bb.494: ; in Loop: Header=BB5_377 Depth=4 global_load_b64 v[8:9], v[29:30], off glc s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v6, vcc_lo, s2, v8 v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v9, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_cmp_lt_u64_e32 vcc_lo, 0x4e1f, v[6:7] v_mov_b32_e32 v6, 1 v_mov_b32_e32 v7, 0 s_and_saveexec_b32 s6, vcc_lo s_cbranch_execz .LBB5_496 ; %bb.495: ; in Loop: Header=BB5_377 Depth=4 v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s3 global_atomic_cmpswap_b64 v[6:7], v[29:30], v[6:9], off glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[8:9] v_mov_b32_e32 v7, s4 v_cndmask_b32_e64 v6, 0, 1, vcc_lo .LBB5_496: ; %Flow1083 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 .LBB5_497: ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s5 v_readfirstlane_b32 s2, v6 v_readfirstlane_b32 s3, v7 s_mov_b32 s18, 0 s_delay_alu instid0(VALU_DEP_1) s_cmp_lg_u64 s[2:3], 0 s_cbranch_scc0 .LBB5_501 ; %bb.498: ; in Loop: Header=BB5_377 Depth=4 v_dual_mov_b32 v7, s3 :: v_dual_mov_b32 v6, s2 .LBB5_499: ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v38, v7 :: v_dual_mov_b32 v37, v6 .LBB5_500: ; %Flow1159 ; in Loop: Header=BB5_377 Depth=4 s_xor_b32 s1, s18, -1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s1 s_cbranch_vccnz .LBB5_377 s_branch .LBB5_616 .LBB5_501: ; in Loop: Header=BB5_377 Depth=4 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_and_saveexec_b32 s20, s1 s_cbranch_execz .LBB5_537 ; %bb.502: ; in Loop: Header=BB5_377 Depth=4 s_clause 0x1 global_load_b64 v[8:9], v16, s[12:13] glc global_load_b64 v[6:7], v16, s[14:15] s_waitcnt vmcnt(0) v_cmp_ge_u64_e32 vcc_lo, v[8:9], v[6:7] s_cbranch_vccnz .LBB5_506 ; %bb.503: ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s2, exec_lo s_mov_b32 s1, exec_lo v_mbcnt_lo_u32_b32 v14, s2, 0 ; implicit-def: $vgpr8_vgpr9 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v14 s_cbranch_execz .LBB5_505 ; %bb.504: ; in Loop: Header=BB5_377 Depth=4 s_bcnt1_i32_b32 s2, s2 v_mov_b32_e32 v9, 0 s_lshl_b32 s2, s2, 21 s_delay_alu instid0(SALU_CYCLE_1) v_mov_b32_e32 v8, s2 global_atomic_add_u64 v[8:9], v16, v[8:9], s[12:13] glc .LBB5_505: ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s1 s_waitcnt vmcnt(0) v_readfirstlane_b32 s3, v9 v_readfirstlane_b32 s2, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[10:11], null, v14, 0x200000, s[2:3] v_cmp_ge_u64_e64 s1, v[10:11], v[6:7] s_branch .LBB5_507 .LBB5_506: ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s1, -1 ; implicit-def: $vgpr10_vgpr11 .LBB5_507: ; %Flow1080 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s21, s1 s_cbranch_execz .LBB5_536 ; %bb.508: ; in Loop: Header=BB5_377 Depth=4 s_load_b64 s[2:3], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s1, v15 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 v_cmp_eq_u32_e64 s1, s1, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB5_514 ; %bb.509: ; in Loop: Header=BB5_377 Depth=4 s_waitcnt lgkmcnt(0) global_load_b64 v[8:9], v16, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[6:7], v16, s[2:3] offset:40 global_load_b64 v[10:11], v16, s[2:3] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v7, v7, v9 v_and_b32_e32 v6, v6, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v7, v7, 24 v_mul_hi_u32 v14, v6, 24 v_mul_lo_u32 v6, v6, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, v14, v7 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v10, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, v11, v7, vcc_lo global_load_b64 v[6:7], v[6:7], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[10:11], v[8:9] s_cbranch_execz .LBB5_513 ; %bb.510: ; %.preheader3.i.i.i89.preheader ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s7, 0 .LBB5_511: ; %.preheader3.i.i.i89 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 s_clause 0x1 global_load_b64 v[6:7], v16, s[2:3] offset:40 global_load_b64 v[48:49], v16, s[2:3] v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v6, v6, v8 v_and_b32_e32 v7, v7, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[10:11], null, v6, 24, v[48:49] v_mov_b32_e32 v6, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[48:49], null, v7, 24, v[6:7] v_mov_b32_e32 v11, v48 global_load_b64 v[6:7], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[8:9] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_511 ; %bb.512: ; %Flow1076 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s7 .LBB5_513: ; %Flow1078 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB5_514: ; %.loopexit4.i.i.i84 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[48:49], v16, s[2:3] offset:40 global_load_b128 v[6:9], v16, s[2:3] v_readfirstlane_b32 s16, v10 v_readfirstlane_b32 s17, v11 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s18, v48 v_readfirstlane_b32 s19, v49 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[18:19], s[16:17], s[18:19] s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB5_516 ; %bb.515: ; in Loop: Header=BB5_377 Depth=4 v_dual_mov_b32 v52, s6 :: v_dual_mov_b32 v53, 0 s_mul_i32 s6, s19, 24 s_mul_hi_u32 s7, s18, 24 v_dual_mov_b32 v54, 3 :: v_dual_mov_b32 v55, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s18, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v7, vcc_lo global_store_b128 v[10:11], v[52:55], off offset:8 .LBB5_516: ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[18:19], 12 v_lshlrev_b64 v[10:11], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v14, vcc_lo, v8, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo s_mov_b32 s5, s4 s_mov_b32 s6, s4 s_mov_b32 s7, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v55, s7 v_add_co_u32 v48, vcc_lo, v14, v10 v_add_co_ci_u32_e32 v49, vcc_lo, v9, v11, vcc_lo v_dual_mov_b32 v10, 0x200000 :: v_dual_mov_b32 v9, v8 v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v54, s6 v_dual_mov_b32 v53, s5 :: v_dual_mov_b32 v52, s4 s_clause 0x3 global_store_b128 v[48:49], v[8:11], off global_store_b128 v[48:49], v[52:55], off offset:16 global_store_b128 v[48:49], v[52:55], off offset:32 global_store_b128 v[48:49], v[52:55], off offset:48 s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB5_524 ; %bb.517: ; in Loop: Header=BB5_377 Depth=4 s_clause 0x1 global_load_b64 v[54:55], v16, s[2:3] offset:32 glc global_load_b64 v[8:9], v16, s[2:3] offset:40 v_dual_mov_b32 v52, s16 :: v_dual_mov_b32 v53, s17 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[16:17] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s22, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s22, s22, s7 v_add_co_u32 v14, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v15, vcc_lo, s22, v7, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[14:15], v[54:55], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v16, v[52:55], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[10:11], v[54:55] s_cbranch_execz .LBB5_520 ; %bb.518: ; %.preheader1.i.i.i87.preheader ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s7, 0 .LBB5_519: ; %.preheader1.i.i.i87 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, s17 s_sleep 1 global_store_b64 v[14:15], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[8:11], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11] v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_519 .LBB5_520: ; %Flow1074 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 global_load_b64 v[8:9], v16, s[2:3] offset:16 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v10, s7, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB5_522 ; %bb.521: ; in Loop: Header=BB5_377 Depth=4 s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[8:9], v[10:11], off offset:8 .LBB5_522: ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[10:11], v[8:9], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] s_cbranch_vccnz .LBB5_524 ; %bb.523: ; in Loop: Header=BB5_377 Depth=4 global_load_b32 v15, v[8:9], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[10:11], v[15:16], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB5_524: ; %Flow1075 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_mul_i32 s5, s19, 24 s_mul_hi_u32 s6, s18, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s6, s6, s5 s_mul_i32 s5, s18, 24 v_add_co_u32 v6, vcc_lo, v6, s5 v_add_co_ci_u32_e32 v7, vcc_lo, s6, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v6, 20 v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo .LBB5_525: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_mov_b32_e32 v8, 1 s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB5_527 ; %bb.526: ; in Loop: Header=BB5_525 Depth=5 global_load_b32 v8, v[6:7], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v8, 1, v8 .LBB5_527: ; in Loop: Header=BB5_525 Depth=5 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s5, v8 s_cmp_eq_u32 s5, 0 s_cbranch_scc1 .LBB5_529 ; %bb.528: ; in Loop: Header=BB5_525 Depth=5 s_mov_b32 s5, 0 s_sleep 1 s_branch .LBB5_530 .LBB5_529: ; in Loop: Header=BB5_525 Depth=5 s_mov_b32 s5, -1 .LBB5_530: ; %Flow1069 ; in Loop: Header=BB5_525 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s5 s_cbranch_vccnz .LBB5_525 ; %bb.531: ; in Loop: Header=BB5_377 Depth=4 global_load_b64 v[10:11], v[48:49], off s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB5_535 ; %bb.532: ; in Loop: Header=BB5_377 Depth=4 s_clause 0x2 global_load_b64 v[8:9], v16, s[2:3] offset:40 global_load_b64 v[48:49], v16, s[2:3] offset:24 glc global_load_b64 v[14:15], v16, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v52, vcc_lo, v8, 1 v_add_co_ci_u32_e32 v53, vcc_lo, 0, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v52, s16 v_add_co_ci_u32_e32 v7, vcc_lo, s17, v53, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7] v_dual_cndmask_b32 v7, v7, v53 :: v_dual_cndmask_b32 v6, v6, v52 v_and_b32_e32 v9, v7, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v8, v6, v8 v_mul_hi_u32 v52, v8, 24 v_mul_lo_u32 v8, v8, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v14, vcc_lo, v14, v8 v_mov_b32_e32 v8, v48 v_mul_lo_u32 v9, v9, 24 v_add_nc_u32_e32 v9, v52, v9 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v15, vcc_lo, v15, v9, vcc_lo v_mov_b32_e32 v9, v49 global_store_b64 v[14:15], v[48:49], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[8:9], v[48:49] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_535 ; %bb.533: ; %.preheader.i.i.i86.preheader ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s1, 0 .LBB5_534: ; %.preheader.i.i.i86 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 global_store_b64 v[14:15], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[48:49], v16, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[48:49], v[8:9] v_dual_mov_b32 v8, v48 :: v_dual_mov_b32 v9, v49 s_or_b32 s1, vcc_lo, s1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB5_534 .LBB5_535: ; %Flow1067 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 .LBB5_536: ; %Flow1081 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s21 .LBB5_537: ; %__ockl_devmem_request.exit90 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s20 s_waitcnt vmcnt(0) v_readfirstlane_b32 s2, v10 v_readfirstlane_b32 s3, v11 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_delay_alu instid0(VALU_DEP_3) s_cmp_eq_u64 s[2:3], 0 s_cbranch_scc1 .LBB5_582 ; %bb.538: ; in Loop: Header=BB5_377 Depth=4 v_mbcnt_lo_u32_b32 v6, exec_lo, 0 ;;#ASMSTART ;;#ASMEND global_load_b32 v10, v[23:24], off s_bcnt1_i32_b32 s5, exec_lo s_add_u32 s6, s2, 16 s_addc_u32 s7, s3, 0 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v7, 31, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_lshrrev_b32_e32 v9, 5, v7 s_and_saveexec_b32 s1, s0 s_xor_b32 s16, exec_lo, s1 s_cbranch_execz .LBB5_546 ; %bb.539: ; in Loop: Header=BB5_377 Depth=4 global_load_b32 v11, v[31:32], off s_mov_b32 s17, exec_lo v_cmpx_lt_u32_e64 v6, v9 s_cbranch_execz .LBB5_542 ; %bb.540: ; %.preheader182.preheader ; in Loop: Header=BB5_377 Depth=4 v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v14, v6 s_add_u32 s1, s2, 16 s_addc_u32 s18, s3, 0 s_mov_b32 s19, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[6:7] s_mov_b32 s20, 0 v_add_co_u32 v7, vcc_lo, s1, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s18, v8, vcc_lo s_lshl_b32 s18, s5, 2 .LBB5_541: ; %.preheader182 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_add_nc_u32_e32 v14, s5, v14 global_store_b32 v[7:8], v16, off v_add_co_u32 v7, s1, v7, s18 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e64 v8, s1, s19, v8, s1 v_cmp_ge_u32_e32 vcc_lo, v14, v9 s_or_b32 s20, vcc_lo, s20 s_and_not1_b32 exec_lo, exec_lo, s20 s_cbranch_execnz .LBB5_541 .LBB5_542: ; %Flow1056 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s17 global_load_b32 v14, v[33:34], off s_mov_b32 s1, exec_lo s_waitcnt vmcnt(0) v_mad_u64_u32 v[7:8], null, v11, v6, v[14:15] s_delay_alu instid0(VALU_DEP_1) v_cmpx_lt_u32_e64 v7, v10 s_cbranch_execz .LBB5_545 ; %bb.543: ; %.preheader180.preheader ; in Loop: Header=BB5_377 Depth=4 v_mul_lo_u32 v8, v11, s5 s_mov_b32 s17, 0 .LBB5_544: ; %.preheader180 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_lshlrev_b32_e64 v11, v7, 1 v_lshrrev_b32_e32 v14, 3, v7 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, v7, v8 v_and_b32_e32 v14, 0x1ffffffc, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_ge_u32_e32 vcc_lo, v7, v10 global_store_b32 v14, v11, s[6:7] s_or_b32 s17, vcc_lo, s17 s_and_not1_b32 exec_lo, exec_lo, s17 s_cbranch_execnz .LBB5_544 .LBB5_545: ; %Flow1053 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s1 .LBB5_546: ; %Flow1061 ; in Loop: Header=BB5_377 Depth=4 s_and_not1_saveexec_b32 s16, s16 s_cbranch_execz .LBB5_551 ; %bb.547: ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s17, exec_lo v_cmpx_lt_u32_e64 v6, v9 s_cbranch_execz .LBB5_550 ; %bb.548: ; %.preheader178.preheader ; in Loop: Header=BB5_377 Depth=4 global_load_b32 v11, v[35:36], off v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v14, v6 s_add_u32 s1, s2, 16 s_addc_u32 s18, s3, 0 s_mov_b32 s19, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[6:7] s_mov_b32 s20, 0 v_add_co_u32 v7, vcc_lo, s1, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s18, v8, vcc_lo s_lshl_b32 s18, s5, 2 .LBB5_549: ; %.preheader178 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_add_nc_u32_e32 v14, s5, v14 s_waitcnt vmcnt(0) global_store_b32 v[7:8], v11, off v_add_co_u32 v7, s1, v7, s18 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e64 v8, s1, s19, v8, s1 v_cmp_ge_u32_e32 vcc_lo, v14, v9 s_or_b32 s20, vcc_lo, s20 s_and_not1_b32 exec_lo, exec_lo, s20 s_cbranch_execnz .LBB5_549 .LBB5_550: ; %Flow1059 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s17 .LBB5_551: ; %.loopexit179 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s16 s_mov_b32 s1, exec_lo v_cmpx_eq_u32_e32 0, v6 s_cbranch_execz .LBB5_555 ; %bb.552: ; in Loop: Header=BB5_377 Depth=4 v_and_b32_e32 v6, 31, v10 s_mov_b32 s5, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_ne_u32_e32 0, v6 s_cbranch_execz .LBB5_554 ; %bb.553: ; in Loop: Header=BB5_377 Depth=4 v_add_nc_u32_e32 v15, -1, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[15:16] v_add_co_u32 v7, vcc_lo, s6, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo global_load_b32 v9, v[7:8], off s_waitcnt vmcnt(0) v_lshl_or_b32 v6, -1, v6, v9 global_store_b32 v[7:8], v6, off .LBB5_554: ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 global_store_b128 v16, v[2:5], s[2:3] .LBB5_555: ; %Flow1050 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s1 ; implicit-def: $sgpr5 .LBB5_556: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 ;;#ASMSTART ;;#ASMEND v_cmp_eq_u32_e64 s1, 0, v51 v_mov_b32_e32 v6, s31 s_delay_alu instid0(VALU_DEP_2) s_and_saveexec_b32 s6, s1 s_cbranch_execz .LBB5_558 ; %bb.557: ; in Loop: Header=BB5_556 Depth=5 global_load_b32 v6, v[17:18], off glc .LBB5_558: ; in Loop: Header=BB5_556 Depth=5 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) v_readfirstlane_b32 s31, v6 s_and_not1_b32 s5, s5, exec_lo s_and_b32 s6, s1, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 s5, s5, s6 s_cmp_eq_u32 s31, 0x10100 s_cbranch_scc1 .LBB5_565 ; %bb.559: ; in Loop: Header=BB5_556 Depth=5 v_mov_b32_e32 v6, s34 s_and_saveexec_b32 s6, s1 s_cbranch_execz .LBB5_561 ; %bb.560: ; in Loop: Header=BB5_556 Depth=5 global_load_b32 v6, v[25:26], off glc .LBB5_561: ; in Loop: Header=BB5_556 Depth=5 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) v_readfirstlane_b32 s34, v6 s_delay_alu instid0(VALU_DEP_1) s_cmp_lg_u32 s31, s34 s_cbranch_scc0 .LBB5_566 ; %bb.562: ; in Loop: Header=BB5_556 Depth=5 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 s_and_saveexec_b32 s6, s1 s_cbranch_execz .LBB5_573 ; %bb.563: ; in Loop: Header=BB5_556 Depth=5 s_cmpk_lt_u32 s31, 0x100 s_cbranch_scc0 .LBB5_567 ; %bb.564: ; in Loop: Header=BB5_556 Depth=5 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 s_mov_b32 s7, 0 v_mad_u64_u32 v[8:9], null, v2, 0x1800, s[16:17] s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, s31, 24, v[8:9] s_branch .LBB5_568 .LBB5_565: ; in Loop: Header=BB5_556 Depth=5 s_mov_b64 s[16:17], 0 s_mov_b32 s1, -1 s_mov_b32 s18, 0 s_mov_b32 s19, -1 ; implicit-def: $sgpr31 ; implicit-def: $sgpr34 ; implicit-def: $sgpr6_sgpr7 s_branch .LBB5_578 .LBB5_566: ; in Loop: Header=BB5_556 Depth=5 s_mov_b32 s18, -1 s_mov_b32 s19, -1 ; implicit-def: $sgpr31 ; implicit-def: $sgpr34 ; implicit-def: $sgpr6_sgpr7 s_branch .LBB5_577 .LBB5_567: ; in Loop: Header=BB5_556 Depth=5 s_mov_b32 s7, -1 ; implicit-def: $vgpr6_vgpr7 .LBB5_568: ; %Flow1042 ; in Loop: Header=BB5_556 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s7 s_cbranch_vccnz .LBB5_570 ; %bb.569: ; in Loop: Header=BB5_556 Depth=5 s_add_i32 s7, s31, 0xffffff00 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_lshr_b32 s7, s7, 8 s_add_u32 s16, s10, 0x2800 s_addc_u32 s17, s11, 0 v_mad_u64_u32 v[6:7], null, v2, 0x1800, s[16:17] s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[8:9], null, s7, 24, v[6:7] s_and_b32 s7, s31, 0xff global_load_b64 v[8:9], v[8:9], off glc s_waitcnt vmcnt(0) v_mad_u64_u32 v[6:7], null, s7, 24, v[8:9] .LBB5_570: ; in Loop: Header=BB5_556 Depth=5 v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, s3 v_mov_b32_e32 v14, s31 s_delay_alu instid0(VALU_DEP_2) v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v11, v10 global_store_b32 v16, v14, s[2:3] offset:4 global_atomic_cmpswap_b64 v[8:9], v[6:7], v[8:11], off offset:8 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9] v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 s_and_saveexec_b32 s7, vcc_lo s_cbranch_execz .LBB5_572 ; %bb.571: ; in Loop: Header=BB5_556 Depth=5 s_waitcnt_vscnt null, 0x0 global_atomic_add_u32 v[17:18], v98, off v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 .LBB5_572: ; %Flow1040 ; in Loop: Header=BB5_556 Depth=5 s_or_b32 exec_lo, exec_lo, s7 .LBB5_573: ; %Flow1043 ; in Loop: Header=BB5_556 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s6 v_readfirstlane_b32 s6, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s7, v9 s_cmp_lg_u64 s[6:7], 0 s_cbranch_scc0 .LBB5_575 ; %bb.574: ; in Loop: Header=BB5_556 Depth=5 s_mov_b32 s19, -1 ; implicit-def: $sgpr31 ; implicit-def: $sgpr34 s_branch .LBB5_576 .LBB5_575: ; in Loop: Header=BB5_556 Depth=5 s_mov_b32 s19, 0 s_and_not1_b32 s1, s1, exec_lo s_sleep 2 .LBB5_576: ; %Flow1048 ; in Loop: Header=BB5_556 Depth=5 s_mov_b32 s18, 0 .LBB5_577: ; %Flow1047 ; in Loop: Header=BB5_556 Depth=5 s_and_not1_b32 s5, s5, exec_lo s_and_b32 s16, s1, exec_lo s_mov_b32 s1, 0 s_or_b32 s5, s5, s16 ; implicit-def: $sgpr16_sgpr17 .LBB5_578: ; %Flow1046 ; in Loop: Header=BB5_556 Depth=5 s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccz .LBB5_556 ; %bb.579: ; %loop.exit.guard777 ; in Loop: Header=BB5_377 Depth=4 v_dual_mov_b32 v6, s16 :: v_dual_mov_b32 v7, s17 s_and_b32 vcc_lo, exec_lo, s1 s_cbranch_vccnz .LBB5_499 ; %bb.580: ; %loop.exit.guard778 ; in Loop: Header=BB5_377 Depth=4 s_xor_b32 s1, s18, -1 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s1 s_cbranch_vccz .LBB5_583 ; %bb.581: ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s18, 0 s_branch .LBB5_584 .LBB5_582: ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s18, 0 s_branch .LBB5_499 .LBB5_583: ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s18, -1 ; implicit-def: $sgpr6_sgpr7 .LBB5_584: ; %Flow1037 ; in Loop: Header=BB5_377 Depth=4 v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 s_and_not1_b32 vcc_lo, exec_lo, s18 s_cbranch_vccnz .LBB5_499 ; %bb.585: ; in Loop: Header=BB5_377 Depth=4 s_and_saveexec_b32 s22, s5 s_cbranch_execz .LBB5_614 ; %bb.586: ; in Loop: Header=BB5_377 Depth=4 s_load_b64 s[16:17], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v15, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s1, v15 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 v_cmp_eq_u32_e64 s1, s1, v15 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB5_592 ; %bb.587: ; in Loop: Header=BB5_377 Depth=4 s_waitcnt lgkmcnt(0) global_load_b64 v[8:9], v16, s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[6:7], v16, s[16:17] offset:40 global_load_b64 v[10:11], v16, s[16:17] s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v7, v7, v9 v_and_b32_e32 v6, v6, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v7, v7, 24 v_mul_hi_u32 v14, v6, 24 v_mul_lo_u32 v6, v6, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, v14, v7 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v10, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, v11, v7, vcc_lo global_load_b64 v[6:7], v[6:7], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[10:11], v[8:9] s_cbranch_execz .LBB5_591 ; %bb.588: ; %.preheader3.i.i.i96.preheader ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s7, 0 .LBB5_589: ; %.preheader3.i.i.i96 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 s_clause 0x1 global_load_b64 v[6:7], v16, s[16:17] offset:40 global_load_b64 v[48:49], v16, s[16:17] v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v6, v6, v8 v_and_b32_e32 v7, v7, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[10:11], null, v6, 24, v[48:49] v_mov_b32_e32 v6, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[48:49], null, v7, 24, v[6:7] v_mov_b32_e32 v11, v48 global_load_b64 v[6:7], v[10:11], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[8:9] s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB5_589 ; %bb.590: ; %Flow1033 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s7 .LBB5_591: ; %Flow1035 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s6 .LBB5_592: ; %.loopexit4.i.i.i91 ; in Loop: Header=BB5_377 Depth=4 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[48:49], v16, s[16:17] offset:40 global_load_b128 v[6:9], v16, s[16:17] v_readfirstlane_b32 s18, v10 v_readfirstlane_b32 s19, v11 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s20, v48 v_readfirstlane_b32 s21, v49 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[20:21], s[18:19], s[20:21] s_and_saveexec_b32 s5, s1 s_cbranch_execz .LBB5_594 ; %bb.593: ; in Loop: Header=BB5_377 Depth=4 v_dual_mov_b32 v51, s6 :: v_dual_mov_b32 v52, 0 s_mul_i32 s6, s21, 24 s_mul_hi_u32 s7, s20, 24 v_dual_mov_b32 v53, 3 :: v_dual_mov_b32 v54, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s20, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v7, vcc_lo global_store_b128 v[10:11], v[51:54], off offset:8 .LBB5_594: ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b64 s[6:7], s[20:21], 12 v_lshlrev_b64 v[10:11], 6, v[15:16] s_waitcnt vmcnt(0) v_add_co_u32 v8, vcc_lo, v8, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo s_mov_b32 s7, s4 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v14, vcc_lo, v8, v10 s_mov_b32 s5, s4 s_mov_b32 s6, s4 v_mov_b32_e32 v48, 0 v_mov_b32_e32 v52, s3 v_add_co_ci_u32_e32 v15, vcc_lo, v9, v11, vcc_lo v_mov_b32_e32 v11, s7 v_dual_mov_b32 v51, s2 :: v_dual_mov_b32 v10, s6 v_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4 v_mov_b32_e32 v49, v48 s_clause 0x4 global_store_b64 v[14:15], v[51:52], off global_store_b128 v[14:15], v[8:11], off offset:8 global_store_b128 v[14:15], v[8:11], off offset:24 global_store_b128 v[14:15], v[8:11], off offset:40 global_store_b64 v[14:15], v[48:49], off offset:56 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB5_602 ; %bb.595: ; in Loop: Header=BB5_377 Depth=4 s_clause 0x1 global_load_b64 v[53:54], v16, s[16:17] offset:32 glc global_load_b64 v[8:9], v16, s[16:17] offset:40 v_dual_mov_b32 v51, s18 :: v_dual_mov_b32 v52, s19 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[18:19] s_mul_i32 s3, s7, 24 s_mul_hi_u32 s5, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s5, s5, s3 v_add_co_u32 v14, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v15, vcc_lo, s5, v7, vcc_lo s_mov_b32 s3, exec_lo global_store_b64 v[14:15], v[53:54], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v16, v[51:54], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[10:11], v[53:54] s_cbranch_execz .LBB5_598 ; %bb.596: ; %.preheader1.i.i.i94.preheader ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s5, 0 .LBB5_597: ; %.preheader1.i.i.i94 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_dual_mov_b32 v8, s18 :: v_dual_mov_b32 v9, s19 s_sleep 1 global_store_b64 v[14:15], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[8:11], s[16:17] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11] v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8 s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB5_597 .LBB5_598: ; %Flow1031 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s3 global_load_b64 v[8:9], v16, s[16:17] offset:16 s_mov_b32 s5, exec_lo s_mov_b32 s3, exec_lo v_mbcnt_lo_u32_b32 v10, s5, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB5_600 ; %bb.599: ; in Loop: Header=BB5_377 Depth=4 s_bcnt1_i32_b32 s5, s5 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, s5 s_waitcnt vmcnt(0) global_atomic_add_u64 v[8:9], v[10:11], off offset:8 .LBB5_600: ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) global_load_b64 v[10:11], v[8:9], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] s_cbranch_vccnz .LBB5_602 ; %bb.601: ; in Loop: Header=BB5_377 Depth=4 global_load_b32 v15, v[8:9], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s3, v15 s_waitcnt_vscnt null, 0x0 global_store_b64 v[10:11], v[15:16], off s_and_b32 m0, s3, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB5_602: ; %Flow1032 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s2 s_mul_i32 s2, s21, 24 s_mul_hi_u32 s3, s20, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s3, s3, s2 s_mul_i32 s2, s20, 24 v_add_co_u32 v6, vcc_lo, v6, s2 v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v6, 20 v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo .LBB5_603: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 v_mov_b32_e32 v8, 1 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB5_605 ; %bb.604: ; in Loop: Header=BB5_603 Depth=5 global_load_b32 v8, v[6:7], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v8, 1, v8 .LBB5_605: ; in Loop: Header=BB5_603 Depth=5 s_or_b32 exec_lo, exec_lo, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s2, v8 s_cmp_eq_u32 s2, 0 s_cbranch_scc1 .LBB5_607 ; %bb.606: ; in Loop: Header=BB5_603 Depth=5 s_mov_b32 s2, 0 s_sleep 1 s_branch .LBB5_608 .LBB5_607: ; in Loop: Header=BB5_603 Depth=5 s_mov_b32 s2, -1 .LBB5_608: ; %Flow1026 ; in Loop: Header=BB5_603 Depth=5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s2 s_cbranch_vccnz .LBB5_603 ; %bb.609: ; in Loop: Header=BB5_377 Depth=4 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB5_613 ; %bb.610: ; in Loop: Header=BB5_377 Depth=4 s_clause 0x2 global_load_b64 v[8:9], v16, s[16:17] offset:40 global_load_b64 v[14:15], v16, s[16:17] offset:24 glc global_load_b64 v[10:11], v16, s[16:17] s_waitcnt vmcnt(2) v_add_co_u32 v48, vcc_lo, v8, 1 v_add_co_ci_u32_e32 v49, vcc_lo, 0, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v48, s18 v_add_co_ci_u32_e32 v7, vcc_lo, s19, v49, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7] v_dual_cndmask_b32 v7, v7, v49 :: v_dual_cndmask_b32 v6, v6, v48 v_and_b32_e32 v9, v7, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v8, v6, v8 v_mul_hi_u32 v48, v8, 24 v_mul_lo_u32 v8, v8, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v10, vcc_lo, v10, v8 v_mov_b32_e32 v8, v14 v_mul_lo_u32 v9, v9, 24 v_add_nc_u32_e32 v9, v48, v9 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v11, vcc_lo, v11, v9, vcc_lo v_mov_b32_e32 v9, v15 global_store_b64 v[10:11], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[8:9], v[14:15] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_613 ; %bb.611: ; %.preheader.i.i.i93.preheader ; in Loop: Header=BB5_377 Depth=4 s_mov_b32 s1, 0 .LBB5_612: ; %.preheader.i.i.i93 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; Parent Loop BB5_377 Depth=4 ; => This Inner Loop Header: Depth=5 s_sleep 1 global_store_b64 v[10:11], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v16, v[6:9], s[16:17] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[8:9] v_dual_mov_b32 v8, v14 :: v_dual_mov_b32 v9, v15 s_or_b32 s1, vcc_lo, s1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB5_612 .LBB5_613: ; %Flow1024 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s2 v_mov_b32_e32 v51, 0 .LBB5_614: ; %Flow1036 ; in Loop: Header=BB5_377 Depth=4 s_or_b32 exec_lo, exec_lo, s22 v_dual_mov_b32 v6, v37 :: v_dual_mov_b32 v7, v38 s_mov_b32 s18, -1 s_branch .LBB5_499 .LBB5_615: ; in Loop: Header=BB5_345 Depth=3 ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $sgpr29 ; implicit-def: $vgpr50 s_branch .LBB5_639 .LBB5_616: ; in Loop: Header=BB5_345 Depth=3 v_cmp_ne_u64_e64 s5, 1, v[37:38] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s5 s_cbranch_vccz .LBB5_618 ; %bb.617: ; in Loop: Header=BB5_345 Depth=3 v_dual_mov_b32 v12, v37 :: v_dual_mov_b32 v13, v38 s_branch .LBB5_638 .LBB5_618: ; in Loop: Header=BB5_345 Depth=3 v_mbcnt_lo_u32_b32 v6, exec_lo, 0 s_mov_b32 s1, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v6 s_cbranch_execz .LBB5_635 ; %bb.619: ; in Loop: Header=BB5_345 Depth=3 global_load_b64 v[6:7], v[29:30], off glc s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_co_u32 v6, vcc_lo, s2, v6 v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_u64_e32 vcc_lo, 0x4e20, v[6:7] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_635 ; %bb.620: ; in Loop: Header=BB5_345 Depth=3 v_sub_nc_u32_e32 v6, 0x4e20, v6 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) v_readfirstlane_b32 s2, v6 s_delay_alu instid0(VALU_DEP_1) s_ashr_i32 s3, s2, 31 s_waitcnt lgkmcnt(0) s_add_u32 s2, s6, s2 s_addc_u32 s3, s7, s3 .LBB5_621: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_waitcnt lgkmcnt(0) s_add_u32 s16, s6, 0x659 s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB5_624 ; %bb.622: ; %.preheader11.i110 ; in Loop: Header=BB5_621 Depth=4 s_sleep 0x7f s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_branch .LBB5_621 .LBB5_623: ; %.preheader9.i109 ; in Loop: Header=BB5_624 Depth=4 s_sleep 63 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_624: ; %Flow1018 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_waitcnt lgkmcnt(0) s_add_u32 s16, s6, 0x326 s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccz .LBB5_623 ; %bb.625: ; %Flow1015 ; in Loop: Header=BB5_345 Depth=3 s_add_u32 s16, s6, 0x18c s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB5_628 .LBB5_626: ; %.preheader7.i108 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_sleep 31 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) s_add_u32 s16, s6, 0x18c s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccnz .LBB5_626 s_branch .LBB5_628 .LBB5_627: ; %.preheader5.i107 ; in Loop: Header=BB5_628 Depth=4 s_sleep 15 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_628: ; %.loopexit8.i100 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_waitcnt lgkmcnt(0) s_add_u32 s16, s6, 0xc0 s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccz .LBB5_627 s_branch .LBB5_630 .LBB5_629: ; %.preheader3.i106 ; in Loop: Header=BB5_630 Depth=4 s_sleep 7 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_630: ; %Flow1009 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_waitcnt lgkmcnt(0) s_add_u32 s16, s6, 0x59 s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccz .LBB5_629 s_branch .LBB5_632 .LBB5_631: ; %.preheader1.i105 ; in Loop: Header=BB5_632 Depth=4 s_sleep 3 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) .LBB5_632: ; %Flow1006 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_waitcnt lgkmcnt(0) s_add_u32 s16, s6, 38 s_addc_u32 s17, s7, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u64_e64 s16, s[2:3], s[16:17] s_and_b32 vcc_lo, exec_lo, s16 s_cbranch_vccz .LBB5_631 ; %bb.633: ; %Flow1003 ; in Loop: Header=BB5_345 Depth=3 v_cmp_le_u64_e64 s6, s[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_635 .LBB5_634: ; %.preheader.i104 ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; Parent Loop BB5_345 Depth=3 ; => This Inner Loop Header: Depth=4 s_sleep 1 s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME) s_waitcnt lgkmcnt(0) v_cmp_gt_u64_e64 s6, s[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_634 .LBB5_635: ; %__ockl_rtcwait_u32.exit111 ; in Loop: Header=BB5_345 Depth=3 s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v6, s29 s_mov_b32 s1, exec_lo v_cmpx_eq_u32_e32 0, v50 s_cbranch_execz .LBB5_637 ; %bb.636: ; in Loop: Header=BB5_345 Depth=3 global_load_b32 v6, v[17:18], off glc .LBB5_637: ; in Loop: Header=BB5_345 Depth=3 s_or_b32 exec_lo, exec_lo, s1 s_waitcnt vmcnt(0) v_readfirstlane_b32 s29, v6 .LBB5_638: ; %Flow1020 ; in Loop: Header=BB5_345 Depth=3 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v7, v12 :: v_dual_mov_b32 v8, v13 .LBB5_639: ; %Flow1165 ; in Loop: Header=BB5_345 Depth=3 s_and_b32 vcc_lo, exec_lo, s5 s_cbranch_vccz .LBB5_345 .LBB5_640: ; %.loopexit189 ; in Loop: Header=BB5_6 Depth=2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_readfirstlane_b32 s6, v7 v_readfirstlane_b32 s7, v8 v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0 s_delay_alu instid0(VALU_DEP_2) s_cmp_eq_u64 s[6:7], 0 s_cbranch_scc1 .LBB5_661 ; %bb.641: ; in Loop: Header=BB5_6 Depth=2 s_mov_b32 s5, exec_lo s_delay_alu instid0(SALU_CYCLE_1) v_mbcnt_lo_u32_b32 v8, s5, 0 ;;#ASMSTART ;;#ASMEND global_load_b64 v[0:1], v16, s[6:7] offset:8 glc v_cmp_eq_u32_e32 vcc_lo, 0, v8 s_waitcnt vmcnt(0) global_load_b32 v6, v[0:1], off s_waitcnt vmcnt(0) v_readfirstlane_b32 s2, v6 v_mov_b32_e32 v6, 0 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB5_645 ; %bb.642: ; in Loop: Header=BB5_6 Depth=2 s_mov_b32 s17, exec_lo s_bcnt1_i32_b32 s5, s5 v_mbcnt_lo_u32_b32 v6, s17, 0 s_mov_b32 s16, exec_lo ; implicit-def: $vgpr7 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v6 s_cbranch_execz .LBB5_644 ; %bb.643: ; in Loop: Header=BB5_6 Depth=2 s_bcnt1_i32_b32 s1, s17 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s1, s5, s1 v_mov_b32_e32 v7, s1 global_atomic_add_u32 v7, v[0:1], v7, off offset:8 glc .LBB5_644: ; in Loop: Header=BB5_6 Depth=2 s_or_b32 exec_lo, exec_lo, s16 s_waitcnt vmcnt(0) v_readfirstlane_b32 s1, v7 s_delay_alu instid0(VALU_DEP_1) v_mad_u32_u24 v6, s5, v6, s1 .LBB5_645: ; %Flow791 ; in Loop: Header=BB5_6 Depth=2 s_or_b32 exec_lo, exec_lo, s3 s_mov_b32 s3, s4 s_getpc_b64 s[18:19] s_add_u32 s18, s18, __unnamed_1@rel32@lo+4 s_addc_u32 s19, s19, __unnamed_1@rel32@hi+12 s_lshl_b64 s[16:17], s[2:3], 5 v_readfirstlane_b32 s1, v6 s_add_u32 s18, s16, s18 s_addc_u32 s19, s17, s19 v_mov_b32_e32 v6, 0 s_load_b32 s5, s[18:19], 0x0 v_mov_b32_e32 v7, 0 s_waitcnt lgkmcnt(0) s_add_i32 s3, s5, 31 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lt_u32 s3, 32 s_cbranch_scc1 .LBB5_655 ; %bb.646: ; in Loop: Header=BB5_6 Depth=2 v_cvt_f32_u32_e32 v6, s5 s_getpc_b64 s[18:19] s_add_u32 s18, s18, __unnamed_1@rel32@lo+32 s_addc_u32 s19, s19, __unnamed_1@rel32@hi+40 s_lshr_b32 s3, s3, 5 s_add_u32 s18, s16, s18 s_addc_u32 s19, s17, s19 v_rcp_iflag_f32_e32 v6, v6 s_load_b32 s18, s[18:19], 0x0 s_sub_i32 s19, 0, s5 v_add_nc_u32_e32 v8, s1, v8 s_waitcnt_depctr 0xfff v_mul_f32_e32 v6, 0x4f7ffffe, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v6, v6 v_mul_lo_u32 v7, s19, v6 s_waitcnt lgkmcnt(0) v_mul_lo_u32 v8, s18, v8 s_getpc_b64 s[18:19] s_add_u32 s18, s18, __unnamed_1@rel32@lo+16 s_addc_u32 s19, s19, __unnamed_1@rel32@hi+24 s_add_u32 s16, s16, s18 s_addc_u32 s17, s17, s19 s_lshr_b32 s18, s2, 1 s_bfe_i32 s2, s2, 0x10000 s_add_i32 s18, s18, 4 v_mul_hi_u32 v7, v6, v7 s_add_i32 s19, s3, -1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v6, v6, v7 v_mul_hi_u32 v6, v8, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v6, v6, s5 v_sub_nc_u32_e32 v6, v8, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_subrev_nc_u32_e32 v7, s5, v6 v_cmp_le_u32_e64 s1, s5, v6 v_cndmask_b32_e64 v6, v6, v7, s1 v_add_co_u32 v10, s1, v0, 16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v11, s1, 0, v1, s1 v_subrev_nc_u32_e32 v7, s5, v6 v_cmp_le_u32_e64 s1, s5, v6 s_delay_alu instid0(VALU_DEP_1) v_cndmask_b32_e64 v8, v6, v7, s1 s_lshl_b32 s1, 1, s18 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_lshr_b32 s5, s1, 1 v_lshrrev_b32_e32 v15, 5, v8 s_and_b32 s18, s2, s5 s_mov_b32 s5, 0 s_add_i32 s18, s18, s1 .LBB5_647: ; Parent Loop BB5_3 Depth=1 ; Parent Loop BB5_6 Depth=2 ; => This Inner Loop Header: Depth=3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], 2, v[15:16] s_mov_b32 s21, -1 s_mov_b32 s20, exec_lo ; implicit-def: $vgpr12 v_add_co_u32 v8, s1, v10, v8 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v9, s1, v11, v9, s1 global_load_b32 v13, v[8:9], off glc s_waitcnt vmcnt(0) v_cmpx_ne_u32_e32 -1, v13 s_cbranch_execz .LBB5_651 ; %bb.648: ; in Loop: Header=BB5_647 Depth=3 v_not_b32_e32 v12, v13 s_mov_b32 s21, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ctz_i32_b32_e32 v12, v12 v_min_u32_e32 v13, 32, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_lshlrev_b32_e64 v12, v13, 1 global_atomic_or_b32 v8, v[8:9], v12, off glc s_waitcnt vmcnt(0) v_and_b32_e32 v8, v8, v12 v_mov_b32_e32 v12, 0 v_cmp_ne_u32_e64 s1, 0, v8 v_cmpx_eq_u32_e32 0, v8 s_cbranch_execz .LBB5_650 ; %bb.649: ; in Loop: Header=BB5_647 Depth=3 s_load_b32 s2, s[16:17], 0x0 v_lshl_add_u32 v6, v15, 5, v13 v_mov_b32_e32 v12, 2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mul_lo_u32 v6, v6, s18 s_waitcnt lgkmcnt(0) v_add_co_u32 v7, s2, v0, s2 v_add_co_ci_u32_e64 v8, s2, 0, v1, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v6, s2, v7, v6 v_add_co_ci_u32_e64 v7, s2, 0, v8, s2 .LBB5_650: ; in Loop: Header=BB5_647 Depth=3 s_or_b32 exec_lo, exec_lo, s21 s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) s_or_not1_b32 s21, s1, exec_lo .LBB5_651: ; %Flow788 ; in Loop: Header=BB5_647 Depth=3 s_or_b32 exec_lo, exec_lo, s20 s_and_saveexec_b32 s2, s21 s_cbranch_execz .LBB5_653 ; %bb.652: ; in Loop: Header=BB5_647 Depth=3 v_cvt_f32_u32_e32 v8, s3 s_sub_i32 s1, 0, s3 v_add_nc_u32_e32 v12, 1, v15 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v8, v8 s_waitcnt_depctr 0xfff v_mul_f32_e32 v8, 0x4f7ffffe, v8 v_cvt_u32_f32_e32 v8, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v9, s1, v8 v_mul_hi_u32 v9, v8, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v8, v8, v9 v_mul_hi_u32 v8, v12, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v8, v8, s3 v_sub_nc_u32_e32 v8, v12, v8 v_mov_b32_e32 v12, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_subrev_nc_u32_e32 v9, s3, v8 v_cmp_le_u32_e64 s1, s3, v8 v_cndmask_b32_e64 v8, v8, v9, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_subrev_nc_u32_e32 v9, s3, v8 v_cmp_le_u32_e64 s1, s3, v8 v_cndmask_b32_e64 v15, v8, v9, s1 .LBB5_653: ; in Loop: Header=BB5_647 Depth=3 s_or_b32 exec_lo, exec_lo, s2 v_cmp_ne_u32_e64 s1, 0, v12 s_cmp_eq_u32 s19, 0 s_cselect_b32 s2, -1, 0 s_add_i32 s19, s19, -1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s1, s1, s2 s_and_b32 s1, exec_lo, s1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s5, s1, s5 s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB5_647 ; %bb.654: ; %Flow789 ; in Loop: Header=BB5_6 Depth=2 s_or_b32 exec_lo, exec_lo, s5 .LBB5_655: ; %.loopexit193 ; in Loop: Header=BB5_6 Depth=2 v_cmp_ne_u64_e64 s1, 0, v[6:7] s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB5_658 ; %bb.656: ; in Loop: Header=BB5_6 Depth=2 s_mov_b32 s3, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mbcnt_lo_u32_b32 v0, s3, 0 v_cmp_eq_u32_e32 vcc_lo, 0, v0 s_and_b32 s5, exec_lo, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 exec_lo, s5 s_cbranch_execz .LBB5_658 ; %bb.657: ; in Loop: Header=BB5_6 Depth=2 s_bcnt1_i32_b32 s1, s1 s_bcnt1_i32_b32 s3, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s1, s1, s3 v_mov_b32_e32 v0, s1 global_atomic_add_u32 v16, v0, s[6:7] offset:16 .LBB5_658: ; in Loop: Header=BB5_6 Depth=2 s_or_b32 exec_lo, exec_lo, s2 v_mov_b32_e32 v0, 0 v_mov_b32_e32 v1, 0 s_mov_b32 s1, exec_lo v_cmpx_ne_u64_e32 0, v[6:7] ; %bb.659: ; in Loop: Header=BB5_6 Depth=2 v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v99, 0 v_dual_mov_b32 v100, 0 :: v_dual_mov_b32 v1, v7 ; %bb.660: ; %Flow ; in Loop: Header=BB5_6 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v6, v100 :: v_dual_mov_b32 v7, v99 .LBB5_661: ; %Flow792 ; in Loop: Header=BB5_6 Depth=2 s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v99, v7 .LBB5_662: ; %Flow1171 ; in Loop: Header=BB5_6 Depth=2 s_or_b32 exec_lo, exec_lo, s28 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mov_b32_e32 v7, v6 ;;#ASMSTART ;;#ASMEND v_cmp_ne_u32_e32 vcc_lo, 0, v7 s_cbranch_vccnz .LBB5_6 .LBB5_663: ; %Flow1173 ; in Loop: Header=BB5_3 Depth=1 s_or_b32 exec_lo, exec_lo, s27 v_mov_b32_e32 v6, v99 .LBB5_664: ; %.loopexit197 ; in Loop: Header=BB5_3 Depth=1 s_or_b32 exec_lo, exec_lo, s26 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mov_b32_e32 v7, v6 ;;#ASMSTART ;;#ASMEND v_cmp_ne_u32_e32 vcc_lo, 0, v7 s_cbranch_vccnz .LBB5_3 ; %bb.665: ; %Flow1175 ; implicit-def: $vgpr2_vgpr3 .LBB5_666: ; %Flow1194 s_and_not1_saveexec_b32 s1, s25 s_cbranch_execz .LBB5_699 ; %bb.667: s_load_b64 s[2:3], s[8:9], 0x50 v_mbcnt_lo_u32_b32 v0, -1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_readfirstlane_b32 s0, v0 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 v_cmp_eq_u32_e64 s0, s0, v0 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s4, s0 s_cbranch_execz .LBB5_673 ; %bb.668: v_mov_b32_e32 v1, 0 s_mov_b32 s5, exec_lo s_waitcnt lgkmcnt(0) global_load_b64 v[6:7], v1, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[4:5], v1, s[2:3] offset:40 global_load_b64 v[8:9], v1, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v4, v4, v6 v_and_b32_e32 v5, v5, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v10, v4, 24 v_mul_lo_u32 v5, v5, 24 v_mul_lo_u32 v4, v4, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v5, v10, v5 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v8, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo global_load_b64 v[4:5], v[4:5], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[8:9], v1, v[4:7], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[8:9], v[6:7] s_cbranch_execz .LBB5_672 ; %bb.669: ; %.preheader3.i.i.i.preheader s_mov_b32 s6, 0 .LBB5_670: ; %.preheader3.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[4:5], v1, s[2:3] offset:40 global_load_b64 v[10:11], v1, s[2:3] v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v4, v4, v6 v_and_b32_e32 v5, v5, v7 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11] v_mov_b32_e32 v4, v9 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5] global_load_b64 v[4:5], v[8:9], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[8:9], v1, v[4:7], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7] s_or_b32 s6, vcc_lo, s6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s6 s_cbranch_execnz .LBB5_670 ; %bb.671: ; %Flow1190 s_or_b32 exec_lo, exec_lo, s6 .LBB5_672: ; %Flow1192 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s5 .LBB5_673: ; %.loopexit4.i.i.i s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 v_mov_b32_e32 v1, 0 v_readfirstlane_b32 s4, v8 v_readfirstlane_b32 s5, v9 s_mov_b32 s11, exec_lo s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[10:11], v1, s[2:3] offset:40 global_load_b128 v[4:7], v1, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v10 v_readfirstlane_b32 s7, v11 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s10, s0 s_cbranch_execz .LBB5_675 ; %bb.674: v_dual_mov_b32 v8, s11 :: v_dual_mov_b32 v9, 0 s_mul_i32 s11, s7, 24 s_mul_hi_u32 s12, s6, 24 v_dual_mov_b32 v10, 3 :: v_dual_mov_b32 v11, 1 s_add_i32 s12, s12, s11 s_mul_i32 s11, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v12, vcc_lo, v4, s11 v_add_co_ci_u32_e32 v13, vcc_lo, s12, v5, vcc_lo global_store_b128 v[12:13], v[8:11], off offset:8 .LBB5_675: s_or_b32 exec_lo, exec_lo, s10 s_lshl_b64 s[10:11], s[6:7], 12 v_lshlrev_b64 v[8:9], 6, v[0:1] s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v6, s10 s_mov_b32 s12, 0 v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo s_mov_b32 s13, s12 s_mov_b32 s14, s12 s_mov_b32 s15, s12 v_mov_b32_e32 v0, 0 v_add_co_u32 v6, vcc_lo, v1, v8 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15 v_mov_b32_e32 v9, s13 v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v10, s14 s_clause 0x3 global_store_b128 v[6:7], v[0:3], off global_store_b128 v[6:7], v[8:11], off offset:16 global_store_b128 v[6:7], v[8:11], off offset:32 global_store_b128 v[6:7], v[8:11], off offset:48 s_and_saveexec_b32 s10, s0 s_cbranch_execz .LBB5_683 ; %bb.676: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4 v_mov_b32_e32 v12, s5 s_clause 0x1 global_load_b64 v[13:14], v10, s[2:3] offset:32 glc global_load_b64 v[0:1], v10, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s12, v0 v_readfirstlane_b32 s13, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[12:13], s[12:13], s[4:5] s_mul_i32 s11, s13, 24 s_mul_hi_u32 s13, s12, 24 s_mul_i32 s12, s12, 24 s_add_i32 s13, s13, s11 v_add_co_u32 v8, vcc_lo, v4, s12 v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo s_mov_b32 s11, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[13:14] s_cbranch_execz .LBB5_679 ; %bb.677: ; %.preheader1.i.i.i.preheader s_mov_b32 s12, 0 .LBB5_678: ; %.preheader1.i.i.i ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 s_sleep 1 global_store_b64 v[8:9], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s12, vcc_lo, s12 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s12 s_cbranch_execnz .LBB5_678 .LBB5_679: ; %Flow1188 s_or_b32 exec_lo, exec_lo, s11 v_mov_b32_e32 v0, 0 s_mov_b32 s12, exec_lo s_mov_b32 s11, exec_lo v_mbcnt_lo_u32_b32 v2, s12, 0 global_load_b64 v[0:1], v0, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB5_681 ; %bb.680: s_bcnt1_i32_b32 s12, s12 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s12 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB5_681: s_or_b32 exec_lo, exec_lo, s11 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB5_683 ; %bb.682: global_load_b32 v0, v[0:1], off offset:24 v_mov_b32_e32 v1, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s11, v0 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[0:1], off s_and_b32 m0, s11, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB5_683: ; %Flow1189 s_or_b32 exec_lo, exec_lo, s10 s_mul_i32 s7, s7, 24 s_mul_hi_u32 s10, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s10, s10, s7 v_add_co_u32 v0, vcc_lo, v4, s6 v_add_co_ci_u32_e32 v1, vcc_lo, s10, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo .LBB5_684: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s6, s0 s_cbranch_execz .LBB5_686 ; %bb.685: ; in Loop: Header=BB5_684 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 .LBB5_686: ; in Loop: Header=BB5_684 Depth=1 s_or_b32 exec_lo, exec_lo, s6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s6, v2 s_cmp_eq_u32 s6, 0 s_cbranch_scc1 .LBB5_688 ; %bb.687: ; in Loop: Header=BB5_684 Depth=1 s_mov_b32 s6, 0 s_sleep 1 s_branch .LBB5_689 .LBB5_688: ; in Loop: Header=BB5_684 Depth=1 s_mov_b32 s6, -1 .LBB5_689: ; %Flow1183 ; in Loop: Header=BB5_684 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s6 s_cbranch_vccnz .LBB5_684 ; %bb.690: global_load_b64 v[0:1], v[6:7], off s_and_saveexec_b32 s6, s0 s_cbranch_execz .LBB5_694 ; %bb.691: v_mov_b32_e32 v8, 0 s_clause 0x2 global_load_b64 v[4:5], v8, s[2:3] offset:40 global_load_b64 v[9:10], v8, s[2:3] offset:24 glc global_load_b64 v[6:7], v8, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v11, vcc_lo, v4, 1 v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, v11, s4 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11 v_and_b32_e32 v5, v3, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v4, v2, v4 v_mul_lo_u32 v5, v5, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v11, v4, 24 v_mul_lo_u32 v4, v4, 24 v_add_nc_u32_e32 v5, v11, v5 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, v6, v4 v_mov_b32_e32 v4, v9 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v5, v10 global_store_b64 v[6:7], v[9:10], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB5_694 ; %bb.692: ; %.preheader.i.i.i.preheader s_mov_b32 s0, 0 .LBB5_693: ; %.preheader.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5] v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB5_693 .LBB5_694: ; %__ockl_devmem_request.exit s_or_b32 exec_lo, exec_lo, s6 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s0, exec_lo s_waitcnt vmcnt(0) v_cmpx_ne_u64_e32 0, v[0:1] s_cbranch_execz .LBB5_698 ; %bb.695: s_mov_b32 s2, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mbcnt_lo_u32_b32 v2, s2, 0 v_cmp_eq_u32_e32 vcc_lo, 0, v2 s_and_b32 s3, exec_lo, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 exec_lo, s3 s_cbranch_execz .LBB5_698 ; %bb.696: s_mov_b32 s3, exec_lo s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mbcnt_lo_u32_b32 v2, s3, 0 v_cmp_eq_u32_e32 vcc_lo, 0, v2 s_and_b32 s4, exec_lo, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 exec_lo, s4 s_cbranch_execz .LBB5_698 ; %bb.697: s_load_b64 s[4:5], s[8:9], 0x60 s_bcnt1_i32_b32 s2, s2 s_bcnt1_i32_b32 s3, s3 v_mov_b32_e32 v4, 0x1a000 s_mul_i32 s2, s2, s3 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s2 s_waitcnt lgkmcnt(0) global_atomic_add_u64 v4, v[2:3], s[4:5] offset:2184 .LBB5_698: s_or_b32 exec_lo, exec_lo, s0 .LBB5_699: ; %Flow1195 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 .LBB5_700: ; %.loopexit198 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s24 v_readlane_b32 s30, v40, 7 v_readlane_b32 s31, v40, 8 v_readlane_b32 s40, v40, 6 v_readlane_b32 s39, v40, 5 v_readlane_b32 s38, v40, 4 v_readlane_b32 s37, v40, 3 v_readlane_b32 s36, v40, 2 v_readlane_b32 s35, v40, 1 v_readlane_b32 s34, v40, 0 s_or_saveexec_b32 s0, -1 scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload s_mov_b32 exec_lo, s0 s_waitcnt vmcnt(0) lgkmcnt(0) s_setpc_b64 s[30:31] .Lfunc_end5: .size __ockl_dm_alloc, .Lfunc_end5-__ockl_dm_alloc ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 24476 ; NumSgprs: 43 ; NumVgprs: 117 ; ScratchSize: 8 ; MemoryBound: 0 .text .p2align 2 ; -- Begin function _Z6unsafePmj .type _Z6unsafePmj,@function _Z6unsafePmj: ; @_Z6unsafePmj ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) s_mov_b32 s0, s33 s_mov_b32 s33, s32 s_or_saveexec_b32 s1, -1 scratch_store_b32 off, v46, s33 offset:40 ; 4-byte Folded Spill s_mov_b32 exec_lo, s1 v_writelane_b32 v46, s0, 22 s_add_i32 s32, s32, 48 s_clause 0x9 scratch_store_b32 off, v40, s33 offset:36 ; meta instruction scratch_store_b32 off, v41, s33 offset:32 ; meta instruction scratch_store_b32 off, v42, s33 offset:28 ; meta instruction scratch_store_b32 off, v43, s33 offset:24 ; meta instruction scratch_store_b32 off, v44, s33 offset:20 ; meta instruction scratch_store_b32 off, v45, s33 offset:16 ; meta instruction scratch_store_b32 off, v56, s33 offset:12 ; meta instruction scratch_store_b32 off, v57, s33 offset:8 ; meta instruction scratch_store_b32 off, v58, s33 offset:4 ; meta instruction scratch_store_b32 off, v59, s33 v_writelane_b32 v46, s34, 0 v_writelane_b32 v46, s35, 1 v_writelane_b32 v46, s36, 2 v_writelane_b32 v46, s37, 3 v_writelane_b32 v46, s38, 4 v_writelane_b32 v46, s39, 5 v_writelane_b32 v46, s40, 6 v_writelane_b32 v46, s41, 7 v_writelane_b32 v46, s42, 8 v_writelane_b32 v46, s43, 9 v_writelane_b32 v46, s44, 10 v_writelane_b32 v46, s45, 11 v_writelane_b32 v46, s46, 12 v_writelane_b32 v46, s47, 13 v_writelane_b32 v46, s48, 14 v_writelane_b32 v46, s49, 15 v_writelane_b32 v46, s50, 16 v_writelane_b32 v46, s51, 17 v_writelane_b32 v46, s52, 18 v_writelane_b32 v46, s53, 19 v_writelane_b32 v46, s30, 20 v_writelane_b32 v46, s31, 21 s_load_b32 s0, s[8:9], 0x0 v_mov_b32_e32 v117, v0 v_dual_mov_b32 v41, v31 :: v_dual_mov_b32 v118, v1 s_mov_b64 s[42:43], s[6:7] s_mov_b64 s[44:45], s[8:9] s_mov_b32 s41, s12 s_mov_b32 s50, s15 s_mov_b32 s51, s14 s_mov_b32 s52, s13 s_mov_b64 s[46:47], s[10:11] s_mov_b64 s[48:49], s[4:5] s_waitcnt lgkmcnt(0) s_cmp_lt_u32 s12, s0 s_cselect_b32 s0, 12, 18 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_dual_mov_b32 v119, v2 :: v_dual_mov_b32 v0, s0 global_load_u16 v128, v0, s[8:9] s_waitcnt vmcnt(0) v_cmp_ne_u16_e64 vcc_lo, 2, v128 v_cmp_eq_u16_e64 s53, 2, v128 s_and_b32 vcc_lo, exec_lo, vcc_lo s_cbranch_vccnz .LBB6_2 ; %bb.1: v_dual_mov_b32 v129, 0 :: v_dual_mov_b32 v0, 64 v_mov_b32_e32 v1, 0 s_mov_b64 s[8:9], s[44:45] s_getpc_b64 s[0:1] s_add_u32 s0, s0, __ockl_dm_alloc@rel32@lo+4 s_addc_u32 s1, s1, __ockl_dm_alloc@rel32@hi+12 s_delay_alu instid0(SALU_CYCLE_1) s_swappc_b64 s[30:31], s[0:1] ds_store_b64 v129, v[0:1] .LBB6_2: v_dual_mov_b32 v129, 0 :: v_dual_mov_b32 v0, 8 v_mov_b32_e32 v1, 0 s_mov_b64 s[8:9], s[44:45] s_getpc_b64 s[0:1] s_add_u32 s0, s0, __ockl_dm_alloc@rel32@lo+4 s_addc_u32 s1, s1, __ockl_dm_alloc@rel32@hi+12 s_delay_alu instid0(SALU_CYCLE_1) s_swappc_b64 s[30:31], s[0:1] s_getpc_b64 s[0:1] s_add_u32 s0, s0, _ZTV1D@rel32@lo+20 s_addc_u32 s1, s1, _ZTV1D@rel32@hi+28 v_dual_mov_b32 v58, v0 :: v_dual_mov_b32 v59, v1 v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ds_load_b64 v[2:3], v129 v_mbcnt_lo_u32_b32 v40, -1, 0 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 global_store_b64 v[58:59], v[0:1], off s_load_b64 s[34:35], s[44:45], 0x50 v_mov_b32_e32 v0, v40 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v0 v_cmp_eq_u32_e64 s0, s0, v0 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_8 ; %bb.3: s_waitcnt lgkmcnt(0) global_load_b64 v[6:7], v129, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[4:5], v129, s[34:35] offset:40 global_load_b64 v[8:9], v129, s[34:35] s_mov_b32 s2, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v1, v5, v7 v_and_b32_e32 v4, v4, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v1, v1, 24 v_mul_hi_u32 v5, v4, 24 v_mul_lo_u32 v4, v4, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v1, v5, v1 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v8, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, v9, v1, vcc_lo global_load_b64 v[4:5], v[4:5], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[8:9], v129, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[8:9], v[6:7] s_cbranch_execz .LBB6_7 ; %bb.4: ; %.preheader3.i.i.i.preheader v_mov_b32_e32 v1, 0 s_mov_b32 s3, 0 .p2align 6 .LBB6_5: ; %.preheader3.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[4:5], v1, s[34:35] offset:40 global_load_b64 v[10:11], v1, s[34:35] v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v4, v4, v6 v_and_b32_e32 v5, v5, v7 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11] v_mov_b32_e32 v4, v9 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5] global_load_b64 v[4:5], v[8:9], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[8:9], v1, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7] s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB6_5 ; %bb.6: ; %Flow1619 s_or_b32 exec_lo, exec_lo, s3 .LBB6_7: ; %Flow1621 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 .LBB6_8: ; %.loopexit4.i.i.i s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[10:11], v129, s[34:35] offset:40 global_load_b128 v[4:7], v129, s[34:35] v_readfirstlane_b32 s2, v8 v_readfirstlane_b32 s3, v9 s_mov_b32 s6, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s4, v10 v_readfirstlane_b32 s5, v11 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[4:5], s[2:3], s[4:5] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_10 ; %bb.9: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, 0 s_mul_i32 s6, s5, 24 s_mul_hi_u32 s7, s4, 24 v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s4, 24 s_waitcnt vmcnt(0) v_add_co_u32 v12, vcc_lo, v4, s6 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v5, vcc_lo global_store_b128 v[12:13], v[8:11], off offset:8 .LBB6_10: s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v1, 0 s_lshl_b64 s[6:7], s[4:5], 12 s_mov_b32 s8, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_mov_b32 s9, s8 v_lshlrev_b64 v[8:9], 6, v[0:1] s_waitcnt vmcnt(0) v_add_co_u32 v0, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_mov_b32_e32 v7, 0 v_add_co_u32 v10, vcc_lo, v0, v8 v_dual_mov_b32 v15, s11 :: v_dual_mov_b32 v14, s10 v_add_co_ci_u32_e32 v11, vcc_lo, v6, v9, vcc_lo v_mov_b32_e32 v6, 33 v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v13, s9 v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v12, s8 s_clause 0x3 global_store_b128 v[10:11], v[6:9], off global_store_b128 v[10:11], v[12:15], off offset:16 global_store_b128 v[10:11], v[12:15], off offset:32 global_store_b128 v[10:11], v[12:15], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_18 ; %bb.11: s_clause 0x1 global_load_b64 v[16:17], v1, s[34:35] offset:32 glc global_load_b64 v[6:7], v1, s[34:35] offset:40 v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v15, s3 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v6 v_readfirstlane_b32 s7, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[2:3] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s8, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s8, s8, s7 v_add_co_u32 v12, vcc_lo, v4, s6 v_add_co_ci_u32_e32 v13, vcc_lo, s8, v5, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[12:13], v[16:17], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v1, v[14:17], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[8:9], v[16:17] s_cbranch_execz .LBB6_14 ; %bb.12: ; %.preheader1.i.i.i.preheader v_mov_b32_e32 v0, 0 s_mov_b32 s7, 0 .LBB6_13: ; %.preheader1.i.i.i ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s3 s_sleep 1 global_store_b64 v[12:13], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB6_13 .LBB6_14: ; %Flow1617 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v0, 0 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v6, s7, 0 global_load_b64 v[0:1], v0, s[34:35] offset:16 v_cmpx_eq_u32_e32 0, v6 s_cbranch_execz .LBB6_16 ; %bb.15: s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[6:7], off offset:8 .LBB6_16: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[6:7], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7] s_cbranch_vccnz .LBB6_18 ; %bb.17: global_load_b32 v0, v[0:1], off offset:24 v_mov_b32_e32 v1, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v0 s_waitcnt_vscnt null, 0x0 global_store_b64 v[6:7], v[0:1], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_18: ; %Flow1618 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s5, 24 s_mul_hi_u32 s5, s4, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s5, s5, s1 s_mul_i32 s1, s4, 24 v_add_co_u32 v0, vcc_lo, v4, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB6_22 .p2align 6 .LBB6_19: ; in Loop: Header=BB6_22 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v4 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_21 ; %bb.20: ; in Loop: Header=BB6_22 Depth=1 s_sleep 1 s_cbranch_execnz .LBB6_22 s_branch .LBB6_24 .p2align 6 .LBB6_21: s_branch .LBB6_24 .LBB6_22: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v4, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_19 ; %bb.23: ; in Loop: Header=BB6_22 Depth=1 global_load_b32 v4, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v4, 1, v4 s_branch .LBB6_19 .LBB6_24: global_load_b64 v[0:1], v[10:11], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_28 ; %bb.25: v_mov_b32_e32 v10, 0 s_clause 0x2 global_load_b64 v[6:7], v10, s[34:35] offset:40 global_load_b64 v[11:12], v10, s[34:35] offset:24 glc global_load_b64 v[8:9], v10, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v13, vcc_lo, v6, 1 v_add_co_ci_u32_e32 v14, vcc_lo, 0, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, v13, s2 v_add_co_ci_u32_e32 v5, vcc_lo, s3, v14, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] v_dual_cndmask_b32 v5, v5, v14 :: v_dual_cndmask_b32 v4, v4, v13 v_and_b32_e32 v7, v5, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v6, v4, v6 v_mul_lo_u32 v7, v7, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v13, v6, 24 v_mul_lo_u32 v6, v6, 24 v_add_nc_u32_e32 v7, v13, v7 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v8, vcc_lo, v8, v6 v_mov_b32_e32 v6, v11 v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo v_mov_b32_e32 v7, v12 global_store_b64 v[8:9], v[11:12], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[6:7], v10, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[11:12] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_28 ; %bb.26: ; %.preheader.i.i.i.preheader s_mov_b32 s0, 0 .LBB6_27: ; %.preheader.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[8:9], v[6:7], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[11:12], v10, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[6:7] v_dual_mov_b32 v6, v11 :: v_dual_mov_b32 v7, v12 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_27 .LBB6_28: ; %__ockl_printf_begin.exit s_or_b32 exec_lo, exec_lo, s1 s_getpc_b64 s[2:3] s_add_u32 s2, s2, .str.1@rel32@lo+4 s_addc_u32 s3, s3, .str.1@rel32@hi+12 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u64 s[2:3], 0 s_cbranch_scc0 .LBB6_106 ; %bb.29: s_waitcnt vmcnt(0) v_dual_mov_b32 v25, 0 :: v_dual_and_b32 v24, 2, v0 v_and_b32_e32 v42, -3, v0 s_mov_b64 s[4:5], 21 v_mov_b32_e32 v43, v1 s_delay_alu instid0(VALU_DEP_3) v_dual_mov_b32 v27, v25 :: v_dual_mov_b32 v26, v24 s_branch .LBB6_31 .LBB6_30: ; %__ockl_hostcall_preview.exit20.i ; in Loop: Header=BB6_31 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_sub_u32 s4, s4, s6 s_subb_u32 s5, s5, s7 s_add_u32 s2, s2, s6 s_addc_u32 s3, s3, s7 s_cmp_lg_u64 s[4:5], 0 s_cbranch_scc0 .LBB6_107 .LBB6_31: ; =>This Loop Header: Depth=1 ; Child Loop BB6_34 Depth 2 ; Child Loop BB6_41 Depth 2 ; Child Loop BB6_48 Depth 2 ; Child Loop BB6_55 Depth 2 ; Child Loop BB6_62 Depth 2 ; Child Loop BB6_69 Depth 2 ; Child Loop BB6_76 Depth 2 ; Child Loop BB6_83 Depth 2 ; Child Loop BB6_91 Depth 2 ; Child Loop BB6_100 Depth 2 ; Child Loop BB6_105 Depth 2 v_cmp_lt_u64_e64 s0, s[4:5], 56 ; implicit-def: $vgpr6_vgpr7 ; implicit-def: $sgpr13 s_delay_alu instid0(VALU_DEP_1) s_and_b32 s0, s0, exec_lo s_cselect_b32 s6, s4, 56 s_cselect_b32 s7, s5, 0 s_cmp_gt_u32 s6, 7 s_mov_b32 s0, -1 s_cbranch_scc1 .LBB6_36 ; %bb.32: ; in Loop: Header=BB6_31 Depth=1 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_cmp_eq_u32 s6, 0 s_cbranch_scc1 .LBB6_35 ; %bb.33: ; %.preheader31.i.preheader ; in Loop: Header=BB6_31 Depth=1 s_lshl_b64 s[0:1], s[6:7], 3 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], s[2:3] .LBB6_34: ; %.preheader31.i ; Parent Loop BB6_31 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v4, v25, s[10:11] s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v4 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[4:5], s8, v[24:25] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_add_u32 s10, s10, 1 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s0, s8 v_or_b32_e32 v6, v4, v6 v_or_b32_e32 v7, v5, v7 s_cbranch_scc1 .LBB6_34 .LBB6_35: ; %Flow1588 ; in Loop: Header=BB6_31 Depth=1 s_mov_b32 s0, 0 s_mov_b32 s13, 0 .LBB6_36: ; %Flow1590 ; in Loop: Header=BB6_31 Depth=1 s_and_not1_b32 vcc_lo, exec_lo, s0 s_mov_b64 s[0:1], s[2:3] s_cbranch_vccnz .LBB6_38 ; %bb.37: ; in Loop: Header=BB6_31 Depth=1 global_load_b64 v[6:7], v25, s[2:3] s_add_i32 s13, s6, -8 s_add_u32 s0, s2, 8 s_addc_u32 s1, s3, 0 .LBB6_38: ; %.loopexit32.i ; in Loop: Header=BB6_31 Depth=1 s_cmp_gt_u32 s13, 7 s_cbranch_scc1 .LBB6_43 ; %bb.39: ; in Loop: Header=BB6_31 Depth=1 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 s_cmp_eq_u32 s13, 0 s_cbranch_scc1 .LBB6_42 ; %bb.40: ; %.preheader29.i.preheader ; in Loop: Header=BB6_31 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_41: ; %.preheader29.i ; Parent Loop BB6_31 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v4, v25, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], s8, v[24:25] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s13, s10 v_or_b32_e32 v8, v4, v8 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v9, v5, v9 s_cbranch_scc1 .LBB6_41 .LBB6_42: ; %Flow1583 ; in Loop: Header=BB6_31 Depth=1 s_mov_b32 s12, 0 s_cbranch_execz .LBB6_44 s_branch .LBB6_45 .LBB6_43: ; in Loop: Header=BB6_31 Depth=1 ; implicit-def: $vgpr8_vgpr9 ; implicit-def: $sgpr12 .LBB6_44: ; in Loop: Header=BB6_31 Depth=1 global_load_b64 v[8:9], v25, s[0:1] s_add_i32 s12, s13, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_45: ; %.loopexit30.i ; in Loop: Header=BB6_31 Depth=1 s_cmp_gt_u32 s12, 7 s_cbranch_scc1 .LBB6_50 ; %bb.46: ; in Loop: Header=BB6_31 Depth=1 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_cmp_eq_u32 s12, 0 s_cbranch_scc1 .LBB6_49 ; %bb.47: ; %.preheader27.i.preheader ; in Loop: Header=BB6_31 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_48: ; %.preheader27.i ; Parent Loop BB6_31 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v4, v25, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], s8, v[24:25] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s12, s10 v_or_b32_e32 v10, v4, v10 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v11, v5, v11 s_cbranch_scc1 .LBB6_48 .LBB6_49: ; %Flow1578 ; in Loop: Header=BB6_31 Depth=1 s_mov_b32 s13, 0 s_cbranch_execz .LBB6_51 s_branch .LBB6_52 .LBB6_50: ; in Loop: Header=BB6_31 Depth=1 ; implicit-def: $sgpr13 .LBB6_51: ; in Loop: Header=BB6_31 Depth=1 global_load_b64 v[10:11], v25, s[0:1] s_add_i32 s13, s12, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_52: ; %.loopexit28.i ; in Loop: Header=BB6_31 Depth=1 s_cmp_gt_u32 s13, 7 s_cbranch_scc1 .LBB6_57 ; %bb.53: ; in Loop: Header=BB6_31 Depth=1 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_cmp_eq_u32 s13, 0 s_cbranch_scc1 .LBB6_56 ; %bb.54: ; %.preheader25.i.preheader ; in Loop: Header=BB6_31 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_55: ; %.preheader25.i ; Parent Loop BB6_31 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v4, v25, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], s8, v[24:25] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s13, s10 v_or_b32_e32 v12, v4, v12 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v13, v5, v13 s_cbranch_scc1 .LBB6_55 .LBB6_56: ; %Flow1573 ; in Loop: Header=BB6_31 Depth=1 s_mov_b32 s12, 0 s_cbranch_execz .LBB6_58 s_branch .LBB6_59 .LBB6_57: ; in Loop: Header=BB6_31 Depth=1 ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $sgpr12 .LBB6_58: ; in Loop: Header=BB6_31 Depth=1 global_load_b64 v[12:13], v25, s[0:1] s_add_i32 s12, s13, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_59: ; %.loopexit26.i ; in Loop: Header=BB6_31 Depth=1 s_cmp_gt_u32 s12, 7 s_cbranch_scc1 .LBB6_64 ; %bb.60: ; in Loop: Header=BB6_31 Depth=1 v_mov_b32_e32 v14, 0 v_mov_b32_e32 v15, 0 s_cmp_eq_u32 s12, 0 s_cbranch_scc1 .LBB6_63 ; %bb.61: ; %.preheader23.i.preheader ; in Loop: Header=BB6_31 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_62: ; %.preheader23.i ; Parent Loop BB6_31 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v4, v25, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], s8, v[24:25] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s12, s10 v_or_b32_e32 v14, v4, v14 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v15, v5, v15 s_cbranch_scc1 .LBB6_62 .LBB6_63: ; %Flow1568 ; in Loop: Header=BB6_31 Depth=1 s_mov_b32 s13, 0 s_cbranch_execz .LBB6_65 s_branch .LBB6_66 .LBB6_64: ; in Loop: Header=BB6_31 Depth=1 ; implicit-def: $sgpr13 .LBB6_65: ; in Loop: Header=BB6_31 Depth=1 global_load_b64 v[14:15], v25, s[0:1] s_add_i32 s13, s12, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_66: ; %.loopexit24.i ; in Loop: Header=BB6_31 Depth=1 s_cmp_gt_u32 s13, 7 s_cbranch_scc1 .LBB6_71 ; %bb.67: ; in Loop: Header=BB6_31 Depth=1 v_mov_b32_e32 v16, 0 v_mov_b32_e32 v17, 0 s_cmp_eq_u32 s13, 0 s_cbranch_scc1 .LBB6_70 ; %bb.68: ; %.preheader21.i.preheader ; in Loop: Header=BB6_31 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_69: ; %.preheader21.i ; Parent Loop BB6_31 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v4, v25, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], s8, v[24:25] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s13, s10 v_or_b32_e32 v16, v4, v16 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v17, v5, v17 s_cbranch_scc1 .LBB6_69 .LBB6_70: ; %Flow1563 ; in Loop: Header=BB6_31 Depth=1 s_mov_b32 s12, 0 s_cbranch_execz .LBB6_72 s_branch .LBB6_73 .LBB6_71: ; in Loop: Header=BB6_31 Depth=1 ; implicit-def: $vgpr16_vgpr17 ; implicit-def: $sgpr12 .LBB6_72: ; in Loop: Header=BB6_31 Depth=1 global_load_b64 v[16:17], v25, s[0:1] s_add_i32 s12, s13, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_73: ; %.loopexit22.i ; in Loop: Header=BB6_31 Depth=1 s_cmp_gt_u32 s12, 7 s_cbranch_scc1 .LBB6_78 ; %bb.74: ; in Loop: Header=BB6_31 Depth=1 v_mov_b32_e32 v18, 0 v_mov_b32_e32 v19, 0 s_cmp_eq_u32 s12, 0 s_cbranch_scc1 .LBB6_77 ; %bb.75: ; %.preheader.i.preheader ; in Loop: Header=BB6_31 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], s[0:1] .LBB6_76: ; %.preheader.i ; Parent Loop BB6_31 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v4, v25, s[10:11] s_add_i32 s12, s12, -1 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v4 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[4:5], s8, v[24:25] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_add_u32 s10, s10, 1 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s12, 0 v_or_b32_e32 v18, v4, v18 v_or_b32_e32 v19, v5, v19 s_cbranch_scc1 .LBB6_76 .LBB6_77: ; %Flow1558 ; in Loop: Header=BB6_31 Depth=1 s_cbranch_execz .LBB6_79 s_branch .LBB6_80 .LBB6_78: ; in Loop: Header=BB6_31 Depth=1 .LBB6_79: ; in Loop: Header=BB6_31 Depth=1 global_load_b64 v[18:19], v25, s[0:1] .LBB6_80: ; %.loopexit.i ; in Loop: Header=BB6_31 Depth=1 v_mov_b32_e32 v24, v40 v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v24 v_cmp_eq_u32_e64 s0, s0, v24 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_86 ; %bb.81: ; in Loop: Header=BB6_31 Depth=1 global_load_b64 v[22:23], v25, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[4:5], v25, s[34:35] offset:40 global_load_b64 v[20:21], v25, s[34:35] s_mov_b32 s8, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v5, v5, v23 v_and_b32_e32 v4, v4, v22 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v5, v5, 24 v_mul_hi_u32 v28, v4, 24 v_mul_lo_u32 v4, v4, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v5, v28, v5 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v20, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, v21, v5, vcc_lo global_load_b64 v[20:21], v[4:5], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[4:5], v25, v[20:23], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[4:5], v[22:23] s_cbranch_execz .LBB6_85 ; %bb.82: ; %.preheader3.i.i19.i.preheader ; in Loop: Header=BB6_31 Depth=1 s_mov_b32 s9, 0 .p2align 6 .LBB6_83: ; %.preheader3.i.i19.i ; Parent Loop BB6_31 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 s_clause 0x1 global_load_b64 v[20:21], v25, s[34:35] offset:40 global_load_b64 v[28:29], v25, s[34:35] v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v20, v20, v22 s_waitcnt vmcnt(0) v_mad_u64_u32 v[4:5], null, v20, 24, v[28:29] v_and_b32_e32 v28, v21, v23 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[20:21], null, v28, 24, v[5:6] v_mov_b32_e32 v5, v20 global_load_b64 v[20:21], v[4:5], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[4:5], v25, v[20:23], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[22:23] s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB6_83 ; %bb.84: ; %Flow1553 ; in Loop: Header=BB6_31 Depth=1 s_or_b32 exec_lo, exec_lo, s9 .LBB6_85: ; %Flow1555 ; in Loop: Header=BB6_31 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s8 .LBB6_86: ; %.loopexit4.i.i14.i ; in Loop: Header=BB6_31 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_clause 0x1 global_load_b64 v[28:29], v25, s[34:35] offset:40 global_load_b128 v[20:23], v25, s[34:35] v_readfirstlane_b32 s8, v4 v_readfirstlane_b32 s9, v5 s_mov_b32 s12, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s10, v28 v_readfirstlane_b32 s11, v29 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[10:11], s[8:9], s[10:11] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_88 ; %bb.87: ; in Loop: Header=BB6_31 Depth=1 v_dual_mov_b32 v28, s12 :: v_dual_mov_b32 v29, 0 s_mul_i32 s12, s11, 24 s_mul_hi_u32 s13, s10, 24 v_dual_mov_b32 v30, 2 :: v_dual_mov_b32 v31, 1 s_add_i32 s13, s13, s12 s_mul_i32 s12, s10, 24 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v20, s12 v_add_co_ci_u32_e32 v5, vcc_lo, s13, v21, vcc_lo global_store_b128 v[4:5], v[28:31], off offset:8 .LBB6_88: ; in Loop: Header=BB6_31 Depth=1 s_or_b32 exec_lo, exec_lo, s1 v_cmp_gt_u64_e64 vcc_lo, s[4:5], 56 v_or_b32_e32 v4, v43, v27 v_or_b32_e32 v28, v42, v26 s_lshl_b64 s[12:13], s[10:11], 12 s_lshl_b32 s1, s6, 2 s_delay_alu instid0(SALU_CYCLE_1) s_add_i32 s1, s1, 28 v_cndmask_b32_e32 v5, v4, v43, vcc_lo v_cndmask_b32_e32 v4, v28, v42, vcc_lo v_lshlrev_b64 v[28:29], 6, v[24:25] s_waitcnt vmcnt(0) v_add_co_u32 v22, vcc_lo, v22, s12 v_add_co_ci_u32_e32 v23, vcc_lo, s13, v23, vcc_lo s_and_b32 s1, s1, 0x1e0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v22, vcc_lo, v22, v28 v_and_or_b32 v4, v4, 0xffffff1f, s1 v_add_co_ci_u32_e32 v23, vcc_lo, v23, v29, vcc_lo s_clause 0x3 global_store_b128 v[22:23], v[4:7], off global_store_b128 v[22:23], v[8:11], off offset:16 global_store_b128 v[22:23], v[12:15], off offset:32 global_store_b128 v[22:23], v[16:19], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_96 ; %bb.89: ; in Loop: Header=BB6_31 Depth=1 s_clause 0x1 global_load_b64 v[12:13], v25, s[34:35] offset:32 glc global_load_b64 v[4:5], v25, s[34:35] offset:40 v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9 s_waitcnt vmcnt(0) v_readfirstlane_b32 s12, v4 v_readfirstlane_b32 s13, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[12:13], s[12:13], s[8:9] s_mul_i32 s13, s13, 24 s_mul_hi_u32 s14, s12, 24 s_mul_i32 s12, s12, 24 s_add_i32 s14, s14, s13 v_add_co_u32 v8, vcc_lo, v20, s12 v_add_co_ci_u32_e32 v9, vcc_lo, s14, v21, vcc_lo s_mov_b32 s12, exec_lo global_store_b64 v[8:9], v[12:13], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[6:7], v25, v[10:13], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[6:7], v[12:13] s_cbranch_execz .LBB6_92 ; %bb.90: ; %.preheader1.i.i17.i.preheader ; in Loop: Header=BB6_31 Depth=1 s_mov_b32 s13, 0 .LBB6_91: ; %.preheader1.i.i17.i ; Parent Loop BB6_31 Depth=1 ; => This Inner Loop Header: Depth=2 v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9 s_sleep 1 global_store_b64 v[8:9], v[6:7], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v25, v[4:7], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7] v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4 s_or_b32 s13, vcc_lo, s13 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s13 s_cbranch_execnz .LBB6_91 .LBB6_92: ; %Flow1551 ; in Loop: Header=BB6_31 Depth=1 s_or_b32 exec_lo, exec_lo, s12 global_load_b64 v[4:5], v25, s[34:35] offset:16 s_mov_b32 s13, exec_lo s_mov_b32 s12, exec_lo v_mbcnt_lo_u32_b32 v6, s13, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v6 s_cbranch_execz .LBB6_94 ; %bb.93: ; in Loop: Header=BB6_31 Depth=1 s_bcnt1_i32_b32 s13, s13 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, s13 s_waitcnt vmcnt(0) global_atomic_add_u64 v[4:5], v[6:7], off offset:8 .LBB6_94: ; in Loop: Header=BB6_31 Depth=1 s_or_b32 exec_lo, exec_lo, s12 s_waitcnt vmcnt(0) global_load_b64 v[6:7], v[4:5], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7] s_cbranch_vccnz .LBB6_96 ; %bb.95: ; in Loop: Header=BB6_31 Depth=1 global_load_b32 v24, v[4:5], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s12, v24 s_waitcnt_vscnt null, 0x0 global_store_b64 v[6:7], v[24:25], off s_and_b32 m0, s12, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_96: ; %Flow1552 ; in Loop: Header=BB6_31 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s11, 24 s_mul_hi_u32 s11, s10, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s11, s11, s1 s_mul_i32 s1, s10, 24 v_add_co_u32 v4, vcc_lo, v20, s1 v_add_co_ci_u32_e32 v5, vcc_lo, s11, v21, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, v4, 20 v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo s_branch .LBB6_100 .p2align 6 .LBB6_97: ; in Loop: Header=BB6_100 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v6 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_99 ; %bb.98: ; in Loop: Header=BB6_100 Depth=2 s_sleep 1 s_cbranch_execnz .LBB6_100 s_branch .LBB6_102 .p2align 6 .LBB6_99: ; in Loop: Header=BB6_31 Depth=1 s_branch .LBB6_102 .LBB6_100: ; Parent Loop BB6_31 Depth=1 ; => This Inner Loop Header: Depth=2 v_mov_b32_e32 v6, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_97 ; %bb.101: ; in Loop: Header=BB6_100 Depth=2 global_load_b32 v6, v[4:5], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v6, 1, v6 s_branch .LBB6_97 .LBB6_102: ; in Loop: Header=BB6_31 Depth=1 global_load_b64 v[42:43], v[22:23], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_30 ; %bb.103: ; in Loop: Header=BB6_31 Depth=1 s_clause 0x2 global_load_b64 v[6:7], v25, s[34:35] offset:40 global_load_b64 v[10:11], v25, s[34:35] offset:24 glc global_load_b64 v[8:9], v25, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v12, vcc_lo, v6, 1 v_add_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, v12, s8 v_add_co_ci_u32_e32 v5, vcc_lo, s9, v13, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12 v_and_b32_e32 v7, v5, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v6, v4, v6 v_mul_hi_u32 v12, v6, 24 v_mul_lo_u32 v6, v6, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v8, vcc_lo, v8, v6 v_mov_b32_e32 v6, v10 v_mul_lo_u32 v7, v7, 24 v_add_nc_u32_e32 v7, v12, v7 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo v_mov_b32_e32 v7, v11 global_store_b64 v[8:9], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[6:7], v25, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[10:11] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_30 ; %bb.104: ; %.preheader.i.i16.i.preheader ; in Loop: Header=BB6_31 Depth=1 s_mov_b32 s0, 0 .LBB6_105: ; %.preheader.i.i16.i ; Parent Loop BB6_31 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 global_store_b64 v[8:9], v[6:7], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v25, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7] v_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_105 s_branch .LBB6_30 .LBB6_106: ; implicit-def: $vgpr42_vgpr43 s_cbranch_execnz .LBB6_108 s_branch .LBB6_135 .LBB6_107: ; %Flow1591 s_branch .LBB6_135 .LBB6_108: v_mov_b32_e32 v8, v40 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v8 v_cmp_eq_u32_e64 s0, s0, v8 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_114 ; %bb.109: v_mov_b32_e32 v4, 0 s_mov_b32 s2, exec_lo global_load_b64 v[12:13], v4, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[5:6], v4, s[34:35] offset:40 global_load_b64 v[9:10], v4, s[34:35] s_waitcnt vmcnt(1) v_and_b32_e32 v5, v5, v12 v_and_b32_e32 v6, v6, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v7, v5, 24 v_mul_lo_u32 v6, v6, 24 v_mul_lo_u32 v5, v5, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v6, v7, v6 s_waitcnt vmcnt(0) v_add_co_u32 v5, vcc_lo, v9, v5 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo global_load_b64 v[10:11], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v4, v[10:13], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[10:11], v[12:13] s_cbranch_execz .LBB6_113 ; %bb.110: ; %.preheader3.i.i.i31.preheader s_mov_b32 s3, 0 .p2align 6 .LBB6_111: ; %.preheader3.i.i.i31 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[5:6], v4, s[34:35] offset:40 global_load_b64 v[14:15], v4, s[34:35] v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v5, v5, v12 v_and_b32_e32 v11, v6, v13 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[9:10], null, v5, 24, v[14:15] v_mov_b32_e32 v5, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, v11, 24, v[5:6] v_mov_b32_e32 v10, v6 global_load_b64 v[10:11], v[9:10], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v4, v[10:13], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13] s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB6_111 ; %bb.112: ; %Flow1603 s_or_b32 exec_lo, exec_lo, s3 .LBB6_113: ; %Flow1605 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 .LBB6_114: ; %.loopexit4.i.i.i26 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v9, 0 v_readfirstlane_b32 s2, v10 v_readfirstlane_b32 s3, v11 s_mov_b32 s6, exec_lo s_clause 0x1 global_load_b64 v[12:13], v9, s[34:35] offset:40 global_load_b128 v[4:7], v9, s[34:35] s_waitcnt vmcnt(1) v_readfirstlane_b32 s4, v12 v_readfirstlane_b32 s5, v13 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[4:5], s[2:3], s[4:5] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_116 ; %bb.115: v_dual_mov_b32 v10, s6 :: v_dual_mov_b32 v11, 0 s_mul_i32 s6, s5, 24 s_mul_hi_u32 s7, s4, 24 v_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s4, 24 s_waitcnt vmcnt(0) v_add_co_u32 v14, vcc_lo, v4, s6 v_add_co_ci_u32_e32 v15, vcc_lo, s7, v5, vcc_lo global_store_b128 v[14:15], v[10:13], off offset:8 .LBB6_116: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[6:7], s[4:5], 12 s_mov_b32 s8, 0 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v7, vcc_lo v_lshlrev_b64 v[6:7], 6, v[8:9] s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_mov_b32_e32 v12, 0 v_and_or_b32 v0, v0, 0xffffff1f, 32 v_add_co_u32 v10, vcc_lo, v10, v6 v_add_co_ci_u32_e32 v11, vcc_lo, v11, v7, vcc_lo v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v9, s11 v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, s10 v_mov_b32_e32 v13, v12 s_clause 0x4 global_store_b64 v[10:11], v[0:1], off global_store_b128 v[10:11], v[6:9], off offset:8 global_store_b128 v[10:11], v[6:9], off offset:24 global_store_b128 v[10:11], v[6:9], off offset:40 global_store_b64 v[10:11], v[12:13], off offset:56 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_124 ; %bb.117: v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, s2 v_mov_b32_e32 v14, s3 s_clause 0x1 global_load_b64 v[15:16], v12, s[34:35] offset:32 glc global_load_b64 v[0:1], v12, s[34:35] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v0 v_readfirstlane_b32 s7, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[2:3] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s8, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s8, s8, s7 v_add_co_u32 v0, vcc_lo, v4, s6 v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[0:1], v[15:16], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v12, v[13:16], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[8:9], v[15:16] s_cbranch_execz .LBB6_120 ; %bb.118: ; %.preheader1.i.i.i29.preheader s_mov_b32 s7, 0 .LBB6_119: ; %.preheader1.i.i.i29 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s3 s_sleep 1 global_store_b64 v[0:1], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[6:7], v12, v[6:9], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB6_119 .LBB6_120: ; %Flow1601 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v0, 0 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v6, s7, 0 global_load_b64 v[0:1], v0, s[34:35] offset:16 v_cmpx_eq_u32_e32 0, v6 s_cbranch_execz .LBB6_122 ; %bb.121: s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[6:7], off offset:8 .LBB6_122: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[6:7], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7] s_cbranch_vccnz .LBB6_124 ; %bb.123: global_load_b32 v0, v[0:1], off offset:24 v_mov_b32_e32 v1, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v0 s_waitcnt_vscnt null, 0x0 global_store_b64 v[6:7], v[0:1], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_124: ; %Flow1602 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s5, 24 s_mul_hi_u32 s5, s4, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s5, s5, s1 s_mul_i32 s1, s4, 24 v_add_co_u32 v0, vcc_lo, v4, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB6_128 .p2align 6 .LBB6_125: ; in Loop: Header=BB6_128 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v4 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_127 ; %bb.126: ; in Loop: Header=BB6_128 Depth=1 s_sleep 1 s_cbranch_execnz .LBB6_128 s_branch .LBB6_130 .p2align 6 .LBB6_127: s_branch .LBB6_130 .LBB6_128: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v4, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_125 ; %bb.129: ; in Loop: Header=BB6_128 Depth=1 global_load_b32 v4, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v4, 1, v4 s_branch .LBB6_125 .LBB6_130: global_load_b64 v[42:43], v[10:11], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_134 ; %bb.131: v_mov_b32_e32 v8, 0 s_clause 0x2 global_load_b64 v[0:1], v8, s[34:35] offset:40 global_load_b64 v[9:10], v8, s[34:35] offset:24 glc global_load_b64 v[6:7], v8, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v11, vcc_lo, v0, 1 v_add_co_ci_u32_e32 v12, vcc_lo, 0, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, v11, s2 v_add_co_ci_u32_e32 v5, vcc_lo, s3, v12, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] v_dual_cndmask_b32 v5, v5, v12 :: v_dual_cndmask_b32 v4, v4, v11 v_and_b32_e32 v1, v5, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v0, v4, v0 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v11, v0, 24 v_mul_lo_u32 v0, v0, 24 v_add_nc_u32_e32 v1, v11, v1 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v0, vcc_lo, v6, v0 v_mov_b32_e32 v6, v9 v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo v_mov_b32_e32 v7, v10 global_store_b64 v[0:1], v[9:10], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[6:7], v8, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[9:10] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_134 ; %bb.132: ; %.preheader.i.i.i28.preheader s_mov_b32 s0, 0 .LBB6_133: ; %.preheader.i.i.i28 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[0:1], v[6:7], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[9:10], v8, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[6:7] v_dual_mov_b32 v6, v9 :: v_dual_mov_b32 v7, v10 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_133 .LBB6_134: ; %__ockl_hostcall_preview.exit.i s_or_b32 exec_lo, exec_lo, s1 .LBB6_135: ; %__ockl_printf_append_string_n.exit s_waitcnt vmcnt(0) v_mov_b32_e32 v0, v40 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v0 v_cmp_eq_u32_e64 s0, s0, v0 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_141 ; %bb.136: v_mov_b32_e32 v1, 0 s_mov_b32 s2, exec_lo global_load_b64 v[6:7], v1, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[4:5], v1, s[34:35] offset:40 global_load_b64 v[8:9], v1, s[34:35] s_waitcnt vmcnt(1) v_and_b32_e32 v4, v4, v6 v_and_b32_e32 v5, v5, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v10, v4, 24 v_mul_lo_u32 v5, v5, 24 v_mul_lo_u32 v4, v4, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v5, v10, v5 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v8, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo global_load_b64 v[4:5], v[4:5], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[8:9], v1, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[8:9], v[6:7] s_cbranch_execz .LBB6_140 ; %bb.137: ; %.preheader3.i.i.i38.preheader s_mov_b32 s3, 0 .p2align 6 .LBB6_138: ; %.preheader3.i.i.i38 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[4:5], v1, s[34:35] offset:40 global_load_b64 v[10:11], v1, s[34:35] v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v4, v4, v6 v_and_b32_e32 v5, v5, v7 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11] v_mov_b32_e32 v4, v9 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5] global_load_b64 v[4:5], v[8:9], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[8:9], v1, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7] s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB6_138 ; %bb.139: ; %Flow1539 s_or_b32 exec_lo, exec_lo, s3 .LBB6_140: ; %Flow1541 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 .LBB6_141: ; %.loopexit4.i.i.i32 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v1, 0 v_readfirstlane_b32 s2, v8 v_readfirstlane_b32 s3, v9 s_mov_b32 s6, exec_lo s_clause 0x1 global_load_b64 v[10:11], v1, s[34:35] offset:40 global_load_b128 v[4:7], v1, s[34:35] s_waitcnt vmcnt(1) v_readfirstlane_b32 s4, v10 v_readfirstlane_b32 s5, v11 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[4:5], s[2:3], s[4:5] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_143 ; %bb.142: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, 0 s_mul_i32 s6, s5, 24 s_mul_hi_u32 s7, s4, 24 v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s4, 24 s_waitcnt vmcnt(0) v_add_co_u32 v12, vcc_lo, v4, s6 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v5, vcc_lo global_store_b128 v[12:13], v[8:11], off offset:8 .LBB6_143: s_or_b32 exec_lo, exec_lo, s1 v_dual_mov_b32 v45, 0 :: v_dual_and_b32 v44, 0xffff, v128 s_mov_b32 s8, 0 s_lshl_b64 s[6:7], s[4:5], 12 s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_mov_b32_e32 v1, v45 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b64 v[0:1], 6, v[0:1] v_and_or_b32 v42, v42, 0xffffff1f, 32 v_add_co_u32 v0, vcc_lo, v6, v0 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9 v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11 s_clause 0x3 global_store_b128 v[0:1], v[42:45], off global_store_b128 v[0:1], v[6:9], off offset:16 global_store_b128 v[0:1], v[6:9], off offset:32 global_store_b128 v[0:1], v[6:9], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_151 ; %bb.144: v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, s2 v_mov_b32_e32 v14, s3 s_clause 0x1 global_load_b64 v[15:16], v12, s[34:35] offset:32 glc global_load_b64 v[6:7], v12, s[34:35] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v6 v_readfirstlane_b32 s7, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[2:3] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s8, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s8, s8, s7 v_add_co_u32 v10, vcc_lo, v4, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s8, v5, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[10:11], v[15:16], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v12, v[13:16], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[8:9], v[15:16] s_cbranch_execz .LBB6_147 ; %bb.145: ; %.preheader1.i.i.i36.preheader s_mov_b32 s7, 0 .LBB6_146: ; %.preheader1.i.i.i36 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s3 s_sleep 1 global_store_b64 v[10:11], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[6:7], v12, v[6:9], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB6_146 .LBB6_147: ; %Flow1537 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v6, 0 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v8, s7, 0 global_load_b64 v[6:7], v6, s[34:35] offset:16 v_cmpx_eq_u32_e32 0, v8 s_cbranch_execz .LBB6_149 ; %bb.148: s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[6:7], v[8:9], off offset:8 .LBB6_149: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[8:9], v[6:7], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9] s_cbranch_vccnz .LBB6_151 ; %bb.150: global_load_b32 v6, v[6:7], off offset:24 v_mov_b32_e32 v7, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v6 s_waitcnt_vscnt null, 0x0 global_store_b64 v[8:9], v[6:7], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_151: ; %Flow1538 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s5, 24 s_mul_hi_u32 s5, s4, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s5, s5, s1 s_mul_i32 s1, s4, 24 v_add_co_u32 v4, vcc_lo, v4, s1 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, v4, 20 v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo s_branch .LBB6_155 .p2align 6 .LBB6_152: ; in Loop: Header=BB6_155 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v6 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_154 ; %bb.153: ; in Loop: Header=BB6_155 Depth=1 s_sleep 1 s_cbranch_execnz .LBB6_155 s_branch .LBB6_157 .p2align 6 .LBB6_154: s_branch .LBB6_157 .LBB6_155: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v6, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_152 ; %bb.156: ; in Loop: Header=BB6_155 Depth=1 global_load_b32 v6, v[4:5], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v6, 1, v6 s_branch .LBB6_152 .LBB6_157: global_load_b64 v[0:1], v[0:1], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_161 ; %bb.158: v_mov_b32_e32 v10, 0 s_clause 0x2 global_load_b64 v[6:7], v10, s[34:35] offset:40 global_load_b64 v[11:12], v10, s[34:35] offset:24 glc global_load_b64 v[8:9], v10, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v13, vcc_lo, v6, 1 v_add_co_ci_u32_e32 v14, vcc_lo, 0, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, v13, s2 v_add_co_ci_u32_e32 v5, vcc_lo, s3, v14, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] v_dual_cndmask_b32 v5, v5, v14 :: v_dual_cndmask_b32 v4, v4, v13 v_and_b32_e32 v7, v5, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v6, v4, v6 v_mul_lo_u32 v7, v7, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v13, v6, 24 v_mul_lo_u32 v6, v6, 24 v_add_nc_u32_e32 v7, v13, v7 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v8, vcc_lo, v8, v6 v_mov_b32_e32 v6, v11 v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo v_mov_b32_e32 v7, v12 global_store_b64 v[8:9], v[11:12], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[6:7], v10, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[11:12] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_161 ; %bb.159: ; %.preheader.i.i.i35.preheader s_mov_b32 s0, 0 .LBB6_160: ; %.preheader.i.i.i35 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[8:9], v[6:7], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[11:12], v10, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[6:7] v_dual_mov_b32 v6, v11 :: v_dual_mov_b32 v7, v12 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_160 .LBB6_161: ; %__ockl_printf_append_args.exit s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v8, v40 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v8 v_cmp_eq_u32_e64 s0, s0, v8 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_167 ; %bb.162: v_mov_b32_e32 v4, 0 s_mov_b32 s2, exec_lo global_load_b64 v[12:13], v4, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[5:6], v4, s[34:35] offset:40 global_load_b64 v[9:10], v4, s[34:35] s_waitcnt vmcnt(1) v_and_b32_e32 v5, v5, v12 v_and_b32_e32 v6, v6, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v7, v5, 24 v_mul_lo_u32 v6, v6, 24 v_mul_lo_u32 v5, v5, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v6, v7, v6 s_waitcnt vmcnt(0) v_add_co_u32 v5, vcc_lo, v9, v5 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo global_load_b64 v[10:11], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v4, v[10:13], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[10:11], v[12:13] s_cbranch_execz .LBB6_166 ; %bb.163: ; %.preheader3.i.i.i45.preheader s_mov_b32 s3, 0 .p2align 6 .LBB6_164: ; %.preheader3.i.i.i45 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[5:6], v4, s[34:35] offset:40 global_load_b64 v[14:15], v4, s[34:35] v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v5, v5, v12 v_and_b32_e32 v11, v6, v13 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[9:10], null, v5, 24, v[14:15] v_mov_b32_e32 v5, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, v11, 24, v[5:6] v_mov_b32_e32 v10, v6 global_load_b64 v[10:11], v[9:10], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[10:11], v4, v[10:13], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13] s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB6_164 ; %bb.165: ; %Flow1525 s_or_b32 exec_lo, exec_lo, s3 .LBB6_166: ; %Flow1527 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 .LBB6_167: ; %.loopexit4.i.i.i39 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v9, 0 v_readfirstlane_b32 s2, v10 v_readfirstlane_b32 s3, v11 s_mov_b32 s6, exec_lo s_clause 0x1 global_load_b64 v[12:13], v9, s[34:35] offset:40 global_load_b128 v[4:7], v9, s[34:35] s_waitcnt vmcnt(1) v_readfirstlane_b32 s4, v12 v_readfirstlane_b32 s5, v13 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[4:5], s[2:3], s[4:5] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_169 ; %bb.168: v_dual_mov_b32 v10, s6 :: v_dual_mov_b32 v11, 0 s_mul_i32 s6, s5, 24 s_mul_hi_u32 s7, s4, 24 v_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s4, 24 s_waitcnt vmcnt(0) v_add_co_u32 v14, vcc_lo, v4, s6 v_add_co_ci_u32_e32 v15, vcc_lo, s7, v5, vcc_lo global_store_b128 v[14:15], v[10:13], off offset:8 .LBB6_169: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[6:7], s[4:5], 12 s_mov_b32 s8, 0 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v7, vcc_lo v_lshlrev_b64 v[6:7], 6, v[8:9] s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_and_or_b32 v0, v0, 0xffffff1d, 34 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, v10, v6 v_add_co_ci_u32_e32 v11, vcc_lo, v11, v7, vcc_lo v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9 v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11 s_clause 0x3 global_store_b128 v[10:11], v[0:3], off global_store_b128 v[10:11], v[6:9], off offset:16 global_store_b128 v[10:11], v[6:9], off offset:32 global_store_b128 v[10:11], v[6:9], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_177 ; %bb.170: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s2 v_mov_b32_e32 v10, s3 s_clause 0x1 global_load_b64 v[11:12], v8, s[34:35] offset:32 glc global_load_b64 v[0:1], v8, s[34:35] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v0 v_readfirstlane_b32 s7, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[2:3] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s8, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s8, s8, s7 v_add_co_u32 v6, vcc_lo, v4, s6 v_add_co_ci_u32_e32 v7, vcc_lo, s8, v5, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[6:7], v[11:12], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[11:12] s_cbranch_execz .LBB6_173 ; %bb.171: ; %.preheader1.i.i.i43.preheader s_mov_b32 s7, 0 .LBB6_172: ; %.preheader1.i.i.i43 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 s_sleep 1 global_store_b64 v[6:7], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB6_172 .LBB6_173: ; %Flow1523 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v0, 0 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v2, s7, 0 global_load_b64 v[0:1], v0, s[34:35] offset:16 v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB6_175 ; %bb.174: s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB6_175: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB6_177 ; %bb.176: global_load_b32 v0, v[0:1], off offset:24 v_mov_b32_e32 v1, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v0 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[0:1], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_177: ; %Flow1524 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s5, 24 s_mul_hi_u32 s5, s4, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s5, s5, s1 s_mul_i32 s1, s4, 24 v_add_co_u32 v0, vcc_lo, v4, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB6_181 .p2align 6 .LBB6_178: ; in Loop: Header=BB6_181 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_180 ; %bb.179: ; in Loop: Header=BB6_181 Depth=1 s_sleep 1 s_cbranch_execnz .LBB6_181 s_branch .LBB6_183 .p2align 6 .LBB6_180: s_branch .LBB6_183 .LBB6_181: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_178 ; %bb.182: ; in Loop: Header=BB6_181 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB6_178 .LBB6_183: s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_187 ; %bb.184: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[34:35] offset:40 global_load_b64 v[7:8], v6, s[34:35] offset:24 glc global_load_b64 v[4:5], v6, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s2 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_187 ; %bb.185: ; %.preheader.i.i.i42.preheader s_mov_b32 s0, 0 .LBB6_186: ; %.preheader.i.i.i42 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_186 .LBB6_187: ; %__ockl_printf_append_args.exit46 s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v4, v40 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v4 v_cmp_eq_u32_e64 s0, s0, v4 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_193 ; %bb.188: v_mov_b32_e32 v0, 0 s_mov_b32 s2, exec_lo global_load_b64 v[8:9], v0, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[5:6], v0, s[34:35] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB6_192 ; %bb.189: ; %.preheader3.i.i.i53.preheader s_mov_b32 s3, 0 .p2align 6 .LBB6_190: ; %.preheader3.i.i.i53 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[10:11], v0, s[34:35] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB6_190 ; %bb.191: ; %Flow1511 s_or_b32 exec_lo, exec_lo, s3 .LBB6_192: ; %Flow1513 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 .LBB6_193: ; %.loopexit4.i.i.i47 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s2, v6 v_readfirstlane_b32 s3, v7 s_mov_b32 s6, exec_lo s_clause 0x1 global_load_b64 v[8:9], v5, s[34:35] offset:40 global_load_b128 v[0:3], v5, s[34:35] s_waitcnt vmcnt(1) v_readfirstlane_b32 s4, v8 v_readfirstlane_b32 s5, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[4:5], s[2:3], s[4:5] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_195 ; %bb.194: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0 s_mul_i32 s6, s5, 24 s_mul_hi_u32 s7, s4, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s4, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB6_195: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[6:7], s[4:5], 12 v_lshlrev_b64 v[4:5], 6, v[4:5] s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v2, s6 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo v_mov_b32_e32 v3, 0 s_mov_b32 s8, 0 s_delay_alu instid0(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, v2, v4 v_mov_b32_e32 v2, 33 s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v4, v3 v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8 v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10 v_mov_b32_e32 v11, s11 s_clause 0x3 global_store_b128 v[6:7], v[2:5], off global_store_b128 v[6:7], v[8:11], off offset:16 global_store_b128 v[6:7], v[8:11], off offset:32 global_store_b128 v[6:7], v[8:11], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_203 ; %bb.196: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2 v_mov_b32_e32 v12, s3 s_clause 0x1 global_load_b64 v[13:14], v10, s[34:35] offset:32 glc global_load_b64 v[2:3], v10, s[34:35] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 v_readfirstlane_b32 s7, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[2:3] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s8, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s8, s8, s7 v_add_co_u32 v8, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[13:14] s_cbranch_execz .LBB6_199 ; %bb.197: ; %.preheader1.i.i.i51.preheader s_mov_b32 s7, 0 .LBB6_198: ; %.preheader1.i.i.i51 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 s_sleep 1 global_store_b64 v[8:9], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB6_198 .LBB6_199: ; %Flow1509 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v2, 0 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v4, s7, 0 global_load_b64 v[2:3], v2, s[34:35] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB6_201 ; %bb.200: s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB6_201: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB6_203 ; %bb.202: global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_203: ; %Flow1510 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s5, 24 s_mul_hi_u32 s5, s4, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s5, s5, s1 s_mul_i32 s1, s4, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB6_207 .p2align 6 .LBB6_204: ; in Loop: Header=BB6_207 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_206 ; %bb.205: ; in Loop: Header=BB6_207 Depth=1 s_sleep 1 s_cbranch_execnz .LBB6_207 s_branch .LBB6_209 .p2align 6 .LBB6_206: s_branch .LBB6_209 .LBB6_207: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_204 ; %bb.208: ; in Loop: Header=BB6_207 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB6_204 .LBB6_209: global_load_b64 v[20:21], v[6:7], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_213 ; %bb.210: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[34:35] offset:40 global_load_b64 v[7:8], v6, s[34:35] offset:24 glc global_load_b64 v[4:5], v6, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s2 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_213 ; %bb.211: ; %.preheader.i.i.i50.preheader s_mov_b32 s0, 0 .LBB6_212: ; %.preheader.i.i.i50 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_212 .LBB6_213: ; %__ockl_printf_begin.exit54 s_or_b32 exec_lo, exec_lo, s1 s_getpc_b64 s[2:3] s_add_u32 s2, s2, .str.2@rel32@lo+4 s_addc_u32 s3, s3, .str.2@rel32@hi+12 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u64 s[2:3], 0 s_cbranch_scc0 .LBB6_291 ; %bb.214: s_waitcnt vmcnt(0) v_dual_mov_b32 v23, 0 :: v_dual_and_b32 v22, 2, v20 v_and_b32_e32 v42, -3, v20 s_mov_b64 s[4:5], 24 v_mov_b32_e32 v43, v21 s_delay_alu instid0(VALU_DEP_3) v_dual_mov_b32 v25, v23 :: v_dual_mov_b32 v24, v22 s_branch .LBB6_216 .LBB6_215: ; %__ockl_hostcall_preview.exit20.i71 ; in Loop: Header=BB6_216 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_sub_u32 s4, s4, s6 s_subb_u32 s5, s5, s7 s_add_u32 s2, s2, s6 s_addc_u32 s3, s3, s7 s_cmp_lg_u64 s[4:5], 0 s_cbranch_scc0 .LBB6_292 .LBB6_216: ; =>This Loop Header: Depth=1 ; Child Loop BB6_219 Depth 2 ; Child Loop BB6_226 Depth 2 ; Child Loop BB6_233 Depth 2 ; Child Loop BB6_240 Depth 2 ; Child Loop BB6_247 Depth 2 ; Child Loop BB6_254 Depth 2 ; Child Loop BB6_261 Depth 2 ; Child Loop BB6_268 Depth 2 ; Child Loop BB6_276 Depth 2 ; Child Loop BB6_285 Depth 2 ; Child Loop BB6_290 Depth 2 v_cmp_lt_u64_e64 s0, s[4:5], 56 ; implicit-def: $vgpr2_vgpr3 ; implicit-def: $sgpr13 s_delay_alu instid0(VALU_DEP_1) s_and_b32 s0, s0, exec_lo s_cselect_b32 s6, s4, 56 s_cselect_b32 s7, s5, 0 s_cmp_gt_u32 s6, 7 s_mov_b32 s0, -1 s_cbranch_scc1 .LBB6_221 ; %bb.217: ; in Loop: Header=BB6_216 Depth=1 v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 s_cmp_eq_u32 s6, 0 s_cbranch_scc1 .LBB6_220 ; %bb.218: ; %.preheader31.i55.preheader ; in Loop: Header=BB6_216 Depth=1 s_lshl_b64 s[0:1], s[6:7], 3 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], s[2:3] .LBB6_219: ; %.preheader31.i55 ; Parent Loop BB6_216 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v0, v23, s[10:11] s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_add_u32 s10, s10, 1 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s0, s8 v_or_b32_e32 v2, v0, v2 v_or_b32_e32 v3, v1, v3 s_cbranch_scc1 .LBB6_219 .LBB6_220: ; %Flow1480 ; in Loop: Header=BB6_216 Depth=1 s_mov_b32 s0, 0 s_mov_b32 s13, 0 .LBB6_221: ; %Flow1482 ; in Loop: Header=BB6_216 Depth=1 s_and_not1_b32 vcc_lo, exec_lo, s0 s_mov_b64 s[0:1], s[2:3] s_cbranch_vccnz .LBB6_223 ; %bb.222: ; in Loop: Header=BB6_216 Depth=1 global_load_b64 v[2:3], v23, s[2:3] s_add_i32 s13, s6, -8 s_add_u32 s0, s2, 8 s_addc_u32 s1, s3, 0 .LBB6_223: ; %.loopexit32.i56 ; in Loop: Header=BB6_216 Depth=1 s_cmp_gt_u32 s13, 7 s_cbranch_scc1 .LBB6_228 ; %bb.224: ; in Loop: Header=BB6_216 Depth=1 v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_cmp_eq_u32 s13, 0 s_cbranch_scc1 .LBB6_227 ; %bb.225: ; %.preheader29.i57.preheader ; in Loop: Header=BB6_216 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_226: ; %.preheader29.i57 ; Parent Loop BB6_216 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v0, v23, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s13, s10 v_or_b32_e32 v4, v0, v4 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v5, v1, v5 s_cbranch_scc1 .LBB6_226 .LBB6_227: ; %Flow1475 ; in Loop: Header=BB6_216 Depth=1 s_mov_b32 s12, 0 s_cbranch_execz .LBB6_229 s_branch .LBB6_230 .LBB6_228: ; in Loop: Header=BB6_216 Depth=1 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $sgpr12 .LBB6_229: ; in Loop: Header=BB6_216 Depth=1 global_load_b64 v[4:5], v23, s[0:1] s_add_i32 s12, s13, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_230: ; %.loopexit30.i58 ; in Loop: Header=BB6_216 Depth=1 s_cmp_gt_u32 s12, 7 s_cbranch_scc1 .LBB6_235 ; %bb.231: ; in Loop: Header=BB6_216 Depth=1 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_cmp_eq_u32 s12, 0 s_cbranch_scc1 .LBB6_234 ; %bb.232: ; %.preheader27.i59.preheader ; in Loop: Header=BB6_216 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_233: ; %.preheader27.i59 ; Parent Loop BB6_216 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v0, v23, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s12, s10 v_or_b32_e32 v6, v0, v6 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v7, v1, v7 s_cbranch_scc1 .LBB6_233 .LBB6_234: ; %Flow1470 ; in Loop: Header=BB6_216 Depth=1 s_mov_b32 s13, 0 s_cbranch_execz .LBB6_236 s_branch .LBB6_237 .LBB6_235: ; in Loop: Header=BB6_216 Depth=1 ; implicit-def: $sgpr13 .LBB6_236: ; in Loop: Header=BB6_216 Depth=1 global_load_b64 v[6:7], v23, s[0:1] s_add_i32 s13, s12, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_237: ; %.loopexit28.i60 ; in Loop: Header=BB6_216 Depth=1 s_cmp_gt_u32 s13, 7 s_cbranch_scc1 .LBB6_242 ; %bb.238: ; in Loop: Header=BB6_216 Depth=1 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 s_cmp_eq_u32 s13, 0 s_cbranch_scc1 .LBB6_241 ; %bb.239: ; %.preheader25.i61.preheader ; in Loop: Header=BB6_216 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_240: ; %.preheader25.i61 ; Parent Loop BB6_216 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v0, v23, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s13, s10 v_or_b32_e32 v8, v0, v8 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v9, v1, v9 s_cbranch_scc1 .LBB6_240 .LBB6_241: ; %Flow1465 ; in Loop: Header=BB6_216 Depth=1 s_mov_b32 s12, 0 s_cbranch_execz .LBB6_243 s_branch .LBB6_244 .LBB6_242: ; in Loop: Header=BB6_216 Depth=1 ; implicit-def: $vgpr8_vgpr9 ; implicit-def: $sgpr12 .LBB6_243: ; in Loop: Header=BB6_216 Depth=1 global_load_b64 v[8:9], v23, s[0:1] s_add_i32 s12, s13, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_244: ; %.loopexit26.i62 ; in Loop: Header=BB6_216 Depth=1 s_cmp_gt_u32 s12, 7 s_cbranch_scc1 .LBB6_249 ; %bb.245: ; in Loop: Header=BB6_216 Depth=1 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_cmp_eq_u32 s12, 0 s_cbranch_scc1 .LBB6_248 ; %bb.246: ; %.preheader23.i63.preheader ; in Loop: Header=BB6_216 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_247: ; %.preheader23.i63 ; Parent Loop BB6_216 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v0, v23, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s12, s10 v_or_b32_e32 v10, v0, v10 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v11, v1, v11 s_cbranch_scc1 .LBB6_247 .LBB6_248: ; %Flow1460 ; in Loop: Header=BB6_216 Depth=1 s_mov_b32 s13, 0 s_cbranch_execz .LBB6_250 s_branch .LBB6_251 .LBB6_249: ; in Loop: Header=BB6_216 Depth=1 ; implicit-def: $sgpr13 .LBB6_250: ; in Loop: Header=BB6_216 Depth=1 global_load_b64 v[10:11], v23, s[0:1] s_add_i32 s13, s12, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_251: ; %.loopexit24.i64 ; in Loop: Header=BB6_216 Depth=1 s_cmp_gt_u32 s13, 7 s_cbranch_scc1 .LBB6_256 ; %bb.252: ; in Loop: Header=BB6_216 Depth=1 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_cmp_eq_u32 s13, 0 s_cbranch_scc1 .LBB6_255 ; %bb.253: ; %.preheader21.i65.preheader ; in Loop: Header=BB6_216 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_254: ; %.preheader21.i65 ; Parent Loop BB6_216 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v0, v23, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s13, s10 v_or_b32_e32 v12, v0, v12 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v13, v1, v13 s_cbranch_scc1 .LBB6_254 .LBB6_255: ; %Flow1455 ; in Loop: Header=BB6_216 Depth=1 s_mov_b32 s12, 0 s_cbranch_execz .LBB6_257 s_branch .LBB6_258 .LBB6_256: ; in Loop: Header=BB6_216 Depth=1 ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $sgpr12 .LBB6_257: ; in Loop: Header=BB6_216 Depth=1 global_load_b64 v[12:13], v23, s[0:1] s_add_i32 s12, s13, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_258: ; %.loopexit22.i66 ; in Loop: Header=BB6_216 Depth=1 s_cmp_gt_u32 s12, 7 s_cbranch_scc1 .LBB6_263 ; %bb.259: ; in Loop: Header=BB6_216 Depth=1 v_mov_b32_e32 v14, 0 v_mov_b32_e32 v15, 0 s_cmp_eq_u32 s12, 0 s_cbranch_scc1 .LBB6_262 ; %bb.260: ; %.preheader.i67.preheader ; in Loop: Header=BB6_216 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], s[0:1] .LBB6_261: ; %.preheader.i67 ; Parent Loop BB6_216 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v0, v23, s[10:11] s_add_i32 s12, s12, -1 s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_add_u32 s10, s10, 1 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s12, 0 v_or_b32_e32 v14, v0, v14 v_or_b32_e32 v15, v1, v15 s_cbranch_scc1 .LBB6_261 .LBB6_262: ; %Flow1450 ; in Loop: Header=BB6_216 Depth=1 s_cbranch_execz .LBB6_264 s_branch .LBB6_265 .LBB6_263: ; in Loop: Header=BB6_216 Depth=1 .LBB6_264: ; in Loop: Header=BB6_216 Depth=1 global_load_b64 v[14:15], v23, s[0:1] .LBB6_265: ; %.loopexit.i68 ; in Loop: Header=BB6_216 Depth=1 v_mov_b32_e32 v22, v40 v_mov_b32_e32 v0, 0 v_mov_b32_e32 v1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v22 v_cmp_eq_u32_e64 s0, s0, v22 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_271 ; %bb.266: ; in Loop: Header=BB6_216 Depth=1 global_load_b64 v[18:19], v23, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[0:1], v23, s[34:35] offset:40 global_load_b64 v[16:17], v23, s[34:35] s_mov_b32 s8, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v19 v_and_b32_e32 v0, v0, v18 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v1, v1, 24 v_mul_hi_u32 v26, v0, 24 v_mul_lo_u32 v0, v0, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v1, v26, v1 s_waitcnt vmcnt(0) v_add_co_u32 v0, vcc_lo, v16, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, v17, v1, vcc_lo global_load_b64 v[16:17], v[0:1], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[0:1], v23, v[16:19], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[0:1], v[18:19] s_cbranch_execz .LBB6_270 ; %bb.267: ; %.preheader3.i.i19.i75.preheader ; in Loop: Header=BB6_216 Depth=1 s_mov_b32 s9, 0 .p2align 6 .LBB6_268: ; %.preheader3.i.i19.i75 ; Parent Loop BB6_216 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 s_clause 0x1 global_load_b64 v[16:17], v23, s[34:35] offset:40 global_load_b64 v[26:27], v23, s[34:35] v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v16, v16, v18 s_waitcnt vmcnt(0) v_mad_u64_u32 v[0:1], null, v16, 24, v[26:27] v_and_b32_e32 v26, v17, v19 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[16:17], null, v26, 24, v[1:2] v_mov_b32_e32 v1, v16 global_load_b64 v[16:17], v[0:1], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[0:1], v23, v[16:19], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[18:19] s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB6_268 ; %bb.269: ; %Flow1445 ; in Loop: Header=BB6_216 Depth=1 s_or_b32 exec_lo, exec_lo, s9 .LBB6_270: ; %Flow1447 ; in Loop: Header=BB6_216 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s8 .LBB6_271: ; %.loopexit4.i.i14.i69 ; in Loop: Header=BB6_216 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_clause 0x1 global_load_b64 v[26:27], v23, s[34:35] offset:40 global_load_b128 v[16:19], v23, s[34:35] v_readfirstlane_b32 s8, v0 v_readfirstlane_b32 s9, v1 s_mov_b32 s12, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s10, v26 v_readfirstlane_b32 s11, v27 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[10:11], s[8:9], s[10:11] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_273 ; %bb.272: ; in Loop: Header=BB6_216 Depth=1 v_dual_mov_b32 v26, s12 :: v_dual_mov_b32 v27, 0 s_mul_i32 s12, s11, 24 s_mul_hi_u32 s13, s10, 24 v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1 s_add_i32 s13, s13, s12 s_mul_i32 s12, s10, 24 s_waitcnt vmcnt(0) v_add_co_u32 v0, vcc_lo, v16, s12 v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo global_store_b128 v[0:1], v[26:29], off offset:8 .LBB6_273: ; in Loop: Header=BB6_216 Depth=1 s_or_b32 exec_lo, exec_lo, s1 v_cmp_gt_u64_e64 vcc_lo, s[4:5], 56 v_or_b32_e32 v0, v43, v25 v_or_b32_e32 v26, v42, v24 s_lshl_b64 s[12:13], s[10:11], 12 s_lshl_b32 s1, s6, 2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_add_i32 s1, s1, 28 v_dual_cndmask_b32 v1, v0, v43 :: v_dual_cndmask_b32 v0, v26, v42 v_lshlrev_b64 v[26:27], 6, v[22:23] s_waitcnt vmcnt(0) v_add_co_u32 v18, vcc_lo, v18, s12 v_add_co_ci_u32_e32 v19, vcc_lo, s13, v19, vcc_lo s_and_b32 s1, s1, 0x1e0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v18, vcc_lo, v18, v26 v_and_or_b32 v0, v0, 0xffffff1f, s1 v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo s_clause 0x3 global_store_b128 v[18:19], v[0:3], off global_store_b128 v[18:19], v[4:7], off offset:16 global_store_b128 v[18:19], v[8:11], off offset:32 global_store_b128 v[18:19], v[12:15], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_281 ; %bb.274: ; in Loop: Header=BB6_216 Depth=1 s_clause 0x1 global_load_b64 v[8:9], v23, s[34:35] offset:32 glc global_load_b64 v[0:1], v23, s[34:35] offset:40 v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9 s_waitcnt vmcnt(0) v_readfirstlane_b32 s12, v0 v_readfirstlane_b32 s13, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[12:13], s[12:13], s[8:9] s_mul_i32 s13, s13, 24 s_mul_hi_u32 s14, s12, 24 s_mul_i32 s12, s12, 24 s_add_i32 s14, s14, s13 v_add_co_u32 v4, vcc_lo, v16, s12 v_add_co_ci_u32_e32 v5, vcc_lo, s14, v17, vcc_lo s_mov_b32 s12, exec_lo global_store_b64 v[4:5], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v23, v[6:9], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[8:9] s_cbranch_execz .LBB6_277 ; %bb.275: ; %.preheader1.i.i17.i73.preheader ; in Loop: Header=BB6_216 Depth=1 s_mov_b32 s13, 0 .LBB6_276: ; %.preheader1.i.i17.i73 ; Parent Loop BB6_216 Depth=1 ; => This Inner Loop Header: Depth=2 v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v23, v[0:3], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s13, vcc_lo, s13 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s13 s_cbranch_execnz .LBB6_276 .LBB6_277: ; %Flow1443 ; in Loop: Header=BB6_216 Depth=1 s_or_b32 exec_lo, exec_lo, s12 global_load_b64 v[0:1], v23, s[34:35] offset:16 s_mov_b32 s13, exec_lo s_mov_b32 s12, exec_lo v_mbcnt_lo_u32_b32 v2, s13, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB6_279 ; %bb.278: ; in Loop: Header=BB6_216 Depth=1 s_bcnt1_i32_b32 s13, s13 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s13 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB6_279: ; in Loop: Header=BB6_216 Depth=1 s_or_b32 exec_lo, exec_lo, s12 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB6_281 ; %bb.280: ; in Loop: Header=BB6_216 Depth=1 global_load_b32 v22, v[0:1], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s12, v22 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[22:23], off s_and_b32 m0, s12, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_281: ; %Flow1444 ; in Loop: Header=BB6_216 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s11, 24 s_mul_hi_u32 s11, s10, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s11, s11, s1 s_mul_i32 s1, s10, 24 v_add_co_u32 v0, vcc_lo, v16, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s11, v17, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB6_285 .p2align 6 .LBB6_282: ; in Loop: Header=BB6_285 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_284 ; %bb.283: ; in Loop: Header=BB6_285 Depth=2 s_sleep 1 s_cbranch_execnz .LBB6_285 s_branch .LBB6_287 .p2align 6 .LBB6_284: ; in Loop: Header=BB6_216 Depth=1 s_branch .LBB6_287 .LBB6_285: ; Parent Loop BB6_216 Depth=1 ; => This Inner Loop Header: Depth=2 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_282 ; %bb.286: ; in Loop: Header=BB6_285 Depth=2 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB6_282 .LBB6_287: ; in Loop: Header=BB6_216 Depth=1 global_load_b64 v[42:43], v[18:19], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_215 ; %bb.288: ; in Loop: Header=BB6_216 Depth=1 s_clause 0x2 global_load_b64 v[2:3], v23, s[34:35] offset:40 global_load_b64 v[6:7], v23, s[34:35] offset:24 glc global_load_b64 v[4:5], v23, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v8, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v8, s8 v_add_co_ci_u32_e32 v1, vcc_lo, s9, v9, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v2, v0, v2 v_mul_hi_u32 v8, v2, 24 v_mul_lo_u32 v2, v2, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v6 v_mul_lo_u32 v3, v3, 24 v_add_nc_u32_e32 v3, v8, v3 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v7 global_store_b64 v[4:5], v[6:7], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v23, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_215 ; %bb.289: ; %.preheader.i.i16.i72.preheader ; in Loop: Header=BB6_216 Depth=1 s_mov_b32 s0, 0 .LBB6_290: ; %.preheader.i.i16.i72 ; Parent Loop BB6_216 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[6:7], v23, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3] v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_290 s_branch .LBB6_215 .LBB6_291: s_cbranch_execnz .LBB6_293 s_branch .LBB6_320 .LBB6_292: ; %Flow1483 s_branch .LBB6_320 .LBB6_293: v_mov_b32_e32 v4, v40 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v4 v_cmp_eq_u32_e64 s0, s0, v4 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_299 ; %bb.294: v_mov_b32_e32 v0, 0 s_mov_b32 s2, exec_lo global_load_b64 v[8:9], v0, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[5:6], v0, s[34:35] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB6_298 ; %bb.295: ; %.preheader3.i.i.i82.preheader s_mov_b32 s3, 0 .p2align 6 .LBB6_296: ; %.preheader3.i.i.i82 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[10:11], v0, s[34:35] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB6_296 ; %bb.297: ; %Flow1495 s_or_b32 exec_lo, exec_lo, s3 .LBB6_298: ; %Flow1497 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 .LBB6_299: ; %.loopexit4.i.i.i76 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s2, v6 v_readfirstlane_b32 s3, v7 s_mov_b32 s6, exec_lo s_clause 0x1 global_load_b64 v[8:9], v5, s[34:35] offset:40 global_load_b128 v[0:3], v5, s[34:35] s_waitcnt vmcnt(1) v_readfirstlane_b32 s4, v8 v_readfirstlane_b32 s5, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[4:5], s[2:3], s[4:5] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_301 ; %bb.300: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0 s_mul_i32 s6, s5, 24 s_mul_hi_u32 s7, s4, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s4, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB6_301: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[6:7], s[4:5], 12 s_mov_b32 s8, 0 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v2, s6 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo v_lshlrev_b64 v[2:3], 6, v[4:5] s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_mov_b32_e32 v8, 0 v_and_or_b32 v20, v20, 0xffffff1f, 32 v_add_co_u32 v6, vcc_lo, v6, v2 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11 v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10 v_mov_b32_e32 v9, v8 s_clause 0x4 global_store_b64 v[6:7], v[20:21], off global_store_b128 v[6:7], v[2:5], off offset:8 global_store_b128 v[6:7], v[2:5], off offset:24 global_store_b128 v[6:7], v[2:5], off offset:40 global_store_b64 v[6:7], v[8:9], off offset:56 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_309 ; %bb.302: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2 v_mov_b32_e32 v12, s3 s_clause 0x1 global_load_b64 v[13:14], v10, s[34:35] offset:32 glc global_load_b64 v[2:3], v10, s[34:35] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 v_readfirstlane_b32 s7, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[2:3] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s8, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s8, s8, s7 v_add_co_u32 v8, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[13:14] s_cbranch_execz .LBB6_305 ; %bb.303: ; %.preheader1.i.i.i80.preheader s_mov_b32 s7, 0 .LBB6_304: ; %.preheader1.i.i.i80 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 s_sleep 1 global_store_b64 v[8:9], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB6_304 .LBB6_305: ; %Flow1493 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v2, 0 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v4, s7, 0 global_load_b64 v[2:3], v2, s[34:35] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB6_307 ; %bb.306: s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB6_307: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB6_309 ; %bb.308: global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_309: ; %Flow1494 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s5, 24 s_mul_hi_u32 s5, s4, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s5, s5, s1 s_mul_i32 s1, s4, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB6_313 .p2align 6 .LBB6_310: ; in Loop: Header=BB6_313 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_312 ; %bb.311: ; in Loop: Header=BB6_313 Depth=1 s_sleep 1 s_cbranch_execnz .LBB6_313 s_branch .LBB6_315 .p2align 6 .LBB6_312: s_branch .LBB6_315 .LBB6_313: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_310 ; %bb.314: ; in Loop: Header=BB6_313 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB6_310 .LBB6_315: global_load_b64 v[42:43], v[6:7], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_319 ; %bb.316: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[34:35] offset:40 global_load_b64 v[7:8], v6, s[34:35] offset:24 glc global_load_b64 v[4:5], v6, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s2 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_319 ; %bb.317: ; %.preheader.i.i.i79.preheader s_mov_b32 s0, 0 .LBB6_318: ; %.preheader.i.i.i79 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_318 .LBB6_319: ; %__ockl_hostcall_preview.exit.i78 s_or_b32 exec_lo, exec_lo, s1 .LBB6_320: ; %__ockl_printf_append_string_n.exit83 v_mov_b32_e32 v4, v40 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v4 v_cmp_eq_u32_e64 s0, s0, v4 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_326 ; %bb.321: v_mov_b32_e32 v0, 0 s_mov_b32 s2, exec_lo global_load_b64 v[8:9], v0, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[5:6], v0, s[34:35] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB6_325 ; %bb.322: ; %.preheader3.i.i.i90.preheader s_mov_b32 s3, 0 .p2align 6 .LBB6_323: ; %.preheader3.i.i.i90 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[10:11], v0, s[34:35] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB6_323 ; %bb.324: ; %Flow1431 s_or_b32 exec_lo, exec_lo, s3 .LBB6_325: ; %Flow1433 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 .LBB6_326: ; %.loopexit4.i.i.i84 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s2, v6 v_readfirstlane_b32 s3, v7 s_mov_b32 s6, exec_lo s_clause 0x1 global_load_b64 v[8:9], v5, s[34:35] offset:40 global_load_b128 v[0:3], v5, s[34:35] s_waitcnt vmcnt(1) v_readfirstlane_b32 s4, v8 v_readfirstlane_b32 s5, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[4:5], s[2:3], s[4:5] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_328 ; %bb.327: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0 s_mul_i32 s6, s5, 24 s_mul_hi_u32 s7, s4, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s4, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB6_328: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[6:7], s[4:5], 12 s_mov_b32 s8, 0 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v2, s6 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo v_lshlrev_b64 v[2:3], 6, v[4:5] s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_and_or_b32 v42, v42, 0xffffff1f, 32 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v6, v2 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9 v_dual_mov_b32 v4, s10 :: v_dual_mov_b32 v5, s11 s_clause 0x3 global_store_b128 v[6:7], v[42:45], off global_store_b128 v[6:7], v[2:5], off offset:16 global_store_b128 v[6:7], v[2:5], off offset:32 global_store_b128 v[6:7], v[2:5], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_336 ; %bb.329: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2 v_mov_b32_e32 v12, s3 s_clause 0x1 global_load_b64 v[13:14], v10, s[34:35] offset:32 glc global_load_b64 v[2:3], v10, s[34:35] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 v_readfirstlane_b32 s7, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[2:3] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s8, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s8, s8, s7 v_add_co_u32 v8, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[13:14] s_cbranch_execz .LBB6_332 ; %bb.330: ; %.preheader1.i.i.i88.preheader s_mov_b32 s7, 0 .LBB6_331: ; %.preheader1.i.i.i88 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 s_sleep 1 global_store_b64 v[8:9], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB6_331 .LBB6_332: ; %Flow1429 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v2, 0 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v4, s7, 0 global_load_b64 v[2:3], v2, s[34:35] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB6_334 ; %bb.333: s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB6_334: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB6_336 ; %bb.335: global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_336: ; %Flow1430 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s5, 24 s_mul_hi_u32 s5, s4, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s5, s5, s1 s_mul_i32 s1, s4, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB6_340 .p2align 6 .LBB6_337: ; in Loop: Header=BB6_340 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_339 ; %bb.338: ; in Loop: Header=BB6_340 Depth=1 s_sleep 1 s_cbranch_execnz .LBB6_340 s_branch .LBB6_342 .p2align 6 .LBB6_339: s_branch .LBB6_342 .LBB6_340: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_337 ; %bb.341: ; in Loop: Header=BB6_340 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB6_337 .LBB6_342: global_load_b64 v[0:1], v[6:7], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_346 ; %bb.343: v_mov_b32_e32 v8, 0 s_clause 0x2 global_load_b64 v[4:5], v8, s[34:35] offset:40 global_load_b64 v[9:10], v8, s[34:35] offset:24 glc global_load_b64 v[6:7], v8, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v11, vcc_lo, v4, 1 v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, v11, s2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v12, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11 v_and_b32_e32 v5, v3, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v4, v2, v4 v_mul_lo_u32 v5, v5, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v11, v4, 24 v_mul_lo_u32 v4, v4, 24 v_add_nc_u32_e32 v5, v11, v5 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, v6, v4 v_mov_b32_e32 v4, v9 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v5, v10 global_store_b64 v[6:7], v[9:10], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_346 ; %bb.344: ; %.preheader.i.i.i87.preheader s_mov_b32 s0, 0 .LBB6_345: ; %.preheader.i.i.i87 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5] v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_345 .LBB6_346: ; %__ockl_printf_append_args.exit91 s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v2, v40 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v2 v_cmp_eq_u32_e64 s0, s0, v2 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_352 ; %bb.347: v_mov_b32_e32 v3, 0 s_mov_b32 s2, exec_lo global_load_b64 v[6:7], v3, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[4:5], v3, s[34:35] offset:40 global_load_b64 v[8:9], v3, s[34:35] s_waitcnt vmcnt(1) v_and_b32_e32 v4, v4, v6 v_and_b32_e32 v5, v5, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v10, v4, 24 v_mul_lo_u32 v5, v5, 24 v_mul_lo_u32 v4, v4, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v5, v10, v5 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v8, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo global_load_b64 v[4:5], v[4:5], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[8:9], v[6:7] s_cbranch_execz .LBB6_351 ; %bb.348: ; %.preheader3.i.i.i98.preheader s_mov_b32 s3, 0 .p2align 6 .LBB6_349: ; %.preheader3.i.i.i98 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[4:5], v3, s[34:35] offset:40 global_load_b64 v[10:11], v3, s[34:35] v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v4, v4, v6 v_and_b32_e32 v5, v5, v7 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11] v_mov_b32_e32 v4, v9 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5] global_load_b64 v[4:5], v[8:9], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7] s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB6_349 ; %bb.350: ; %Flow1417 s_or_b32 exec_lo, exec_lo, s3 .LBB6_351: ; %Flow1419 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 .LBB6_352: ; %.loopexit4.i.i.i92 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v3, 0 v_readfirstlane_b32 s2, v8 v_readfirstlane_b32 s3, v9 s_mov_b32 s6, exec_lo s_clause 0x1 global_load_b64 v[10:11], v3, s[34:35] offset:40 global_load_b128 v[4:7], v3, s[34:35] s_waitcnt vmcnt(1) v_readfirstlane_b32 s4, v10 v_readfirstlane_b32 s5, v11 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[4:5], s[2:3], s[4:5] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_354 ; %bb.353: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, 0 s_mul_i32 s6, s5, 24 s_mul_hi_u32 s7, s4, 24 v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s4, 24 s_waitcnt vmcnt(0) v_add_co_u32 v12, vcc_lo, v4, s6 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v5, vcc_lo global_store_b128 v[12:13], v[8:11], off offset:8 .LBB6_354: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[6:7], s[4:5], 12 v_lshlrev_b64 v[2:3], 6, v[2:3] s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v6, s6 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo s_mov_b32 s8, 0 s_getpc_b64 s[6:7] s_add_u32 s6, s6, _Z6secretv@rel32@lo+4 s_addc_u32 s7, s7, _Z6secretv@rel32@hi+12 v_add_co_u32 v10, vcc_lo, v6, v2 s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_and_or_b32 v0, v0, 0xffffff1d, 34 v_add_co_ci_u32_e32 v11, vcc_lo, v7, v3, vcc_lo v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9 v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11 s_clause 0x3 global_store_b128 v[10:11], v[0:3], off global_store_b128 v[10:11], v[6:9], off offset:16 global_store_b128 v[10:11], v[6:9], off offset:32 global_store_b128 v[10:11], v[6:9], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_362 ; %bb.355: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s2 v_mov_b32_e32 v10, s3 s_clause 0x1 global_load_b64 v[11:12], v8, s[34:35] offset:32 glc global_load_b64 v[0:1], v8, s[34:35] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v0 v_readfirstlane_b32 s7, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[2:3] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s8, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s8, s8, s7 v_add_co_u32 v6, vcc_lo, v4, s6 v_add_co_ci_u32_e32 v7, vcc_lo, s8, v5, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[6:7], v[11:12], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[11:12] s_cbranch_execz .LBB6_358 ; %bb.356: ; %.preheader1.i.i.i96.preheader s_mov_b32 s7, 0 .LBB6_357: ; %.preheader1.i.i.i96 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 s_sleep 1 global_store_b64 v[6:7], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB6_357 .LBB6_358: ; %Flow1415 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v0, 0 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v2, s7, 0 global_load_b64 v[0:1], v0, s[34:35] offset:16 v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB6_360 ; %bb.359: s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB6_360: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB6_362 ; %bb.361: global_load_b32 v0, v[0:1], off offset:24 v_mov_b32_e32 v1, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v0 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[0:1], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_362: ; %Flow1416 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s5, 24 s_mul_hi_u32 s5, s4, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s5, s5, s1 s_mul_i32 s1, s4, 24 v_add_co_u32 v0, vcc_lo, v4, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB6_366 .p2align 6 .LBB6_363: ; in Loop: Header=BB6_366 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_365 ; %bb.364: ; in Loop: Header=BB6_366 Depth=1 s_sleep 1 s_cbranch_execnz .LBB6_366 s_branch .LBB6_368 .p2align 6 .LBB6_365: s_branch .LBB6_368 .LBB6_366: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_363 ; %bb.367: ; in Loop: Header=BB6_366 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB6_363 .LBB6_368: s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_372 ; %bb.369: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[34:35] offset:40 global_load_b64 v[7:8], v6, s[34:35] offset:24 glc global_load_b64 v[4:5], v6, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s2 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_372 ; %bb.370: ; %.preheader.i.i.i95.preheader s_mov_b32 s0, 0 .LBB6_371: ; %.preheader.i.i.i95 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_371 .LBB6_372: ; %__ockl_printf_append_args.exit99 s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v4, v40 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v4 v_cmp_eq_u32_e64 s0, s0, v4 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_378 ; %bb.373: v_mov_b32_e32 v0, 0 s_mov_b32 s2, exec_lo global_load_b64 v[8:9], v0, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[5:6], v0, s[34:35] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB6_377 ; %bb.374: ; %.preheader3.i.i.i106.preheader s_mov_b32 s3, 0 .p2align 6 .LBB6_375: ; %.preheader3.i.i.i106 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[10:11], v0, s[34:35] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB6_375 ; %bb.376: ; %Flow1403 s_or_b32 exec_lo, exec_lo, s3 .LBB6_377: ; %Flow1405 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 .LBB6_378: ; %.loopexit4.i.i.i100 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s2, v6 v_readfirstlane_b32 s3, v7 s_mov_b32 s6, exec_lo s_clause 0x1 global_load_b64 v[8:9], v5, s[34:35] offset:40 global_load_b128 v[0:3], v5, s[34:35] s_waitcnt vmcnt(1) v_readfirstlane_b32 s4, v8 v_readfirstlane_b32 s5, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[4:5], s[2:3], s[4:5] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_380 ; %bb.379: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0 s_mul_i32 s6, s5, 24 s_mul_hi_u32 s7, s4, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s4, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB6_380: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[6:7], s[4:5], 12 v_lshlrev_b64 v[4:5], 6, v[4:5] s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v2, s6 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo v_mov_b32_e32 v3, 0 s_mov_b32 s8, 0 s_delay_alu instid0(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, v2, v4 v_mov_b32_e32 v2, 33 s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v4, v3 v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8 v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10 v_mov_b32_e32 v11, s11 s_clause 0x3 global_store_b128 v[6:7], v[2:5], off global_store_b128 v[6:7], v[8:11], off offset:16 global_store_b128 v[6:7], v[8:11], off offset:32 global_store_b128 v[6:7], v[8:11], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_388 ; %bb.381: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2 v_mov_b32_e32 v12, s3 s_clause 0x1 global_load_b64 v[13:14], v10, s[34:35] offset:32 glc global_load_b64 v[2:3], v10, s[34:35] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 v_readfirstlane_b32 s7, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[2:3] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s8, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s8, s8, s7 v_add_co_u32 v8, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[13:14] s_cbranch_execz .LBB6_384 ; %bb.382: ; %.preheader1.i.i.i104.preheader s_mov_b32 s7, 0 .LBB6_383: ; %.preheader1.i.i.i104 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 s_sleep 1 global_store_b64 v[8:9], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB6_383 .LBB6_384: ; %Flow1401 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v2, 0 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v4, s7, 0 global_load_b64 v[2:3], v2, s[34:35] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB6_386 ; %bb.385: s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB6_386: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB6_388 ; %bb.387: global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_388: ; %Flow1402 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s5, 24 s_mul_hi_u32 s5, s4, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s5, s5, s1 s_mul_i32 s1, s4, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB6_392 .p2align 6 .LBB6_389: ; in Loop: Header=BB6_392 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_391 ; %bb.390: ; in Loop: Header=BB6_392 Depth=1 s_sleep 1 s_cbranch_execnz .LBB6_392 s_branch .LBB6_394 .p2align 6 .LBB6_391: s_branch .LBB6_394 .LBB6_392: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_389 ; %bb.393: ; in Loop: Header=BB6_392 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB6_389 .LBB6_394: global_load_b64 v[20:21], v[6:7], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_398 ; %bb.395: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[34:35] offset:40 global_load_b64 v[7:8], v6, s[34:35] offset:24 glc global_load_b64 v[4:5], v6, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s2 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_398 ; %bb.396: ; %.preheader.i.i.i103.preheader s_mov_b32 s0, 0 .LBB6_397: ; %.preheader.i.i.i103 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_397 .LBB6_398: ; %__ockl_printf_begin.exit107 s_or_b32 exec_lo, exec_lo, s1 s_getpc_b64 s[2:3] s_add_u32 s2, s2, .str.3@rel32@lo+4 s_addc_u32 s3, s3, .str.3@rel32@hi+12 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u64 s[2:3], 0 s_cbranch_scc0 .LBB6_476 ; %bb.399: s_waitcnt vmcnt(0) v_dual_mov_b32 v23, 0 :: v_dual_and_b32 v22, 2, v20 v_and_b32_e32 v42, -3, v20 s_mov_b64 s[4:5], 22 v_mov_b32_e32 v43, v21 s_delay_alu instid0(VALU_DEP_3) v_dual_mov_b32 v25, v23 :: v_dual_mov_b32 v24, v22 s_branch .LBB6_401 .LBB6_400: ; %__ockl_hostcall_preview.exit20.i124 ; in Loop: Header=BB6_401 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_sub_u32 s4, s4, s6 s_subb_u32 s5, s5, s7 s_add_u32 s2, s2, s6 s_addc_u32 s3, s3, s7 s_cmp_lg_u64 s[4:5], 0 s_cbranch_scc0 .LBB6_477 .LBB6_401: ; =>This Loop Header: Depth=1 ; Child Loop BB6_404 Depth 2 ; Child Loop BB6_411 Depth 2 ; Child Loop BB6_418 Depth 2 ; Child Loop BB6_425 Depth 2 ; Child Loop BB6_432 Depth 2 ; Child Loop BB6_439 Depth 2 ; Child Loop BB6_446 Depth 2 ; Child Loop BB6_453 Depth 2 ; Child Loop BB6_461 Depth 2 ; Child Loop BB6_470 Depth 2 ; Child Loop BB6_475 Depth 2 v_cmp_lt_u64_e64 s0, s[4:5], 56 ; implicit-def: $vgpr2_vgpr3 ; implicit-def: $sgpr13 s_delay_alu instid0(VALU_DEP_1) s_and_b32 s0, s0, exec_lo s_cselect_b32 s6, s4, 56 s_cselect_b32 s7, s5, 0 s_cmp_gt_u32 s6, 7 s_mov_b32 s0, -1 s_cbranch_scc1 .LBB6_406 ; %bb.402: ; in Loop: Header=BB6_401 Depth=1 v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 s_cmp_eq_u32 s6, 0 s_cbranch_scc1 .LBB6_405 ; %bb.403: ; %.preheader31.i108.preheader ; in Loop: Header=BB6_401 Depth=1 s_lshl_b64 s[0:1], s[6:7], 3 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], s[2:3] .LBB6_404: ; %.preheader31.i108 ; Parent Loop BB6_401 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v0, v23, s[10:11] s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_add_u32 s10, s10, 1 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s0, s8 v_or_b32_e32 v2, v0, v2 v_or_b32_e32 v3, v1, v3 s_cbranch_scc1 .LBB6_404 .LBB6_405: ; %Flow1372 ; in Loop: Header=BB6_401 Depth=1 s_mov_b32 s0, 0 s_mov_b32 s13, 0 .LBB6_406: ; %Flow1374 ; in Loop: Header=BB6_401 Depth=1 s_and_not1_b32 vcc_lo, exec_lo, s0 s_mov_b64 s[0:1], s[2:3] s_cbranch_vccnz .LBB6_408 ; %bb.407: ; in Loop: Header=BB6_401 Depth=1 global_load_b64 v[2:3], v23, s[2:3] s_add_i32 s13, s6, -8 s_add_u32 s0, s2, 8 s_addc_u32 s1, s3, 0 .LBB6_408: ; %.loopexit32.i109 ; in Loop: Header=BB6_401 Depth=1 s_cmp_gt_u32 s13, 7 s_cbranch_scc1 .LBB6_413 ; %bb.409: ; in Loop: Header=BB6_401 Depth=1 v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_cmp_eq_u32 s13, 0 s_cbranch_scc1 .LBB6_412 ; %bb.410: ; %.preheader29.i110.preheader ; in Loop: Header=BB6_401 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_411: ; %.preheader29.i110 ; Parent Loop BB6_401 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v0, v23, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s13, s10 v_or_b32_e32 v4, v0, v4 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v5, v1, v5 s_cbranch_scc1 .LBB6_411 .LBB6_412: ; %Flow1367 ; in Loop: Header=BB6_401 Depth=1 s_mov_b32 s12, 0 s_cbranch_execz .LBB6_414 s_branch .LBB6_415 .LBB6_413: ; in Loop: Header=BB6_401 Depth=1 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $sgpr12 .LBB6_414: ; in Loop: Header=BB6_401 Depth=1 global_load_b64 v[4:5], v23, s[0:1] s_add_i32 s12, s13, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_415: ; %.loopexit30.i111 ; in Loop: Header=BB6_401 Depth=1 s_cmp_gt_u32 s12, 7 s_cbranch_scc1 .LBB6_420 ; %bb.416: ; in Loop: Header=BB6_401 Depth=1 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_cmp_eq_u32 s12, 0 s_cbranch_scc1 .LBB6_419 ; %bb.417: ; %.preheader27.i112.preheader ; in Loop: Header=BB6_401 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_418: ; %.preheader27.i112 ; Parent Loop BB6_401 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v0, v23, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s12, s10 v_or_b32_e32 v6, v0, v6 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v7, v1, v7 s_cbranch_scc1 .LBB6_418 .LBB6_419: ; %Flow1362 ; in Loop: Header=BB6_401 Depth=1 s_mov_b32 s13, 0 s_cbranch_execz .LBB6_421 s_branch .LBB6_422 .LBB6_420: ; in Loop: Header=BB6_401 Depth=1 ; implicit-def: $sgpr13 .LBB6_421: ; in Loop: Header=BB6_401 Depth=1 global_load_b64 v[6:7], v23, s[0:1] s_add_i32 s13, s12, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_422: ; %.loopexit28.i113 ; in Loop: Header=BB6_401 Depth=1 s_cmp_gt_u32 s13, 7 s_cbranch_scc1 .LBB6_427 ; %bb.423: ; in Loop: Header=BB6_401 Depth=1 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 s_cmp_eq_u32 s13, 0 s_cbranch_scc1 .LBB6_426 ; %bb.424: ; %.preheader25.i114.preheader ; in Loop: Header=BB6_401 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_425: ; %.preheader25.i114 ; Parent Loop BB6_401 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v0, v23, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s13, s10 v_or_b32_e32 v8, v0, v8 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v9, v1, v9 s_cbranch_scc1 .LBB6_425 .LBB6_426: ; %Flow1357 ; in Loop: Header=BB6_401 Depth=1 s_mov_b32 s12, 0 s_cbranch_execz .LBB6_428 s_branch .LBB6_429 .LBB6_427: ; in Loop: Header=BB6_401 Depth=1 ; implicit-def: $vgpr8_vgpr9 ; implicit-def: $sgpr12 .LBB6_428: ; in Loop: Header=BB6_401 Depth=1 global_load_b64 v[8:9], v23, s[0:1] s_add_i32 s12, s13, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_429: ; %.loopexit26.i115 ; in Loop: Header=BB6_401 Depth=1 s_cmp_gt_u32 s12, 7 s_cbranch_scc1 .LBB6_434 ; %bb.430: ; in Loop: Header=BB6_401 Depth=1 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_cmp_eq_u32 s12, 0 s_cbranch_scc1 .LBB6_433 ; %bb.431: ; %.preheader23.i116.preheader ; in Loop: Header=BB6_401 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_432: ; %.preheader23.i116 ; Parent Loop BB6_401 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v0, v23, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s12, s10 v_or_b32_e32 v10, v0, v10 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v11, v1, v11 s_cbranch_scc1 .LBB6_432 .LBB6_433: ; %Flow1352 ; in Loop: Header=BB6_401 Depth=1 s_mov_b32 s13, 0 s_cbranch_execz .LBB6_435 s_branch .LBB6_436 .LBB6_434: ; in Loop: Header=BB6_401 Depth=1 ; implicit-def: $sgpr13 .LBB6_435: ; in Loop: Header=BB6_401 Depth=1 global_load_b64 v[10:11], v23, s[0:1] s_add_i32 s13, s12, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_436: ; %.loopexit24.i117 ; in Loop: Header=BB6_401 Depth=1 s_cmp_gt_u32 s13, 7 s_cbranch_scc1 .LBB6_441 ; %bb.437: ; in Loop: Header=BB6_401 Depth=1 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_cmp_eq_u32 s13, 0 s_cbranch_scc1 .LBB6_440 ; %bb.438: ; %.preheader21.i118.preheader ; in Loop: Header=BB6_401 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], 0 .LBB6_439: ; %.preheader21.i118 ; Parent Loop BB6_401 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s14, s0, s10 s_addc_u32 s15, s1, s11 s_add_u32 s10, s10, 1 global_load_u8 v0, v23, s[14:15] s_addc_u32 s11, s11, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_cmp_lg_u32 s13, s10 v_or_b32_e32 v12, v0, v12 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v13, v1, v13 s_cbranch_scc1 .LBB6_439 .LBB6_440: ; %Flow1347 ; in Loop: Header=BB6_401 Depth=1 s_mov_b32 s12, 0 s_cbranch_execz .LBB6_442 s_branch .LBB6_443 .LBB6_441: ; in Loop: Header=BB6_401 Depth=1 ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $sgpr12 .LBB6_442: ; in Loop: Header=BB6_401 Depth=1 global_load_b64 v[12:13], v23, s[0:1] s_add_i32 s12, s13, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_443: ; %.loopexit22.i119 ; in Loop: Header=BB6_401 Depth=1 s_cmp_gt_u32 s12, 7 s_cbranch_scc1 .LBB6_448 ; %bb.444: ; in Loop: Header=BB6_401 Depth=1 v_mov_b32_e32 v14, 0 v_mov_b32_e32 v15, 0 s_cmp_eq_u32 s12, 0 s_cbranch_scc1 .LBB6_447 ; %bb.445: ; %.preheader.i120.preheader ; in Loop: Header=BB6_401 Depth=1 s_mov_b64 s[8:9], 0 s_mov_b64 s[10:11], s[0:1] .LBB6_446: ; %.preheader.i120 ; Parent Loop BB6_401 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v0, v23, s[10:11] s_add_i32 s12, s12, -1 s_waitcnt vmcnt(0) v_and_b32_e32 v22, 0xffff, v0 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[0:1], s8, v[22:23] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_add_u32 s10, s10, 1 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s12, 0 v_or_b32_e32 v14, v0, v14 v_or_b32_e32 v15, v1, v15 s_cbranch_scc1 .LBB6_446 .LBB6_447: ; %Flow1342 ; in Loop: Header=BB6_401 Depth=1 s_cbranch_execz .LBB6_449 s_branch .LBB6_450 .LBB6_448: ; in Loop: Header=BB6_401 Depth=1 .LBB6_449: ; in Loop: Header=BB6_401 Depth=1 global_load_b64 v[14:15], v23, s[0:1] .LBB6_450: ; %.loopexit.i121 ; in Loop: Header=BB6_401 Depth=1 v_mov_b32_e32 v22, v40 v_mov_b32_e32 v0, 0 v_mov_b32_e32 v1, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v22 v_cmp_eq_u32_e64 s0, s0, v22 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_456 ; %bb.451: ; in Loop: Header=BB6_401 Depth=1 global_load_b64 v[18:19], v23, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[0:1], v23, s[34:35] offset:40 global_load_b64 v[16:17], v23, s[34:35] s_mov_b32 s8, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v19 v_and_b32_e32 v0, v0, v18 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v1, v1, 24 v_mul_hi_u32 v26, v0, 24 v_mul_lo_u32 v0, v0, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v1, v26, v1 s_waitcnt vmcnt(0) v_add_co_u32 v0, vcc_lo, v16, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, v17, v1, vcc_lo global_load_b64 v[16:17], v[0:1], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[0:1], v23, v[16:19], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[0:1], v[18:19] s_cbranch_execz .LBB6_455 ; %bb.452: ; %.preheader3.i.i19.i128.preheader ; in Loop: Header=BB6_401 Depth=1 s_mov_b32 s9, 0 .p2align 6 .LBB6_453: ; %.preheader3.i.i19.i128 ; Parent Loop BB6_401 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 s_clause 0x1 global_load_b64 v[16:17], v23, s[34:35] offset:40 global_load_b64 v[26:27], v23, s[34:35] v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v16, v16, v18 s_waitcnt vmcnt(0) v_mad_u64_u32 v[0:1], null, v16, 24, v[26:27] v_and_b32_e32 v26, v17, v19 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[16:17], null, v26, 24, v[1:2] v_mov_b32_e32 v1, v16 global_load_b64 v[16:17], v[0:1], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[0:1], v23, v[16:19], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[18:19] s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB6_453 ; %bb.454: ; %Flow1337 ; in Loop: Header=BB6_401 Depth=1 s_or_b32 exec_lo, exec_lo, s9 .LBB6_455: ; %Flow1339 ; in Loop: Header=BB6_401 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s8 .LBB6_456: ; %.loopexit4.i.i14.i122 ; in Loop: Header=BB6_401 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_clause 0x1 global_load_b64 v[26:27], v23, s[34:35] offset:40 global_load_b128 v[16:19], v23, s[34:35] v_readfirstlane_b32 s8, v0 v_readfirstlane_b32 s9, v1 s_mov_b32 s12, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s10, v26 v_readfirstlane_b32 s11, v27 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[10:11], s[8:9], s[10:11] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_458 ; %bb.457: ; in Loop: Header=BB6_401 Depth=1 v_dual_mov_b32 v26, s12 :: v_dual_mov_b32 v27, 0 s_mul_i32 s12, s11, 24 s_mul_hi_u32 s13, s10, 24 v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1 s_add_i32 s13, s13, s12 s_mul_i32 s12, s10, 24 s_waitcnt vmcnt(0) v_add_co_u32 v0, vcc_lo, v16, s12 v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo global_store_b128 v[0:1], v[26:29], off offset:8 .LBB6_458: ; in Loop: Header=BB6_401 Depth=1 s_or_b32 exec_lo, exec_lo, s1 v_cmp_gt_u64_e64 vcc_lo, s[4:5], 56 v_or_b32_e32 v0, v43, v25 v_or_b32_e32 v26, v42, v24 s_lshl_b64 s[12:13], s[10:11], 12 s_lshl_b32 s1, s6, 2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_add_i32 s1, s1, 28 v_dual_cndmask_b32 v1, v0, v43 :: v_dual_cndmask_b32 v0, v26, v42 v_lshlrev_b64 v[26:27], 6, v[22:23] s_waitcnt vmcnt(0) v_add_co_u32 v18, vcc_lo, v18, s12 v_add_co_ci_u32_e32 v19, vcc_lo, s13, v19, vcc_lo s_and_b32 s1, s1, 0x1e0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v18, vcc_lo, v18, v26 v_and_or_b32 v0, v0, 0xffffff1f, s1 v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo s_clause 0x3 global_store_b128 v[18:19], v[0:3], off global_store_b128 v[18:19], v[4:7], off offset:16 global_store_b128 v[18:19], v[8:11], off offset:32 global_store_b128 v[18:19], v[12:15], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_466 ; %bb.459: ; in Loop: Header=BB6_401 Depth=1 s_clause 0x1 global_load_b64 v[8:9], v23, s[34:35] offset:32 glc global_load_b64 v[0:1], v23, s[34:35] offset:40 v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9 s_waitcnt vmcnt(0) v_readfirstlane_b32 s12, v0 v_readfirstlane_b32 s13, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[12:13], s[12:13], s[8:9] s_mul_i32 s13, s13, 24 s_mul_hi_u32 s14, s12, 24 s_mul_i32 s12, s12, 24 s_add_i32 s14, s14, s13 v_add_co_u32 v4, vcc_lo, v16, s12 v_add_co_ci_u32_e32 v5, vcc_lo, s14, v17, vcc_lo s_mov_b32 s12, exec_lo global_store_b64 v[4:5], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v23, v[6:9], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[8:9] s_cbranch_execz .LBB6_462 ; %bb.460: ; %.preheader1.i.i17.i126.preheader ; in Loop: Header=BB6_401 Depth=1 s_mov_b32 s13, 0 .LBB6_461: ; %.preheader1.i.i17.i126 ; Parent Loop BB6_401 Depth=1 ; => This Inner Loop Header: Depth=2 v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v23, v[0:3], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s13, vcc_lo, s13 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s13 s_cbranch_execnz .LBB6_461 .LBB6_462: ; %Flow1335 ; in Loop: Header=BB6_401 Depth=1 s_or_b32 exec_lo, exec_lo, s12 global_load_b64 v[0:1], v23, s[34:35] offset:16 s_mov_b32 s13, exec_lo s_mov_b32 s12, exec_lo v_mbcnt_lo_u32_b32 v2, s13, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB6_464 ; %bb.463: ; in Loop: Header=BB6_401 Depth=1 s_bcnt1_i32_b32 s13, s13 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s13 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB6_464: ; in Loop: Header=BB6_401 Depth=1 s_or_b32 exec_lo, exec_lo, s12 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB6_466 ; %bb.465: ; in Loop: Header=BB6_401 Depth=1 global_load_b32 v22, v[0:1], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s12, v22 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[22:23], off s_and_b32 m0, s12, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_466: ; %Flow1336 ; in Loop: Header=BB6_401 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s11, 24 s_mul_hi_u32 s11, s10, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s11, s11, s1 s_mul_i32 s1, s10, 24 v_add_co_u32 v0, vcc_lo, v16, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s11, v17, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB6_470 .p2align 6 .LBB6_467: ; in Loop: Header=BB6_470 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_469 ; %bb.468: ; in Loop: Header=BB6_470 Depth=2 s_sleep 1 s_cbranch_execnz .LBB6_470 s_branch .LBB6_472 .p2align 6 .LBB6_469: ; in Loop: Header=BB6_401 Depth=1 s_branch .LBB6_472 .LBB6_470: ; Parent Loop BB6_401 Depth=1 ; => This Inner Loop Header: Depth=2 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_467 ; %bb.471: ; in Loop: Header=BB6_470 Depth=2 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB6_467 .LBB6_472: ; in Loop: Header=BB6_401 Depth=1 global_load_b64 v[42:43], v[18:19], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_400 ; %bb.473: ; in Loop: Header=BB6_401 Depth=1 s_clause 0x2 global_load_b64 v[2:3], v23, s[34:35] offset:40 global_load_b64 v[6:7], v23, s[34:35] offset:24 glc global_load_b64 v[4:5], v23, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v8, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v8, s8 v_add_co_ci_u32_e32 v1, vcc_lo, s9, v9, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v2, v0, v2 v_mul_hi_u32 v8, v2, 24 v_mul_lo_u32 v2, v2, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v6 v_mul_lo_u32 v3, v3, 24 v_add_nc_u32_e32 v3, v8, v3 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v7 global_store_b64 v[4:5], v[6:7], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v23, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_400 ; %bb.474: ; %.preheader.i.i16.i125.preheader ; in Loop: Header=BB6_401 Depth=1 s_mov_b32 s0, 0 .LBB6_475: ; %.preheader.i.i16.i125 ; Parent Loop BB6_401 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[6:7], v23, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3] v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_475 s_branch .LBB6_400 .LBB6_476: s_cbranch_execnz .LBB6_478 s_branch .LBB6_505 .LBB6_477: ; %Flow1375 s_branch .LBB6_505 .LBB6_478: v_mov_b32_e32 v4, v40 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v4 v_cmp_eq_u32_e64 s0, s0, v4 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_484 ; %bb.479: v_mov_b32_e32 v0, 0 s_mov_b32 s2, exec_lo global_load_b64 v[8:9], v0, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[5:6], v0, s[34:35] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB6_483 ; %bb.480: ; %.preheader3.i.i.i135.preheader s_mov_b32 s3, 0 .p2align 6 .LBB6_481: ; %.preheader3.i.i.i135 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[10:11], v0, s[34:35] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB6_481 ; %bb.482: ; %Flow1387 s_or_b32 exec_lo, exec_lo, s3 .LBB6_483: ; %Flow1389 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 .LBB6_484: ; %.loopexit4.i.i.i129 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s2, v6 v_readfirstlane_b32 s3, v7 s_mov_b32 s6, exec_lo s_clause 0x1 global_load_b64 v[8:9], v5, s[34:35] offset:40 global_load_b128 v[0:3], v5, s[34:35] s_waitcnt vmcnt(1) v_readfirstlane_b32 s4, v8 v_readfirstlane_b32 s5, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[4:5], s[2:3], s[4:5] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_486 ; %bb.485: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0 s_mul_i32 s6, s5, 24 s_mul_hi_u32 s7, s4, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s4, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB6_486: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[6:7], s[4:5], 12 s_mov_b32 s8, 0 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v2, s6 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo v_lshlrev_b64 v[2:3], 6, v[4:5] s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_mov_b32_e32 v8, 0 v_and_or_b32 v20, v20, 0xffffff1f, 32 v_add_co_u32 v6, vcc_lo, v6, v2 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11 v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10 v_mov_b32_e32 v9, v8 s_clause 0x4 global_store_b64 v[6:7], v[20:21], off global_store_b128 v[6:7], v[2:5], off offset:8 global_store_b128 v[6:7], v[2:5], off offset:24 global_store_b128 v[6:7], v[2:5], off offset:40 global_store_b64 v[6:7], v[8:9], off offset:56 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_494 ; %bb.487: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2 v_mov_b32_e32 v12, s3 s_clause 0x1 global_load_b64 v[13:14], v10, s[34:35] offset:32 glc global_load_b64 v[2:3], v10, s[34:35] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 v_readfirstlane_b32 s7, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[2:3] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s8, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s8, s8, s7 v_add_co_u32 v8, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[13:14] s_cbranch_execz .LBB6_490 ; %bb.488: ; %.preheader1.i.i.i133.preheader s_mov_b32 s7, 0 .LBB6_489: ; %.preheader1.i.i.i133 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 s_sleep 1 global_store_b64 v[8:9], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB6_489 .LBB6_490: ; %Flow1385 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v2, 0 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v4, s7, 0 global_load_b64 v[2:3], v2, s[34:35] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB6_492 ; %bb.491: s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB6_492: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB6_494 ; %bb.493: global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_494: ; %Flow1386 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s5, 24 s_mul_hi_u32 s5, s4, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s5, s5, s1 s_mul_i32 s1, s4, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB6_498 .p2align 6 .LBB6_495: ; in Loop: Header=BB6_498 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_497 ; %bb.496: ; in Loop: Header=BB6_498 Depth=1 s_sleep 1 s_cbranch_execnz .LBB6_498 s_branch .LBB6_500 .p2align 6 .LBB6_497: s_branch .LBB6_500 .LBB6_498: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_495 ; %bb.499: ; in Loop: Header=BB6_498 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB6_495 .LBB6_500: global_load_b64 v[42:43], v[6:7], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_504 ; %bb.501: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[34:35] offset:40 global_load_b64 v[7:8], v6, s[34:35] offset:24 glc global_load_b64 v[4:5], v6, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s2 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_504 ; %bb.502: ; %.preheader.i.i.i132.preheader s_mov_b32 s0, 0 .LBB6_503: ; %.preheader.i.i.i132 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_503 .LBB6_504: ; %__ockl_hostcall_preview.exit.i131 s_or_b32 exec_lo, exec_lo, s1 .LBB6_505: ; %__ockl_printf_append_string_n.exit136 v_mov_b32_e32 v4, v40 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v4 v_cmp_eq_u32_e64 s0, s0, v4 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_511 ; %bb.506: v_mov_b32_e32 v0, 0 s_mov_b32 s2, exec_lo global_load_b64 v[8:9], v0, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[5:6], v0, s[34:35] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB6_510 ; %bb.507: ; %.preheader3.i.i.i143.preheader s_mov_b32 s3, 0 .p2align 6 .LBB6_508: ; %.preheader3.i.i.i143 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[10:11], v0, s[34:35] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB6_508 ; %bb.509: ; %Flow1323 s_or_b32 exec_lo, exec_lo, s3 .LBB6_510: ; %Flow1325 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 .LBB6_511: ; %.loopexit4.i.i.i137 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s2, v6 v_readfirstlane_b32 s3, v7 s_mov_b32 s6, exec_lo s_clause 0x1 global_load_b64 v[8:9], v5, s[34:35] offset:40 global_load_b128 v[0:3], v5, s[34:35] s_waitcnt vmcnt(1) v_readfirstlane_b32 s4, v8 v_readfirstlane_b32 s5, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[4:5], s[2:3], s[4:5] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_513 ; %bb.512: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0 s_mul_i32 s6, s5, 24 s_mul_hi_u32 s7, s4, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s4, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB6_513: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[6:7], s[4:5], 12 s_mov_b32 s8, 0 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v2, s6 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo v_lshlrev_b64 v[2:3], 6, v[4:5] s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_and_or_b32 v42, v42, 0xffffff1f, 32 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v6, v2 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9 v_dual_mov_b32 v4, s10 :: v_dual_mov_b32 v5, s11 s_clause 0x3 global_store_b128 v[6:7], v[42:45], off global_store_b128 v[6:7], v[2:5], off offset:16 global_store_b128 v[6:7], v[2:5], off offset:32 global_store_b128 v[6:7], v[2:5], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_521 ; %bb.514: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2 v_mov_b32_e32 v12, s3 s_clause 0x1 global_load_b64 v[13:14], v10, s[34:35] offset:32 glc global_load_b64 v[2:3], v10, s[34:35] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 v_readfirstlane_b32 s7, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[2:3] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s8, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s8, s8, s7 v_add_co_u32 v8, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[13:14] s_cbranch_execz .LBB6_517 ; %bb.515: ; %.preheader1.i.i.i141.preheader s_mov_b32 s7, 0 .LBB6_516: ; %.preheader1.i.i.i141 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 s_sleep 1 global_store_b64 v[8:9], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB6_516 .LBB6_517: ; %Flow1321 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v2, 0 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v4, s7, 0 global_load_b64 v[2:3], v2, s[34:35] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB6_519 ; %bb.518: s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB6_519: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB6_521 ; %bb.520: global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_521: ; %Flow1322 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s5, 24 s_mul_hi_u32 s5, s4, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s5, s5, s1 s_mul_i32 s1, s4, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB6_525 .p2align 6 .LBB6_522: ; in Loop: Header=BB6_525 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_524 ; %bb.523: ; in Loop: Header=BB6_525 Depth=1 s_sleep 1 s_cbranch_execnz .LBB6_525 s_branch .LBB6_527 .p2align 6 .LBB6_524: s_branch .LBB6_527 .LBB6_525: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_522 ; %bb.526: ; in Loop: Header=BB6_525 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB6_522 .LBB6_527: global_load_b64 v[56:57], v[6:7], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_531 ; %bb.528: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[34:35] offset:40 global_load_b64 v[7:8], v6, s[34:35] offset:24 glc global_load_b64 v[4:5], v6, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s2 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_531 ; %bb.529: ; %.preheader.i.i.i140.preheader s_mov_b32 s0, 0 .LBB6_530: ; %.preheader.i.i.i140 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_530 .LBB6_531: ; %__ockl_printf_append_args.exit144 s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v4, v40 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v4 v_cmp_eq_u32_e64 s0, s0, v4 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_537 ; %bb.532: v_mov_b32_e32 v0, 0 s_mov_b32 s2, exec_lo global_load_b64 v[8:9], v0, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[5:6], v0, s[34:35] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB6_536 ; %bb.533: ; %.preheader3.i.i.i151.preheader s_mov_b32 s3, 0 .p2align 6 .LBB6_534: ; %.preheader3.i.i.i151 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[34:35] offset:40 global_load_b64 v[10:11], v0, s[34:35] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB6_534 ; %bb.535: ; %Flow1309 s_or_b32 exec_lo, exec_lo, s3 .LBB6_536: ; %Flow1311 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 .LBB6_537: ; %.loopexit4.i.i.i145 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s2, v6 v_readfirstlane_b32 s3, v7 s_mov_b32 s6, exec_lo s_clause 0x1 global_load_b64 v[8:9], v5, s[34:35] offset:40 global_load_b128 v[0:3], v5, s[34:35] s_waitcnt vmcnt(1) v_readfirstlane_b32 s4, v8 v_readfirstlane_b32 s5, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[4:5], s[2:3], s[4:5] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_539 ; %bb.538: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0 s_mul_i32 s6, s5, 24 s_mul_hi_u32 s7, s4, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s7, s7, s6 s_mul_i32 s6, s4, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB6_539: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[6:7], s[4:5], 12 s_mov_b32 s8, 0 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v2, s6 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo v_lshlrev_b64 v[2:3], 6, v[4:5] s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_and_or_b32 v56, v56, 0xffffff1d, 34 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, v6, v2 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9 v_dual_mov_b32 v4, s10 :: v_dual_mov_b32 v5, s11 s_clause 0x3 global_store_b128 v[6:7], v[56:59], off global_store_b128 v[6:7], v[2:5], off offset:16 global_store_b128 v[6:7], v[2:5], off offset:32 global_store_b128 v[6:7], v[2:5], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_547 ; %bb.540: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s2 v_mov_b32_e32 v10, s3 s_clause 0x1 global_load_b64 v[11:12], v8, s[34:35] offset:32 glc global_load_b64 v[2:3], v8, s[34:35] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 v_readfirstlane_b32 s7, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[6:7], s[6:7], s[2:3] s_mul_i32 s7, s7, 24 s_mul_hi_u32 s8, s6, 24 s_mul_i32 s6, s6, 24 s_add_i32 s8, s8, s7 v_add_co_u32 v6, vcc_lo, v0, s6 v_add_co_ci_u32_e32 v7, vcc_lo, s8, v1, vcc_lo s_mov_b32 s6, exec_lo global_store_b64 v[6:7], v[11:12], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[11:12] s_cbranch_execz .LBB6_543 ; %bb.541: ; %.preheader1.i.i.i149.preheader s_mov_b32 s7, 0 .LBB6_542: ; %.preheader1.i.i.i149 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execnz .LBB6_542 .LBB6_543: ; %Flow1307 s_or_b32 exec_lo, exec_lo, s6 v_mov_b32_e32 v2, 0 s_mov_b32 s7, exec_lo s_mov_b32 s6, exec_lo v_mbcnt_lo_u32_b32 v4, s7, 0 global_load_b64 v[2:3], v2, s[34:35] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB6_545 ; %bb.544: s_bcnt1_i32_b32 s7, s7 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB6_545: s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB6_547 ; %bb.546: global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s6, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s6, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_547: ; %Flow1308 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s5, 24 s_mul_hi_u32 s5, s4, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s5, s5, s1 s_mul_i32 s1, s4, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB6_551 .p2align 6 .LBB6_548: ; in Loop: Header=BB6_551 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_550 ; %bb.549: ; in Loop: Header=BB6_551 Depth=1 s_sleep 1 s_cbranch_execnz .LBB6_551 s_branch .LBB6_553 .p2align 6 .LBB6_550: s_branch .LBB6_553 .LBB6_551: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_548 ; %bb.552: ; in Loop: Header=BB6_551 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB6_548 .LBB6_553: s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_557 ; %bb.554: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[34:35] offset:40 global_load_b64 v[7:8], v6, s[34:35] offset:24 glc global_load_b64 v[4:5], v6, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s2 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_557 ; %bb.555: ; %.preheader.i.i.i148.preheader s_mov_b32 s0, 0 .LBB6_556: ; %.preheader.i.i.i148 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_556 .LBB6_557: ; %__ockl_printf_append_args.exit152 s_or_b32 exec_lo, exec_lo, s1 v_and_b32_e32 v0, 0x3ff, v41 v_cmp_ne_u32_e64 s0, 0, v119 s_mov_b32 s1, 0 s_delay_alu instid0(VALU_DEP_2) v_cmp_eq_u32_e32 vcc_lo, 1, v0 s_and_b32 s2, s53, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) s_and_b32 s0, s2, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s2, s0 s_cbranch_execz .LBB6_560 ; %bb.558: ; %.lr.ph v_mov_b32_e32 v0, 0 ds_load_b64 v[0:1], v0 .LBB6_559: ; =>This Inner Loop Header: Depth=1 flat_load_b64 v[2:3], v[117:118] v_add_nc_u32_e32 v119, -1, v119 v_add_co_u32 v117, vcc_lo, v117, 8 v_add_co_ci_u32_e32 v118, vcc_lo, 0, v118, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v119 s_or_b32 s1, vcc_lo, s1 s_waitcnt vmcnt(0) lgkmcnt(0) flat_store_b64 v[0:1], v[2:3] v_add_co_u32 v0, s0, v0, 8 v_add_co_ci_u32_e64 v1, s0, 0, v1, s0 s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB6_559 .LBB6_560: ; %Flow1297 s_or_b32 exec_lo, exec_lo, s2 v_mov_b32_e32 v0, 0 v_mov_b32_e32 v4, 0x1505 v_mov_b32_e32 v5, 0 s_mov_b64 s[0:1], 0 ds_load_b64 v[0:1], v0 .LBB6_561: ; =>This Inner Loop Header: Depth=1 s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, v0, s0 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 s_cmp_eq_u32 s0, 64 flat_load_b64 v[6:7], v[2:3] s_waitcnt vmcnt(0) lgkmcnt(0) v_mad_u64_u32 v[2:3], null, v4, 33, v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, v5, 33, v[3:4] v_mov_b32_e32 v3, v6 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_cbranch_scc0 .LBB6_561 ; %bb.562: global_load_b64 v[0:1], v[58:59], off s_mov_b32 s36, exec_lo s_waitcnt vmcnt(0) global_load_b64 v[0:1], v[0:1], off .LBB6_563: ; =>This Inner Loop Header: Depth=1 s_waitcnt vmcnt(0) v_readfirstlane_b32 s0, v0 v_readfirstlane_b32 s1, v1 s_mov_b32 s37, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u64_e64 s[0:1], v[0:1] v_dual_mov_b32 v31, v41 :: v_dual_mov_b32 v0, v58 v_mov_b32_e32 v1, v59 s_mov_b64 s[4:5], s[48:49] s_mov_b64 s[6:7], s[42:43] s_mov_b64 s[8:9], s[44:45] s_mov_b64 s[10:11], s[46:47] s_mov_b32 s12, s41 s_mov_b32 s13, s52 s_mov_b32 s14, s51 s_mov_b32 s15, s50 s_swappc_b64 s[30:31], s[0:1] v_mov_b32_e32 v3, v0 ; implicit-def: $vgpr0_vgpr1 ; implicit-def: $vgpr2 s_xor_b32 exec_lo, exec_lo, s37 s_cbranch_execnz .LBB6_563 ; %bb.564: s_mov_b32 exec_lo, s36 global_load_b64 v[0:1], v[58:59], off s_mov_b32 s36, exec_lo s_waitcnt vmcnt(0) global_load_b64 v[0:1], v[0:1], off offset:8 .LBB6_565: ; =>This Inner Loop Header: Depth=1 s_waitcnt vmcnt(0) v_readfirstlane_b32 s0, v0 v_readfirstlane_b32 s1, v1 s_mov_b32 s37, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u64_e64 s[0:1], v[0:1] v_dual_mov_b32 v31, v41 :: v_dual_mov_b32 v0, v58 v_mov_b32_e32 v1, v59 v_mov_b32_e32 v2, v3 s_mov_b64 s[4:5], s[48:49] s_mov_b64 s[6:7], s[42:43] s_mov_b64 s[8:9], s[44:45] s_mov_b64 s[10:11], s[46:47] s_mov_b32 s12, s41 s_mov_b32 s13, s52 s_mov_b32 s14, s51 s_mov_b32 s15, s50 s_swappc_b64 s[30:31], s[0:1] v_mov_b32_e32 v4, v0 ; implicit-def: $vgpr0_vgpr1 ; implicit-def: $vgpr3 s_xor_b32 exec_lo, exec_lo, s37 s_cbranch_execnz .LBB6_565 ; %bb.566: s_mov_b32 exec_lo, s36 global_load_b64 v[0:1], v[58:59], off s_mov_b32 s36, exec_lo s_waitcnt vmcnt(0) global_load_b64 v[0:1], v[0:1], off offset:16 .LBB6_567: ; =>This Inner Loop Header: Depth=1 s_waitcnt vmcnt(0) v_readfirstlane_b32 s0, v0 v_readfirstlane_b32 s1, v1 s_mov_b32 s37, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u64_e64 s[0:1], v[0:1] v_dual_mov_b32 v31, v41 :: v_dual_mov_b32 v0, v58 v_dual_mov_b32 v1, v59 :: v_dual_mov_b32 v2, v4 s_mov_b64 s[4:5], s[48:49] s_mov_b64 s[6:7], s[42:43] s_mov_b64 s[8:9], s[44:45] s_mov_b64 s[10:11], s[46:47] s_mov_b32 s12, s41 s_mov_b32 s13, s52 s_mov_b32 s14, s51 s_mov_b32 s15, s50 s_swappc_b64 s[30:31], s[0:1] v_mov_b32_e32 v2, v0 ; implicit-def: $vgpr0_vgpr1 ; implicit-def: $vgpr4 s_xor_b32 exec_lo, exec_lo, s37 s_cbranch_execnz .LBB6_567 ; %bb.568: s_mov_b32 exec_lo, s36 global_load_b64 v[0:1], v[58:59], off s_mov_b32 s36, exec_lo s_waitcnt vmcnt(0) global_load_b64 v[3:4], v[0:1], off offset:24 .LBB6_569: ; =>This Inner Loop Header: Depth=1 s_waitcnt vmcnt(0) v_readfirstlane_b32 s0, v3 v_readfirstlane_b32 s1, v4 s_mov_b32 s37, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u64_e64 s[0:1], v[3:4] v_dual_mov_b32 v31, v41 :: v_dual_mov_b32 v0, v58 v_mov_b32_e32 v1, v59 s_mov_b64 s[4:5], s[48:49] s_mov_b64 s[6:7], s[42:43] s_mov_b64 s[8:9], s[44:45] s_mov_b64 s[10:11], s[46:47] s_mov_b32 s12, s41 s_mov_b32 s13, s52 s_mov_b32 s14, s51 s_mov_b32 s15, s50 s_swappc_b64 s[30:31], s[0:1] ; implicit-def: $vgpr3_vgpr4 ; implicit-def: $vgpr41 ; implicit-def: $vgpr58 ; implicit-def: $vgpr2 s_xor_b32 exec_lo, exec_lo, s37 s_cbranch_execnz .LBB6_569 ; %bb.570: s_mov_b32 exec_lo, s36 v_cmp_ne_u32_e32 vcc_lo, 1, v44 s_cbranch_vccnz .LBB6_759 ; %bb.571: ; %.preheader207 v_dual_mov_b32 v29, 0 :: v_dual_mov_b32 v2, 33 v_mov_b32_e32 v3, 0 s_mov_b32 s3, 0 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s2, s3 s_branch .LBB6_573 .LBB6_572: ; %__ockl_printf_append_args.exit205 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_add_i32 s2, s2, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u32 s2, 11 s_cbranch_scc0 .LBB6_759 .LBB6_573: ; =>This Loop Header: Depth=1 ; Child Loop BB6_576 Depth 2 ; Child Loop BB6_584 Depth 2 ; Child Loop BB6_593 Depth 2 ; Child Loop BB6_598 Depth 2 ; Child Loop BB6_683 Depth 2 ; Child Loop BB6_691 Depth 2 ; Child Loop BB6_700 Depth 2 ; Child Loop BB6_705 Depth 2 ; Child Loop BB6_602 Depth 2 ; Child Loop BB6_605 Depth 3 ; Child Loop BB6_613 Depth 3 ; Child Loop BB6_620 Depth 3 ; Child Loop BB6_627 Depth 3 ; Child Loop BB6_634 Depth 3 ; Child Loop BB6_641 Depth 3 ; Child Loop BB6_648 Depth 3 ; Child Loop BB6_655 Depth 3 ; Child Loop BB6_663 Depth 3 ; Child Loop BB6_672 Depth 3 ; Child Loop BB6_677 Depth 3 ; Child Loop BB6_710 Depth 2 ; Child Loop BB6_718 Depth 2 ; Child Loop BB6_727 Depth 2 ; Child Loop BB6_732 Depth 2 ; Child Loop BB6_736 Depth 2 ; Child Loop BB6_744 Depth 2 ; Child Loop BB6_753 Depth 2 ; Child Loop BB6_758 Depth 2 ds_load_b64 v[4:5], v29 s_lshl_b64 s[0:1], s[2:3], 3 v_mov_b32_e32 v28, v40 s_waitcnt lgkmcnt(0) v_add_co_u32 v4, vcc_lo, v4, s0 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo flat_load_b64 v[6:7], v[4:5] v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 ;;#ASMSTART ;;#ASMEND v_readfirstlane_b32 s0, v28 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s0, s0, v28 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_579 ; %bb.574: ; in Loop: Header=BB6_573 Depth=1 global_load_b64 v[10:11], v29, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[4:5], v29, s[34:35] offset:40 global_load_b64 v[8:9], v29, s[34:35] s_mov_b32 s4, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v5, v5, v11 v_and_b32_e32 v4, v4, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v5, v5, 24 v_mul_hi_u32 v12, v4, 24 v_mul_lo_u32 v4, v4, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v5, v12, v5 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v8, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo global_load_b64 v[8:9], v[4:5], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[4:5], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[4:5], v[10:11] s_cbranch_execz .LBB6_578 ; %bb.575: ; %.preheader3.i.i.i159.preheader ; in Loop: Header=BB6_573 Depth=1 s_mov_b32 s5, 0 .p2align 6 .LBB6_576: ; %.preheader3.i.i.i159 ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 s_clause 0x1 global_load_b64 v[8:9], v29, s[34:35] offset:40 global_load_b64 v[12:13], v29, s[34:35] v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v4 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v8, v8, v10 s_waitcnt vmcnt(0) v_mad_u64_u32 v[4:5], null, v8, 24, v[12:13] v_and_b32_e32 v12, v9, v11 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[8:9], null, v12, 24, v[5:6] v_mov_b32_e32 v5, v8 global_load_b64 v[8:9], v[4:5], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[4:5], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[10:11] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB6_576 ; %bb.577: ; %Flow1291 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s5 .LBB6_578: ; %Flow1293 ; in Loop: Header=BB6_573 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB6_579: ; %.loopexit4.i.i.i153 ; in Loop: Header=BB6_573 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_clause 0x1 global_load_b64 v[12:13], v29, s[34:35] offset:40 global_load_b128 v[8:11], v29, s[34:35] v_readfirstlane_b32 s4, v4 v_readfirstlane_b32 s5, v5 s_mov_b32 s8, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v12 v_readfirstlane_b32 s7, v13 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_581 ; %bb.580: ; in Loop: Header=BB6_573 Depth=1 v_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v13, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v14, 2 :: v_dual_mov_b32 v15, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v8, s8 v_add_co_ci_u32_e32 v5, vcc_lo, s9, v9, vcc_lo global_store_b128 v[4:5], v[12:15], off offset:8 .LBB6_581: ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 v_lshlrev_b64 v[4:5], 6, v[28:29] s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v10, s8 v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo s_mov_b32 s11, s3 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v14, vcc_lo, v10, v4 s_mov_b32 s8, s3 s_mov_b32 s9, s3 s_mov_b32 s10, s3 v_add_co_ci_u32_e32 v15, vcc_lo, v11, v5, vcc_lo v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v13, s11 v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v12, s10 v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8 s_clause 0x3 global_store_b128 v[14:15], v[2:5], off global_store_b128 v[14:15], v[10:13], off offset:16 global_store_b128 v[14:15], v[10:13], off offset:32 global_store_b128 v[14:15], v[10:13], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_589 ; %bb.582: ; in Loop: Header=BB6_573 Depth=1 s_clause 0x1 global_load_b64 v[18:19], v29, s[34:35] offset:32 glc global_load_b64 v[4:5], v29, s[34:35] offset:40 v_dual_mov_b32 v16, s4 :: v_dual_mov_b32 v17, s5 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v4 v_readfirstlane_b32 s9, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v4, vcc_lo, v8, s8 v_add_co_ci_u32_e32 v5, vcc_lo, s10, v9, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[4:5], v[18:19], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v29, v[16:19], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[12:13], v[18:19] s_cbranch_execz .LBB6_585 ; %bb.583: ; %.preheader1.i.i.i157.preheader ; in Loop: Header=BB6_573 Depth=1 s_mov_b32 s9, 0 .LBB6_584: ; %.preheader1.i.i.i157 ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 v_dual_mov_b32 v10, s4 :: v_dual_mov_b32 v11, s5 s_sleep 1 global_store_b64 v[4:5], v[12:13], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v29, v[10:13], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13] v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB6_584 .LBB6_585: ; %Flow1289 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s8 global_load_b64 v[4:5], v29, s[34:35] offset:16 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v10, s9, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB6_587 ; %bb.586: ; in Loop: Header=BB6_573 Depth=1 s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v11, v3 :: v_dual_mov_b32 v10, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[4:5], v[10:11], off offset:8 .LBB6_587: ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[10:11], v[4:5], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] s_cbranch_vccnz .LBB6_589 ; %bb.588: ; in Loop: Header=BB6_573 Depth=1 global_load_b32 v28, v[4:5], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v28 s_waitcnt_vscnt null, 0x0 global_store_b64 v[10:11], v[28:29], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_589: ; %Flow1290 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v4, vcc_lo, v8, s1 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, v4, 20 v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo s_branch .LBB6_593 .p2align 6 .LBB6_590: ; in Loop: Header=BB6_593 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v8 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_592 ; %bb.591: ; in Loop: Header=BB6_593 Depth=2 s_sleep 1 s_cbranch_execnz .LBB6_593 s_branch .LBB6_595 .p2align 6 .LBB6_592: ; in Loop: Header=BB6_573 Depth=1 s_branch .LBB6_595 .LBB6_593: ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 v_mov_b32_e32 v8, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_590 ; %bb.594: ; in Loop: Header=BB6_593 Depth=2 global_load_b32 v8, v[4:5], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v8, 1, v8 s_branch .LBB6_590 .LBB6_595: ; in Loop: Header=BB6_573 Depth=1 global_load_b64 v[4:5], v[14:15], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_599 ; %bb.596: ; in Loop: Header=BB6_573 Depth=1 s_clause 0x2 global_load_b64 v[10:11], v29, s[34:35] offset:40 global_load_b64 v[14:15], v29, s[34:35] offset:24 glc global_load_b64 v[12:13], v29, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v16, vcc_lo, v10, 1 v_add_co_ci_u32_e32 v17, vcc_lo, 0, v11, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v8, vcc_lo, v16, s4 v_add_co_ci_u32_e32 v9, vcc_lo, s5, v17, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9] v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16 v_and_b32_e32 v11, v9, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v10, v8, v10 v_mul_hi_u32 v16, v10, 24 v_mul_lo_u32 v10, v10, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v12, vcc_lo, v12, v10 v_mov_b32_e32 v10, v14 v_mul_lo_u32 v11, v11, 24 v_add_nc_u32_e32 v11, v16, v11 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v13, vcc_lo, v13, v11, vcc_lo v_mov_b32_e32 v11, v15 global_store_b64 v[12:13], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[14:15] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_599 ; %bb.597: ; %.preheader.i.i.i156.preheader ; in Loop: Header=BB6_573 Depth=1 s_mov_b32 s0, 0 .LBB6_598: ; %.preheader.i.i.i156 ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 global_store_b64 v[12:13], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[10:11] v_dual_mov_b32 v10, v14 :: v_dual_mov_b32 v11, v15 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_598 .LBB6_599: ; %__ockl_printf_begin.exit160 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_getpc_b64 s[4:5] s_add_u32 s4, s4, .str.4@rel32@lo+4 s_addc_u32 s5, s5, .str.4@rel32@hi+12 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u64 s[4:5], 0 s_cbranch_scc0 .LBB6_678 ; %bb.600: ; in Loop: Header=BB6_573 Depth=1 s_waitcnt vmcnt(0) v_dual_mov_b32 v43, v5 :: v_dual_and_b32 v28, 2, v4 v_dual_mov_b32 v31, v29 :: v_dual_and_b32 v42, -3, v4 s_mov_b64 s[6:7], 17 s_delay_alu instid0(VALU_DEP_2) v_mov_b32_e32 v30, v28 s_branch .LBB6_602 .LBB6_601: ; %__ockl_hostcall_preview.exit20.i177 ; in Loop: Header=BB6_602 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_sub_u32 s6, s6, s8 s_subb_u32 s7, s7, s9 s_add_u32 s4, s4, s8 s_addc_u32 s5, s5, s9 s_cmp_lg_u64 s[6:7], 0 s_cbranch_scc0 .LBB6_679 .LBB6_602: ; Parent Loop BB6_573 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB6_605 Depth 3 ; Child Loop BB6_613 Depth 3 ; Child Loop BB6_620 Depth 3 ; Child Loop BB6_627 Depth 3 ; Child Loop BB6_634 Depth 3 ; Child Loop BB6_641 Depth 3 ; Child Loop BB6_648 Depth 3 ; Child Loop BB6_655 Depth 3 ; Child Loop BB6_663 Depth 3 ; Child Loop BB6_672 Depth 3 ; Child Loop BB6_677 Depth 3 v_cmp_lt_u64_e64 s0, s[6:7], 56 s_delay_alu instid0(VALU_DEP_1) s_and_b32 s0, s0, exec_lo s_cselect_b32 s8, s6, 56 s_cselect_b32 s9, s7, 0 s_cmp_gt_u32 s8, 7 s_cbranch_scc1 .LBB6_607 ; %bb.603: ; in Loop: Header=BB6_602 Depth=2 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_cmp_eq_u32 s8, 0 s_cbranch_scc1 .LBB6_606 ; %bb.604: ; %.preheader31.i161.preheader ; in Loop: Header=BB6_602 Depth=2 s_lshl_b64 s[0:1], s[8:9], 3 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], s[4:5] .LBB6_605: ; %.preheader31.i161 ; Parent Loop BB6_573 Depth=1 ; Parent Loop BB6_602 Depth=2 ; => This Inner Loop Header: Depth=3 global_load_u8 v8, v29, s[12:13] s_waitcnt vmcnt(0) v_and_b32_e32 v28, 0xffff, v8 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[8:9], s10, v[28:29] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_add_u32 s12, s12, 1 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s0, s10 v_or_b32_e32 v10, v8, v10 v_or_b32_e32 v11, v9, v11 s_cbranch_scc1 .LBB6_605 .LBB6_606: ; %Flow1260 ; in Loop: Header=BB6_602 Depth=2 s_mov_b32 s0, 0 s_mov_b32 s14, 0 s_branch .LBB6_608 .LBB6_607: ; in Loop: Header=BB6_602 Depth=2 s_mov_b32 s0, -1 ; implicit-def: $vgpr10_vgpr11 ; implicit-def: $sgpr14 .LBB6_608: ; %Flow1262 ; in Loop: Header=BB6_602 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s0 s_mov_b64 s[0:1], s[4:5] s_cbranch_vccnz .LBB6_610 ; %bb.609: ; in Loop: Header=BB6_602 Depth=2 global_load_b64 v[10:11], v29, s[4:5] s_add_i32 s14, s8, -8 s_add_u32 s0, s4, 8 s_addc_u32 s1, s5, 0 .LBB6_610: ; %.loopexit32.i162 ; in Loop: Header=BB6_602 Depth=2 s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB6_615 ; %bb.611: ; in Loop: Header=BB6_602 Depth=2 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB6_614 ; %bb.612: ; %.preheader29.i163.preheader ; in Loop: Header=BB6_602 Depth=2 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB6_613: ; %.preheader29.i163 ; Parent Loop BB6_573 Depth=1 ; Parent Loop BB6_602 Depth=2 ; => This Inner Loop Header: Depth=3 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v8, v29, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v28, 0xffff, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], s10, v[28:29] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s14, s12 v_or_b32_e32 v12, v8, v12 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v13, v9, v13 s_cbranch_scc1 .LBB6_613 .LBB6_614: ; %Flow1255 ; in Loop: Header=BB6_602 Depth=2 s_mov_b32 s15, 0 s_cbranch_execz .LBB6_616 s_branch .LBB6_617 .LBB6_615: ; in Loop: Header=BB6_602 Depth=2 ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $sgpr15 .LBB6_616: ; in Loop: Header=BB6_602 Depth=2 global_load_b64 v[12:13], v29, s[0:1] s_add_i32 s15, s14, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_617: ; %.loopexit30.i164 ; in Loop: Header=BB6_602 Depth=2 s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB6_622 ; %bb.618: ; in Loop: Header=BB6_602 Depth=2 v_mov_b32_e32 v14, 0 v_mov_b32_e32 v15, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB6_621 ; %bb.619: ; %.preheader27.i165.preheader ; in Loop: Header=BB6_602 Depth=2 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB6_620: ; %.preheader27.i165 ; Parent Loop BB6_573 Depth=1 ; Parent Loop BB6_602 Depth=2 ; => This Inner Loop Header: Depth=3 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v8, v29, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v28, 0xffff, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], s10, v[28:29] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v14, v8, v14 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v15, v9, v15 s_cbranch_scc1 .LBB6_620 .LBB6_621: ; %Flow1250 ; in Loop: Header=BB6_602 Depth=2 s_mov_b32 s14, 0 s_cbranch_execz .LBB6_623 s_branch .LBB6_624 .LBB6_622: ; in Loop: Header=BB6_602 Depth=2 ; implicit-def: $sgpr14 .LBB6_623: ; in Loop: Header=BB6_602 Depth=2 global_load_b64 v[14:15], v29, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_624: ; %.loopexit28.i166 ; in Loop: Header=BB6_602 Depth=2 s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB6_629 ; %bb.625: ; in Loop: Header=BB6_602 Depth=2 v_mov_b32_e32 v16, 0 v_mov_b32_e32 v17, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB6_628 ; %bb.626: ; %.preheader25.i167.preheader ; in Loop: Header=BB6_602 Depth=2 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB6_627: ; %.preheader25.i167 ; Parent Loop BB6_573 Depth=1 ; Parent Loop BB6_602 Depth=2 ; => This Inner Loop Header: Depth=3 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v8, v29, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v28, 0xffff, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], s10, v[28:29] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s14, s12 v_or_b32_e32 v16, v8, v16 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v17, v9, v17 s_cbranch_scc1 .LBB6_627 .LBB6_628: ; %Flow1245 ; in Loop: Header=BB6_602 Depth=2 s_mov_b32 s15, 0 s_cbranch_execz .LBB6_630 s_branch .LBB6_631 .LBB6_629: ; in Loop: Header=BB6_602 Depth=2 ; implicit-def: $vgpr16_vgpr17 ; implicit-def: $sgpr15 .LBB6_630: ; in Loop: Header=BB6_602 Depth=2 global_load_b64 v[16:17], v29, s[0:1] s_add_i32 s15, s14, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_631: ; %.loopexit26.i168 ; in Loop: Header=BB6_602 Depth=2 s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB6_636 ; %bb.632: ; in Loop: Header=BB6_602 Depth=2 v_mov_b32_e32 v18, 0 v_mov_b32_e32 v19, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB6_635 ; %bb.633: ; %.preheader23.i169.preheader ; in Loop: Header=BB6_602 Depth=2 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB6_634: ; %.preheader23.i169 ; Parent Loop BB6_573 Depth=1 ; Parent Loop BB6_602 Depth=2 ; => This Inner Loop Header: Depth=3 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v8, v29, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v28, 0xffff, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], s10, v[28:29] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v18, v8, v18 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v19, v9, v19 s_cbranch_scc1 .LBB6_634 .LBB6_635: ; %Flow1240 ; in Loop: Header=BB6_602 Depth=2 s_mov_b32 s14, 0 s_cbranch_execz .LBB6_637 s_branch .LBB6_638 .LBB6_636: ; in Loop: Header=BB6_602 Depth=2 ; implicit-def: $sgpr14 .LBB6_637: ; in Loop: Header=BB6_602 Depth=2 global_load_b64 v[18:19], v29, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_638: ; %.loopexit24.i170 ; in Loop: Header=BB6_602 Depth=2 s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB6_643 ; %bb.639: ; in Loop: Header=BB6_602 Depth=2 v_mov_b32_e32 v20, 0 v_mov_b32_e32 v21, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB6_642 ; %bb.640: ; %.preheader21.i171.preheader ; in Loop: Header=BB6_602 Depth=2 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB6_641: ; %.preheader21.i171 ; Parent Loop BB6_573 Depth=1 ; Parent Loop BB6_602 Depth=2 ; => This Inner Loop Header: Depth=3 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v8, v29, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v28, 0xffff, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], s10, v[28:29] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s14, s12 v_or_b32_e32 v20, v8, v20 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v21, v9, v21 s_cbranch_scc1 .LBB6_641 .LBB6_642: ; %Flow1235 ; in Loop: Header=BB6_602 Depth=2 s_mov_b32 s15, 0 s_cbranch_execz .LBB6_644 s_branch .LBB6_645 .LBB6_643: ; in Loop: Header=BB6_602 Depth=2 ; implicit-def: $vgpr20_vgpr21 ; implicit-def: $sgpr15 .LBB6_644: ; in Loop: Header=BB6_602 Depth=2 global_load_b64 v[20:21], v29, s[0:1] s_add_i32 s15, s14, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB6_645: ; %.loopexit22.i172 ; in Loop: Header=BB6_602 Depth=2 s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB6_650 ; %bb.646: ; in Loop: Header=BB6_602 Depth=2 v_mov_b32_e32 v22, 0 v_mov_b32_e32 v23, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB6_649 ; %bb.647: ; %.preheader.i173.preheader ; in Loop: Header=BB6_602 Depth=2 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], s[0:1] .LBB6_648: ; %.preheader.i173 ; Parent Loop BB6_573 Depth=1 ; Parent Loop BB6_602 Depth=2 ; => This Inner Loop Header: Depth=3 global_load_u8 v8, v29, s[12:13] s_add_i32 s15, s15, -1 s_waitcnt vmcnt(0) v_and_b32_e32 v28, 0xffff, v8 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[8:9], s10, v[28:29] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_add_u32 s12, s12, 1 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s15, 0 v_or_b32_e32 v22, v8, v22 v_or_b32_e32 v23, v9, v23 s_cbranch_scc1 .LBB6_648 .LBB6_649: ; %Flow1230 ; in Loop: Header=BB6_602 Depth=2 s_cbranch_execz .LBB6_651 s_branch .LBB6_652 .LBB6_650: ; in Loop: Header=BB6_602 Depth=2 .LBB6_651: ; in Loop: Header=BB6_602 Depth=2 global_load_b64 v[22:23], v29, s[0:1] .LBB6_652: ; %.loopexit.i174 ; in Loop: Header=BB6_602 Depth=2 v_mov_b32_e32 v28, v40 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v28 v_cmp_eq_u32_e64 s0, s0, v28 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_658 ; %bb.653: ; in Loop: Header=BB6_602 Depth=2 global_load_b64 v[26:27], v29, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[8:9], v29, s[34:35] offset:40 global_load_b64 v[24:25], v29, s[34:35] s_mov_b32 s10, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v9, v9, v27 v_and_b32_e32 v8, v8, v26 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v9, v9, 24 v_mul_hi_u32 v32, v8, 24 v_mul_lo_u32 v8, v8, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v9, v32, v9 s_waitcnt vmcnt(0) v_add_co_u32 v8, vcc_lo, v24, v8 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v9, vcc_lo, v25, v9, vcc_lo global_load_b64 v[24:25], v[8:9], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[8:9], v29, v[24:27], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[8:9], v[26:27] s_cbranch_execz .LBB6_657 ; %bb.654: ; %.preheader3.i.i19.i181.preheader ; in Loop: Header=BB6_602 Depth=2 s_mov_b32 s11, 0 .p2align 6 .LBB6_655: ; %.preheader3.i.i19.i181 ; Parent Loop BB6_573 Depth=1 ; Parent Loop BB6_602 Depth=2 ; => This Inner Loop Header: Depth=3 s_sleep 1 s_clause 0x1 global_load_b64 v[24:25], v29, s[34:35] offset:40 global_load_b64 v[32:33], v29, s[34:35] v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v24, v24, v26 s_waitcnt vmcnt(0) v_mad_u64_u32 v[8:9], null, v24, 24, v[32:33] v_and_b32_e32 v32, v25, v27 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[24:25], null, v32, 24, v[9:10] v_mov_b32_e32 v9, v24 global_load_b64 v[24:25], v[8:9], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[8:9], v29, v[24:27], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[26:27] s_or_b32 s11, vcc_lo, s11 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s11 s_cbranch_execnz .LBB6_655 ; %bb.656: ; %Flow1225 ; in Loop: Header=BB6_602 Depth=2 s_or_b32 exec_lo, exec_lo, s11 .LBB6_657: ; %Flow1227 ; in Loop: Header=BB6_602 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s10 .LBB6_658: ; %.loopexit4.i.i14.i175 ; in Loop: Header=BB6_602 Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_clause 0x1 global_load_b64 v[32:33], v29, s[34:35] offset:40 global_load_b128 v[24:27], v29, s[34:35] v_readfirstlane_b32 s10, v8 v_readfirstlane_b32 s11, v9 s_mov_b32 s14, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s12, v32 v_readfirstlane_b32 s13, v33 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[12:13], s[10:11], s[12:13] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_660 ; %bb.659: ; in Loop: Header=BB6_602 Depth=2 v_dual_mov_b32 v32, s14 :: v_dual_mov_b32 v33, 0 s_mul_i32 s14, s13, 24 s_mul_hi_u32 s15, s12, 24 v_dual_mov_b32 v34, 2 :: v_dual_mov_b32 v35, 1 s_add_i32 s15, s15, s14 s_mul_i32 s14, s12, 24 s_waitcnt vmcnt(0) v_add_co_u32 v8, vcc_lo, v24, s14 v_add_co_ci_u32_e32 v9, vcc_lo, s15, v25, vcc_lo global_store_b128 v[8:9], v[32:35], off offset:8 .LBB6_660: ; in Loop: Header=BB6_602 Depth=2 s_or_b32 exec_lo, exec_lo, s1 v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56 v_or_b32_e32 v8, v43, v31 v_or_b32_e32 v32, v42, v30 s_lshl_b64 s[14:15], s[12:13], 12 s_lshl_b32 s1, s8, 2 s_delay_alu instid0(SALU_CYCLE_1) s_add_i32 s1, s1, 28 v_cndmask_b32_e32 v9, v8, v43, vcc_lo v_cndmask_b32_e32 v8, v32, v42, vcc_lo v_lshlrev_b64 v[32:33], 6, v[28:29] s_waitcnt vmcnt(0) v_add_co_u32 v26, vcc_lo, v26, s14 v_add_co_ci_u32_e32 v27, vcc_lo, s15, v27, vcc_lo s_and_b32 s1, s1, 0x1e0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v26, vcc_lo, v26, v32 v_and_or_b32 v8, v8, 0xffffff1f, s1 v_add_co_ci_u32_e32 v27, vcc_lo, v27, v33, vcc_lo s_clause 0x3 global_store_b128 v[26:27], v[8:11], off global_store_b128 v[26:27], v[12:15], off offset:16 global_store_b128 v[26:27], v[16:19], off offset:32 global_store_b128 v[26:27], v[20:23], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_668 ; %bb.661: ; in Loop: Header=BB6_602 Depth=2 s_clause 0x1 global_load_b64 v[16:17], v29, s[34:35] offset:32 glc global_load_b64 v[8:9], v29, s[34:35] offset:40 v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v15, s11 s_waitcnt vmcnt(0) v_readfirstlane_b32 s14, v8 v_readfirstlane_b32 s15, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[14:15], s[14:15], s[10:11] s_mul_i32 s15, s15, 24 s_mul_hi_u32 s16, s14, 24 s_mul_i32 s14, s14, 24 s_add_i32 s16, s16, s15 v_add_co_u32 v12, vcc_lo, v24, s14 v_add_co_ci_u32_e32 v13, vcc_lo, s16, v25, vcc_lo s_mov_b32 s14, exec_lo global_store_b64 v[12:13], v[16:17], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v29, v[14:17], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[10:11], v[16:17] s_cbranch_execz .LBB6_664 ; %bb.662: ; %.preheader1.i.i17.i179.preheader ; in Loop: Header=BB6_602 Depth=2 s_mov_b32 s15, 0 .LBB6_663: ; %.preheader1.i.i17.i179 ; Parent Loop BB6_573 Depth=1 ; Parent Loop BB6_602 Depth=2 ; => This Inner Loop Header: Depth=3 v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11 s_sleep 1 global_store_b64 v[12:13], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v29, v[8:11], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11] v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8 s_or_b32 s15, vcc_lo, s15 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s15 s_cbranch_execnz .LBB6_663 .LBB6_664: ; %Flow1223 ; in Loop: Header=BB6_602 Depth=2 s_or_b32 exec_lo, exec_lo, s14 global_load_b64 v[8:9], v29, s[34:35] offset:16 s_mov_b32 s15, exec_lo s_mov_b32 s14, exec_lo v_mbcnt_lo_u32_b32 v10, s15, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB6_666 ; %bb.665: ; in Loop: Header=BB6_602 Depth=2 s_bcnt1_i32_b32 s15, s15 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, s15 s_waitcnt vmcnt(0) global_atomic_add_u64 v[8:9], v[10:11], off offset:8 .LBB6_666: ; in Loop: Header=BB6_602 Depth=2 s_or_b32 exec_lo, exec_lo, s14 s_waitcnt vmcnt(0) global_load_b64 v[10:11], v[8:9], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] s_cbranch_vccnz .LBB6_668 ; %bb.667: ; in Loop: Header=BB6_602 Depth=2 global_load_b32 v28, v[8:9], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s14, v28 s_waitcnt_vscnt null, 0x0 global_store_b64 v[10:11], v[28:29], off s_and_b32 m0, s14, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_668: ; %Flow1224 ; in Loop: Header=BB6_602 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s13, 24 s_mul_hi_u32 s13, s12, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s13, s13, s1 s_mul_i32 s1, s12, 24 v_add_co_u32 v8, vcc_lo, v24, s1 v_add_co_ci_u32_e32 v9, vcc_lo, s13, v25, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v8, vcc_lo, v8, 20 v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo s_branch .LBB6_672 .p2align 6 .LBB6_669: ; in Loop: Header=BB6_672 Depth=3 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v10 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_671 ; %bb.670: ; in Loop: Header=BB6_672 Depth=3 s_sleep 1 s_cbranch_execnz .LBB6_672 s_branch .LBB6_674 .p2align 6 .LBB6_671: ; in Loop: Header=BB6_602 Depth=2 s_branch .LBB6_674 .LBB6_672: ; Parent Loop BB6_573 Depth=1 ; Parent Loop BB6_602 Depth=2 ; => This Inner Loop Header: Depth=3 v_mov_b32_e32 v10, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_669 ; %bb.673: ; in Loop: Header=BB6_672 Depth=3 global_load_b32 v10, v[8:9], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v10, 1, v10 s_branch .LBB6_669 .LBB6_674: ; in Loop: Header=BB6_602 Depth=2 global_load_b64 v[42:43], v[26:27], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_601 ; %bb.675: ; in Loop: Header=BB6_602 Depth=2 s_clause 0x2 global_load_b64 v[10:11], v29, s[34:35] offset:40 global_load_b64 v[14:15], v29, s[34:35] offset:24 glc global_load_b64 v[12:13], v29, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v16, vcc_lo, v10, 1 v_add_co_ci_u32_e32 v17, vcc_lo, 0, v11, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v8, vcc_lo, v16, s10 v_add_co_ci_u32_e32 v9, vcc_lo, s11, v17, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9] v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16 v_and_b32_e32 v11, v9, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v10, v8, v10 v_mul_hi_u32 v16, v10, 24 v_mul_lo_u32 v10, v10, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v12, vcc_lo, v12, v10 v_mov_b32_e32 v10, v14 v_mul_lo_u32 v11, v11, 24 v_add_nc_u32_e32 v11, v16, v11 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v13, vcc_lo, v13, v11, vcc_lo v_mov_b32_e32 v11, v15 global_store_b64 v[12:13], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[14:15] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_601 ; %bb.676: ; %.preheader.i.i16.i178.preheader ; in Loop: Header=BB6_602 Depth=2 s_mov_b32 s0, 0 .LBB6_677: ; %.preheader.i.i16.i178 ; Parent Loop BB6_573 Depth=1 ; Parent Loop BB6_602 Depth=2 ; => This Inner Loop Header: Depth=3 s_sleep 1 global_store_b64 v[12:13], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[10:11] v_dual_mov_b32 v10, v14 :: v_dual_mov_b32 v11, v15 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_677 s_branch .LBB6_601 .LBB6_678: ; in Loop: Header=BB6_573 Depth=1 s_cbranch_execnz .LBB6_680 s_branch .LBB6_707 .LBB6_679: ; %Flow1263 ; in Loop: Header=BB6_573 Depth=1 s_branch .LBB6_707 .LBB6_680: ; in Loop: Header=BB6_573 Depth=1 v_mov_b32_e32 v28, v40 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v28 v_cmp_eq_u32_e64 s0, s0, v28 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_686 ; %bb.681: ; in Loop: Header=BB6_573 Depth=1 global_load_b64 v[10:11], v29, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[8:9], v29, s[34:35] offset:40 global_load_b64 v[12:13], v29, s[34:35] s_mov_b32 s4, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v9, v9, v11 v_and_b32_e32 v8, v8, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v9, v9, 24 v_mul_hi_u32 v14, v8, 24 v_mul_lo_u32 v8, v8, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v9, v14, v9 s_waitcnt vmcnt(0) v_add_co_u32 v8, vcc_lo, v12, v8 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v9, vcc_lo, v13, v9, vcc_lo global_load_b64 v[8:9], v[8:9], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[12:13], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[12:13], v[10:11] s_cbranch_execz .LBB6_685 ; %bb.682: ; %.preheader3.i.i.i188.preheader ; in Loop: Header=BB6_573 Depth=1 s_mov_b32 s5, 0 .p2align 6 .LBB6_683: ; %.preheader3.i.i.i188 ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 s_clause 0x1 global_load_b64 v[8:9], v29, s[34:35] offset:40 global_load_b64 v[14:15], v29, s[34:35] v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v8, v8, v10 v_and_b32_e32 v9, v9, v11 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[12:13], null, v8, 24, v[14:15] v_mov_b32_e32 v8, v13 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[13:14], null, v9, 24, v[8:9] global_load_b64 v[8:9], v[12:13], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[12:13], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB6_683 ; %bb.684: ; %Flow1275 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s5 .LBB6_685: ; %Flow1277 ; in Loop: Header=BB6_573 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB6_686: ; %.loopexit4.i.i.i182 ; in Loop: Header=BB6_573 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_clause 0x1 global_load_b64 v[14:15], v29, s[34:35] offset:40 global_load_b128 v[8:11], v29, s[34:35] v_readfirstlane_b32 s4, v12 v_readfirstlane_b32 s5, v13 s_mov_b32 s8, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v14 v_readfirstlane_b32 s7, v15 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_688 ; %bb.687: ; in Loop: Header=BB6_573 Depth=1 v_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v13, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v14, 2 :: v_dual_mov_b32 v15, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v16, vcc_lo, v8, s8 v_add_co_ci_u32_e32 v17, vcc_lo, s9, v9, vcc_lo global_store_b128 v[16:17], v[12:15], off offset:8 .LBB6_688: ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 s_mov_b32 s11, s3 s_waitcnt vmcnt(0) v_add_co_u32 v12, vcc_lo, v10, s8 v_add_co_ci_u32_e32 v13, vcc_lo, s9, v11, vcc_lo v_lshlrev_b64 v[10:11], 6, v[28:29] s_mov_b32 s8, s3 s_mov_b32 s9, s3 s_mov_b32 s10, s3 v_mov_b32_e32 v16, 0 v_and_or_b32 v4, v4, 0xffffff1f, 32 v_add_co_u32 v14, vcc_lo, v12, v10 v_add_co_ci_u32_e32 v15, vcc_lo, v13, v11, vcc_lo v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10 v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8 v_mov_b32_e32 v17, v16 s_clause 0x4 global_store_b64 v[14:15], v[4:5], off global_store_b128 v[14:15], v[10:13], off offset:8 global_store_b128 v[14:15], v[10:13], off offset:24 global_store_b128 v[14:15], v[10:13], off offset:40 global_store_b64 v[14:15], v[16:17], off offset:56 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_696 ; %bb.689: ; in Loop: Header=BB6_573 Depth=1 s_clause 0x1 global_load_b64 v[18:19], v29, s[34:35] offset:32 glc global_load_b64 v[4:5], v29, s[34:35] offset:40 v_dual_mov_b32 v16, s4 :: v_dual_mov_b32 v17, s5 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v4 v_readfirstlane_b32 s9, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v4, vcc_lo, v8, s8 v_add_co_ci_u32_e32 v5, vcc_lo, s10, v9, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[4:5], v[18:19], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v29, v[16:19], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[12:13], v[18:19] s_cbranch_execz .LBB6_692 ; %bb.690: ; %.preheader1.i.i.i186.preheader ; in Loop: Header=BB6_573 Depth=1 s_mov_b32 s9, 0 .LBB6_691: ; %.preheader1.i.i.i186 ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 v_dual_mov_b32 v10, s4 :: v_dual_mov_b32 v11, s5 s_sleep 1 global_store_b64 v[4:5], v[12:13], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v29, v[10:13], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13] v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB6_691 .LBB6_692: ; %Flow1273 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s8 global_load_b64 v[4:5], v29, s[34:35] offset:16 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v10, s9, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB6_694 ; %bb.693: ; in Loop: Header=BB6_573 Depth=1 s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[4:5], v[10:11], off offset:8 .LBB6_694: ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[10:11], v[4:5], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11] s_cbranch_vccnz .LBB6_696 ; %bb.695: ; in Loop: Header=BB6_573 Depth=1 global_load_b32 v28, v[4:5], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v28 s_waitcnt_vscnt null, 0x0 global_store_b64 v[10:11], v[28:29], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_696: ; %Flow1274 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v4, vcc_lo, v8, s1 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, v4, 20 v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo s_branch .LBB6_700 .p2align 6 .LBB6_697: ; in Loop: Header=BB6_700 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v8 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_699 ; %bb.698: ; in Loop: Header=BB6_700 Depth=2 s_sleep 1 s_cbranch_execnz .LBB6_700 s_branch .LBB6_702 .p2align 6 .LBB6_699: ; in Loop: Header=BB6_573 Depth=1 s_branch .LBB6_702 .LBB6_700: ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 v_mov_b32_e32 v8, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_697 ; %bb.701: ; in Loop: Header=BB6_700 Depth=2 global_load_b32 v8, v[4:5], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v8, 1, v8 s_branch .LBB6_697 .LBB6_702: ; in Loop: Header=BB6_573 Depth=1 global_load_b64 v[42:43], v[14:15], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_706 ; %bb.703: ; in Loop: Header=BB6_573 Depth=1 s_clause 0x2 global_load_b64 v[4:5], v29, s[34:35] offset:40 global_load_b64 v[12:13], v29, s[34:35] offset:24 glc global_load_b64 v[10:11], v29, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v14, vcc_lo, v4, 1 v_add_co_ci_u32_e32 v15, vcc_lo, 0, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v8, vcc_lo, v14, s4 v_add_co_ci_u32_e32 v9, vcc_lo, s5, v15, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9] v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14 v_and_b32_e32 v5, v9, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v4, v8, v4 v_mul_hi_u32 v14, v4, 24 v_mul_lo_u32 v4, v4, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v4, vcc_lo, v10, v4 v_mov_b32_e32 v10, v12 v_mul_lo_u32 v5, v5, 24 v_add_nc_u32_e32 v5, v14, v5 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo v_mov_b32_e32 v11, v13 global_store_b64 v[4:5], v[12:13], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[12:13] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_706 ; %bb.704: ; %.preheader.i.i.i185.preheader ; in Loop: Header=BB6_573 Depth=1 s_mov_b32 s0, 0 .LBB6_705: ; %.preheader.i.i.i185 ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 global_store_b64 v[4:5], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11] v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_705 .LBB6_706: ; %__ockl_hostcall_preview.exit.i184 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s1 .LBB6_707: ; %__ockl_printf_append_string_n.exit189 ; in Loop: Header=BB6_573 Depth=1 v_mov_b32_e32 v28, v40 s_waitcnt vmcnt(0) v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 ;;#ASMSTART ;;#ASMEND v_readfirstlane_b32 s0, v28 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s0, s0, v28 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_713 ; %bb.708: ; in Loop: Header=BB6_573 Depth=1 global_load_b64 v[10:11], v29, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[4:5], v29, s[34:35] offset:40 global_load_b64 v[8:9], v29, s[34:35] s_mov_b32 s4, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v5, v5, v11 v_and_b32_e32 v4, v4, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v5, v5, 24 v_mul_hi_u32 v12, v4, 24 v_mul_lo_u32 v4, v4, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v5, v12, v5 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v8, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo global_load_b64 v[8:9], v[4:5], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[4:5], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[4:5], v[10:11] s_cbranch_execz .LBB6_712 ; %bb.709: ; %.preheader3.i.i.i196.preheader ; in Loop: Header=BB6_573 Depth=1 s_mov_b32 s5, 0 .p2align 6 .LBB6_710: ; %.preheader3.i.i.i196 ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 s_clause 0x1 global_load_b64 v[8:9], v29, s[34:35] offset:40 global_load_b64 v[12:13], v29, s[34:35] v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v4 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v8, v8, v10 s_waitcnt vmcnt(0) v_mad_u64_u32 v[4:5], null, v8, 24, v[12:13] v_and_b32_e32 v12, v9, v11 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[8:9], null, v12, 24, v[5:6] v_mov_b32_e32 v5, v8 global_load_b64 v[8:9], v[4:5], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[4:5], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[10:11] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB6_710 ; %bb.711: ; %Flow1211 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s5 .LBB6_712: ; %Flow1213 ; in Loop: Header=BB6_573 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB6_713: ; %.loopexit4.i.i.i190 ; in Loop: Header=BB6_573 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_clause 0x1 global_load_b64 v[12:13], v29, s[34:35] offset:40 global_load_b128 v[8:11], v29, s[34:35] v_readfirstlane_b32 s4, v4 v_readfirstlane_b32 s5, v5 s_mov_b32 s8, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v12 v_readfirstlane_b32 s7, v13 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_715 ; %bb.714: ; in Loop: Header=BB6_573 Depth=1 v_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v13, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v14, 2 :: v_dual_mov_b32 v15, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v8, s8 v_add_co_ci_u32_e32 v5, vcc_lo, s9, v9, vcc_lo global_store_b128 v[4:5], v[12:15], off offset:8 .LBB6_715: ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 v_lshlrev_b64 v[4:5], 6, v[28:29] s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v10, s8 v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo s_mov_b32 s11, s3 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, v10, v4 s_mov_b32 s8, s3 s_mov_b32 s9, s3 s_mov_b32 s10, s3 v_and_or_b32 v42, v42, 0xffffff1f, 32 v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10 v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8 s_clause 0x3 global_store_b128 v[4:5], v[42:45], off global_store_b128 v[4:5], v[10:13], off offset:16 global_store_b128 v[4:5], v[10:13], off offset:32 global_store_b128 v[4:5], v[10:13], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_723 ; %bb.716: ; in Loop: Header=BB6_573 Depth=1 s_clause 0x1 global_load_b64 v[18:19], v29, s[34:35] offset:32 glc global_load_b64 v[10:11], v29, s[34:35] offset:40 v_dual_mov_b32 v16, s4 :: v_dual_mov_b32 v17, s5 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v10 v_readfirstlane_b32 s9, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v14, vcc_lo, v8, s8 v_add_co_ci_u32_e32 v15, vcc_lo, s10, v9, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[14:15], v[18:19], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[12:13], v29, v[16:19], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[12:13], v[18:19] s_cbranch_execz .LBB6_719 ; %bb.717: ; %.preheader1.i.i.i194.preheader ; in Loop: Header=BB6_573 Depth=1 s_mov_b32 s9, 0 .LBB6_718: ; %.preheader1.i.i.i194 ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 v_dual_mov_b32 v10, s4 :: v_dual_mov_b32 v11, s5 s_sleep 1 global_store_b64 v[14:15], v[12:13], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v29, v[10:13], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13] v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB6_718 .LBB6_719: ; %Flow1209 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s8 global_load_b64 v[10:11], v29, s[34:35] offset:16 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v12, s9, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v12 s_cbranch_execz .LBB6_721 ; %bb.720: ; in Loop: Header=BB6_573 Depth=1 s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v12, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[10:11], v[12:13], off offset:8 .LBB6_721: ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[12:13], v[10:11], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13] s_cbranch_vccnz .LBB6_723 ; %bb.722: ; in Loop: Header=BB6_573 Depth=1 global_load_b32 v28, v[10:11], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v28 s_waitcnt_vscnt null, 0x0 global_store_b64 v[12:13], v[28:29], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_723: ; %Flow1210 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v8, vcc_lo, v8, s1 v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v8, vcc_lo, v8, 20 v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo s_branch .LBB6_727 .p2align 6 .LBB6_724: ; in Loop: Header=BB6_727 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v10 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_726 ; %bb.725: ; in Loop: Header=BB6_727 Depth=2 s_sleep 1 s_cbranch_execnz .LBB6_727 s_branch .LBB6_729 .p2align 6 .LBB6_726: ; in Loop: Header=BB6_573 Depth=1 s_branch .LBB6_729 .LBB6_727: ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 v_mov_b32_e32 v10, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_724 ; %bb.728: ; in Loop: Header=BB6_727 Depth=2 global_load_b32 v10, v[8:9], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v10, 1, v10 s_branch .LBB6_724 .LBB6_729: ; in Loop: Header=BB6_573 Depth=1 global_load_b64 v[4:5], v[4:5], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_733 ; %bb.730: ; in Loop: Header=BB6_573 Depth=1 s_clause 0x2 global_load_b64 v[10:11], v29, s[34:35] offset:40 global_load_b64 v[14:15], v29, s[34:35] offset:24 glc global_load_b64 v[12:13], v29, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v16, vcc_lo, v10, 1 v_add_co_ci_u32_e32 v17, vcc_lo, 0, v11, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v8, vcc_lo, v16, s4 v_add_co_ci_u32_e32 v9, vcc_lo, s5, v17, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9] v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16 v_and_b32_e32 v11, v9, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v10, v8, v10 v_mul_hi_u32 v16, v10, 24 v_mul_lo_u32 v10, v10, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v12, vcc_lo, v12, v10 v_mov_b32_e32 v10, v14 v_mul_lo_u32 v11, v11, 24 v_add_nc_u32_e32 v11, v16, v11 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v13, vcc_lo, v13, v11, vcc_lo v_mov_b32_e32 v11, v15 global_store_b64 v[12:13], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[14:15] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_733 ; %bb.731: ; %.preheader.i.i.i193.preheader ; in Loop: Header=BB6_573 Depth=1 s_mov_b32 s0, 0 .LBB6_732: ; %.preheader.i.i.i193 ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 global_store_b64 v[12:13], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[14:15], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[10:11] v_dual_mov_b32 v10, v14 :: v_dual_mov_b32 v11, v15 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_732 .LBB6_733: ; %__ockl_printf_append_args.exit197 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v28, v40 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v28 v_cmp_eq_u32_e64 s0, s0, v28 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_739 ; %bb.734: ; in Loop: Header=BB6_573 Depth=1 global_load_b64 v[10:11], v29, s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[8:9], v29, s[34:35] offset:40 global_load_b64 v[12:13], v29, s[34:35] s_mov_b32 s4, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v9, v9, v11 v_and_b32_e32 v8, v8, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v9, v9, 24 v_mul_hi_u32 v14, v8, 24 v_mul_lo_u32 v8, v8, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v9, v14, v9 s_waitcnt vmcnt(0) v_add_co_u32 v8, vcc_lo, v12, v8 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v9, vcc_lo, v13, v9, vcc_lo global_load_b64 v[8:9], v[8:9], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[12:13], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[12:13], v[10:11] s_cbranch_execz .LBB6_738 ; %bb.735: ; %.preheader3.i.i.i204.preheader ; in Loop: Header=BB6_573 Depth=1 s_mov_b32 s5, 0 .p2align 6 .LBB6_736: ; %.preheader3.i.i.i204 ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 s_clause 0x1 global_load_b64 v[8:9], v29, s[34:35] offset:40 global_load_b64 v[14:15], v29, s[34:35] v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v8, v8, v10 v_and_b32_e32 v9, v9, v11 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[12:13], null, v8, 24, v[14:15] v_mov_b32_e32 v8, v13 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[13:14], null, v9, 24, v[8:9] global_load_b64 v[8:9], v[12:13], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[12:13], v29, v[8:11], s[34:35] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB6_736 ; %bb.737: ; %Flow1197 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s5 .LBB6_738: ; %Flow1199 ; in Loop: Header=BB6_573 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB6_739: ; %.loopexit4.i.i.i198 ; in Loop: Header=BB6_573 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_clause 0x1 global_load_b64 v[14:15], v29, s[34:35] offset:40 global_load_b128 v[8:11], v29, s[34:35] v_readfirstlane_b32 s4, v12 v_readfirstlane_b32 s5, v13 s_mov_b32 s8, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v14 v_readfirstlane_b32 s7, v15 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_741 ; %bb.740: ; in Loop: Header=BB6_573 Depth=1 v_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v13, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v14, 2 :: v_dual_mov_b32 v15, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v16, vcc_lo, v8, s8 v_add_co_ci_u32_e32 v17, vcc_lo, s9, v9, vcc_lo global_store_b128 v[16:17], v[12:15], off offset:8 .LBB6_741: ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 s_mov_b32 s11, s3 s_waitcnt vmcnt(0) v_add_co_u32 v12, vcc_lo, v10, s8 v_add_co_ci_u32_e32 v13, vcc_lo, s9, v11, vcc_lo v_lshlrev_b64 v[10:11], 6, v[28:29] s_mov_b32 s8, s3 s_mov_b32 s9, s3 s_mov_b32 s10, s3 v_and_or_b32 v4, v4, 0xffffff1d, 34 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v14, vcc_lo, v12, v10 v_add_co_ci_u32_e32 v15, vcc_lo, v13, v11, vcc_lo v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10 v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8 s_waitcnt lgkmcnt(0) s_clause 0x3 global_store_b128 v[14:15], v[4:7], off global_store_b128 v[14:15], v[10:13], off offset:16 global_store_b128 v[14:15], v[10:13], off offset:32 global_store_b128 v[14:15], v[10:13], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_749 ; %bb.742: ; in Loop: Header=BB6_573 Depth=1 s_clause 0x1 global_load_b64 v[14:15], v29, s[34:35] offset:32 glc global_load_b64 v[4:5], v29, s[34:35] offset:40 v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v13, s5 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v4 v_readfirstlane_b32 s9, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v10, vcc_lo, v8, s8 v_add_co_ci_u32_e32 v11, vcc_lo, s10, v9, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[10:11], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[6:7], v29, v[12:15], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[6:7], v[14:15] s_cbranch_execz .LBB6_745 ; %bb.743: ; %.preheader1.i.i.i202.preheader ; in Loop: Header=BB6_573 Depth=1 s_mov_b32 s9, 0 .LBB6_744: ; %.preheader1.i.i.i202 ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 s_sleep 1 global_store_b64 v[10:11], v[6:7], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v29, v[4:7], s[34:35] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7] v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB6_744 .LBB6_745: ; %Flow1195 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s8 global_load_b64 v[4:5], v29, s[34:35] offset:16 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v6, s9, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v6 s_cbranch_execz .LBB6_747 ; %bb.746: ; in Loop: Header=BB6_573 Depth=1 s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[4:5], v[6:7], off offset:8 .LBB6_747: ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[6:7], v[4:5], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7] s_cbranch_vccnz .LBB6_749 ; %bb.748: ; in Loop: Header=BB6_573 Depth=1 global_load_b32 v28, v[4:5], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v28 s_waitcnt_vscnt null, 0x0 global_store_b64 v[6:7], v[28:29], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB6_749: ; %Flow1196 ; in Loop: Header=BB6_573 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v4, vcc_lo, v8, s1 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, v4, 20 v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo s_branch .LBB6_753 .p2align 6 .LBB6_750: ; in Loop: Header=BB6_753 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v6 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB6_752 ; %bb.751: ; in Loop: Header=BB6_753 Depth=2 s_sleep 1 s_cbranch_execnz .LBB6_753 s_branch .LBB6_755 .p2align 6 .LBB6_752: ; in Loop: Header=BB6_573 Depth=1 s_branch .LBB6_755 .LBB6_753: ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 v_mov_b32_e32 v6, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_750 ; %bb.754: ; in Loop: Header=BB6_753 Depth=2 global_load_b32 v6, v[4:5], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v6, 1, v6 s_branch .LBB6_750 .LBB6_755: ; in Loop: Header=BB6_573 Depth=1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB6_572 ; %bb.756: ; in Loop: Header=BB6_573 Depth=1 s_clause 0x2 global_load_b64 v[6:7], v29, s[34:35] offset:40 global_load_b64 v[10:11], v29, s[34:35] offset:24 glc global_load_b64 v[8:9], v29, s[34:35] s_waitcnt vmcnt(2) v_add_co_u32 v12, vcc_lo, v6, 1 v_add_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, v12, s4 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v13, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12 v_and_b32_e32 v7, v5, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v6, v4, v6 v_mul_hi_u32 v12, v6, 24 v_mul_lo_u32 v6, v6, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v8, vcc_lo, v8, v6 v_mov_b32_e32 v6, v10 v_mul_lo_u32 v7, v7, 24 v_add_nc_u32_e32 v7, v12, v7 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo v_mov_b32_e32 v7, v11 global_store_b64 v[8:9], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[6:7], v29, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[10:11] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_572 ; %bb.757: ; %.preheader.i.i.i201.preheader ; in Loop: Header=BB6_573 Depth=1 s_mov_b32 s0, 0 .LBB6_758: ; %.preheader.i.i.i201 ; Parent Loop BB6_573 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 global_store_b64 v[8:9], v[6:7], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v29, v[4:7], s[34:35] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7] v_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB6_758 s_branch .LBB6_572 .LBB6_759: ; %.loopexit s_clause 0x9 scratch_load_b32 v59, off, s33 scratch_load_b32 v58, off, s33 offset:4 scratch_load_b32 v57, off, s33 offset:8 scratch_load_b32 v56, off, s33 offset:12 scratch_load_b32 v45, off, s33 offset:16 scratch_load_b32 v44, off, s33 offset:20 scratch_load_b32 v43, off, s33 offset:24 scratch_load_b32 v42, off, s33 offset:28 scratch_load_b32 v41, off, s33 offset:32 scratch_load_b32 v40, off, s33 offset:36 v_readlane_b32 s30, v46, 20 v_readlane_b32 s31, v46, 21 v_readlane_b32 s53, v46, 19 v_readlane_b32 s52, v46, 18 v_readlane_b32 s51, v46, 17 v_readlane_b32 s50, v46, 16 v_readlane_b32 s49, v46, 15 v_readlane_b32 s48, v46, 14 v_readlane_b32 s47, v46, 13 v_readlane_b32 s46, v46, 12 v_readlane_b32 s45, v46, 11 v_readlane_b32 s44, v46, 10 v_readlane_b32 s43, v46, 9 v_readlane_b32 s42, v46, 8 v_readlane_b32 s41, v46, 7 v_readlane_b32 s40, v46, 6 v_readlane_b32 s39, v46, 5 v_readlane_b32 s38, v46, 4 v_readlane_b32 s37, v46, 3 v_readlane_b32 s36, v46, 2 v_readlane_b32 s35, v46, 1 v_readlane_b32 s34, v46, 0 v_readlane_b32 s0, v46, 22 s_or_saveexec_b32 s1, -1 scratch_load_b32 v46, off, s33 offset:40 ; 4-byte Folded Reload s_mov_b32 exec_lo, s1 s_addk_i32 s32, 0xffd0 s_mov_b32 s33, s0 s_waitcnt vmcnt(0) lgkmcnt(0) s_setpc_b64 s[30:31] .Lfunc_end6: .size _Z6unsafePmj, .Lfunc_end6-_Z6unsafePmj ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 33580 ; NumSgprs: 56 ; NumVgprs: 130 ; ScratchSize: 56 ; MemoryBound: 0 .text .protected _Z11test_kernelPmS_jPi ; -- Begin function _Z11test_kernelPmS_jPi .globl _Z11test_kernelPmS_jPi .p2align 8 .type _Z11test_kernelPmS_jPi,@function _Z11test_kernelPmS_jPi: ; @_Z11test_kernelPmS_jPi ; %bb.0: s_mov_b64 s[20:21], s[0:1] s_clause 0x1 s_load_b64 s[0:1], s[2:3], 0x18 s_load_b32 s57, s[2:3], 0x2c v_mov_b32_e32 v40, v0 v_mov_b32_e32 v0, 0 s_mov_b32 s22, s15 s_mov_b64 s[54:55], s[2:3] s_mov_b32 s23, s14 s_mov_b32 s56, s13 s_mov_b64 s[18:19], s[4:5] s_mov_b32 s24, 0 s_mov_b32 s32, 0 s_waitcnt lgkmcnt(0) global_load_b32 v0, v0, s[0:1] s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, 0, v0 s_cbranch_vccnz .LBB7_3 ; %bb.1: s_add_u32 s8, s54, 32 s_addc_u32 s9, s55, 0 s_getpc_b64 s[0:1] s_add_u32 s0, s0, _Z6secretv@rel32@lo+4 s_addc_u32 s1, s1, _Z6secretv@rel32@hi+12 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_swappc_b64 s[30:31], s[0:1] s_mov_b32 s0, 0x99999999 s_mov_b32 s1, s0 s_and_not1_b32 vcc_lo, exec_lo, s24 s_cbranch_vccnz .LBB7_4 .LBB7_2: s_clause 0x1 s_load_b64 s[0:1], s[54:55], 0x8 s_load_b32 s6, s[54:55], 0x10 v_mov_b32_e32 v31, v40 s_add_u32 s8, s54, 32 s_addc_u32 s9, s55, 0 s_mov_b64 s[4:5], s[20:21] s_mov_b64 s[10:11], s[18:19] s_mov_b32 s12, s56 s_mov_b32 s13, s23 s_mov_b32 s14, s22 s_getpc_b64 s[2:3] s_add_u32 s2, s2, _Z6unsafePmj@rel32@lo+4 s_addc_u32 s3, s3, _Z6unsafePmj@rel32@hi+12 s_waitcnt lgkmcnt(0) v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 v_mov_b32_e32 v2, s6 s_swappc_b64 s[30:31], s[2:3] s_branch .LBB7_5 .LBB7_3: ; implicit-def: $sgpr0_sgpr1 s_branch .LBB7_2 .LBB7_4: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 .LBB7_5: v_and_b32_e32 v2, 0x3ff, v40 s_and_b32 s2, 0xffff, s57 s_load_b64 s[0:1], s[54:55], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[3:4], null, s56, s2, v[2:3] v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 3, v[3:4] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s0, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo global_store_b64 v[2:3], v[0:1], off s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11test_kernelPmS_jPi .amdhsa_group_segment_fixed_size 8 .amdhsa_private_segment_fixed_size 56 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 13 .amdhsa_user_sgpr_dispatch_ptr 1 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 1 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 1 .amdhsa_enable_private_segment 1 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 1 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 130 .amdhsa_next_free_sgpr 58 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end7: .size _Z11test_kernelPmS_jPi, .Lfunc_end7-_Z11test_kernelPmS_jPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 332 ; NumSgprs: 60 ; NumVgprs: 130 ; ScratchSize: 56 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 8 bytes/workgroup (compile time only) ; SGPRBlocks: 7 ; VGPRBlocks: 16 ; NumSGPRsForWavesPerEU: 60 ; NumVGPRsForWavesPerEU: 130 ; Occupancy: 10 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1 ; COMPUTE_PGM_RSRC2:USER_SGPR: 13 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2 .text .protected _Z12test_kernel2PmS_jPi ; -- Begin function _Z12test_kernel2PmS_jPi .globl _Z12test_kernel2PmS_jPi .p2align 8 .type _Z12test_kernel2PmS_jPi,@function _Z12test_kernel2PmS_jPi: ; @_Z12test_kernel2PmS_jPi ; %bb.0: s_mov_b64 s[20:21], s[0:1] s_clause 0x1 s_load_b64 s[0:1], s[2:3], 0x18 s_load_b32 s57, s[2:3], 0x2c v_mov_b32_e32 v40, v0 v_mov_b32_e32 v0, 0 s_mov_b32 s22, s15 s_mov_b64 s[54:55], s[2:3] s_mov_b32 s23, s14 s_mov_b32 s56, s13 s_mov_b64 s[18:19], s[4:5] s_mov_b32 s24, 0 s_mov_b32 s32, 0 s_waitcnt lgkmcnt(0) global_load_b32 v0, v0, s[0:1] s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, 0, v0 s_cbranch_vccnz .LBB8_3 ; %bb.1: s_add_u32 s8, s54, 32 s_addc_u32 s9, s55, 0 s_getpc_b64 s[0:1] s_add_u32 s0, s0, _Z6secretv@rel32@lo+4 s_addc_u32 s1, s1, _Z6secretv@rel32@hi+12 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_swappc_b64 s[30:31], s[0:1] s_mov_b32 s0, 0x99999999 s_mov_b32 s1, s0 s_and_not1_b32 vcc_lo, exec_lo, s24 s_cbranch_vccnz .LBB8_4 .LBB8_2: s_clause 0x1 s_load_b64 s[0:1], s[54:55], 0x8 s_load_b32 s6, s[54:55], 0x10 v_mov_b32_e32 v31, v40 s_add_u32 s8, s54, 32 s_addc_u32 s9, s55, 0 s_mov_b64 s[4:5], s[20:21] s_mov_b64 s[10:11], s[18:19] s_mov_b32 s12, s56 s_mov_b32 s13, s23 s_mov_b32 s14, s22 s_getpc_b64 s[2:3] s_add_u32 s2, s2, _Z6unsafePmj@rel32@lo+4 s_addc_u32 s3, s3, _Z6unsafePmj@rel32@hi+12 s_waitcnt lgkmcnt(0) v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 v_mov_b32_e32 v2, s6 s_swappc_b64 s[30:31], s[2:3] s_branch .LBB8_5 .LBB8_3: ; implicit-def: $sgpr0_sgpr1 s_branch .LBB8_2 .LBB8_4: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 .LBB8_5: v_and_b32_e32 v2, 0x3ff, v40 s_and_b32 s2, 0xffff, s57 s_load_b64 s[0:1], s[54:55], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[3:4], null, s56, s2, v[2:3] v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 3, v[3:4] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s0, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo global_store_b64 v[2:3], v[0:1], off s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12test_kernel2PmS_jPi .amdhsa_group_segment_fixed_size 8 .amdhsa_private_segment_fixed_size 56 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 13 .amdhsa_user_sgpr_dispatch_ptr 1 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 1 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 1 .amdhsa_enable_private_segment 1 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 1 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 130 .amdhsa_next_free_sgpr 58 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end8: .size _Z12test_kernel2PmS_jPi, .Lfunc_end8-_Z12test_kernel2PmS_jPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 332 ; NumSgprs: 60 ; NumVgprs: 130 ; ScratchSize: 56 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 8 bytes/workgroup (compile time only) ; SGPRBlocks: 7 ; VGPRBlocks: 16 ; NumSGPRsForWavesPerEU: 60 ; NumVGPRsForWavesPerEU: 130 ; Occupancy: 10 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1 ; COMPUTE_PGM_RSRC2:USER_SGPR: 13 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type .str,@object ; @.str .section .rodata.str1.1,"aMS",@progbits,1 .str: .asciz "Hello Admin!\n" .size .str, 14 .type .str.1,@object ; @.str.1 .str.1: .asciz "blockDim %d, buf %p\n" .size .str.1, 21 .type .str.2,@object ; @.str.2 .str.2: .asciz "blockDim %d, secret %p\n" .size .str.2, 24 .type .str.3,@object ; @.str.3 .str.3: .asciz "blockDim %d, objD %p\n" .size .str.3, 22 .type .str.4,@object ; @.str.4 .str.4: .asciz "blockDim %d %lx\n" .size .str.4, 17 .hidden _ZTV1D ; @_ZTV1D .type _ZTV1D,@object .section .data.rel.ro,"aw",@progbits .globl _ZTV1D .p2align 3, 0x0 _ZTV1D: .quad 0 .quad 0 .quad _ZN1D2f1Ej .quad _ZN1D2f2Ej .quad _ZN1D2f3Ej .quad _ZN1D2f4Ej .size _ZTV1D, 48 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .type __unnamed_1,@object ; @0 .section .rodata,"a",@progbits .p2align 2, 0x0 __unnamed_1: .long 130054 ; 0x1fc06 .long 129546 ; 0x1fa0a .long 110114 ; 0x1ae22 .long 16288 ; 0x3fa0 .long 6 ; 0x6 .long 256 ; 0x100 .long 0 ; 0x0 .long 4195 ; 0x1063 .long 86927 ; 0x1538f .long 86758 ; 0x152e6 .long 73744 ; 0x12010 .long 10904 ; 0x2a98 .long 399 ; 0x18f .long 512 ; 0x200 .long 0 ; 0x0 .long 2804 ; 0xaf4 .long 65280 ; 0xff00 .long 64770 ; 0xfd02 .long 55054 ; 0xd70e .long 8192 ; 0x2000 .long 0 ; 0x0 .long 128 ; 0x80 .long 0 ; 0x0 .long 2107 ; 0x83b .long 43576 ; 0xaa38 .long 43406 ; 0xa98e .long 36895 ; 0x901f .long 5504 ; 0x1580 .long 56 ; 0x38 .long 256 ; 0x100 .long 0 ; 0x0 .long 1405 ; 0x57d .long 32703 ; 0x7fbf .long 32193 ; 0x7dc1 .long 27364 ; 0x6ae4 .long 4160 ; 0x1040 .long 63 ; 0x3f .long 64 ; 0x40 .long 0 ; 0x0 .long 1054 ; 0x41e .long 21816 ; 0x5538 .long 21646 ; 0x548e .long 18399 ; 0x47df .long 2816 ; 0xb00 .long 56 ; 0x38 .long 128 ; 0x80 .long 0 ; 0x0 .long 703 ; 0x2bf .long 16367 ; 0x3fef .long 15856 ; 0x3df0 .long 13477 ; 0x34a5 .long 2176 ; 0x880 .long 15 ; 0xf .long 32 ; 0x20 .long 32768 ; 0x8000 .long 527 ; 0x20f .long 10915 ; 0x2aa3 .long 10745 ; 0x29f9 .long 9133 ; 0x23ad .long 1472 ; 0x5c0 .long 35 ; 0x23 .long 64 ; 0x40 .long 0 ; 0x0 .long 352 ; 0x160 .long 8187 ; 0x1ffb .long 7676 ; 0x1dfc .long 6524 ; 0x197c .long 1280 ; 0x500 .long 11 ; 0xb .long 16 ; 0x10 .long 134219776 ; 0x8000800 .long 265 ; 0x109 .long 5459 ; 0x1553 .long 5289 ; 0x14a9 .long 4495 ; 0x118f .long 896 ; 0x380 .long 19 ; 0x13 .long 32 ; 0x20 .long 524288 ; 0x80000 .long 176 ; 0xb0 .long 4094 ; 0xffe .long 3583 ; 0xdff .long 3045 ; 0xbe5 .long 1024 ; 0x400 .long 6 ; 0x6 .long 8 ; 0x8 .long 1077952576 ; 0x40404040 .long 133 ; 0x85 .long 2730 ; 0xaaa .long 2560 ; 0xa00 .long 2176 ; 0x880 .long 512 ; 0x200 .long 10 ; 0xa .long 16 ; 0x10 .long 67109888 ; 0x4000400 .long 89 ; 0x59 .long 2047 ; 0x7ff .long 1536 ; 0x600 .long 1305 ; 0x519 .long 1024 ; 0x400 .long 3 ; 0x3 .long 4 ; 0x4 .long 2290649224 ; 0x88888888 .long 66 ; 0x42 .long 1365 ; 0x555 .long 1195 ; 0x4ab .long 1015 ; 0x3f7 .long 512 ; 0x200 .long 5 ; 0x5 .long 8 ; 0x8 .long 538976288 ; 0x20202020 .long 44 ; 0x2c .long 1023 ; 0x3ff .long 512 ; 0x200 .long 435 ; 0x1b3 .long 2048 ; 0x800 .long 1 ; 0x1 .long 2 ; 0x2 .long 2863311530 ; 0xaaaaaaaa .long 34 ; 0x22 .long 682 ; 0x2aa .long 512 ; 0x200 .long 435 ; 0x1b3 .long 2048 ; 0x800 .long 2 ; 0x2 .long 4 ; 0x4 .long 1145324612 ; 0x44444444 .long 35 ; 0x23 .size __unnamed_1, 512 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z6secretv .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims - .offset: 112 .size: 8 .value_kind: hidden_hostcall_buffer - .offset: 120 .size: 8 .value_kind: hidden_multigrid_sync_arg - .offset: 128 .size: 8 .value_kind: hidden_heap_v1 - .offset: 136 .size: 8 .value_kind: hidden_default_queue - .offset: 232 .size: 8 .value_kind: hidden_queue_ptr .group_segment_fixed_size: 8 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11test_kernelPmS_jPi .private_segment_fixed_size: 56 .sgpr_count: 60 .sgpr_spill_count: 0 .symbol: _Z11test_kernelPmS_jPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: true .vgpr_count: 130 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims - .offset: 112 .size: 8 .value_kind: hidden_hostcall_buffer - .offset: 120 .size: 8 .value_kind: hidden_multigrid_sync_arg - .offset: 128 .size: 8 .value_kind: hidden_heap_v1 - .offset: 136 .size: 8 .value_kind: hidden_default_queue - .offset: 232 .size: 8 .value_kind: hidden_queue_ptr .group_segment_fixed_size: 8 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12test_kernel2PmS_jPi .private_segment_fixed_size: 56 .sgpr_count: 60 .sgpr_spill_count: 0 .symbol: _Z12test_kernel2PmS_jPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: true .vgpr_count: 130 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "4836af2626a3d02cbee1b44129c8c87ce99027fe.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z26__device_stub__test_kernelPmS_jPi # -- Begin function _Z26__device_stub__test_kernelPmS_jPi .p2align 4, 0x90 .type _Z26__device_stub__test_kernelPmS_jPi,@function _Z26__device_stub__test_kernelPmS_jPi: # @_Z26__device_stub__test_kernelPmS_jPi .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 4(%rsp) movq %rcx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) leaq 56(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z11test_kernelPmS_jPi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z26__device_stub__test_kernelPmS_jPi, .Lfunc_end0-_Z26__device_stub__test_kernelPmS_jPi .cfi_endproc # -- End function .globl _Z27__device_stub__test_kernel2PmS_jPi # -- Begin function _Z27__device_stub__test_kernel2PmS_jPi .p2align 4, 0x90 .type _Z27__device_stub__test_kernel2PmS_jPi,@function _Z27__device_stub__test_kernel2PmS_jPi: # @_Z27__device_stub__test_kernel2PmS_jPi .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 4(%rsp) movq %rcx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) leaq 56(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z12test_kernel2PmS_jPi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end1: .size _Z27__device_stub__test_kernel2PmS_jPi, .Lfunc_end1-_Z27__device_stub__test_kernel2PmS_jPi .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $1776, %rsp # imm = 0x6F0 .cfi_def_cfa_offset 1792 .cfi_offset %rbx, -16 movl $0, 124(%rsp) xorl %eax, %eax .p2align 4, 0x90 .LBB2_1: # =>This Inner Loop Header: Depth=1 movq $20, 976(%rsp,%rax,8) incq %rax cmpq $4, %rax jne .LBB2_1 # %bb.2: # %.preheader51.preheader movl $4, %eax movabsq $21514942752, %rcx # imm = 0x50263F920 .p2align 4, 0x90 .LBB2_3: # %.preheader51 # =>This Inner Loop Header: Depth=1 movq %rcx, 976(%rsp,%rax,8) incq %rax cmpq $60, %rax jne .LBB2_3 # %bb.4: # %.preheader50.preheader xorl %eax, %eax .p2align 4, 0x90 .LBB2_5: # %.preheader50 # =>This Inner Loop Header: Depth=1 movq $20, 176(%rsp,%rax,8) incq %rax cmpq $4, %rax jne .LBB2_5 # %bb.6: # %.preheader49.preheader movl $4, %eax .p2align 4, 0x90 .LBB2_7: # %.preheader49 # =>This Inner Loop Header: Depth=1 movq $69905, 176(%rsp,%rax,8) # imm = 0x11111 incq %rax cmpq $40, %rax jne .LBB2_7 # %bb.8: movabsq $4294967297, %rbx # imm = 0x100000001 leaq 56(%rsp), %rdi movl $16, %esi callq hipMalloc movl $.L.str.1, %esi movl $126, %edi movl %eax, %edx callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t leaq 48(%rsp), %rdi movl $16, %esi callq hipMalloc movl $.L.str.2, %esi movl $127, %edi movl %eax, %edx callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t leaq 40(%rsp), %rdi movl $800, %esi # imm = 0x320 callq hipMalloc movl $.L.str.3, %esi movl $128, %edi movl %eax, %edx callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t leaq 168(%rsp), %rdi movl $800, %esi # imm = 0x320 callq hipMalloc movl $.L.str.4, %esi movl $129, %edi movl %eax, %edx callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t leaq 8(%rsp), %rdi movl $4, %esi callq hipMalloc movl $.L.str.5, %esi movl $130, %edi movl %eax, %edx callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t movq 40(%rsp), %rdi leaq 976(%rsp), %rsi movl $800, %edx # imm = 0x320 movl $1, %ecx callq hipMemcpy movl $.L.str.6, %esi movl $131, %edi movl %eax, %edx callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t movq 168(%rsp), %rdi leaq 176(%rsp), %rsi movl $800, %edx # imm = 0x320 movl $1, %ecx callq hipMemcpy movl $.L.str.7, %esi movl $132, %edi movl %eax, %edx callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t movq 8(%rsp), %rdi leaq 124(%rsp), %rsi movl $4, %edx movl $1, %ecx callq hipMemcpy movl $.L.str.8, %esi movl $133, %edi movl %eax, %edx callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t leaq 1(%rbx), %rdx movq %rbx, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_10 # %bb.9: movq 56(%rsp), %rax movq 40(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 112(%rsp) movq %rcx, 104(%rsp) movl $8, 4(%rsp) movq %rdx, 96(%rsp) leaq 112(%rsp), %rax movq %rax, 128(%rsp) leaq 104(%rsp), %rax movq %rax, 136(%rsp) leaq 4(%rsp), %rax movq %rax, 144(%rsp) leaq 96(%rsp), %rax movq %rax, 152(%rsp) leaq 16(%rsp), %rdi leaq 80(%rsp), %rsi leaq 72(%rsp), %rdx leaq 64(%rsp), %rcx callq __hipPopCallConfiguration movq 16(%rsp), %rsi movl 24(%rsp), %edx movq 80(%rsp), %rcx movl 88(%rsp), %r8d leaq 128(%rsp), %r9 movl $_Z11test_kernelPmS_jPi, %edi pushq 64(%rsp) .cfi_adjust_cfa_offset 8 pushq 80(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_10: movq %rbx, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_12 # %bb.11: movq 48(%rsp), %rax movq 168(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 112(%rsp) movq %rcx, 104(%rsp) movl $8, 4(%rsp) movq %rdx, 96(%rsp) leaq 112(%rsp), %rax movq %rax, 128(%rsp) leaq 104(%rsp), %rax movq %rax, 136(%rsp) leaq 4(%rsp), %rax movq %rax, 144(%rsp) leaq 96(%rsp), %rax movq %rax, 152(%rsp) leaq 16(%rsp), %rdi leaq 80(%rsp), %rsi leaq 72(%rsp), %rdx leaq 64(%rsp), %rcx callq __hipPopCallConfiguration movq 16(%rsp), %rsi movl 24(%rsp), %edx movq 80(%rsp), %rcx movl 88(%rsp), %r8d leaq 128(%rsp), %r9 movl $_Z12test_kernel2PmS_jPi, %edi pushq 64(%rsp) .cfi_adjust_cfa_offset 8 pushq 80(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_12: movq 56(%rsp), %rsi leaq 128(%rsp), %rdi movl $16, %edx movl $2, %ecx callq hipMemcpy movl $.L.str.9, %esi movl $141, %edi movl %eax, %edx callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t movq 48(%rsp), %rsi leaq 16(%rsp), %rdi movl $16, %edx movl $2, %ecx callq hipMemcpy movl $.L.str.10, %esi movl $142, %edi movl %eax, %edx callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t xorl %ebx, %ebx .p2align 4, 0x90 .LBB2_13: # =>This Inner Loop Header: Depth=1 movq 128(%rsp,%rbx,8), %rdx movl $.L.str.11, %edi movl %ebx, %esi xorl %eax, %eax callq printf incq %rbx cmpq $1, %rbx je .LBB2_13 # %bb.14: # %.preheader.preheader xorl %ebx, %ebx .p2align 4, 0x90 .LBB2_15: # %.preheader # =>This Inner Loop Header: Depth=1 movq 16(%rsp,%rbx,8), %rdx movl $.L.str.11, %edi movl %ebx, %esi xorl %eax, %eax callq printf incq %rbx cmpq $1, %rbx je .LBB2_15 # %bb.16: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB2_21 # %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB2_19 # %bb.18: movzbl 67(%rbx), %eax jmp .LBB2_20 .LBB2_19: movq %rbx, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) .LBB2_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 56(%rsp), %rdi callq hipFree movq 48(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi callq hipFree xorl %eax, %eax addq $1776, %rsp # imm = 0x6F0 .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .LBB2_21: .cfi_def_cfa_offset 1792 callq _ZSt16__throw_bad_castv .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t .type _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t,@function _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t: # @_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t .cfi_startproc # %bb.0: testl %edx, %edx jne .LBB3_2 # %bb.1: retq .LBB3_2: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movl %edi, %ebx movl $_ZSt4cerr, %edi movl %edx, %ebp callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.12, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %r14 movl %ebp, %edi callq hipGetErrorString movq %r14, %rdi movq %rax, %rsi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.13, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movl %ebp, %esi callq _ZNSolsEi movl $.L.str.14, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movl $.L.str.15, %esi movq %rax, %rdi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc movq %rax, %rdi movl %ebx, %esi callq _ZNSolsEj movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ movl $1, %edi callq exit .Lfunc_end3: .size _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t, .Lfunc_end3-_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11test_kernelPmS_jPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12test_kernel2PmS_jPi, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z11test_kernelPmS_jPi,@object # @_Z11test_kernelPmS_jPi .section .rodata,"a",@progbits .globl _Z11test_kernelPmS_jPi .p2align 3, 0x0 _Z11test_kernelPmS_jPi: .quad _Z26__device_stub__test_kernelPmS_jPi .size _Z11test_kernelPmS_jPi, 8 .type _Z12test_kernel2PmS_jPi,@object # @_Z12test_kernel2PmS_jPi .globl _Z12test_kernel2PmS_jPi .p2align 3, 0x0 _Z12test_kernel2PmS_jPi: .quad _Z27__device_stub__test_kernel2PmS_jPi .size _Z12test_kernel2PmS_jPi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "/home/ubuntu/Datasets/Stack_v2_cuda-hip-as/4836af2626a3d02cbee1b44129c8c87ce99027fe.hip" .size .L.str, 88 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "hipMalloc((void**)&dev_hashes,N*sizeof(unsigned long))" .size .L.str.1, 55 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "hipMalloc((void**)&dev_hashes2,N*sizeof(unsigned long))" .size .L.str.2, 56 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "hipMalloc((void**)&dev_input,100*sizeof(unsigned long))" .size .L.str.3, 56 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "hipMalloc((void**)&dev_input2,100*sizeof(unsigned long))" .size .L.str.4, 57 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "hipMalloc((void**)&dev_admin,sizeof(int))" .size .L.str.5, 42 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "hipMemcpy(dev_input,input,100*sizeof(unsigned long),hipMemcpyHostToDevice)" .size .L.str.6, 75 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "hipMemcpy(dev_input2,input2,100*sizeof(unsigned long),hipMemcpyHostToDevice)" .size .L.str.7, 77 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "hipMemcpy(dev_admin,&admin,sizeof(int),hipMemcpyHostToDevice)" .size .L.str.8, 62 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "hipMemcpy(&hashes,dev_hashes,N*sizeof(unsigned long),hipMemcpyDeviceToHost)" .size .L.str.9, 76 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "hipMemcpy(&hashes2,dev_hashes2,N*sizeof(unsigned long),hipMemcpyDeviceToHost)" .size .L.str.10, 78 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "%d, %lx\n" .size .L.str.11, 10 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz " returned " .size .L.str.12, 11 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz "(" .size .L.str.13, 2 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz ") at " .size .L.str.14, 6 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz ":" .size .L.str.15, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z11test_kernelPmS_jPi" .size .L__unnamed_1, 23 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z12test_kernel2PmS_jPi" .size .L__unnamed_2, 24 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub__test_kernelPmS_jPi .addrsig_sym _Z27__device_stub__test_kernel2PmS_jPi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z11test_kernelPmS_jPi .addrsig_sym _Z12test_kernel2PmS_jPi .addrsig_sym _ZSt4cout .addrsig_sym _ZSt4cerr .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z3addPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R6, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R6, R6, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; @P0 EXIT ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; LDG.E R4, [R4.64] ; LDG.E R3, [R2.64] ; IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; IADD3 R9, R4, R3, RZ ; STG.E [R6.64], R9 ; EXIT ; BRA 0x100; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0001fe83_00000000-6_2a91744acc88ef1fda2368c727072d0086c7a323.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i .type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function _Z27__device_stub__Z3addPiS_S_iPiS_S_i: .LFB2082: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z3addPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i .globl _Z3addPiS_S_i .type _Z3addPiS_S_i, @function _Z3addPiS_S_i: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z3addPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z3addPiS_S_i, .-_Z3addPiS_S_i .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "Usage: %s vector_size block_size\n" .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Initializing input arrays.\n" .LC2: .string "Running sequential job.\n" .section .rodata.str1.8 .align 8 .LC3: .string "\tSequential Job Time: %.2f ms\n" .section .rodata.str1.1 .LC4: .string "Running parallel job.\n" .LC5: .string "\tParallel Job Time: %.2f ms\n" .section .rodata.str1.8 .align 8 .LC6: .string "Error starting element %d, %d != %d\n" .align 8 .LC7: .string "Correct result. No errors were found.\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $120, %rsp .cfi_def_cfa_offset 176 movq %rsi, %rbx movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax cmpl $3, %edi je .L12 movq (%rsi), %rdx leaq .LC0(%rip), %rsi movl $2, %edi call __printf_chk@PLT movl $1, %eax .L11: movq 104(%rsp), %rdx subq %fs:40, %rdx jne .L32 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L12: .cfi_restore_state movq 8(%rsi), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %r15 movq %rax, 8(%rsp) movl %eax, 28(%rsp) movq 16(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %rsi movq %rax, 16(%rsp) movl %r15d, %eax subl $1, %eax cltd idivl %esi addl $1, %eax movl %eax, 24(%rsp) movl $0, %edi call cudaSetDevice@PLT leaq 40(%rsp), %rdi call cudaEventCreate@PLT leaq 48(%rsp), %rdi call cudaEventCreate@PLT movslq %r15d, %rax movabsq $2305843009213693950, %rdx cmpq %rax, %rdx jb .L14 leaq 0(,%rax,4), %rbx movq %rbx, (%rsp) movq %rbx, %rdi call _Znam@PLT movq %rax, %r12 movq %rbx, %rdi call _Znam@PLT movq %rax, %r13 movq %rbx, %rdi call _Znam@PLT movq %rax, %rbp movq %rbx, %rdi call _Znam@PLT movq %rax, %r14 leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT testl %r15d, %r15d jle .L33 movq 8(%rsp), %rax leal -1(%rax), %r15d movl $0, %ebx .L18: call rand@PLT movslq %eax, %rdx imulq $1717986919, %rdx, %rdx sarq $34, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx leal (%rdx,%rdx,4), %edx addl %edx, %edx subl %edx, %eax movl %eax, (%r12,%rbx,4) call rand@PLT movslq %eax, %rdx imulq $1717986919, %rdx, %rdx sarq $34, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx leal (%rdx,%rdx,4), %edx addl %edx, %edx subl %edx, %eax movl %eax, 0(%r13,%rbx,4) movq %rbx, %rax addq $1, %rbx cmpq %r15, %rax jne .L18 leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %esi movq 40(%rsp), %rdi call cudaEventRecord@PLT movl $0, %eax .L19: movl 0(%r13,%rax,4), %edx addl (%r12,%rax,4), %edx movl %edx, 0(%rbp,%rax,4) movq %rax, %rdx addq $1, %rax cmpq %r15, %rdx jne .L19 .L25: movl $0, %esi movq 48(%rsp), %rdi call cudaEventRecord@PLT movq 48(%rsp), %rdi call cudaEventSynchronize@PLT leaq 36(%rsp), %rdi movq 48(%rsp), %rdx movq 40(%rsp), %rsi call cudaEventElapsedTime@PLT pxor %xmm0, %xmm0 cvtss2sd 36(%rsp), %xmm0 leaq .LC3(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT leaq 56(%rsp), %rdi movq (%rsp), %rbx movq %rbx, %rsi call cudaMalloc@PLT leaq 64(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 72(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movl $1, %ecx movq %rbx, %rdx movq %r12, %rsi movq 56(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq %r13, %rsi movq 64(%rsp), %rdi call cudaMemcpy@PLT leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %esi movq 40(%rsp), %rdi call cudaEventRecord@PLT movl 16(%rsp), %eax movl %eax, 92(%rsp) movl $1, 96(%rsp) movl 24(%rsp), %eax movl %eax, 80(%rsp) movl $1, 84(%rsp) movl $0, %r9d movl $0, %r8d movq 92(%rsp), %rdx movl $1, %ecx movq 80(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L34 .L20: movl $0, %esi movq 48(%rsp), %rdi call cudaEventRecord@PLT movq 48(%rsp), %rdi call cudaEventSynchronize@PLT leaq 36(%rsp), %rdi movq 48(%rsp), %rdx movq 40(%rsp), %rsi call cudaEventElapsedTime@PLT pxor %xmm0, %xmm0 cvtss2sd 36(%rsp), %xmm0 leaq .LC5(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl $2, %ecx movq (%rsp), %rdx movq 72(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT movq 8(%rsp), %rax testl %eax, %eax jle .L21 leal -1(%rax), %esi movl $0, %edx jmp .L24 .L14: movq 104(%rsp), %rax subq %fs:40, %rax je .L17 call __stack_chk_fail@PLT .L17: call __cxa_throw_bad_array_new_length@PLT .L34: movl 28(%rsp), %ecx movq 72(%rsp), %rdx movq 64(%rsp), %rsi movq 56(%rsp), %rdi call _Z27__device_stub__Z3addPiS_S_iPiS_S_i jmp .L20 .L27: movq %rax, %rdx .L24: movl 0(%rbp,%rdx,4), %r8d movl (%r14,%rdx,4), %ecx cmpl %ecx, %r8d jne .L35 leaq 1(%rdx), %rax cmpq %rsi, %rdx jne .L27 .L21: leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L23 .L35: leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L23: movq %r12, %rdi call free@PLT movq %r13, %rdi call free@PLT movq %rbp, %rdi call free@PLT movq %r14, %rdi call free@PLT movq 56(%rsp), %rdi call cudaFree@PLT movq 64(%rsp), %rdi call cudaFree@PLT movq 72(%rsp), %rdi call cudaFree@PLT movl $0, %eax jmp .L11 .L33: leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %esi movq 40(%rsp), %rdi call cudaEventRecord@PLT jmp .L25 .L32: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC8: .string "_Z3addPiS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC8(%rip), %rdx movq %rdx, %rcx leaq _Z3addPiS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z3addPiS_S_i ; -- Begin function _Z3addPiS_S_i .globl _Z3addPiS_S_i .p2align 8 .type _Z3addPiS_S_i,@function _Z3addPiS_S_i: ; @_Z3addPiS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_add_nc_u32_e32 v2, v3, v2 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z3addPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 180 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z3addPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z3addPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "2a91744acc88ef1fda2368c727072d0086c7a323.hip" .globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i .p2align 4, 0x90 .type _Z18__device_stub__addPiS_S_i,@function _Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3addPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $200, %rsp .cfi_def_cfa_offset 256 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 cmpl $3, %edi jne .LBB1_1 # %bb.2: movq 8(%rsi), %rdi movq %rsi, %rbx xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r14 movq 16(%rbx), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %rcx leal -1(%r14), %eax cltd movq %rcx, 72(%rsp) # 8-byte Spill idivl %ecx movl %eax, 20(%rsp) # 4-byte Spill xorl %edi, %edi callq hipSetDevice leaq 24(%rsp), %rdi callq hipEventCreate leaq 8(%rsp), %rdi callq hipEventCreate movq %r14, 64(%rsp) # 8-byte Spill movslq %r14d, %rbx leaq (,%rbx,4), %rax testl %ebx, %ebx movq $-1, %r13 movq %rax, 80(%rsp) # 8-byte Spill cmovnsq %rax, %r13 movq %r13, %rdi callq _Znam movq %rax, %r14 movq %r13, %rdi callq _Znam movq %rax, %r15 movq %r13, %rdi callq _Znam movq %rax, %r12 movq %r13, %rdi callq _Znam movq %rax, %r13 movl $.Lstr, %edi callq puts@PLT testl %ebx, %ebx jle .LBB1_5 # %bb.3: # %.lr.ph.preheader movl 64(%rsp), %ebx # 4-byte Reload xorl %ebp, %ebp .p2align 4, 0x90 .LBB1_4: # %.lr.ph # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx subl %ecx, %eax movl %eax, (%r14,%rbp,4) callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx subl %ecx, %eax movl %eax, (%r15,%rbp,4) incq %rbp cmpq %rbp, %rbx jne .LBB1_4 .LBB1_5: # %._crit_edge incl 20(%rsp) # 4-byte Folded Spill movl $.Lstr.1, %edi callq puts@PLT movq 24(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 64(%rsp), %rbx # 8-byte Reload testl %ebx, %ebx jle .LBB1_8 # %bb.6: # %.lr.ph82.preheader movl %ebx, %eax xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_7: # %.lr.ph82 # =>This Inner Loop Header: Depth=1 movl (%r15,%rcx,4), %edx addl (%r14,%rcx,4), %edx movl %edx, (%r12,%rcx,4) incq %rcx cmpq %rcx, %rax jne .LBB1_7 .LBB1_8: # %._crit_edge83 movq 8(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 8(%rsp), %rdi callq hipEventSynchronize movq 24(%rsp), %rsi movq 8(%rsp), %rdx leaq 4(%rsp), %rdi callq hipEventElapsedTime movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.3, %edi movb $1, %al callq printf leaq 48(%rsp), %rdi movq 80(%rsp), %rbp # 8-byte Reload movq %rbp, %rsi callq hipMalloc leaq 40(%rsp), %rdi movq %rbp, %rsi callq hipMalloc leaq 32(%rsp), %rdi movq %rbp, %rsi callq hipMalloc movq 48(%rsp), %rdi movq %r14, %rsi movq %rbp, %rdx movl $1, %ecx callq hipMemcpy movq 40(%rsp), %rdi movq %r15, %rsi movq %rbp, %rdx movl $1, %ecx callq hipMemcpy movl $.Lstr.2, %edi callq puts@PLT movq 24(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movl 20(%rsp), %edi # 4-byte Reload movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi movl 72(%rsp), %edx # 4-byte Reload orq %rax, %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_10 # %bb.9: movq 48(%rsp), %rax movq 40(%rsp), %rcx movq 32(%rsp), %rdx movq %rax, 152(%rsp) movq %rcx, 144(%rsp) movq %rdx, 136(%rsp) movl %ebx, 60(%rsp) leaq 152(%rsp), %rax movq %rax, 160(%rsp) leaq 144(%rsp), %rax movq %rax, 168(%rsp) leaq 136(%rsp), %rax movq %rax, 176(%rsp) leaq 60(%rsp), %rax movq %rax, 184(%rsp) leaq 120(%rsp), %rdi leaq 104(%rsp), %rsi leaq 96(%rsp), %rdx leaq 88(%rsp), %rcx callq __hipPopCallConfiguration movq 120(%rsp), %rsi movl 128(%rsp), %edx movq 104(%rsp), %rcx movl 112(%rsp), %r8d leaq 160(%rsp), %r9 movl $_Z3addPiS_S_i, %edi pushq 88(%rsp) .cfi_adjust_cfa_offset 8 pushq 104(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_10: movq 8(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 8(%rsp), %rdi callq hipEventSynchronize movq 24(%rsp), %rsi movq 8(%rsp), %rdx leaq 4(%rsp), %rdi callq hipEventElapsedTime movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.5, %edi movb $1, %al callq printf movq 32(%rsp), %rsi movq %r13, %rdi movq %rbp, %rdx movl $2, %ecx callq hipMemcpy testl %ebx, %ebx jle .LBB1_15 # %bb.11: # %.lr.ph87.preheader movl %ebx, %eax xorl %esi, %esi .p2align 4, 0x90 .LBB1_12: # %.lr.ph87 # =>This Inner Loop Header: Depth=1 movl (%r12,%rsi,4), %ecx movl (%r13,%rsi,4), %edx cmpl %edx, %ecx jne .LBB1_13 # %bb.14: # %.critedge # in Loop: Header=BB1_12 Depth=1 incq %rsi cmpq %rsi, %rax jne .LBB1_12 .LBB1_15: # %.critedge73 movl $.Lstr.3, %edi callq puts@PLT jmp .LBB1_16 .LBB1_1: movq (%rsi), %rsi movl $.L.str, %edi xorl %eax, %eax callq printf movl $1, %eax jmp .LBB1_17 .LBB1_13: movl $.L.str.6, %edi # kill: def $esi killed $esi killed $rsi xorl %eax, %eax callq printf .LBB1_16: movq %r14, %rdi callq free movq %r15, %rdi callq free movq %r12, %rdi callq free movq %r13, %rdi callq free movq 48(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree xorl %eax, %eax .LBB1_17: addq $200, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3addPiS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i .section .rodata,"a",@progbits .globl _Z3addPiS_S_i .p2align 3, 0x0 _Z3addPiS_S_i: .quad _Z18__device_stub__addPiS_S_i .size _Z3addPiS_S_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Usage: %s vector_size block_size\n" .size .L.str, 34 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "\tSequential Job Time: %.2f ms\n" .size .L.str.3, 31 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "\tParallel Job Time: %.2f ms\n" .size .L.str.5, 29 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Error starting element %d, %d != %d\n" .size .L.str.6, 37 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z3addPiS_S_i" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Initializing input arrays." .size .Lstr, 27 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "Running sequential job." .size .Lstr.1, 24 .type .Lstr.2,@object # @str.2 .Lstr.2: .asciz "Running parallel job." .size .Lstr.2, 22 .type .Lstr.3,@object # @str.3 .Lstr.3: .asciz "Correct result. No errors were found." .size .Lstr.3, 38 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__addPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3addPiS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
539
5,153
2,554
5,452
139
code for sm_80 Function : _Z16kernel_hypercubePiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; I2F.F64.U32 R4, c[0x0][0x0] ; S2R R3, SR_CTAID.X ; S2R R0, SR_TID.X ; ISETP.GT.AND P0, PT, R5, 0xfffff, PT ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; IMAD R3, R3, c[0x0][0x0], RZ ; @!P0 DMUL R6, R6, 1.80143985094819840000e+16 ; IMAD R3, R3, c[0x0][0x16c], RZ ; @!P0 IMAD.MOV.U32 R5, RZ, RZ, R7 ; @!P0 IMAD.MOV.U32 R4, RZ, RZ, R6 ; IADD3 R2, R5, -0x1, RZ ; ISETP.GE.U32.AND P1, PT, R2, 0x7fefffff, PT ; IMAD.MOV.U32 R2, RZ, RZ, -0x3ff ; @!P0 IMAD.MOV.U32 R2, RZ, RZ, -0x435 ; @!P1 BRA 0x180 ; IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; FSETP.NEU.AND P0, PT, R7, RZ, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x7ff00000 ; DFMA R4, R6, R4, +INF ; FSEL R6, R4, RZ, P0 ; FSEL R7, R5, -QNAN , P0 ; BRA 0x420 ; LOP3.LUT R6, R5.reuse, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; LEA.HI R5, R5, R2, RZ, 0xc ; IMAD.MOV.U32 R16, RZ, RZ, 0x3ae80f1e ; LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; IMAD.MOV.U32 R17, RZ, RZ, 0x3eb1380b ; ISETP.GE.AND P0, PT, R7, 0x3ff6a09f, PT ; @P0 IADD3 R9, R7, -0x100000, RZ ; @P0 IADD3 R5, R5, 0x1, RZ ; @P0 IMAD.MOV.U32 R7, RZ, RZ, R9 ; LOP3.LUT R4, R5, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x43300000 ; DADD R14, R6, 1 ; DADD R6, R6, -1 ; MUFU.RCP64H R9, R15 ; DADD R4, R4, c[0x2][0x38] ; DFMA R10, -R14, R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R8, R8, R10, R8 ; DMUL R10, R8, R6 ; DFMA R10, R8, R6, R10 ; DMUL R12, R10, R10 ; DADD R14, R6, -R10 ; DFMA R16, R12, R16, c[0x2][0x0] ; DADD R18, R14, R14 ; DFMA R16, R12, R16, c[0x2][0x8] ; DFMA R14, R4, c[0x2][0x40], R10 ; DFMA R16, R12, R16, c[0x2][0x10] ; DFMA R18, R6, -R10, R18 ; DFMA R16, R12, R16, c[0x2][0x18] ; DFMA R6, -R4, c[0x2][0x40], R14 ; DFMA R16, R12, R16, c[0x2][0x20] ; DMUL R18, R8, R18 ; DFMA R16, R12, R16, c[0x2][0x28] ; DADD R6, -R10, R6 ; DFMA R16, R12, R16, c[0x2][0x30] ; DMUL R16, R12, R16 ; DFMA R16, R10, R16, R18 ; DADD R6, R16, -R6 ; DFMA R6, R4, c[0x2][0x48], R6 ; DADD R6, R14, R6 ; IMAD R8, R0, c[0x0][0x16c], R3 ; ULDC.64 UR4, c[0x0][0x118] ; ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x168], PT ; @!P0 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; @!P0 IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x160] ; @!P0 LDG.E R9, [R8.64] ; DMUL R4, R6, c[0x2][0x50] ; @P0 STS [R0.X4], RZ ; DFMA R4, R6, c[0x2][0x58], R4 ; F2I.F64.CEIL R2, R4 ; @!P0 STS [R0.X4], R9 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P0, PT, R2, 0x1, PT ; @!P0 BRA 0xa30 ; IADD3 R4, R2.reuse, -0x1, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; ISETP.NE.AND P0, PT, R5, RZ, PT ; @!P1 BRA 0x8f0 ; IMAD.IADD R4, R2, 0x1, -R5 ; IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; IMAD.IADD R9, R2, 0x1, -R7 ; IADD3 R13, R7.reuse, 0x1, RZ ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; IADD3 R17, R7, 0x2, RZ ; IADD3 R4, R4, -0x4, RZ ; IMAD.IADD R11, R2, 0x1, -R13 ; SHF.L.U32 R9, R6, R9, RZ ; IMAD.IADD R15, R2, 0x1, -R17 ; ISETP.GE.AND P2, PT, R0, R9, PT ; SHF.L.U32 R11, R6.reuse, R11, RZ ; SHF.L.U32 R15, R6, R15, RZ ; ISETP.GE.AND P1, PT, R0, R11, PT ; @!P2 IADD3 R9, R7, -0x1, RZ ; @!P2 SHF.L.U32 R8, R0, R7, RZ ; @!P2 SHF.L.U32 R9, R6, R9, RZ ; @!P1 SHF.L.U32 R12, R0, R13, RZ ; @!P2 LDS R10, [R8.X4] ; @!P2 LOP3.LUT R9, R9, R8, RZ, 0xfc, !PT ; @!P1 SHF.L.U32 R13, R6, R7, RZ ; @!P2 LDS R9, [R9.X4] ; @!P1 LOP3.LUT R13, R13, R12, RZ, 0xfc, !PT ; @!P2 IMAD.IADD R11, R10, 0x1, R9 ; @!P2 STS [R8.X4], R11 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P2, PT, R0, R15, PT ; @!P2 IMAD.MOV.U32 R16, RZ, RZ, 0x2 ; @!P2 SHF.L.U32 R14, R0, R17, RZ ; @!P2 SHF.L.U32 R15, R16, R7, RZ ; @!P2 LOP3.LUT R15, R15, R14, RZ, 0xfc, !PT ; @!P1 LDS R10, [R13.X4] ; @!P1 LDS R9, [R12.X4] ; IADD3 R13, R7, 0x3, RZ ; IMAD.IADD R11, R2, 0x1, -R13 ; SHF.L.U32 R11, R6, R11, RZ ; @!P1 IMAD.IADD R9, R9, 0x1, R10 ; @!P1 STS [R12.X4], R9 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P1, PT, R0, R11, PT ; @!P1 IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; @!P1 SHF.L.U32 R6, R0, R13, RZ ; @!P1 SHF.L.U32 R11, R10, R7, RZ ; IADD3 R7, R7, 0x4, RZ ; @!P1 LOP3.LUT R11, R11, R6, RZ, 0xfc, !PT ; @!P2 LDS R15, [R15.X4] ; @!P2 LDS R8, [R14.X4] ; @!P2 IMAD.IADD R9, R8, 0x1, R15 ; @!P2 STS [R14.X4], R9 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P1 LDS R11, [R11.X4] ; @!P1 LDS R8, [R6.X4] ; @!P1 IMAD.IADD R13, R8, 0x1, R11 ; @!P1 STS [R6.X4], R13 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.AND P1, PT, R4, RZ, PT ; @P1 BRA 0x580 ; @!P0 BRA 0xa30 ; IMAD.IADD R2, R2, 0x1, -R7 ; IADD3 R7, R7, -0x1, RZ ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; SHF.L.U32 R9, R8, R2, RZ ; IADD3 R11, R7, 0x1, RZ ; ISETP.GE.AND P0, PT, R0, R9, PT ; IADD3 R5, R5, -0x1, RZ ; IADD3 R2, R2, -0x1, RZ ; @!P0 SHF.L.U32 R7, R8, R7, RZ ; @!P0 SHF.L.U32 R4, R0, R11, RZ ; @!P0 LOP3.LUT R6, R7, R4, RZ, 0xfc, !PT ; @!P0 LDS R7, [R4.X4] ; @!P0 LDS R6, [R6.X4] ; @!P0 IMAD.IADD R9, R7, 0x1, R6 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; @!P0 STS [R4.X4], R9 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.AND P0, PT, R5, RZ, PT ; @P0 BRA 0x930 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @P0 EXIT ; LDS R5, [RZ] ; IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; STG.E [R2.64], R5 ; EXIT ; BRA 0xaa0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0007b3f5_00000000-6_ca8ad5708dcfe6e15b0d03df5a3a606537147bee.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2065: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2065: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Erreur CUDA: %s:%d %s\n" .text .globl _Z14checkCudaError9cudaErrorPKci .type _Z14checkCudaError9cudaErrorPKci, @function _Z14checkCudaError9cudaErrorPKci: .LFB2057: .cfi_startproc endbr64 testl %edi, %edi jne .L8 ret .L8: pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rsi, %rbx movl %edx, %ebp call cudaGetErrorString@PLT movq %rax, %r9 movl %ebp, %r8d movq %rbx, %rcx leaq .LC0(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .cfi_endproc .LFE2057: .size _Z14checkCudaError9cudaErrorPKci, .-_Z14checkCudaError9cudaErrorPKci .globl _Z5sommePii .type _Z5sommePii, @function _Z5sommePii: .LFB2059: .cfi_startproc endbr64 testl %esi, %esi jle .L12 movq %rdi, %rdx movslq %esi, %rsi leaq (%rdi,%rsi,4), %rsi movl $0, %eax .L11: movslq (%rdx), %rcx addq %rcx, %rax addq $4, %rdx cmpq %rsi, %rdx jne .L11 ret .L12: movl $0, %eax ret .cfi_endproc .LFE2059: .size _Z5sommePii, .-_Z5sommePii .globl _Z12fillRandomlyPii .type _Z12fillRandomlyPii, @function _Z12fillRandomlyPii: .LFB2060: .cfi_startproc endbr64 testl %esi, %esi jle .L19 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movslq %esi, %rsi leaq (%rdi,%rsi,4), %rbp .L16: call rand@PLT movslq %eax, %rdx imulq $1431655766, %rdx, %rdx shrq $32, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx leal (%rdx,%rdx,2), %edx subl %edx, %eax movl %eax, (%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L16 addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L19: .cfi_restore 3 .cfi_restore 6 ret .cfi_endproc .LFE2060: .size _Z12fillRandomlyPii, .-_Z12fillRandomlyPii .section .rodata.str1.1 .LC1: .string "%d " .LC2: .string "\n" .text .globl _Z8printArrPii .type _Z8printArrPii, @function _Z8printArrPii: .LFB2061: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 testl %esi, %esi jle .L23 movq %rdi, %rbx movslq %esi, %rsi leaq (%rdi,%rsi,4), %r12 leaq .LC1(%rip), %rbp .L24: movl (%rbx), %edx movq %rbp, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %r12, %rbx jne .L24 .L23: leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _Z8printArrPii, .-_Z8printArrPii .globl _Z38__device_stub__Z16kernel_hypercubePiiiPiii .type _Z38__device_stub__Z16kernel_hypercubePiiiPiii, @function _Z38__device_stub__Z16kernel_hypercubePiiiPiii: .LFB2087: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L31 .L27: movq 104(%rsp), %rax subq %fs:40, %rax jne .L32 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L31: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z16kernel_hypercubePiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L27 .L32: call __stack_chk_fail@PLT .cfi_endproc .LFE2087: .size _Z38__device_stub__Z16kernel_hypercubePiiiPiii, .-_Z38__device_stub__Z16kernel_hypercubePiiiPiii .globl _Z16kernel_hypercubePiii .type _Z16kernel_hypercubePiii, @function _Z16kernel_hypercubePiii: .LFB2088: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z38__device_stub__Z16kernel_hypercubePiiiPiii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2088: .size _Z16kernel_hypercubePiii, .-_Z16kernel_hypercubePiii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC3: .string "/home/ubuntu/Datasets/Stack_v2_cuda-hip/train/ca8ad5708dcfe6e15b0d03df5a3a606537147bee.cu" .section .rodata.str1.1 .LC4: .string "R\303\251duction: stride=%d\n" .LC9: .string "nbBlocks=%d\n" .text .globl _Z9hypercubePii .type _Z9hypercubePii, @function _Z9hypercubePii: .LFB2058: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $64, %rsp .cfi_def_cfa_offset 112 movq %rdi, %r13 movl %esi, %ebp movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movq $0, 8(%rsp) leal 0(,%rsi,4), %r12d movslq %r12d, %r12 leaq 8(%rsp), %rdi movq %r12, %rsi call cudaMalloc@PLT movl %eax, %edi movl $79, %edx leaq .LC3(%rip), %rbx movq %rbx, %rsi call _Z14checkCudaError9cudaErrorPKci leaq 16(%rsp), %rdi call cudaEventCreate@PLT movl %eax, %edi movl $80, %edx movq %rbx, %rsi call _Z14checkCudaError9cudaErrorPKci leaq 24(%rsp), %rdi call cudaEventCreate@PLT movl %eax, %edi movl $81, %edx movq %rbx, %rsi call _Z14checkCudaError9cudaErrorPKci movl $1, %ecx movq %r12, %rdx movq %r13, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %edi movl $83, %edx movq %rbx, %rsi call _Z14checkCudaError9cudaErrorPKci movl $0, %esi movq 16(%rsp), %rdi call cudaEventRecord@PLT movl $1, %ebx jmp .L38 .L36: cvttsd2sil %xmm2, %r14d movl %r14d, %edx leaq .LC9(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1024, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl %r14d, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L42 .L37: call cudaDeviceSynchronize@PLT movl %eax, %edi movl $93, %edx leaq .LC3(%rip), %rsi call _Z14checkCudaError9cudaErrorPKci sall $10, %ebx cmpl %ebx, %ebp jle .L43 .L38: movl %ebx, %edx leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT pxor %xmm0, %xmm0 cvtsi2sdl %ebp, %xmm0 pxor %xmm1, %xmm1 cvtsi2sdl %ebx, %xmm1 divsd %xmm1, %xmm0 mulsd .LC5(%rip), %xmm0 movapd %xmm0, %xmm2 movsd .LC10(%rip), %xmm1 andpd %xmm0, %xmm1 movsd .LC6(%rip), %xmm3 ucomisd %xmm1, %xmm3 jbe .L36 cvttsd2siq %xmm0, %rax pxor %xmm1, %xmm1 cvtsi2sdq %rax, %xmm1 cmpnlesd %xmm1, %xmm2 movsd .LC8(%rip), %xmm4 andpd %xmm4, %xmm2 addsd %xmm2, %xmm1 movsd .LC10(%rip), %xmm2 andnpd %xmm0, %xmm2 orpd %xmm1, %xmm2 jmp .L36 .L42: movl %ebx, %edx movl %ebp, %esi movq 8(%rsp), %rdi call _Z38__device_stub__Z16kernel_hypercubePiiiPiii jmp .L37 .L43: movl $0, %esi movq 24(%rsp), %rdi call cudaEventRecord@PLT movl %eax, %edi movl $97, %edx leaq .LC3(%rip), %rbx movq %rbx, %rsi call _Z14checkCudaError9cudaErrorPKci movq 24(%rsp), %rdi call cudaEventSynchronize@PLT movl %eax, %edi movl $98, %edx movq %rbx, %rsi call _Z14checkCudaError9cudaErrorPKci leaq 44(%rsp), %rdi movq 24(%rsp), %rdx movq 16(%rsp), %rsi call cudaEventElapsedTime@PLT movl %eax, %edi movl $99, %edx movq %rbx, %rsi call _Z14checkCudaError9cudaErrorPKci movl $2, %ecx movq %r12, %rdx movq 8(%rsp), %rsi movq %r13, %rdi call cudaMemcpy@PLT movl %eax, %edi movl $101, %edx movq %rbx, %rsi call _Z14checkCudaError9cudaErrorPKci movq 8(%rsp), %rdi call cudaFree@PLT movl %eax, %edi movl $104, %edx movq %rbx, %rsi call _Z14checkCudaError9cudaErrorPKci movq 16(%rsp), %rdi call cudaEventDestroy@PLT movl %eax, %edi movl $105, %edx movq %rbx, %rsi call _Z14checkCudaError9cudaErrorPKci movq 24(%rsp), %rdi call cudaEventDestroy@PLT movl %eax, %edi movl $106, %edx movq %rbx, %rsi call _Z14checkCudaError9cudaErrorPKci movss 44(%rsp), %xmm0 movq 56(%rsp), %rax subq %fs:40, %rax jne .L44 addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L44: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size _Z9hypercubePii, .-_Z9hypercubePii .section .rodata.str1.8 .align 8 .LC11: .string "Erreur d'allocation m\303\251moire host\n" .section .rodata.str1.1 .LC15: .string "%ld \303\251l\303\251ments, %.3fMo\n" .LC16: .string "SequentielCPU: %ld, %.3lfs\n" .LC18: .string "HypercubeCUDA: %d, %.3fs\n" .text .globl main .type main, @function main: .LFB2062: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $64, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax cmpl $1, %edi jg .L58 movl $4000000, %edi call malloc@PLT movq %rax, %rbx testq %rax, %rax je .L52 movl $1234, %edi call srand@PLT movl $1000000, %esi movq %rbx, %rdi call _Z12fillRandomlyPii movl $1000000, %r12d movl $1000000, %r13d .L48: leaq 16(%rsp), %rdi call ftime@PLT movl %r13d, %esi movq %rbx, %rdi call _Z5sommePii movl %eax, %ebp leaq 32(%rsp), %rdi call ftime@PLT imulq $1000, 32(%rsp), %rax movzwl 40(%rsp), %edx addq %rdx, %rax imulq $1000, 16(%rsp), %rdx movzwl 24(%rsp), %ecx addq %rcx, %rdx subq %rdx, %rax pxor %xmm0, %xmm0 cvtsi2sdq %rax, %xmm0 divsd .LC12(%rip), %xmm0 movq %xmm0, %r14 testq %r12, %r12 js .L49 pxor %xmm0, %xmm0 cvtsi2sdq %r12, %xmm0 .L50: mulsd .LC13(%rip), %xmm0 mulsd .LC5(%rip), %xmm0 mulsd .LC14(%rip), %xmm0 movq %r12, %rdx leaq .LC15(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movslq %ebp, %rdx movq %r14, %xmm0 leaq .LC16(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl $1234, %edi call srand@PLT movl %r13d, %esi movq %rbx, %rdi call _Z12fillRandomlyPii movl %r13d, %esi movq %rbx, %rdi call _Z9hypercubePii movss %xmm0, 12(%rsp) cmpq $99, %r12 jbe .L59 .L51: movss 12(%rsp), %xmm0 divss .LC17(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movl (%rbx), %edx leaq .LC18(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq %rbx, %rdi call free@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L60 movl $0, %eax addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L58: .cfi_restore_state movq 8(%rsi), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %rbp movq %rax, %r12 leaq 0(,%rax,4), %rdi call malloc@PLT movq %rax, %rbx testq %rax, %rax je .L52 movl $1234, %edi call srand@PLT movl %ebp, %r13d movl %ebp, %esi movq %rbx, %rdi call _Z12fillRandomlyPii cmpq $99, %rbp ja .L48 movl %ebp, %esi movq %rbx, %rdi call _Z8printArrPii jmp .L48 .L52: leaq .LC11(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L49: movq %r12, %rax shrq %rax movq %r12, %rdx andl $1, %edx orq %rdx, %rax pxor %xmm0, %xmm0 cvtsi2sdq %rax, %xmm0 addsd %xmm0, %xmm0 jmp .L50 .L59: movl %r13d, %esi movq %rbx, %rdi call _Z8printArrPii jmp .L51 .L60: call __stack_chk_fail@PLT .cfi_endproc .LFE2062: .size main, .-main .section .rodata.str1.1 .LC19: .string "_Z16kernel_hypercubePiii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2090: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC19(%rip), %rdx movq %rdx, %rcx leaq _Z16kernel_hypercubePiii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2090: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC5: .long 0 .long 1062207488 .align 8 .LC6: .long 0 .long 1127219200 .align 8 .LC8: .long 0 .long 1072693248 .align 8 .LC10: .long -1 .long 2147483647 .align 8 .LC12: .long 0 .long 1083129856 .align 8 .LC13: .long 0 .long 1063256064 .align 8 .LC14: .long 0 .long 1074790400 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC17: .long 1148846080 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z16kernel_hypercubePiii ; -- Begin function _Z16kernel_hypercubePiii .globl _Z16kernel_hypercubePiii .p2align 8 .type _Z16kernel_hypercubePiii,@function _Z16kernel_hypercubePiii: ; @_Z16kernel_hypercubePiii ; %bb.0: s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b32 s1, s[0:1], 0x1c s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_mul_i32 s0, s15, s7 s_and_b32 s2, s1, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s0, s0, s2 v_mad_u64_u32 v[1:2], null, v0, s7, s[0:1] v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_2) v_cmpx_gt_u32_e64 s6, v1 s_cbranch_execz .LBB0_2 ; %bb.1: v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v1, vcc_lo, s4, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo global_load_b32 v2, v[1:2], off .LBB0_2: s_or_b32 exec_lo, exec_lo, s3 v_cvt_f64_u32_e32 v[3:4], s2 s_mov_b32 s3, 0x3fe55555 s_mov_b32 s2, 0x55555555 s_mov_b32 s7, 0x3fc38538 s_mov_b32 s6, 0x6b47b09a s_mov_b32 s9, 0x3fc3ab76 s_mov_b32 s8, 0xbf559e2b s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_frexp_mant_f64_e32 v[5:6], v[3:4] v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[5:6] s_mov_b32 s2, 0x55555780 v_cndmask_b32_e64 v1, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[5:6], v[5:6], v1 v_frexp_exp_i32_f64_e32 v1, v[3:4] v_add_f64 v[7:8], v[5:6], 1.0 v_add_f64 v[13:14], v[5:6], -1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo v_cmp_ne_u16_e64 vcc_lo, s1, 0 s_mov_b32 s1, 1 v_rcp_f64_e32 v[9:10], v[7:8] v_add_f64 v[15:16], v[7:8], -1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_f64 v[5:6], v[5:6], -v[15:16] s_waitcnt_depctr 0xfff v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[11:12], v[13:14], v[9:10] v_mul_f64 v[17:18], v[7:8], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[7:8], v[11:12], v[7:8], -v[17:18] v_fma_f64 v[5:6], v[11:12], v[5:6], v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[7:8], v[17:18], v[5:6] v_add_f64 v[15:16], v[13:14], -v[7:8] v_add_f64 v[17:18], v[7:8], -v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[13:14], v[13:14], -v[15:16] v_add_f64 v[5:6], v[17:18], -v[5:6] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[7:8], v[13:14], -v[7:8] v_add_f64 v[5:6], v[5:6], v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[5:6], v[15:16], v[5:6] v_mul_f64 v[5:6], v[9:10], v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[7:8], v[11:12], v[5:6] v_mul_f64 v[9:10], v[7:8], v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_fma_f64 v[13:14], v[9:10], s[8:9], s[6:7] s_mov_b32 s7, 0x3fc7474d s_mov_b32 s6, 0xd7f4df2e v_mul_f64 v[15:16], v[7:8], v[9:10] v_fma_f64 v[13:14], v[9:10], v[13:14], s[6:7] s_mov_b32 s7, 0x3fcc71c0 s_mov_b32 s6, 0x16291751 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[13:14], v[9:10], v[13:14], s[6:7] s_mov_b32 s7, 0x3fd24924 s_mov_b32 s6, 0x9b27acf1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[13:14], v[9:10], v[13:14], s[6:7] s_mov_b32 s7, 0x3fd99999 s_mov_b32 s6, 0x998ef7b6 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[13:14], v[9:10], v[13:14], s[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) v_fma_f64 v[9:10], v[9:10], v[13:14], s[2:3] v_ldexp_f64 v[13:14], v[7:8], 1 v_add_f64 v[7:8], v[7:8], -v[11:12] s_mov_b32 s3, 0x3ff71547 s_mov_b32 s2, 0x652b82fe v_mul_f64 v[9:10], v[15:16], v[9:10] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[5:6], v[5:6], -v[7:8] v_add_f64 v[11:12], v[13:14], v[9:10] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ldexp_f64 v[5:6], v[5:6], 1 v_add_f64 v[7:8], v[11:12], -v[13:14] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[7:8], v[9:10], -v[7:8] v_add_f64 v[5:6], v[5:6], v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[7:8], v[11:12], v[5:6] v_add_f64 v[9:10], v[7:8], -v[11:12] v_mul_f64 v[11:12], v[7:8], s[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[5:6], v[5:6], -v[9:10] v_fma_f64 v[9:10], v[7:8], s[2:3], -v[11:12] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[5:6], v[5:6], s[2:3], v[9:10] s_mov_b32 s3, 0x3c7777d0 s_mov_b32 s2, 0xffda0d24 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[3:4], v[7:8], s[2:3], v[5:6] v_cvt_f64_i32_e32 v[5:6], v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[7:8], v[11:12], v[3:4] v_add_f64 v[9:10], v[7:8], v[5:6] v_add_f64 v[11:12], v[7:8], -v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[13:14], v[9:10], -v[5:6] v_add_f64 v[3:4], v[3:4], -v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[15:16], v[13:14], -v[9:10] v_add_f64 v[7:8], v[7:8], -v[13:14] v_add_f64 v[5:6], v[15:16], v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[5:6], v[7:8], v[5:6] v_add_f64 v[3:4], v[3:4], v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[3:4], v[9:10], v[3:4] v_cndmask_b32_e32 v4, 0xfff00000, v4, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v3, 0, v3, vcc_lo v_ceil_f64_e32 v[3:4], v[3:4] s_delay_alu instid0(VALU_DEP_1) v_cvt_i32_f64_e32 v1, v[3:4] v_lshlrev_b32_e32 v3, 2, v0 s_waitcnt vmcnt(0) ds_store_b32 v3, v2 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmp_gt_i32_e32 vcc_lo, 1, v1 v_readfirstlane_b32 s2, v1 s_cbranch_vccnz .LBB0_7 ; %bb.3: ; %.lr.ph.preheader s_delay_alu instid0(VALU_DEP_1) s_add_i32 s2, s2, -1 s_branch .LBB0_5 .p2align 6 .LBB0_4: ; in Loop: Header=BB0_5 Depth=1 s_or_b32 exec_lo, exec_lo, s3 s_add_i32 s2, s2, -1 s_add_i32 s1, s1, 1 s_cmp_lg_u32 s2, -1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB0_7 .LBB0_5: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_lshl_b32 s3, 1, s2 s_delay_alu instid0(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s3, v0 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB0_4 ; %bb.6: ; in Loop: Header=BB0_5 Depth=1 v_lshlrev_b32_e32 v1, s1, v0 s_add_i32 s6, s1, -1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_lshl_or_b32 v2, 1, s6, v1 v_lshlrev_b32_e32 v1, 2, v1 s_delay_alu instid0(VALU_DEP_2) v_lshlrev_b32_e32 v2, 2, v2 ds_load_b32 v2, v2 ds_load_b32 v3, v1 s_waitcnt lgkmcnt(0) v_add_nc_u32_e32 v2, v3, v2 ds_store_b32 v1, v2 s_branch .LBB0_4 .LBB0_7: ; %._crit_edge s_mov_b32 s1, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_9 ; %bb.8: v_mov_b32_e32 v0, 0 s_ashr_i32 s1, s0, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[0:1], s[0:1], 2 s_add_u32 s0, s4, s0 ds_load_b32 v1, v0 s_addc_u32 s1, s5, s1 s_waitcnt lgkmcnt(0) global_store_b32 v0, v1, s[0:1] .LBB0_9: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z16kernel_hypercubePiii .amdhsa_group_segment_fixed_size 4096 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 19 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z16kernel_hypercubePiii, .Lfunc_end0-_Z16kernel_hypercubePiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1180 ; NumSgprs: 18 ; NumVgprs: 19 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 4096 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 19 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 4096 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z16kernel_hypercubePiii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z16kernel_hypercubePiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 19 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "ca8ad5708dcfe6e15b0d03df5a3a606537147bee.hip" .globl _Z14checkCudaError10hipError_tPKci # -- Begin function _Z14checkCudaError10hipError_tPKci .p2align 4, 0x90 .type _Z14checkCudaError10hipError_tPKci,@function _Z14checkCudaError10hipError_tPKci: # @_Z14checkCudaError10hipError_tPKci .cfi_startproc # %bb.0: testl %edi, %edi jne .LBB0_2 # %bb.1: retq .LBB0_2: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movq stderr(%rip), %rbx movl %edx, %ebp movq %rsi, %r14 callq hipGetErrorString movl $.L.str, %esi movq %rbx, %rdi movq %r14, %rdx movl %ebp, %ecx movq %rax, %r8 xorl %eax, %eax callq fprintf movl $1, %edi callq exit .Lfunc_end0: .size _Z14checkCudaError10hipError_tPKci, .Lfunc_end0-_Z14checkCudaError10hipError_tPKci .cfi_endproc # -- End function .globl _Z31__device_stub__kernel_hypercubePiii # -- Begin function _Z31__device_stub__kernel_hypercubePiii .p2align 4, 0x90 .type _Z31__device_stub__kernel_hypercubePiii,@function _Z31__device_stub__kernel_hypercubePiii: # @_Z31__device_stub__kernel_hypercubePiii .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) movq %rsp, %rax movq %rax, 80(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z16kernel_hypercubePiii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end1: .size _Z31__device_stub__kernel_hypercubePiii, .Lfunc_end1-_Z31__device_stub__kernel_hypercubePiii .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function _Z9hypercubePii .LCPI2_0: .quad 0x3f50000000000000 # double 9.765625E-4 .text .globl _Z9hypercubePii .p2align 4, 0x90 .type _Z9hypercubePii,@function _Z9hypercubePii: # @_Z9hypercubePii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $136, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %esi, %r15d movq %rdi, %rbx leal (,%r15,4), %eax movq $0, (%rsp) movslq %eax, %r14 movq %rsp, %rdi movq %r14, %rsi callq hipMalloc testl %eax, %eax jne .LBB2_1 # %bb.3: # %_Z14checkCudaError10hipError_tPKci.exit leaq 16(%rsp), %rdi callq hipEventCreate testl %eax, %eax jne .LBB2_4 # %bb.5: # %_Z14checkCudaError10hipError_tPKci.exit19 leaq 8(%rsp), %rdi callq hipEventCreate testl %eax, %eax jne .LBB2_6 # %bb.7: # %_Z14checkCudaError10hipError_tPKci.exit21 movq (%rsp), %rdi movl $1, %ebp movq %rbx, 64(%rsp) # 8-byte Spill movq %rbx, %rsi movq %r14, 56(%rsp) # 8-byte Spill movq %r14, %rdx movl $1, %ecx callq hipMemcpy testl %eax, %eax jne .LBB2_8 # %bb.9: # %_Z14checkCudaError10hipError_tPKci.exit23 movabsq $4294967296, %r13 # imm = 0x100000000 movq 16(%rsp), %rdi xorl %esi, %esi callq hipEventRecord cvtsi2sd %r15d, %xmm0 movsd %xmm0, 72(%rsp) # 8-byte Spill leaq 1024(%r13), %r12 leaq 32(%rsp), %rbx .p2align 4, 0x90 .LBB2_10: # =>This Inner Loop Header: Depth=1 movl $.L.str.2, %edi movl %ebp, %esi xorl %eax, %eax callq printf xorps %xmm1, %xmm1 cvtsi2sd %ebp, %xmm1 movsd 72(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero divsd %xmm1, %xmm0 mulsd .LCPI2_0(%rip), %xmm0 callq ceil@PLT cvttsd2si %xmm0, %r14d movl $.L.str.3, %edi movl %r14d, %esi xorl %eax, %eax callq printf orq %r13, %r14 movq %r14, %rdi movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_12 # %bb.11: # in Loop: Header=BB2_10 Depth=1 movq (%rsp), %rax movq %rax, 128(%rsp) movl %r15d, 28(%rsp) movl %ebp, 24(%rsp) leaq 128(%rsp), %rax movq %rax, 32(%rsp) leaq 28(%rsp), %rax movq %rax, 40(%rsp) leaq 24(%rsp), %rax movq %rax, 48(%rsp) leaq 112(%rsp), %rdi leaq 96(%rsp), %rsi leaq 88(%rsp), %rdx leaq 80(%rsp), %rcx callq __hipPopCallConfiguration movq 112(%rsp), %rsi movl 120(%rsp), %edx movq 96(%rsp), %rcx movl 104(%rsp), %r8d movl $_Z16kernel_hypercubePiii, %edi movq %rbx, %r9 pushq 80(%rsp) .cfi_adjust_cfa_offset 8 pushq 96(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_12: # in Loop: Header=BB2_10 Depth=1 callq hipDeviceSynchronize testl %eax, %eax jne .LBB2_13 # %bb.14: # %_Z14checkCudaError10hipError_tPKci.exit25 # in Loop: Header=BB2_10 Depth=1 shll $10, %ebp cmpl %r15d, %ebp jl .LBB2_10 # %bb.15: movq 8(%rsp), %rdi xorl %esi, %esi callq hipEventRecord testl %eax, %eax jne .LBB2_16 # %bb.17: # %_Z14checkCudaError10hipError_tPKci.exit27 movq 8(%rsp), %rdi callq hipEventSynchronize testl %eax, %eax movq 64(%rsp), %rbx # 8-byte Reload movq 56(%rsp), %r14 # 8-byte Reload jne .LBB2_18 # %bb.19: # %_Z14checkCudaError10hipError_tPKci.exit29 movq 16(%rsp), %rsi movq 8(%rsp), %rdx leaq 32(%rsp), %rdi callq hipEventElapsedTime testl %eax, %eax jne .LBB2_20 # %bb.21: # %_Z14checkCudaError10hipError_tPKci.exit31 movq (%rsp), %rsi movq %rbx, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy testl %eax, %eax jne .LBB2_22 # %bb.23: # %_Z14checkCudaError10hipError_tPKci.exit33 movq (%rsp), %rdi callq hipFree testl %eax, %eax jne .LBB2_24 # %bb.25: # %_Z14checkCudaError10hipError_tPKci.exit35 movq 16(%rsp), %rdi callq hipEventDestroy testl %eax, %eax jne .LBB2_26 # %bb.27: # %_Z14checkCudaError10hipError_tPKci.exit37 movq 8(%rsp), %rdi callq hipEventDestroy testl %eax, %eax jne .LBB2_28 # %bb.29: # %_Z14checkCudaError10hipError_tPKci.exit39 movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero addq $136, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_13: .cfi_def_cfa_offset 192 movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movl $.L.str.1, %edx movq %rbx, %rdi movl $95, %ecx .LBB2_2: movq %rax, %r8 xorl %eax, %eax callq fprintf movl $1, %edi callq exit .LBB2_1: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movl $.L.str.1, %edx movq %rbx, %rdi movl $81, %ecx jmp .LBB2_2 .LBB2_4: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movl $.L.str.1, %edx movq %rbx, %rdi movl $82, %ecx jmp .LBB2_2 .LBB2_6: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movl $.L.str.1, %edx movq %rbx, %rdi movl $83, %ecx jmp .LBB2_2 .LBB2_8: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movl $.L.str.1, %edx movq %rbx, %rdi movl $85, %ecx jmp .LBB2_2 .LBB2_16: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movl $.L.str.1, %edx movq %rbx, %rdi movl $99, %ecx jmp .LBB2_2 .LBB2_18: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movl $.L.str.1, %edx movq %rbx, %rdi movl $100, %ecx jmp .LBB2_2 .LBB2_20: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movl $.L.str.1, %edx movq %rbx, %rdi movl $101, %ecx jmp .LBB2_2 .LBB2_22: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movl $.L.str.1, %edx movq %rbx, %rdi movl $103, %ecx jmp .LBB2_2 .LBB2_24: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movl $.L.str.1, %edx movq %rbx, %rdi movl $106, %ecx jmp .LBB2_2 .LBB2_26: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movl $.L.str.1, %edx movq %rbx, %rdi movl $107, %ecx jmp .LBB2_2 .LBB2_28: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str, %esi movl $.L.str.1, %edx movq %rbx, %rdi movl $108, %ecx jmp .LBB2_2 .Lfunc_end2: .size _Z9hypercubePii, .Lfunc_end2-_Z9hypercubePii .cfi_endproc # -- End function .globl _Z5sommePii # -- Begin function _Z5sommePii .p2align 4, 0x90 .type _Z5sommePii,@function _Z5sommePii: # @_Z5sommePii .cfi_startproc # %bb.0: testl %esi, %esi jle .LBB3_1 # %bb.2: # %.lr.ph.preheader movslq %esi, %rcx xorl %eax, %eax xorl %edx, %edx .p2align 4, 0x90 .LBB3_3: # %.lr.ph # =>This Inner Loop Header: Depth=1 movl (%rdi,%rdx,4), %esi addq %rsi, %rax incq %rdx cmpq %rdx, %rcx jne .LBB3_3 # %bb.4: # %._crit_edge # kill: def $eax killed $eax killed $rax retq .LBB3_1: xorl %eax, %eax # kill: def $eax killed $eax killed $rax retq .Lfunc_end3: .size _Z5sommePii, .Lfunc_end3-_Z5sommePii .cfi_endproc # -- End function .globl _Z12fillRandomlyPii # -- Begin function _Z12fillRandomlyPii .p2align 4, 0x90 .type _Z12fillRandomlyPii,@function _Z12fillRandomlyPii: # @_Z12fillRandomlyPii .cfi_startproc # %bb.0: testl %esi, %esi jle .LBB4_4 # %bb.1: # %.lr.ph.preheader pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx movl %esi, %r14d xorl %r15d, %r15d .p2align 4, 0x90 .LBB4_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1431655766, %rax, %rcx # imm = 0x55555556 movq %rcx, %rdx shrq $63, %rdx shrq $32, %rcx addl %edx, %ecx leal (%rcx,%rcx,2), %ecx subl %ecx, %eax movl %eax, (%rbx,%r15,4) incq %r15 cmpq %r15, %r14 jne .LBB4_2 # %bb.3: popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 .cfi_restore %rbx .cfi_restore %r14 .cfi_restore %r15 .LBB4_4: # %._crit_edge retq .Lfunc_end4: .size _Z12fillRandomlyPii, .Lfunc_end4-_Z12fillRandomlyPii .cfi_endproc # -- End function .globl _Z8printArrPii # -- Begin function _Z8printArrPii .p2align 4, 0x90 .type _Z8printArrPii,@function _Z8printArrPii: # @_Z8printArrPii .cfi_startproc # %bb.0: testl %esi, %esi jle .LBB5_4 # %bb.1: # %.lr.ph.preheader pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx movl %esi, %r14d xorl %r15d, %r15d .p2align 4, 0x90 .LBB5_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movl (%rbx,%r15,4), %esi movl $.L.str.4, %edi xorl %eax, %eax callq printf incq %r15 cmpq %r15, %r14 jne .LBB5_2 # %bb.3: popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 .cfi_restore %rbx .cfi_restore %r14 .cfi_restore %r15 .LBB5_4: # %._crit_edge movl $10, %edi jmp putchar@PLT # TAILCALL .Lfunc_end5: .size _Z8printArrPii, .Lfunc_end5-_Z8printArrPii .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI6_0: .quad 0x408f400000000000 # double 1000 .LCPI6_3: .quad 0x3f60000000000000 # double 0.001953125 .LCPI6_4: .quad 0x3f50000000000000 # double 9.765625E-4 .LCPI6_5: .quad 0x4010000000000000 # double 4 .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 .LCPI6_1: .long 1127219200 # 0x43300000 .long 1160773632 # 0x45300000 .long 0 # 0x0 .long 0 # 0x0 .LCPI6_2: .quad 0x4330000000000000 # double 4503599627370496 .quad 0x4530000000000000 # double 1.9342813113834067E+25 .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 .LCPI6_6: .long 0x447a0000 # float 1000 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $40, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $1000000, %r14d # imm = 0xF4240 cmpl $2, %edi jl .LBB6_2 # %bb.1: movq 8(%rsi), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r14 .LBB6_2: leaq (,%r14,4), %rdi callq malloc testq %rax, %rax je .LBB6_25 # %bb.3: movq %rax, %rbx movl $1234, %edi # imm = 0x4D2 callq srand testl %r14d, %r14d jle .LBB6_6 # %bb.4: # %.lr.ph.preheader.i movl %r14d, %r15d xorl %r12d, %r12d .p2align 4, 0x90 .LBB6_5: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1431655766, %rax, %rcx # imm = 0x55555556 movq %rcx, %rdx shrq $63, %rdx shrq $32, %rcx addl %edx, %ecx leal (%rcx,%rcx,2), %ecx subl %ecx, %eax movl %eax, (%rbx,%r12,4) incq %r12 cmpq %r12, %r15 jne .LBB6_5 .LBB6_6: # %_Z12fillRandomlyPii.exit cmpq $99, %r14 ja .LBB6_11 # %bb.7: testl %r14d, %r14d jle .LBB6_10 # %bb.8: # %.lr.ph.i27.preheader xorl %r15d, %r15d .p2align 4, 0x90 .LBB6_9: # %.lr.ph.i27 # =>This Inner Loop Header: Depth=1 movl (%rbx,%r15,4), %esi movl $.L.str.4, %edi xorl %eax, %eax callq printf incq %r15 cmpq %r15, %r14 jne .LBB6_9 .LBB6_10: # %_Z8printArrPii.exit movl $10, %edi callq putchar@PLT .LBB6_11: leaq 24(%rsp), %rdi callq ftime testl %r14d, %r14d jle .LBB6_12 # %bb.13: # %.lr.ph.i31.preheader movslq %r14d, %rcx xorl %eax, %eax xorl %edx, %edx .p2align 4, 0x90 .LBB6_14: # %.lr.ph.i31 # =>This Inner Loop Header: Depth=1 movl (%rbx,%rdx,4), %esi addq %rsi, %rax incq %rdx cmpq %rdx, %rcx jne .LBB6_14 # %bb.15: # %._crit_edge.loopexit.i movslq %eax, %r15 jmp .LBB6_16 .LBB6_12: xorl %r15d, %r15d .LBB6_16: # %_Z5sommePii.exit leaq 8(%rsp), %rdi callq ftime movq 8(%rsp), %rax movzwl 16(%rsp), %ecx movzwl 32(%rsp), %edx subq %rdx, %rcx subq 24(%rsp), %rax imulq $1000, %rax, %rax # imm = 0x3E8 addq %rcx, %rax cvtsi2sd %rax, %xmm0 divsd .LCPI6_0(%rip), %xmm0 movsd %xmm0, (%rsp) # 8-byte Spill movq %r14, %xmm1 punpckldq .LCPI6_1(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] subpd .LCPI6_2(%rip), %xmm1 movapd %xmm1, %xmm0 unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1] addsd %xmm1, %xmm0 mulsd .LCPI6_3(%rip), %xmm0 mulsd .LCPI6_4(%rip), %xmm0 mulsd .LCPI6_5(%rip), %xmm0 movl $.L.str.7, %edi movq %r14, %rsi movb $1, %al callq printf movl $.L.str.8, %edi movq %r15, %rsi movsd (%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero movb $1, %al callq printf movl $1234, %edi # imm = 0x4D2 callq srand testl %r14d, %r14d jle .LBB6_19 # %bb.17: # %.lr.ph.preheader.i33 movl %r14d, %r15d xorl %r12d, %r12d .p2align 4, 0x90 .LBB6_18: # %.lr.ph.i35 # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1431655766, %rax, %rcx # imm = 0x55555556 movq %rcx, %rdx shrq $63, %rdx shrq $32, %rcx addl %edx, %ecx leal (%rcx,%rcx,2), %ecx subl %ecx, %eax movl %eax, (%rbx,%r12,4) incq %r12 cmpq %r12, %r15 jne .LBB6_18 .LBB6_19: # %_Z12fillRandomlyPii.exit39 movq %rbx, %rdi movl %r14d, %esi callq _Z9hypercubePii cmpq $99, %r14 ja .LBB6_24 # %bb.20: movss %xmm0, (%rsp) # 4-byte Spill testl %r14d, %r14d jle .LBB6_23 # %bb.21: # %.lr.ph.i43.preheader xorl %r15d, %r15d .p2align 4, 0x90 .LBB6_22: # %.lr.ph.i43 # =>This Inner Loop Header: Depth=1 movl (%rbx,%r15,4), %esi movl $.L.str.4, %edi xorl %eax, %eax callq printf incq %r15 cmpq %r15, %r14 jne .LBB6_22 .LBB6_23: # %_Z8printArrPii.exit47 movl $10, %edi callq putchar@PLT movss (%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero .LBB6_24: movl (%rbx), %esi divss .LCPI6_6(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movl $.L.str.9, %edi movb $1, %al callq printf movq %rbx, %rdi callq free xorl %eax, %eax addq $40, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB6_25: .cfi_def_cfa_offset 80 movq stderr(%rip), %rcx movl $.L.str.6, %edi movl $32, %esi movl $1, %edx callq fwrite@PLT movl $1, %edi callq exit .Lfunc_end6: .size main, .Lfunc_end6-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB7_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB7_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z16kernel_hypercubePiii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end7: .size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB8_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB8_2: retq .Lfunc_end8: .size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Erreur CUDA: %s:%d %s\n" .size .L.str, 23 .type _Z16kernel_hypercubePiii,@object # @_Z16kernel_hypercubePiii .section .rodata,"a",@progbits .globl _Z16kernel_hypercubePiii .p2align 3, 0x0 _Z16kernel_hypercubePiii: .quad _Z31__device_stub__kernel_hypercubePiii .size _Z16kernel_hypercubePiii, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "/home/ubuntu/Datasets/Stack_v2_cuda-hip-as/ca8ad5708dcfe6e15b0d03df5a3a606537147bee.hip" .size .L.str.1, 88 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Rduction: stride=%d\n" .size .L.str.2, 21 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "nbBlocks=%d\n" .size .L.str.3, 13 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "%d " .size .L.str.4, 4 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Erreur d'allocation mmoire host\n" .size .L.str.6, 33 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "%ld lments, %.3fMo\n" .size .L.str.7, 20 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "SequentielCPU: %ld, %.3lfs\n" .size .L.str.8, 28 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "HypercubeCUDA: %d, %.3fs\n" .size .L.str.9, 26 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z16kernel_hypercubePiii" .size .L__unnamed_1, 25 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z31__device_stub__kernel_hypercubePiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z16kernel_hypercubePiii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
4,226
7,730
6,443
10,713
140
code for sm_80 Function : _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_TID.X ; IMAD.MOV.U32 R30, RZ, RZ, c[0x0][0x160] ; ULDC.64 UR6, c[0x0][0x118] ; IMAD.MOV.U32 R31, RZ, RZ, c[0x0][0x164] ; ISETP.NE.AND P1, PT, R2, RZ, PT ; @!P1 IMAD.MOV.U32 R3, RZ, RZ, -0x1 ; @!P1 STS [RZ], R3 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDG.E R0, [R30.64] ; LDS R5, [RZ] ; IADD3 R0, R0, -0x1, RZ ; ISETP.GE.AND P0, PT, R5, R0, PT ; @P0 EXIT ; IADD3 R3, R2.reuse, 0x1, RZ ; IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; SHF.R.S32.HI R7, RZ, 0x1f, R2 ; IMAD.MOV.U32 R0, RZ, RZ, R5 ; SHF.R.S32.HI R6, RZ, 0x1f, R3 ; IMAD.WIDE R28, R2.reuse, R17.reuse, c[0x0][0x178] ; SHF.L.U64.HI R4, R2.reuse, 0x2, R7 ; SHF.L.U64.HI R5, R3, 0x2, R6 ; IMAD.WIDE R26, R2, R17, c[0x0][0x180] ; IMAD.WIDE R24, R2, R17, c[0x0][0x168] ; IMAD.WIDE R22, R2, R17, c[0x0][0x170] ; IMAD.WIDE R20, R2, R17, c[0x0][0x188] ; IMAD.WIDE R18, R2, R17, c[0x0][0x190] ; IMAD.WIDE R16, R2, R17, c[0x0][0x1b0] ; @!P1 IADD3 R0, R0, 0x1, RZ ; BSSY B0, 0x3a0 ; @!P1 STS [RZ], R0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDS R7, [RZ] ; STS [0xc], RZ ; ISETP.NE.AND P0, PT, R2, R7, PT ; @P0 IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; @P0 IMAD.MOV.U32 R9, RZ, RZ, 0x7fffffff ; @P0 STG.E [R24.64], R7 ; @P0 STG.E [R22.64], RZ ; @P0 STG.E [R28.64], R9 ; @P0 STG.E [R26.64], RZ ; @P0 BRA 0x390 ; IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; STG.E [R28.64], RZ ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x1a0] ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x1a4] ; STG.E [R26.64], R11 ; IMAD.MOV.U32 R0, RZ, RZ, 0x2 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x198] ; STG.E [R24.64], RZ ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x19c] ; STG.E [R22.64], R11 ; STG.E [R6.64], R2 ; STS [0x4], R0 ; STS [0x8], R11 ; STG.E [R8.64+0x4], R11 ; STG.E [R8.64], RZ ; BSYNC B0 ; STG.E [R20.64], RZ ; STG.E [R18.64], RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDS R0, [0xc] ; ISETP.NE.AND P0, PT, R0, 0x7fffffff, PT ; @!P0 BRA 0xc90 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDG.E R0, [R22.64] ; ISETP.NE.AND P0, PT, R0, 0x1, PT ; @P0 BRA 0x830 ; LDG.E.64 R6, [R30.64+0x8] ; LEA R6, P0, R2, R6, 0x2 ; IMAD.X R7, R7, 0x1, R4, P0 ; LD.E R0, [R6.64+0x4] ; LD.E R9, [R6.64] ; ISETP.GE.AND P0, PT, R9, R0, PT ; @P0 BRA 0x830 ; IMAD.MOV.U32 R0, RZ, RZ, R9 ; LDG.E.64 R6, [R30.64+0x10] ; LDG.E.64 R8, [R30.64+0x18] ; IMAD.WIDE R14, R0, 0x4, R6 ; IMAD.WIDE R32, R0, 0x4, R8 ; LD.E R14, [R14.64] ; LD.E R32, [R32.64] ; IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; BSSY B0, 0x7c0 ; IMAD.MOV.U32 R34, RZ, RZ, 0x1 ; IMAD.WIDE R6, R14, R13, c[0x0][0x190] ; IMAD.WIDE R8, R14, R13, c[0x0][0x168] ; IMAD.WIDE R10, R14, R13, c[0x0][0x178] ; IMAD.WIDE R12, R14, R13, c[0x0][0x180] ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; YIELD ; IMAD.MOV.U32 R15, RZ, RZ, 0x1 ; ATOMG.E.CAS.STRONG.GPU PT, R14, [R6], R14, R15 ; BSSY B1, 0x790 ; ISETP.NE.AND P0, PT, R14, RZ, PT ; @P0 BRA 0x780 ; LDG.E R14, [R8.64] ; BSSY B2, 0x6b0 ; ISETP.NE.AND P0, PT, R14, 0x1, PT ; @P0 BRA 0x6a0 ; LDG.E R14, [R28.64] ; LDG.E R15, [R10.64] ; IMAD.IADD R14, R32, 0x1, R14 ; ISETP.GE.AND P0, PT, R14, R15, PT ; @!P0 STG.E [R10.64], R14 ; @!P0 STG.E [R12.64], RZ ; BSYNC B2 ; LDG.E R15, [R28.64] ; LDG.E R14, [R10.64] ; BSSY B2, 0x760 ; IMAD.IADD R15, R32, 0x1, R15 ; ISETP.NE.AND P0, PT, R14, R15, PT ; @P0 BRA 0x750 ; LDG.E R15, [R12.64] ; LDG.E R14, [R26.64] ; IMAD.IADD R15, R14, 0x1, R15 ; STG.E [R12.64], R15 ; BSYNC B2 ; ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R6.64], RZ ; PRMT R34, RZ, 0x7610, R34 ; BSYNC B1 ; LOP3.LUT P0, RZ, R34, 0xff, RZ, 0xc0, !PT ; @P0 BRA 0x590 ; BSYNC B0 ; LDG.E.64 R6, [R30.64+0x8] ; LEA R6, P0, R3, R6, 0x2 ; IMAD.X R7, R7, 0x1, R5, P0 ; LD.E R7, [R6.64] ; IADD3 R0, R0, 0x1, RZ ; ISETP.GE.AND P0, PT, R0, R7, PT ; @!P0 BRA 0x4c0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x7fffffff ; WARPSYNC 0xffffffff ; STS [0xc], R6 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDG.E R0, [R24.64] ; BSSY B0, 0x980 ; ISETP.NE.AND P0, PT, R0, 0x1, PT ; @P0 BRA 0x970 ; LDG.E R0, [R28.64] ; ISETP.NE.AND P0, PT, R0, 0x7fffffff, PT ; @!P0 BRA 0x970 ; LDG.E R7, [R16.64] ; VOTEU.ANY UR4, UPT, PT ; UFLO.U32 UR4, UR4 ; S2R R6, SR_LANEID ; ISETP.EQ.U32.AND P0, PT, R6, UR4, PT ; IMAD.IADD R7, R0, 0x1, R7 ; REDUX.MIN.S32 UR5, R7 ; IMAD.U32 R0, RZ, RZ, UR5 ; @P0 ATOMS.MIN.S32 RZ, [0xc], R0 ; BSYNC B0 ; STS [0x1c], RZ ; STG.E [R22.64], RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDG.E R0, [R24.64] ; BSSY B0, 0xb60 ; ISETP.NE.AND P0, PT, R0, 0x1, PT ; @P0 BRA 0xb50 ; LDG.E R0, [R28.64] ; LDS R7, [0xc] ; ISETP.GE.AND P0, PT, R0, R7, PT ; @P0 BRA 0xb50 ; S2R R7, SR_LANEID ; VOTEU.ANY UR4, UPT, PT ; IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; FLO.U32 R8, UR4 ; IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; STG.E [R24.64], RZ ; STG.E [R22.64], R11 ; POPC R0, UR4 ; ISETP.EQ.U32.AND P0, PT, R8, R7, PT ; S2R R7, SR_LTMASK ; @P0 ATOMS.ADD R9, [0x8], R0 ; ATOMS.POPC.INC.32 RZ, [URZ+0x1c] ; LOP3.LUT R10, R7, UR4, RZ, 0xc0, !PT ; POPC R7, R10 ; SHFL.IDX PT, R6, R9, R8, 0x1f ; IMAD.IADD R6, R6, 0x1, R7 ; IMAD.WIDE R6, R6, R13, c[0x0][0x1a0] ; STG.E [R6.64], R2 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0xc50 ; LDS R0, [0x1c] ; ISETP.GE.AND P0, PT, R0, 0x1, PT ; ISETP.NE.OR P0, PT, R2, RZ, !P0 ; @P0 BRA 0xc40 ; LDS R8, [0x4] ; IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; IMAD.WIDE R6, R8, R7, c[0x0][0x198] ; LDG.E R9, [R6.64+-0x4] ; IADD3 R8, R8, 0x1, RZ ; STS [0x4], R8 ; IMAD.IADD R9, R0, 0x1, R9 ; STG.E [R6.64], R9 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDS R0, [0xc] ; ISETP.NE.AND P0, PT, R0, 0x7fffffff, PT ; @P0 BRA 0x400 ; @!P1 LDS R0, [0x4] ; WARPSYNC 0xffffffff ; @!P1 IADD3 R0, R0, -0x1, RZ ; @!P1 STS [0x10], R0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDS R6, [0x10] ; ISETP.GE.AND P0, PT, R6, 0x1, PT ; @!P0 BRA 0x14e0 ; BSSY B0, 0xdb0 ; @P1 BRA 0xda0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; IMAD.WIDE R6, R6, R7, c[0x0][0x198] ; LDG.E R8, [R6.64] ; LDG.E R0, [R6.64+-0x4] ; IADD3 R8, R8, -0x1, RZ ; STS [0x14], R0 ; STS [0x18], R8 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P0, PT, R2, RZ, PT ; BSSY B0, 0x1460 ; @!P0 BRA 0x1450 ; LDS R9, [0x14] ; LDS R0, [0x18] ; IMAD.IADD R7, R0, 0x1, -R9 ; ISETP.GT.AND P0, PT, R2, R7, PT ; @P0 BRA 0x1450 ; IMAD.IADD R8, R2, 0x1, R9 ; LDG.E.64 R32, [R30.64+0x8] ; IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; IMAD.WIDE R8, R8, R9, c[0x0][0x1a0] ; LDG.E R6, [R8.64] ; IMAD.WIDE R10, R6, 0x4, R32 ; LD.E R0, [R10.64+0x4] ; LD.E R9, [R10.64] ; BSSY B1, 0x1390 ; SHF.R.S32.HI R7, RZ, 0x1f, R6 ; ISETP.GE.AND P0, PT, R9, R0, PT ; @P0 BRA 0x1380 ; IMAD.SHL.U32 R10, R6.reuse, 0x4, RZ ; SHF.L.U64.HI R0, R6.reuse, 0x2, R7 ; IADD3 R8, R6, 0x1, RZ ; IADD3 R14, P0, R10.reuse, c[0x0][0x178], RZ ; IADD3 R12, P2, R10.reuse, c[0x0][0x188], RZ ; IADD3 R10, P3, R10, c[0x0][0x180], RZ ; SHF.R.S32.HI R47, RZ, 0x1f, R8 ; IADD3.X R15, R0.reuse, c[0x0][0x17c], RZ, P0, !PT ; IADD3.X R13, R0.reuse, c[0x0][0x18c], RZ, P2, !PT ; IADD3.X R11, R0, c[0x0][0x184], RZ, P3, !PT ; LDG.E.64 R34, [R30.64+0x10] ; LDG.E.64 R36, [R30.64+0x18] ; IMAD.MOV.U32 R39, RZ, RZ, 0x4 ; LDG.E R0, [R14.64] ; IMAD.WIDE R34, R9, 0x4, R34 ; LD.E R34, [R34.64] ; IMAD.WIDE R36, R9, 0x4, R36 ; LD.E R37, [R36.64] ; IMAD.WIDE R38, R34, R39, c[0x0][0x178] ; LDG.E R39, [R38.64] ; IMAD.IADD R0, R0, 0x1, R37 ; YIELD ; BSSY B2, 0x1320 ; ISETP.NE.AND P0, PT, R39, R0, PT ; @P0 BRA 0x1310 ; SHF.R.S32.HI R35, RZ, 0x1f, R34 ; IMAD.SHL.U32 R46, R34, 0x4, RZ ; SHF.L.U64.HI R48, R34, 0x2, R35 ; IADD3 R34, P0, R46, c[0x0][0x180], RZ ; IADD3.X R35, R48, c[0x0][0x184], RZ, P0, !PT ; LDG.E R52, [R34.64] ; ISETP.NE.AND P0, PT, R52, RZ, PT ; @!P0 BRA 0x1310 ; LDG.E R36, [R10.64] ; I2F.F64 R52, R52 ; IMAD.MOV.U32 R32, RZ, RZ, 0x1 ; BSSY B3, 0x1280 ; MUFU.RCP64H R33, R53 ; DFMA R34, -R52, R32, 1 ; DFMA R34, R34, R34, R34 ; DFMA R32, R32, R34, R32 ; DFMA R38, -R52, R32, 1 ; DFMA R38, R32, R38, R32 ; I2F.F64 R36, R36 ; DMUL R32, R36, R38 ; FSETP.GEU.AND P2, PT, |R37|, 6.5827683646048100446e-37, PT ; DFMA R34, -R52, R32, R36 ; DFMA R32, R38, R34, R32 ; FFMA R0, RZ, R53, R33 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P2, 0x1270 ; MOV R0, 0x1250 ; CALL.REL.NOINC 0x1550 ; IMAD.MOV.U32 R32, RZ, RZ, R40 ; IMAD.MOV.U32 R33, RZ, RZ, R41 ; BSYNC B3 ; IADD3 R36, P0, R46, c[0x0][0x188], RZ ; IADD3.X R37, R48, c[0x0][0x18c], RZ, P0, !PT ; LDG.E R36, [R36.64] ; FADD R0, R36, 1 ; F2F.F64.F32 R34, R0 ; DMUL R34, R34, R32 ; F2F.F32.F64 R35, R34 ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R12.64], R35 ; LDG.E.64 R32, [R30.64+0x8] ; BSYNC B2 ; LEA R34, P0, R8, R32, 0x2 ; LEA.HI.X R35, R8, R33, R47, 0x2, P0 ; LD.E R34, [R34.64] ; IADD3 R9, R9, 0x1, RZ ; ISETP.GE.AND P0, PT, R9, R34, PT ; @!P0 BRA 0xfa0 ; BSYNC B1 ; LDS R9, [RZ] ; ISETP.NE.AND P0, PT, R6, R9, PT ; @!P0 BRA 0x1450 ; IMAD.SHL.U32 R0, R6.reuse, 0x4, RZ ; SHF.L.U64.HI R7, R6, 0x2, R7 ; IADD3 R8, P0, R0, c[0x0][0x188], RZ ; IADD3.X R9, R7, c[0x0][0x18c], RZ, P0, !PT ; LDG.E R8, [R8.64] ; IADD3 R6, P0, R0, c[0x0][0x1a8], RZ ; IADD3.X R7, R7, c[0x0][0x1ac], RZ, P0, !PT ; FMUL R11, R8, 0.5 ; RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64], R11 ; BSYNC B0 ; @!P1 LDS R0, [0x10] ; WARPSYNC 0xffffffff ; @!P1 IADD3 R0, R0, -0x1, RZ ; @!P1 STS [0x10], R0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDS R6, [0x10] ; ISETP.GT.AND P0, PT, R6, RZ, PT ; @P0 BRA 0xd10 ; LDG.E R6, [R30.64] ; LDS R0, [RZ] ; IADD3 R7, R6, -0x1, RZ ; ISETP.GE.AND P0, PT, R0, R7, PT ; @P0 CALL.REL.NOINC 0x1540 ; BRA 0x1c0 ; EXIT ; FSETP.GEU.AND P0, PT, |R53|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R34, RZ, RZ, R52.reuse ; LOP3.LUT R32, R53, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R35, RZ, RZ, R53 ; FSETP.GEU.AND P3, PT, |R37|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R38, RZ, RZ, 0x1 ; LOP3.LUT R33, R32, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R32, RZ, RZ, R52 ; LOP3.LUT R49, R37, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R50, RZ, RZ, 0x1ca00000 ; LOP3.LUT R52, R53, 0x7ff00000, RZ, 0xc0, !PT ; BSSY B4, 0x1b00 ; @!P0 DMUL R32, R34, 8.98846567431157953865e+307 ; ISETP.GE.U32.AND P2, PT, R49, R52, PT ; @!P3 LOP3.LUT R40, R35, 0x7ff00000, RZ, 0xc0, !PT ; MUFU.RCP64H R39, R33 ; @!P3 ISETP.GE.U32.AND P4, PT, R49, R40, PT ; @!P3 IMAD.MOV.U32 R40, RZ, RZ, RZ ; @!P0 LOP3.LUT R52, R33, 0x7ff00000, RZ, 0xc0, !PT ; @!P3 SEL R41, R50, 0x63400000, !P4 ; @!P3 LOP3.LUT R41, R41, 0x80000000, R37, 0xf8, !PT ; @!P3 LOP3.LUT R41, R41, 0x100000, RZ, 0xfc, !PT ; DFMA R42, R38, -R32, 1 ; DFMA R42, R42, R42, R42 ; DFMA R42, R38, R42, R38 ; SEL R39, R50, 0x63400000, !P2 ; IMAD.MOV.U32 R38, RZ, RZ, R36 ; LOP3.LUT R39, R39, 0x800fffff, R37, 0xf8, !PT ; @!P3 DFMA R38, R38, 2, -R40 ; DFMA R40, R42, -R32, 1 ; DFMA R40, R42, R40, R42 ; DMUL R42, R40, R38 ; DFMA R44, R42, -R32, R38 ; DFMA R44, R40, R44, R42 ; IMAD.MOV.U32 R43, RZ, RZ, R49 ; @!P3 LOP3.LUT R43, R39, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R40, R43, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R40, 0x7feffffe, PT ; IADD3 R40, R52, -0x1, RZ ; ISETP.GT.U32.OR P0, PT, R40, 0x7feffffe, P0 ; @P0 BRA 0x19a0 ; LOP3.LUT R40, R35, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R49.reuse, R40, PT ; IMAD.IADD R36, R49, 0x1, -R40 ; SEL R37, R50, 0x63400000, !P0 ; IMNMX R36, R36, -0x46a00000, !PT ; IMNMX R36, R36, 0x46a00000, PT ; IMAD.IADD R42, R36, 0x1, -R37 ; IMAD.MOV.U32 R36, RZ, RZ, RZ ; IADD3 R37, R42, 0x7fe00000, RZ ; DMUL R40, R44, R36 ; FSETP.GTU.AND P0, PT, |R41|, 1.469367938527859385e-39, PT ; @P0 BRA 0x1af0 ; DFMA R32, R44, -R32, R38 ; IMAD.MOV.U32 R36, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R33.reuse, RZ, PT ; LOP3.LUT R35, R33, 0x80000000, R35, 0x48, !PT ; LOP3.LUT R37, R35, R37, RZ, 0xfc, !PT ; @!P0 BRA 0x1af0 ; IMAD.MOV R33, RZ, RZ, -R42 ; DMUL.RP R36, R44, R36 ; IMAD.MOV.U32 R32, RZ, RZ, RZ ; DFMA R32, R40, -R32, R44 ; LOP3.LUT R35, R37, R35, RZ, 0x3c, !PT ; IADD3 R32, -R42, -0x43300000, RZ ; FSETP.NEU.AND P0, PT, |R33|, R32, PT ; FSEL R40, R36, R40, !P0 ; FSEL R41, R35, R41, !P0 ; BRA 0x1af0 ; DSETP.NAN.AND P0, PT, R36, R36, PT ; @P0 BRA 0x1ad0 ; DSETP.NAN.AND P0, PT, R34, R34, PT ; @P0 BRA 0x1aa0 ; ISETP.NE.AND P0, PT, R43, R52, PT ; IMAD.MOV.U32 R40, RZ, RZ, 0x0 ; IMAD.MOV.U32 R41, RZ, RZ, -0x80000 ; @!P0 BRA 0x1af0 ; ISETP.NE.AND P0, PT, R43, 0x7ff00000, PT ; LOP3.LUT R41, R37, 0x80000000, R35, 0x48, !PT ; ISETP.EQ.OR P0, PT, R52, RZ, !P0 ; @P0 LOP3.LUT R32, R41, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R40, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R40, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R41, RZ, RZ, R32 ; BRA 0x1af0 ; LOP3.LUT R41, R35, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R40, RZ, RZ, R34 ; BRA 0x1af0 ; LOP3.LUT R41, R37, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R40, RZ, RZ, R36 ; BSYNC B4 ; IMAD.MOV.U32 R32, RZ, RZ, R0 ; IMAD.MOV.U32 R33, RZ, RZ, 0x0 ; RET.REL.NODEC R32 0x0 ; BRA 0x1b30; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z9cal_deltaP5GraphPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; LDG.E.64 R2, [R4.64+0x8] ; S2R R0, SR_TID.X ; IMAD.WIDE R2, R0, 0x4, R2 ; LDG.E R8, [R2.64+0x4] ; LDG.E R7, [R2.64] ; BSSY B2, 0x890 ; IMAD.MOV.U32 R6, RZ, RZ, 0x7fffffff ; ISETP.GE.AND P0, PT, R7, R8, PT ; @P0 BRA 0x880 ; LDG.E.64 R2, [R4.64+0x18] ; IADD3 R9, R7, 0x1, RZ ; BSSY B1, 0x7c0 ; LOP3.LUT R11, RZ, R7, RZ, 0x33, !PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x7fffffff ; IMNMX R8, R8, R9, !PT ; IMAD.IADD R11, R8.reuse, 0x1, R11 ; IMAD.IADD R9, R8, 0x1, -R7 ; ISETP.GE.U32.AND P0, PT, R11, 0x3, PT ; LOP3.LUT R8, R9, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0x7b0 ; IMAD.IADD R9, R9, 0x1, -R8 ; BSSY B0, 0x6b0 ; IMAD.WIDE R4, R7, 0x4, R2 ; ISETP.GT.AND P0, PT, R9, RZ, PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x7fffffff ; IADD3 R4, P1, R4, 0x8, RZ ; IMAD.X R5, RZ, RZ, R5, P1 ; @!P0 BRA 0x6a0 ; ISETP.GT.AND P1, PT, R9, 0xc, PT ; BSSY B3, 0x4c0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x4b0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E R21, [R4.64+-0x8] ; LDG.E R22, [R4.64+-0x4] ; LDG.E R24, [R4.64] ; LDG.E R26, [R4.64+0x4] ; LDG.E R28, [R4.64+0x8] ; LDG.E R20, [R4.64+0xc] ; LDG.E R19, [R4.64+0x10] ; LDG.E R18, [R4.64+0x14] ; LDG.E R17, [R4.64+0x18] ; LDG.E R16, [R4.64+0x1c] ; LDG.E R15, [R4.64+0x20] ; LDG.E R14, [R4.64+0x24] ; LDG.E R13, [R4.64+0x28] ; LDG.E R11, [R4.64+0x2c] ; LDG.E R12, [R4.64+0x30] ; LDG.E R10, [R4.64+0x34] ; IADD3 R9, R9, -0x10, RZ ; IADD3 R7, R7, 0x10, RZ ; ISETP.GT.AND P1, PT, R9, 0xc, PT ; IADD3 R4, P2, R4, 0x40, RZ ; IMAD.X R5, RZ, RZ, R5, P2 ; IMNMX R21, R21, R6, PT ; IMNMX R21, R21, R22, PT ; IMNMX R21, R21, R24, PT ; IMNMX R21, R21, R26, PT ; IMNMX R21, R21, R28, PT ; IMNMX R20, R21, R20, PT ; IMNMX R19, R20, R19, PT ; IMNMX R18, R19, R18, PT ; IMNMX R17, R18, R17, PT ; IMNMX R16, R17, R16, PT ; IMNMX R15, R16, R15, PT ; IMNMX R14, R15, R14, PT ; IMNMX R14, R14, R13, PT ; IMNMX R11, R14, R11, PT ; IMNMX R11, R11, R12, PT ; IMNMX R6, R11, R10, PT ; @P1 BRA 0x250 ; BSYNC B3 ; ISETP.GT.AND P1, PT, R9, 0x4, PT ; BSSY B3, 0x670 ; @!P1 BRA 0x660 ; LDG.E R11, [R4.64+-0x8] ; LDG.E R10, [R4.64+-0x4] ; LDG.E R13, [R4.64] ; LDG.E R15, [R4.64+0x4] ; LDG.E R17, [R4.64+0x8] ; LDG.E R19, [R4.64+0xc] ; LDG.E R21, [R4.64+0x10] ; LDG.E R23, [R4.64+0x14] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R7, R7, 0x8, RZ ; IADD3 R9, R9, -0x8, RZ ; IMNMX R11, R6, R11, PT ; IMNMX R10, R11, R10, PT ; IADD3 R11, P1, R4, 0x20, RZ ; IMNMX R10, R10, R13, PT ; IMAD.X R12, RZ, RZ, R5, P1 ; IMNMX R10, R10, R15, PT ; IMAD.MOV.U32 R4, RZ, RZ, R11 ; IMAD.MOV.U32 R5, RZ, RZ, R12 ; IMNMX R10, R10, R17, PT ; IMNMX R10, R10, R19, PT ; IMNMX R10, R10, R21, PT ; IMNMX R6, R10, R23, PT ; BSYNC B3 ; ISETP.NE.OR P0, PT, R9, RZ, P0 ; @!P0 BREAK B0 ; @!P0 BRA 0x7b0 ; BSYNC B0 ; LDG.E R11, [R4.64+-0x8] ; LDG.E R10, [R4.64+-0x4] ; LDG.E R13, [R4.64] ; LDG.E R15, [R4.64+0x4] ; IADD3 R9, R9, -0x4, RZ ; IADD3 R7, R7, 0x4, RZ ; ISETP.NE.AND P0, PT, R9, RZ, PT ; IMNMX R11, R11, R6, PT ; IMNMX R10, R11, R10, PT ; IADD3 R11, P1, R4, 0x10, RZ ; IMNMX R10, R10, R13, PT ; IMAD.X R12, RZ, RZ, R5, P1 ; IMNMX R6, R10, R15, PT ; IMAD.MOV.U32 R4, RZ, RZ, R11 ; IMAD.MOV.U32 R5, RZ, RZ, R12 ; @P0 BRA 0x6b0 ; BSYNC B1 ; ISETP.NE.AND P0, PT, R8, RZ, PT ; @!P0 BRA 0x880 ; IMAD.WIDE R2, R7, 0x4, R2 ; IMAD.MOV.U32 R5, RZ, RZ, R3 ; IMAD.MOV.U32 R3, RZ, RZ, R5 ; LDG.E R3, [R2.64] ; IADD3 R8, R8, -0x1, RZ ; ISETP.NE.AND P0, PT, R8, RZ, PT ; IADD3 R2, P1, R2, 0x4, RZ ; IMAD.X R5, RZ, RZ, R5, P1 ; IMNMX R6, R3, R6, PT ; @P0 BRA 0x800 ; BSYNC B2 ; WARPSYNC 0xffffffff ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; STG.E [R2.64], R6 ; EXIT ; BRA 0x8e0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000e8971_00000000-6_81472862b0a7f59b878780cb8929a66c2f55a376.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .globl _Z19compareTwoEdgePairs9edgepairsS_ .type _Z19compareTwoEdgePairs9edgepairsS_, @function _Z19compareTwoEdgePairs9edgepairsS_: .LFB10859: .cfi_startproc endbr64 movq %rdi, -16(%rsp) movq %rdx, -32(%rsp) cmpl %edx, %edi je .L2 setl %al ret .L2: movl -12(%rsp), %ecx movl -28(%rsp), %edx movl $1, %eax cmpl %edx, %ecx je .L1 setl %al .L1: ret .cfi_endproc .LFE10859: .size _Z19compareTwoEdgePairs9edgepairsS_, .-_Z19compareTwoEdgePairs9edgepairsS_ .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB10876: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE10876: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z35__device_stub__Z9cal_deltaP5GraphPiP5GraphPi .type _Z35__device_stub__Z9cal_deltaP5GraphPiP5GraphPi, @function _Z35__device_stub__Z9cal_deltaP5GraphPiP5GraphPi: .LFB10898: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 104(%rsp), %rax subq %fs:40, %rax jne .L12 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z9cal_deltaP5GraphPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE10898: .size _Z35__device_stub__Z9cal_deltaP5GraphPiP5GraphPi, .-_Z35__device_stub__Z9cal_deltaP5GraphPiP5GraphPi .globl _Z9cal_deltaP5GraphPi .type _Z9cal_deltaP5GraphPi, @function _Z9cal_deltaP5GraphPi: .LFB10899: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z9cal_deltaP5GraphPiP5GraphPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE10899: .size _Z9cal_deltaP5GraphPi, .-_Z9cal_deltaP5GraphPi .globl _Z58__device_stub__Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_P5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .type _Z58__device_stub__Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_P5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_, @function _Z58__device_stub__Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_P5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_: .LFB10900: .cfi_startproc endbr64 subq $264, %rsp .cfi_def_cfa_offset 272 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movq %r9, 48(%rsp) movq 272(%rsp), %rax movq %rax, 40(%rsp) movq 280(%rsp), %rax movq %rax, 32(%rsp) movq 288(%rsp), %rax movq %rax, 24(%rsp) movq 296(%rsp), %rax movq %rax, 16(%rsp) movq 304(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 248(%rsp) xorl %eax, %eax leaq 88(%rsp), %rax movq %rax, 160(%rsp) leaq 80(%rsp), %rax movq %rax, 168(%rsp) leaq 72(%rsp), %rax movq %rax, 176(%rsp) leaq 64(%rsp), %rax movq %rax, 184(%rsp) leaq 56(%rsp), %rax movq %rax, 192(%rsp) leaq 48(%rsp), %rax movq %rax, 200(%rsp) leaq 40(%rsp), %rax movq %rax, 208(%rsp) leaq 32(%rsp), %rax movq %rax, 216(%rsp) leaq 24(%rsp), %rax movq %rax, 224(%rsp) leaq 16(%rsp), %rax movq %rax, 232(%rsp) leaq 8(%rsp), %rax movq %rax, 240(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) movl $1, 120(%rsp) movl $1, 124(%rsp) movl $1, 128(%rsp) movl $1, 132(%rsp) leaq 104(%rsp), %rcx leaq 96(%rsp), %rdx leaq 124(%rsp), %rsi leaq 112(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L19 .L15: movq 248(%rsp), %rax subq %fs:40, %rax jne .L20 addq $264, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state pushq 104(%rsp) .cfi_def_cfa_offset 280 pushq 104(%rsp) .cfi_def_cfa_offset 288 leaq 176(%rsp), %r9 movq 140(%rsp), %rcx movl 148(%rsp), %r8d movq 128(%rsp), %rsi movl 136(%rsp), %edx leaq _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 272 jmp .L15 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE10900: .size _Z58__device_stub__Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_P5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_, .-_Z58__device_stub__Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_P5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .globl _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .type _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_, @function _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_: .LFB10901: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 pushq 56(%rsp) .cfi_def_cfa_offset 32 pushq 56(%rsp) .cfi_def_cfa_offset 40 pushq 56(%rsp) .cfi_def_cfa_offset 48 pushq 56(%rsp) .cfi_def_cfa_offset 56 pushq 56(%rsp) .cfi_def_cfa_offset 64 call _Z58__device_stub__Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_P5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ addq $56, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE10901: .size _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_, .-_Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .globl _Z3funP5Graph .type _Z3funP5Graph, @function _Z3funP5Graph: .LFB10863: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $168, %rsp .cfi_def_cfa_offset 224 movq %rdi, %r13 movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax movq %rsp, %rdi movl $32, %esi call cudaMalloc@PLT movl 0(%r13), %r12d movl 4(%r13), %ebx movl $1, %ecx movl $32, %edx movq %r13, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT leal 1(%r12), %ebp movslq %ebp, %rbp salq $2, %rbp leaq 8(%rsp), %r14 movq %rbp, %rsi movq %r14, %rdi call cudaMalloc@PLT movq 8(%r13), %rsi movl $1, %ecx movq %rbp, %rdx movq 8(%rsp), %rdi call cudaMemcpy@PLT movq (%rsp), %rax leaq 8(%rax), %rdi movl $1, %ecx movl $8, %edx movq %r14, %rsi call cudaMemcpy@PLT addl %ebx, %ebx leal 1(%rbx), %r14d movslq %r14d, %r14 salq $2, %r14 leaq 16(%rsp), %r15 movq %r14, %rsi movq %r15, %rdi call cudaMalloc@PLT movq 16(%r13), %rsi movl $1, %ecx movq %r14, %rdx movq 16(%rsp), %rdi call cudaMemcpy@PLT movq (%rsp), %rax leaq 16(%rax), %rdi movl $1, %ecx movl $8, %edx movq %r15, %rsi call cudaMemcpy@PLT movslq %ebx, %rbx salq $2, %rbx leaq 24(%rsp), %r14 movq %rbx, %rsi movq %r14, %rdi call cudaMalloc@PLT movq 24(%r13), %rsi movl $1, %ecx movq %rbx, %rdx movq 24(%rsp), %rdi call cudaMemcpy@PLT movq (%rsp), %rax leaq 24(%rax), %rdi movl $1, %ecx movl $8, %edx movq %r14, %rsi call cudaMemcpy@PLT movslq %r12d, %rbx movabsq $2305843009213693950, %rax cmpq %rbx, %rax jb .L24 subq $4, %rbp movq %rbp, %rdi call _Znam@PLT movq %rax, %r13 movq %rax, %rdx movq %rbx, %rax subq $1, %rax js .L26 .L28: movl $0x00000000, (%rdx) addq $4, %rdx subq $1, %rax jns .L28 .L26: leaq 32(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT movl $1, %ecx movq %rbp, %rdx movq %r13, %rsi movq 32(%rsp), %rdi call cudaMemcpy@PLT leaq 40(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq 48(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq 56(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq 64(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq 72(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq 80(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq 88(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq 96(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT leaq 104(%rsp), %rdi call cudaEventCreate@PLT leaq 112(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 104(%rsp), %rdi call cudaEventRecord@PLT leaq 120(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT movl %r12d, 140(%rsp) movl $1, 144(%rsp) movl $1, 148(%rsp) movl $1, 128(%rsp) movl $1, 132(%rsp) movl $1, 136(%rsp) movl $0, %r9d movl $0, %r8d movq 140(%rsp), %rdx movl $1, %ecx movq 128(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L39 .L29: call cudaDeviceSynchronize@PLT movl %r12d, 140(%rsp) movl $1, 144(%rsp) movl $1, 148(%rsp) movl $1, 128(%rsp) movl $1, 132(%rsp) movl $1, 136(%rsp) movl $0, %r9d movl $0, %r8d movq 140(%rsp), %rdx movl $1, %ecx movq 128(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L40 .L30: call cudaDeviceSynchronize@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rip), %rdx movq 240(%rdx,%rax), %rbx testq %rbx, %rbx je .L41 cmpb $0, 56(%rbx) je .L33 movzbl 67(%rbx), %esi .L34: movsbl %sil, %esi leaq _ZSt4cout(%rip), %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $0, %esi movq 112(%rsp), %rdi call cudaEventRecord@PLT movq 112(%rsp), %rdi call cudaEventSynchronize@PLT movq 112(%rsp), %rdx movq 104(%rsp), %rsi leaq device_time_taken(%rip), %rdi call cudaEventElapsedTime@PLT movl $2, %ecx movq %rbp, %rdx movq 32(%rsp), %rsi movq %r13, %rdi call cudaMemcpy@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq 48(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rdi call cudaFree@PLT movq 64(%rsp), %rdi call cudaFree@PLT movq 72(%rsp), %rdi call cudaFree@PLT movq 80(%rsp), %rdi call cudaFree@PLT movq 88(%rsp), %rdi call cudaFree@PLT movq 96(%rsp), %rdi call cudaFree@PLT movq 120(%rsp), %rdi call cudaFree@PLT movq 152(%rsp), %rax subq %fs:40, %rax jne .L42 movq %r13, %rax addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L24: .cfi_restore_state movq 152(%rsp), %rax subq %fs:40, %rax je .L27 call __stack_chk_fail@PLT .L27: call __cxa_throw_bad_array_new_length@PLT .L39: movq 120(%rsp), %rsi movq (%rsp), %rdi call _Z35__device_stub__Z9cal_deltaP5GraphPiP5GraphPi jmp .L29 .L40: subq $8, %rsp .cfi_def_cfa_offset 232 pushq 128(%rsp) .cfi_def_cfa_offset 240 pushq 48(%rsp) .cfi_def_cfa_offset 248 pushq 120(%rsp) .cfi_def_cfa_offset 256 pushq 120(%rsp) .cfi_def_cfa_offset 264 pushq 120(%rsp) .cfi_def_cfa_offset 272 movq 120(%rsp), %r9 movq 112(%rsp), %r8 movq 104(%rsp), %rcx movq 96(%rsp), %rdx movq 88(%rsp), %rsi movq 48(%rsp), %rdi call _Z58__device_stub__Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_P5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ addq $48, %rsp .cfi_def_cfa_offset 224 jmp .L30 .L41: movq 152(%rsp), %rax subq %fs:40, %rax jne .L43 call _ZSt16__throw_bad_castv@PLT .L43: call __stack_chk_fail@PLT .L33: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) movl %eax, %esi jmp .L34 .L42: call __stack_chk_fail@PLT .cfi_endproc .LFE10863: .size _Z3funP5Graph, .-_Z3funP5Graph .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "_Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_" .section .rodata.str1.1,"aMS",@progbits,1 .LC2: .string "_Z9cal_deltaP5GraphPi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB10903: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z9cal_deltaP5GraphPi(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE10903: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .text._ZNSt6vectorI9edgepairsSaIS0_EED2Ev,"axG",@progbits,_ZNSt6vectorI9edgepairsSaIS0_EED5Ev,comdat .align 2 .weak _ZNSt6vectorI9edgepairsSaIS0_EED2Ev .type _ZNSt6vectorI9edgepairsSaIS0_EED2Ev, @function _ZNSt6vectorI9edgepairsSaIS0_EED2Ev: .LFB11594: .cfi_startproc endbr64 movq (%rdi), %rax testq %rax, %rax je .L49 subq $8, %rsp .cfi_def_cfa_offset 16 movq 16(%rdi), %rsi subq %rax, %rsi movq %rax, %rdi call _ZdlPvm@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .L49: ret .cfi_endproc .LFE11594: .size _ZNSt6vectorI9edgepairsSaIS0_EED2Ev, .-_ZNSt6vectorI9edgepairsSaIS0_EED2Ev .weak _ZNSt6vectorI9edgepairsSaIS0_EED1Ev .set _ZNSt6vectorI9edgepairsSaIS0_EED1Ev,_ZNSt6vectorI9edgepairsSaIS0_EED2Ev .section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat .align 2 .weak _ZNSt6vectorIiSaIiEED2Ev .type _ZNSt6vectorIiSaIiEED2Ev, @function _ZNSt6vectorIiSaIiEED2Ev: .LFB11610: .cfi_startproc endbr64 movq (%rdi), %rax testq %rax, %rax je .L55 subq $8, %rsp .cfi_def_cfa_offset 16 movq 16(%rdi), %rsi subq %rax, %rsi movq %rax, %rdi call _ZdlPvm@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .L55: ret .cfi_endproc .LFE11610: .size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev .weak _ZNSt6vectorIiSaIiEED1Ev .set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev .section .rodata._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.str1.1,"aMS",@progbits,1 .LC3: .string "vector::_M_realloc_insert" .section .text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat .align 2 .weak _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_ .type _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_: .LFB12065: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $24, %rsp .cfi_def_cfa_offset 80 movq %rsi, (%rsp) movq %rdx, 8(%rsp) movq 8(%rdi), %rbp movq (%rdi), %r13 movq %rbp, %rax subq %r13, %rax sarq $2, %rax movabsq $2305843009213693951, %rdx cmpq %rdx, %rax je .L75 movq %rdi, %rbx cmpq %r13, %rbp movl $1, %edx cmovne %rax, %rdx addq %rdx, %rax jc .L61 movabsq $2305843009213693951, %r14 cmpq %r14, %rax cmovbe %rax, %r14 movq (%rsp), %r15 subq %r13, %r15 movl $0, %r12d testq %rax, %rax je .L62 jmp .L69 .L75: leaq .LC3(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .L76: movq %r15, %rdx movq %r13, %rsi movq %r12, %rdi call memmove@PLT leaq 4(%r12,%r15), %r15 movq (%rsp), %rax subq %rax, %rbp testq %rbp, %rbp jg .L64 addq %rbp, %r15 movq 16(%rbx), %rsi subq %r13, %rsi jmp .L68 .L61: movq (%rsp), %r15 subq %r13, %r15 movabsq $2305843009213693951, %r14 .L69: leaq 0(,%r14,4), %rdi call _Znwm@PLT movq %rax, %r12 .L62: movq 8(%rsp), %rax movl (%rax), %eax movl %eax, (%r12,%r15) testq %r15, %r15 jg .L76 leaq 4(%r12,%r15), %r15 movq (%rsp), %rax subq %rax, %rbp testq %rbp, %rbp jle .L66 .L64: movq %rbp, %rdx movq (%rsp), %rsi movq %r15, %rdi call memcpy@PLT .L66: addq %rbp, %r15 testq %r13, %r13 je .L67 movq 16(%rbx), %rsi subq %r13, %rsi .L68: movq %r13, %rdi call _ZdlPvm@PLT .L67: movq %r12, (%rbx) movq %r15, 8(%rbx) leaq (%r12,%r14,4), %rax movq %rax, 16(%rbx) addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE12065: .size _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_ .section .text._ZSt25__unguarded_linear_insertIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops14_Val_comp_iterIPFbS2_S2_EEEEvT_T0_,"axG",@progbits,_ZSt25__unguarded_linear_insertIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops14_Val_comp_iterIPFbS2_S2_EEEEvT_T0_,comdat .weak _ZSt25__unguarded_linear_insertIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops14_Val_comp_iterIPFbS2_S2_EEEEvT_T0_ .type _ZSt25__unguarded_linear_insertIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops14_Val_comp_iterIPFbS2_S2_EEEEvT_T0_, @function _ZSt25__unguarded_linear_insertIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops14_Val_comp_iterIPFbS2_S2_EEEEvT_T0_: .LFB12585: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $24, %rsp .cfi_def_cfa_offset 48 movq %rsi, %rbp movq (%rdi), %rax movq %rax, 4(%rsp) movl 8(%rdi), %eax movl %eax, 12(%rsp) leaq -12(%rdi), %rbx jmp .L78 .L79: movq (%rbx), %rax movq %rax, 12(%rbx) movl 8(%rbx), %eax movl %eax, 20(%rbx) subq $12, %rbx .L78: movq (%rbx), %rdx movl 8(%rbx), %ecx movq 4(%rsp), %rdi movl 12(%rsp), %esi call *%rbp testb %al, %al jne .L79 movq 4(%rsp), %rax movq %rax, 12(%rbx) movl 12(%rsp), %eax movl %eax, 20(%rbx) addq $24, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE12585: .size _ZSt25__unguarded_linear_insertIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops14_Val_comp_iterIPFbS2_S2_EEEEvT_T0_, .-_ZSt25__unguarded_linear_insertIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops14_Val_comp_iterIPFbS2_S2_EEEEvT_T0_ .section .text._ZSt16__insertion_sortIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_,"axG",@progbits,_ZSt16__insertion_sortIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_,comdat .weak _ZSt16__insertion_sortIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_ .type _ZSt16__insertion_sortIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_, @function _ZSt16__insertion_sortIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_: .LFB12464: .cfi_startproc endbr64 cmpq %rsi, %rdi je .L90 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $24, %rsp .cfi_def_cfa_offset 80 movq %rdi, %rbp movq %rsi, %r13 movq %rdx, %r12 leaq 12(%rdi), %rbx cmpq %rbx, %rsi jne .L87 .L81: addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L84: .cfi_restore_state je .L93 .L85: movl %r15d, 0(%rbp) movl %r14d, 4(%rbp) movl 12(%rsp), %eax movl %eax, 8(%rbp) .L86: addq $12, %rbx cmpq %rbx, %r13 je .L81 .L87: movq %rbx, (%rsp) movq 0(%rbp), %rdx movl 8(%rbp), %ecx movq (%rbx), %rdi movl 8(%rbx), %esi call *%r12 testb %al, %al je .L83 movl (%rbx), %r15d movl 4(%rbx), %r14d movl 8(%rbx), %ecx movl %ecx, 12(%rsp) movq %rbx, %rdx subq %rbp, %rdx cmpq $12, %rdx jle .L84 movl $12, %edi subq %rdx, %rdi movq (%rsp), %rax addq %rdi, %rax movq %rax, %rdi movq %rbp, %rsi call memmove@PLT jmp .L85 .L93: movq 0(%rbp), %rax movq (%rsp), %rcx movq %rax, (%rcx) movl 8(%rbp), %eax movl %eax, 8(%rcx) jmp .L85 .L83: movq %r12, %rsi movq %rbx, %rdi call _ZSt25__unguarded_linear_insertIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops14_Val_comp_iterIPFbS2_S2_EEEEvT_T0_ jmp .L86 .L90: .cfi_def_cfa_offset 8 .cfi_restore 3 .cfi_restore 6 .cfi_restore 12 .cfi_restore 13 .cfi_restore 14 .cfi_restore 15 ret .cfi_endproc .LFE12464: .size _ZSt16__insertion_sortIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_, .-_ZSt16__insertion_sortIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_ .section .text._ZSt13__adjust_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElS2_NS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_T0_SE_T1_T2_,"axG",@progbits,_ZSt13__adjust_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElS2_NS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_T0_SE_T1_T2_,comdat .weak _ZSt13__adjust_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElS2_NS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_T0_SE_T1_T2_ .type _ZSt13__adjust_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElS2_NS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_T0_SE_T1_T2_, @function _ZSt13__adjust_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElS2_NS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_T0_SE_T1_T2_: .LFB12733: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %rdi, %rbp movq %rsi, %r14 movq %rdx, 8(%rsp) movq %r9, %r13 movq %rcx, 16(%rsp) movl %r8d, 24(%rsp) leaq -1(%rdx), %rax movq %rax, %r15 shrq $63, %r15 addq %rax, %r15 sarq %r15 cmpq %r15, %rsi jge .L95 movq %rsi, %r12 jmp .L97 .L103: movq %rbx, %r12 .L97: leaq 1(%r12), %rax leaq (%rax,%rax), %rbx leaq -3(%rbx,%rbx,2), %rdx leaq 0(%rbp,%rdx,4), %rdx movq (%rdx), %r8 movl 8(%rdx), %ecx leaq (%rbx,%rax,4), %rax leaq 0(%rbp,%rax,4), %rax movq (%rax), %rdi movl 8(%rax), %esi movq %r8, %rdx call *%r13 cmpb $1, %al adcq $-1, %rbx leaq (%r12,%r12,2), %rax leaq 0(%rbp,%rax,4), %rax leaq (%rbx,%rbx,2), %rdx leaq 0(%rbp,%rdx,4), %rdx movq (%rdx), %rcx movq %rcx, (%rax) movl 8(%rdx), %edx movl %edx, 8(%rax) cmpq %r15, %rbx jl .L103 testb $1, 8(%rsp) jne .L98 .L101: movq 8(%rsp), %rdx subq $2, %rdx movq %rdx, %rax shrq $63, %rax addq %rdx, %rax sarq %rax cmpq %rbx, %rax je .L109 .L98: movq 16(%rsp), %rax movq %rax, 36(%rsp) movl 24(%rsp), %eax movl %eax, 44(%rsp) leaq -1(%rbx), %rax movq %rax, %r12 shrq $63, %r12 addq %rax, %r12 sarq %r12 cmpq %r14, %rbx jg .L100 jmp .L99 .L105: movq %r14, %rbx jmp .L101 .L109: leaq 1(%rbx,%rbx), %rax leaq (%rbx,%rbx,2), %rdx leaq 0(%rbp,%rdx,4), %rdx leaq (%rax,%rax,2), %rcx leaq 0(%rbp,%rcx,4), %rcx movq (%rcx), %rsi movq %rsi, (%rdx) movl 8(%rcx), %ecx movl %ecx, 8(%rdx) movq %rax, %rbx jmp .L98 .L104: movq %rax, %r12 .L100: leaq (%r12,%r12,2), %rax leaq 0(%rbp,%rax,4), %r15 movl 44(%rsp), %ecx movq (%r15), %rdi movl 8(%r15), %esi movq 36(%rsp), %rdx call *%r13 testb %al, %al je .L99 leaq (%rbx,%rbx,2), %rax leaq 0(%rbp,%rax,4), %rax movq (%r15), %rdx movq %rdx, (%rax) movl 8(%r15), %edx movl %edx, 8(%rax) leaq -1(%r12), %rdx movq %rdx, %rax shrq $63, %rax addq %rdx, %rax sarq %rax movq %r12, %rbx cmpq %r12, %r14 jl .L104 .L99: leaq (%rbx,%rbx,2), %rax leaq 0(%rbp,%rax,4), %rax movq 36(%rsp), %rdx movq %rdx, (%rax) movl 44(%rsp), %edx movl %edx, 8(%rax) addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L95: .cfi_restore_state testb $1, 8(%rsp) je .L105 movq 16(%rsp), %rax movq %rax, 36(%rsp) movl 24(%rsp), %eax movl %eax, 44(%rsp) movq %r14, %rbx jmp .L99 .cfi_endproc .LFE12733: .size _ZSt13__adjust_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElS2_NS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_T0_SE_T1_T2_, .-_ZSt13__adjust_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElS2_NS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_T0_SE_T1_T2_ .section .text._ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_,"axG",@progbits,_ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_,comdat .weak _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_ .type _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_, @function _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_: .LFB12292: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $40, %rsp .cfi_def_cfa_offset 96 movq %rsi, %rax movq %rdx, 8(%rsp) subq %rdi, %rax cmpq $192, %rax jle .L110 movq %rdi, %rbp movq %rcx, %r12 movq %rsi, %r15 cmpq $0, 8(%rsp) jne .L113 movq %r15, %r13 .L130: sarq $2, %rax movabsq $-6148914691236517205, %rdx imulq %rdx, %rax movq %rax, %rbx leaq -2(%rax), %rax movq %rax, %r14 shrq $63, %r14 addq %rax, %r14 sarq %r14 jmp .L117 .L114: subq $1, %r14 .L117: leaq (%r14,%r14,2), %rax movq 0(%rbp,%rax,4), %rcx movq %rcx, 20(%rsp) movl 8(%rbp,%rax,4), %r8d movl %r8d, 28(%rsp) movq %r12, %r9 movq %rbx, %rdx movq %r14, %rsi movq %rbp, %rdi call _ZSt13__adjust_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElS2_NS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_T0_SE_T1_T2_ testq %r14, %r14 jne .L114 movq %r13, %rax subq %rbp, %rax subq $12, %r13 movabsq $-6148914691236517205, %r14 cmpq $12, %rax jle .L110 .L118: movq 0(%r13), %rcx movq %rcx, 20(%rsp) movl 8(%r13), %r8d movl %r8d, 28(%rsp) movq 0(%rbp), %rax movq %rax, 0(%r13) movl 8(%rbp), %eax movl %eax, 8(%r13) movq %r13, %rbx subq %rbp, %rbx movq %rbx, %rdx sarq $2, %rdx imulq %r14, %rdx movq %r12, %r9 movl $0, %esi movq %rbp, %rdi call _ZSt13__adjust_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElS2_NS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_T0_SE_T1_T2_ subq $12, %r13 cmpq $12, %rbx jg .L118 .L110: addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L120: .cfi_restore_state movq (%r14), %rdx movl 8(%r14), %ecx movq 12(%rbp), %rdi movl 8(%rbx), %esi call *%r12 testb %al, %al je .L122 movl 0(%rbp), %ecx movl 4(%rbp), %edx movl 8(%rbp), %eax movq -12(%r15), %rsi movq %rsi, 0(%rbp) movl -4(%r15), %esi movl %esi, 8(%rbp) movl %ecx, -12(%r15) movl %edx, -8(%r15) movl %eax, -4(%r15) jmp .L121 .L122: movl 0(%rbp), %ecx movl 4(%rbp), %edx movl 8(%rbp), %eax movq 12(%rbp), %rsi movq %rsi, 0(%rbp) movl 20(%rbp), %esi movl %esi, 8(%rbp) movl %ecx, 12(%rbp) movl %edx, 16(%rbp) movl %eax, 20(%rbp) jmp .L121 .L119: movq -12(%r15), %rdx movl 8(%r14), %ecx movq 12(%rbp), %rdi movl 8(%rbx), %esi call *%r12 testb %al, %al je .L123 movl 0(%rbp), %ecx movl 4(%rbp), %edx movl 8(%rbp), %eax movq 12(%rbp), %rsi movq %rsi, 0(%rbp) movl 20(%rbp), %esi movl %esi, 8(%rbp) movl %ecx, 12(%rbp) movl %edx, 16(%rbp) movl %eax, 20(%rbp) jmp .L121 .L123: movq (%r14), %rdx movl 8(%r14), %ecx movq 0(%r13), %rdi movl 8(%r13), %esi call *%r12 testb %al, %al je .L124 movl 0(%rbp), %ecx movl 4(%rbp), %edx movl 8(%rbp), %eax movq -12(%r15), %rsi movq %rsi, 0(%rbp) movl -4(%r15), %esi movl %esi, 8(%rbp) movl %ecx, -12(%r15) movl %edx, -8(%r15) movl %eax, -4(%r15) jmp .L121 .L124: movl 0(%rbp), %ecx movl 4(%rbp), %edx movl 8(%rbp), %eax movq 0(%r13), %rsi movq %rsi, 0(%rbp) movl 8(%r13), %esi movl %esi, 8(%rbp) movl %ecx, 0(%r13) movl %edx, 4(%r13) movl %eax, 8(%r13) jmp .L121 .L138: movq %r12, %rcx movq 8(%rsp), %rdx movq %r15, %rsi movq %r13, %rdi call _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_ movq %r13, %rax subq %rbp, %rax cmpq $192, %rax jle .L110 cmpq $0, 8(%rsp) je .L130 movq %r13, %r15 .L113: subq $1, 8(%rsp) sarq $2, %rax movabsq $-6148914691236517205, %rdi imulq %rdi, %rax movq %rax, %rdx shrq $63, %rdx addq %rdx, %rax movq %rax, %rdx sarq %rdx andq $-2, %rax addq %rdx, %rax leaq 0(%rbp,%rax,4), %r13 leaq -12(%r15), %r14 leaq 12(%rbp), %rbx movq 0(%r13), %rdx movl 8(%r13), %ecx movq 12(%rbp), %rdi movl 8(%rbx), %esi call *%r12 testb %al, %al je .L119 movq -12(%r15), %rdx movl 8(%r14), %ecx movq 0(%r13), %rdi movl 8(%r13), %esi call *%r12 testb %al, %al je .L120 movl 0(%rbp), %ecx movl 4(%rbp), %edx movl 8(%rbp), %eax movq 0(%r13), %rsi movq %rsi, 0(%rbp) movl 8(%r13), %esi movl %esi, 8(%rbp) movl %ecx, 0(%r13) movl %edx, 4(%r13) movl %eax, 8(%r13) .L121: movq %r15, %r14 .L125: movq %rbx, %r13 movq 0(%rbp), %rdx movl 8(%rbp), %ecx movq (%rbx), %rdi movl 8(%rbx), %esi call *%r12 addq $12, %rbx testb %al, %al jne .L125 leaq -12(%r14), %rbx .L126: movq %rbx, %r14 movq (%rbx), %rdx movl 8(%rbx), %ecx movq 0(%rbp), %rdi movl 8(%rbp), %esi call *%r12 subq $12, %rbx testb %al, %al jne .L126 cmpq %r14, %r13 jnb .L138 movl 0(%r13), %ecx movl 4(%r13), %edx movl 8(%r13), %eax movq (%r14), %rsi movq %rsi, 0(%r13) movl 8(%r14), %esi movl %esi, 8(%r13) movl %ecx, (%r14) movl %edx, 4(%r14) movl %eax, 8(%r14) leaq 12(%r13), %rbx jmp .L125 .cfi_endproc .LFE12292: .size _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_, .-_ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_ .section .rodata.str1.1 .LC5: .string "r" .section .rodata.str1.8 .align 8 .LC6: .string "input.txt file failed to open." .section .rodata.str1.1 .LC7: .string "%d" .section .rodata.str1.8 .align 8 .LC8: .string "cannot create std::vector larger than max_size()" .align 8 .LC9: .string "Betweeness Centrality of all the nodes(vertices)\n" .section .rodata.str1.1 .LC10: .string "Node " .LC11: .string " : " .section .rodata.str1.8 .align 8 .LC12: .string "\nMaximum Betweenness Centrality = " .align 8 .LC13: .string "Vertices with Maximum Betweenness Centrality: [" .section .rodata.str1.1 .LC14: .string " , " .LC15: .string "]" .LC16: .string "Total device time taken : " .text .globl main .type main, @function main: .LFB10864: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA10864 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $120, %rsp .cfi_def_cfa_offset 176 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq 8(%rsi), %rdi leaq .LC5(%rip), %rsi .LEHB0: call fopen@PLT testq %rax, %rax je .L214 movq %rax, %r13 leaq 28(%rsp), %rdx leaq .LC7(%rip), %rbx movq %rbx, %rsi movq %rax, %rdi movl $0, %eax call __isoc23_fscanf@PLT leaq 24(%rsp), %rdx movq %rbx, %rsi movq %r13, %rdi movl $0, %eax call __isoc23_fscanf@PLT movl $32, %edi call _Znwm@PLT .LEHE0: movq %rax, %rbp movl 28(%rsp), %edi movl %edi, (%rax) movl 24(%rsp), %eax movl %eax, 4(%rbp) addl $1, %edi movslq %edi, %rdi movabsq $2305843009213693950, %rax cmpq %rdi, %rax jb .L142 salq $2, %rdi .LEHB1: call _Znam@PLT .LEHE1: jmp .L215 .L214: leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax .LEHB2: call __printf_chk@PLT .LEHE2: jmp .L141 .L215: movq %rax, 8(%rbp) movl 4(%rbp), %eax leal 1(%rax,%rax), %edi movslq %edi, %rdi movabsq $2305843009213693950, %rax cmpq %rdi, %rax jb .L216 salq $2, %rdi .LEHB3: call _Znam@PLT jmp .L217 .L142: movq 104(%rsp), %rax subq %fs:40, %rax je .L145 call __stack_chk_fail@PLT .L145: call __cxa_throw_bad_array_new_length@PLT .L195: endbr64 movq %rax, %rbx movl $32, %esi movq %rbp, %rdi call _ZdlPvm@PLT movq 104(%rsp), %rax subq %fs:40, %rax je .L187 call __stack_chk_fail@PLT .L217: movq %rax, 16(%rbp) movl 4(%rbp), %eax leal (%rax,%rax), %edi movslq %edi, %rdi movabsq $2305843009213693950, %rax cmpq %rdi, %rax jb .L218 salq $2, %rdi call _Znam@PLT jmp .L219 .L216: movq 104(%rsp), %rax subq %fs:40, %rax je .L148 call __stack_chk_fail@PLT .L148: call __cxa_throw_bad_array_new_length@PLT .LEHE3: .L219: movq %rax, 24(%rbp) movl 24(%rsp), %eax addl %eax, %eax cltq movabsq $768614336404564650, %rdx cmpq %rax, %rdx jb .L220 testq %rax, %rax je .L153 imulq $12, %rax, %rbx movq %rbx, 8(%rsp) movq %rbx, %rdi .LEHB4: call _Znwm@PLT .LEHE4: movq %rax, %r12 movq %rax, 48(%rsp) movq %rax, 56(%rsp) leaq (%rax,%rbx), %rcx movq %rcx, (%rsp) movq %rcx, 64(%rsp) movl $0, (%rax) movl $0, 4(%rax) movl $0, 8(%rax) leaq 12(%rax), %rax cmpq %rax, %rcx je .L154 .L155: movq (%r12), %rdx movq %rdx, (%rax) movl 8(%r12), %edx movl %edx, 8(%rax) addq $12, %rax cmpq %rax, (%rsp) jne .L155 .L154: movq (%rsp), %rax movq %rax, 56(%rsp) cmpl $0, 24(%rsp) jle .L156 movq %r12, %rbx movl $0, %r14d leaq .LC7(%rip), %r15 jmp .L157 .L218: movq 104(%rsp), %rax subq %fs:40, %rax je .L151 call __stack_chk_fail@PLT .L151: .LEHB5: call __cxa_throw_bad_array_new_length@PLT .LEHE5: .L220: movq 104(%rsp), %rax subq %fs:40, %rax jne .L221 leaq .LC8(%rip), %rdi .LEHB6: call _ZSt20__throw_length_errorPKc@PLT .LEHE6: .L221: call __stack_chk_fail@PLT .L222: leaq 36(%rsp), %rdx movq %r15, %rsi movq %r13, %rdi movl $0, %eax .LEHB7: call __isoc23_fscanf@PLT leaq 40(%rsp), %rdx movq %r15, %rsi movq %r13, %rdi movl $0, %eax call __isoc23_fscanf@PLT movl 32(%rsp), %edx movl %edx, (%rbx) movl 36(%rsp), %ecx movl %ecx, 4(%rbx) movl 40(%rsp), %eax movl %eax, 8(%rbx) movl %ecx, 12(%rbx) movl %edx, 16(%rbx) movl %eax, 20(%rbx) addl $1, %r14d addq $24, %rbx cmpl %r14d, 24(%rsp) jle .L156 .L157: leaq 32(%rsp), %rdx movq %r15, %rsi movq %r13, %rdi movl $0, %eax call __isoc23_fscanf@PLT jmp .L222 .L156: movq 8(%rsp), %rax sarq $2, %rax movabsq $-6148914691236517205, %rdx imulq %rdx, %rax movl $64, %ecx testq %rax, %rax je .L158 bsrq %rax, %rcx xorl $63, %ecx .L158: movl $63, %edx subl %ecx, %edx movslq %edx, %rdx addq %rdx, %rdx leaq _Z19compareTwoEdgePairs9edgepairsS_(%rip), %rcx movq (%rsp), %r15 movq %r15, %rsi movq %r12, %rdi call _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_ leaq _Z19compareTwoEdgePairs9edgepairsS_(%rip), %rdx cmpq $192, 8(%rsp) jle .L159 leaq 192(%r12), %rbx movq %rbx, %rsi movq %r12, %rdi call _ZSt16__insertion_sortIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_ cmpq %rbx, %r15 je .L191 leaq _Z19compareTwoEdgePairs9edgepairsS_(%rip), %r13 jmp .L161 .L223: addq $12, %rbx cmpq %rbx, (%rsp) je .L191 .L161: movq %r13, %rsi movq %rbx, %rdi call _ZSt25__unguarded_linear_insertIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops14_Val_comp_iterIPFbS2_S2_EEEEvT_T0_ jmp .L223 .L159: movq (%rsp), %rsi movq %r12, %rdi call _ZSt16__insertion_sortIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_ .LEHE7: jmp .L191 .L230: movq %rax, %r14 movq $0, 80(%rsp) movq $0, 88(%rsp) movq $0, 96(%rsp) leaq .LC9(%rip), %rsi leaq _ZSt4cout(%rip), %rdi .LEHB8: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpl $0, 28(%rsp) jle .L194 movl $0, %ebx movss .LC4(%rip), %xmm3 movss %xmm3, (%rsp) leaq _ZSt4cout(%rip), %r15 jmp .L175 .L227: movl %ebx, %esi movq %r15, %rdi call _ZNSolsEi@PLT movq %rax, %r12 movl $3, %edx leaq .LC11(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT pxor %xmm0, %xmm0 cvtss2sd (%r14,%rbx,4), %xmm0 movq %r12, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %r12 movq (%rax), %rax movq -24(%rax), %rax movq 240(%r12,%rax), %r13 testq %r13, %r13 je .L224 cmpb $0, 56(%r13) je .L173 movzbl 67(%r13), %esi .L174: movsbl %sil, %esi movq %r12, %rdi call _ZNSo3putEc@PLT jmp .L225 .L224: movq 104(%rsp), %rax subq %fs:40, %rax jne .L226 call _ZSt16__throw_bad_castv@PLT .L197: endbr64 movq %rax, %rbx leaq 80(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev .L189: leaq 48(%rsp), %rdi call _ZNSt6vectorI9edgepairsSaIS0_EED1Ev movq 104(%rsp), %rax subq %fs:40, %rax je .L190 call __stack_chk_fail@PLT .L226: call __stack_chk_fail@PLT .L173: movq %r13, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%r13), %rax movl $10, %esi movq %r13, %rdi call *48(%rax) movl %eax, %esi jmp .L174 .L225: movq %rax, %rdi call _ZNSo5flushEv@PLT addq $1, %rbx cmpl %ebx, 28(%rsp) jle .L170 .L175: movss (%r14,%rbx,4), %xmm0 movss (%rsp), %xmm1 call fmaxf@PLT movss %xmm0, (%rsp) movl $5, %edx leaq .LC10(%rip), %rsi movq %r15, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT jmp .L227 .L194: movss .LC4(%rip), %xmm4 movss %xmm4, (%rsp) .L170: movl $0, 44(%rsp) cmpl $0, 28(%rsp) jle .L176 movl $0, %ebx jmp .L180 .L179: leaq 44(%rsp), %rdx leaq 80(%rsp), %rdi call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_ .L177: addl $1, %r12d movl %r12d, 44(%rsp) addq $1, %rbx cmpl %ebx, 28(%rsp) jle .L176 .L180: movl %ebx, %r12d movss (%rsp), %xmm2 ucomiss (%r14,%rbx,4), %xmm2 jp .L177 jne .L177 movq 88(%rsp), %rsi cmpq 96(%rsp), %rsi je .L179 movl %ebx, (%rsi) addq $4, %rsi movq %rsi, 88(%rsp) jmp .L177 .L176: leaq _ZSt4cout(%rip), %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC12(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd (%rsp), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC13(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq 88(%rsp), %rax movq 80(%rsp), %r13 movq %rax, %r12 subq %r13, %r12 sarq $2, %r12 cmpq %rax, %r13 je .L181 movl $0, %ebx leaq -1(%r12), %r15 jmp .L184 .L228: movq %rax, %rdi movl $3, %edx leaq .LC14(%rip), %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT jmp .L183 .L182: movl 0(%r13,%rbx,4), %esi leaq _ZSt4cout(%rip), %rdi call _ZNSolsEi@PLT .L183: addq $1, %rbx cmpq %r12, %rbx jnb .L181 .L184: cmpq %rbx, %r15 je .L182 movl 0(%r13,%rbx,4), %esi leaq _ZSt4cout(%rip), %rdi call _ZNSolsEi@PLT jmp .L228 .L181: leaq .LC15(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC16(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT pxor %xmm0, %xmm0 cvtss2sd device_time_taken(%rip), %xmm0 leaq _ZSt4cout(%rip), %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT .LEHE8: testq %r14, %r14 je .L185 movq %r14, %rdi call _ZdaPv@PLT .L185: movl $32, %esi movq %rbp, %rdi call _ZdlPvm@PLT leaq 80(%rsp), %rdi call _ZNSt6vectorIiSaIiEED1Ev leaq 48(%rsp), %rdi call _ZNSt6vectorI9edgepairsSaIS0_EED1Ev .L141: movq 104(%rsp), %rax subq %fs:40, %rax jne .L229 movl $0, %eax addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L187: .cfi_restore_state movq %rbx, %rdi .LEHB9: call _Unwind_Resume@PLT .L196: endbr64 movq %rax, %rbx jmp .L189 .L190: movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE9: .L153: movq $0, 48(%rsp) movq $0, 64(%rsp) movq $0, 56(%rsp) movl $0, %r12d .L191: cmpl $0, 28(%rsp) js .L163 movl $0, %eax .L164: movq 8(%rbp), %rdx movl $0, (%rdx,%rax,4) addq $1, %rax cmpl %eax, 28(%rsp) jge .L164 .L163: movq 8(%rbp), %rax movl $0, (%rax) cmpl $0, 24(%rsp) jle .L165 leaq 4(%r12), %rdx movl $0, %eax .L166: movl (%rdx), %esi movq 16(%rbp), %rcx movl %esi, (%rcx,%rax,4) movl 4(%rdx), %esi movq 24(%rbp), %rcx movl %esi, (%rcx,%rax,4) movl 24(%rsp), %ecx addq $1, %rax addq $12, %rdx leal (%rcx,%rcx), %esi cmpl %eax, %esi jg .L166 testl %ecx, %ecx jle .L165 movl $0, %edx .L167: movslq (%r12), %rcx movq 8(%rbp), %rax addl $1, 4(%rax,%rcx,4) addl $1, %edx addq $12, %r12 movl 24(%rsp), %eax addl %eax, %eax cmpl %edx, %eax jg .L167 .L165: cmpl $0, 28(%rsp) jle .L168 movl $4, %eax movl $0, %ecx .L169: movq 8(%rbp), %rdx movl -4(%rdx,%rax), %esi addl %esi, (%rdx,%rax) addl $1, %ecx addq $4, %rax cmpl %ecx, 28(%rsp) jg .L169 .L168: movq %rbp, %rdi .LEHB10: call _Z3funP5Graph .LEHE10: jmp .L230 .L229: call __stack_chk_fail@PLT .cfi_endproc .LFE10864: .globl __gxx_personality_v0 .section .gcc_except_table,"a",@progbits .LLSDA10864: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE10864-.LLSDACSB10864 .LLSDACSB10864: .uleb128 .LEHB0-.LFB10864 .uleb128 .LEHE0-.LEHB0 .uleb128 0 .uleb128 0 .uleb128 .LEHB1-.LFB10864 .uleb128 .LEHE1-.LEHB1 .uleb128 .L195-.LFB10864 .uleb128 0 .uleb128 .LEHB2-.LFB10864 .uleb128 .LEHE2-.LEHB2 .uleb128 0 .uleb128 0 .uleb128 .LEHB3-.LFB10864 .uleb128 .LEHE3-.LEHB3 .uleb128 .L195-.LFB10864 .uleb128 0 .uleb128 .LEHB4-.LFB10864 .uleb128 .LEHE4-.LEHB4 .uleb128 0 .uleb128 0 .uleb128 .LEHB5-.LFB10864 .uleb128 .LEHE5-.LEHB5 .uleb128 .L195-.LFB10864 .uleb128 0 .uleb128 .LEHB6-.LFB10864 .uleb128 .LEHE6-.LEHB6 .uleb128 0 .uleb128 0 .uleb128 .LEHB7-.LFB10864 .uleb128 .LEHE7-.LEHB7 .uleb128 .L196-.LFB10864 .uleb128 0 .uleb128 .LEHB8-.LFB10864 .uleb128 .LEHE8-.LEHB8 .uleb128 .L197-.LFB10864 .uleb128 0 .uleb128 .LEHB9-.LFB10864 .uleb128 .LEHE9-.LEHB9 .uleb128 0 .uleb128 0 .uleb128 .LEHB10-.LFB10864 .uleb128 .LEHE10-.LEHB10 .uleb128 .L196-.LFB10864 .uleb128 0 .LLSDACSE10864: .text .size main, .-main .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .globl device_time_taken .bss .align 4 .type device_time_taken, @object .size device_time_taken, 4 device_time_taken: .zero 4 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC4: .long -1082130432 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9cal_deltaP5GraphPi ; -- Begin function _Z9cal_deltaP5GraphPi .globl _Z9cal_deltaP5GraphPi .p2align 8 .type _Z9cal_deltaP5GraphPi,@function _Z9cal_deltaP5GraphPi: ; @_Z9cal_deltaP5GraphPi ; %bb.0: s_load_b64 s[2:3], s[0:1], 0x0 v_lshlrev_b32_e32 v1, 2, v0 v_bfrev_b32_e32 v5, -2 s_waitcnt lgkmcnt(0) s_load_b64 s[4:5], s[2:3], 0x8 s_waitcnt lgkmcnt(0) v_add_co_u32 v1, s4, s4, v1 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v2, null, s5, 0, s4 s_mov_b32 s5, 0 s_mov_b32 s4, exec_lo flat_load_b64 v[1:2], v[1:2] s_waitcnt vmcnt(0) lgkmcnt(0) v_cmpx_lt_i32_e64 v1, v2 s_cbranch_execz .LBB0_4 ; %bb.1: ; %.lr.ph s_load_b64 s[2:3], s[2:3], 0x18 v_ashrrev_i32_e32 v4, 31, v1 v_mov_b32_e32 v3, v1 v_bfrev_b32_e32 v5, -2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[3:4], 2, v[3:4] s_waitcnt lgkmcnt(0) v_add_co_u32 v3, vcc_lo, s2, v3 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo .LBB0_2: ; =>This Inner Loop Header: Depth=1 flat_load_b32 v6, v[3:4] v_add_nc_u32_e32 v1, 1, v1 v_add_co_u32 v3, vcc_lo, v3, 4 v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_ge_i32_e64 s2, v1, v2 s_or_b32 s5, s2, s5 s_waitcnt vmcnt(0) lgkmcnt(0) v_min_i32_e32 v5, v5, v6 s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_2 ; %bb.3: ; %Flow s_or_b32 exec_lo, exec_lo, s5 .LBB0_4: ; %Flow20 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 s_load_b64 s[0:1], s[0:1], 0x8 v_lshlrev_b32_e32 v0, 2, v0 s_waitcnt lgkmcnt(0) global_store_b32 v0, v5, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9cal_deltaP5GraphPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 6 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9cal_deltaP5GraphPi, .Lfunc_end0-_Z9cal_deltaP5GraphPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 240 ; NumSgprs: 8 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 8 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ ; -- Begin function _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .globl _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .p2align 8 .type _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_,@function _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_: ; @_Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ ; %bb.0: v_cmp_eq_u32_e64 s2, 0, v0 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB1_2 ; %bb.1: v_dual_mov_b32 v1, -1 :: v_dual_mov_b32 v2, 0 ds_store_b32 v2, v1 .LBB1_2: s_or_b32 exec_lo, exec_lo, s3 s_load_b64 s[24:25], s[0:1], 0x0 v_mov_b32_e32 v2, 0 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv ds_load_b32 v1, v2 s_load_b32 s3, s[24:25], 0x0 s_waitcnt lgkmcnt(0) s_add_i32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) v_cmp_le_i32_e32 vcc_lo, s3, v1 s_cbranch_vccnz .LBB1_59 ; %bb.3: ; %.lr.ph171 s_clause 0x2 s_load_b256 s[4:11], s[0:1], 0x8 s_load_b256 s[12:19], s[0:1], 0x28 s_load_b128 s[20:23], s[0:1], 0x48 v_dual_mov_b32 v30, 1 :: v_dual_lshlrev_b32 v15, 2, v0 v_bfrev_b32_e32 v31, -2 v_mov_b32_e32 v32, 2 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v3, s0, s4, v15 v_add_co_ci_u32_e64 v4, null, s5, 0, s0 v_add_co_u32 v5, s0, s6, v15 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v6, null, s7, 0, s0 v_add_co_u32 v7, s0, s8, v15 v_add_co_ci_u32_e64 v8, null, s9, 0, s0 v_add_co_u32 v9, s0, s10, v15 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v10, null, s11, 0, s0 v_add_co_u32 v11, s0, s12, v15 v_add_co_ci_u32_e64 v12, null, s13, 0, s0 v_add_co_u32 v13, s0, s14, v15 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v14, null, s15, 0, s0 v_add_co_u32 v15, s0, s22, v15 v_add_co_ci_u32_e64 v16, null, s23, 0, s0 s_add_u32 s0, s16, -4 s_addc_u32 s1, s17, -1 s_branch .LBB1_5 .LBB1_4: ; %.loopexit159 ; in Loop: Header=BB1_5 Depth=1 global_load_b32 v17, v2, s[24:25] ds_load_b32 v1, v2 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v17, -1, v17 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_cmp_ge_i32_e32 vcc_lo, v1, v17 s_cbranch_vccnz .LBB1_59 .LBB1_5: ; =>This Loop Header: Depth=1 ; Child Loop BB1_15 Depth 2 ; Child Loop BB1_19 Depth 3 ; Child Loop BB1_22 Depth 4 ; Child Loop BB1_31 Depth 3 ; Child Loop BB1_43 Depth 2 ; Child Loop BB1_50 Depth 3 ; Child Loop BB1_53 Depth 4 ; Child Loop BB1_56 Depth 3 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB1_7 ; %bb.6: ; in Loop: Header=BB1_5 Depth=1 v_add_nc_u32_e32 v1, 1, v1 ds_store_b32 v2, v1 .LBB1_7: ; in Loop: Header=BB1_5 Depth=1 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv ds_load_b32 v1, v2 s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) v_cmpx_ne_u32_e64 v0, v1 s_xor_b32 s3, exec_lo, s3 s_cbranch_execz .LBB1_9 ; %bb.8: ; in Loop: Header=BB1_5 Depth=1 global_store_b32 v[3:4], v30, off global_store_b32 v[5:6], v2, off global_store_b32 v[7:8], v31, off global_store_b32 v[9:10], v2, off ; implicit-def: $vgpr1 .LBB1_9: ; %Flow228 ; in Loop: Header=BB1_5 Depth=1 s_and_not1_saveexec_b32 s3, s3 s_cbranch_execz .LBB1_11 ; %bb.10: ; in Loop: Header=BB1_5 Depth=1 v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v18, 1 global_store_b32 v[7:8], v17, off global_store_b32 v[9:10], v18, off global_store_b32 v[3:4], v17, off global_store_b32 v[5:6], v18, off s_clause 0x1 global_store_b32 v2, v1, s[18:19] global_store_b64 v2, v[17:18], s[16:17] ds_store_2addr_b32 v2, v18, v32 offset0:5 offset1:7 .LBB1_11: ; in Loop: Header=BB1_5 Depth=1 s_or_b32 exec_lo, exec_lo, s3 global_store_b32 v[11:12], v2, off global_store_b32 v[13:14], v2, off ds_store_b32 v2, v2 offset:12 s_waitcnt lgkmcnt(0) s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv ds_load_b32 v1, v2 offset:12 s_waitcnt lgkmcnt(0) v_cmp_eq_u32_e32 vcc_lo, 0x7fffffff, v1 s_cbranch_vccz .LBB1_15 .LBB1_12: ; %._crit_edge ; in Loop: Header=BB1_5 Depth=1 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB1_43 ; %bb.13: ; in Loop: Header=BB1_5 Depth=1 ds_load_b32 v1, v2 offset:28 s_branch .LBB1_42 .LBB1_14: ; in Loop: Header=BB1_15 Depth=2 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt lgkmcnt(0) s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv ds_load_b32 v1, v2 offset:12 s_waitcnt lgkmcnt(0) v_cmp_ne_u32_e32 vcc_lo, 0x7fffffff, v1 s_cbranch_vccz .LBB1_12 .LBB1_15: ; %.lr.ph163 ; Parent Loop BB1_5 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB1_19 Depth 3 ; Child Loop BB1_22 Depth 4 ; Child Loop BB1_31 Depth 3 s_barrier buffer_gl0_inv global_load_b32 v1, v[5:6], off s_mov_b32 s3, exec_lo s_waitcnt vmcnt(0) v_cmpx_eq_u32_e32 1, v1 s_cbranch_execz .LBB1_28 ; %bb.16: ; in Loop: Header=BB1_15 Depth=2 global_load_b64 v[17:18], v2, s[24:25] offset:8 v_lshlrev_b32_e32 v1, 2, v0 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_add_co_u32 v17, vcc_lo, v17, v1 v_add_co_ci_u32_e32 v18, vcc_lo, 0, v18, vcc_lo flat_load_b64 v[17:18], v[17:18] s_waitcnt vmcnt(0) lgkmcnt(0) v_cmp_lt_i32_e32 vcc_lo, v17, v18 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB1_28 ; %bb.17: ; %.lr.ph.preheader ; in Loop: Header=BB1_15 Depth=2 s_mov_b32 s6, 0 s_branch .LBB1_19 .LBB1_18: ; in Loop: Header=BB1_19 Depth=3 s_or_b32 exec_lo, exec_lo, s22 global_load_b64 v[18:19], v2, s[24:25] offset:8 s_waitcnt lgkmcnt(0) v_lshlrev_b32_e32 v1, 2, v0 v_add_nc_u32_e32 v17, 1, v17 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v18, vcc_lo, v18, v1 v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo flat_load_b32 v1, v[18:19] offset:4 s_waitcnt vmcnt(0) lgkmcnt(0) v_cmp_ge_i32_e32 vcc_lo, v17, v1 s_or_b32 s6, vcc_lo, s6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s6 s_cbranch_execz .LBB1_28 .LBB1_19: ; %.lr.ph ; Parent Loop BB1_5 Depth=1 ; Parent Loop BB1_15 Depth=2 ; => This Loop Header: Depth=3 ; Child Loop BB1_22 Depth 4 global_load_b128 v[19:22], v2, s[24:25] offset:16 v_ashrrev_i32_e32 v18, 31, v17 s_mov_b32 s7, -1 s_mov_b32 s22, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[23:24], 2, v[17:18] s_waitcnt vmcnt(0) v_add_co_u32 v18, vcc_lo, v19, v23 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v19, vcc_lo, v20, v24, vcc_lo flat_load_b32 v18, v[18:19] v_add_co_u32 v19, vcc_lo, v21, v23 v_add_co_ci_u32_e32 v20, vcc_lo, v22, v24, vcc_lo flat_load_b32 v1, v[19:20] s_waitcnt vmcnt(1) lgkmcnt(1) v_ashrrev_i32_e32 v19, 31, v18 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[24:25], 2, v[18:19] v_add_co_u32 v18, vcc_lo, s14, v24 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v19, vcc_lo, s15, v25, vcc_lo v_add_co_u32 v20, vcc_lo, s4, v24 v_add_co_ci_u32_e32 v21, vcc_lo, s5, v25, vcc_lo v_add_co_u32 v22, vcc_lo, s8, v24 v_add_co_ci_u32_e32 v23, vcc_lo, s9, v25, vcc_lo v_add_co_u32 v24, vcc_lo, s10, v24 v_add_co_ci_u32_e32 v25, vcc_lo, s11, v25, vcc_lo s_branch .LBB1_22 .LBB1_20: ; in Loop: Header=BB1_22 Depth=4 s_or_b32 exec_lo, exec_lo, s26 global_atomic_swap_b32 v[18:19], v2, off s_and_not1_b32 s7, s7, exec_lo .LBB1_21: ; %Flow221 ; in Loop: Header=BB1_22 Depth=4 s_or_b32 exec_lo, exec_lo, s23 s_xor_b32 s23, s7, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s23, exec_lo, s23 s_or_b32 s22, s23, s22 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s22 s_cbranch_execz .LBB1_18 .LBB1_22: ; Parent Loop BB1_5 Depth=1 ; Parent Loop BB1_15 Depth=2 ; Parent Loop BB1_19 Depth=3 ; => This Inner Loop Header: Depth=4 v_dual_mov_b32 v26, 1 :: v_dual_mov_b32 v27, 0 s_mov_b32 s23, exec_lo global_atomic_cmpswap_b32 v26, v[18:19], v[26:27], off glc s_waitcnt vmcnt(0) v_cmpx_eq_u32_e32 0, v26 s_cbranch_execz .LBB1_21 ; %bb.23: ; in Loop: Header=BB1_22 Depth=4 global_load_b32 v26, v[20:21], off s_mov_b32 s26, exec_lo s_waitcnt vmcnt(0) v_cmpx_eq_u32_e32 1, v26 s_cbranch_execz .LBB1_26 ; %bb.24: ; in Loop: Header=BB1_22 Depth=4 s_clause 0x1 global_load_b32 v26, v[7:8], off global_load_b32 v27, v[22:23], off s_waitcnt vmcnt(1) lgkmcnt(0) v_add_nc_u32_e32 v26, v26, v1 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_cmp_lt_i32_e32 vcc_lo, v26, v27 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB1_26 ; %bb.25: ; in Loop: Header=BB1_22 Depth=4 global_store_b32 v[22:23], v26, off global_store_b32 v[24:25], v2, off .LBB1_26: ; in Loop: Header=BB1_22 Depth=4 s_or_b32 exec_lo, exec_lo, s26 s_clause 0x1 global_load_b32 v26, v[7:8], off global_load_b32 v27, v[22:23], off s_mov_b32 s26, exec_lo s_waitcnt vmcnt(1) lgkmcnt(0) v_add_nc_u32_e32 v26, v26, v1 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e64 v27, v26 s_cbranch_execz .LBB1_20 ; %bb.27: ; in Loop: Header=BB1_22 Depth=4 s_clause 0x1 global_load_b32 v26, v[24:25], off global_load_b32 v27, v[9:10], off s_waitcnt vmcnt(0) v_add_nc_u32_e32 v26, v27, v26 global_store_b32 v[24:25], v26, off s_branch .LBB1_20 .LBB1_28: ; %.loopexit ; in Loop: Header=BB1_15 Depth=2 s_or_b32 exec_lo, exec_lo, s3 ds_store_b32 v2, v31 offset:12 s_waitcnt lgkmcnt(0) s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv global_load_b32 v1, v[3:4], off s_mov_b32 s3, exec_lo s_waitcnt vmcnt(0) v_cmpx_eq_u32_e32 1, v1 s_cbranch_execz .LBB1_34 ; %bb.29: ; in Loop: Header=BB1_15 Depth=2 global_load_b32 v1, v[7:8], off s_waitcnt vmcnt(0) v_cmp_ne_u32_e32 vcc_lo, 0x7fffffff, v1 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB1_34 ; %bb.30: ; in Loop: Header=BB1_15 Depth=2 global_load_b32 v17, v[15:16], off s_mov_b32 s7, exec_lo s_brev_b32 s6, -2 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v1, v17, v1 .LBB1_31: ; %ComputeLoop ; Parent Loop BB1_5 Depth=1 ; Parent Loop BB1_15 Depth=2 ; => This Inner Loop Header: Depth=3 s_ctz_i32_b32 s22, s7 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_readlane_b32 s23, v1, s22 s_lshl_b32 s22, 1, s22 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_and_not1_b32 s7, s7, s22 s_min_i32 s6, s6, s23 s_cmp_lg_u32 s7, 0 s_cbranch_scc1 .LBB1_31 ; %bb.32: ; %ComputeEnd ; in Loop: Header=BB1_15 Depth=2 v_mbcnt_lo_u32_b32 v1, exec_lo, 0 s_mov_b32 s7, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v1 s_xor_b32 s7, exec_lo, s7 s_cbranch_execz .LBB1_34 ; %bb.33: ; in Loop: Header=BB1_15 Depth=2 v_mov_b32_e32 v1, s6 ds_min_i32 v2, v1 offset:12 .LBB1_34: ; in Loop: Header=BB1_15 Depth=2 s_or_b32 exec_lo, exec_lo, s3 ds_store_b32 v2, v2 offset:8 global_store_b32 v[5:6], v2, off s_waitcnt lgkmcnt(0) s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv global_load_b32 v1, v[3:4], off s_mov_b32 s3, exec_lo s_waitcnt vmcnt(0) v_cmpx_eq_u32_e32 1, v1 s_cbranch_execz .LBB1_40 ; %bb.35: ; in Loop: Header=BB1_15 Depth=2 global_load_b32 v1, v[7:8], off ds_load_b32 v17, v2 offset:12 s_waitcnt vmcnt(0) lgkmcnt(0) v_cmp_lt_i32_e32 vcc_lo, v1, v17 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB1_40 ; %bb.36: ; in Loop: Header=BB1_15 Depth=2 s_mov_b32 s6, exec_lo s_mov_b32 s7, exec_lo v_mbcnt_lo_u32_b32 v1, s6, 0 global_store_b32 v[3:4], v2, off global_store_b32 v[5:6], v30, off ; implicit-def: $vgpr17 v_cmpx_eq_u32_e32 0, v1 s_cbranch_execz .LBB1_38 ; %bb.37: ; in Loop: Header=BB1_15 Depth=2 s_bcnt1_i32_b32 s6, s6 s_delay_alu instid0(SALU_CYCLE_1) v_mov_b32_e32 v17, s6 ds_add_rtn_u32 v17, v2, v17 offset:20 .LBB1_38: ; in Loop: Header=BB1_15 Depth=2 s_or_b32 exec_lo, exec_lo, s7 s_waitcnt lgkmcnt(0) v_readfirstlane_b32 s7, v17 s_mov_b32 s6, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v17, s7, v1 v_mbcnt_lo_u32_b32 v1, s6, 0 v_ashrrev_i32_e32 v18, 31, v17 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[17:18], 2, v[17:18] v_add_co_u32 v17, vcc_lo, s18, v17 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e32 v18, vcc_lo, s19, v18, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v1 global_store_b32 v[17:18], v0, off s_and_b32 s7, exec_lo, vcc_lo s_mov_b32 exec_lo, s7 s_cbranch_execz .LBB1_40 ; %bb.39: ; in Loop: Header=BB1_15 Depth=2 s_bcnt1_i32_b32 s6, s6 s_delay_alu instid0(SALU_CYCLE_1) v_mov_b32_e32 v1, s6 ds_add_u32 v2, v1 offset:8 .LBB1_40: ; in Loop: Header=BB1_15 Depth=2 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt lgkmcnt(0) s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv ds_load_b32 v1, v2 offset:8 s_waitcnt lgkmcnt(0) v_readfirstlane_b32 s3, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_cmp_gt_i32 s3, 0 s_cselect_b32 s3, -1, 0 s_and_b32 s6, s2, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s6 s_cbranch_execz .LBB1_14 ; %bb.41: ; in Loop: Header=BB1_15 Depth=2 ds_load_b32 v17, v2 offset:28 s_waitcnt lgkmcnt(0) v_ashrrev_i32_e32 v18, 31, v17 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[18:19], 2, v[17:18] v_add_nc_u32_e32 v17, 1, v17 ds_store_b32 v2, v17 offset:28 v_add_co_u32 v18, vcc_lo, s16, v18 v_add_co_ci_u32_e32 v19, vcc_lo, s17, v19, vcc_lo global_load_b32 v20, v[18:19], off offset:-4 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v1, v20, v1 global_store_b32 v[18:19], v1, off s_branch .LBB1_14 .LBB1_42: ; in Loop: Header=BB1_5 Depth=1 s_waitcnt lgkmcnt(0) v_add_nc_u32_e32 v1, -1, v1 ds_store_b32 v2, v1 offset:16 .LBB1_43: ; Parent Loop BB1_5 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB1_50 Depth 3 ; Child Loop BB1_53 Depth 4 ; Child Loop BB1_56 Depth 3 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv ds_load_b32 v1, v2 offset:16 s_waitcnt lgkmcnt(0) v_cmp_gt_i32_e32 vcc_lo, 1, v1 s_cbranch_vccnz .LBB1_4 ; %bb.44: ; %.lr.ph169 ; in Loop: Header=BB1_43 Depth=2 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB1_46 ; %bb.45: ; in Loop: Header=BB1_43 Depth=2 v_lshlrev_b64 v[17:18], 2, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v19, vcc_lo, s16, v17 v_add_co_ci_u32_e32 v20, vcc_lo, s17, v18, vcc_lo v_add_co_u32 v17, vcc_lo, s0, v17 v_add_co_ci_u32_e32 v18, vcc_lo, s1, v18, vcc_lo s_clause 0x1 global_load_b32 v1, v[19:20], off global_load_b32 v17, v[17:18], off s_waitcnt vmcnt(1) v_add_nc_u32_e32 v1, -1, v1 s_waitcnt vmcnt(0) ds_store_2addr_b32 v2, v1, v17 offset0:1 offset1:6 .LBB1_46: ; in Loop: Header=BB1_43 Depth=2 s_or_b32 exec_lo, exec_lo, s3 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv ds_load_2addr_b32 v[17:18], v2 offset0:1 offset1:6 s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) v_sub_nc_u32_e32 v1, v17, v18 s_delay_alu instid0(VALU_DEP_1) v_cmpx_le_i32_e64 v0, v1 s_cbranch_execz .LBB1_57 ; %bb.47: ; in Loop: Header=BB1_43 Depth=2 v_add_nc_u32_e32 v17, v18, v0 s_mov_b32 s6, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v18, 31, v17 v_lshlrev_b64 v[17:18], 2, v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v17, vcc_lo, s18, v17 v_add_co_ci_u32_e32 v18, vcc_lo, s19, v18, vcc_lo global_load_b32 v19, v[17:18], off global_load_b64 v[21:22], v2, s[24:25] offset:8 s_waitcnt vmcnt(1) v_ashrrev_i32_e32 v20, 31, v19 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[17:18], 2, v[19:20] s_waitcnt vmcnt(0) v_add_co_u32 v20, vcc_lo, v21, v17 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v21, vcc_lo, v22, v18, vcc_lo flat_load_b64 v[20:21], v[20:21] s_waitcnt vmcnt(0) lgkmcnt(0) v_cmpx_lt_i32_e64 v20, v21 s_cbranch_execz .LBB1_54 ; %bb.48: ; %.lr.ph166 ; in Loop: Header=BB1_43 Depth=2 v_add_co_u32 v22, vcc_lo, s8, v17 v_add_co_ci_u32_e32 v23, vcc_lo, s9, v18, vcc_lo v_add_co_u32 v24, vcc_lo, s12, v17 v_add_co_ci_u32_e32 v25, vcc_lo, s13, v18, vcc_lo v_add_co_u32 v26, vcc_lo, s10, v17 v_add_co_ci_u32_e32 v27, vcc_lo, s11, v18, vcc_lo s_mov_b32 s7, 0 s_branch .LBB1_50 .LBB1_49: ; in Loop: Header=BB1_50 Depth=3 s_or_b32 exec_lo, exec_lo, s22 global_load_b64 v[28:29], v2, s[24:25] offset:8 v_add_nc_u32_e32 v20, 1, v20 s_waitcnt vmcnt(0) v_add_co_u32 v28, vcc_lo, v28, v17 v_add_co_ci_u32_e32 v29, vcc_lo, v29, v18, vcc_lo flat_load_b32 v1, v[28:29] offset:4 s_waitcnt vmcnt(0) lgkmcnt(0) v_cmp_ge_i32_e32 vcc_lo, v20, v1 s_or_b32 s7, vcc_lo, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s7 s_cbranch_execz .LBB1_54 .LBB1_50: ; Parent Loop BB1_5 Depth=1 ; Parent Loop BB1_43 Depth=2 ; => This Loop Header: Depth=3 ; Child Loop BB1_53 Depth 4 global_load_b128 v[33:36], v2, s[24:25] offset:16 v_ashrrev_i32_e32 v21, 31, v20 s_mov_b32 s22, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[28:29], 2, v[20:21] s_waitcnt vmcnt(0) v_add_co_u32 v33, vcc_lo, v33, v28 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v34, vcc_lo, v34, v29, vcc_lo v_add_co_u32 v35, vcc_lo, v35, v28 v_add_co_ci_u32_e32 v36, vcc_lo, v36, v29, vcc_lo flat_load_b32 v33, v[33:34] flat_load_b32 v1, v[35:36] s_waitcnt vmcnt(1) lgkmcnt(1) v_ashrrev_i32_e32 v34, 31, v33 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[28:29], 2, v[33:34] v_add_co_u32 v33, vcc_lo, s8, v28 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v34, vcc_lo, s9, v29, vcc_lo s_clause 0x1 global_load_b32 v21, v[22:23], off global_load_b32 v33, v[33:34], off s_waitcnt vmcnt(1) lgkmcnt(0) v_add_nc_u32_e32 v1, v21, v1 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e64 v33, v1 s_cbranch_execz .LBB1_49 ; %bb.51: ; in Loop: Header=BB1_50 Depth=3 v_add_co_u32 v33, vcc_lo, s10, v28 v_add_co_ci_u32_e32 v34, vcc_lo, s11, v29, vcc_lo global_load_b32 v1, v[33:34], off s_waitcnt vmcnt(0) v_cmp_ne_u32_e32 vcc_lo, 0, v1 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB1_49 ; %bb.52: ; in Loop: Header=BB1_50 Depth=3 global_load_b32 v21, v[26:27], off v_cvt_f64_i32_e32 v[33:34], v1 v_add_co_u32 v28, vcc_lo, s12, v28 v_add_co_ci_u32_e32 v29, vcc_lo, s13, v29, vcc_lo s_mov_b32 s23, 0 global_load_b32 v1, v[28:29], off s_waitcnt vmcnt(1) v_cvt_f64_i32_e32 v[35:36], v21 s_waitcnt vmcnt(0) v_add_f32_e32 v1, 1.0, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f64 v[37:38], null, v[33:34], v[33:34], v[35:36] v_div_scale_f64 v[43:44], vcc_lo, v[35:36], v[33:34], v[35:36] v_rcp_f64_e32 v[28:29], v[37:38] s_waitcnt_depctr 0xfff v_fma_f64 v[39:40], -v[37:38], v[28:29], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_fma_f64 v[39:40], v[28:29], v[39:40], v[28:29] global_load_b32 v29, v[24:25], off v_fma_f64 v[41:42], -v[37:38], v[39:40], 1.0 v_fma_f64 v[39:40], v[39:40], v[41:42], v[39:40] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[41:42], v[43:44], v[39:40] v_fma_f64 v[37:38], -v[37:38], v[41:42], v[43:44] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[37:38], v[37:38], v[39:40], v[41:42] v_div_fixup_f64 v[33:34], v[37:38], v[33:34], v[35:36] v_cvt_f64_f32_e32 v[35:36], v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[33:34], v[33:34], v[35:36] v_cvt_f32_f64_e32 v1, v[33:34] .LBB1_53: ; %atomicrmw.start ; Parent Loop BB1_5 Depth=1 ; Parent Loop BB1_43 Depth=2 ; Parent Loop BB1_50 Depth=3 ; => This Inner Loop Header: Depth=4 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v28, v29, v1 global_atomic_cmpswap_b32 v21, v[24:25], v[28:29], off glc s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, v21, v29 v_mov_b32_e32 v29, v21 s_or_b32 s23, vcc_lo, s23 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s23 s_cbranch_execnz .LBB1_53 s_branch .LBB1_49 .LBB1_54: ; %Flow212 ; in Loop: Header=BB1_43 Depth=2 s_or_b32 exec_lo, exec_lo, s6 ds_load_b32 v1, v2 s_waitcnt lgkmcnt(0) v_cmp_ne_u32_e32 vcc_lo, v19, v1 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB1_57 ; %bb.55: ; in Loop: Header=BB1_43 Depth=2 v_add_co_u32 v19, vcc_lo, s12, v17 v_add_co_ci_u32_e32 v20, vcc_lo, s13, v18, vcc_lo v_add_co_u32 v17, vcc_lo, s20, v17 v_add_co_ci_u32_e32 v18, vcc_lo, s21, v18, vcc_lo s_mov_b32 s6, 0 global_load_b32 v1, v[19:20], off global_load_b32 v20, v[17:18], off s_waitcnt vmcnt(1) v_mul_f32_e32 v1, 0.5, v1 .LBB1_56: ; %atomicrmw.start174 ; Parent Loop BB1_5 Depth=1 ; Parent Loop BB1_43 Depth=2 ; => This Inner Loop Header: Depth=3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v19, v20, v1 global_atomic_cmpswap_b32 v19, v[17:18], v[19:20], off glc s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, v19, v20 v_mov_b32_e32 v20, v19 s_or_b32 s6, vcc_lo, s6 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s6 s_cbranch_execnz .LBB1_56 .LBB1_57: ; %Flow213 ; in Loop: Header=BB1_43 Depth=2 s_or_b32 exec_lo, exec_lo, s3 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB1_43 ; %bb.58: ; in Loop: Header=BB1_5 Depth=1 ds_load_b32 v1, v2 offset:16 s_branch .LBB1_42 .LBB1_59: ; %._crit_edge172 s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .amdhsa_group_segment_fixed_size 32 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 88 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 45 .amdhsa_next_free_sgpr 27 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_, .Lfunc_end1-_Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 2860 ; NumSgprs: 29 ; NumVgprs: 45 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 32 bytes/workgroup (compile time only) ; SGPRBlocks: 3 ; VGPRBlocks: 5 ; NumSGPRsForWavesPerEU: 29 ; NumVGPRsForWavesPerEU: 45 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9cal_deltaP5GraphPi .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z9cal_deltaP5GraphPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 32 .kernarg_segment_align: 8 .kernarg_segment_size: 88 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .private_segment_fixed_size: 0 .sgpr_count: 29 .sgpr_spill_count: 0 .symbol: _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 45 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "81472862b0a7f59b878780cb8929a66c2f55a376.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z19compareTwoEdgePairs9edgepairsS_ # -- Begin function _Z19compareTwoEdgePairs9edgepairsS_ .p2align 4, 0x90 .type _Z19compareTwoEdgePairs9edgepairsS_,@function _Z19compareTwoEdgePairs9edgepairsS_: # @_Z19compareTwoEdgePairs9edgepairsS_ .cfi_startproc # %bb.0: cmpl %edx, %edi jne .LBB0_1 # %bb.2: shrq $32, %rdx shrq $32, %rdi cmpq %rdx, %rdi sete %cl cmpl %edx, %edi setl %al orb %cl, %al retq .LBB0_1: setl %al retq .Lfunc_end0: .size _Z19compareTwoEdgePairs9edgepairsS_, .Lfunc_end0-_Z19compareTwoEdgePairs9edgepairsS_ .cfi_endproc # -- End function .globl _Z24__device_stub__cal_deltaP5GraphPi # -- Begin function _Z24__device_stub__cal_deltaP5GraphPi .p2align 4, 0x90 .type _Z24__device_stub__cal_deltaP5GraphPi,@function _Z24__device_stub__cal_deltaP5GraphPi: # @_Z24__device_stub__cal_deltaP5GraphPi .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z9cal_deltaP5GraphPi, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end1: .size _Z24__device_stub__cal_deltaP5GraphPi, .Lfunc_end1-_Z24__device_stub__cal_deltaP5GraphPi .cfi_endproc # -- End function .globl _Z21__device_stub__kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ # -- Begin function _Z21__device_stub__kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .p2align 4, 0x90 .type _Z21__device_stub__kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_,@function _Z21__device_stub__kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_: # @_Z21__device_stub__kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movq %r9, 48(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) leaq 224(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end2: .size _Z21__device_stub__kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_, .Lfunc_end2-_Z21__device_stub__kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .cfi_endproc # -- End function .globl _Z3funP5Graph # -- Begin function _Z3funP5Graph .p2align 4, 0x90 .type _Z3funP5Graph,@function _Z3funP5Graph: # @_Z3funP5Graph .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $360, %rsp # imm = 0x168 .cfi_def_cfa_offset 416 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdi, %rbx leaq 8(%rsp), %rdi movl $32, %esi callq hipMalloc movslq (%rbx), %r13 movslq 4(%rbx), %rbp movq 8(%rsp), %rdi movl $32, %edx movq %rbx, %rsi movl $1, %ecx callq hipMemcpy leaq 4(,%r13,4), %r14 leaq 192(%rsp), %r12 movq %r12, %rdi movq %r14, %rsi callq hipMalloc movq 192(%rsp), %rdi movq 8(%rbx), %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi addq $8, %rdi movl $8, %edx movq %r12, %rsi movl $1, %ecx callq hipMemcpy leal (,%rbp,2), %r15d leaq 4(,%rbp,8), %r14 leaq 184(%rsp), %r12 movq %r12, %rdi movq %r14, %rsi callq hipMalloc movq 184(%rsp), %rdi movq 16(%rbx), %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi addq $16, %rdi movl $8, %edx movq %r12, %rsi movl $1, %ecx callq hipMemcpy movslq %r15d, %r14 movabsq $4294967297, %r15 # imm = 0x100000001 shlq $2, %r14 leaq 176(%rsp), %r12 movq %r12, %rdi movq %r14, %rsi callq hipMalloc movq 176(%rsp), %rdi movq 24(%rbx), %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi addq $24, %rdi movl $8, %edx movq %r12, %rsi movl $1, %ecx callq hipMemcpy leaq (,%r13,4), %r14 testq %r13, %r13 movq $-1, %r12 cmovnsq %r14, %r12 movq %r12, %rdi callq _Znam movq %rax, %rbx movq %rax, %rdi xorl %esi, %esi movq %r12, %rdx callq memset@PLT leaq 16(%rsp), %rdi movq %r14, %rsi callq hipMalloc movq 16(%rsp), %rdi movq %rbx, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 168(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 160(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 152(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 144(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 136(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 128(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 120(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 112(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 104(%rsp), %rdi callq hipEventCreate leaq 32(%rsp), %rdi callq hipEventCreate movq 104(%rsp), %rdi xorl %esi, %esi callq hipEventRecord leaq 24(%rsp), %rdi movq %r14, %rsi callq hipMalloc movl %r13d, %eax leaq (%rax,%r15), %r12 decq %r12 movq %r15, %rdi movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_2 # %bb.1: movq 8(%rsp), %rax movq 24(%rsp), %rcx movq %rax, 96(%rsp) movq %rcx, 88(%rsp) leaq 96(%rsp), %rax movq %rax, 272(%rsp) leaq 88(%rsp), %rax movq %rax, 280(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 80(%rsp), %rdx leaq 72(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 272(%rsp), %r9 movl $_Z9cal_deltaP5GraphPi, %edi pushq 72(%rsp) .cfi_adjust_cfa_offset 8 pushq 88(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_2: callq hipDeviceSynchronize movq %r15, %rdi movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_4 # %bb.3: movq 8(%rsp), %rax movq 168(%rsp), %rcx movq 160(%rsp), %rdx movq 152(%rsp), %rsi movq 144(%rsp), %rdi movq 136(%rsp), %r8 movq 128(%rsp), %r9 movq 120(%rsp), %r10 movq 112(%rsp), %r11 movq 16(%rsp), %r15 movq 24(%rsp), %r12 movq %rax, 96(%rsp) movq %rcx, 88(%rsp) movq %rdx, 80(%rsp) movq %rsi, 72(%rsp) movq %rdi, 264(%rsp) movq %r8, 256(%rsp) movq %r9, 248(%rsp) movq %r10, 240(%rsp) movq %r11, 232(%rsp) movq %r15, 224(%rsp) movq %r12, 216(%rsp) leaq 96(%rsp), %rax movq %rax, 272(%rsp) leaq 88(%rsp), %rax movq %rax, 280(%rsp) leaq 80(%rsp), %rax movq %rax, 288(%rsp) leaq 72(%rsp), %rax movq %rax, 296(%rsp) leaq 264(%rsp), %rax movq %rax, 304(%rsp) leaq 256(%rsp), %rax movq %rax, 312(%rsp) leaq 248(%rsp), %rax movq %rax, 320(%rsp) leaq 240(%rsp), %rax movq %rax, 328(%rsp) leaq 232(%rsp), %rax movq %rax, 336(%rsp) leaq 224(%rsp), %rax movq %rax, 344(%rsp) leaq 216(%rsp), %rax movq %rax, 352(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 208(%rsp), %rdx leaq 200(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 272(%rsp), %r9 movl $_Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_, %edi pushq 200(%rsp) .cfi_adjust_cfa_offset 8 pushq 216(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_4: callq hipDeviceSynchronize movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB3_9 # %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r15) je .LBB3_7 # %bb.6: movzbl 67(%r15), %eax jmp .LBB3_8 .LBB3_7: movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB3_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 32(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 32(%rsp), %rdi callq hipEventSynchronize movq 104(%rsp), %rsi movq 32(%rsp), %rdx movl $device_time_taken, %edi callq hipEventElapsedTime movq 16(%rsp), %rsi movq %rbx, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 16(%rsp), %rdi callq hipFree movq 168(%rsp), %rdi callq hipFree movq 160(%rsp), %rdi callq hipFree movq 152(%rsp), %rdi callq hipFree movq 144(%rsp), %rdi callq hipFree movq 136(%rsp), %rdi callq hipFree movq 128(%rsp), %rdi callq hipFree movq 120(%rsp), %rdi callq hipFree movq 112(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq %rbx, %rax addq $360, %rsp # imm = 0x168 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB3_9: .cfi_def_cfa_offset 416 callq _ZSt16__throw_bad_castv .Lfunc_end3: .size _Z3funP5Graph, .Lfunc_end3-_Z3funP5Graph .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI4_0: .long 0xbf800000 # float -1 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $88, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq 8(%rsi), %rdi movl $.L.str, %esi callq fopen testq %rax, %rax je .LBB4_7 # %bb.1: movq %rax, %r15 leaq 8(%rsp), %rdx movl $.L.str.2, %esi movq %rax, %rdi xorl %eax, %eax callq __isoc23_fscanf leaq 12(%rsp), %rdx movl $.L.str.2, %esi movq %r15, %rdi xorl %eax, %eax callq __isoc23_fscanf movl $32, %edi callq _Znwm movq %rax, %r12 movslq 8(%rsp), %rax cmpq $-1, %rax movl 12(%rsp), %r14d movl %eax, (%r12) movl %r14d, 4(%r12) leaq 4(,%rax,4), %rdi movq $-1, %rbx cmovlq %rbx, %rdi .Ltmp0: callq _Znam .Ltmp1: # %bb.2: # %.noexc movq %rax, 8(%r12) leal 1(,%r14,2), %eax movslq %eax, %rdi shlq $2, %rdi testl %r14d, %r14d cmovsq %rbx, %rdi .Ltmp2: callq _Znam .Ltmp3: # %bb.3: # %.noexc85 leal (%r14,%r14), %ecx movslq %ecx, %rbx shlq $2, %rbx testl %r14d, %r14d movq %rax, 16(%r12) movq $-1, %rdi cmovnsq %rbx, %rdi .Ltmp4: callq _Znam .Ltmp5: # %bb.4: # %_ZN5GraphC2Eii.exit movq %r12, 32(%rsp) # 8-byte Spill movq %rax, 24(%r12) testl %r14d, %r14d js .LBB4_179 # %bb.5: # %_ZNSt6vectorI9edgepairsSaIS0_EE17_S_check_init_lenEmRKS1_.exit.i je .LBB4_8 # %bb.6: # %_ZNSt16allocator_traitsISaI9edgepairsEE8allocateERS1_m.exit.i.i.i.i leaq (%rbx,%rbx,2), %rdi callq _Znwm jmp .LBB4_9 .LBB4_7: movl $.L.str.1, %edi xorl %eax, %eax callq printf jmp .LBB4_172 .LBB4_8: xorl %eax, %eax .LBB4_9: # %_ZNSt12_Vector_baseI9edgepairsSaIS0_EEC2EmRKS1_.exit.i movq %rax, 16(%rsp) # 8-byte Spill testl %r14d, %r14d je .LBB4_13 # %bb.10: leaq (%rbx,%rbx,2), %r14 movq 16(%rsp), %rdx # 8-byte Reload movl $0, 8(%rdx) movq $0, (%rdx) movl $12, %eax .p2align 4, 0x90 .LBB4_11: # %.lr.ph.i.i.i.i.i.i.i.i.i # =>This Inner Loop Header: Depth=1 movl 8(%rdx), %ecx movl %ecx, 8(%rdx,%rax) movq (%rdx), %rcx movq %rcx, (%rdx,%rax) addq $12, %rax cmpq %rax, %r14 jne .LBB4_11 # %bb.12: # %_ZNSt6vectorI9edgepairsSaIS0_EEC2EmRKS1_.exit cmpl $0, 12(%rsp) jg .LBB4_14 jmp .LBB4_19 .LBB4_13: xorl %r14d, %r14d cmpl $0, 12(%rsp) jle .LBB4_19 .LBB4_14: # %.lr.ph.preheader movq 16(%rsp), %rax # 8-byte Reload leaq 20(%rax), %rbx leaq 80(%rsp), %r13 leaq 76(%rsp), %rbp xorl %r12d, %r12d .p2align 4, 0x90 .LBB4_15: # %.lr.ph # =>This Inner Loop Header: Depth=1 .Ltmp7: movl $.L.str.2, %esi movq %r15, %rdi leaq 84(%rsp), %rdx xorl %eax, %eax callq __isoc23_fscanf .Ltmp8: # %bb.16: # in Loop: Header=BB4_15 Depth=1 .Ltmp9: movl $.L.str.2, %esi movq %r15, %rdi movq %r13, %rdx xorl %eax, %eax callq __isoc23_fscanf .Ltmp10: # %bb.17: # in Loop: Header=BB4_15 Depth=1 .Ltmp11: movl $.L.str.2, %esi movq %r15, %rdi movq %rbp, %rdx xorl %eax, %eax callq __isoc23_fscanf .Ltmp12: # %bb.18: # in Loop: Header=BB4_15 Depth=1 movl 84(%rsp), %eax movl %eax, -20(%rbx) movl 80(%rsp), %ecx movl %ecx, -16(%rbx) movl 76(%rsp), %edx movl %edx, -12(%rbx) movl %ecx, -8(%rbx) movl %eax, -4(%rbx) movl %edx, (%rbx) incl %r12d addq $24, %rbx cmpl 12(%rsp), %r12d jl .LBB4_15 .LBB4_19: # %._crit_edge testq %r14, %r14 movq 16(%rsp), %rbx # 8-byte Reload je .LBB4_74 # %bb.20: leaq (%rbx,%r14), %r15 movq %r14, %rax sarq $2, %rax movabsq $-6148914691236517205, %rcx # imm = 0xAAAAAAAAAAAAAAAB imulq %rax, %rcx bsrq %rcx, %rax xorl $63, %eax addl %eax, %eax movl $126, %edx subq %rax, %rdx .Ltmp14: movl $_Z19compareTwoEdgePairs9edgepairsS_, %ecx movq %rbx, %rdi movq %r15, %rsi callq _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_ .Ltmp15: # %bb.21: # %.noexc89 cmpq $193, %r14 jl .LBB4_43 # %bb.22: # %.preheader.i.i.preheader leaq 12(%rbx), %r14 movl $12, %r12d movq %rbx, %rdi jmp .LBB4_25 .p2align 4, 0x90 .LBB4_23: # %_ZSt25__unguarded_linear_insertIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops14_Val_comp_iterIPFbS2_S2_EEEEvT_T0_.exit.i.i # in Loop: Header=BB4_25 Depth=1 movq %rax, (%rdx) movl %ecx, 8(%rdx) .LBB4_24: # in Loop: Header=BB4_25 Depth=1 addq $12, %r12 addq $12, %r14 movq %r13, %rdi cmpq $192, %r12 je .LBB4_63 .LBB4_25: # %.preheader.i.i # =>This Loop Header: Depth=1 # Child Loop BB4_39 Depth 2 movq (%rbx,%r12), %rax movq (%rbx), %rcx cmpl %ecx, %eax jne .LBB4_27 # %bb.26: # in Loop: Header=BB4_25 Depth=1 shrq $32, %rcx movq %rax, %rdx shrq $32, %rdx cmpq %rcx, %rdx sete %sil cmpl %ecx, %edx setl %cl orb %sil, %cl jmp .LBB4_28 .p2align 4, 0x90 .LBB4_27: # in Loop: Header=BB4_25 Depth=1 setl %cl .LBB4_28: # %_Z19compareTwoEdgePairs9edgepairsS_.exit255 # in Loop: Header=BB4_25 Depth=1 leaq (%rbx,%r12), %r13 testb %cl, %cl je .LBB4_32 # %bb.29: # in Loop: Header=BB4_25 Depth=1 movl 8(%r13), %eax movl %eax, 56(%rsp) movq (%r13), %rax movq %rax, 48(%rsp) cmpq $13, %r12 jb .LBB4_41 # %bb.30: # in Loop: Header=BB4_25 Depth=1 subq %r12, %rdi addq $24, %rdi movq %rbx, %rsi movq %r12, %rdx callq memmove@PLT .LBB4_31: # %_ZSt13move_backwardIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEES7_ET0_T_S9_S8_.exit.i.i # in Loop: Header=BB4_25 Depth=1 movl 56(%rsp), %eax movl %eax, 8(%rbx) movq 48(%rsp), %rax movq %rax, (%rbx) jmp .LBB4_24 .p2align 4, 0x90 .LBB4_32: # in Loop: Header=BB4_25 Depth=1 movq (%rdi), %rcx cmpl %ecx, %eax jne .LBB4_34 # %bb.33: # in Loop: Header=BB4_25 Depth=1 shrq $32, %rcx movq %rax, %rdx shrq $32, %rdx cmpq %rcx, %rdx sete %r8b cmpl %ecx, %edx setl %sil orb %r8b, %sil jmp .LBB4_35 .p2align 4, 0x90 .LBB4_34: # in Loop: Header=BB4_25 Depth=1 setl %sil .LBB4_35: # %_Z19compareTwoEdgePairs9edgepairsS_.exit244 # in Loop: Header=BB4_25 Depth=1 movl 20(%rdi), %ecx movq %r13, %rdx testb %sil, %sil je .LBB4_23 # %bb.36: # %.lr.ph.i.i.i.preheader # in Loop: Header=BB4_25 Depth=1 movq %rax, %rsi shrq $32, %rsi movq %r14, %rdx jmp .LBB4_39 .p2align 4, 0x90 .LBB4_37: # in Loop: Header=BB4_39 Depth=2 shrq $32, %rdi cmpq %rdi, %rsi sete %r8b cmpl %edi, %esi setl %dil orb %r8b, %dil .LBB4_38: # %_Z19compareTwoEdgePairs9edgepairsS_.exit233 # in Loop: Header=BB4_39 Depth=2 addq $-12, %rdx testb %dil, %dil je .LBB4_23 .LBB4_39: # %.lr.ph.i.i.i # Parent Loop BB4_25 Depth=1 # => This Inner Loop Header: Depth=2 movl -4(%rdx), %edi movl %edi, 8(%rdx) movq -24(%rdx), %rdi movq -12(%rdx), %r8 movq %r8, (%rdx) cmpl %edi, %eax je .LBB4_37 # %bb.40: # in Loop: Header=BB4_39 Depth=2 setl %dil jmp .LBB4_38 .LBB4_41: # in Loop: Header=BB4_25 Depth=1 cmpq $12, %r12 jne .LBB4_31 # %bb.42: # in Loop: Header=BB4_25 Depth=1 movl 8(%rbx), %eax movl %eax, 20(%rdi) movq (%rbx), %rax movq %rax, 12(%rdi) jmp .LBB4_31 .LBB4_43: # %.lr.ph.i28.i leaq 12(%rbx), %rax movq %rbx, %rdi jmp .LBB4_46 .p2align 4, 0x90 .LBB4_44: # %_ZSt25__unguarded_linear_insertIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops14_Val_comp_iterIPFbS2_S2_EEEEvT_T0_.exit.i42.i # in Loop: Header=BB4_46 Depth=1 movq %rax, (%rdx) movl %ecx, 8(%rdx) .LBB4_45: # in Loop: Header=BB4_46 Depth=1 leaq 12(%r14), %rax movq %r14, %rdi cmpq %r15, %rax je .LBB4_74 .LBB4_46: # =>This Loop Header: Depth=1 # Child Loop BB4_59 Depth 2 movq %rax, %r14 movq 12(%rdi), %rax movq (%rbx), %rcx cmpl %ecx, %eax jne .LBB4_50 # %bb.47: # in Loop: Header=BB4_46 Depth=1 shrq $32, %rcx movq %rax, %rdx shrq $32, %rdx cmpq %rcx, %rdx sete %sil cmpl %ecx, %edx setl %cl orb %sil, %cl testb %cl, %cl jne .LBB4_51 .LBB4_48: # in Loop: Header=BB4_46 Depth=1 movq (%rdi), %rcx cmpl %ecx, %eax jne .LBB4_54 # %bb.49: # in Loop: Header=BB4_46 Depth=1 shrq $32, %rcx movq %rax, %rdx shrq $32, %rdx cmpq %rcx, %rdx sete %r8b cmpl %ecx, %edx setl %sil orb %r8b, %sil jmp .LBB4_55 .p2align 4, 0x90 .LBB4_50: # in Loop: Header=BB4_46 Depth=1 setl %cl testb %cl, %cl je .LBB4_48 .LBB4_51: # in Loop: Header=BB4_46 Depth=1 movl 8(%r14), %eax movl %eax, 56(%rsp) movq (%r14), %rax movq %rax, 48(%rsp) movq %r14, %rdx subq %rbx, %rdx cmpq $13, %rdx jl .LBB4_61 # %bb.52: # in Loop: Header=BB4_46 Depth=1 subq %rdx, %rdi addq $24, %rdi movq %rbx, %rsi callq memmove@PLT .LBB4_53: # %_ZSt13move_backwardIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEES7_ET0_T_S9_S8_.exit.i53.i # in Loop: Header=BB4_46 Depth=1 movl 56(%rsp), %eax movl %eax, 8(%rbx) movq 48(%rsp), %rax movq %rax, (%rbx) jmp .LBB4_45 .p2align 4, 0x90 .LBB4_54: # in Loop: Header=BB4_46 Depth=1 setl %sil .LBB4_55: # %_Z19compareTwoEdgePairs9edgepairsS_.exit189 # in Loop: Header=BB4_46 Depth=1 movl 20(%rdi), %ecx movq %r14, %rdx testb %sil, %sil je .LBB4_44 # %bb.56: # %.lr.ph.i.i46.i.preheader # in Loop: Header=BB4_46 Depth=1 movq %rax, %rsi shrq $32, %rsi movq %r14, %rdx jmp .LBB4_59 .p2align 4, 0x90 .LBB4_57: # in Loop: Header=BB4_59 Depth=2 shrq $32, %rdi cmpq %rdi, %rsi sete %r8b cmpl %edi, %esi setl %dil orb %r8b, %dil .LBB4_58: # %_Z19compareTwoEdgePairs9edgepairsS_.exit # in Loop: Header=BB4_59 Depth=2 addq $-12, %rdx testb %dil, %dil je .LBB4_44 .LBB4_59: # %.lr.ph.i.i46.i # Parent Loop BB4_46 Depth=1 # => This Inner Loop Header: Depth=2 movl -4(%rdx), %edi movl %edi, 8(%rdx) movq -24(%rdx), %rdi movq -12(%rdx), %r8 movq %r8, (%rdx) cmpl %edi, %eax je .LBB4_57 # %bb.60: # in Loop: Header=BB4_59 Depth=2 setl %dil jmp .LBB4_58 .LBB4_61: # in Loop: Header=BB4_46 Depth=1 cmpq $12, %rdx jne .LBB4_53 # %bb.62: # in Loop: Header=BB4_46 Depth=1 movl 8(%rbx), %eax movl %eax, 20(%rdi) movq (%rbx), %rax movq %rax, 12(%rdi) jmp .LBB4_53 .LBB4_63: # %.lr.ph.i10.i.preheader leaq 192(%rbx), %rax jmp .LBB4_65 .p2align 4, 0x90 .LBB4_64: # %_ZSt25__unguarded_linear_insertIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops14_Val_comp_iterIPFbS2_S2_EEEEvT_T0_.exit.i16.i # in Loop: Header=BB4_65 Depth=1 movq %rcx, (%rsi) movl %edx, 8(%rsi) addq $12, %rax cmpq %r15, %rax je .LBB4_74 .LBB4_65: # %.lr.ph.i10.i # =>This Loop Header: Depth=1 # Child Loop BB4_72 Depth 2 movq -12(%rax), %rdx movq (%rax), %rcx cmpl %edx, %ecx jne .LBB4_67 # %bb.66: # in Loop: Header=BB4_65 Depth=1 shrq $32, %rdx movq %rcx, %rsi shrq $32, %rsi cmpq %rdx, %rsi sete %r8b cmpl %edx, %esi setl %dil orb %r8b, %dil jmp .LBB4_68 .p2align 4, 0x90 .LBB4_67: # in Loop: Header=BB4_65 Depth=1 setl %dil .LBB4_68: # %_Z19compareTwoEdgePairs9edgepairsS_.exit222 # in Loop: Header=BB4_65 Depth=1 movl 8(%rax), %edx movq %rax, %rsi testb %dil, %dil je .LBB4_64 # %bb.69: # %.lr.ph.i.i19.i.preheader # in Loop: Header=BB4_65 Depth=1 movq %rcx, %rdi shrq $32, %rdi movq %rax, %rsi jmp .LBB4_72 .p2align 4, 0x90 .LBB4_70: # in Loop: Header=BB4_72 Depth=2 shrq $32, %r8 cmpq %r8, %rdi sete %r9b cmpl %r8d, %edi setl %r8b orb %r9b, %r8b .LBB4_71: # %_Z19compareTwoEdgePairs9edgepairsS_.exit211 # in Loop: Header=BB4_72 Depth=2 addq $-12, %rsi testb %r8b, %r8b je .LBB4_64 .LBB4_72: # %.lr.ph.i.i19.i # Parent Loop BB4_65 Depth=1 # => This Inner Loop Header: Depth=2 movl -4(%rsi), %r8d movl %r8d, 8(%rsi) movq -24(%rsi), %r8 movq -12(%rsi), %r9 movq %r9, (%rsi) cmpl %r8d, %ecx je .LBB4_70 # %bb.73: # in Loop: Header=BB4_72 Depth=2 setl %r8b jmp .LBB4_71 .LBB4_74: # %_ZSt4sortIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEEPFbS2_S2_EEvT_SA_T0_.exit cmpl $0, 8(%rsp) js .LBB4_77 # %bb.75: # %.lr.ph302 movq 32(%rsp), %rax # 8-byte Reload movq 8(%rax), %rax movq $-1, %rcx .p2align 4, 0x90 .LBB4_76: # =>This Inner Loop Header: Depth=1 movl $0, 4(%rax,%rcx,4) movslq 8(%rsp), %rdx incq %rcx cmpq %rdx, %rcx jl .LBB4_76 .LBB4_77: # %._crit_edge303 movq 32(%rsp), %rax # 8-byte Reload movq 8(%rax), %rax movl $0, (%rax) cmpl $0, 12(%rsp) jle .LBB4_80 # %bb.78: # %.lr.ph306 movq 32(%rsp), %rdx # 8-byte Reload movq 16(%rdx), %rcx movq 24(%rdx), %rdx leaq 8(%rbx), %rsi xorl %edi, %edi .p2align 4, 0x90 .LBB4_79: # =>This Inner Loop Header: Depth=1 movl -4(%rsi), %r8d movl %r8d, (%rcx,%rdi,4) movl (%rsi), %r8d movl %r8d, (%rdx,%rdi,4) incq %rdi movslq 12(%rsp), %r8 addq %r8, %r8 addq $12, %rsi cmpq %r8, %rdi jl .LBB4_79 .LBB4_80: # %.preheader289 cmpl $0, 12(%rsp) jle .LBB4_83 # %bb.81: # %.lr.ph308.preheader xorl %ecx, %ecx movq %rbx, %rdx .p2align 4, 0x90 .LBB4_82: # %.lr.ph308 # =>This Inner Loop Header: Depth=1 movslq (%rdx), %rsi incl 4(%rax,%rsi,4) incq %rcx movslq 12(%rsp), %rsi addq %rsi, %rsi addq $12, %rdx cmpq %rsi, %rcx jl .LBB4_82 .LBB4_83: # %.preheader288 cmpl $0, 8(%rsp) jle .LBB4_86 # %bb.84: # %.lr.ph310.preheader xorl %ecx, %ecx .p2align 4, 0x90 .LBB4_85: # %.lr.ph310 # =>This Inner Loop Header: Depth=1 movl (%rax,%rcx,4), %edx addl %edx, 4(%rax,%rcx,4) incq %rcx movslq 8(%rsp), %rdx cmpq %rdx, %rcx jl .LBB4_85 .LBB4_86: # %._crit_edge311 .Ltmp17: movq 32(%rsp), %rdi # 8-byte Reload callq _Z3funP5Graph movq %rax, 64(%rsp) # 8-byte Spill .Ltmp18: # %bb.87: xorl %r12d, %r12d .Ltmp20: movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $49, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp21: # %bb.88: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit.preheader cmpl $0, 8(%rsp) jle .LBB4_102 # %bb.89: # %.lr.ph314.preheader movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, 44(%rsp) # 4-byte Spill xorl %r12d, %r12d .p2align 4, 0x90 .LBB4_90: # %.lr.ph314 # =>This Inner Loop Header: Depth=1 movq 64(%rsp), %rax # 8-byte Reload movss (%rax,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, 28(%rsp) # 4-byte Spill .Ltmp22: movl $_ZSt4cout, %edi movl $.L.str.4, %esi movl $5, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp23: # %bb.91: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit93 # in Loop: Header=BB4_90 Depth=1 .Ltmp24: movl $_ZSt4cout, %edi movl %r12d, %esi callq _ZNSolsEi .Ltmp25: # %bb.92: # in Loop: Header=BB4_90 Depth=1 .Ltmp26: movq %rax, %r14 movl $.L.str.5, %esi movl $3, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp27: # %bb.93: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit95 # in Loop: Header=BB4_90 Depth=1 movq 64(%rsp), %rax # 8-byte Reload movss (%rax,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp28: movq %r14, %rdi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp29: # %bb.94: # %_ZNSolsEf.exit # in Loop: Header=BB4_90 Depth=1 movq %rax, %r13 movq (%rax), %rax movq -24(%rax), %rax movq 240(%r13,%rax), %r14 testq %r14, %r14 je .LBB4_173 # %bb.95: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i # in Loop: Header=BB4_90 Depth=1 cmpb $0, 56(%r14) je .LBB4_97 # %bb.96: # in Loop: Header=BB4_90 Depth=1 movzbl 67(%r14), %eax jmp .LBB4_99 .p2align 4, 0x90 .LBB4_97: # in Loop: Header=BB4_90 Depth=1 .Ltmp30: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv .Ltmp31: # %bb.98: # %.noexc130 # in Loop: Header=BB4_90 Depth=1 movq (%r14), %rax .Ltmp32: movq %r14, %rdi movl $10, %esi callq *48(%rax) .Ltmp33: .LBB4_99: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i # in Loop: Header=BB4_90 Depth=1 .Ltmp34: movsbl %al, %esi movq %r13, %rdi callq _ZNSo3putEc .Ltmp35: # %bb.100: # %.noexc132 # in Loop: Header=BB4_90 Depth=1 .Ltmp36: movq %rax, %rdi callq _ZNSo5flushEv .Ltmp37: # %bb.101: # %_ZNSolsEPFRSoS_E.exit # in Loop: Header=BB4_90 Depth=1 movss 28(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero maxss 44(%rsp), %xmm0 # 4-byte Folded Reload incq %r12 movslq 8(%rsp), %rax movss %xmm0, 44(%rsp) # 4-byte Spill cmpq %rax, %r12 jl .LBB4_90 jmp .LBB4_103 .LBB4_102: movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero .LBB4_103: # %.preheader movss %xmm0, 28(%rsp) # 4-byte Spill cmpl $0, 8(%rsp) jle .LBB4_124 # %bb.104: # %.lr.ph319.preheader xorl %r14d, %r14d movabsq $2305843009213693951, %rdx # imm = 0x1FFFFFFFFFFFFFFF xorl %eax, %eax xorl %r15d, %r15d xorl %ebp, %ebp jmp .LBB4_108 .p2align 4, 0x90 .LBB4_105: # in Loop: Header=BB4_108 Depth=1 movl %r14d, (%r15) addq $4, %r15 .LBB4_106: # %_ZNSt6vectorIiSaIiEE9push_backERKi.exit # in Loop: Header=BB4_108 Depth=1 movq %rbp, %r12 .LBB4_107: # %_ZNSt6vectorIiSaIiEE9push_backERKi.exit # in Loop: Header=BB4_108 Depth=1 incq %r14 movslq 8(%rsp), %rcx movq %r12, %rbp cmpq %rcx, %r14 jge .LBB4_125 .LBB4_108: # %.lr.ph319 # =>This Inner Loop Header: Depth=1 movq 64(%rsp), %rcx # 8-byte Reload movss 28(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero ucomiss (%rcx,%r14,4), %xmm0 jne .LBB4_106 jp .LBB4_106 # %bb.109: # in Loop: Header=BB4_108 Depth=1 cmpq %rax, %r15 jne .LBB4_105 # %bb.110: # in Loop: Header=BB4_108 Depth=1 subq %rbp, %r15 movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC cmpq %rax, %r15 je .LBB4_175 # %bb.111: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i # in Loop: Header=BB4_108 Depth=1 movq %r15, %r13 sarq $2, %r13 cmpq $1, %r13 movq %r13, %rax adcq $0, %rax leaq (%rax,%r13), %rcx cmpq %rdx, %rcx jb .LBB4_113 # %bb.112: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i # in Loop: Header=BB4_108 Depth=1 movq %rdx, %rcx .LBB4_113: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i # in Loop: Header=BB4_108 Depth=1 movq %rdx, %rbx addq %r13, %rax jb .LBB4_115 # %bb.114: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i # in Loop: Header=BB4_108 Depth=1 movq %rcx, %rbx .LBB4_115: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i # in Loop: Header=BB4_108 Depth=1 testq %rbx, %rbx je .LBB4_118 # %bb.116: # in Loop: Header=BB4_108 Depth=1 leaq (,%rbx,4), %rdi .Ltmp39: callq _Znwm .Ltmp40: # %bb.117: # in Loop: Header=BB4_108 Depth=1 movq %rax, %r12 jmp .LBB4_119 .LBB4_118: # in Loop: Header=BB4_108 Depth=1 xorl %r12d, %r12d .LBB4_119: # %_ZNSt12_Vector_baseIiSaIiEE11_M_allocateEm.exit.i.i # in Loop: Header=BB4_108 Depth=1 movl %r14d, (%r12,%r13,4) testq %r15, %r15 jle .LBB4_121 # %bb.120: # in Loop: Header=BB4_108 Depth=1 movq %r12, %rdi movq %rbp, %rsi movq %r15, %rdx callq memmove@PLT .LBB4_121: # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit.i.i # in Loop: Header=BB4_108 Depth=1 testq %rbp, %rbp je .LBB4_123 # %bb.122: # in Loop: Header=BB4_108 Depth=1 movq %rbp, %rdi callq _ZdlPv .LBB4_123: # %_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.exit.i # in Loop: Header=BB4_108 Depth=1 addq %r12, %r15 addq $4, %r15 leaq (%r12,%rbx,4), %rax movq 16(%rsp), %rbx # 8-byte Reload movabsq $2305843009213693951, %rdx # imm = 0x1FFFFFFFFFFFFFFF jmp .LBB4_107 .LBB4_124: xorl %r12d, %r12d xorl %r15d, %r15d .LBB4_125: # %._crit_edge320 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbp testq %rbp, %rbp je .LBB4_177 # %bb.126: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i135 cmpb $0, 56(%rbp) je .LBB4_128 # %bb.127: movzbl 67(%rbp), %eax jmp .LBB4_130 .LBB4_128: .Ltmp42: movq %rbp, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv .Ltmp43: # %bb.129: # %.noexc140 movq (%rbp), %rax .Ltmp44: movq %rbp, %rdi movl $10, %esi callq *48(%rax) .Ltmp45: .LBB4_130: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i137 .Ltmp46: movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc .Ltmp47: # %bb.131: # %.noexc142 .Ltmp48: movq %rax, %rdi callq _ZNSo5flushEv .Ltmp49: # %bb.132: # %_ZNSolsEPFRSoS_E.exit99 .Ltmp50: movl $_ZSt4cout, %edi movl $.L.str.6, %esi movl $34, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp51: # %bb.133: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit103 movss 28(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp52: movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp53: # %bb.134: # %_ZNSolsEf.exit105 movq %rax, %rbp movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbp,%rax), %r14 testq %r14, %r14 je .LBB4_177 # %bb.135: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i146 cmpb $0, 56(%r14) je .LBB4_137 # %bb.136: movzbl 67(%r14), %eax jmp .LBB4_139 .LBB4_137: .Ltmp54: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv .Ltmp55: # %bb.138: # %.noexc151 movq (%r14), %rax .Ltmp56: movq %r14, %rdi movl $10, %esi callq *48(%rax) .Ltmp57: .LBB4_139: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i148 .Ltmp58: movsbl %al, %esi movq %rbp, %rdi callq _ZNSo3putEc .Ltmp59: # %bb.140: # %.noexc153 .Ltmp60: movq %rax, %rdi callq _ZNSo5flushEv .Ltmp61: # %bb.141: # %_ZNSolsEPFRSoS_E.exit107 .Ltmp62: movl $_ZSt4cout, %edi movl $.L.str.7, %esi movl $47, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp63: # %bb.142: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit109.preheader subq %r12, %r15 je .LBB4_149 # %bb.143: # %.lr.ph324 sarq $2, %r15 leaq -1(%r15), %rbx cmpq $1, %r15 adcq $0, %r15 xorl %r14d, %r14d jmp .LBB4_146 .p2align 4, 0x90 .LBB4_144: # in Loop: Header=BB4_146 Depth=1 .Ltmp68: movl $_ZSt4cout, %edi callq _ZNSolsEi .Ltmp69: .LBB4_145: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit113 # in Loop: Header=BB4_146 Depth=1 incq %r14 cmpq %r14, %r15 je .LBB4_149 .LBB4_146: # =>This Inner Loop Header: Depth=1 movl (%r12,%r14,4), %esi cmpq %r14, %rbx je .LBB4_144 # %bb.147: # in Loop: Header=BB4_146 Depth=1 .Ltmp64: movl $_ZSt4cout, %edi callq _ZNSolsEi .Ltmp65: # %bb.148: # in Loop: Header=BB4_146 Depth=1 .Ltmp66: movl $.L.str.8, %esi movl $3, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp67: jmp .LBB4_145 .LBB4_149: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit109._crit_edge .Ltmp71: movl $_ZSt4cout, %edi movl $.L.str.9, %esi movl $1, %edx movq 16(%rsp), %rbx # 8-byte Reload callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp72: # %bb.150: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit111 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB4_177 # %bb.151: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i157 cmpb $0, 56(%r14) je .LBB4_153 # %bb.152: movzbl 67(%r14), %eax jmp .LBB4_155 .LBB4_153: .Ltmp73: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv .Ltmp74: # %bb.154: # %.noexc162 movq (%r14), %rax .Ltmp75: movq %r14, %rdi movl $10, %esi callq *48(%rax) .Ltmp76: .LBB4_155: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i159 .Ltmp77: movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc .Ltmp78: # %bb.156: # %.noexc164 .Ltmp79: movq %rax, %rdi callq _ZNSo5flushEv .Ltmp80: # %bb.157: # %_ZNSolsEPFRSoS_E.exit115 .Ltmp81: movl $_ZSt4cout, %edi movl $.L.str.10, %esi movl $26, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp82: # %bb.158: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit117 movss device_time_taken(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp83: movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp84: # %bb.159: # %_ZNSolsEf.exit119 movq %rax, %r13 movq (%rax), %rax movq -24(%rax), %rax movq 240(%r13,%rax), %r14 testq %r14, %r14 je .LBB4_177 # %bb.160: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i168 cmpb $0, 56(%r14) je .LBB4_162 # %bb.161: movzbl 67(%r14), %eax jmp .LBB4_164 .LBB4_162: .Ltmp85: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv .Ltmp86: # %bb.163: # %.noexc173 movq (%r14), %rax .Ltmp87: movq %r14, %rdi movl $10, %esi callq *48(%rax) .Ltmp88: .LBB4_164: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i170 .Ltmp89: movsbl %al, %esi movq %r13, %rdi callq _ZNSo3putEc .Ltmp90: # %bb.165: # %.noexc175 .Ltmp91: movq %rax, %rdi callq _ZNSo5flushEv .Ltmp92: # %bb.166: # %_ZNSolsEPFRSoS_E.exit121 movq 64(%rsp), %rdi # 8-byte Reload testq %rdi, %rdi je .LBB4_168 # %bb.167: callq _ZdaPv .LBB4_168: movq 32(%rsp), %rdi # 8-byte Reload callq _ZdlPv testq %r12, %r12 je .LBB4_170 # %bb.169: movq %r12, %rdi callq _ZdlPv .LBB4_170: # %_ZNSt6vectorIiSaIiEED2Ev.exit testq %rbx, %rbx je .LBB4_172 # %bb.171: movq %rbx, %rdi callq _ZdlPv .LBB4_172: # %_ZNSt6vectorI9edgepairsSaIS0_EED2Ev.exit xorl %eax, %eax addq $88, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB4_173: .cfi_def_cfa_offset 144 .Ltmp99: callq _ZSt16__throw_bad_castv .Ltmp100: # %bb.174: # %.noexc129 .LBB4_175: .Ltmp96: movl $.L.str.12, %edi callq _ZSt20__throw_length_errorPKc .Ltmp97: # %bb.176: # %.noexc100 .LBB4_177: # %.invoke .Ltmp93: callq _ZSt16__throw_bad_castv .Ltmp94: # %bb.178: # %.cont .LBB4_179: # %.noexc87 movl $.L.str.11, %edi callq _ZSt20__throw_length_errorPKc .LBB4_180: .Ltmp16: jmp .LBB4_181 .LBB4_182: .Ltmp19: .LBB4_181: movq %rax, %r15 testq %rbx, %rbx je .LBB4_194 jmp .LBB4_196 .LBB4_183: # %.loopexit .Ltmp41: jmp .LBB4_186 .LBB4_184: .Ltmp6: movq %rax, %r15 movq %r12, %rbx jmp .LBB4_196 .LBB4_185: # %.loopexit.split-lp .Ltmp98: .LBB4_186: movq %rax, %r15 movq %rbp, %r12 movq 16(%rsp), %rbx # 8-byte Reload jmp .LBB4_192 .LBB4_187: # %.loopexit.split-lp284 .Ltmp101: movq %rax, %r15 xorl %r12d, %r12d movq 16(%rsp), %rbx # 8-byte Reload jmp .LBB4_192 .LBB4_188: .Ltmp95: movq %rax, %r15 jmp .LBB4_192 .LBB4_189: .Ltmp70: movq %rax, %r15 movq 16(%rsp), %rbx # 8-byte Reload jmp .LBB4_192 .LBB4_190: .Ltmp13: movq %rax, %r15 movq 16(%rsp), %rbx # 8-byte Reload testq %rbx, %rbx je .LBB4_194 jmp .LBB4_196 .LBB4_191: # %.loopexit283 .Ltmp38: movq %rax, %r15 xorl %r12d, %r12d .LBB4_192: testq %r12, %r12 jne .LBB4_195 # %bb.193: # %_ZNSt6vectorIiSaIiEED2Ev.exit125 testq %rbx, %rbx jne .LBB4_196 .LBB4_194: # %_ZNSt6vectorI9edgepairsSaIS0_EED2Ev.exit127 movq %r15, %rdi callq _Unwind_Resume@PLT .LBB4_195: movq %r12, %rdi callq _ZdlPv testq %rbx, %rbx je .LBB4_194 .LBB4_196: # %_ZNSt6vectorI9edgepairsSaIS0_EED2Ev.exit127.sink.split movq %rbx, %rdi callq _ZdlPv movq %r15, %rdi callq _Unwind_Resume@PLT .Lfunc_end4: .size main, .Lfunc_end4-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table4: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp5-.Ltmp0 # Call between .Ltmp0 and .Ltmp5 .uleb128 .Ltmp6-.Lfunc_begin0 # jumps to .Ltmp6 .byte 0 # On action: cleanup .uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp7-.Ltmp5 # Call between .Ltmp5 and .Ltmp7 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp12-.Ltmp7 # Call between .Ltmp7 and .Ltmp12 .uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13 .byte 0 # On action: cleanup .uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15 .uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16 .byte 0 # On action: cleanup .uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Ltmp17-.Ltmp15 # Call between .Ltmp15 and .Ltmp17 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 7 << .uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18 .uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19 .byte 0 # On action: cleanup .uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 8 << .uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21 .uleb128 .Ltmp95-.Lfunc_begin0 # jumps to .Ltmp95 .byte 0 # On action: cleanup .uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 9 << .uleb128 .Ltmp37-.Ltmp22 # Call between .Ltmp22 and .Ltmp37 .uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38 .byte 0 # On action: cleanup .uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 10 << .uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40 .uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41 .byte 0 # On action: cleanup .uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 11 << .uleb128 .Ltmp42-.Ltmp40 # Call between .Ltmp40 and .Ltmp42 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp42-.Lfunc_begin0 # >> Call Site 12 << .uleb128 .Ltmp63-.Ltmp42 # Call between .Ltmp42 and .Ltmp63 .uleb128 .Ltmp95-.Lfunc_begin0 # jumps to .Ltmp95 .byte 0 # On action: cleanup .uleb128 .Ltmp68-.Lfunc_begin0 # >> Call Site 13 << .uleb128 .Ltmp67-.Ltmp68 # Call between .Ltmp68 and .Ltmp67 .uleb128 .Ltmp70-.Lfunc_begin0 # jumps to .Ltmp70 .byte 0 # On action: cleanup .uleb128 .Ltmp71-.Lfunc_begin0 # >> Call Site 14 << .uleb128 .Ltmp92-.Ltmp71 # Call between .Ltmp71 and .Ltmp92 .uleb128 .Ltmp95-.Lfunc_begin0 # jumps to .Ltmp95 .byte 0 # On action: cleanup .uleb128 .Ltmp99-.Lfunc_begin0 # >> Call Site 15 << .uleb128 .Ltmp100-.Ltmp99 # Call between .Ltmp99 and .Ltmp100 .uleb128 .Ltmp101-.Lfunc_begin0 # jumps to .Ltmp101 .byte 0 # On action: cleanup .uleb128 .Ltmp96-.Lfunc_begin0 # >> Call Site 16 << .uleb128 .Ltmp97-.Ltmp96 # Call between .Ltmp96 and .Ltmp97 .uleb128 .Ltmp98-.Lfunc_begin0 # jumps to .Ltmp98 .byte 0 # On action: cleanup .uleb128 .Ltmp93-.Lfunc_begin0 # >> Call Site 17 << .uleb128 .Ltmp94-.Ltmp93 # Call between .Ltmp93 and .Ltmp94 .uleb128 .Ltmp95-.Lfunc_begin0 # jumps to .Ltmp95 .byte 0 # On action: cleanup .uleb128 .Ltmp94-.Lfunc_begin0 # >> Call Site 18 << .uleb128 .Lfunc_end4-.Ltmp94 # Call between .Ltmp94 and .Lfunc_end4 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .p2align 2, 0x0 # -- End function .section .text._ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_,"axG",@progbits,_ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_,comdat .weak _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_ # -- Begin function _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_ .p2align 4, 0x90 .type _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_,@function _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_: # @_ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $56, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %rbp subq %rdi, %rbp cmpq $193, %rbp jl .LBB5_12 # %bb.1: # %.lr.ph movq %rcx, %r15 movq %rdx, %r12 movq %rsi, %r14 movq %rdi, %rbx leaq 12(%rdi), %rax movq %rax, 16(%rsp) # 8-byte Spill movq $-12, %rax subq %rdi, %rax movq %rax, 40(%rsp) # 8-byte Spill jmp .LBB5_2 .p2align 4, 0x90 .LBB5_11: # %_ZSt27__unguarded_partition_pivotIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEET_SD_SD_T0_.exit # in Loop: Header=BB5_2 Depth=1 movq %r14, %rdi movq 32(%rsp), %rsi # 8-byte Reload movq 24(%rsp), %r12 # 8-byte Reload movq %r12, %rdx movq %r15, %rcx callq _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_ cmpq $192, %rbp jle .LBB5_12 .LBB5_2: # =>This Loop Header: Depth=1 # Child Loop BB5_5 Depth 2 # Child Loop BB5_6 Depth 3 # Child Loop BB5_8 Depth 3 subq $1, %r12 jb .LBB5_3 # %bb.4: # in Loop: Header=BB5_2 Depth=1 movq %r12, 24(%rsp) # 8-byte Spill movq %rbp, %rax movabsq $-6148914691236517205, %rcx # imm = 0xAAAAAAAAAAAAAAAB mulq %rcx shrq $4, %rdx leaq (%rdx,%rdx,2), %rax leaq (%rbx,%rax,4), %rdx leaq -12(%r14), %rcx movq %rbx, %rdi movq 16(%rsp), %r13 # 8-byte Reload movq %r13, %rsi movq %r15, %r8 callq _ZSt22__move_median_to_firstIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_SD_SD_T0_ movq %r14, 32(%rsp) # 8-byte Spill movq %r14, %r12 .p2align 4, 0x90 .LBB5_5: # Parent Loop BB5_2 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB5_6 Depth 3 # Child Loop BB5_8 Depth 3 movq 40(%rsp), %rax # 8-byte Reload leaq (%rax,%r13), %rbp addq $-12, %r13 movq %r13, %r14 .p2align 4, 0x90 .LBB5_6: # Parent Loop BB5_2 Depth=1 # Parent Loop BB5_5 Depth=2 # => This Inner Loop Header: Depth=3 movq 12(%r14), %rdi movl 20(%r14), %esi addq $12, %r14 movq (%rbx), %rdx movl 8(%rbx), %ecx callq *%r15 addq $12, %rbp testb %al, %al jne .LBB5_6 # %bb.7: # %.preheader.i.i.preheader # in Loop: Header=BB5_5 Depth=2 leaq 12(%r14), %r13 .p2align 4, 0x90 .LBB5_8: # %.preheader.i.i # Parent Loop BB5_2 Depth=1 # Parent Loop BB5_5 Depth=2 # => This Inner Loop Header: Depth=3 movq -12(%r12), %rdx movl -4(%r12), %ecx addq $-12, %r12 movq (%rbx), %rdi movl 8(%rbx), %esi callq *%r15 testb %al, %al jne .LBB5_8 # %bb.9: # in Loop: Header=BB5_5 Depth=2 cmpq %r12, %r14 jae .LBB5_11 # %bb.10: # in Loop: Header=BB5_5 Depth=2 movl 8(%r14), %eax movl %eax, 8(%rsp) movq (%r14), %rax movq %rax, (%rsp) movl 8(%r12), %eax movl %eax, 8(%r14) movq (%r12), %rax movq %rax, (%r14) movl 8(%rsp), %eax movl %eax, 8(%r12) movq (%rsp), %rax movq %rax, (%r12) jmp .LBB5_5 .LBB5_3: movq %r15, 48(%rsp) movq %r15, (%rsp) movq %rsp, %rdx movq %rbx, %rdi movq %r14, %rsi callq _ZSt11__make_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_ leaq 48(%rsp), %rdx movq %rbx, %rdi movq %r14, %rsi callq _ZSt11__sort_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_ .LBB5_12: # %.loopexit addq $56, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end5: .size _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_, .Lfunc_end5-_ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElNS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_T0_T1_ .cfi_endproc # -- End function .section .text._ZSt11__sort_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_,"axG",@progbits,_ZSt11__sort_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_,comdat .weak _ZSt11__sort_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_ # -- Begin function _ZSt11__sort_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_ .p2align 4, 0x90 .type _ZSt11__sort_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_,@function _ZSt11__sort_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_: # @_ZSt11__sort_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $56, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdx, 24(%rsp) # 8-byte Spill movq %rsi, %rax subq %rdi, %rax cmpq $13, %rax jl .LBB6_18 # %bb.1: # %.lr.ph.preheader movq %rdi, %r14 jmp .LBB6_4 .p2align 4, 0x90 .LBB6_2: # in Loop: Header=BB6_4 Depth=1 movq %rbp, %r15 .LBB6_3: # %_ZSt10__pop_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_SD_RT0_.exit # in Loop: Header=BB6_4 Depth=1 leaq (%r15,%r15,2), %rax movq %r13, (%r14,%rax,4) movl 12(%rsp), %ecx # 4-byte Reload movl %ecx, 8(%r14,%rax,4) cmpq $12, 40(%rsp) # 8-byte Folded Reload movq 48(%rsp), %rsi # 8-byte Reload jle .LBB6_18 .LBB6_4: # %.lr.ph # =>This Loop Header: Depth=1 # Child Loop BB6_7 Depth 2 # Child Loop BB6_15 Depth 2 movq %rsi, %rax movq -12(%rsi), %rcx movq %rcx, 16(%rsp) # 8-byte Spill movl -4(%rsi), %ecx movl %ecx, 12(%rsp) # 4-byte Spill movl 8(%r14), %ecx movl %ecx, -4(%rsi) movq (%r14), %rcx movq %rcx, -12(%rsi) leaq -12(%rsi), %rax movq %rax, 48(%rsp) # 8-byte Spill movq %rax, %rcx subq %r14, %rcx movq %rcx, %rdx sarq $2, %rdx movabsq $-6148914691236517205, %rax # imm = 0xAAAAAAAAAAAAAAAB imulq %rax, %rdx movq 24(%rsp), %rax # 8-byte Reload movq (%rax), %rbx movq %rcx, 40(%rsp) # 8-byte Spill cmpq $25, %rcx movq %rdx, 32(%rsp) # 8-byte Spill jl .LBB6_9 # %bb.5: # %.lr.ph.i.i.preheader # in Loop: Header=BB6_4 Depth=1 leaq -1(%rdx), %rax shrq $63, %rax leaq (%rdx,%rax), %r12 decq %r12 sarq %r12 xorl %r13d, %r13d jmp .LBB6_7 .p2align 4, 0x90 .LBB6_6: # %.lr.ph.i.i # in Loop: Header=BB6_7 Depth=2 leaq (,%rbp,2), %rax addq %rbp, %rax leaq (%r13,%r13,2), %rcx movq (%r14,%rax,4), %rdx movq %rdx, (%r14,%rcx,4) movl 8(%r14,%rax,4), %eax movl %eax, 8(%r14,%rcx,4) movq %rbp, %r13 cmpq %r12, %rbp jge .LBB6_10 .LBB6_7: # %.lr.ph.i.i # Parent Loop BB6_4 Depth=1 # => This Inner Loop Header: Depth=2 leaq 2(,%r13,2), %r15 leaq (%r15,%r15,2), %rax leaq 1(,%r13,2), %rbp leaq (,%rbp,2), %rcx addq %rbp, %rcx movq (%r14,%rax,4), %rdi movl 8(%r14,%rax,4), %esi movq (%r14,%rcx,4), %rdx movl 8(%r14,%rcx,4), %ecx callq *%rbx testb %al, %al jne .LBB6_6 # %bb.8: # %.lr.ph.i.i # in Loop: Header=BB6_7 Depth=2 movq %r15, %rbp jmp .LBB6_6 .p2align 4, 0x90 .LBB6_9: # in Loop: Header=BB6_4 Depth=1 xorl %ebp, %ebp .LBB6_10: # %._crit_edge.i.i # in Loop: Header=BB6_4 Depth=1 movq 32(%rsp), %rax # 8-byte Reload testb $1, %al jne .LBB6_13 # %bb.11: # in Loop: Header=BB6_4 Depth=1 addq $-2, %rax sarq %rax cmpq %rax, %rbp movq 16(%rsp), %r13 # 8-byte Reload jne .LBB6_14 # %bb.12: # in Loop: Header=BB6_4 Depth=1 leaq (,%rbp,2), %rax addq %rbp, %rax leaq 1(%rbp,%rbp), %rbp leaq (%rbp,%rbp,2), %rcx movl 8(%r14,%rcx,4), %edx movl %edx, 8(%r14,%rax,4) movq (%r14,%rcx,4), %rcx movq %rcx, (%r14,%rax,4) jmp .LBB6_14 .p2align 4, 0x90 .LBB6_13: # in Loop: Header=BB6_4 Depth=1 movq 16(%rsp), %r13 # 8-byte Reload .LBB6_14: # in Loop: Header=BB6_4 Depth=1 testq %rbp, %rbp jle .LBB6_2 .p2align 4, 0x90 .LBB6_15: # %.lr.ph.i.i.i # Parent Loop BB6_4 Depth=1 # => This Inner Loop Header: Depth=2 leaq -1(%rbp), %rax shrq $63, %rax leaq (%rax,%rbp), %r15 decq %r15 sarq %r15 leaq (%r15,%r15,2), %r12 movq (%r14,%r12,4), %rdi movl 8(%r14,%r12,4), %esi movq %r13, %rdx movl 12(%rsp), %ecx # 4-byte Reload callq *%rbx testb %al, %al je .LBB6_2 # %bb.16: # in Loop: Header=BB6_15 Depth=2 leaq (%r14,%r12,4), %rax leaq (,%rbp,2), %rcx addq %rbp, %rcx movl 8(%rax), %edx movl %edx, 8(%r14,%rcx,4) movq (%rax), %rax movq %rax, (%r14,%rcx,4) cmpq $2, %rbp movq %r15, %rbp jg .LBB6_15 jmp .LBB6_3 .LBB6_18: # %._crit_edge addq $56, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end6: .size _ZSt11__sort_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_, .Lfunc_end6-_ZSt11__sort_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_ .cfi_endproc # -- End function .section .text._ZSt11__make_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_,"axG",@progbits,_ZSt11__make_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_,comdat .weak _ZSt11__make_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_ # -- Begin function _ZSt11__make_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_ .p2align 4, 0x90 .type _ZSt11__make_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_,@function _ZSt11__make_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_: # @_ZSt11__make_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $56, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdx, 48(%rsp) # 8-byte Spill subq %rdi, %rsi cmpq $24, %rsi jge .LBB7_1 .LBB7_16: # %.loopexit addq $56, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB7_1: .cfi_def_cfa_offset 112 movq %rdi, %r14 movabsq $-6148914691236517205, %rcx # imm = 0xAAAAAAAAAAAAAAAB movq %rsi, %rax mulq %rcx shrq $3, %rdx leaq -2(%rdx), %rsi movq %rsi, %rax shrq $63, %rax leaq (%rdx,%rax), %rdi addq $-2, %rdi sarq %rdi leaq -1(%rdx), %rax shrq $63, %rax movq %rdx, %rcx movq %rdx, 40(%rsp) # 8-byte Spill leaq (%rdx,%rax), %rbp decq %rbp sarq %rbp sarq %rsi movq %rsi, 32(%rsp) # 8-byte Spill jmp .LBB7_2 .p2align 4, 0x90 .LBB7_11: # in Loop: Header=BB7_2 Depth=1 movq %r12, %r13 .LBB7_15: # %_ZSt13__adjust_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEElS2_NS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_T0_SE_T1_T2_.exit # in Loop: Header=BB7_2 Depth=1 leaq (,%r13,2), %rax addq %r13, %rax movq 24(%rsp), %rdx # 8-byte Reload movq %rdx, (%r14,%rax,4) movl 20(%rsp), %edx # 4-byte Reload movl %edx, 8(%r14,%rax,4) movq %rcx, %rax subq $1, %rax movl $0, %edx cmovbq %rdx, %rax testq %rcx, %rcx movq %rax, %rdi je .LBB7_16 .LBB7_2: # =>This Loop Header: Depth=1 # Child Loop BB7_4 Depth 2 # Child Loop BB7_12 Depth 2 leaq (%rdi,%rdi,2), %rax movq (%r14,%rax,4), %rcx movq %rcx, 24(%rsp) # 8-byte Spill movl 8(%r14,%rax,4), %eax movl %eax, 20(%rsp) # 4-byte Spill movq 48(%rsp), %rax # 8-byte Reload movq (%rax), %r15 movq %rdi, %r12 movq %rdi, 8(%rsp) # 8-byte Spill cmpq %rdi, %rbp jle .LBB7_7 # %bb.3: # %.lr.ph.i.preheader # in Loop: Header=BB7_2 Depth=1 movq 8(%rsp), %r13 # 8-byte Reload jmp .LBB7_4 .p2align 4, 0x90 .LBB7_6: # %.lr.ph.i # in Loop: Header=BB7_4 Depth=2 leaq (%r12,%r12,2), %rax leaq (,%r13,2), %rcx addq %r13, %rcx movq (%r14,%rax,4), %rdx movq %rdx, (%r14,%rcx,4) movl 8(%r14,%rax,4), %eax movl %eax, 8(%r14,%rcx,4) movq %r12, %r13 cmpq %rbp, %r12 jge .LBB7_7 .LBB7_4: # %.lr.ph.i # Parent Loop BB7_2 Depth=1 # => This Inner Loop Header: Depth=2 leaq 2(,%r13,2), %rbx leaq (%rbx,%rbx,2), %rax leaq 1(,%r13,2), %r12 leaq (%r12,%r12,2), %rcx movq (%r14,%rax,4), %rdi movl 8(%r14,%rax,4), %esi movq (%r14,%rcx,4), %rdx movl 8(%r14,%rcx,4), %ecx callq *%r15 testb %al, %al jne .LBB7_6 # %bb.5: # %.lr.ph.i # in Loop: Header=BB7_4 Depth=2 movq %rbx, %r12 jmp .LBB7_6 .p2align 4, 0x90 .LBB7_7: # %._crit_edge.i # in Loop: Header=BB7_2 Depth=1 testb $1, 40(%rsp) # 1-byte Folded Reload jne .LBB7_10 # %bb.8: # %._crit_edge.i # in Loop: Header=BB7_2 Depth=1 cmpq 32(%rsp), %r12 # 8-byte Folded Reload jne .LBB7_10 # %bb.9: # in Loop: Header=BB7_2 Depth=1 leaq (%r12,%r12,2), %rax leaq 1(,%r12,2), %r12 leaq (%r12,%r12,2), %rcx movl 8(%r14,%rcx,4), %edx movl %edx, 8(%r14,%rax,4) movq (%r14,%rcx,4), %rcx movq %rcx, (%r14,%rax,4) .LBB7_10: # in Loop: Header=BB7_2 Depth=1 movq 8(%rsp), %rcx # 8-byte Reload cmpq %rcx, %r12 jle .LBB7_11 .p2align 4, 0x90 .LBB7_12: # %.lr.ph.i.i # Parent Loop BB7_2 Depth=1 # => This Inner Loop Header: Depth=2 leaq -1(%r12), %rax shrq $63, %rax leaq (%r12,%rax), %r13 decq %r13 sarq %r13 leaq (,%r13,2), %rbx addq %r13, %rbx movq (%r14,%rbx,4), %rdi movl 8(%r14,%rbx,4), %esi movq 24(%rsp), %rdx # 8-byte Reload movl 20(%rsp), %ecx # 4-byte Reload callq *%r15 testb %al, %al je .LBB7_13 # %bb.14: # in Loop: Header=BB7_12 Depth=2 leaq (%r14,%rbx,4), %rax leaq (%r12,%r12,2), %rcx movl 8(%rax), %edx movl %edx, 8(%r14,%rcx,4) movq (%rax), %rax movq %rax, (%r14,%rcx,4) movq %r13, %r12 movq 8(%rsp), %rcx # 8-byte Reload cmpq %rcx, %r13 jg .LBB7_12 jmp .LBB7_15 .p2align 4, 0x90 .LBB7_13: # in Loop: Header=BB7_2 Depth=1 movq %r12, %r13 movq 8(%rsp), %rcx # 8-byte Reload jmp .LBB7_15 .Lfunc_end7: .size _ZSt11__make_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_, .Lfunc_end7-_ZSt11__make_heapIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_RT0_ .cfi_endproc # -- End function .section .text._ZSt22__move_median_to_firstIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_SD_SD_T0_,"axG",@progbits,_ZSt22__move_median_to_firstIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_SD_SD_T0_,comdat .weak _ZSt22__move_median_to_firstIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_SD_SD_T0_ # -- Begin function _ZSt22__move_median_to_firstIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_SD_SD_T0_ .p2align 4, 0x90 .type _ZSt22__move_median_to_firstIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_SD_SD_T0_,@function _ZSt22__move_median_to_firstIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_SD_SD_T0_: # @_ZSt22__move_median_to_firstIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_SD_SD_T0_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $16, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %r8, %r13 movq %rcx, %r14 movq %rdx, %r15 movq %rsi, %r12 movq %rdi, %rbx movq (%rsi), %rdi movl 8(%rsi), %esi movq (%rdx), %rdx movl 8(%r15), %ecx callq *%r8 movq (%r14), %rdx movl 8(%r14), %ecx testb %al, %al je .LBB8_4 # %bb.1: movq (%r15), %rdi movl 8(%r15), %esi callq *%r13 testb %al, %al jne .LBB8_7 # %bb.2: movq (%r12), %rdi movl 8(%r12), %esi movq (%r14), %rdx movl 8(%r14), %ecx callq *%r13 testb %al, %al je .LBB8_5 jmp .LBB8_3 .LBB8_4: movq (%r12), %rdi movl 8(%r12), %esi callq *%r13 testb %al, %al je .LBB8_6 .LBB8_5: movl 8(%rbx), %eax movl %eax, 8(%rsp) movq (%rbx), %rax movq %rax, (%rsp) movl 8(%r12), %eax movl %eax, 8(%rbx) movq (%r12), %rax movq %rax, (%rbx) movl 8(%rsp), %eax movl %eax, 8(%r12) movq (%rsp), %rax movq %rax, (%r12) jmp .LBB8_8 .LBB8_6: movq (%r15), %rdi movl 8(%r15), %esi movq (%r14), %rdx movl 8(%r14), %ecx callq *%r13 testb %al, %al je .LBB8_7 .LBB8_3: movl 8(%rbx), %eax movl %eax, 8(%rsp) movq (%rbx), %rax movq %rax, (%rsp) movl 8(%r14), %eax movl %eax, 8(%rbx) movq (%r14), %rax movq %rax, (%rbx) movl 8(%rsp), %eax movl %eax, 8(%r14) movq (%rsp), %rax movq %rax, (%r14) jmp .LBB8_8 .LBB8_7: movl 8(%rbx), %eax movl %eax, 8(%rsp) movq (%rbx), %rax movq %rax, (%rsp) movl 8(%r15), %eax movl %eax, 8(%rbx) movq (%r15), %rax movq %rax, (%rbx) movl 8(%rsp), %eax movl %eax, 8(%r15) movq (%rsp), %rax movq %rax, (%r15) .LBB8_8: addq $16, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end8: .size _ZSt22__move_median_to_firstIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_SD_SD_T0_, .Lfunc_end8-_ZSt22__move_median_to_firstIN9__gnu_cxx17__normal_iteratorIP9edgepairsSt6vectorIS2_SaIS2_EEEENS0_5__ops15_Iter_comp_iterIPFbS2_S2_EEEEvT_SD_SD_SD_T0_ .cfi_endproc # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB9_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB9_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9cal_deltaP5GraphPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end9: .size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB10_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB10_2: retq .Lfunc_end10: .size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor .cfi_endproc # -- End function .type device_time_taken,@object # @device_time_taken .bss .globl device_time_taken .p2align 2, 0x0 device_time_taken: .long 0x00000000 # float 0 .size device_time_taken, 4 .type _Z9cal_deltaP5GraphPi,@object # @_Z9cal_deltaP5GraphPi .section .rodata,"a",@progbits .globl _Z9cal_deltaP5GraphPi .p2align 3, 0x0 _Z9cal_deltaP5GraphPi: .quad _Z24__device_stub__cal_deltaP5GraphPi .size _Z9cal_deltaP5GraphPi, 8 .type _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_,@object # @_Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .globl _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .p2align 3, 0x0 _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_: .quad _Z21__device_stub__kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .size _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "r" .size .L.str, 2 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "input.txt file failed to open." .size .L.str.1, 31 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "%d" .size .L.str.2, 3 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Betweeness Centrality of all the nodes(vertices)\n" .size .L.str.3, 50 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Node " .size .L.str.4, 6 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz " : " .size .L.str.5, 4 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "\nMaximum Betweenness Centrality = " .size .L.str.6, 35 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Vertices with Maximum Betweenness Centrality: [" .size .L.str.7, 48 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz " , " .size .L.str.8, 4 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "]" .size .L.str.9, 2 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Total device time taken : " .size .L.str.10, 27 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "cannot create std::vector larger than max_size()" .size .L.str.11, 49 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz "vector::_M_realloc_insert" .size .L.str.12, 26 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9cal_deltaP5GraphPi" .size .L__unnamed_1, 22 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_" .size .L__unnamed_2, 45 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z19compareTwoEdgePairs9edgepairsS_ .addrsig_sym _Z24__device_stub__cal_deltaP5GraphPi .addrsig_sym _Z21__device_stub__kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .addrsig_sym __gxx_personality_v0 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Unwind_Resume .addrsig_sym device_time_taken .addrsig_sym _Z9cal_deltaP5GraphPi .addrsig_sym _Z6kernelP5GraphPiS1_S1_S1_PfS1_S1_S1_S2_S1_ .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
14,321
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code for sm_80 Function : _Z6squarePfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R4, SR_TID.X ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; LDG.E R2, [R2.64] ; IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; FMUL R7, R2, R2 ; STG.E [R4.64], R7 ; EXIT ; BRA 0xa0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000fff70_00000000-6_a254cd18934b0c19043554c646e46155a2f5fa09.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z27__device_stub__Z6squarePfS_PfS_ .type _Z27__device_stub__Z6squarePfS_PfS_, @function _Z27__device_stub__Z6squarePfS_PfS_: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z6squarePfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_ .globl _Z6squarePfS_ .type _Z6squarePfS_, @function _Z6squarePfS_: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z6squarePfS_PfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z6squarePfS_, .-_Z6squarePfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "\t" .LC1: .string "\n" .LC10: .string "%f" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 addq $-128, %rsp .cfi_def_cfa_offset 176 movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax movl $0x00000000, 48(%rsp) movl $0x3f800000, 52(%rsp) movl $0x40000000, 56(%rsp) movl $0x40400000, 60(%rsp) movl $0x40800000, 64(%rsp) movl $0x40a00000, 68(%rsp) movl $0x40c00000, 72(%rsp) movl $0x40e00000, 76(%rsp) leaq 8(%rsp), %rdi movl $32, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $32, %esi call cudaMalloc@PLT leaq 48(%rsp), %rsi movl $1, %ecx movl $32, %edx movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $8, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $0, %r9d movl $0, %r8d movq 36(%rsp), %rdx movl $1, %ecx movq 24(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L19 .L12: leaq 80(%rsp), %rdi movl $2, %ecx movl $32, %edx movq 16(%rsp), %rsi call cudaMemcpy@PLT movl $0, %ebx leaq 80(%rsp), %r14 leaq .LC10(%rip), %r13 leaq .LC1(%rip), %r12 leaq .LC0(%rip), %rbp .L14: pxor %xmm0, %xmm0 cvtss2sd (%r14,%rbx,4), %xmm0 movq %r13, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl %ebx, %edx sarl $31, %edx shrl $30, %edx leal (%rdx,%rbx), %eax andl $3, %eax subl %edx, %eax cmpl $3, %eax movq %rbp, %rsi cmove %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $1, %rbx cmpq $8, %rbx jne .L14 movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 120(%rsp), %rax subq %fs:40, %rax jne .L20 movl $0, %eax subq $-128, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state movq 8(%rsp), %rsi movq 16(%rsp), %rdi call _Z27__device_stub__Z6squarePfS_PfS_ jmp .L12 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC11: .string "_Z6squarePfS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC11(%rip), %rdx movq %rdx, %rcx leaq _Z6squarePfS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6squarePfS_ ; -- Begin function _Z6squarePfS_ .globl _Z6squarePfS_ .p2align 8 .type _Z6squarePfS_,@function _Z6squarePfS_: ; @_Z6squarePfS_ ; %bb.0: s_load_b128 s[0:3], s[0:1], 0x0 v_lshlrev_b32_e32 v0, 2, v0 s_waitcnt lgkmcnt(0) global_load_b32 v1, v0, s[2:3] s_waitcnt vmcnt(0) v_mul_f32_e32 v1, v1, v1 global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6squarePfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 4 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6squarePfS_, .Lfunc_end0-_Z6squarePfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 52 ; NumSgprs: 4 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 4 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6squarePfS_ .private_segment_fixed_size: 0 .sgpr_count: 4 .sgpr_spill_count: 0 .symbol: _Z6squarePfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "a254cd18934b0c19043554c646e46155a2f5fa09.hip" .globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_ .p2align 4, 0x90 .type _Z21__device_stub__squarePfS_,@function _Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z6squarePfS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z21__device_stub__squarePfS_, .Lfunc_end0-_Z21__device_stub__squarePfS_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $152, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 movss %xmm0, 112(%rsp,%rax,4) incq %rax cmpq $8, %rax jne .LBB1_1 # %bb.2: leaq 8(%rsp), %rdi movl $32, %esi callq hipMalloc movq %rsp, %rdi movl $32, %esi callq hipMalloc movq 8(%rsp), %rdi leaq 112(%rsp), %rsi movl $32, %edx movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 7(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq (%rsp), %rax movq 8(%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6squarePfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: movq (%rsp), %rsi leaq 80(%rsp), %rdi movl $32, %edx movl $2, %ecx callq hipMemcpy movl $.L.str.2, %ebx xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 movss 80(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str, %edi movb $1, %al callq printf movl %r14d, %eax notl %eax testb $3, %al movl $.L.str.1, %edi cmoveq %rbx, %rdi xorl %eax, %eax callq printf incq %r14 cmpq $8, %r14 jne .LBB1_5 # %bb.6: movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree xorl %eax, %eax addq $152, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6squarePfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z6squarePfS_,@object # @_Z6squarePfS_ .section .rodata,"a",@progbits .globl _Z6squarePfS_ .p2align 3, 0x0 _Z6squarePfS_: .quad _Z21__device_stub__squarePfS_ .size _Z6squarePfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%f" .size .L.str, 3 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "\t" .size .L.str.1, 2 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "\n" .size .L.str.2, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z6squarePfS_" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__squarePfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z6squarePfS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
383
3,153
1,675
2,990
142
code for sm_80 Function : _Z15mute_directwaveiiffffiiiiPfS_S_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; ULDC.64 UR4, c[0x0][0x160] ; UIMAD UR4, UR5, UR4, URZ ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R2, UR4, PT ; @P0 EXIT ; IABS R3, c[0x0][0x164] ; BSSY B0, 0x2e0 ; I2F.RP R0, R3 ; MUFU.RCP R0, R0 ; IADD3 R4, R0, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; IMAD.MOV R6, RZ, RZ, -R5 ; IMAD R7, R6, R3, RZ ; IABS R6, R2 ; IMAD.HI.U32 R5, R5, R7, R4 ; IMAD.HI.U32 R5, R5, R6, RZ ; IMAD.MOV R0, RZ, RZ, -R5 ; IMAD R0, R3, R0, R6 ; ISETP.GT.U32.AND P1, PT, R3, R0, PT ; @!P1 IMAD.IADD R0, R0, 0x1, -R3 ; @!P1 IADD3 R5, R5, 0x1, RZ ; ISETP.NE.AND P1, PT, RZ, c[0x0][0x164], PT ; ISETP.GE.U32.AND P0, PT, R0, R3, PT ; LOP3.LUT R0, R2, c[0x0][0x164], RZ, 0x3c, !PT ; ISETP.GE.AND P2, PT, R0, RZ, PT ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x184] ; IADD3 R0, -R0, 0x1, RZ ; @P0 IADD3 R5, R5, 0x1, RZ ; @!P2 IMAD.MOV R5, RZ, RZ, -R5 ; @!P1 LOP3.LUT R5, RZ, c[0x0][0x164], RZ, 0x33, !PT ; IADD3 R5, R5, -c[0x0][0x178], RZ ; IMAD R5, R0, c[0x0][0x17c], R5 ; MOV R0, 0x2d0 ; IABS R6, R5 ; I2F R3, R6 ; FMUL R3, R3, c[0x0][0x170] ; F2F.F64.F32 R24, R3 ; DADD R4, -RZ, |R24| ; IMAD.MOV.U32 R10, RZ, RZ, R4 ; IMAD.MOV.U32 R8, RZ, RZ, R5 ; CALL.REL.NOINC 0x22c0 ; BSYNC B0 ; DADD R4, R24, 2 ; I2F R26, c[0x0][0x180] ; FSETP.NEU.AND P0, PT, R3, RZ, PT ; BSSY B0, 0x440 ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; ISETP.NE.AND P1, PT, R4, 0x7ff00000, PT ; IMAD.MOV.U32 R4, RZ, RZ, R8 ; @!P0 CS2R R4, SRZ ; FMUL R26, R26, c[0x0][0x174] ; @P1 BRA 0x430 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x420 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R24, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R24, 0x7ff00000, P0 ; @P0 BRA 0x430 ; IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x7ff00000 ; BRA 0x430 ; DADD R4, R24, 2 ; BSYNC B0 ; F2F.F64.F32 R24, R26 ; BSSY B0, 0x4c0 ; MOV R0, 0x4b0 ; DADD R6, -RZ, |R24| ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; IMAD.MOV.U32 R8, RZ, RZ, R7 ; CALL.REL.NOINC 0x22c0 ; BSYNC B0 ; DADD R6, R24, 2 ; FSETP.NEU.AND P1, PT, R26, RZ, PT ; FSETP.NEU.AND P0, PT, R3, 1, PT ; FSEL R4, R4, RZ, P0 ; FSEL R5, R5, 1.875, P0 ; LOP3.LUT R6, R7, 0x7ff00000, RZ, 0xc0, !PT ; @!P1 CS2R R8, SRZ ; ISETP.NE.AND P2, PT, R6, 0x7ff00000, PT ; @P2 BRA 0x5f0 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x5e0 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R24, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R24, 0x7ff00000, P0 ; @P0 BRA 0x5f0 ; IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; IMAD.MOV.U32 R9, RZ, RZ, 0x7ff00000 ; BRA 0x5f0 ; DADD R8, R24, 2 ; IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x198] ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x19c] ; LDG.E R3, [R14.64+0x4] ; IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x190] ; IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x194] ; LDG.E R7, [R12.64+0x4] ; IABS R18, c[0x0][0x164] ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x188] ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x18c] ; I2F.RP R0, R18 ; LDG.E R6, [R10.64+0x4] ; FSETP.NEU.AND P2, PT, R26, 1, PT ; ISETP.GE.AND P1, PT, R2, RZ, PT ; FSEL R8, R8, RZ, P2 ; FSEL R9, R9, 1.875, P2 ; ISETP.NE.AND P2, PT, RZ, c[0x0][0x164], PT ; IABS R10, R2 ; MUFU.RCP R0, R0 ; DADD R4, R4, R8 ; IMAD.MOV.U32 R8, RZ, RZ, 0x40000000 ; IADD3 R16, R0, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R17, R16 ; IMAD.MOV.U32 R16, RZ, RZ, RZ ; IMAD.MOV R15, RZ, RZ, -R17 ; IMAD R13, R15, R18, RZ ; IMAD.HI.U32 R13, R17, R13, R16 ; IMAD.HI.U32 R13, R13, R10, RZ ; IMAD.MOV R13, RZ, RZ, -R13 ; IMAD R13, R18, R13, R10 ; ISETP.GT.U32.AND P0, PT, R18, R13, PT ; @!P0 IMAD.IADD R13, R13, 0x1, -R18 ; ISETP.GT.U32.AND P0, PT, R18, R13, PT ; @!P0 IMAD.IADD R13, R13, 0x1, -R18 ; FMUL R0, R3.reuse, 0.63661974668502807617 ; FSETP.GE.AND P0, PT, |R3|, 105615, PT ; F2I.NTZ R14, R0 ; FFMA R7, R7, R8, 1 ; IMAD.MOV.U32 R0, RZ, RZ, R13 ; @!P1 IMAD.MOV R0, RZ, RZ, -R0 ; @!P2 LOP3.LUT R0, RZ, c[0x0][0x164], RZ, 0x33, !PT ; I2F R10, R14 ; FFMA R9, R10, -1.5707962512969970703, R3 ; FFMA R9, R10, -7.5497894158615963534e-08, R9 ; FFMA R9, R10, -5.3903029534742383927e-15, R9 ; @!P0 BRA 0xf60 ; FSETP.NEU.AND P0, PT, |R3|, +INF , PT ; @!P0 BRA 0xf40 ; SHF.R.U32.HI R8, RZ, 0x17, R3 ; IMAD.SHL.U32 R9, R3, 0x100, RZ ; ULDC.64 UR6, c[0x4][0x8] ; IMAD.MOV.U32 R13, RZ, RZ, RZ ; LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R23, RZ, RZ, RZ ; LOP3.LUT R16, R9, 0x80000000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R17, RZ, RZ, RZ ; IADD3 R15, R8, -0x80, RZ ; IMAD.MOV.U32 R24, RZ, RZ, RZ ; SHF.R.U32.HI R14, RZ, 0x5, R15 ; IMAD.U32 R9, RZ, RZ, UR7 ; IMAD.U32 R8, RZ, RZ, UR6 ; LDG.E.CONSTANT R9, [R8.64] ; IADD3 R17, R17, 0x1, RZ ; UIADD3 UR6, UP0, UR6, 0x4, URZ ; ISETP.EQ.AND P0, PT, R24.reuse, RZ, PT ; ISETP.EQ.AND P5, PT, R24.reuse, 0x4, PT ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; ISETP.EQ.AND P4, PT, R24.reuse, 0x8, PT ; ISETP.EQ.AND P3, PT, R24.reuse, 0xc, PT ; ISETP.EQ.AND P2, PT, R24, 0x10, PT ; ISETP.EQ.AND P1, PT, R24.reuse, 0x14, PT ; IADD3 R24, R24, 0x4, RZ ; IMAD.WIDE.U32 R10, R9, R16, RZ ; IADD3 R10, P6, R10, R13, RZ ; IMAD.X R13, R11, 0x1, R23, P6 ; ISETP.NE.AND P6, PT, R17, 0x6, PT ; @P0 IMAD.MOV.U32 R12, RZ, RZ, R10.reuse ; @P5 IMAD.MOV.U32 R22, RZ, RZ, R10.reuse ; @P4 IMAD.MOV.U32 R21, RZ, RZ, R10.reuse ; @P3 IMAD.MOV.U32 R20, RZ, RZ, R10.reuse ; @P2 IMAD.MOV.U32 R19, RZ, RZ, R10 ; @P1 IMAD.MOV.U32 R18, RZ, RZ, R10 ; @P6 BRA 0x9a0 ; IADD3 R8, -R14, 0x6, RZ ; IMAD.SHL.U32 R8, R8, 0x4, RZ ; ISETP.EQ.AND P0, PT, R8.reuse, RZ, PT ; ISETP.EQ.AND P3, PT, R8.reuse, 0x4, PT ; ISETP.EQ.AND P4, PT, R8.reuse, 0x8, PT ; ISETP.EQ.AND P2, PT, R8.reuse, 0xc, PT ; ISETP.EQ.AND P1, PT, R8, 0x10, PT ; @P0 IMAD.MOV.U32 R9, RZ, RZ, R12.reuse ; ISETP.EQ.AND P0, PT, R8.reuse, 0x14, PT ; @P3 IMAD.MOV.U32 R10, RZ, RZ, R12 ; @P3 IMAD.MOV.U32 R9, RZ, RZ, R22.reuse ; ISETP.EQ.AND P3, PT, R8.reuse, 0x18, PT ; @P4 IMAD.MOV.U32 R10, RZ, RZ, R22 ; @P4 IMAD.MOV.U32 R9, RZ, RZ, R21.reuse ; ISETP.EQ.AND P4, PT, R8, 0x1c, PT ; @P2 IMAD.MOV.U32 R10, RZ, RZ, R21 ; @P2 IMAD.MOV.U32 R9, RZ, RZ, R20.reuse ; @P1 IMAD.MOV.U32 R10, RZ, RZ, R20 ; @P1 IMAD.MOV.U32 R9, RZ, RZ, R19 ; LOP3.LUT P1, R15, R15, 0x1f, RZ, 0xc0, !PT ; @P0 IMAD.MOV.U32 R9, RZ, RZ, R18 ; @P3 IMAD.MOV.U32 R9, RZ, RZ, R13 ; @P0 IMAD.MOV.U32 R10, RZ, RZ, R19 ; @P3 IMAD.MOV.U32 R10, RZ, RZ, R18 ; @P4 IMAD.MOV.U32 R10, RZ, RZ, R13 ; IMAD.MOV.U32 R8, RZ, RZ, R9 ; @!P1 BRA 0xe30 ; IADD3 R14, -R14, 0x4, RZ ; IADD3 R9, -R15, 0x20, RZ ; SHF.L.U32 R11, R8, R15.reuse, RZ ; IMAD.SHL.U32 R14, R14, 0x4, RZ ; SHF.L.U32 R15, R10, R15, RZ ; SHF.R.U32.HI R8, RZ, R9, R10 ; ISETP.EQ.AND P1, PT, R14.reuse, 0x4, PT ; ISETP.EQ.AND P2, PT, R14, 0x8, PT ; IMAD.IADD R8, R8, 0x1, R11 ; ISETP.EQ.AND P0, PT, R14.reuse, RZ, PT ; ISETP.EQ.AND P3, PT, R14.reuse, 0xc, PT ; ISETP.EQ.AND P0, PT, R14, 0x10, PT ; @P1 IMAD.MOV.U32 R12, RZ, RZ, R22 ; ISETP.EQ.AND P1, PT, R14.reuse, 0x14, PT ; @P2 IMAD.MOV.U32 R12, RZ, RZ, R21 ; ISETP.EQ.AND P2, PT, R14, 0x18, PT ; @P3 IMAD.MOV.U32 R12, RZ, RZ, R20 ; @P0 IMAD.MOV.U32 R12, RZ, RZ, R19 ; @P1 IMAD.MOV.U32 R12, RZ, RZ, R18 ; @P2 IMAD.MOV.U32 R12, RZ, RZ, R13 ; SHF.R.U32.HI R12, RZ, R9, R12 ; IMAD.IADD R10, R12, 0x1, R15 ; SHF.L.U32.HI R13, R10.reuse, 0x2, R8 ; IMAD.SHL.U32 R12, R10, 0x4, RZ ; LOP3.LUT P1, R3, R3, 0x80000000, RZ, 0xc0, !PT ; SHF.R.U32.HI R9, RZ, 0x1f, R13 ; ISETP.NE.AND P0, PT, R9, RZ, PT ; LEA.HI R14, R8, R9, RZ, 0x2 ; @P0 LOP3.LUT R13, RZ, R13, RZ, 0x33, !PT ; @P0 LOP3.LUT R12, RZ, R12, RZ, 0x33, !PT ; @P0 LOP3.LUT R3, R3, 0x80000000, RZ, 0x3c, !PT ; I2F.F64.S64 R10, R12 ; ISETP.NE.AND P0, PT, R3, RZ, PT ; IMAD.MOV R3, RZ, RZ, -R14 ; @P1 IMAD.MOV.U32 R14, RZ, RZ, R3 ; DMUL R10, R10, c[0x2][0x0] ; F2F.F32.F64 R10, R10 ; FSEL R9, R10, -R10, !P0 ; BRA 0xf60 ; FMUL R9, RZ, R3 ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; IADD3 R14, R14, 0x1, RZ ; IMAD.MOV.U32 R8, RZ, RZ, 0x3c0885e4 ; FMUL R12, R9, R9 ; LOP3.LUT P1, RZ, R14.reuse, 0x1, RZ, 0xc0, !PT ; IMAD.MOV.U32 R11, RZ, RZ, 0x3e2aaaa8 ; LOP3.LUT P0, RZ, R14, 0x2, RZ, 0xc0, !PT ; IMAD.MOV.U32 R3, RZ, RZ, -0x46b2bead ; FSEL R8, R8, 0.041666727513074874878, !P1 ; FSEL R9, R9, 1, !P1 ; @P1 IMAD.MOV.U32 R10, RZ, RZ, 0x37cbac00 ; @P1 FFMA R3, R12.reuse, R10, -0.0013887860113754868507 ; FSEL R10, -R11, -0.4999999701976776123, !P1 ; IADD3 R11, R7, -0xd000000, RZ ; FFMA R3, R12.reuse, R3, R8 ; FFMA R8, R9, R12, RZ ; ISETP.GT.U32.AND P1, PT, R11, 0x727fffff, PT ; FFMA R3, R12, R3, R10 ; MUFU.RSQ R10, R7 ; FFMA R3, R3, R8, R9 ; @P0 FFMA R3, R3, -1, RZ ; @!P1 BRA 0x1110 ; BSSY B0, 0x1100 ; IMAD.MOV.U32 R12, RZ, RZ, R7 ; MOV R13, 0x10f0 ; CALL.REL.NOINC 0x1af0 ; BSYNC B0 ; BRA 0x1150 ; FMUL.FTZ R8, R7, R10 ; FMUL.FTZ R10, R10, 0.5 ; FFMA R7, -R8, R8, R7 ; FFMA R7, R7, R10, R8 ; F2F.F32.F64 R12, R4 ; FADD R8, R7, -1 ; BSSY B0, 0x1270 ; FFMA R3, R8, R3, 1 ; FMUL R14, R6, R3 ; IADD3 R9, R12, -0xd000000, RZ ; MUFU.RSQ R11, R12 ; ISETP.GT.U32.AND P0, PT, R9, 0x727fffff, PT ; @!P0 BRA 0x1220 ; MOV R13, 0x1200 ; CALL.REL.NOINC 0x1af0 ; IMAD.MOV.U32 R4, RZ, RZ, R7 ; BRA 0x1260 ; FMUL.FTZ R4, R12, R11 ; FMUL.FTZ R5, R11, 0.5 ; FFMA R3, -R4, R4, R12 ; FFMA R4, R3, R5, R4 ; BSYNC B0 ; MUFU.RCP R3, R14 ; BSSY B0, 0x1350 ; FCHK P0, R4, R14 ; FFMA R6, -R14, R3, 1 ; FFMA R3, R3, R6, R3 ; FFMA R5, R3, R4, RZ ; FFMA R6, -R14, R5, R4 ; FFMA R3, R3, R6, R5 ; @!P0 BRA 0x1340 ; IMAD.MOV.U32 R7, RZ, RZ, R4 ; MOV R6, 0x1340 ; IMAD.MOV.U32 R8, RZ, RZ, R14 ; CALL.REL.NOINC 0x1c50 ; BSYNC B0 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FMUL R4, R4, c[0x0][0x16c] ; F2F.F64.F32 R4, R4 ; MUFU.RCP64H R7, R5 ; DFMA R8, -R4, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R4, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R8, R6, 2 ; DFMA R10, -R4, R8, 2 ; DFMA R6, R6, R10, R8 ; FFMA R8, RZ, R5, R7 ; FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; @P0 BRA 0x1470 ; MOV R8, 0x1470 ; CALL.REL.NOINC 0x1620 ; MUFU.RCP R5, c[0x0][0x168] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ; BSSY B0, 0x1580 ; FCHK P0, R3, c[0x0][0x168] ; FFMA R8, R5, -R8, 1 ; F2I.F64.TRUNC R4, R6 ; FFMA R8, R5, R8, R5 ; FFMA R5, R8, R3, RZ ; FFMA R9, R5, -c[0x0][0x168], R3 ; FFMA R5, R8, R9, R5 ; @!P0 BRA 0x1570 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; MOV R6, 0x1560 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ; CALL.REL.NOINC 0x1c50 ; IMAD.MOV.U32 R5, RZ, RZ, R3 ; BSYNC B0 ; F2I.TRUNC.NTZ R5, R5 ; IADD3 R3, R5.reuse, c[0x0][0x1a8], R4 ; IADD3 R7, R5, -c[0x0][0x1a8], RZ ; ISETP.GE.AND P0, PT, R0, R3, PT ; ISETP.LE.OR P0, PT, R0, R7, P0 ; @P0 EXIT ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; IMAD.WIDE R2, R2, R3, c[0x0][0x1a0] ; STG.E [R2.64], RZ ; EXIT ; FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; LOP3.LUT R6, R5, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R16, RZ, RZ, 0x40000000 ; IMAD.MOV.U32 R9, RZ, RZ, 0x1ca00000 ; LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; IADD3 R18, R16, -0x1, RZ ; @!P0 DMUL R6, R4, 8.98846567431157953865e+307 ; MUFU.RCP64H R11, R7 ; DFMA R12, R10, -R6, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R10, R12, R10 ; LOP3.LUT R10, R5, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R14, R12.reuse, -R6, 1 ; ISETP.LE.U32.AND P1, PT, R10, 0x40000000, PT ; IMAD.MOV.U32 R17, RZ, RZ, R10 ; @!P0 LOP3.LUT R17, R7, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; SEL R11, R9, 0x63400000, !P1 ; DFMA R12, R12, R14, R12 ; ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ; IADD3 R20, R17, -0x1, RZ ; DMUL R14, R12, R10 ; ISETP.GT.U32.OR P0, PT, R20, 0x7feffffe, P0 ; DFMA R18, R14, -R6, R10 ; DFMA R12, R12, R18, R14 ; @P0 BRA 0x19a0 ; LOP3.LUT R15, R5, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R16, RZ, RZ, RZ ; IADD3 R14, -R15.reuse, 0x40000000, RZ ; ISETP.LE.U32.AND P0, PT, R15, 0x40000000, PT ; IMNMX R14, R14, -0x46a00000, !PT ; SEL R9, R9, 0x63400000, !P0 ; IMNMX R14, R14, 0x46a00000, PT ; IMAD.IADD R9, R14, 0x1, -R9 ; IADD3 R17, R9, 0x7fe00000, RZ ; DMUL R14, R12, R16 ; FSETP.GTU.AND P0, PT, |R15|, 1.469367938527859385e-39, PT ; @P0 BRA 0x1ab0 ; DFMA R6, R12, -R6, R10 ; IMAD.MOV.U32 R16, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R7.reuse, RZ, PT ; LOP3.LUT R11, R7, 0x80000000, R5, 0x48, !PT ; LOP3.LUT R17, R11, R17, RZ, 0xfc, !PT ; @!P0 BRA 0x1ab0 ; IMAD.MOV R5, RZ, RZ, -R9 ; IADD3 R9, -R9, -0x43300000, RZ ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; DFMA R4, R14, -R4, R12 ; DMUL.RP R12, R12, R16 ; FSETP.NEU.AND P0, PT, |R5|, R9, PT ; LOP3.LUT R11, R13, R11, RZ, 0x3c, !PT ; FSEL R14, R12, R14, !P0 ; FSEL R15, R11, R15, !P0 ; BRA 0x1ab0 ; DSETP.NAN.AND P0, PT, R4, R4, PT ; @P0 BRA 0x1a90 ; ISETP.NE.AND P0, PT, R16, R17, PT ; IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; IMAD.MOV.U32 R15, RZ, RZ, -0x80000 ; @!P0 BRA 0x1ab0 ; ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; LOP3.LUT R4, R5, 0x40000000, RZ, 0x3c, !PT ; ISETP.EQ.OR P0, PT, R17, RZ, !P0 ; LOP3.LUT R15, R4, 0x80000000, RZ, 0xc0, !PT ; @P0 LOP3.LUT R4, R15, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R15, RZ, RZ, R4 ; BRA 0x1ab0 ; LOP3.LUT R15, R5, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R14, RZ, RZ, R4 ; IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; IMAD.MOV.U32 R6, RZ, RZ, R14 ; IMAD.MOV.U32 R7, RZ, RZ, R15 ; RET.REL.NODEC R8 0x0 ; LOP3.LUT P0, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; @!P0 IMAD.MOV.U32 R7, RZ, RZ, R12 ; @!P0 BRA 0x1c20 ; FSETP.GEU.FTZ.AND P0, PT, R12, RZ, PT ; @!P0 IMAD.MOV.U32 R7, RZ, RZ, 0x7fffffff ; @!P0 BRA 0x1c20 ; FSETP.GTU.FTZ.AND P0, PT, |R12|, +INF , PT ; @P0 FADD.FTZ R7, R12, 1 ; @P0 BRA 0x1c20 ; FSETP.NEU.FTZ.AND P0, PT, |R12|, +INF , PT ; @P0 FFMA R8, R12, 1.84467440737095516160e+19, RZ ; @P0 MUFU.RSQ R7, R8 ; @P0 FMUL.FTZ R9, R8, R7 ; @P0 FMUL.FTZ R11, R7, 0.5 ; @P0 FADD.FTZ R10, -R9.reuse, -RZ ; @!P0 IMAD.MOV.U32 R7, RZ, RZ, R12 ; @P0 FFMA R10, R9, R10, R8 ; @P0 FFMA R10, R10, R11, R9 ; @P0 FMUL.FTZ R7, R10, 2.3283064365386962891e-10 ; IMAD.MOV.U32 R8, RZ, RZ, R13 ; IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; RET.REL.NODEC R8 0x0 ; SHF.R.U32.HI R5, RZ, 0x17, R8 ; BSSY B1, 0x22a0 ; SHF.R.U32.HI R3, RZ, 0x17, R7.reuse ; LOP3.LUT R13, R5, 0xff, RZ, 0xc0, !PT ; LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R3, RZ, RZ, R7 ; IADD3 R10, R13, -0x1, RZ ; IADD3 R9, R11, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; @!P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; @!P0 BRA 0x1e80 ; FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; FSETP.GTU.FTZ.AND P1, PT, |R8|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0x2280 ; LOP3.LUT P0, RZ, R8, 0x7fffffff, R3, 0xc8, !PT ; @!P0 BRA 0x2260 ; FSETP.NEU.FTZ.AND P0, PT, |R7|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P2, PT, |R8|, +INF , PT ; FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; @!P2 BRA !P0, 0x2260 ; LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P2, P0, PT, 0x2a, 0x0 ; @P0 BRA 0x2240 ; LOP3.LUT P0, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P1, P0, PT, 0x2a, 0x0 ; @P0 BRA 0x2210 ; ISETP.GE.AND P0, PT, R9, RZ, PT ; ISETP.GE.AND P1, PT, R10, RZ, PT ; @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; @!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x40 ; @!P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R8, R8, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R5, R5, 0x40, RZ ; LEA R7, R13, 0xc0800000, 0x17 ; BSSY B2, 0x2200 ; IMAD.IADD R7, R8, 0x1, -R7 ; IADD3 R8, R11, -0x7f, RZ ; MUFU.RCP R9, R7 ; FADD.FTZ R10, -R7, -RZ ; IMAD R3, R8.reuse, -0x800000, R3 ; IADD3 R8, R8, 0x7f, -R13 ; IMAD.IADD R8, R8, 0x1, R5 ; FFMA R12, R9, R10, 1 ; FFMA R14, R9, R12, R9 ; FFMA R9, R3, R14, RZ ; FFMA R12, R10, R9, R3 ; FFMA R9, R14, R12, R9 ; FFMA R10, R10, R9, R3 ; FFMA R3, R14, R10, R9 ; SHF.R.U32.HI R7, RZ, 0x17, R3 ; LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; IMAD.IADD R11, R7, 0x1, R8 ; IADD3 R5, R11, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; @!P0 BRA 0x21e0 ; ISETP.GT.AND P0, PT, R11, 0xfe, PT ; @P0 BRA 0x21b0 ; ISETP.GE.AND P0, PT, R11, 0x1, PT ; @P0 BRA 0x21f0 ; ISETP.GE.AND P0, PT, R11, -0x18, PT ; LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0x21f0 ; FFMA.RZ R5, R14.reuse, R10.reuse, R9.reuse ; ISETP.NE.AND P2, PT, R11.reuse, RZ, PT ; FFMA.RM R8, R14.reuse, R10.reuse, R9.reuse ; ISETP.NE.AND P1, PT, R11, RZ, PT ; LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; FFMA.RP R5, R14, R10, R9 ; IADD3 R10, R11, 0x20, RZ ; IMAD.MOV R9, RZ, RZ, -R11 ; LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; FSETP.NEU.FTZ.AND P0, PT, R5, R8, PT ; SHF.L.U32 R10, R7, R10, RZ ; SEL R8, R9, RZ, P2 ; ISETP.NE.AND P1, PT, R10, RZ, P1 ; SHF.R.U32.HI R8, RZ, R8, R7 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R10, RZ, 0x1, R8 ; SEL R5, RZ, 0x1, !P0 ; LOP3.LUT R5, R5, 0x1, R10, 0xf8, !PT ; LOP3.LUT R5, R5, R8, RZ, 0xc0, !PT ; IMAD.IADD R10, R10, 0x1, R5 ; LOP3.LUT R3, R10, R3, RZ, 0xfc, !PT ; BRA 0x21f0 ; LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x21f0 ; IMAD R3, R8, 0x800000, R3 ; BSYNC B2 ; BRA 0x2290 ; LOP3.LUT R3, R8, 0x80000000, R3, 0x48, !PT ; LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x2290 ; LOP3.LUT R3, R8, 0x80000000, R3, 0x48, !PT ; BRA 0x2290 ; MUFU.RSQ R3, -QNAN ; BRA 0x2290 ; FADD.FTZ R3, R7, R8 ; BSYNC B1 ; IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; RET.REL.NODEC R6 0x0 ; SHF.R.U32.HI R27, RZ, 0x14, R8 ; IMAD.MOV.U32 R6, RZ, RZ, R10 ; IMAD.MOV.U32 R7, RZ, RZ, R8 ; ISETP.NE.AND P0, PT, R27, RZ, PT ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; IMAD.MOV.U32 R16, RZ, RZ, 0x7d2cafe2 ; IMAD.MOV.U32 R17, RZ, RZ, 0x3eb0f5ff ; @!P0 DMUL R6, R6, 1.80143985094819840000e+16 ; @!P0 IMAD.MOV.U32 R8, RZ, RZ, R7 ; @!P0 LEA.HI R27, R7, 0xffffffca, RZ, 0xc ; @!P0 IMAD.MOV.U32 R10, RZ, RZ, R6 ; IMAD.MOV.U32 R7, RZ, RZ, 0x43300000 ; LOP3.LUT R8, R8, 0x800fffff, RZ, 0xc0, !PT ; IADD3 R6, R27, -0x3ff, RZ ; LOP3.LUT R11, R8, 0x3ff00000, RZ, 0xfc, !PT ; ISETP.GE.U32.AND P1, PT, R11, 0x3ff6a09f, PT ; @P1 IADD3 R9, R11, -0x100000, RZ ; @P1 IADD3 R6, R27, -0x3fe, RZ ; @P1 IMAD.MOV.U32 R11, RZ, RZ, R9 ; LOP3.LUT R6, R6, 0x80000000, RZ, 0x3c, !PT ; DADD R12, R10, 1 ; DADD R10, R10, -1 ; MUFU.RCP64H R15, R13 ; DFMA R8, -R12, R14, 1 ; DFMA R8, R8, R8, R8 ; DFMA R14, R14, R8, R14 ; DMUL R8, R14, R10 ; DFMA R8, R14, R10, R8 ; DMUL R20, R8, R8 ; DADD R12, R10, -R8 ; DFMA R16, R20, R16, c[0x2][0x8] ; DADD R12, R12, R12 ; DFMA R16, R20, R16, c[0x2][0x10] ; DFMA R12, R10, -R8, R12 ; DFMA R16, R20, R16, c[0x2][0x18] ; DMUL R12, R14, R12 ; DFMA R18, R20, R16, c[0x2][0x20] ; DMUL R14, R8, R8 ; DFMA R18, R20, R18, c[0x2][0x28] ; DFMA R18, R20, R18, c[0x2][0x30] ; DFMA R10, R20, R18, c[0x2][0x38] ; DADD R16, -R10, c[0x2][0x38] ; DFMA R16, R20, R18, R16 ; IADD3 R19, R13, 0x100000, RZ ; IMAD.MOV.U32 R18, RZ, RZ, R12 ; DFMA R20, R8, R8, -R14 ; DFMA R18, R8, R18, R20 ; DMUL R20, R8, R14 ; DFMA R22, R8, R14, -R20 ; DFMA R22, R12, R14, R22 ; DADD R14, RZ, R16 ; DFMA R18, R8, R18, R22 ; DADD R14, R14, c[0x2][0x40] ; DADD R16, R10, R14 ; DADD R22, R10, -R16 ; DADD R22, R14, R22 ; DMUL R14, R16, R20 ; DFMA R10, R16, R20, -R14 ; DFMA R10, R16, R18, R10 ; DFMA R22, R22, R20, R10 ; DADD R10, R14, R22 ; DADD R16, R8, R10 ; DADD R14, R14, -R10 ; DADD R8, R8, -R16 ; DADD R14, R22, R14 ; DADD R8, R10, R8 ; DADD R8, R14, R8 ; DADD R12, R12, R8 ; DADD R8, R6, c[0x2][0x48] ; DADD R10, R16, R12 ; DFMA R6, R8, c[0x2][0x50], R10 ; DADD R16, R16, -R10 ; DFMA R14, -R8, c[0x2][0x50], R6 ; DADD R16, R12, R16 ; DADD R14, -R10, R14 ; DADD R14, R16, -R14 ; DFMA R14, R8, c[0x2][0x58], R14 ; DADD R8, R6, R14 ; DADD R6, R6, -R8 ; DMUL R12, R8, 2 ; DADD R6, R14, R6 ; IMAD.MOV.U32 R14, RZ, RZ, 0x69ce2bdf ; DFMA R10, R8, 2, -R12 ; IMAD.MOV.U32 R15, RZ, RZ, 0x3e5ade15 ; DFMA R10, R6, 2, R10 ; IMAD.MOV.U32 R6, RZ, RZ, 0x652b82fe ; IMAD.MOV.U32 R7, RZ, RZ, 0x3ff71547 ; DADD R8, R12, R10 ; DFMA R6, R8, R6, 6.75539944105574400000e+15 ; FSETP.GEU.AND P0, PT, |R9|, 4.1917929649353027344, PT ; DADD R16, R6, -6.75539944105574400000e+15 ; DFMA R18, R16, c[0x2][0x60], R8 ; DFMA R16, R16, c[0x2][0x68], R18 ; DFMA R14, R16, R14, c[0x2][0x70] ; DFMA R14, R16, R14, c[0x2][0x78] ; DFMA R14, R16, R14, c[0x2][0x80] ; DFMA R14, R16, R14, c[0x2][0x88] ; DFMA R14, R16, R14, c[0x2][0x90] ; DFMA R14, R16, R14, c[0x2][0x98] ; DFMA R14, R16, R14, c[0x2][0xa0] ; DFMA R14, R16, R14, c[0x2][0xa8] ; DFMA R14, R16, R14, c[0x2][0xb0] ; DFMA R14, R16, R14, 1 ; DFMA R16, R16, R14, 1 ; IMAD R15, R6, 0x100000, R17 ; IMAD.MOV.U32 R14, RZ, RZ, R16 ; @!P0 BRA 0x2a30 ; FSETP.GEU.AND P1, PT, |R9|, 4.2275390625, PT ; DADD R14, R8, +INF ; DSETP.GEU.AND P0, PT, R8, RZ, PT ; FSEL R14, R14, RZ, P0 ; @!P1 LEA.HI R7, R6, R6, RZ, 0x1 ; FSEL R15, R15, RZ, P0 ; @!P1 SHF.R.S32.HI R7, RZ, 0x1, R7 ; @!P1 IMAD.IADD R6, R6, 0x1, -R7 ; @!P1 IMAD R17, R7, 0x100000, R17 ; @!P1 LEA R7, R6, 0x3ff00000, 0x14 ; @!P1 IMAD.MOV.U32 R6, RZ, RZ, RZ ; @!P1 DMUL R14, R16, R6 ; LOP3.LUT R6, R15, 0x7fffffff, RZ, 0xc0, !PT ; DADD R8, R12, -R8 ; IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; ISETP.NE.AND P0, PT, R6, 0x7ff00000, PT ; IMAD.MOV.U32 R6, RZ, RZ, R0 ; DADD R8, R10, R8 ; ISETP.EQ.AND P0, PT, R14, RZ, !P0 ; @!P0 DFMA R14, R8, R14, R14 ; IMAD.MOV.U32 R8, RZ, RZ, R14 ; IMAD.MOV.U32 R9, RZ, RZ, R15 ; RET.REL.NODEC R6 0x0 ; BRA 0x2ae0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z11shot_recordiiiiiiiPfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_TID.X ; S2R R3, SR_CTAID.X ; IMAD R0, R3, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; @P0 EXIT ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; IADD3 R2, R0, c[0x0][0x170], RZ ; ULDC.64 UR4, c[0x0][0x118] ; MOV R3, c[0x0][0x164] ; IMAD R2, R2, R3, c[0x0][0x170] ; IMAD.WIDE R2, R2, R5, c[0x0][0x180] ; LDG.E R3, [R2.64] ; MOV R7, c[0x0][0x178] ; IMAD R4, R0, R7, c[0x0][0x174] ; IMAD.WIDE R4, R4, R5, c[0x0][0x188] ; STG.E [R4.64], R3 ; EXIT ; BRA 0x120; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z13initial_coffefiPfS_S_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; ULDC UR5, c[0x0][0x188] ; ULDC UR4, c[0x0][0x164] ; S2R R3, SR_TID.X ; ULEA UR4, UR5, UR4, 0x1 ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, UR4, PT ; @P0 EXIT ; ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ; ULDC.64 UR6, c[0x0][0x118] ; @!P0 BRA 0xd50 ; ULDC UR4, c[0x0][0x164] ; UIADD3 UR4, UR5, UR4, URZ ; ISETP.GE.AND P0, PT, R0, UR4, PT ; @!P0 BRA 0xca0 ; IMAD.MOV.U32 R14, RZ, RZ, c[0x4][0x0] ; IMAD.MOV.U32 R15, RZ, RZ, c[0x4][0x4] ; LDG.E R22, [R14.64] ; I2F.F64 R12, c[0x0][0x188] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B0, 0x2d0 ; I2F.F64 R2, R0 ; MUFU.RCP64H R7, R13 ; I2F.F64 R4, c[0x0][0x164] ; DADD R2, R2, 0.5 ; DFMA R8, -R12, R6, 1 ; DFMA R8, R8, R8, R8 ; DADD R2, R2, -R4 ; DFMA R8, R6, R8, R6 ; DADD R2, R2, -R12 ; DFMA R4, -R12, R8, 1 ; DFMA R4, R8, R4, R8 ; FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; DMUL R20, R2, R4 ; DFMA R6, -R12, R20, R2 ; DFMA R20, R4, R6, R20 ; FFMA R4, RZ, R13, R21 ; FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2c0 ; IMAD.MOV.U32 R4, RZ, RZ, R12 ; MOV R10, 0x2c0 ; IMAD.MOV.U32 R5, RZ, RZ, R13 ; CALL.REL.NOINC 0x1b50 ; BSYNC B0 ; DADD R6, -RZ, |R20| ; BSSY B0, 0x320 ; MOV R2, 0x310 ; CALL.REL.NOINC 0x2120 ; BSYNC B0 ; DADD R2, R20.reuse, 2 ; BSSY B0, 0x440 ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; LOP3.LUT R2, R3, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R2, 0x7ff00000, PT ; @!P0 CS2R R18, SRZ ; @P1 BRA 0x430 ; DSETP.GTU.AND P0, PT, |R20|, +INF , PT ; @P0 BRA 0x420 ; ISETP.NE.AND P0, PT, R20, RZ, PT ; LOP3.LUT R2, R21, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R2, 0x7ff00000, P0 ; @P0 BRA 0x430 ; IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; IMAD.MOV.U32 R19, RZ, RZ, 0x7ff00000 ; BRA 0x430 ; DADD R18, R20, 2 ; BSYNC B0 ; FMUL R22, R22, c[0x0][0x160] ; DSETP.NEU.AND P0, PT, R20, 1, PT ; IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; BSSY B0, 0x5d0 ; F2F.F64.F32 R2, R22 ; IMAD.MOV.U32 R5, RZ, RZ, 0x3ff00000 ; FSEL R16, R18, RZ, P0 ; FSEL R17, R19, 1.875, P0 ; DMUL R2, R16, R2 ; DFMA R8, R2, 0.5, R4 ; MUFU.RCP64H R3, R9 ; IADD3 R2, R9, 0x300402, RZ ; FSETP.GEU.AND P0, PT, |R2|, 5.8789094863358348022e-39, PT ; DFMA R4, -R8, R2, 1 ; DFMA R4, R4, R4, R4 ; DFMA R4, R2, R4, R2 ; DFMA R6, -R8, R4, 1 ; DFMA R4, R4, R6, R4 ; @P0 BRA 0x5c0 ; LOP3.LUT R4, R9, 0x7fffffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; MOV R2, 0x5c0 ; IADD3 R4, R4, -0x100000, RZ ; CALL.REL.NOINC 0x18c0 ; BSYNC B0 ; F2F.F32.F64 R19, R4 ; IMAD.MOV.U32 R21, RZ, RZ, 0x4 ; IMAD.WIDE R2, R0, R21, c[0x0][0x168] ; STG.E [R2.64], R19 ; LDG.E R6, [R14.64] ; IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; IMAD.MOV.U32 R11, RZ, RZ, 0x3ff00000 ; IMAD.WIDE R4, R0, R21, c[0x0][0x170] ; MUFU.RCP64H R3, R13 ; IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; FMUL R18, R6, c[0x0][0x160] ; F2F.F64.F32 R6, R19 ; F2F.F64.F32 R8, R18 ; DMUL R8, R16, R8 ; DFMA R8, R8, -0.5, R10 ; DMUL R6, R6, R8 ; F2F.F32.F64 R11, R6 ; STG.E [R4.64], R11 ; LDG.E R22, [R14.64] ; DFMA R8, -R12, R2, 1 ; IADD3 R10, R0, -c[0x0][0x164], RZ ; BSSY B0, 0x860 ; SHF.R.S32.HI R23, RZ, 0x1f, R0 ; IADD3 R10, R10, -c[0x0][0x188], RZ ; DFMA R8, R8, R8, R8 ; DFMA R8, R2, R8, R2 ; I2F.F64 R2, R10 ; DFMA R6, -R12, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R20, R6, R2 ; FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; DFMA R4, -R12, R20, R2 ; DFMA R20, R6, R4, R20 ; FFMA R4, RZ, R13, R21 ; FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x850 ; IMAD.MOV.U32 R4, RZ, RZ, R12 ; MOV R10, 0x850 ; IMAD.MOV.U32 R5, RZ, RZ, R13 ; CALL.REL.NOINC 0x1b50 ; BSYNC B0 ; DADD R6, -RZ, |R20| ; BSSY B0, 0x8b0 ; MOV R2, 0x8a0 ; CALL.REL.NOINC 0x2120 ; BSYNC B0 ; DADD R2, R20.reuse, 2 ; BSSY B0, 0x9d0 ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; LOP3.LUT R2, R3, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R2, 0x7ff00000, PT ; @!P0 CS2R R18, SRZ ; @P1 BRA 0x9c0 ; DSETP.GTU.AND P0, PT, |R20|, +INF , PT ; @P0 BRA 0x9b0 ; ISETP.NE.AND P0, PT, R20, RZ, PT ; LOP3.LUT R2, R21, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R2, 0x7ff00000, P0 ; @P0 BRA 0x9c0 ; IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; IMAD.MOV.U32 R19, RZ, RZ, 0x7ff00000 ; BRA 0x9c0 ; DADD R18, R20, 2 ; BSYNC B0 ; FMUL R22, R22, c[0x0][0x160] ; DSETP.NEU.AND P0, PT, R20, 1, PT ; IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; BSSY B0, 0xb60 ; F2F.F64.F32 R2, R22 ; IMAD.MOV.U32 R9, RZ, RZ, 0x3ff00000 ; FSEL R12, R18, RZ, P0 ; FSEL R13, R19, 1.875, P0 ; DMUL R2, R12, R2 ; DFMA R8, R2, 0.5, R8 ; MUFU.RCP64H R3, R9 ; IADD3 R2, R9, 0x300402, RZ ; FSETP.GEU.AND P0, PT, |R2|, 5.8789094863358348022e-39, PT ; DFMA R4, -R8, R2, 1 ; DFMA R4, R4, R4, R4 ; DFMA R4, R2, R4, R2 ; DFMA R6, -R8, R4, 1 ; DFMA R4, R4, R6, R4 ; @P0 BRA 0xb50 ; LOP3.LUT R4, R9, 0x7fffffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; MOV R2, 0xb50 ; IADD3 R4, R4, -0x100000, RZ ; CALL.REL.NOINC 0x18c0 ; BSYNC B0 ; F2F.F32.F64 R17, R4 ; IMAD.SHL.U32 R16, R0.reuse, 0x4, RZ ; SHF.L.U64.HI R23, R0, 0x2, R23 ; IADD3 R8, P0, R16, c[0x0][0x178], RZ ; IADD3.X R9, R23, c[0x0][0x17c], RZ, P0, !PT ; STG.E [R8.64], R17 ; LDG.E R14, [R14.64] ; F2F.F64.F32 R2, R17 ; IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; IADD3 R4, P0, R16, c[0x0][0x180], RZ ; IMAD.MOV.U32 R11, RZ, RZ, 0x3ff00000 ; IADD3.X R5, R23, c[0x0][0x184], RZ, P0, !PT ; FMUL R0, R14, c[0x0][0x160] ; F2F.F64.F32 R6, R0 ; DMUL R6, R12, R6 ; DFMA R6, R6, -0.5, R10 ; DMUL R2, R2, R6 ; F2F.F32.F64 R3, R2 ; STG.E [R4.64], R3 ; EXIT ; IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; IMAD.MOV.U32 R11, RZ, RZ, 0x3f800000 ; IMAD.WIDE R6, R0, R5, c[0x0][0x168] ; IMAD.WIDE R8, R0.reuse, R5.reuse, c[0x0][0x170] ; STG.E [R6.64], R11 ; IMAD.WIDE R2, R0.reuse, R5.reuse, c[0x0][0x178] ; STG.E [R8.64], R11 ; IMAD.WIDE R4, R0, R5, c[0x0][0x180] ; STG.E [R2.64], R11 ; STG.E [R4.64], R11 ; EXIT ; IMAD.MOV.U32 R12, RZ, RZ, c[0x4][0x0] ; IMAD.MOV.U32 R13, RZ, RZ, c[0x4][0x4] ; LDG.E R22, [R12.64] ; I2F.F64 R14, c[0x0][0x188] ; IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; BSSY B0, 0xf00 ; MUFU.RCP64H R3, R15 ; DFMA R4, -R14, R2, 1 ; DFMA R6, R4, R4, R4 ; I2F.F64 R4, R0 ; DFMA R6, R2, R6, R2 ; DADD R2, R14, -0.5 ; DFMA R8, -R14, R6, 1 ; DADD R2, R2, -R4 ; DFMA R8, R6, R8, R6 ; DMUL R20, R2, R8 ; FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; DFMA R4, R20, -R14, R2 ; DFMA R20, R4, R8, R20 ; FFMA R4, RZ, R15, R21 ; FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xef0 ; IMAD.MOV.U32 R4, RZ, RZ, R14 ; MOV R10, 0xef0 ; IMAD.MOV.U32 R5, RZ, RZ, R15 ; CALL.REL.NOINC 0x1b50 ; BSYNC B0 ; DADD R6, -RZ, |R20| ; BSSY B0, 0xf50 ; MOV R2, 0xf40 ; CALL.REL.NOINC 0x2120 ; BSYNC B0 ; DADD R2, R20.reuse, 2 ; BSSY B0, 0x1070 ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; LOP3.LUT R2, R3, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R2, 0x7ff00000, PT ; @!P0 CS2R R18, SRZ ; @P1 BRA 0x1060 ; DSETP.GTU.AND P0, PT, |R20|, +INF , PT ; @P0 BRA 0x1050 ; ISETP.NE.AND P0, PT, R20, RZ, PT ; LOP3.LUT R2, R21, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R2, 0x7ff00000, P0 ; @P0 BRA 0x1060 ; IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; IMAD.MOV.U32 R19, RZ, RZ, 0x7ff00000 ; BRA 0x1060 ; DADD R18, R20, 2 ; BSYNC B0 ; FMUL R22, R22, c[0x0][0x160] ; DSETP.NEU.AND P0, PT, R20, 1, PT ; IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; BSSY B0, 0x1200 ; F2F.F64.F32 R2, R22 ; IMAD.MOV.U32 R9, RZ, RZ, 0x3ff00000 ; FSEL R16, R18, RZ, P0 ; FSEL R17, R19, 1.875, P0 ; DMUL R2, R16, R2 ; DFMA R8, R2, 0.5, R8 ; MUFU.RCP64H R3, R9 ; IADD3 R2, R9, 0x300402, RZ ; FSETP.GEU.AND P0, PT, |R2|, 5.8789094863358348022e-39, PT ; DFMA R4, -R8, R2, 1 ; DFMA R4, R4, R4, R4 ; DFMA R4, R2, R4, R2 ; DFMA R6, -R8, R4, 1 ; DFMA R4, R4, R6, R4 ; @P0 BRA 0x11f0 ; LOP3.LUT R4, R9, 0x7fffffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; MOV R2, 0x11f0 ; IADD3 R4, R4, -0x100000, RZ ; CALL.REL.NOINC 0x18c0 ; BSYNC B0 ; F2F.F32.F64 R19, R4 ; IMAD.MOV.U32 R21, RZ, RZ, 0x4 ; IMAD.WIDE R8, R0, R21, c[0x0][0x168] ; STG.E [R8.64], R19 ; LDG.E R2, [R12.64] ; IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; IMAD.MOV.U32 R11, RZ, RZ, 0x3ff00000 ; IMAD.WIDE R4, R0, R21, c[0x0][0x170] ; FMUL R18, R2, c[0x0][0x160] ; F2F.F64.F32 R2, R19 ; F2F.F64.F32 R6, R18 ; DMUL R6, R16, R6 ; DFMA R6, R6, -0.5, R10 ; DMUL R2, R2, R6 ; F2F.F32.F64 R11, R2 ; STG.E [R4.64], R11 ; LDG.E R22, [R12.64] ; MUFU.RCP64H R7, R15 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; IADD3 R10, -R0, c[0x0][0x188], RZ ; BSSY B0, 0x1480 ; SHF.R.S32.HI R23, RZ, 0x1f, R0 ; I2F.F64 R2, R10 ; DFMA R8, -R14, R6, 1 ; DFMA R8, R8, R8, R8 ; FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, R8, R6 ; DFMA R6, -R14, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R20, R6, R2 ; DFMA R4, -R14, R20, R2 ; DFMA R20, R6, R4, R20 ; FFMA R4, RZ, R15, R21 ; FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1470 ; IMAD.MOV.U32 R4, RZ, RZ, R14 ; MOV R10, 0x1470 ; IMAD.MOV.U32 R5, RZ, RZ, R15 ; CALL.REL.NOINC 0x1b50 ; BSYNC B0 ; DADD R6, -RZ, |R20| ; BSSY B0, 0x14d0 ; MOV R2, 0x14c0 ; CALL.REL.NOINC 0x2120 ; BSYNC B0 ; DADD R2, R20.reuse, 2 ; BSSY B0, 0x15f0 ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; LOP3.LUT R2, R3, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R2, 0x7ff00000, PT ; @!P0 CS2R R18, SRZ ; @P1 BRA 0x15e0 ; DSETP.GTU.AND P0, PT, |R20|, +INF , PT ; @P0 BRA 0x15d0 ; ISETP.NE.AND P0, PT, R20, RZ, PT ; LOP3.LUT R2, R21, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R2, 0x7ff00000, P0 ; @P0 BRA 0x15e0 ; IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; IMAD.MOV.U32 R19, RZ, RZ, 0x7ff00000 ; BRA 0x15e0 ; DADD R18, R20, 2 ; BSYNC B0 ; FMUL R22, R22, c[0x0][0x160] ; DSETP.NEU.AND P0, PT, R20, 1, PT ; IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; BSSY B0, 0x1780 ; F2F.F64.F32 R2, R22 ; IMAD.MOV.U32 R9, RZ, RZ, 0x3ff00000 ; FSEL R14, R18, RZ, P0 ; FSEL R15, R19, 1.875, P0 ; DMUL R2, R14, R2 ; DFMA R8, R2, 0.5, R8 ; MUFU.RCP64H R3, R9 ; IADD3 R2, R9, 0x300402, RZ ; FSETP.GEU.AND P0, PT, |R2|, 5.8789094863358348022e-39, PT ; DFMA R4, -R8, R2, 1 ; DFMA R4, R4, R4, R4 ; DFMA R4, R2, R4, R2 ; DFMA R6, -R8, R4, 1 ; DFMA R4, R4, R6, R4 ; @P0 BRA 0x1770 ; LOP3.LUT R4, R9, 0x7fffffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; MOV R2, 0x1770 ; IADD3 R4, R4, -0x100000, RZ ; CALL.REL.NOINC 0x18c0 ; BSYNC B0 ; F2F.F32.F64 R17, R4 ; IMAD.SHL.U32 R16, R0.reuse, 0x4, RZ ; SHF.L.U64.HI R23, R0, 0x2, R23 ; IADD3 R8, P0, R16, c[0x0][0x178], RZ ; IADD3.X R9, R23, c[0x0][0x17c], RZ, P0, !PT ; STG.E [R8.64], R17 ; LDG.E R12, [R12.64] ; F2F.F64.F32 R2, R17 ; IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; IADD3 R4, P0, R16, c[0x0][0x180], RZ ; IMAD.MOV.U32 R11, RZ, RZ, 0x3ff00000 ; IADD3.X R5, R23, c[0x0][0x184], RZ, P0, !PT ; FMUL R0, R12, c[0x0][0x160] ; F2F.F64.F32 R6, R0 ; DMUL R6, R14, R6 ; DFMA R6, R6, -0.5, R10 ; DMUL R2, R2, R6 ; F2F.F32.F64 R3, R2 ; STG.E [R4.64], R3 ; EXIT ; IMAD.MOV.U32 R7, RZ, RZ, R9 ; BSSY B1, 0x1b10 ; DSETP.GTU.AND P0, PT, |R6|, +INF , PT ; @P0 BRA 0x1ae0 ; LOP3.LUT R5, R9, 0x7fffffff, RZ, 0xc0, !PT ; IADD3 R3, R5, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R3, 0x7fefffff, PT ; @P0 LOP3.LUT R9, R7, 0x7ff00000, RZ, 0x3c, !PT ; @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; @P0 BRA 0x1b00 ; ISETP.GE.U32.AND P0, PT, R5, 0x1000001, PT ; @!P0 BRA 0x1a50 ; IADD3 R9, R7, -0x3fe00000, RZ ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MUFU.RCP64H R5, R9 ; DFMA R10, -R8, R4, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R4, R10, R4 ; DFMA R4, -R8, R10, 1 ; DFMA R4, R10, R4, R10 ; DMUL R4, R4, 2.2250738585072013831e-308 ; DFMA R6, -R6, R4, 1 ; DFMA R6, R6, R6, R6 ; DFMA R8, R4, R6, R4 ; BRA 0x1b00 ; DMUL R6, R6, 8.11296384146066816958e+31 ; MUFU.RCP64H R5, R7 ; DFMA R8, -R6, R4, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R4, R8, R4 ; DFMA R4, -R6, R8, 1 ; DFMA R4, R8, R4, R8 ; DMUL R8, R4, 8.11296384146066816958e+31 ; BRA 0x1b00 ; LOP3.LUT R9, R7, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; BSYNC B1 ; IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, R8 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; RET.REL.NODEC R2 0x0 ; FSETP.GEU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R8, RZ, RZ, 0x1ca00000 ; FSETP.GEU.AND P2, PT, |R3|, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R26, RZ, RZ, 0x1 ; LOP3.LUT R24, R5, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R20, RZ, RZ, R2 ; LOP3.LUT R9, R3, 0x7ff00000, RZ, 0xc0, !PT ; BSSY B1, 0x20e0 ; LOP3.LUT R25, R24, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R24, RZ, RZ, R4 ; LOP3.LUT R16, R5, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; @!P0 DMUL R24, R4, 8.98846567431157953865e+307 ; ISETP.GE.U32.AND P1, PT, R9, R16, PT ; @!P2 LOP3.LUT R6, R5, 0x7ff00000, RZ, 0xc0, !PT ; SEL R21, R8.reuse, 0x63400000, !P1 ; MUFU.RCP64H R27, R25 ; @!P2 ISETP.GE.U32.AND P3, PT, R9, R6, PT ; LOP3.LUT R21, R21, 0x800fffff, R3, 0xf8, !PT ; @!P2 SEL R7, R8, 0x63400000, !P3 ; @!P0 LOP3.LUT R16, R25, 0x7ff00000, RZ, 0xc0, !PT ; @!P2 LOP3.LUT R6, R7, 0x80000000, R3, 0xf8, !PT ; @!P2 LOP3.LUT R7, R6, 0x100000, RZ, 0xfc, !PT ; @!P2 IMAD.MOV.U32 R6, RZ, RZ, RZ ; DFMA R18, R26, -R24, 1 ; @!P2 DFMA R20, R20, 2, -R6 ; DFMA R18, R18, R18, R18 ; DFMA R18, R26, R18, R26 ; @!P2 LOP3.LUT R11, R21, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R17, R11, -0x1, RZ ; DFMA R6, R18, -R24, 1 ; ISETP.GT.U32.AND P0, PT, R17, 0x7feffffe, PT ; DFMA R6, R18, R6, R18 ; IADD3 R18, R16, -0x1, RZ ; ISETP.GT.U32.OR P0, PT, R18, 0x7feffffe, P0 ; DMUL R26, R6, R20 ; DFMA R28, R26, -R24, R20 ; DFMA R28, R6, R28, R26 ; @P0 BRA 0x1f80 ; LOP3.LUT R6, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R9.reuse, R6, PT ; IMAD.IADD R2, R9, 0x1, -R6 ; SEL R3, R8, 0x63400000, !P0 ; IMNMX R2, R2, -0x46a00000, !PT ; IMNMX R2, R2, 0x46a00000, PT ; IMAD.IADD R8, R2, 0x1, -R3 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IADD3 R3, R8, 0x7fe00000, RZ ; DMUL R6, R28, R2 ; FSETP.GTU.AND P0, PT, |R7|, 1.469367938527859385e-39, PT ; @P0 BRA 0x20d0 ; DFMA R20, R28, -R24, R20 ; IMAD.MOV.U32 R16, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R21.reuse, RZ, PT ; LOP3.LUT R5, R21, 0x80000000, R5, 0x48, !PT ; LOP3.LUT R17, R5, R3, RZ, 0xfc, !PT ; @!P0 BRA 0x20d0 ; IMAD.MOV R3, RZ, RZ, -R8 ; DMUL.RP R16, R28, R16 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; DFMA R2, R6, -R2, R28 ; LOP3.LUT R5, R17, R5, RZ, 0x3c, !PT ; IADD3 R2, -R8, -0x43300000, RZ ; FSETP.NEU.AND P0, PT, |R3|, R2, PT ; FSEL R6, R16, R6, !P0 ; FSEL R7, R5, R7, !P0 ; BRA 0x20d0 ; DSETP.NAN.AND P0, PT, R2, R2, PT ; @P0 BRA 0x20b0 ; DSETP.NAN.AND P0, PT, R4, R4, PT ; @P0 BRA 0x2080 ; ISETP.NE.AND P0, PT, R11, R16, PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, -0x80000 ; @!P0 BRA 0x20d0 ; ISETP.NE.AND P0, PT, R11, 0x7ff00000, PT ; LOP3.LUT R7, R3, 0x80000000, R5, 0x48, !PT ; ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; @P0 LOP3.LUT R2, R7, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R7, RZ, RZ, R2 ; BRA 0x20d0 ; LOP3.LUT R7, R5, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; BRA 0x20d0 ; LOP3.LUT R7, R3, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R6, RZ, RZ, R2 ; BSYNC B1 ; IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; IMAD.MOV.U32 R20, RZ, RZ, R6 ; IMAD.MOV.U32 R21, RZ, RZ, R7 ; RET.REL.NODEC R10 0x0 ; SHF.R.U32.HI R3, RZ, 0x14, R7 ; IMAD.MOV.U32 R16, RZ, RZ, R6 ; ISETP.NE.AND P0, PT, R3, RZ, PT ; @!P0 DMUL R4, R6, 1.80143985094819840000e+16 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; @!P0 IMAD.MOV.U32 R7, RZ, RZ, R5 ; @!P0 LEA.HI R3, R5, 0xffffffca, RZ, 0xc ; @!P0 IMAD.MOV.U32 R16, RZ, RZ, R4 ; LOP3.LUT R7, R7, 0x800fffff, RZ, 0xc0, !PT ; LOP3.LUT R17, R7, 0x3ff00000, RZ, 0xfc, !PT ; ISETP.GE.U32.AND P1, PT, R17, 0x3ff6a09f, PT ; @P1 IADD3 R4, R17, -0x100000, RZ ; @P1 IMAD.MOV.U32 R17, RZ, RZ, R4 ; DADD R18, R16, 1 ; DADD R16, R16, -1 ; MUFU.RCP64H R7, R19 ; DFMA R10, -R18, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; IMAD.MOV.U32 R6, RZ, RZ, 0x7d2cafe2 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3eb0f5ff ; DMUL R26, R10, R16 ; DFMA R26, R10, R16, R26 ; DMUL R8, R26, R26 ; DADD R24, R16, -R26 ; DFMA R6, R8, R6, c[0x2][0x0] ; DADD R24, R24, R24 ; DFMA R6, R8, R6, c[0x2][0x8] ; DFMA R24, R16, -R26, R24 ; DFMA R6, R8, R6, c[0x2][0x10] ; DMUL R24, R10, R24 ; DFMA R6, R8, R6, c[0x2][0x18] ; DMUL R10, R26, R26 ; DFMA R6, R8, R6, c[0x2][0x20] ; DFMA R6, R8, R6, c[0x2][0x28] ; DFMA R18, R8, R6, c[0x2][0x30] ; DADD R16, -R18, c[0x2][0x30] ; DFMA R16, R8, R6, R16 ; IADD3 R9, R25, 0x100000, RZ ; IMAD.MOV.U32 R8, RZ, RZ, R24 ; DFMA R6, R26, R26, -R10 ; DADD R16, RZ, R16 ; DFMA R8, R26, R8, R6 ; DMUL R6, R26, R10 ; DADD R16, R16, c[0x2][0x38] ; DFMA R4, R26, R10, -R6 ; DFMA R4, R24, R10, R4 ; DADD R10, R18, R16 ; DFMA R4, R26, R8, R4 ; DADD R18, R18, -R10 ; DMUL R8, R10, R6 ; DADD R18, R16, R18 ; DFMA R16, R10, R6, -R8 ; DFMA R4, R10, R4, R16 ; DFMA R18, R18, R6, R4 ; DADD R4, R8, R18 ; DADD R6, R26, R4 ; DADD R8, R8, -R4 ; DADD R26, R26, -R6 ; DADD R8, R18, R8 ; DADD R26, R4, R26 ; IADD3 R4, R3.reuse, -0x3ff, RZ ; IMAD.MOV.U32 R5, RZ, RZ, 0x43300000 ; @P1 IADD3 R4, R3, -0x3fe, RZ ; DADD R8, R8, R26 ; LOP3.LUT R4, R4, 0x80000000, RZ, 0x3c, !PT ; DADD R24, R24, R8 ; DADD R8, R4, c[0x2][0x40] ; DADD R10, R6, R24 ; DFMA R4, R8, c[0x2][0x48], R10 ; DADD R16, R6, -R10 ; DFMA R6, -R8, c[0x2][0x48], R4 ; DADD R16, R24, R16 ; DADD R6, -R10, R6 ; DADD R6, R16, -R6 ; IMAD.MOV.U32 R16, RZ, RZ, 0x69ce2bdf ; IMAD.MOV.U32 R17, RZ, RZ, 0x3e5ade15 ; DFMA R8, R8, c[0x2][0x50], R6 ; DADD R6, R4, R8 ; DADD R4, R4, -R6 ; DMUL R10, R6, 2 ; DADD R8, R8, R4 ; IMAD.MOV.U32 R4, RZ, RZ, 0x652b82fe ; DFMA R6, R6, 2, -R10 ; IMAD.MOV.U32 R5, RZ, RZ, 0x3ff71547 ; DFMA R8, R8, 2, R6 ; DADD R6, R10, R8 ; DFMA R4, R6, R4, 6.75539944105574400000e+15 ; FSETP.GEU.AND P0, PT, |R7|, 4.1917929649353027344, PT ; DADD R24, R4, -6.75539944105574400000e+15 ; DFMA R18, R24, c[0x2][0x58], R6 ; DFMA R18, R24, c[0x2][0x60], R18 ; DFMA R16, R18, R16, c[0x2][0x68] ; DFMA R16, R18, R16, c[0x2][0x70] ; DFMA R16, R18, R16, c[0x2][0x78] ; DFMA R16, R18, R16, c[0x2][0x80] ; DFMA R16, R18, R16, c[0x2][0x88] ; DFMA R16, R18, R16, c[0x2][0x90] ; DFMA R16, R18, R16, c[0x2][0x98] ; DFMA R16, R18, R16, c[0x2][0xa0] ; DFMA R16, R18, R16, c[0x2][0xa8] ; DFMA R16, R18, R16, 1 ; DFMA R16, R18, R16, 1 ; IMAD R19, R4, 0x100000, R17 ; IMAD.MOV.U32 R18, RZ, RZ, R16 ; @!P0 BRA 0x2880 ; FSETP.GEU.AND P1, PT, |R7|, 4.2275390625, PT ; DADD R18, R6, +INF ; DSETP.GEU.AND P0, PT, R6, RZ, PT ; FSEL R18, R18, RZ, P0 ; @!P1 LEA.HI R3, R4, R4, RZ, 0x1 ; FSEL R19, R19, RZ, P0 ; @!P1 SHF.R.S32.HI R3, RZ, 0x1, R3 ; @!P1 IMAD R17, R3, 0x100000, R17 ; @!P1 IMAD.IADD R3, R4, 0x1, -R3 ; @!P1 IMAD.MOV.U32 R4, RZ, RZ, RZ ; @!P1 LEA R5, R3, 0x3ff00000, 0x14 ; @!P1 DMUL R18, R16, R4 ; LOP3.LUT R3, R19, 0x7fffffff, RZ, 0xc0, !PT ; DADD R6, R10, -R6 ; ISETP.NE.AND P0, PT, R3, 0x7ff00000, PT ; IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; DADD R6, R8, R6 ; ISETP.EQ.AND P0, PT, R18, RZ, !P0 ; @!P0 DFMA R18, R6, R18, R18 ; RET.REL.NODEC R2 0x0 ; BRA 0x2900; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z6get_d0ffiiiPf .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; IMAD R0, R0, c[0x0][0x168], RZ ; LEA.HI R0, R0, R0, RZ, 0x1 ; SHF.R.S32.HI R0, RZ, 0x1, R0 ; IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; LDG.E R0, [R4.64] ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x160] ; I2F.F64 R2, c[0x0][0x170] ; FADD R10, R10, c[0x0][0x164] ; F2F.F64.F32 R6, R10 ; DADD R2, R2, R2 ; DMUL R6, R6, 0.5 ; DMUL R2, R2, R6 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; MUFU.RCP64H R7, R3 ; DFMA R8, -R2, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R10, -R2, R8, 1 ; DFMA R10, R8, R10, R8 ; F2F.F64.F32 R4, R0 ; DMUL R4, R4, 10 ; DMUL R6, R4, c[0x2][0x0] ; DMUL R4, R6, R10 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; DFMA R8, -R2, R4, R6 ; DFMA R4, R10, R8, R4 ; FFMA R8, RZ, R3, R5 ; FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x230 ; MOV R0, 0x230 ; CALL.REL.NOINC 0x280 ; F2F.F32.F64 R5, R4 ; IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x0] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x4] ; STG.E [R2.64], R5 ; EXIT ; FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; LOP3.LUT R4, R3.reuse, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; LOP3.LUT R14, R3, 0x7ff00000, RZ, 0xc0, !PT ; LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R4, RZ, RZ, R2 ; LOP3.LUT R12, R7, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P1, PT, R12, R14, PT ; @!P0 DMUL R4, R2, 8.98846567431157953865e+307 ; SEL R15, R13, 0x63400000, !P1 ; FSETP.GEU.AND P1, PT, |R7|, 1.469367938527859385e-39, PT ; MUFU.RCP64H R9, R5 ; @!P0 LOP3.LUT R14, R5, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R10, R8, -R4, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R4, 1 ; DFMA R10, R10, R8, R10 ; LOP3.LUT R9, R15, 0x800fffff, R7, 0xf8, !PT ; IMAD.MOV.U32 R15, RZ, RZ, R12 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; @P1 BRA 0x470 ; LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R16, RZ, RZ, RZ ; ISETP.GE.U32.AND P0, PT, R12, R15, PT ; SEL R15, R13, 0x63400000, !P0 ; LOP3.LUT R15, R15, 0x80000000, R7, 0xf8, !PT ; LOP3.LUT R17, R15, 0x100000, RZ, 0xfc, !PT ; DFMA R8, R8, 2, -R16 ; LOP3.LUT R15, R9, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R18, R15, -0x1, RZ ; DMUL R16, R10, R8 ; IADD3 R20, R14, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ; DFMA R18, R16, -R4, R8 ; ISETP.GT.U32.OR P0, PT, R20, 0x7feffffe, P0 ; DFMA R10, R10, R18, R16 ; @P0 BRA 0x6b0 ; LOP3.LUT R7, R3, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R12.reuse, R7, PT ; IMAD.IADD R6, R12, 0x1, -R7 ; SEL R13, R13, 0x63400000, !P0 ; IMNMX R6, R6, -0x46a00000, !PT ; IMNMX R6, R6, 0x46a00000, PT ; IMAD.IADD R14, R6, 0x1, -R13 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IADD3 R7, R14, 0x7fe00000, RZ ; DMUL R12, R10, R6 ; FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; @P0 BRA 0x800 ; DFMA R4, R10, -R4, R8 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; LOP3.LUT R9, R5, 0x80000000, R3, 0x48, !PT ; LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; @!P0 BRA 0x800 ; IMAD.MOV R3, RZ, RZ, -R14 ; DMUL.RP R6, R10, R6 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; DFMA R2, R12, -R2, R10 ; LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; IADD3 R2, -R14, -0x43300000, RZ ; FSETP.NEU.AND P0, PT, |R3|, R2, PT ; FSEL R12, R6, R12, !P0 ; FSEL R13, R9, R13, !P0 ; BRA 0x800 ; DSETP.NAN.AND P0, PT, R6, R6, PT ; @P0 BRA 0x7e0 ; DSETP.NAN.AND P0, PT, R2, R2, PT ; @P0 BRA 0x7b0 ; ISETP.NE.AND P0, PT, R15, R14, PT ; IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; @!P0 BRA 0x800 ; ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; LOP3.LUT R13, R7, 0x80000000, R3, 0x48, !PT ; ISETP.EQ.OR P0, PT, R14, RZ, !P0 ; @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; BRA 0x800 ; LOP3.LUT R13, R3, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R12, RZ, RZ, R2 ; BRA 0x800 ; LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R12, RZ, RZ, R6 ; IMAD.MOV.U32 R2, RZ, RZ, R0 ; IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, R12 ; IMAD.MOV.U32 R5, RZ, RZ, R13 ; RET.REL.NODEC R2 0x0 ; BRA 0x850; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IABS R7, c[0x0][0x16c] ; S2R R0, SR_CTAID.X ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x170] ; IADD3 R1, R1, -0x48, RZ ; I2F.RP R4, R7 ; S2R R5, SR_TID.X ; MUFU.RCP R4, R4 ; IMAD R0, R0, c[0x0][0x0], R5 ; IADD3 R2, R4, 0xffffffe, RZ ; IABS R4, R0 ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.MOV R6, RZ, RZ, -R3 ; IMAD R5, R6, R7, RZ ; IMAD.HI.U32 R3, R3, R5, R2 ; IMAD.HI.U32 R16, R3, R4, RZ ; IMAD.MOV R3, RZ, RZ, -R16 ; IMAD R2, R7.reuse, R3, R4 ; MUFU.RCP R3, c[0x0][0x174] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x174] ; ISETP.GT.U32.AND P1, PT, R7, R2, PT ; @!P1 IMAD.IADD R2, R2, 0x1, -R7 ; @!P1 IADD3 R16, R16, 0x1, RZ ; ISETP.NE.AND P1, PT, RZ, c[0x0][0x16c], PT ; ISETP.GE.U32.AND P0, PT, R2, R7, PT ; LOP3.LUT R2, R0, c[0x0][0x16c], RZ, 0x3c, !PT ; ISETP.GE.AND P2, PT, R2, RZ, PT ; FFMA R2, R3, -R4, 1 ; FFMA R2, R3, R2, R3 ; @P0 IADD3 R16, R16, 0x1, RZ ; FCHK P0, R9, c[0x0][0x174] ; FFMA R3, R2, c[0x0][0x170], RZ ; @!P2 IMAD.MOV R16, RZ, RZ, -R16 ; @!P1 LOP3.LUT R16, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; FFMA R4, R3, -R4, c[0x0][0x170] ; IMAD.MOV R5, RZ, RZ, -R16 ; FFMA R2, R2, R4, R3 ; IMAD R6, R5, c[0x0][0x16c], R0 ; @!P0 BRA 0x2c0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x174] ; MOV R4, 0x2b0 ; CALL.REL.NOINC 0x4dd0 ; IMAD.MOV.U32 R2, RZ, RZ, R3 ; MUFU.RCP R3, c[0x0][0x178] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x170] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x178] ; FCHK P0, R9, c[0x0][0x178] ; FFMA R4, R3, -R5, 1 ; FFMA R3, R3, R4, R3 ; FFMA R4, R3, c[0x0][0x170], RZ ; FFMA R5, R4, -R5, c[0x0][0x170] ; FFMA R3, R3, R5, R4 ; @!P0 BRA 0x390 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; MOV R4, 0x390 ; CALL.REL.NOINC 0x4dd0 ; ULDC.64 UR4, c[0x0][0x168] ; UIMAD UR4, UR5, UR4, -0x4 ; ISETP.GE.AND P0, PT, R0, UR4, PT ; ISETP.LT.OR P0, PT, R0, 0x4, P0 ; @P0 EXIT ; ULDC.S8 UR4, c[0x0][0x238] ; IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; ISETP.NE.AND P0, PT, RZ, UR4, PT ; ULDC.64 UR8, c[0x0][0x118] ; BSSY B0, 0xf80 ; IMAD.WIDE R20, R0, R19, c[0x0][0x218] ; IMAD.WIDE R18, R0, R19, c[0x0][0x210] ; @!P0 BRA 0xf50 ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x234] ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x1a8] ; IADD3 R5, R5, -0x1, RZ ; IADD3 R4, R7, c[0x0][0x228], RZ ; IMAD R5, R5, c[0x0][0x22c], R4 ; IADD3 R4, R6, -c[0x0][0x230], -R7 ; IMAD.IADD R5, R16, 0x1, -R5 ; IMAD R5, R5, R5, RZ ; IMAD R5, R4, R4, R5 ; ISETP.GE.U32.AND P0, PT, R5, 0xe2, PT ; @!P0 BRA 0x540 ; LDG.E R15, [R20.64] ; LDG.E R4, [R18.64] ; BRA 0xf70 ; ISETP.GE.U32.AND P0, PT, R5, 0x11, PT ; IMAD.MOV.U32 R15, RZ, RZ, RZ ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; @!P0 BRA 0xf70 ; I2F R34, R5 ; BSSY B1, 0x670 ; IADD3 R4, R34, -0xd000000, RZ ; MUFU.RSQ R9, R34 ; ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; @!P0 BRA 0x620 ; MOV R28, 0x600 ; CALL.REL.NOINC 0x4c70 ; IMAD.MOV.U32 R7, RZ, RZ, R36 ; BRA 0x660 ; FMUL.FTZ R7, R34, R9 ; FMUL.FTZ R5, R9, 0.5 ; FFMA R4, -R7, R7, R34 ; FFMA R7, R4, R5, R7 ; BSYNC B1 ; MUFU.RCP64H R9, 44 ; IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; BSSY B1, 0x7e0 ; IMAD.MOV.U32 R13, RZ, RZ, 0x40460000 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; FADD R7, R7, -4 ; DFMA R4, R8, -R12, 1 ; DFMA R10, R4, R4, R4 ; F2F.F64.F32 R4, R7 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R12, 1 ; DFMA R8, R10, R8, R10 ; DMUL R14, R4, 4 ; DMUL R4, R14, R8 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R10, R4, -44, R14 ; DFMA R4, R8, R10, R4 ; FFMA R8, RZ, 3.09375, R5 ; FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7d0 ; MOV R10, 0x7d0 ; CALL.REL.NOINC 0x4750 ; BSYNC B1 ; DMUL R22, R4, c[0x2][0x0] ; BSSY B1, 0x9d0 ; IADD3 R15, R1, c[0x0][0x20], RZ ; LOP3.LUT R4, R23, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.EQ.AND P0, PT, R22, RZ, PT ; ISETP.NE.AND P3, PT, R4, 0x7ff00000, PT ; ISETP.EQ.AND P2, PT, R22, RZ, PT ; @!P3 BRA P0, 0x9a0 ; DMUL R8, R22.reuse, c[0x2][0x8] ; BSSY B2, 0x980 ; DSETP.GE.AND P0, PT, |R22|, 2.14748364800000000000e+09, PT ; F2I.F64 R8, R8 ; I2F.F64 R10, R8 ; STL [R1], R8 ; DFMA R4, -R10, c[0x2][0x10], R22 ; DFMA R4, -R10, c[0x2][0x18], R4 ; DFMA R4, -R10, c[0x2][0x20], R4 ; @!P0 BRA 0x970 ; BSSY B3, 0x960 ; IMAD.MOV.U32 R5, RZ, RZ, R22 ; MOV R24, 0x950 ; IMAD.MOV.U32 R17, RZ, RZ, R23 ; CALL.REL.NOINC 0x5410 ; BSYNC B3 ; LDL R8, [R1] ; BSYNC B2 ; IADD3 R14, R8, 0x1, RZ ; BRA 0x9c0 ; DMUL R4, RZ, R22 ; IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; BSYNC B1 ; IMAD.SHL.U32 R7, R14, 0x8, RZ ; IMAD.MOV.U32 R32, RZ, RZ, 0x8 ; LOP3.LUT R7, R7, 0x8, RZ, 0xc0, !PT ; IMAD.WIDE R32, R7, R32, c[0x4][0x10] ; LDG.E R7, [R20.64] ; LDG.E.64.CONSTANT R30, [R32.64+0x8] ; LDG.E.64.CONSTANT R28, [R32.64+0x10] ; LDG.E.64.CONSTANT R26, [R32.64+0x18] ; LDG.E.64.CONSTANT R10, [R32.64+0x20] ; LDG.E.64.CONSTANT R8, [R32.64+0x28] ; LDG.E.64.CONSTANT R12, [R32.64+0x30] ; R2P PR, R14, 0x3 ; IMAD.MOV.U32 R34, RZ, RZ, 0x79785eba ; IMAD.MOV.U32 R14, RZ, RZ, 0x3de5db65 ; DMUL R24, R4, R4 ; FSEL R34, -R34, 4.2945490664224492434e-19, !P0 ; FSEL R35, R14, -0.082518599927425384521, !P0 ; BSSY B1, 0xd40 ; DFMA R30, R24, R34, R30 ; DFMA R28, R24, R30, R28 ; DFMA R26, R24, R28, R26 ; DFMA R10, R24, R26, R10 ; DFMA R8, R24, R10, R8 ; DFMA R8, R24, R8, R12 ; DFMA R4, R8, R4, R4 ; @P0 DFMA R4, R24, R8, 1 ; F2F.F64.F32 R20, R7 ; @P1 DFMA R4, R4, -1, RZ ; DADD R4, -R4, 1 ; DMUL R4, R4, 0.5 ; DMUL R20, R4, R20 ; @!P3 BRA P2, 0xd10 ; DMUL R8, R22.reuse, c[0x2][0x8] ; BSSY B2, 0xcf0 ; DSETP.GE.AND P0, PT, |R22|, 2.14748364800000000000e+09, PT ; F2I.F64 R8, R8 ; I2F.F64 R10, R8 ; STL [R1], R8 ; DFMA R4, -R10, c[0x2][0x10], R22 ; DFMA R4, -R10, c[0x2][0x18], R4 ; DFMA R4, -R10, c[0x2][0x20], R4 ; @!P0 BRA 0xce0 ; BSSY B3, 0xcd0 ; IMAD.MOV.U32 R5, RZ, RZ, R22 ; MOV R24, 0xcc0 ; IMAD.MOV.U32 R17, RZ, RZ, R23 ; CALL.REL.NOINC 0x5410 ; BSYNC B3 ; LDL R8, [R1] ; BSYNC B2 ; IADD3 R8, R8, 0x1, RZ ; BRA 0xd30 ; DMUL R4, RZ, R22 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSYNC B1 ; IMAD.SHL.U32 R7, R8, 0x8, RZ ; LDG.E R18, [R18.64] ; IMAD.MOV.U32 R26, RZ, RZ, 0x8 ; LOP3.LUT R7, R7, 0x8, RZ, 0xc0, !PT ; IMAD.WIDE R26, R7, R26, c[0x4][0x10] ; LDG.E.64.CONSTANT R28, [R26.64+0x8] ; LDG.E.64.CONSTANT R24, [R26.64+0x10] ; LDG.E.64.CONSTANT R22, [R26.64+0x18] ; LDG.E.64.CONSTANT R14, [R26.64+0x20] ; LDG.E.64.CONSTANT R10, [R26.64+0x28] ; LDG.E.64.CONSTANT R12, [R26.64+0x30] ; R2P PR, R8, 0x3 ; IMAD.MOV.U32 R30, RZ, RZ, 0x79785eba ; IMAD.MOV.U32 R7, RZ, RZ, 0x3de5db65 ; DMUL R8, R4, R4 ; FSEL R30, -R30, 4.2945490664224492434e-19, !P0 ; FSEL R31, R7, -0.082518599927425384521, !P0 ; DFMA R28, R8, R30, R28 ; DFMA R24, R8, R28, R24 ; DFMA R22, R8, R24, R22 ; DFMA R14, R8, R22, R14 ; DFMA R10, R8, R14, R10 ; DFMA R10, R8, R10, R12 ; DFMA R4, R10, R4, R4 ; @P0 DFMA R4, R8, R10, 1 ; F2F.F64.F32 R8, R18 ; @P1 DFMA R4, R4, -1, RZ ; DADD R4, -R4, 1 ; DMUL R4, R4, 0.5 ; DMUL R4, R4, R8 ; F2F.F32.F64 R15, R20 ; F2F.F32.F64 R4, R4 ; BRA 0xf70 ; LDG.E R15, [R20.64] ; LDG.E R4, [R18.64] ; BSYNC B0 ; UMOV UR5, 0x4 ; ULDC.64 UR6, c[0x0][0x168] ; UIADD3 UR4, -UR5, UR6, URZ ; ISETP.GE.AND P0, PT, R16, UR4, PT ; UIADD3 UR4, -UR5, UR7, URZ ; ISETP.LT.OR P0, PT, R16, 0x4, P0 ; ISETP.LT.OR P0, PT, R6, 0x4, P0 ; ISETP.GE.OR P0, PT, R6, UR4, P0 ; @P0 EXIT ; IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; IMAD.WIDE R26, R0, R11, c[0x0][0x180] ; LDG.E R17, [R26.64] ; LDG.E R28, [R26.64+-0x4] ; IADD3 R44, R0, -c[0x0][0x16c], RZ ; LDG.E R42, [R26.64+-0x8] ; LDG.E R41, [R26.64+0x4] ; IMAD.MOV R29, RZ, RZ, -c[0x0][0x16c] ; IMAD.WIDE R20, R0, R11.reuse, c[0x0][0x188] ; LDG.E R31, [R26.64+-0x10] ; IMAD R36, R29, 0x2, R0 ; LDG.E R7, [R20.64] ; IMAD.WIDE R8, R44, R11, c[0x0][0x180] ; LDG.E R10, [R26.64+0xc] ; IMAD.WIDE R44, R44, R11, c[0x0][0x188] ; LDG.E R8, [R8.64] ; IMAD.WIDE R12, R36, R11, c[0x0][0x180] ; LDG.E R30, [R44.64] ; IMAD.WIDE R36, R36, R11, c[0x0][0x188] ; LDG.E R34, [R20.64+-0x4] ; IMAD.WIDE R24, R11, c[0x0][0x16c], R26 ; LDG.E R9, [R12.64] ; IMAD.WIDE R22, R11, c[0x0][0x16c], R20 ; LDG.E R18, [R24.64] ; LDG.E R36, [R36.64] ; LDG.E R19, [R22.64] ; LDG.E R32, [R20.64+-0x8] ; LDG.E R5, [R20.64+0x4] ; LDG.E R38, [R26.64+-0xc] ; LDG.E R35, [R26.64+0x8] ; IMAD.MOV.U32 R33, RZ, RZ, c[0x0][0x16c] ; LDG.E R12, [R20.64+-0xc] ; IMAD R44, R33, 0x2, R0 ; LDG.E R13, [R20.64+0x8] ; LDG.E R14, [R20.64+-0x10] ; LDG.E R33, [R20.64+0xc] ; IMAD.WIDE R20, R0, R11, c[0x0][0x220] ; IMAD.WIDE R24, R44, R11, c[0x0][0x188] ; IMAD.MOV.U32 R45, RZ, RZ, c[0x0][0x16c] ; LDG.E R39, [R24.64] ; IMAD.WIDE R22, R44, R11, c[0x0][0x180] ; IMAD R40, R29, 0x4, R0 ; LDG.E R37, [R22.64] ; IMAD R24, R45, -0x5, R44 ; IMAD.WIDE R26, R40, R11, c[0x0][0x180] ; IMAD.WIDE R22, R24, R11, c[0x0][0x180] ; IMAD R44, R45, 0x6, R24 ; LDG.E R22, [R22.64] ; IMAD.WIDE R24, R24, R11, c[0x0][0x188] ; LDG.E R24, [R24.64] ; FADD R43, R17, -R28 ; FFMA R43, R43, c[0x3][0x0], RZ ; FADD R41, -R42, R41 ; FFMA R43, R41, c[0x3][0x4], R43 ; LDG.E R41, [R20.64] ; IMAD.WIDE R28, R40, R11, c[0x0][0x188] ; LDG.E R40, [R26.64] ; LDG.E R42, [R28.64] ; FADD R8, -R8, R17 ; IMAD.WIDE R26, R44, R11, c[0x0][0x180] ; FADD R30, R7, -R30 ; FFMA R8, R8, c[0x3][0x0], RZ ; LDG.E R27, [R26.64] ; FFMA R30, R30, c[0x3][0x0], RZ ; FADD R9, -R9, R18 ; IMAD.WIDE R28, R44, R11, c[0x0][0x188] ; FADD R19, -R36, R19 ; LDG.E R29, [R28.64] ; FADD R26, -R31, R10 ; FFMA R23, R9, c[0x3][0x4], R8 ; FFMA R10, R19, c[0x3][0x4], R30 ; IMAD.WIDE R8, R6, R11, c[0x0][0x200] ; IMAD.WIDE R18, R16, R11.reuse, c[0x0][0x1f0] ; LDG.E R28, [R8.64] ; FADD R34, -R34, R7 ; LDG.E R25, [R18.64] ; IMAD.WIDE R30, R0, R11, c[0x0][0x1a0] ; FADD R32, -R32, R5 ; FADD R38, -R38, R35 ; FFMA R5, R34, c[0x3][0x0], RZ ; IMAD.WIDE R6, R6, R11, c[0x0][0x208] ; IMAD.WIDE R34, R0, R11, c[0x0][0x1b8] ; IMAD.WIDE R16, R16, R11, c[0x0][0x1f8] ; LDG.E R11, [R30.64] ; FFMA R5, R32, c[0x3][0x4], R5 ; LDG.E R32, [R6.64] ; LDG.E R45, [R16.64] ; LDG.E R34, [R34.64] ; FADD R12, -R12, R13 ; FFMA R5, R12, c[0x3][0x8], R5 ; FADD R14, -R14, R33 ; FADD R12, -R22, R37 ; FFMA R13, R12, c[0x3][0x8], R23 ; FFMA R12, R14, c[0x3][0xc], R5 ; FADD R39, -R24, R39 ; IMAD.MOV.U32 R23, RZ, RZ, 0x40000000 ; FFMA R10, R39, c[0x3][0x8], R10 ; BSSY B0, 0x1b90 ; FFMA R43, R38, c[0x3][0x8], R43 ; FFMA R26, R26, c[0x3][0xc], R43 ; FMUL R36, R41, 0.63661974668502807617 ; F2I.NTZ R36, R36 ; FSETP.GE.AND P0, PT, |R41|, 105615, PT ; I2F R22, R36 ; FADD R40, -R40, R27 ; IMAD.MOV.U32 R35, RZ, RZ, R36 ; FADD R29, -R42, R29 ; FFMA R5, R22, -1.5707962512969970703, R41 ; FFMA R5, R22, -7.5497894158615963534e-08, R5 ; FFMA R14, R29, c[0x3][0xc], R10 ; FMUL R28, R28, R25 ; FFMA R10, R15, R23, 1 ; FFMA R27, R22, -5.3903029534742383927e-15, R5 ; SHF.R.S32.HI R15, RZ, 0x1f, R0 ; FFMA R13, R40, c[0x3][0xc], R13 ; IMAD.MOV.U32 R5, RZ, RZ, R27 ; FMUL R28, R28, R11 ; FMUL R25, R11, R28 ; FMUL R45, R32, R45 ; FMUL R25, R25, R10 ; FMUL R34, R45, R34 ; @!P0 BRA 0x1b80 ; FSETP.NEU.AND P1, PT, |R41|, +INF , PT ; @!P1 BRA 0x1b60 ; SHF.R.U32.HI R5, RZ, 0x17, R41 ; IMAD.SHL.U32 R22, R41, 0x100, RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R36, RZ, RZ, RZ ; LOP3.LUT R22, R22, 0x80000000, RZ, 0xfc, !PT ; ULDC.64 UR6, c[0x4][0x8] ; IADD3 R11, R5, -0x80, RZ ; IMAD.MOV.U32 R5, RZ, RZ, R1 ; SHF.R.U32.HI R24, RZ, 0x5, R11 ; IMAD.U32 R29, RZ, RZ, UR7 ; IMAD.U32 R28, RZ, RZ, UR6 ; LDG.E.CONSTANT R29, [R28.64] ; IADD3 R36, R36, 0x1, RZ ; UIADD3 UR6, UP0, UR6, 0x4, URZ ; ISETP.NE.AND P1, PT, R36, 0x6, PT ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD.WIDE.U32 R32, R29, R22, RZ ; IADD3 R32, P2, R32, R10, RZ ; IADD3.X R10, R33, UR4, RZ, P2, !PT ; STL [R5], R32 ; IADD3 R5, R5, 0x4, RZ ; @P1 BRA 0x1880 ; LOP3.LUT P1, R29, R11, 0x1f, RZ, 0xc0, !PT ; STL [R1+0x18], R10 ; IADD3 R22, -R24.reuse, 0x4, RZ ; IADD3 R24, -R24, 0x6, RZ ; IMAD R32, R24, 0x4, R1 ; @P1 IMAD R33, R22, 0x4, R1 ; LDL R5, [R32] ; @P1 LDL R24, [R33] ; LDL R22, [R32+-0x4] ; @P1 IADD3 R11, -R29, 0x20, RZ ; @P1 SHF.R.U32.HI R28, RZ, R11, R24 ; @P1 SHF.L.U32 R24, R5, R29, RZ ; @P1 SHF.R.U32.HI R11, RZ, R11, R22 ; @P1 SHF.L.U32 R29, R22, R29, RZ ; @P1 IMAD.IADD R5, R11, 0x1, R24 ; @P1 IMAD.IADD R22, R28, 0x1, R29 ; SHF.L.U32.HI R11, R22, 0x2, R5 ; SHF.R.U32.HI R36, RZ, 0x1f, R11 ; ISETP.NE.AND P1, PT, R36, RZ, PT ; IMAD.SHL.U32 R10, R22, 0x4, RZ ; @P1 LOP3.LUT R11, RZ, R11, RZ, 0x33, !PT ; @P1 LOP3.LUT R10, RZ, R10, RZ, 0x33, !PT ; I2F.F64.S64 R10, R10 ; LOP3.LUT P2, R22, R41, 0x80000000, RZ, 0xc0, !PT ; DMUL R28, R10, c[0x2][0x28] ; LEA.HI R36, R5, R36, RZ, 0x2 ; F2F.F32.F64 R28, R28 ; @P1 LOP3.LUT R22, R22, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV R5, RZ, RZ, -R36 ; ISETP.NE.AND P1, PT, R22, RZ, PT ; @P2 IMAD.MOV.U32 R36, RZ, RZ, R5 ; FSEL R5, R28, -R28, !P1 ; BRA 0x1b80 ; FMUL R5, RZ, R41 ; IMAD.MOV.U32 R36, RZ, RZ, RZ ; BSYNC B0 ; IADD3 R29, R36, 0x1, RZ ; IMAD.MOV.U32 R24, RZ, RZ, 0x3c0885e4 ; BSSY B0, 0x2090 ; FMUL R28, R5, R5 ; LOP3.LUT P2, RZ, R29.reuse, 0x1, RZ, 0xc0, !PT ; IMAD.MOV.U32 R36, RZ, RZ, 0x3e2aaaa8 ; LOP3.LUT P1, RZ, R29, 0x2, RZ, 0xc0, !PT ; IMAD.MOV.U32 R10, RZ, RZ, -0x46b2bead ; FSEL R11, R24, 0.041666727513074874878, !P2 ; FSEL R37, R5, 1, !P2 ; FSEL R5, -R36, -0.4999999701976776123, !P2 ; @P2 IMAD.MOV.U32 R22, RZ, RZ, 0x37cbac00 ; @P2 FFMA R10, R28.reuse, R22, -0.0013887860113754868507 ; FFMA R22, R37, R28, RZ ; FFMA R10, R28, R10, R11 ; FFMA R5, R28, R10, R5 ; FFMA R37, R5, R22, R37 ; @P1 FFMA R37, R37, -1, RZ ; @!P0 BRA 0x2080 ; FSETP.NEU.AND P0, PT, |R41|, +INF , PT ; @!P0 BRA 0x2060 ; SHF.R.U32.HI R5, RZ, 0x17, R41 ; IMAD.SHL.U32 R22, R41, 0x100, RZ ; CS2R R10, SRZ ; UMOV UR4, URZ ; LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; ULDC.64 UR6, c[0x4][0x8] ; LOP3.LUT R35, R22, 0x80000000, RZ, 0xfc, !PT ; IADD3 R27, R5, -0x80, RZ ; IMAD.MOV.U32 R5, RZ, RZ, R1 ; SHF.R.U32.HI R38, RZ, 0x5, R27 ; IMAD.U32 R28, RZ, RZ, UR6 ; IMAD.U32 R29, RZ, RZ, UR7 ; LDG.E.CONSTANT R28, [R28.64] ; IADD3 R11, R11, 0x1, RZ ; UIADD3 UR6, UP0, UR6, 0x4, URZ ; ISETP.NE.AND P0, PT, R11, 0x6, PT ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD.WIDE.U32 R32, R28, R35, RZ ; IADD3 R22, P1, R32, R10, RZ ; IADD3.X R10, R33, UR4, RZ, P1, !PT ; STL [R5], R22 ; IADD3 R5, R5, 0x4, RZ ; @P0 BRA 0x1d80 ; LOP3.LUT P0, R32, R27, 0x1f, RZ, 0xc0, !PT ; STL [R1+0x18], R10 ; IADD3 R22, -R38.reuse, 0x4, RZ ; IADD3 R38, -R38, 0x6, RZ ; IMAD R38, R38, 0x4, R1 ; @P0 IMAD R33, R22, 0x4, R1 ; LDL R5, [R38] ; @P0 LDL R11, [R33] ; LDL R22, [R38+-0x4] ; @P0 IADD3 R29, -R32, 0x20, RZ ; LOP3.LUT P1, R41, R41, 0x80000000, RZ, 0xc0, !PT ; @P0 SHF.L.U32 R28, R5, R32.reuse, RZ ; @P0 SHF.R.U32.HI R27, RZ, R29.reuse, R11 ; @P0 SHF.R.U32.HI R11, RZ, R29, R22 ; @P0 SHF.L.U32 R32, R22, R32, RZ ; @P0 IMAD.IADD R5, R11, 0x1, R28 ; @P0 IMAD.IADD R22, R27, 0x1, R32 ; SHF.L.U32.HI R11, R22, 0x2, R5 ; SHF.R.U32.HI R32, RZ, 0x1f, R11 ; ISETP.NE.AND P0, PT, R32, RZ, PT ; IMAD.SHL.U32 R10, R22, 0x4, RZ ; @P0 LOP3.LUT R11, RZ, R11, RZ, 0x33, !PT ; @P0 LOP3.LUT R10, RZ, R10, RZ, 0x33, !PT ; I2F.F64.S64 R10, R10 ; DMUL R28, R10, c[0x2][0x28] ; LEA.HI R35, R5, R32, RZ, 0x2 ; F2F.F32.F64 R28, R28 ; @P0 LOP3.LUT R41, R41, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV R5, RZ, RZ, -R35 ; ISETP.NE.AND P0, PT, R41, RZ, PT ; @P1 IMAD.MOV.U32 R35, RZ, RZ, R5 ; FSEL R27, R28, -R28, !P0 ; BRA 0x2080 ; FMUL R27, RZ, R41 ; IMAD.MOV.U32 R35, RZ, RZ, RZ ; BSYNC B0 ; LOP3.LUT P1, RZ, R35, 0x1, RZ, 0xc0, !PT ; FMUL R22, R27, R27 ; LOP3.LUT P0, RZ, R35, 0x2, RZ, 0xc0, !PT ; IMAD.MOV.U32 R5, RZ, RZ, -0x46b2bead ; FSEL R24, R24, 0.041666727513074874878, !P1 ; FMUL R37, R37, R2 ; FSEL R27, R27, 1, !P1 ; FSEL R36, -R36, -0.4999999701976776123, !P1 ; SHF.L.U64.HI R15, R0, 0x2, R15 ; FFMA R10, R27, R22, RZ ; @P1 IMAD.MOV.U32 R11, RZ, RZ, 0x37cbac00 ; @P1 FFMA R5, R22, R11, -0.0013887860113754868507 ; FFMA R5, R22, R5, R24 ; FFMA R5, R22, R5, R36 ; FFMA R10, R5, R10, R27 ; IMAD.SHL.U32 R5, R0, 0x4, RZ ; @P0 FFMA R10, R10, -1, RZ ; FMUL R11, R10, R3 ; IADD3 R10, P0, R5, c[0x0][0x1b0], RZ ; FMUL R22, R26, R11 ; IADD3.X R11, R15, c[0x0][0x1b4], RZ, P0, !PT ; FFMA R22, R13, R37, -R22 ; FFMA R25, -R25, R22, R34 ; STG.E [R10.64], R25 ; LDG.E R22, [R20.64] ; IADD3 R28, P0, R5, c[0x0][0x1c8], RZ ; LDG.E R32, [R8.64] ; IADD3.X R29, R15, c[0x0][0x1cc], RZ, P0, !PT ; LDG.E R33, [R18.64] ; LDG.E R24, [R6.64] ; LDG.E R27, [R16.64] ; LDG.E R35, [R30.64] ; LDG.E R29, [R28.64] ; BSSY B0, 0x2790 ; FMUL R0, R22, 0.63661974668502807617 ; F2I.NTZ R0, R0 ; FSETP.GE.AND P0, PT, |R22|, 105615, PT ; I2F R25, R0 ; FMUL R32, R32, R33 ; FMUL R24, R24, R27 ; FMUL R32, R32, R35 ; FFMA R34, R25, -1.5707962512969970703, R22 ; FFMA R34, R25, -7.5497894158615963534e-08, R34 ; FFMA R25, R25, -5.3903029534742383927e-15, R34 ; FFMA R34, R4, R23, 1 ; FMUL R24, R24, R29 ; FMUL R23, R35, R32 ; IMAD.MOV.U32 R37, RZ, RZ, R0 ; IMAD.MOV.U32 R4, RZ, RZ, R25 ; @!P0 BRA 0x2780 ; FSETP.NEU.AND P1, PT, |R22|, +INF , PT ; @!P1 BRA 0x2760 ; SHF.R.U32.HI R0, RZ, 0x17, R22 ; IMAD.SHL.U32 R28, R22, 0x100, RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R38, RZ, RZ, RZ ; LOP3.LUT R4, R0, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; LOP3.LUT R35, R28, 0x80000000, RZ, 0xfc, !PT ; ULDC.64 UR6, c[0x4][0x8] ; IADD3 R27, R4, -0x80, RZ ; IMAD.MOV.U32 R4, RZ, RZ, R1 ; SHF.R.U32.HI R36, RZ, 0x5, R27 ; IMAD.U32 R28, RZ, RZ, UR6 ; IMAD.U32 R29, RZ, RZ, UR7 ; LDG.E.CONSTANT R28, [R28.64] ; IADD3 R38, R38, 0x1, RZ ; UIADD3 UR6, UP0, UR6, 0x4, URZ ; ISETP.NE.AND P1, PT, R38, 0x6, PT ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD.WIDE.U32 R32, R28, R35, RZ ; IADD3 R39, P2, R32, R0, RZ ; IADD3.X R0, R33, UR4, RZ, P2, !PT ; STL [R4], R39 ; IADD3 R4, R4, 0x4, RZ ; @P1 BRA 0x2480 ; LOP3.LUT P1, R33, R27, 0x1f, RZ, 0xc0, !PT ; STL [R1+0x18], R0 ; IADD3 R4, -R36.reuse, 0x4, RZ ; IADD3 R36, -R36, 0x6, RZ ; IMAD R36, R36, 0x4, R1 ; @P1 IMAD R35, R4, 0x4, R1 ; LDL R27, [R36+-0x4] ; @P1 LDL R29, [R35] ; LDL R4, [R36] ; @P1 IADD3 R28, -R33, 0x20, RZ ; @P1 SHF.R.U32.HI R32, RZ, R28.reuse, R29 ; @P1 SHF.R.U32.HI R28, RZ, R28, R27 ; @P1 SHF.L.U32 R29, R4, R33.reuse, RZ ; @P1 SHF.L.U32 R33, R27, R33, RZ ; @P1 IMAD.IADD R4, R28, 0x1, R29 ; @P1 IMAD.IADD R27, R32, 0x1, R33 ; SHF.L.U32.HI R29, R27, 0x2, R4 ; SHF.R.U32.HI R35, RZ, 0x1f, R29 ; ISETP.NE.AND P1, PT, R35, RZ, PT ; IMAD.SHL.U32 R28, R27, 0x4, RZ ; @P1 LOP3.LUT R29, RZ, R29, RZ, 0x33, !PT ; @P1 LOP3.LUT R28, RZ, R28, RZ, 0x33, !PT ; I2F.F64.S64 R28, R28 ; LOP3.LUT P2, R27, R22, 0x80000000, RZ, 0xc0, !PT ; DMUL R32, R28, c[0x2][0x28] ; LEA.HI R0, R4, R35, RZ, 0x2 ; F2F.F32.F64 R32, R32 ; @P1 LOP3.LUT R27, R27, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV R4, RZ, RZ, -R0 ; ISETP.NE.AND P1, PT, R27, RZ, PT ; @P2 IMAD.MOV.U32 R0, RZ, RZ, R4 ; FSEL R4, R32, -R32, !P1 ; BRA 0x2780 ; FMUL R4, RZ, R22 ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; BSYNC B0 ; IADD3 R27, R34, -0xd000000, RZ ; MUFU.RSQ R29, R34 ; BSSY B0, 0x2860 ; ISETP.GT.U32.AND P1, PT, R27, 0x727fffff, PT ; @!P1 BRA 0x2810 ; MOV R28, 0x2800 ; CALL.REL.NOINC 0x4c70 ; BRA 0x2850 ; FMUL.FTZ R27, R34, R29 ; FMUL.FTZ R36, R29, 0.5 ; FFMA R34, -R27, R27, R34 ; FFMA R36, R34, R36, R27 ; BSYNC B0 ; LOP3.LUT P2, RZ, R0.reuse, 0x1, RZ, 0xc0, !PT ; IMAD.MOV.U32 R27, RZ, RZ, 0x3c0885e4 ; LOP3.LUT P1, RZ, R0, 0x2, RZ, 0xc0, !PT ; FMUL R35, R4.reuse, R4 ; FSEL R4, R4, 1, !P2 ; IMAD.MOV.U32 R32, RZ, RZ, 0x3e2aaaa8 ; FSEL R29, R27, 0.041666727513074874878, !P2 ; IMAD.MOV.U32 R28, RZ, RZ, -0x46b2bead ; BSSY B0, 0x2d60 ; FFMA R0, R4, R35, RZ ; FSEL R33, -R32, -0.4999999701976776123, !P2 ; @P2 IMAD.MOV.U32 R34, RZ, RZ, 0x37cbac00 ; @P2 FFMA R28, R35, R34, -0.0013887860113754868507 ; FFMA R28, R35, R28, R29 ; FFMA R33, R35, R28, R33 ; FFMA R33, R33, R0, R4 ; @P1 FFMA R33, R33, -1, RZ ; @!P0 BRA 0x2d50 ; FSETP.NEU.AND P0, PT, |R22|, +INF , PT ; @!P0 BRA 0x2d30 ; SHF.R.U32.HI R0, RZ, 0x17, R22 ; IMAD.SHL.U32 R28, R22, 0x100, RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R25, RZ, RZ, RZ ; LOP3.LUT R39, R28, 0x80000000, RZ, 0xfc, !PT ; ULDC.64 UR6, c[0x4][0x8] ; IADD3 R38, R0, -0x80, RZ ; IMAD.MOV.U32 R0, RZ, RZ, R1 ; SHF.R.U32.HI R40, RZ, 0x5, R38 ; IMAD.U32 R28, RZ, RZ, UR6 ; IMAD.U32 R29, RZ, RZ, UR7 ; LDG.E.CONSTANT R28, [R28.64] ; IADD3 R25, R25, 0x1, RZ ; UIADD3 UR6, UP0, UR6, 0x4, URZ ; ISETP.NE.AND P0, PT, R25, 0x6, PT ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD.WIDE.U32 R34, R28, R39, RZ ; IADD3 R37, P1, R34, R4, RZ ; IADD3.X R4, R35, UR4, RZ, P1, !PT ; STL [R0], R37 ; IADD3 R0, R0, 0x4, RZ ; @P0 BRA 0x2a50 ; LOP3.LUT P0, R38, R38, 0x1f, RZ, 0xc0, !PT ; STL [R1+0x18], R4 ; IADD3 R0, -R40.reuse, 0x4, RZ ; IADD3 R40, -R40, 0x6, RZ ; IMAD R40, R40, 0x4, R1 ; @P0 IMAD R37, R0, 0x4, R1 ; LDL R25, [R40+-0x4] ; @P0 LDL R28, [R37] ; LDL R0, [R40] ; @P0 IADD3 R35, -R38, 0x20, RZ ; LOP3.LUT P1, R22, R22, 0x80000000, RZ, 0xc0, !PT ; @P0 SHF.R.U32.HI R34, RZ, R35.reuse, R28 ; @P0 SHF.R.U32.HI R28, RZ, R35, R25 ; @P0 SHF.L.U32 R29, R0, R38.reuse, RZ ; @P0 SHF.L.U32 R35, R25, R38, RZ ; @P0 IMAD.IADD R0, R28, 0x1, R29 ; @P0 IMAD.IADD R25, R34, 0x1, R35 ; SHF.L.U32.HI R29, R25, 0x2, R0 ; SHF.R.U32.HI R37, RZ, 0x1f, R29 ; ISETP.NE.AND P0, PT, R37, RZ, PT ; IMAD.SHL.U32 R28, R25, 0x4, RZ ; @P0 LOP3.LUT R29, RZ, R29, RZ, 0x33, !PT ; @P0 LOP3.LUT R28, RZ, R28, RZ, 0x33, !PT ; I2F.F64.S64 R28, R28 ; DMUL R34, R28, c[0x2][0x28] ; LEA.HI R37, R0, R37, RZ, 0x2 ; F2F.F32.F64 R34, R34 ; @P0 LOP3.LUT R22, R22, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV R0, RZ, RZ, -R37 ; ISETP.NE.AND P0, PT, R22, RZ, PT ; @P1 IMAD.MOV.U32 R37, RZ, RZ, R0 ; FSEL R25, R34, -R34, !P0 ; BRA 0x2d50 ; FMUL R25, RZ, R22 ; IMAD.MOV.U32 R37, RZ, RZ, RZ ; BSYNC B0 ; IADD3 R37, R37, 0x1, RZ ; FMUL R35, R25, R25 ; IMAD.MOV.U32 R0, RZ, RZ, -0x46b2bead ; LOP3.LUT P1, RZ, R37, 0x1, RZ, 0xc0, !PT ; FMUL R33, R33, R2 ; LOP3.LUT P0, RZ, R37, 0x2, RZ, 0xc0, !PT ; FSEL R29, R27, 0.041666727513074874878, !P1 ; @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x37cbac00 ; @P1 FFMA R0, R35, R4, -0.0013887860113754868507 ; FSEL R4, R25, 1, !P1 ; FSEL R25, -R32, -0.4999999701976776123, !P1 ; FFMA R0, R35.reuse, R0, R29 ; FFMA R29, R4, R35, RZ ; FFMA R0, R35, R0, R25 ; FFMA R0, R0, R29, R4 ; @P0 FFMA R0, R0, -1, RZ ; IADD3 R22, P0, R5, c[0x0][0x1c0], RZ ; FMUL R25, R0, R3 ; FMUL R0, R23, R36 ; IADD3.X R23, R15, c[0x0][0x1c4], RZ, P0, !PT ; FMUL R25, R12, R25 ; FFMA R25, R14, R33, R25 ; FFMA R29, R25, -R0, R24 ; STG.E [R22.64], R29 ; LDG.E R35, [R20.64] ; LDG.E R28, [R8.64] ; LDG.E R37, [R18.64] ; IADD3 R24, P0, R5, c[0x0][0x1d8], RZ ; LDG.E R39, [R30.64] ; IADD3.X R25, R15, c[0x0][0x1dc], RZ, P0, !PT ; LDG.E R4, [R6.64] ; LDG.E R33, [R16.64] ; LDG.E R24, [R24.64] ; BSSY B0, 0x3470 ; FMUL R0, R35.reuse, 0.63661974668502807617 ; FSETP.GE.AND P0, PT, |R35|, 105615, PT ; F2I.NTZ R0, R0 ; FMUL R28, R28, R37 ; FMUL R28, R28, R39 ; FMUL R39, R39, R28 ; I2F R34, R0 ; FFMA R29, R34, -1.5707962512969970703, R35 ; FFMA R37, R34, -7.5497894158615963534e-08, R29 ; FMUL R29, R4, R33 ; FFMA R37, R34, -5.3903029534742383927e-15, R37 ; FMUL R33, R39, R36 ; FMUL R34, R29, R24 ; IMAD.MOV.U32 R36, RZ, RZ, R0 ; IMAD.MOV.U32 R4, RZ, RZ, R37 ; @!P0 BRA 0x3460 ; FSETP.NEU.AND P1, PT, |R35|, +INF , PT ; @!P1 BRA 0x3440 ; SHF.R.U32.HI R0, RZ, 0x17, R35 ; IMAD.SHL.U32 R24, R35, 0x100, RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R41, RZ, RZ, RZ ; LOP3.LUT R40, R24, 0x80000000, RZ, 0xfc, !PT ; ULDC.64 UR6, c[0x4][0x8] ; IADD3 R39, R0, -0x80, RZ ; IMAD.MOV.U32 R0, RZ, RZ, R1 ; SHF.R.U32.HI R38, RZ, 0x5, R39 ; IMAD.U32 R25, RZ, RZ, UR7 ; IMAD.U32 R24, RZ, RZ, UR6 ; LDG.E.CONSTANT R25, [R24.64] ; IADD3 R41, R41, 0x1, RZ ; UIADD3 UR6, UP0, UR6, 0x4, URZ ; ISETP.NE.AND P1, PT, R41, 0x6, PT ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD.WIDE.U32 R28, R25, R40, RZ ; IADD3 R43, P2, R28, R4, RZ ; IADD3.X R4, R29, UR4, RZ, P2, !PT ; STL [R0], R43 ; IADD3 R0, R0, 0x4, RZ ; @P1 BRA 0x3150 ; LOP3.LUT P1, R39, R39, 0x1f, RZ, 0xc0, !PT ; STL [R1+0x18], R4 ; IADD3 R0, -R38.reuse, 0x4, RZ ; IADD3 R38, -R38, 0x6, RZ ; IMAD R38, R38, 0x4, R1 ; @P1 IMAD R40, R0, 0x4, R1 ; LDL R25, [R38+-0x4] ; @P1 LDL R29, [R40] ; LDL R0, [R38] ; @P1 IADD3 R24, -R39, 0x20, RZ ; @P1 SHF.R.U32.HI R28, RZ, R24.reuse, R29 ; @P1 SHF.R.U32.HI R24, RZ, R24, R25 ; @P1 SHF.L.U32 R29, R0, R39.reuse, RZ ; @P1 SHF.L.U32 R39, R25, R39, RZ ; @P1 IMAD.IADD R0, R24, 0x1, R29 ; @P1 IMAD.IADD R25, R28, 0x1, R39 ; SHF.L.U32.HI R4, R25, 0x2, R0 ; SHF.R.U32.HI R39, RZ, 0x1f, R4 ; ISETP.NE.AND P1, PT, R39, RZ, PT ; IMAD.SHL.U32 R24, R25, 0x4, RZ ; @P1 LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; @P1 LOP3.LUT R24, RZ, R24, RZ, 0x33, !PT ; IMAD.MOV.U32 R25, RZ, RZ, R4 ; I2F.F64.S64 R24, R24 ; LOP3.LUT P2, R4, R35, 0x80000000, RZ, 0xc0, !PT ; DMUL R28, R24, c[0x2][0x28] ; @P1 LOP3.LUT R4, R4, 0x80000000, RZ, 0x3c, !PT ; LEA.HI R0, R0, R39, RZ, 0x2 ; F2F.F32.F64 R28, R28 ; ISETP.NE.AND P1, PT, R4, RZ, PT ; IMAD.MOV R4, RZ, RZ, -R0 ; @P2 IMAD.MOV.U32 R0, RZ, RZ, R4 ; FSEL R4, R28, -R28, !P1 ; BRA 0x3460 ; FMUL R4, RZ, R35 ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; BSYNC B0 ; IADD3 R28, R0, 0x1, RZ ; FMUL R39, R4, R4 ; BSSY B0, 0x3980 ; IMAD.MOV.U32 R0, RZ, RZ, -0x46b2bead ; LOP3.LUT P2, RZ, R28.reuse, 0x1, RZ, 0xc0, !PT ; LOP3.LUT P1, RZ, R28, 0x2, RZ, 0xc0, !PT ; FSEL R25, R27, 0.041666727513074874878, !P2 ; FSEL R4, R4, 1, !P2 ; FSEL R29, -R32, -0.4999999701976776123, !P2 ; @P2 IMAD.MOV.U32 R24, RZ, RZ, 0x37cbac00 ; @P2 FFMA R0, R39, R24, -0.0013887860113754868507 ; FFMA R0, R39.reuse, R0, R25 ; FFMA R25, R4, R39, RZ ; FFMA R0, R39, R0, R29 ; FFMA R25, R0, R25, R4 ; @P1 FFMA R25, R25, -1, RZ ; FMUL R0, R25, R2 ; FMUL R39, R13, R0 ; @!P0 BRA 0x3970 ; FSETP.NEU.AND P0, PT, |R35|, +INF , PT ; @!P0 BRA 0x3950 ; SHF.R.U32.HI R0, RZ, 0x17, R35 ; IMAD.SHL.U32 R24, R35, 0x100, RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R13, RZ, RZ, RZ ; LOP3.LUT R41, R24, 0x80000000, RZ, 0xfc, !PT ; ULDC.64 UR6, c[0x4][0x8] ; IADD3 R36, R0, -0x80, RZ ; IMAD.MOV.U32 R0, RZ, RZ, R1 ; SHF.R.U32.HI R38, RZ, 0x5, R36 ; IMAD.U32 R24, RZ, RZ, UR6 ; IMAD.U32 R25, RZ, RZ, UR7 ; LDG.E.CONSTANT R24, [R24.64] ; IADD3 R13, R13, 0x1, RZ ; UIADD3 UR6, UP0, UR6, 0x4, URZ ; ISETP.NE.AND P0, PT, R13, 0x6, PT ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD.WIDE.U32 R28, R24, R41, RZ ; IADD3 R37, P1, R28, R4, RZ ; IADD3.X R4, R29, UR4, RZ, P1, !PT ; STL [R0], R37 ; IADD3 R0, R0, 0x4, RZ ; @P0 BRA 0x3670 ; LOP3.LUT P0, R36, R36, 0x1f, RZ, 0xc0, !PT ; STL [R1+0x18], R4 ; IADD3 R0, -R38.reuse, 0x4, RZ ; IADD3 R38, -R38, 0x6, RZ ; IMAD R38, R38, 0x4, R1 ; @P0 IMAD R37, R0, 0x4, R1 ; LDL R13, [R38+-0x4] ; @P0 LDL R24, [R37] ; LDL R0, [R38] ; @P0 IADD3 R29, -R36, 0x20, RZ ; LOP3.LUT P1, R35, R35, 0x80000000, RZ, 0xc0, !PT ; @P0 SHF.R.U32.HI R28, RZ, R29.reuse, R24 ; @P0 SHF.R.U32.HI R24, RZ, R29, R13 ; @P0 SHF.L.U32 R25, R0, R36.reuse, RZ ; @P0 SHF.L.U32 R29, R13, R36, RZ ; @P0 IMAD.IADD R0, R24, 0x1, R25 ; @P0 IMAD.IADD R13, R28, 0x1, R29 ; SHF.L.U32.HI R25, R13, 0x2, R0 ; SHF.R.U32.HI R37, RZ, 0x1f, R25 ; ISETP.NE.AND P0, PT, R37, RZ, PT ; IMAD.SHL.U32 R24, R13, 0x4, RZ ; @P0 LOP3.LUT R25, RZ, R25, RZ, 0x33, !PT ; @P0 LOP3.LUT R24, RZ, R24, RZ, 0x33, !PT ; I2F.F64.S64 R24, R24 ; DMUL R28, R24, c[0x2][0x28] ; LEA.HI R36, R0, R37, RZ, 0x2 ; F2F.F32.F64 R28, R28 ; @P0 LOP3.LUT R35, R35, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV R0, RZ, RZ, -R36 ; ISETP.NE.AND P0, PT, R35, RZ, PT ; @P1 IMAD.MOV.U32 R36, RZ, RZ, R0 ; FSEL R37, R28, -R28, !P0 ; BRA 0x3970 ; FMUL R37, RZ, R35 ; IMAD.MOV.U32 R36, RZ, RZ, RZ ; BSYNC B0 ; LOP3.LUT P1, RZ, R36.reuse, 0x1, RZ, 0xc0, !PT ; FMUL R4, R37, R37 ; LOP3.LUT P0, RZ, R36, 0x2, RZ, 0xc0, !PT ; IMAD.MOV.U32 R0, RZ, RZ, -0x46b2bead ; FSEL R13, R27, 0.041666727513074874878, !P1 ; FSEL R37, R37, 1, !P1 ; @P1 IMAD.MOV.U32 R25, RZ, RZ, 0x37cbac00 ; @P1 FFMA R0, R4, R25, -0.0013887860113754868507 ; FSEL R25, -R32, -0.4999999701976776123, !P1 ; FFMA R0, R4.reuse, R0, R13 ; FFMA R13, R37, R4, RZ ; FFMA R0, R4, R0, R25 ; FFMA R0, R0, R13, R37 ; @P0 FFMA R0, R0, -1, RZ ; IADD3 R24, P0, R5, c[0x0][0x1d0], RZ ; FMUL R0, R0, R3 ; IADD3.X R25, R15, c[0x0][0x1d4], RZ, P0, !PT ; FFMA R0, -R26, R0, R39 ; FFMA R33, -R33, R0, R34 ; STG.E [R24.64], R33 ; LDG.E R20, [R20.64] ; IADD3 R28, P0, R5, c[0x0][0x1e8], RZ ; LDG.E R8, [R8.64] ; IADD3.X R29, R15, c[0x0][0x1ec], RZ, P0, !PT ; LDG.E R19, [R18.64] ; LDG.E R6, [R6.64] ; LDG.E R17, [R16.64] ; LDG.E R31, [R30.64] ; LDG.E R29, [R28.64] ; BSSY B0, 0x4030 ; FMUL R0, R20.reuse, 0.63661974668502807617 ; FSETP.GE.AND P0, PT, |R20|, 105615, PT ; F2I.NTZ R0, R0 ; FMUL R8, R8, R19 ; FMUL R6, R6, R17 ; FMUL R8, R8, R31 ; I2F R13, R0 ; IMAD.MOV.U32 R19, RZ, RZ, R0 ; FMUL R16, R31, R8 ; FMUL R17, R6, R29 ; FFMA R4, R13, -1.5707962512969970703, R20 ; FFMA R4, R13, -7.5497894158615963534e-08, R4 ; FFMA R18, R13, -5.3903029534742383927e-15, R4 ; IMAD.MOV.U32 R4, RZ, RZ, R18 ; @!P0 BRA 0x4020 ; FSETP.NEU.AND P1, PT, |R20|, +INF , PT ; @!P1 BRA 0x4000 ; SHF.R.U32.HI R0, RZ, 0x17, R20 ; IMAD.SHL.U32 R6, R20, 0x100, RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R21, RZ, RZ, RZ ; LOP3.LUT R9, R6, 0x80000000, RZ, 0xfc, !PT ; ULDC.64 UR6, c[0x4][0x8] ; IADD3 R4, R0, -0x80, RZ ; IMAD.MOV.U32 R0, RZ, RZ, R1 ; SHF.R.U32.HI R13, RZ, 0x5, R4 ; IMAD.U32 R6, RZ, RZ, UR6 ; IMAD.U32 R7, RZ, RZ, UR7 ; LDG.E.CONSTANT R6, [R6.64] ; IADD3 R21, R21, 0x1, RZ ; UIADD3 UR6, UP0, UR6, 0x4, URZ ; ISETP.NE.AND P1, PT, R21, 0x6, PT ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD.WIDE.U32 R28, R6, R9, RZ ; IADD3 R31, P2, R28, R8, RZ ; IADD3.X R8, R29, UR4, RZ, P2, !PT ; STL [R0], R31 ; IADD3 R0, R0, 0x4, RZ ; @P1 BRA 0x3d20 ; LOP3.LUT P1, R26, R4, 0x1f, RZ, 0xc0, !PT ; STL [R1+0x18], R8 ; IADD3 R0, -R13.reuse, 0x4, RZ ; IADD3 R4, -R13, 0x6, RZ ; IMAD R21, R4, 0x4, R1 ; @P1 IMAD R28, R0, 0x4, R1 ; LDL R7, [R21+-0x4] ; @P1 LDL R9, [R28] ; LDL R0, [R21] ; @P1 IADD3 R4, -R26, 0x20, RZ ; @P1 SHF.L.U32 R13, R7, R26, RZ ; @P1 SHF.R.U32.HI R6, RZ, R4.reuse, R9 ; @P1 SHF.R.U32.HI R4, RZ, R4, R7 ; @P1 SHF.L.U32 R9, R0, R26, RZ ; @P1 IMAD.IADD R7, R6, 0x1, R13 ; @P1 IMAD.IADD R0, R4, 0x1, R9 ; SHF.L.U32.HI R9, R7, 0x2, R0 ; SHF.R.U32.HI R13, RZ, 0x1f, R9 ; ISETP.NE.AND P1, PT, R13, RZ, PT ; IMAD.SHL.U32 R8, R7, 0x4, RZ ; @P1 LOP3.LUT R9, RZ, R9, RZ, 0x33, !PT ; @P1 LOP3.LUT R8, RZ, R8, RZ, 0x33, !PT ; I2F.F64.S64 R6, R8 ; LOP3.LUT P2, R4, R20, 0x80000000, RZ, 0xc0, !PT ; DMUL R6, R6, c[0x2][0x28] ; @P1 LOP3.LUT R4, R4, 0x80000000, RZ, 0x3c, !PT ; LEA.HI R0, R0, R13, RZ, 0x2 ; F2F.F32.F64 R6, R6 ; ISETP.NE.AND P1, PT, R4, RZ, PT ; IMAD.MOV R4, RZ, RZ, -R0 ; @P2 IMAD.MOV.U32 R0, RZ, RZ, R4 ; FSEL R4, R6, -R6, !P1 ; BRA 0x4020 ; FMUL R4, RZ, R20 ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; BSYNC B0 ; LOP3.LUT P2, RZ, R0, 0x1, RZ, 0xc0, !PT ; FMUL R13, R4, R4 ; LOP3.LUT P1, RZ, R0, 0x2, RZ, 0xc0, !PT ; IMAD.MOV.U32 R6, RZ, RZ, -0x46b2bead ; FSEL R7, R27, 0.041666727513074874878, !P2 ; BSSY B0, 0x4530 ; FSEL R0, R4, 1, !P2 ; FSEL R9, -R32, -0.4999999701976776123, !P2 ; @P2 IMAD.MOV.U32 R8, RZ, RZ, 0x37cbac00 ; @P2 FFMA R6, R13, R8, -0.0013887860113754868507 ; FFMA R6, R13.reuse, R6, R7 ; FFMA R7, R0, R13, RZ ; FFMA R6, R13, R6, R9 ; FFMA R7, R6, R7, R0 ; @P1 FFMA R7, R7, -1, RZ ; FMUL R21, R7, R2 ; FMUL R21, R14, R21 ; @!P0 BRA 0x4520 ; FSETP.NEU.AND P0, PT, |R20|, +INF , PT ; @!P0 BRA 0x4500 ; SHF.R.U32.HI R0, RZ, 0x17, R20 ; IMAD.SHL.U32 R7, R20, 0x100, RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; LOP3.LUT R13, R7, 0x80000000, RZ, 0xfc, !PT ; ULDC.64 UR6, c[0x4][0x8] ; IADD3 R4, R0, -0x80, RZ ; IMAD.MOV.U32 R0, RZ, RZ, R1 ; SHF.R.U32.HI R14, RZ, 0x5, R4 ; IMAD.U32 R18, RZ, RZ, UR6 ; IMAD.U32 R19, RZ, RZ, UR7 ; LDG.E.CONSTANT R8, [R18.64] ; IADD3 R2, R2, 0x1, RZ ; UIADD3 UR6, UP0, UR6, 0x4, URZ ; ISETP.NE.AND P0, PT, R2, 0x6, PT ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD.WIDE.U32 R8, R8, R13, RZ ; IADD3 R7, P1, R8, R6, RZ ; IADD3.X R6, R9, UR4, RZ, P1, !PT ; STL [R0], R7 ; IADD3 R0, R0, 0x4, RZ ; @P0 BRA 0x4220 ; LOP3.LUT P0, R13, R4, 0x1f, RZ, 0xc0, !PT ; STL [R1+0x18], R6 ; IADD3 R0, -R14.reuse, 0x4, RZ ; IADD3 R14, -R14, 0x6, RZ ; IMAD R14, R14, 0x4, R1 ; @P0 IMAD R18, R0, 0x4, R1 ; LDL R7, [R14+-0x4] ; @P0 LDL R2, [R18] ; LDL R0, [R14] ; @P0 IADD3 R8, -R13, 0x20, RZ ; LOP3.LUT P1, R20, R20, 0x80000000, RZ, 0xc0, !PT ; @P0 SHF.R.U32.HI R4, RZ, R8.reuse, R2 ; @P0 SHF.R.U32.HI R2, RZ, R8, R7 ; @P0 SHF.L.U32 R9, R0, R13.reuse, RZ ; @P0 SHF.L.U32 R13, R7, R13, RZ ; @P0 IMAD.IADD R0, R2, 0x1, R9 ; @P0 IMAD.IADD R7, R4, 0x1, R13 ; SHF.L.U32.HI R9, R7, 0x2, R0 ; SHF.R.U32.HI R19, RZ, 0x1f, R9 ; ISETP.NE.AND P0, PT, R19, RZ, PT ; IMAD.SHL.U32 R8, R7, 0x4, RZ ; @P0 LOP3.LUT R9, RZ, R9, RZ, 0x33, !PT ; @P0 LOP3.LUT R8, RZ, R8, RZ, 0x33, !PT ; I2F.F64.S64 R6, R8 ; DMUL R6, R6, c[0x2][0x28] ; LEA.HI R19, R0, R19, RZ, 0x2 ; F2F.F32.F64 R6, R6 ; @P0 LOP3.LUT R20, R20, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV R0, RZ, RZ, -R19 ; ISETP.NE.AND P0, PT, R20, RZ, PT ; @P1 IMAD.MOV.U32 R19, RZ, RZ, R0 ; FSEL R18, R6, -R6, !P0 ; BRA 0x4520 ; FMUL R18, RZ, R20 ; IMAD.MOV.U32 R19, RZ, RZ, RZ ; BSYNC B0 ; IADD3 R19, R19, 0x1, RZ ; FMUL R13, R18, R18 ; IMAD.MOV.U32 R0, RZ, RZ, -0x46b2bead ; LOP3.LUT P1, RZ, R19.reuse, 0x1, RZ, 0xc0, !PT ; LOP3.LUT P0, RZ, R19, 0x2, RZ, 0xc0, !PT ; FSEL R27, R27, 0.041666727513074874878, !P1 ; FSEL R18, R18, 1, !P1 ; FSEL R7, -R32, -0.4999999701976776123, !P1 ; FFMA R9, R18, R13, RZ ; @P1 IMAD.MOV.U32 R2, RZ, RZ, 0x37cbac00 ; @P1 FFMA R0, R13, R2, -0.0013887860113754868507 ; FFMA R0, R13, R0, R27 ; FFMA R0, R13, R0, R7 ; FFMA R0, R0, R9, R18 ; @P0 FFMA R0, R0, -1, RZ ; IADD3 R2, P0, R5, c[0x0][0x1e0], RZ ; FMUL R0, R0, R3 ; IADD3.X R3, R15, c[0x0][0x1e4], RZ, P0, !PT ; FFMA R0, R12, R0, R21 ; FFMA R17, -R16, R0, R17 ; STG.E [R2.64], R17 ; LDG.E R22, [R22.64] ; LDG.E R11, [R10.64] ; IADD3 R6, P0, R5, c[0x0][0x190], RZ ; IADD3.X R7, R15, c[0x0][0x194], RZ, P0, !PT ; FADD R9, R22, R11 ; STG.E [R6.64], R9 ; LDG.E R0, [R2.64] ; LDG.E R25, [R24.64] ; IADD3 R4, P0, R5, c[0x0][0x198], RZ ; IADD3.X R5, R15, c[0x0][0x19c], RZ, P0, !PT ; FADD R13, R0, R25 ; STG.E [R4.64], R13 ; EXIT ; IMAD.MOV.U32 R5, RZ, RZ, 0x3ff60000 ; BSSY B2, 0x4c30 ; IMAD.MOV.U32 R9, RZ, RZ, R15 ; MUFU.RCP64H R13, R5 ; IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R8, RZ, RZ, R14 ; LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R7, RZ, RZ, 0x1ca00000 ; IMAD.MOV.U32 R26, RZ, RZ, 0x40400000 ; ISETP.GE.U32.AND P0, PT, R17, 0x40400000, PT ; SEL R7, R7, 0x63400000, !P0 ; DFMA R14, R12, -R4, 1 ; IADD3 R28, R26, -0x1, RZ ; @!P1 LOP3.LUT R11, R7, 0x80000000, R9, 0xf8, !PT ; DFMA R14, R14, R14, R14 ; DFMA R22, R12, R14, R12 ; LOP3.LUT R13, R7, 0x800fffff, R9, 0xf8, !PT ; IMAD.MOV.U32 R12, RZ, RZ, R8 ; @!P1 LOP3.LUT R15, R11, 0x100000, RZ, 0xfc, !PT ; @!P1 IMAD.MOV.U32 R14, RZ, RZ, RZ ; DFMA R24, R22, -R4, 1 ; IMAD.MOV.U32 R11, RZ, RZ, R17 ; @!P1 DFMA R12, R12, 2, -R14 ; DFMA R24, R22, R24, R22 ; @!P1 LOP3.LUT R11, R13, 0x7ff00000, RZ, 0xc0, !PT ; DMUL R14, R24, R12 ; IADD3 R27, R11, -0x1, RZ ; DFMA R22, R14, -R4, R12 ; ISETP.GT.U32.AND P0, PT, R27, 0x7feffffe, PT ; ISETP.GT.U32.OR P0, PT, R28, 0x7feffffe, P0 ; DFMA R14, R24, R22, R14 ; @P0 BRA 0x4b10 ; IADD3 R8, R17, -0x40400000, RZ ; IMNMX R8, R8, -0x46a00000, !PT ; IMNMX R8, R8, 0x46a00000, PT ; IMAD.IADD R11, R8, 0x1, -R7 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; IADD3 R9, R11, 0x7fe00000, RZ ; DMUL R22, R14, R8 ; FSETP.GTU.AND P0, PT, |R23|, 1.469367938527859385e-39, PT ; @P0 BRA 0x4c20 ; DFMA R4, R14, -R4, R12 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; LOP3.LUT R4, R5, 0x40460000, RZ, 0x3c, !PT ; LOP3.LUT R7, R4, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R9, R7, R9, RZ, 0xfc, !PT ; @!P0 BRA 0x4c20 ; IMAD.MOV R5, RZ, RZ, -R11 ; DMUL.RP R8, R14, R8 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; DFMA R4, R22, -R4, R14 ; LOP3.LUT R7, R9, R7, RZ, 0x3c, !PT ; IADD3 R4, -R11, -0x43300000, RZ ; FSETP.NEU.AND P0, PT, |R5|, R4, PT ; FSEL R22, R8, R22, !P0 ; FSEL R23, R7, R23, !P0 ; BRA 0x4c20 ; DSETP.NAN.AND P0, PT, R8, R8, PT ; @P0 BRA 0x4c00 ; ISETP.NE.AND P0, PT, R11, R26, PT ; IMAD.MOV.U32 R22, RZ, RZ, 0x0 ; IMAD.MOV.U32 R23, RZ, RZ, -0x80000 ; @!P0 BRA 0x4c20 ; ISETP.NE.AND P0, PT, R11, 0x7ff00000, PT ; LOP3.LUT R8, R9, 0x40460000, RZ, 0x3c, !PT ; ISETP.EQ.OR P0, PT, R26, RZ, !P0 ; LOP3.LUT R23, R8, 0x80000000, RZ, 0xc0, !PT ; @P0 LOP3.LUT R4, R23, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R22, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R22, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R23, RZ, RZ, R4 ; BRA 0x4c20 ; LOP3.LUT R23, R9, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R22, RZ, RZ, R8 ; BSYNC B2 ; IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, R22 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; RET.REL.NODEC R10 0x0 ; LOP3.LUT P1, RZ, R34, 0x7fffffff, RZ, 0xc0, !PT ; @!P1 IMAD.MOV.U32 R29, RZ, RZ, R34 ; @!P1 BRA 0x4da0 ; FSETP.GEU.FTZ.AND P1, PT, R34, RZ, PT ; @!P1 IMAD.MOV.U32 R29, RZ, RZ, 0x7fffffff ; @!P1 BRA 0x4da0 ; FSETP.GTU.FTZ.AND P1, PT, |R34|, +INF , PT ; @P1 FADD.FTZ R29, R34, 1 ; @P1 BRA 0x4da0 ; FSETP.NEU.FTZ.AND P1, PT, |R34|, +INF , PT ; @P1 FFMA R32, R34, 1.84467440737095516160e+19, RZ ; @P1 MUFU.RSQ R29, R32 ; @P1 FMUL.FTZ R27, R32, R29 ; @P1 FMUL.FTZ R35, R29, 0.5 ; @P1 FADD.FTZ R33, -R27.reuse, -RZ ; @!P1 IMAD.MOV.U32 R29, RZ, RZ, R34 ; @P1 FFMA R36, R27, R33, R32 ; @P1 FFMA R35, R36, R35, R27 ; @P1 FMUL.FTZ R29, R35, 2.3283064365386962891e-10 ; IMAD.MOV.U32 R36, RZ, RZ, R29 ; IMAD.MOV.U32 R29, RZ, RZ, 0x0 ; RET.REL.NODEC R28 0x0 ; SHF.R.U32.HI R5, RZ, 0x17, R8 ; SHF.R.U32.HI R3, RZ, 0x17, R9.reuse ; LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; IADD3 R12, R11, -0x1, RZ ; IADD3 R10, R3, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; @!P0 BRA 0x4ff0 ; FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; FSETP.GTU.FTZ.AND P1, PT, |R8|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0x53d0 ; LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ; @!P0 BRA 0x53b0 ; FSETP.NEU.FTZ.AND P0, PT, |R9|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P2, PT, |R8|, +INF , PT ; FSETP.NEU.FTZ.AND P1, PT, |R9|, +INF , PT ; @!P2 BRA !P0, 0x53b0 ; LOP3.LUT P0, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P2, P0, PT, 0x2a, 0x0 ; @P0 BRA 0x5390 ; LOP3.LUT P0, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P1, P0, PT, 0x2a, 0x0 ; @P0 BRA 0x5360 ; ISETP.GE.AND P0, PT, R10, RZ, PT ; ISETP.GE.AND P1, PT, R12, RZ, PT ; @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; @!P0 FFMA R5, R9, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R8, R8, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R7, R7, 0x40, RZ ; LEA R9, R11, 0xc0800000, 0x17 ; IMAD.IADD R9, R8, 0x1, -R9 ; IADD3 R8, R3, -0x7f, RZ ; MUFU.RCP R10, R9 ; FADD.FTZ R12, -R9, -RZ ; IMAD R5, R8.reuse, -0x800000, R5 ; IADD3 R8, R8, 0x7f, -R11 ; IMAD.IADD R8, R8, 0x1, R7 ; FFMA R3, R10, R12, 1 ; FFMA R14, R10, R3, R10 ; FFMA R3, R5, R14, RZ ; FFMA R10, R12, R3, R5 ; FFMA R13, R14, R10, R3 ; FFMA R12, R12, R13, R5 ; FFMA R5, R14, R12, R13 ; SHF.R.U32.HI R3, RZ, 0x17, R5 ; LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; IMAD.IADD R9, R3, 0x1, R8 ; IADD3 R3, R9, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; @!P0 BRA 0x5340 ; ISETP.GT.AND P0, PT, R9, 0xfe, PT ; @P0 BRA 0x5310 ; ISETP.GE.AND P0, PT, R9, 0x1, PT ; @P0 BRA 0x53e0 ; ISETP.GE.AND P0, PT, R9, -0x18, PT ; LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0x53e0 ; FFMA.RZ R3, R14.reuse, R12.reuse, R13.reuse ; IADD3 R10, R9.reuse, 0x20, RZ ; FFMA.RM R8, R14.reuse, R12.reuse, R13.reuse ; ISETP.NE.AND P2, PT, R9, RZ, PT ; LOP3.LUT R7, R3, 0x7fffff, RZ, 0xc0, !PT ; FFMA.RP R3, R14, R12, R13 ; ISETP.NE.AND P1, PT, R9, RZ, PT ; IMAD.MOV R9, RZ, RZ, -R9 ; LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; FSETP.NEU.FTZ.AND P0, PT, R3, R8, PT ; SHF.L.U32 R10, R7, R10, RZ ; SEL R8, R9, RZ, P2 ; ISETP.NE.AND P1, PT, R10, RZ, P1 ; SHF.R.U32.HI R8, RZ, R8, R7 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R10, RZ, 0x1, R8 ; SEL R3, RZ, 0x1, !P0 ; LOP3.LUT R3, R3, 0x1, R10, 0xf8, !PT ; LOP3.LUT R3, R3, R8, RZ, 0xc0, !PT ; IMAD.IADD R10, R10, 0x1, R3 ; LOP3.LUT R5, R10, R5, RZ, 0xfc, !PT ; BRA 0x53e0 ; LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x53e0 ; IMAD R5, R8, 0x800000, R5 ; BRA 0x53e0 ; LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x53e0 ; LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; BRA 0x53e0 ; MUFU.RSQ R5, -QNAN ; BRA 0x53e0 ; FADD.FTZ R5, R9, R8 ; IMAD.MOV.U32 R3, RZ, RZ, R5 ; IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; RET.REL.NODEC R4 0x0 ; SHF.R.U32.HI R4, RZ, 0x14, R17 ; IMAD.MOV.U32 R31, RZ, RZ, R5 ; IMAD.MOV.U32 R5, RZ, RZ, R17 ; LOP3.LUT R4, R4, 0x7ff, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R4, 0x7ff, PT ; @!P0 BRA 0x5d80 ; IADD3 R25, R4, -0x400, RZ ; BSSY B4, 0x57a0 ; IADD3 R10, R1, 0x20, RZ ; CS2R R26, SRZ ; SHF.R.U32.HI R9, RZ, 0x6, R25 ; LOP3.LUT P4, R25, R25, 0x3f, RZ, 0xc0, !PT ; IADD3 R4, -R9.reuse, 0x10, RZ ; IADD3 R7, -R9, 0x13, RZ ; ISETP.GT.AND P0, PT, R4, 0xe, PT ; IADD3 R9, -R9, 0xf, RZ ; SEL R7, R7, 0x12, !P0 ; IMAD.MOV.U32 R12, RZ, RZ, R9 ; ISETP.GT.AND P0, PT, R4, R7, PT ; @P0 BRA 0x5790 ; IMAD.MOV.U32 R12, RZ, RZ, 0x8 ; SHF.L.U64.HI R29, R31.reuse, 0xb, R5 ; IMAD.SHL.U32 R31, R31, 0x800, RZ ; CS2R R26, SRZ ; IMAD.WIDE R12, R9, R12, c[0x4][0x18] ; LOP3.LUT R29, R29, 0x80000000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R8, RZ, RZ, R12 ; IMAD.MOV.U32 R11, RZ, RZ, R10 ; IMAD.MOV.U32 R12, RZ, RZ, R9 ; IMAD.MOV.U32 R4, RZ, RZ, R8 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R5, RZ, RZ, R13 ; LDG.E.64.CONSTANT R4, [R4.64] ; IADD3 R12, R12, 0x1, RZ ; IMAD.WIDE.U32 R26, P5, R4, R31, R26 ; IMAD R33, R4.reuse, R29.reuse, RZ ; IMAD.HI.U32 R14, R4, R29, RZ ; IADD3 R27, P0, R33, R27, RZ ; IMAD R28, R5.reuse, R31.reuse, RZ ; IMAD.HI.U32 R33, R5, R31, RZ ; IADD3 R27, P1, R28, R27, RZ ; IMAD.X R14, RZ, RZ, R14, P5 ; ISETP.GE.AND P5, PT, R12, R7, PT ; IMAD.HI.U32 R4, R5, R29.reuse, RZ ; STL.64 [R11], R26 ; IADD3.X R14, P0, R33, R14, RZ, P0, !PT ; IMAD R5, R5, R29, RZ ; IMAD.X R4, RZ, RZ, R4, P0 ; IADD3.X R14, P1, R5, R14, RZ, P1, !PT ; IADD3 R8, P0, R8, 0x8, RZ ; IMAD.X R5, RZ, RZ, R4, P1 ; IADD3 R11, R11, 0x8, RZ ; IMAD.X R13, RZ, RZ, R13, P0 ; IMAD.MOV.U32 R26, RZ, RZ, R14 ; IMAD.MOV.U32 R27, RZ, RZ, R5 ; @!P5 BRA 0x55e0 ; BSYNC B4 ; IMAD.IADD R9, R12, 0x1, -R9 ; IMAD R29, R9, 0x8, R10 ; STL.64 [R29], R26 ; LDL.64 R4, [R1+0x30] ; @P4 LDL.64 R12, [R1+0x28] ; LDL.64 R8, [R1+0x38] ; @P4 IADD3 R10, -R25, 0x40, RZ ; UMOV UR4, URZ ; @P4 SHF.L.U32 R14, R4, R25, RZ ; @P4 SHF.L.U64.HI R11, R4, R25.reuse, R5 ; @P4 SHF.R.U64 R7, R12, R10.reuse, R13.reuse ; @P4 SHF.R.U32.HI R12, RZ, R10.reuse, R13 ; @P4 SHF.R.U64 R13, R4, R10, R5 ; @P4 LOP3.LUT R4, R7, R14, RZ, 0xfc, !PT ; @P4 SHF.L.U32 R14, R8, R25, RZ ; @P4 SHF.L.U64.HI R25, R8, R25, R9 ; @P4 SHF.R.U32.HI R10, RZ, R10, R5 ; @P4 LOP3.LUT R8, R14, R13, RZ, 0xfc, !PT ; IMAD.SHL.U32 R14, R4, 0x4, RZ ; @P4 LOP3.LUT R5, R12, R11, RZ, 0xfc, !PT ; @P4 LOP3.LUT R9, R25, R10, RZ, 0xfc, !PT ; IMAD.SHL.U32 R27, R8, 0x4, RZ ; SHF.L.U64.HI R13, R4, 0x2, R5 ; SHF.R.U32.HI R12, RZ, 0x1e, R5 ; IADD3 RZ, P0, RZ, -R14, RZ ; LOP3.LUT R4, RZ, R13, RZ, 0x33, !PT ; LOP3.LUT R27, R12, R27, RZ, 0xfc, !PT ; SHF.L.U64.HI R10, R8, 0x2, R9 ; IADD3.X R8, P0, RZ, R4, RZ, P0, !PT ; LOP3.LUT R4, RZ, R27, RZ, 0x33, !PT ; LOP3.LUT R7, RZ, R10, RZ, 0x33, !PT ; IADD3.X R4, P0, RZ, R4, RZ, P0, !PT ; SHF.R.U32.HI R5, RZ, 0x1d, R9 ; IMAD.X R7, RZ, RZ, R7, P0 ; LOP3.LUT P1, RZ, R5, 0x1, RZ, 0xc0, !PT ; SEL R7, R10, R7, !P1 ; SEL R27, R27, R4, !P1 ; ISETP.NE.U32.AND P0, PT, R7, RZ, PT ; SEL R12, R13, R8, !P1 ; SEL R10, R27, R7, !P0 ; @P1 IMAD.MOV R14, RZ, RZ, -R14 ; FLO.U32 R10, R10 ; IADD3 R11, -R10.reuse, 0x1f, RZ ; IADD3 R4, -R10, 0x3f, RZ ; @P0 IMAD.MOV R4, RZ, RZ, R11 ; ISETP.NE.U32.AND P0, PT, R4.reuse, RZ, PT ; IADD3 R11, -R4, 0x40, RZ ; ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; SHF.L.U32 R13, R27.reuse, R4.reuse, RZ ; SHF.R.U64 R8, R14, R11, R12 ; SHF.L.U64.HI R25, R27, R4, R7 ; @P0 LOP3.LUT R27, R8, R13, RZ, 0xfc, !PT ; SHF.R.U32.HI R8, RZ, R11, R12 ; IMAD.MOV.U32 R11, RZ, RZ, RZ ; IMAD.WIDE.U32 R12, R27, 0x2168c235, RZ ; @P0 LOP3.LUT R7, R8, R25, RZ, 0xfc, !PT ; IMAD.MOV.U32 R10, RZ, RZ, R13 ; IADD3 RZ, P0, R12, R12, RZ ; IMAD.HI.U32 R8, R7, -0x36f0255e, RZ ; IMAD.WIDE.U32 R10, R27, -0x36f0255e, R10 ; IMAD R13, R7.reuse, -0x36f0255e, RZ ; IMAD.WIDE.U32 R10, P4, R7, 0x2168c235, R10 ; IMAD.X R7, RZ, RZ, R8, P4 ; IADD3 R8, P4, R13, R11, RZ ; IADD3.X RZ, P0, R10, R10, RZ, P0, !PT ; ISETP.GT.U32.AND P5, PT, R8.reuse, RZ, PT ; IMAD.X R7, RZ, RZ, R7, P4 ; IADD3.X R11, P4, R8, R8, RZ, P0, !PT ; ISETP.GT.AND.EX P0, PT, R7.reuse, RZ, PT, P5 ; IMAD.X R10, R7, 0x1, R7, P4 ; LOP3.LUT P4, RZ, R17, 0x80000000, RZ, 0xc0, !PT ; SEL R11, R11, R8, P0 ; LOP3.LUT R8, R5, 0x1, RZ, 0xc0, !PT ; SEL R10, R10, R7, P0 ; IADD3 R5, P5, R11, 0x1, RZ ; LEA.HI R8, R9, R8, RZ, 0x2 ; IADD3 R9, R15, -c[0x0][0x20], RZ ; IMAD.X R10, RZ, RZ, R10, P5 ; IMAD.MOV R7, RZ, RZ, -R8 ; SHF.R.U64 R5, R5, 0xa, R10 ; @P4 IMAD.MOV.U32 R8, RZ, RZ, R7 ; SEL R7, RZ, 0x1, !P0 ; IADD3 R5, P4, R5, 0x1, RZ ; STL [R9], R8 ; IMAD.IADD R12, R7, 0x1, R4 ; LEA.HI.X R10, R10, RZ, RZ, 0x16, P4 ; LOP3.LUT R4, R17, 0x80000000, RZ, 0xc0, !PT ; IMAD.SHL.U32 R12, R12, 0x100000, RZ ; SHF.R.U64 R5, R5, 0x1, R10 ; SHF.R.U32.HI R7, RZ, 0x1, R10 ; IADD3 R31, P0, P4, R5, -UR4, RZ ; @P1 LOP3.LUT R4, R4, 0x80000000, RZ, 0x3c, !PT ; IADD3.X R5, R7, 0x3fe00000, ~R12, P0, P4 ; LOP3.LUT R5, R5, R4, RZ, 0xfc, !PT ; IMAD.MOV.U32 R25, RZ, RZ, 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, R31 ; RET.REL.NODEC R24 0x0 ; BRA 0x5db0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IABS R7, c[0x0][0x16c] ; S2R R5, SR_CTAID.X ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; IADD3 R1, R1, -0x20, RZ ; I2F.RP R0, R7 ; S2R R4, SR_TID.X ; MUFU.RCP R0, R0 ; IMAD R5, R5, c[0x0][0x0], R4 ; IADD3 R2, R0, 0xffffffe, RZ ; IABS R0, R5 ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.MOV R6, RZ, RZ, -R3 ; IMAD R9, R6, R7, RZ ; IMAD.HI.U32 R3, R3, R9, R2 ; MUFU.RCP R2, c[0x0][0x178] ; IMAD.HI.U32 R4, R3, R0, RZ ; IMAD.MOV R3, RZ, RZ, -R4 ; IMAD R0, R7, R3, R0 ; ISETP.GT.U32.AND P0, PT, R7, R0, PT ; @!P0 IMAD.IADD R0, R0, 0x1, -R7 ; @!P0 IADD3 R4, R4, 0x1, RZ ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x16c], PT ; ISETP.GE.U32.AND P1, PT, R0, R7, PT ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x178] ; LOP3.LUT R0, R5, c[0x0][0x16c], RZ, 0x3c, !PT ; FFMA R3, R2, -R7, 1 ; ISETP.GE.AND P2, PT, R0, RZ, PT ; FFMA R3, R2, R3, R2 ; @P1 IADD3 R4, R4, 0x1, RZ ; FCHK P1, R11, c[0x0][0x178] ; FFMA R0, R3, c[0x0][0x174], RZ ; @!P2 IADD3 R4, -R4, RZ, RZ ; FFMA R2, R0, -R7, c[0x0][0x174] ; @!P0 LOP3.LUT R4, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; FFMA R3, R3, R2, R0 ; IMAD.MOV R6, RZ, RZ, -R4 ; IMAD R2, R6, c[0x0][0x16c], R5 ; @!P1 BRA 0x2c0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; MOV R0, 0x2b0 ; CALL.REL.NOINC 0x21d0 ; IMAD.MOV.U32 R3, RZ, RZ, R8 ; MUFU.RCP R0, c[0x0][0x17c] ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; FCHK P0, R11, c[0x0][0x17c] ; FFMA R7, R0, -R6, 1 ; FFMA R0, R0, R7, R0 ; FFMA R7, R0, c[0x0][0x174], RZ ; FFMA R6, R7, -R6, c[0x0][0x174] ; FFMA R0, R0, R6, R7 ; @!P0 BRA 0x3a0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x17c] ; MOV R0, 0x390 ; CALL.REL.NOINC 0x21d0 ; MOV R0, R8 ; IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x16c] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ; IMAD R6, R23, R8, -0x4 ; ISETP.GE.AND P0, PT, R5, R6, PT ; ISETP.LT.OR P0, PT, R5, 0x4, P0 ; @P0 EXIT ; IADD3 R7, R8, -0x4, RZ ; ISETP.GE.AND P0, PT, R4.reuse, R7, PT ; IADD3 R7, R23, -0x4, RZ ; ISETP.LT.OR P0, PT, R4, 0x4, P0 ; ISETP.LT.OR P0, PT, R2, 0x4, P0 ; ISETP.GE.OR P0, PT, R2, R7, P0 ; @P0 EXIT ; IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; ULDC.64 UR6, c[0x0][0x118] ; IMAD.WIDE R24, R5, R6, c[0x0][0x1a0] ; LDG.E R33, [R24.64+-0x4] ; LDG.E R36, [R24.64+0x8] ; LDG.E R7, [R24.64] ; LDG.E R32, [R24.64+0x4] ; IADD3 R19, R5, -c[0x0][0x16c], RZ ; LDG.E R35, [R24.64+-0x8] ; IADD3 R11, R5, c[0x0][0x16c], RZ ; IMAD.WIDE R16, R19, R6.reuse, c[0x0][0x1a0] ; LDG.E R34, [R24.64+0xc] ; IADD3 R13, R11.reuse, c[0x0][0x16c], RZ ; IMAD.WIDE R20, R11, R6.reuse, c[0x0][0x1a0] ; LDG.E R8, [R24.64+-0xc] ; IMAD.WIDE R28, R13, R6, c[0x0][0x1a8] ; LDG.E R9, [R24.64+0x10] ; IMAD.WIDE R14, R23, 0x4, R20 ; LDG.E R10, [R16.64] ; IMAD.MOV.U32 R22, RZ, RZ, c[0x0][0x16c] ; IMAD.WIDE R18, R19, R6, c[0x0][0x1a8] ; LDG.E R12, [R20.64] ; IMAD R22, R22, 0x2, R13 ; LDG.E R24, [R28.64] ; IMAD.WIDE R16, R23, 0x4, R14 ; LDG.E R13, [R14.64] ; IMAD.MOV R26, RZ, RZ, -c[0x0][0x16c] ; IMAD R25, R23.reuse, -0x7, R22 ; LDG.E R11, [R18.64] ; IMAD.WIDE R28, R23, 0x4, R28 ; LDG.E R30, [R16.64] ; IMAD.WIDE R14, R5, R6, c[0x0][0x1a8] ; LEA R27, R26, R5, 0x1 ; LDG.E R31, [R28.64] ; IMAD.WIDE R18, R23, 0x4, R28 ; IMAD.WIDE R16, R23.reuse, 0x4, R16 ; LDG.E R18, [R18.64] ; IMAD.WIDE R22, R23, 0x4, R14 ; LDG.E R28, [R14.64+-0x4] ; IMAD.WIDE R20, R27.reuse, R6.reuse, c[0x0][0x1a0] ; LDG.E R22, [R22.64] ; IMAD.WIDE R26, R27, R6, c[0x0][0x1a8] ; LDG.E R37, [R20.64] ; LDG.E R26, [R26.64] ; LDG.E R23, [R14.64] ; LDG.E R29, [R14.64+0x8] ; LDG.E R16, [R16.64] ; LDG.E R27, [R14.64+0xc] ; FADD R33, -R33, R36 ; LDG.E R36, [R14.64+0x4] ; FADD R32, -R7, R32 ; FFMA R32, R32, c[0x3][0x0], RZ ; FFMA R20, R33, c[0x3][0x4], R32 ; FADD R35, -R35, R34 ; LDG.E R32, [R14.64+-0x8] ; FFMA R17, R35, c[0x3][0x8], R20 ; LDG.E R33, [R14.64+-0xc] ; IMAD.WIDE R20, R5, R6, c[0x0][0x1d0] ; LDG.E R34, [R14.64+0x10] ; LDG.E R35, [R20.64] ; FADD R12, -R7, R12 ; FADD R19, -R8, R9 ; IMAD.WIDE R8, R25, R6, c[0x0][0x1a0] ; FADD R13, -R10, R13 ; LDG.E R7, [R8.64] ; FFMA R12, R12, c[0x3][0x0], RZ ; FADD R24, -R11, R24 ; IMAD.WIDE R10, R25, R6, c[0x0][0x1a8] ; IMAD.WIDE R8, R2.reuse, R6.reuse, c[0x0][0x1c8] ; LDG.E R25, [R10.64] ; IMAD.WIDE R10, R2, R6, c[0x0][0x1c0] ; LDG.E R2, [R10.64] ; FADD R37, -R37, R30 ; FADD R22, -R23, R22 ; FFMA R15, R22, c[0x3][0x0], RZ ; FFMA R22, R13, c[0x3][0x4], R12 ; IMAD.WIDE R12, R4, R6, c[0x0][0x1b8] ; FADD R26, -R26, R31 ; FFMA R31, R24, c[0x3][0x4], R15 ; FADD R30, -R28, R29 ; LDG.E R24, [R8.64] ; IMAD.WIDE R14, R5, R6, c[0x0][0x180] ; IMAD.WIDE R28, R4, R6, c[0x0][0x1b0] ; LDG.E R14, [R14.64] ; LDG.E R4, [R28.64] ; FADD R36, -R23, R36 ; LDG.E R23, [R12.64] ; FFMA R36, R36, c[0x3][0x0], RZ ; FFMA R30, R30, c[0x3][0x4], R36 ; FMUL R6, R35, 0.63661974668502807617 ; F2I.NTZ R6, R6 ; FADD R27, -R32, R27 ; FFMA R27, R27, c[0x3][0x8], R30 ; I2F R30, R6 ; FSETP.GE.AND P0, PT, |R35|, 105615, PT ; FFMA R17, R19, c[0x3][0xc], R17 ; FFMA R22, R37, c[0x3][0x8], R22 ; FADD R7, -R7, R16 ; FFMA R26, R26, c[0x3][0x8], R31 ; FADD R25, -R25, R18 ; FFMA R19, R30, -1.5707962512969970703, R35 ; FFMA R19, R30.reuse, -7.5497894158615963534e-08, R19 ; BSSY B0, 0xf90 ; FADD R34, -R33, R34 ; FFMA R30, R30, -5.3903029534742383927e-15, R19 ; FFMA R16, R7, c[0x3][0xc], R22 ; FFMA R7, R25, c[0x3][0xc], R26 ; FFMA R15, R34, c[0x3][0xc], R27 ; IMAD.MOV.U32 R26, RZ, RZ, R6 ; FMUL R25, R2, R4 ; IMAD.MOV.U32 R2, RZ, RZ, R30 ; FMUL R23, R24, R23 ; SHF.R.S32.HI R24, RZ, 0x1f, R5 ; FMUL R14, R23, R14 ; @!P0 BRA 0xf80 ; FSETP.NEU.AND P1, PT, |R35|, +INF , PT ; @!P1 BRA 0xf60 ; SHF.R.U32.HI R2, RZ, 0x17, R35 ; IMAD.SHL.U32 R6, R35, 0x100, RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; LOP3.LUT R2, R2, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R32, RZ, RZ, RZ ; LOP3.LUT R31, R6, 0x80000000, RZ, 0xfc, !PT ; ULDC.64 UR8, c[0x4][0x8] ; IADD3 R27, R2, -0x80, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R1 ; SHF.R.U32.HI R6, RZ, 0x5, R27 ; MOV R18, UR8 ; IMAD.U32 R19, RZ, RZ, UR9 ; LDG.E.CONSTANT R18, [R18.64] ; IADD3 R32, R32, 0x1, RZ ; UIADD3 UR8, UP0, UR8, 0x4, URZ ; ISETP.NE.AND P1, PT, R32, 0x6, PT ; UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; IMAD.WIDE.U32 R22, R18, R31, RZ ; IADD3 R33, P2, R22, R4, RZ ; IADD3.X R4, R23, UR4, RZ, P2, !PT ; STL [R2], R33 ; IADD3 R2, R2, 0x4, RZ ; @P1 BRA 0xc70 ; LOP3.LUT P1, R27, R27, 0x1f, RZ, 0xc0, !PT ; STL [R1+0x18], R4 ; IADD3 R2, -R6.reuse, 0x4, RZ ; IADD3 R6, -R6, 0x6, RZ ; IMAD R22, R6, 0x4, R1 ; @P1 IMAD R31, R2, 0x4, R1 ; LDL R19, [R22+-0x4] ; @P1 LDL R23, [R31] ; LDL R2, [R22] ; @P1 IADD3 R6, -R27, 0x20, RZ ; @P1 SHF.R.U32.HI R18, RZ, R6.reuse, R23 ; @P1 SHF.R.U32.HI R6, RZ, R6, R19 ; @P1 SHF.L.U32 R23, R2, R27.reuse, RZ ; @P1 SHF.L.U32 R27, R19, R27, RZ ; @P1 IMAD.IADD R2, R6, 0x1, R23 ; @P1 IMAD.IADD R19, R18, 0x1, R27 ; SHF.L.U32.HI R4, R19, 0x2, R2 ; SHF.R.U32.HI R27, RZ, 0x1f, R4 ; ISETP.NE.AND P2, PT, R27, RZ, PT ; IMAD.SHL.U32 R18, R19, 0x4, RZ ; @P2 LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; @P2 LOP3.LUT R18, RZ, R18, RZ, 0x33, !PT ; MOV R19, R4 ; I2F.F64.S64 R18, R18 ; LOP3.LUT P1, R4, R35, 0x80000000, RZ, 0xc0, !PT ; DMUL R22, R18, c[0x2][0x0] ; LEA.HI R6, R2, R27, RZ, 0x2 ; F2F.F32.F64 R22, R22 ; @P2 LOP3.LUT R4, R4, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV R2, RZ, RZ, -R6 ; ISETP.NE.AND P2, PT, R4, RZ, PT ; @P1 IMAD.MOV.U32 R6, RZ, RZ, R2 ; FSEL R2, R22, -R22, !P2 ; BRA 0xf80 ; FMUL R2, RZ, R35 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; BSYNC B0 ; IADD3 R23, R6, 0x1, RZ ; IMAD.MOV.U32 R6, RZ, RZ, 0x3c0885e4 ; MOV R4, 0x3e2aaaa8 ; FMUL R27, R2, R2 ; LOP3.LUT P2, RZ, R23.reuse, 0x1, RZ, 0xc0, !PT ; IMAD.MOV.U32 R18, RZ, RZ, -0x46b2bead ; LOP3.LUT P1, RZ, R23, 0x2, RZ, 0xc0, !PT ; BSSY B0, 0x14d0 ; FSEL R19, R6, 0.041666727513074874878, !P2 ; FSEL R2, R2, 1, !P2 ; FSEL R23, -R4, -0.4999999701976776123, !P2 ; @P2 IMAD.MOV.U32 R22, RZ, RZ, 0x37cbac00 ; @P2 FFMA R18, R27, R22, -0.0013887860113754868507 ; FFMA R18, R27.reuse, R18, R19 ; FFMA R19, R2, R27, RZ ; FFMA R18, R27, R18, R23 ; FFMA R18, R18, R19, R2 ; @P1 FFMA R18, R18, -1, RZ ; FMUL R19, R18, R3 ; FMUL R16, R16, R19 ; @!P0 BRA 0x14c0 ; FSETP.NEU.AND P0, PT, |R35|, +INF , PT ; @!P0 BRA 0x14a0 ; SHF.R.U32.HI R2, RZ, 0x17, R35 ; IMAD.SHL.U32 R18, R35, 0x100, RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R26, RZ, RZ, RZ ; LOP3.LUT R2, R2, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R30, RZ, RZ, RZ ; LOP3.LUT R33, R18, 0x80000000, RZ, 0xfc, !PT ; ULDC.64 UR8, c[0x4][0x8] ; IADD3 R32, R2, -0x80, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R1 ; SHF.R.U32.HI R27, RZ, 0x5, R32 ; IMAD.U32 R18, RZ, RZ, UR8 ; IMAD.U32 R19, RZ, RZ, UR9 ; LDG.E.CONSTANT R18, [R18.64] ; IADD3 R30, R30, 0x1, RZ ; UIADD3 UR8, UP0, UR8, 0x4, URZ ; ISETP.NE.AND P0, PT, R30, 0x6, PT ; UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; IMAD.WIDE.U32 R22, R18, R33, RZ ; IADD3 R31, P1, R22, R26, RZ ; IADD3.X R26, R23, UR4, RZ, P1, !PT ; STL [R2], R31 ; IADD3 R2, R2, 0x4, RZ ; @P0 BRA 0x11b0 ; LOP3.LUT P0, R30, R32, 0x1f, RZ, 0xc0, !PT ; STL [R1+0x18], R26 ; IADD3 R2, -R27.reuse, 0x4, RZ ; IADD3 R18, -R27, 0x6, RZ ; IMAD R31, R18, 0x4, R1 ; @P0 LEA R32, R2, R1, 0x2 ; LDL R19, [R31+-0x4] ; @P0 LDL R18, [R32] ; LDL R2, [R31] ; @P0 IADD3 R27, -R30, 0x20, RZ ; LOP3.LUT P1, R35, R35, 0x80000000, RZ, 0xc0, !PT ; @P0 SHF.R.U32.HI R22, RZ, R27.reuse, R18 ; @P0 SHF.R.U32.HI R18, RZ, R27, R19 ; @P0 SHF.L.U32 R23, R2, R30.reuse, RZ ; @P0 SHF.L.U32 R27, R19, R30, RZ ; @P0 IMAD.IADD R2, R18, 0x1, R23 ; @P0 IMAD.IADD R19, R22, 0x1, R27 ; SHF.L.U32.HI R22, R19, 0x2, R2 ; SHF.R.U32.HI R27, RZ, 0x1f, R22 ; ISETP.NE.AND P0, PT, R27, RZ, PT ; IMAD.SHL.U32 R18, R19, 0x4, RZ ; @P0 LOP3.LUT R22, RZ, R22, RZ, 0x33, !PT ; @P0 LOP3.LUT R18, RZ, R18, RZ, 0x33, !PT ; IMAD.MOV.U32 R19, RZ, RZ, R22 ; I2F.F64.S64 R18, R18 ; DMUL R22, R18, c[0x2][0x0] ; LEA.HI R26, R2, R27, RZ, 0x2 ; F2F.F32.F64 R22, R22 ; @P0 LOP3.LUT R35, R35, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV R2, RZ, RZ, -R26 ; ISETP.NE.AND P0, PT, R35, RZ, PT ; @P1 MOV R26, R2 ; FSEL R30, R22, -R22, !P0 ; BRA 0x14c0 ; FMUL R30, RZ, R35 ; IMAD.MOV.U32 R26, RZ, RZ, RZ ; BSYNC B0 ; LOP3.LUT P1, RZ, R26, 0x1, RZ, 0xc0, !PT ; FMUL R27, R30, R30 ; LOP3.LUT P0, RZ, R26, 0x2, RZ, 0xc0, !PT ; IMAD.MOV.U32 R2, RZ, RZ, -0x46b2bead ; FSEL R19, R6, 0.041666727513074874878, !P1 ; FSEL R30, R30, 1, !P1 ; FSEL R23, -R4, -0.4999999701976776123, !P1 ; SHF.L.U64.HI R24, R5, 0x2, R24 ; @P1 IMAD.MOV.U32 R18, RZ, RZ, 0x37cbac00 ; @P1 FFMA R2, R27, R18, -0.0013887860113754868507 ; IMAD.SHL.U32 R18, R5, 0x4, RZ ; FFMA R2, R27.reuse, R2, R19 ; FFMA R19, R30, R27, RZ ; FFMA R2, R27, R2, R23 ; FFMA R19, R2, R19, R30 ; @P0 FFMA R19, R19, -1, RZ ; IADD3 R22, P0, R18, c[0x0][0x190], RZ ; FMUL R19, R19, R0 ; IADD3.X R23, R24, c[0x0][0x194], RZ, P0, !PT ; FFMA R16, -R17, R19, R16 ; FFMA R25, -R25, R16, R14 ; STG.E [R22.64], R25 ; LDG.E R20, [R20.64] ; IADD3 R26, P0, R18, c[0x0][0x188], RZ ; LDG.E R8, [R8.64] ; IADD3.X R27, R24, c[0x0][0x18c], RZ, P0, !PT ; LDG.E R13, [R12.64] ; LDG.E R10, [R10.64] ; LDG.E R29, [R28.64] ; LDG.E R27, [R26.64] ; BSSY B0, 0x1b70 ; FMUL R2, R20, 0.63661974668502807617 ; F2I.NTZ R2, R2 ; FSETP.GE.AND P0, PT, |R20|, 105615, PT ; I2F R5, R2 ; IMAD.MOV.U32 R17, RZ, RZ, R2 ; FFMA R14, R5, -1.5707962512969970703, R20 ; FFMA R16, R5.reuse, -7.5497894158615963534e-08, R14 ; FMUL R14, R8, R13 ; FFMA R16, R5, -5.3903029534742383927e-15, R16 ; FMUL R13, R10, R29 ; FMUL R14, R14, R27 ; IMAD.MOV.U32 R5, RZ, RZ, R16 ; @!P0 BRA 0x1b60 ; FSETP.NEU.AND P1, PT, |R20|, +INF , PT ; @!P1 BRA 0x1b40 ; SHF.R.U32.HI R2, RZ, 0x17, R20 ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; SHF.L.U32 R8, R20, 0x8, RZ ; IMAD.MOV.U32 R22, RZ, RZ, RZ ; LOP3.LUT R2, R2, 0xff, RZ, 0xc0, !PT ; UMOV UR4, URZ ; LOP3.LUT R19, R8, 0x80000000, RZ, 0xfc, !PT ; ULDC.64 UR8, c[0x4][0x8] ; IADD3 R5, R2, -0x80, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R1 ; SHF.R.U32.HI R21, RZ, 0x5, R5 ; IMAD.U32 R8, RZ, RZ, UR8 ; IMAD.U32 R9, RZ, RZ, UR9 ; LDG.E.CONSTANT R8, [R8.64] ; IADD3 R22, R22, 0x1, RZ ; UIADD3 UR8, UP0, UR8, 0x4, URZ ; ISETP.NE.AND P1, PT, R22, 0x6, PT ; UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; IMAD.WIDE.U32 R10, R8, R19, RZ ; IADD3 R23, P2, R10, R12, RZ ; IADD3.X R12, R11, UR4, RZ, P2, !PT ; STL [R2], R23 ; IADD3 R2, R2, 0x4, RZ ; @P1 BRA 0x1860 ; LOP3.LUT P1, R11, R5, 0x1f, RZ, 0xc0, !PT ; STL [R1+0x18], R12 ; IADD3 R2, -R21.reuse, 0x4, RZ ; IADD3 R8, -R21, 0x6, RZ ; LEA R19, R8, R1, 0x2 ; @P1 IMAD R21, R2, 0x4, R1 ; LDL R5, [R19+-0x4] ; @P1 LDL R9, [R21] ; LDL R2, [R19] ; @P1 IADD3 R8, -R11, 0x20, RZ ; @P1 SHF.R.U32.HI R10, RZ, R8.reuse, R9 ; @P1 SHF.R.U32.HI R8, RZ, R8, R5 ; @P1 SHF.L.U32 R9, R2, R11.reuse, RZ ; @P1 SHF.L.U32 R11, R5, R11, RZ ; @P1 IMAD.IADD R2, R8, 0x1, R9 ; @P1 IMAD.IADD R5, R10, 0x1, R11 ; SHF.L.U32.HI R11, R5, 0x2, R2 ; SHF.R.U32.HI R21, RZ, 0x1f, R11 ; ISETP.NE.AND P2, PT, R21, RZ, PT ; IMAD.SHL.U32 R10, R5, 0x4, RZ ; @P2 LOP3.LUT R11, RZ, R11, RZ, 0x33, !PT ; @P2 LOP3.LUT R10, RZ, R10, RZ, 0x33, !PT ; I2F.F64.S64 R8, R10 ; LOP3.LUT P1, R5, R20, 0x80000000, RZ, 0xc0, !PT ; DMUL R8, R8, c[0x2][0x0] ; @P2 LOP3.LUT R5, R5, 0x80000000, RZ, 0x3c, !PT ; LEA.HI R2, R2, R21, RZ, 0x2 ; F2F.F32.F64 R8, R8 ; ISETP.NE.AND P2, PT, R5, RZ, PT ; IMAD.MOV R5, RZ, RZ, -R2 ; @P1 IMAD.MOV.U32 R2, RZ, RZ, R5 ; FSEL R5, R8, -R8, !P2 ; BRA 0x1b60 ; FMUL R5, RZ, R20 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; BSYNC B0 ; LOP3.LUT P2, RZ, R2, 0x1, RZ, 0xc0, !PT ; FMUL R11, R5, R5 ; MOV R8, 0xb94d4153 ; BSSY B0, 0x2070 ; FSEL R9, R6, 0.041666727513074874878, !P2 ; LOP3.LUT P1, RZ, R2, 0x2, RZ, 0xc0, !PT ; @P2 IMAD.MOV.U32 R10, RZ, RZ, 0x37cbac00 ; @P2 FFMA R8, R11, R10, -0.0013887860113754868507 ; FSEL R10, R5, 1, !P2 ; FSEL R5, -R4, -0.4999999701976776123, !P2 ; FFMA R8, R11.reuse, R8, R9 ; FFMA R2, R10, R11, RZ ; FFMA R5, R11, R8, R5 ; FFMA R2, R5, R2, R10 ; @P1 FFMA R2, R2, -1, RZ ; FMUL R22, R2, R3 ; FMUL R22, R7, R22 ; @!P0 BRA 0x2060 ; FSETP.NEU.AND P0, PT, |R20|, +INF , PT ; @!P0 BRA 0x2040 ; SHF.R.U32.HI R2, RZ, 0x17, R20 ; IMAD.SHL.U32 R5, R20, 0x100, RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; LOP3.LUT R2, R2, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R3, RZ, RZ, RZ ; LOP3.LUT R17, R5, 0x80000000, RZ, 0xfc, !PT ; ULDC.64 UR8, c[0x4][0x8] ; IADD3 R7, R2, -0x80, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R1 ; SHF.R.U32.HI R16, RZ, 0x5, R7 ; IMAD.U32 R10, RZ, RZ, UR8 ; MOV R11, UR9 ; LDG.E.CONSTANT R8, [R10.64] ; IADD3 R3, R3, 0x1, RZ ; UIADD3 UR8, UP0, UR8, 0x4, URZ ; ISETP.NE.AND P0, PT, R3, 0x6, PT ; UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; IMAD.WIDE.U32 R8, R8, R17, RZ ; IADD3 R5, P1, R8, R12, RZ ; IADD3.X R12, R9, UR4, RZ, P1, !PT ; STL [R2], R5 ; IADD3 R2, R2, 0x4, RZ ; @P0 BRA 0x1d60 ; LOP3.LUT P0, R9, R7, 0x1f, RZ, 0xc0, !PT ; STL [R1+0x18], R12 ; IADD3 R2, -R16.reuse, 0x4, RZ ; IADD3 R16, -R16, 0x6, RZ ; IMAD R16, R16, 0x4, R1 ; @P0 IMAD R17, R2, 0x4, R1 ; LDL R3, [R16+-0x4] ; @P0 LDL R5, [R17] ; LDL R2, [R16] ; @P0 IADD3 R10, -R9, 0x20, RZ ; LOP3.LUT P1, R20, R20, 0x80000000, RZ, 0xc0, !PT ; @P0 SHF.R.U32.HI R7, RZ, R10.reuse, R5 ; @P0 SHF.R.U32.HI R5, RZ, R10, R3 ; @P0 SHF.L.U32 R8, R2, R9.reuse, RZ ; @P0 SHF.L.U32 R10, R3, R9, RZ ; @P0 IMAD.IADD R2, R5, 0x1, R8 ; @P0 IMAD.IADD R3, R7, 0x1, R10 ; SHF.L.U32.HI R11, R3, 0x2, R2 ; SHF.R.U32.HI R17, RZ, 0x1f, R11 ; ISETP.NE.AND P0, PT, R17, RZ, PT ; IMAD.SHL.U32 R10, R3, 0x4, RZ ; @P0 LOP3.LUT R11, RZ, R11, RZ, 0x33, !PT ; @P0 LOP3.LUT R10, RZ, R10, RZ, 0x33, !PT ; I2F.F64.S64 R8, R10 ; DMUL R8, R8, c[0x2][0x0] ; LEA.HI R17, R2, R17, RZ, 0x2 ; F2F.F32.F64 R8, R8 ; @P0 LOP3.LUT R20, R20, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV R2, RZ, RZ, -R17 ; ISETP.NE.AND P0, PT, R20, RZ, PT ; @P1 MOV R17, R2 ; FSEL R16, R8, -R8, !P0 ; BRA 0x2060 ; FMUL R16, RZ, R20 ; IMAD.MOV.U32 R17, RZ, RZ, RZ ; BSYNC B0 ; IADD3 R17, R17, 0x1, RZ ; FMUL R7, R16, R16 ; IMAD.MOV.U32 R2, RZ, RZ, -0x46b2bead ; LOP3.LUT P1, RZ, R17, 0x1, RZ, 0xc0, !PT ; LOP3.LUT P0, RZ, R17, 0x2, RZ, 0xc0, !PT ; FSEL R3, R6, 0.041666727513074874878, !P1 ; FSEL R16, R16, 1, !P1 ; FSEL R5, -R4, -0.4999999701976776123, !P1 ; @P1 IMAD.MOV.U32 R8, RZ, RZ, 0x37cbac00 ; @P1 FFMA R2, R7, R8, -0.0013887860113754868507 ; FFMA R2, R7.reuse, R2, R3 ; FFMA R3, R16, R7, RZ ; FFMA R2, R7, R2, R5 ; FFMA R3, R2, R3, R16 ; @P0 FFMA R3, R3, -1, RZ ; IADD3 R18, P0, R18, c[0x0][0x198], RZ ; FMUL R0, R3, R0 ; IADD3.X R19, R24, c[0x0][0x19c], RZ, P0, !PT ; FFMA R0, R15, R0, R22 ; FFMA R13, -R13, R0, R14 ; STG.E [R18.64], R13 ; EXIT ; SHF.R.U32.HI R7, RZ, 0x17, R8 ; SHF.R.U32.HI R6, RZ, 0x17, R11.reuse ; LOP3.LUT R15, R7, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; IADD3 R12, R15, -0x1, RZ ; IADD3 R10, R6, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; @!P0 BRA 0x23f0 ; FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; FSETP.GTU.FTZ.AND P1, PT, |R8|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0x27d0 ; LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; @!P0 BRA 0x27b0 ; FSETP.NEU.FTZ.AND P2, PT, |R11|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P1, PT, |R8|, +INF , PT ; FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; @!P1 BRA !P2, 0x27b0 ; LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; @P1 BRA 0x2790 ; LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; @P0 BRA 0x2760 ; ISETP.GE.AND P0, PT, R10, RZ, PT ; ISETP.GE.AND P1, PT, R12, RZ, PT ; @P0 MOV R9, RZ ; @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; @!P0 FFMA R7, R11, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R8, R8, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R9, R9, 0x40, RZ ; LEA R11, R15, 0xc0800000, 0x17 ; IADD3 R6, R6, -0x7f, RZ ; IMAD.IADD R11, R8, 0x1, -R11 ; IMAD R7, R6, -0x800000, R7 ; MUFU.RCP R8, R11 ; FADD.FTZ R10, -R11, -RZ ; FFMA R13, R8, R10, 1 ; FFMA R12, R8, R13, R8 ; FFMA R8, R7, R12, RZ ; FFMA R13, R10, R8, R7 ; FFMA R13, R12, R13, R8 ; IADD3 R8, R6, 0x7f, -R15 ; FFMA R10, R10, R13, R7 ; IMAD.IADD R8, R8, 0x1, R9 ; FFMA R7, R12, R10, R13 ; SHF.R.U32.HI R6, RZ, 0x17, R7 ; LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; IMAD.IADD R14, R6, 0x1, R8 ; IADD3 R6, R14, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; @!P0 BRA 0x2740 ; ISETP.GT.AND P0, PT, R14, 0xfe, PT ; @P0 BRA 0x2710 ; ISETP.GE.AND P0, PT, R14, 0x1, PT ; @P0 BRA 0x27e0 ; ISETP.GE.AND P0, PT, R14, -0x18, PT ; LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0x27e0 ; FFMA.RZ R6, R12, R10.reuse, R13.reuse ; IADD3 R11, R14, 0x20, RZ ; FFMA.RM R9, R12, R10.reuse, R13.reuse ; ISETP.NE.AND P2, PT, R14, RZ, PT ; LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; FFMA.RP R6, R12, R10, R13 ; ISETP.NE.AND P1, PT, R14, RZ, PT ; IMAD.MOV R10, RZ, RZ, -R14 ; LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; FSETP.NEU.FTZ.AND P0, PT, R6, R9, PT ; SHF.L.U32 R11, R8, R11, RZ ; SEL R9, R10, RZ, P2 ; ISETP.NE.AND P1, PT, R11, RZ, P1 ; SHF.R.U32.HI R9, RZ, R9, R8 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R11, RZ, 0x1, R9 ; SEL R6, RZ, 0x1, !P0 ; LOP3.LUT R6, R6, 0x1, R11, 0xf8, !PT ; LOP3.LUT R6, R6, R9, RZ, 0xc0, !PT ; IADD3 R6, R11, R6, RZ ; LOP3.LUT R7, R6, R7, RZ, 0xfc, !PT ; BRA 0x27e0 ; LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x27e0 ; IMAD R7, R8, 0x800000, R7 ; BRA 0x27e0 ; LOP3.LUT R7, R8, 0x80000000, R7, 0x48, !PT ; LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x27e0 ; LOP3.LUT R7, R8, 0x80000000, R7, 0x48, !PT ; BRA 0x27e0 ; MUFU.RSQ R7, -QNAN ; BRA 0x27e0 ; FADD.FTZ R7, R11, R8 ; IMAD.MOV.U32 R8, RZ, RZ, R7 ; IMAD.MOV.U32 R6, RZ, RZ, R0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; RET.REL.NODEC R6 0x0 ; BRA 0x2820; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z10add_sourcefffiiiifffiiiiPfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; IADD3 R0, R3, 0x1800000, RZ ; LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; @P0 BRA 0xa0 ; MOV R0, 0x80 ; CALL.REL.NOINC 0x11a0 ; IMAD.MOV.U32 R0, RZ, RZ, R4 ; BRA 0xe0 ; MUFU.RCP R0, c[0x0][0x184] ; FFMA R2, R0, R3, -1 ; FADD.FTZ R3, -R2, -RZ ; FFMA R0, R0, R3, R0 ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; FADD R10, -R0, c[0x0][0x180] ; ISETP.NE.AND P0, PT, R2, 0x1, PT ; @!P0 BRA 0x6f0 ; ISETP.NE.AND P0, PT, R2, 0x2, PT ; @!P0 BRA 0x400 ; ISETP.NE.AND P0, PT, R2, 0x3, PT ; IMAD.MOV.U32 R11, RZ, RZ, RZ ; @P0 BRA 0x9e0 ; MUFU.RCP64H R5, -2.3025836944580078125 ; MOV R11, c[0x0][0x184] ; IMAD.MOV.U32 R8, RZ, RZ, -0x444aaaeb ; IMAD.MOV.U32 R9, RZ, RZ, 0x40026bb1 ; IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; FMUL R11, R11, c[0x0][0x184] ; F2F.F64.F32 R2, R11 ; DFMA R6, R4, R8, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R4, R6, R4 ; DMUL R2, R2, c[0x2][0x0] ; DFMA R4, R6, R8, 1 ; DMUL R2, R2, c[0x2][0x0] ; DFMA R4, R6, R4, R6 ; DMUL R6, R2, R4 ; FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, c[0x2][0x8], R2 ; DFMA R4, R4, R8, R6 ; FFMA R6, RZ, -2.0378229618072509766, R5 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x320 ; IMAD.MOV.U32 R11, RZ, RZ, R2 ; MOV R16, R3 ; IMAD.MOV.U32 R4, RZ, RZ, -0x444aaaeb ; MOV R12, 0x320 ; IMAD.MOV.U32 R5, RZ, RZ, -0x3ffd944f ; CALL.REL.NOINC 0xbc0 ; F2F.F32.F64 R5, R4 ; IMAD.MOV.U32 R2, RZ, RZ, 0x3bbb989d ; IMAD.MOV.U32 R7, RZ, RZ, 0x437c0000 ; FMUL R3, R10, R5 ; FMUL R3, R10, R3 ; FFMA.SAT R2, R3, R2, 0.5 ; FFMA.RM R2, R2, R7, 12582913 ; FADD R6, R2.reuse, -12583039 ; SHF.L.U32 R2, R2, 0x17, RZ ; FFMA R6, R3, 1.4426950216293334961, -R6 ; FFMA R6, R3, 1.925963033500011079e-08, R6 ; MUFU.EX2 R11, R6 ; FMUL R11, R2, R11 ; BRA 0x9e0 ; MUFU.RCP64H R5, 2.3025836944580078125 ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x184] ; IMAD.MOV.U32 R8, RZ, RZ, -0x444aaaeb ; FMUL R2, R2, -4 ; IMAD.MOV.U32 R9, RZ, RZ, 0x40026bb1 ; IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; FMUL R11, R2, c[0x0][0x184] ; F2F.F64.F32 R2, R11 ; DFMA R6, R4, -R8, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R4, R6, R4 ; DMUL R2, R2, c[0x2][0x0] ; DFMA R4, R6, -R8, 1 ; DMUL R2, R2, c[0x2][0x0] ; DFMA R4, R6, R4, R6 ; DMUL R6, R2, R4 ; FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, c[0x2][0x10], R2 ; DFMA R4, R4, R8, R6 ; FFMA R6, RZ, 2.0378229618072509766, R5 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x5c0 ; MOV R11, R2 ; IMAD.MOV.U32 R16, RZ, RZ, R3 ; MOV R12, 0x5c0 ; IMAD.MOV.U32 R4, RZ, RZ, -0x444aaaeb ; IMAD.MOV.U32 R5, RZ, RZ, 0x40026bb1 ; CALL.REL.NOINC 0xbc0 ; F2F.F32.F64 R5, R4 ; IMAD.MOV.U32 R2, RZ, RZ, 0x3bbb989d ; MOV R7, 0x437c0000 ; FMUL R3, R10, R5 ; FMUL R3, R10, R3 ; F2F.F64.F32 R10, R10 ; FFMA.SAT R2, R3, R2, 0.5 ; FFMA.RM R2, R2, R7, 12582913 ; FADD R6, R2.reuse, -12583039 ; IMAD.SHL.U32 R2, R2, 0x800000, RZ ; FFMA R6, R3, 1.4426950216293334961, -R6 ; FFMA R6, R3, 1.925963033500011079e-08, R6 ; MUFU.EX2 R3, R6 ; FMUL R4, R2, R3 ; DMUL R2, R10, c[0x2][0x18] ; F2F.F64.F32 R4, R4 ; DMUL R2, R2, R4 ; F2F.F32.F64 R11, R2 ; BRA 0x9e0 ; FMUL R10, R10, c[0x0][0x184] ; MOV R13, 0x3e5ade15 ; IMAD.MOV.U32 R6, RZ, RZ, 0x652b82fe ; FMUL R2, R10, R10 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3ff71547 ; IMAD.MOV.U32 R12, RZ, RZ, 0x69ce2bdf ; F2F.F64.F32 R2, R2 ; DMUL R4, R2, c[0x2][0x28] ; DFMA R6, R4, R6, 6.75539944105574400000e+15 ; FSETP.GEU.AND P0, PT, |R5|, 4.1917929649353027344, PT ; DADD R8, R6, -6.75539944105574400000e+15 ; DFMA R10, R8, c[0x2][0x30], R4 ; DFMA R8, R8, c[0x2][0x38], R10 ; DFMA R10, R8, R12, c[0x2][0x40] ; DFMA R10, R8, R10, c[0x2][0x48] ; DFMA R10, R8, R10, c[0x2][0x50] ; DFMA R10, R8, R10, c[0x2][0x58] ; DFMA R10, R8, R10, c[0x2][0x60] ; DFMA R10, R8, R10, c[0x2][0x68] ; DFMA R10, R8, R10, c[0x2][0x70] ; DFMA R10, R8, R10, c[0x2][0x78] ; DFMA R10, R8, R10, c[0x2][0x80] ; DFMA R10, R8, R10, 1 ; DFMA R12, R8, R10, 1 ; IMAD.MOV.U32 R10, RZ, RZ, -0x36618f3a ; IMAD.MOV.U32 R11, RZ, RZ, 0x4033bd3c ; DFMA R10, R2, -R10, 1 ; IMAD R9, R6, 0x100000, R13 ; IMAD.MOV.U32 R8, RZ, RZ, R12 ; @!P0 BRA 0x9c0 ; DMUL R2, R2, c[0x2][0x20] ; FSETP.GEU.AND P1, PT, |R5|, 4.2275390625, PT ; DADD R8, -R2, +INF ; DSETP.GT.AND P0, PT, R2, RZ, PT ; FSEL R8, R8, RZ, !P0 ; FSEL R9, R9, RZ, !P0 ; @P1 BRA 0x9c0 ; LEA.HI R2, R6, R6, RZ, 0x1 ; IMAD.MOV.U32 R8, RZ, RZ, R12 ; SHF.R.S32.HI R9, RZ, 0x1, R2 ; IADD3 R2, R6, -R9, RZ ; IMAD R9, R9, 0x100000, R13 ; LEA R3, R2, 0x3ff00000, 0x14 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; DMUL R8, R8, R2 ; DMUL R10, R10, R8 ; F2F.F32.F64 R11, R10 ; FADD R0, R0, R0 ; FSETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; @!P0 EXIT ; ULDC.64 UR4, c[0x0][0x190] ; F2F.F64.F32 R4, c[0x0][0x168] ; UIADD3 UR4, UR4, -0x1, URZ ; IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; UIMAD UR4, UR4, UR5, URZ ; I2F R0, UR4 ; ULDC UR4, c[0x0][0x18c] ; DADD R4, R4, 0.5 ; UIADD3 UR4, UR4, -0x1, URZ ; F2I.F64.TRUNC R4, R4 ; FADD R0, R0, c[0x0][0x164] ; F2F.F64.F32 R2, R0 ; IADD3 R7, R4, UR4, RZ ; DADD R2, R2, 0.5 ; F2I.F64.TRUNC R2, R2 ; IADD3 R6, R2, UR4, RZ ; ULDC.64 UR4, c[0x0][0x118] ; IMAD R8, R6, c[0x0][0x178], R7 ; IMAD.WIDE R6, R8, R9, c[0x0][0x198] ; LDG.E R0, [R6.64] ; IMAD.WIDE R2, R8, R9, c[0x0][0x1a0] ; FFMA R5, R11, c[0x0][0x160], R0 ; STG.E [R6.64], R5 ; LDG.E R0, [R2.64] ; FFMA R11, R11, c[0x0][0x160], R0 ; STG.E [R2.64], R11 ; EXIT ; FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; LOP3.LUT R2, R5.reuse, 0x800fffff, RZ, 0xc0, !PT ; LOP3.LUT R18, R5, 0x7ff00000, RZ, 0xc0, !PT ; LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; MOV R2, R4 ; @!P0 DMUL R2, R4, 8.98846567431157953865e+307 ; MUFU.RCP64H R9, R3 ; DFMA R6, R8, -R2, 1 ; DFMA R14, R6, R6, R6 ; IMAD.MOV.U32 R7, RZ, RZ, R16 ; IMAD.MOV.U32 R6, RZ, RZ, R11 ; IMAD.MOV.U32 R11, RZ, RZ, 0x1ca00000 ; LOP3.LUT R13, R7, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R14, R8, R14, R8 ; ISETP.GE.U32.AND P1, PT, R13, R18, PT ; MOV R19, R13 ; DFMA R8, R14.reuse, -R2, 1 ; SEL R17, R11, 0x63400000, !P1 ; FSETP.GEU.AND P1, PT, |R7|, 1.469367938527859385e-39, PT ; @!P0 LOP3.LUT R18, R3, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R14, R14, R8, R14 ; LOP3.LUT R9, R17, 0x800fffff, R7, 0xf8, !PT ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; @P1 BRA 0xdd0 ; LOP3.LUT R16, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R13, R16, PT ; IMAD.MOV.U32 R16, RZ, RZ, RZ ; SEL R17, R11, 0x63400000, !P0 ; LOP3.LUT R17, R17, 0x80000000, R7, 0xf8, !PT ; LOP3.LUT R17, R17, 0x100000, RZ, 0xfc, !PT ; DFMA R8, R8, 2, -R16 ; LOP3.LUT R19, R9, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R20, R19, -0x1, RZ ; DMUL R16, R14, R8 ; IADD3 R22, R18, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; DFMA R20, R16, -R2, R8 ; ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; DFMA R14, R14, R20, R16 ; @P0 BRA 0x1010 ; LOP3.LUT R16, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R13.reuse, R16, PT ; IMAD.IADD R6, R13, 0x1, -R16 ; SEL R11, R11, 0x63400000, !P0 ; IMNMX R6, R6, -0x46a00000, !PT ; IMNMX R6, R6, 0x46a00000, PT ; IMAD.IADD R11, R6, 0x1, -R11 ; MOV R6, RZ ; IADD3 R7, R11, 0x7fe00000, RZ ; DMUL R16, R14, R6 ; FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT ; @P0 BRA 0x1160 ; DFMA R2, R14, -R2, R8 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; LOP3.LUT R5, R3, 0x80000000, R5, 0x48, !PT ; LOP3.LUT R7, R5, R7, RZ, 0xfc, !PT ; @!P0 BRA 0x1160 ; IMAD.MOV R3, RZ, RZ, -R11 ; DMUL.RP R6, R14, R6 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; DFMA R2, R16, -R2, R14 ; LOP3.LUT R5, R7, R5, RZ, 0x3c, !PT ; IADD3 R2, -R11, -0x43300000, RZ ; FSETP.NEU.AND P0, PT, |R3|, R2, PT ; FSEL R16, R6, R16, !P0 ; FSEL R17, R5, R17, !P0 ; BRA 0x1160 ; DSETP.NAN.AND P0, PT, R6, R6, PT ; @P0 BRA 0x1140 ; DSETP.NAN.AND P0, PT, R4, R4, PT ; @P0 BRA 0x1110 ; ISETP.NE.AND P0, PT, R19, R18, PT ; IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; MOV R17, 0xfff80000 ; @!P0 BRA 0x1160 ; ISETP.NE.AND P0, PT, R19, 0x7ff00000, PT ; LOP3.LUT R17, R7, 0x80000000, R5, 0x48, !PT ; ISETP.EQ.OR P0, PT, R18, RZ, !P0 ; @P0 LOP3.LUT R2, R17, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R17, RZ, RZ, R2 ; BRA 0x1160 ; LOP3.LUT R17, R5, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R16, RZ, RZ, R4 ; BRA 0x1160 ; LOP3.LUT R17, R7, 0x80000, RZ, 0xfc, !PT ; MOV R16, R6 ; IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, R16 ; IMAD.MOV.U32 R5, RZ, RZ, R17 ; RET.REL.NODEC R12 0x0 ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x184] ; SHF.L.U32 R3, R11, 0x1, RZ ; SHF.R.U32.HI R2, RZ, 0x18, R3 ; ISETP.NE.U32.AND P0, PT, R2, RZ, PT ; @P0 BRA 0x1290 ; ISETP.NE.AND P0, PT, R3, RZ, PT ; @!P0 MUFU.RCP R2, c[0x0][0x184] ; @!P0 BRA 0x14b0 ; FFMA R3, R11, 1.84467440737095516160e+19, RZ ; MUFU.RCP R2, R3 ; FFMA R4, R3, R2, -1 ; FADD.FTZ R5, -R4, -RZ ; FFMA R2, R2, R5, R2 ; FFMA R2, R2, 1.84467440737095516160e+19, RZ ; BRA 0x14b0 ; IADD3 R3, R2, -0xfd, RZ ; ISETP.GT.U32.AND P0, PT, R3, 0x1, PT ; @P0 BRA 0x14a0 ; LOP3.LUT R4, R11, 0x7fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R8, RZ, RZ, 0x3 ; LOP3.LUT R4, R4, 0x3f800000, RZ, 0xfc, !PT ; SHF.L.U32 R9, R8, R3, RZ ; MUFU.RCP R5, R4 ; FFMA R6, R4, R5, -1 ; FADD.FTZ R6, -R6, -RZ ; FFMA.RM R7, R5.reuse, R6.reuse, R5.reuse ; FFMA.RP R6, R5, R6, R5 ; LOP3.LUT R5, R7.reuse, 0x7fffff, RZ, 0xc0, !PT ; FSETP.NEU.FTZ.AND P0, PT, R7, R6, PT ; LOP3.LUT R6, R5, 0x800000, RZ, 0xfc, !PT ; SEL R5, RZ, 0xffffffff, !P0 ; LOP3.LUT R4, R9, R6, RZ, 0xc0, !PT ; IMAD.MOV R5, RZ, RZ, -R5 ; SHF.R.U32.HI R4, RZ, R3, R4 ; LOP3.LUT P1, RZ, R5, R3, R6, 0xf8, !PT ; LOP3.LUT P0, RZ, R4.reuse, 0x1, RZ, 0xc0, !PT ; LOP3.LUT P2, RZ, R4, 0x2, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; LOP3.LUT P1, RZ, R11, 0x7fffff, RZ, 0xc0, !PT ; SEL R3, RZ, 0x1, !P0 ; IMAD.MOV R3, RZ, RZ, -R3 ; ISETP.GE.AND P0, PT, R3, RZ, PT ; IADD3 R3, R2, -0xfc, RZ ; SHF.R.U32.HI R2, RZ, R3, R6 ; @!P0 IADD3 R2, R2, 0x1, RZ ; @!P1 IMAD.SHL.U32 R2, R2, 0x2, RZ ; LOP3.LUT R2, R2, 0x80000000, R11, 0xf8, !PT ; BRA 0x14b0 ; MUFU.RCP R2, c[0x0][0x184] ; MOV R4, R2 ; IMAD.MOV.U32 R2, RZ, RZ, R0 ; IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; RET.REL.NODEC R2 0x0 ; BRA 0x14f0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0004d737_00000000-6_297789cdb8cb1e88d34425cfd19a9286e06b9395.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2063: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2063: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Cuda error: %s: %s\n" .text .globl _Z15check_gpu_errorPKc .type _Z15check_gpu_errorPKc, @function _Z15check_gpu_errorPKc: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx call cudaGetLastError@PLT testl %eax, %eax jne .L6 popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L6: .cfi_restore_state movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx movq %rbx, %rdx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %edi call exit@PLT .cfi_endproc .LFE2057: .size _Z15check_gpu_errorPKc, .-_Z15check_gpu_errorPKc .globl _Z6pad_vviiiiiPf .type _Z6pad_vviiiiiPf, @function _Z6pad_vviiiiiPf: .LFB2058: .cfi_startproc endbr64 movl %edx, %esi imull %ecx, %esi testl %esi, %esi jle .L18 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movl %edx, %r10d subl %r8d, %r10d leal -1(%r10), %ebx imull %ecx, %ebx movl %ecx, %r11d imull %r8d, %r11d movslq %esi, %rsi movl $0, %edi jmp .L11 .L9: cmpl %eax, %r10d jg .L10 addl %ebx, %edx movslq %edx, %rdx movss (%r9,%rdx,4), %xmm0 movss %xmm0, (%r9,%rdi,4) .L10: leaq 1(%rdi), %rax cmpq %rsi, %rax je .L21 movq %rax, %rdi .L11: movl %edi, %eax cltd idivl %ecx cmpl %eax, %r8d jle .L9 addl %r11d, %edx movslq %edx, %rdx movss (%r9,%rdx,4), %xmm0 movss %xmm0, (%r9,%rdi,4) jmp .L10 .L21: movl $0, %esi movl %ecx, %r10d subl %r8d, %r10d jmp .L14 .L12: cmpl %edx, %r10d jg .L13 imull %ecx, %eax addl %ecx, %eax subl %r8d, %eax cltq movss -4(%r9,%rax,4), %xmm0 movss %xmm0, (%r9,%rsi,4) .L13: leaq 1(%rsi), %rax cmpq %rdi, %rsi je .L22 movq %rax, %rsi .L14: movl %esi, %eax cltd idivl %ecx cmpl %r8d, %edx jge .L12 imull %ecx, %eax addl %r8d, %eax cltq movss (%r9,%rax,4), %xmm0 movss %xmm0, (%r9,%rsi,4) jmp .L13 .L22: popq %rbx .cfi_def_cfa_offset 8 ret .L18: .cfi_restore 3 ret .cfi_endproc .LFE2058: .size _Z6pad_vviiiiiPf, .-_Z6pad_vviiiiiPf .section .rodata.str1.1 .LC1: .string "rb" .LC2: .string "error open <%s>!\n" .text .globl _Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i .type _Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i, @function _Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i: .LFB2059: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %rdi, %r12 movq %rsi, %rbp movq %rdx, %rbx movq %rcx, %r13 movl %r8d, %r14d movl %r9d, %r15d leaq .LC1(%rip), %rsi call fopen@PLT movq %rax, (%rsp) testq %rax, %rax je .L35 .L24: leaq .LC1(%rip), %rsi movq %rbp, %rdi call fopen@PLT movq %rax, 8(%rsp) testq %rax, %rax je .L36 .L25: leaq .LC1(%rip), %rsi movq %rbx, %rdi call fopen@PLT movq %rax, 16(%rsp) testq %rax, %rax je .L37 .L26: leaq .LC1(%rip), %rsi movq %r13, %rdi call fopen@PLT movq %rax, 24(%rsp) testq %rax, %rax je .L38 .L27: movl %r14d, %esi addl 160(%rsp), %esi cmpl 160(%rsp), %esi jle .L28 movl 160(%rsp), %ecx imull 120(%rsp), %ecx movl 160(%rsp), %edx movl %esi, 44(%rsp) movl %r15d, %edi movl %edx, %esi jmp .L29 .L35: movq %r12, %rdx leaq .LC2(%rip), %rsi movl $2, %edi call __printf_chk@PLT jmp .L24 .L36: movq %rbp, %rdx leaq .LC2(%rip), %rsi movl $2, %edi call __printf_chk@PLT jmp .L25 .L37: movq %rbx, %rdx leaq .LC2(%rip), %rsi movl $2, %edi call __printf_chk@PLT jmp .L26 .L38: movq %r13, %rdx leaq .LC2(%rip), %rsi movl $2, %edi call __printf_chk@PLT jmp .L27 .L31: movslq %esi, %rbx movslq %ecx, %r8 addq %r8, %rbx salq $2, %rbx movq %rbx, %r14 addq 128(%rsp), %r14 movq %rbx, %r13 addq 136(%rsp), %r13 movq %rbx, %r12 addq 144(%rsp), %r12 addq 152(%rsp), %rbx movl %esi, %ebp movl %edx, 32(%rsp) movl %ecx, 36(%rsp) movl %edi, 40(%rsp) movl %esi, 160(%rsp) .L30: movq (%rsp), %r8 movl $1, %ecx movl $4, %edx movq $-1, %rsi movq %r14, %rdi call __fread_chk@PLT movq 8(%rsp), %r8 movl $1, %ecx movl $4, %edx movq $-1, %rsi movq %r13, %rdi call __fread_chk@PLT movq 16(%rsp), %r8 movl $1, %ecx movl $4, %edx movq $-1, %rsi movq %r12, %rdi call __fread_chk@PLT movq 24(%rsp), %r8 movl $1, %ecx movl $4, %edx movq $-1, %rsi movq %rbx, %rdi call __fread_chk@PLT pxor %xmm0, %xmm0 cvtss2sd (%rbx), %xmm0 mulsd .LC3(%rip), %xmm0 cvtsd2ss %xmm0, %xmm0 movss %xmm0, (%rbx) addl $1, %ebp addq $4, %r14 addq $4, %r13 addq $4, %r12 addq $4, %rbx cmpl %r15d, %ebp jl .L30 movl 32(%rsp), %edx movl 36(%rsp), %ecx movl 40(%rsp), %edi movl 160(%rsp), %esi .L32: addl $1, %edx addl 120(%rsp), %ecx cmpl %edx, 44(%rsp) je .L28 .L29: leal (%rsi,%rdi), %r15d testl %edi, %edi jg .L31 jmp .L32 .L28: movq (%rsp), %rdi call fclose@PLT movq 8(%rsp), %rdi call fclose@PLT movq 16(%rsp), %rdi call fclose@PLT movq 24(%rsp), %rdi call fclose@PLT addq $56, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2059: .size _Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i, .-_Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i .globl _Z46__device_stub__Z10add_sourcefffiiiifffiiiiPfS_fffiiiifffiiiiPfS_ .type _Z46__device_stub__Z10add_sourcefffiiiifffiiiiPfS_fffiiiifffiiiiPfS_, @function _Z46__device_stub__Z10add_sourcefffiiiifffiiiiPfS_fffiiiifffiiiiPfS_: .LFB2085: .cfi_startproc endbr64 subq $280, %rsp .cfi_def_cfa_offset 288 movss %xmm0, 60(%rsp) movss %xmm1, 56(%rsp) movss %xmm2, 52(%rsp) movl %edi, 48(%rsp) movl %esi, 44(%rsp) movl %edx, 40(%rsp) movl %ecx, 36(%rsp) movss %xmm3, 32(%rsp) movss %xmm4, 28(%rsp) movss %xmm5, 24(%rsp) movl %r8d, 20(%rsp) movl %r9d, 16(%rsp) movq 304(%rsp), %rax movq %rax, 8(%rsp) movq 312(%rsp), %rax movq %rax, (%rsp) movq %fs:40, %rax movq %rax, 264(%rsp) xorl %eax, %eax leaq 60(%rsp), %rax movq %rax, 128(%rsp) leaq 56(%rsp), %rax movq %rax, 136(%rsp) leaq 52(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 44(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 36(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 28(%rsp), %rax movq %rax, 192(%rsp) leaq 24(%rsp), %rax movq %rax, 200(%rsp) leaq 20(%rsp), %rax movq %rax, 208(%rsp) leaq 16(%rsp), %rax movq %rax, 216(%rsp) leaq 288(%rsp), %rax movq %rax, 224(%rsp) leaq 296(%rsp), %rax movq %rax, 232(%rsp) leaq 8(%rsp), %rax movq %rax, 240(%rsp) movq %rsp, %rax movq %rax, 248(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L43 .L39: movq 264(%rsp), %rax subq %fs:40, %rax jne .L44 addq $280, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L43: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 296 pushq 72(%rsp) .cfi_def_cfa_offset 304 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z10add_sourcefffiiiifffiiiiPfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 288 jmp .L39 .L44: call __stack_chk_fail@PLT .cfi_endproc .LFE2085: .size _Z46__device_stub__Z10add_sourcefffiiiifffiiiiPfS_fffiiiifffiiiiPfS_, .-_Z46__device_stub__Z10add_sourcefffiiiifffiiiiPfS_fffiiiifffiiiiPfS_ .globl _Z10add_sourcefffiiiifffiiiiPfS_ .type _Z10add_sourcefffiiiifffiiiiPfS_, @function _Z10add_sourcefffiiiifffiiiiPfS_: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 pushq 40(%rsp) .cfi_def_cfa_offset 24 pushq 40(%rsp) .cfi_def_cfa_offset 32 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 call _Z46__device_stub__Z10add_sourcefffiiiifffiiiiPfS_fffiiiifffiiiiPfS_ addq $40, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _Z10add_sourcefffiiiifffiiiiPfS_, .-_Z10add_sourcefffiiiifffiiiiPfS_ .globl _Z58__device_stub__Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_iiiiifffPfS_S_S_S_S_S_S_S_S_S_ .type _Z58__device_stub__Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_iiiiifffPfS_S_S_S_S_S_S_S_S_S_, @function _Z58__device_stub__Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_iiiiifffPfS_S_S_S_S_S_S_S_S_S_: .LFB2087: .cfi_startproc endbr64 subq $360, %rsp .cfi_def_cfa_offset 368 movl %edi, 124(%rsp) movl %esi, 120(%rsp) movl %edx, 116(%rsp) movl %ecx, 112(%rsp) movl %r8d, 108(%rsp) movss %xmm0, 104(%rsp) movss %xmm1, 100(%rsp) movss %xmm2, 96(%rsp) movq %r9, 88(%rsp) movq 368(%rsp), %rax movq %rax, 80(%rsp) movq 376(%rsp), %rax movq %rax, 72(%rsp) movq 384(%rsp), %rax movq %rax, 64(%rsp) movq 392(%rsp), %rax movq %rax, 56(%rsp) movq 400(%rsp), %rax movq %rax, 48(%rsp) movq 408(%rsp), %rax movq %rax, 40(%rsp) movq 416(%rsp), %rax movq %rax, 32(%rsp) movq 424(%rsp), %rax movq %rax, 24(%rsp) movq 432(%rsp), %rax movq %rax, 16(%rsp) movq 440(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 344(%rsp) xorl %eax, %eax leaq 124(%rsp), %rax movq %rax, 192(%rsp) leaq 120(%rsp), %rax movq %rax, 200(%rsp) leaq 116(%rsp), %rax movq %rax, 208(%rsp) leaq 112(%rsp), %rax movq %rax, 216(%rsp) leaq 108(%rsp), %rax movq %rax, 224(%rsp) leaq 104(%rsp), %rax movq %rax, 232(%rsp) leaq 100(%rsp), %rax movq %rax, 240(%rsp) leaq 96(%rsp), %rax movq %rax, 248(%rsp) leaq 88(%rsp), %rax movq %rax, 256(%rsp) leaq 80(%rsp), %rax movq %rax, 264(%rsp) leaq 72(%rsp), %rax movq %rax, 272(%rsp) leaq 64(%rsp), %rax movq %rax, 280(%rsp) leaq 56(%rsp), %rax movq %rax, 288(%rsp) leaq 48(%rsp), %rax movq %rax, 296(%rsp) leaq 40(%rsp), %rax movq %rax, 304(%rsp) leaq 32(%rsp), %rax movq %rax, 312(%rsp) leaq 24(%rsp), %rax movq %rax, 320(%rsp) leaq 16(%rsp), %rax movq %rax, 328(%rsp) leaq 8(%rsp), %rax movq %rax, 336(%rsp) movl $1, 144(%rsp) movl $1, 148(%rsp) movl $1, 152(%rsp) movl $1, 156(%rsp) movl $1, 160(%rsp) movl $1, 164(%rsp) leaq 136(%rsp), %rcx leaq 128(%rsp), %rdx leaq 156(%rsp), %rsi leaq 144(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L51 .L47: movq 344(%rsp), %rax subq %fs:40, %rax jne .L52 addq $360, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L51: .cfi_restore_state pushq 136(%rsp) .cfi_def_cfa_offset 376 pushq 136(%rsp) .cfi_def_cfa_offset 384 leaq 208(%rsp), %r9 movq 172(%rsp), %rcx movl 180(%rsp), %r8d movq 160(%rsp), %rsi movl 168(%rsp), %edx leaq _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 368 jmp .L47 .L52: call __stack_chk_fail@PLT .cfi_endproc .LFE2087: .size _Z58__device_stub__Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_iiiiifffPfS_S_S_S_S_S_S_S_S_S_, .-_Z58__device_stub__Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_iiiiifffPfS_S_S_S_S_S_S_S_S_S_ .globl _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .type _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_, @function _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_: .LFB2088: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 pushq 88(%rsp) .cfi_def_cfa_offset 24 pushq 88(%rsp) .cfi_def_cfa_offset 32 pushq 88(%rsp) .cfi_def_cfa_offset 40 pushq 88(%rsp) .cfi_def_cfa_offset 48 pushq 88(%rsp) .cfi_def_cfa_offset 56 pushq 88(%rsp) .cfi_def_cfa_offset 64 pushq 88(%rsp) .cfi_def_cfa_offset 72 pushq 88(%rsp) .cfi_def_cfa_offset 80 pushq 88(%rsp) .cfi_def_cfa_offset 88 pushq 88(%rsp) .cfi_def_cfa_offset 96 call _Z58__device_stub__Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_iiiiifffPfS_S_S_S_S_S_S_S_S_S_ addq $88, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2088: .size _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_, .-_Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .globl _Z84__device_stub__Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiibiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .type _Z84__device_stub__Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiibiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib, @function _Z84__device_stub__Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiibiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib: .LFB2089: .cfi_startproc endbr64 subq $536, %rsp .cfi_def_cfa_offset 544 movl %edi, 188(%rsp) movl %esi, 184(%rsp) movl %edx, 180(%rsp) movl %ecx, 176(%rsp) movss %xmm0, 172(%rsp) movss %xmm1, 168(%rsp) movss %xmm2, 164(%rsp) movq %r8, 152(%rsp) movq %r9, 144(%rsp) movq 544(%rsp), %rax movq %rax, 136(%rsp) movq 552(%rsp), %rax movq %rax, 128(%rsp) movq 560(%rsp), %rax movq %rax, 120(%rsp) movq 576(%rsp), %rax movq %rax, 112(%rsp) movq 584(%rsp), %rax movq %rax, 104(%rsp) movq 592(%rsp), %rax movq %rax, 96(%rsp) movq 600(%rsp), %rax movq %rax, 88(%rsp) movq 608(%rsp), %rax movq %rax, 80(%rsp) movq 616(%rsp), %rax movq %rax, 72(%rsp) movq 624(%rsp), %rax movq %rax, 64(%rsp) movq 632(%rsp), %rax movq %rax, 56(%rsp) movq 640(%rsp), %rax movq %rax, 48(%rsp) movq 648(%rsp), %rax movq %rax, 40(%rsp) movq 656(%rsp), %rax movq %rax, 32(%rsp) movq 664(%rsp), %rax movq %rax, 24(%rsp) movq 672(%rsp), %rax movq %rax, 16(%rsp) movq 680(%rsp), %rax movq %rax, 8(%rsp) movq 688(%rsp), %rax movq %rax, (%rsp) movl 728(%rsp), %eax movb %al, 160(%rsp) movq %fs:40, %rax movq %rax, 520(%rsp) xorl %eax, %eax leaq 188(%rsp), %rax movq %rax, 256(%rsp) leaq 184(%rsp), %rax movq %rax, 264(%rsp) leaq 180(%rsp), %rax movq %rax, 272(%rsp) leaq 176(%rsp), %rax movq %rax, 280(%rsp) leaq 172(%rsp), %rax movq %rax, 288(%rsp) leaq 168(%rsp), %rax movq %rax, 296(%rsp) leaq 164(%rsp), %rax movq %rax, 304(%rsp) leaq 152(%rsp), %rax movq %rax, 312(%rsp) leaq 144(%rsp), %rax movq %rax, 320(%rsp) leaq 136(%rsp), %rax movq %rax, 328(%rsp) leaq 128(%rsp), %rax movq %rax, 336(%rsp) leaq 120(%rsp), %rax movq %rax, 344(%rsp) leaq 568(%rsp), %rax movq %rax, 352(%rsp) leaq 112(%rsp), %rax movq %rax, 360(%rsp) leaq 104(%rsp), %rax movq %rax, 368(%rsp) leaq 96(%rsp), %rax movq %rax, 376(%rsp) leaq 88(%rsp), %rax movq %rax, 384(%rsp) leaq 80(%rsp), %rax movq %rax, 392(%rsp) leaq 72(%rsp), %rax movq %rax, 400(%rsp) leaq 64(%rsp), %rax movq %rax, 408(%rsp) leaq 56(%rsp), %rax movq %rax, 416(%rsp) leaq 48(%rsp), %rax movq %rax, 424(%rsp) leaq 40(%rsp), %rax movq %rax, 432(%rsp) leaq 32(%rsp), %rax movq %rax, 440(%rsp) leaq 24(%rsp), %rax movq %rax, 448(%rsp) leaq 16(%rsp), %rax movq %rax, 456(%rsp) leaq 8(%rsp), %rax movq %rax, 464(%rsp) movq %rsp, %rax movq %rax, 472(%rsp) leaq 696(%rsp), %rax movq %rax, 480(%rsp) leaq 704(%rsp), %rax movq %rax, 488(%rsp) leaq 712(%rsp), %rax movq %rax, 496(%rsp) leaq 720(%rsp), %rax movq %rax, 504(%rsp) leaq 160(%rsp), %rax movq %rax, 512(%rsp) movl $1, 208(%rsp) movl $1, 212(%rsp) movl $1, 216(%rsp) movl $1, 220(%rsp) movl $1, 224(%rsp) movl $1, 228(%rsp) leaq 200(%rsp), %rcx leaq 192(%rsp), %rdx leaq 220(%rsp), %rsi leaq 208(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L59 .L55: movq 520(%rsp), %rax subq %fs:40, %rax jne .L60 addq $536, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L59: .cfi_restore_state pushq 200(%rsp) .cfi_def_cfa_offset 552 pushq 200(%rsp) .cfi_def_cfa_offset 560 leaq 272(%rsp), %r9 movq 236(%rsp), %rcx movl 244(%rsp), %r8d movq 224(%rsp), %rsi movl 232(%rsp), %edx leaq _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 544 jmp .L55 .L60: call __stack_chk_fail@PLT .cfi_endproc .LFE2089: .size _Z84__device_stub__Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiibiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib, .-_Z84__device_stub__Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiibiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .globl _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .type _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib, @function _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib: .LFB2090: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movzbl 200(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 200(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 200(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 200(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 movl 200(%rsp), %eax pushq %rax .cfi_def_cfa_offset 56 pushq 200(%rsp) .cfi_def_cfa_offset 64 pushq 200(%rsp) .cfi_def_cfa_offset 72 pushq 200(%rsp) .cfi_def_cfa_offset 80 pushq 200(%rsp) .cfi_def_cfa_offset 88 pushq 200(%rsp) .cfi_def_cfa_offset 96 pushq 200(%rsp) .cfi_def_cfa_offset 104 pushq 200(%rsp) .cfi_def_cfa_offset 112 pushq 200(%rsp) .cfi_def_cfa_offset 120 pushq 200(%rsp) .cfi_def_cfa_offset 128 pushq 200(%rsp) .cfi_def_cfa_offset 136 pushq 200(%rsp) .cfi_def_cfa_offset 144 pushq 200(%rsp) .cfi_def_cfa_offset 152 pushq 200(%rsp) .cfi_def_cfa_offset 160 pushq 200(%rsp) .cfi_def_cfa_offset 168 pushq 200(%rsp) .cfi_def_cfa_offset 176 movl 200(%rsp), %eax pushq %rax .cfi_def_cfa_offset 184 pushq 200(%rsp) .cfi_def_cfa_offset 192 pushq 200(%rsp) .cfi_def_cfa_offset 200 pushq 200(%rsp) .cfi_def_cfa_offset 208 call _Z84__device_stub__Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiibiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib addq $200, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2090: .size _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib, .-_Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .globl _Z30__device_stub__Z6get_d0ffiiiPfffiiiPf .type _Z30__device_stub__Z6get_d0ffiiiPfffiiiPf, @function _Z30__device_stub__Z6get_d0ffiiiPfffiiiPf: .LFB2091: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movss %xmm0, 28(%rsp) movss %xmm1, 24(%rsp) movl %edi, 20(%rsp) movl %esi, 16(%rsp) movl %edx, 12(%rsp) movq %rcx, (%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 24(%rsp), %rax movq %rax, 104(%rsp) leaq 20(%rsp), %rax movq %rax, 112(%rsp) leaq 16(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) movq %rsp, %rax movq %rax, 136(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L67 .L63: movq 152(%rsp), %rax subq %fs:40, %rax jne .L68 addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L67: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 184 pushq 40(%rsp) .cfi_def_cfa_offset 192 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6get_d0ffiiiPf(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 176 jmp .L63 .L68: call __stack_chk_fail@PLT .cfi_endproc .LFE2091: .size _Z30__device_stub__Z6get_d0ffiiiPfffiiiPf, .-_Z30__device_stub__Z6get_d0ffiiiPfffiiiPf .globl _Z6get_d0ffiiiPf .type _Z6get_d0ffiiiPf, @function _Z6get_d0ffiiiPf: .LFB2092: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z6get_d0ffiiiPfffiiiPf addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2092: .size _Z6get_d0ffiiiPf, .-_Z6get_d0ffiiiPf .globl _Z42__device_stub__Z13initial_coffefiPfS_S_S_ifiPfS_S_S_i .type _Z42__device_stub__Z13initial_coffefiPfS_S_S_ifiPfS_S_S_i, @function _Z42__device_stub__Z13initial_coffefiPfS_S_S_ifiPfS_S_S_i: .LFB2093: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movss %xmm0, 44(%rsp) movl %edi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movq %r8, 8(%rsp) movl %r9d, 4(%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 44(%rsp), %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rax movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 16(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) leaq 4(%rsp), %rax movq %rax, 160(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L75 .L71: movq 168(%rsp), %rax subq %fs:40, %rax jne .L76 addq $184, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L75: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 200 pushq 56(%rsp) .cfi_def_cfa_offset 208 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z13initial_coffefiPfS_S_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L71 .L76: call __stack_chk_fail@PLT .cfi_endproc .LFE2093: .size _Z42__device_stub__Z13initial_coffefiPfS_S_S_ifiPfS_S_S_i, .-_Z42__device_stub__Z13initial_coffefiPfS_S_S_ifiPfS_S_S_i .globl _Z13initial_coffefiPfS_S_S_i .type _Z13initial_coffefiPfS_S_S_i, @function _Z13initial_coffefiPfS_S_S_i: .LFB2094: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z42__device_stub__Z13initial_coffefiPfS_S_S_ifiPfS_S_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2094: .size _Z13initial_coffefiPfS_S_S_i, .-_Z13initial_coffefiPfS_S_S_i .globl _Z40__device_stub__Z11shot_recordiiiiiiiPfS_iiiiiiiPfS_ .type _Z40__device_stub__Z11shot_recordiiiiiiiPfS_iiiiiiiPfS_, @function _Z40__device_stub__Z11shot_recordiiiiiiiPfS_iiiiiiiPfS_: .LFB2095: .cfi_startproc endbr64 subq $200, %rsp .cfi_def_cfa_offset 208 movl %edi, 44(%rsp) movl %esi, 40(%rsp) movl %edx, 36(%rsp) movl %ecx, 32(%rsp) movl %r8d, 28(%rsp) movl %r9d, 24(%rsp) movq 216(%rsp), %rax movq %rax, 16(%rsp) movq 224(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax leaq 44(%rsp), %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rax movq %rax, 120(%rsp) leaq 36(%rsp), %rax movq %rax, 128(%rsp) leaq 32(%rsp), %rax movq %rax, 136(%rsp) leaq 28(%rsp), %rax movq %rax, 144(%rsp) leaq 24(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 16(%rsp), %rax movq %rax, 168(%rsp) leaq 8(%rsp), %rax movq %rax, 176(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L83 .L79: movq 184(%rsp), %rax subq %fs:40, %rax jne .L84 addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L83: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 216 pushq 56(%rsp) .cfi_def_cfa_offset 224 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z11shot_recordiiiiiiiPfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 208 jmp .L79 .L84: call __stack_chk_fail@PLT .cfi_endproc .LFE2095: .size _Z40__device_stub__Z11shot_recordiiiiiiiPfS_iiiiiiiPfS_, .-_Z40__device_stub__Z11shot_recordiiiiiiiPfS_iiiiiiiPfS_ .globl _Z11shot_recordiiiiiiiPfS_ .type _Z11shot_recordiiiiiiiPfS_, @function _Z11shot_recordiiiiiiiPfS_: .LFB2096: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 pushq 40(%rsp) .cfi_def_cfa_offset 32 pushq 40(%rsp) .cfi_def_cfa_offset 40 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 call _Z40__device_stub__Z11shot_recordiiiiiiiPfS_iiiiiiiPfS_ addq $40, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2096: .size _Z11shot_recordiiiiiiiPfS_, .-_Z11shot_recordiiiiiiiPfS_ .section .rodata.str1.1 .LC5: .string "wb" .LC6: .string "Failed to initialize device!" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC7: .string "Failed to allocate memory for variables!" .align 8 .LC9: .string "--------------------------------------------------------\n" .section .rodata.str1.1 .LC10: .string "--- \n" .LC11: .string "--- IS=%3d \n" .LC12: .string "--- is===%d it===%d\n" .section .rodata.str1.8 .align 8 .LC17: .string "--- The forward is over \n" .section .rodata.str1.1 .LC18: .string "--- Complete!!!!!!!!! \n" .LC20: .string "total %d shots: %f (s)\n" .text .globl main .type main, @function main: .LFB2060: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $1832, %rsp .cfi_def_cfa_offset 1888 movq %fs:40, %rax movq %rax, 1816(%rsp) xorl %eax, %eax movabsq $8529664258503501940, %rax movabsq $3701731506173996133, %rdx movq %rax, 272(%rsp) movq %rdx, 280(%rsp) movabsq $127961641398320, %rax movl $0, %edx movq %rax, 288(%rsp) movq %rdx, 296(%rsp) movq $0, 304(%rsp) movq $0, 312(%rsp) movq $0, 320(%rsp) movq $0, 328(%rsp) movq $0, 336(%rsp) movq $0, 344(%rsp) movq $0, 352(%rsp) movq $0, 360(%rsp) movq $0, 368(%rsp) movq $0, 376(%rsp) movq $0, 384(%rsp) movq $0, 392(%rsp) movq $0, 400(%rsp) movq $0, 408(%rsp) movq $0, 416(%rsp) movq $0, 424(%rsp) movq $0, 432(%rsp) movq $0, 440(%rsp) movq $0, 448(%rsp) movq $0, 456(%rsp) movq $0, 464(%rsp) movq $0, 472(%rsp) movq $0, 480(%rsp) movq $0, 488(%rsp) movq $0, 496(%rsp) movq $0, 504(%rsp) movq $0, 506(%rsp) movq $0, 514(%rsp) movabsq $7304685159858727028, %rax movabsq $3990029219712824176, %rdx movq %rax, 528(%rsp) movq %rdx, 536(%rsp) movabsq $7218760236299923761, %rax movl $29793, %edx movq %rax, 544(%rsp) movq %rdx, 552(%rsp) movq $0, 560(%rsp) movq $0, 568(%rsp) movq $0, 576(%rsp) movq $0, 584(%rsp) movq $0, 592(%rsp) movq $0, 600(%rsp) movq $0, 608(%rsp) movq $0, 616(%rsp) movq $0, 624(%rsp) movq $0, 632(%rsp) movq $0, 640(%rsp) movq $0, 648(%rsp) movq $0, 656(%rsp) movq $0, 664(%rsp) movq $0, 672(%rsp) movq $0, 680(%rsp) movq $0, 688(%rsp) movq $0, 696(%rsp) movq $0, 704(%rsp) movq $0, 712(%rsp) movq $0, 720(%rsp) movq $0, 728(%rsp) movq $0, 736(%rsp) movq $0, 744(%rsp) movq $0, 752(%rsp) movq $0, 760(%rsp) movq $0, 762(%rsp) movq $0, 770(%rsp) movabsq $7232627565820799092, %rax movabsq $3544675264513731685, %rdx movq %rax, 784(%rsp) movq %rdx, 792(%rsp) movabsq $8386094130680312671, %rax movl $0, %edx movq %rax, 800(%rsp) movq %rdx, 808(%rsp) movq $0, 816(%rsp) movq $0, 824(%rsp) movq $0, 832(%rsp) movq $0, 840(%rsp) movq $0, 848(%rsp) movq $0, 856(%rsp) movq $0, 864(%rsp) movq $0, 872(%rsp) movq $0, 880(%rsp) movq $0, 888(%rsp) movq $0, 896(%rsp) movq $0, 904(%rsp) movq $0, 912(%rsp) movq $0, 920(%rsp) movq $0, 928(%rsp) movq $0, 936(%rsp) movq $0, 944(%rsp) movq $0, 952(%rsp) movq $0, 960(%rsp) movq $0, 968(%rsp) movq $0, 976(%rsp) movq $0, 984(%rsp) movq $0, 992(%rsp) movq $0, 1000(%rsp) movq $0, 1008(%rsp) movq $0, 1016(%rsp) movq $0, 1018(%rsp) movq $0, 1026(%rsp) movabsq $8385549070427646068, %rcx movabsq $3544675264513729896, %rbx movq %rcx, 1040(%rsp) movq %rbx, 1048(%rsp) movq %rax, 1056(%rsp) movq %rdx, 1064(%rsp) movq $0, 1072(%rsp) movq $0, 1080(%rsp) movq $0, 1088(%rsp) movq $0, 1096(%rsp) movq $0, 1104(%rsp) movq $0, 1112(%rsp) movq $0, 1120(%rsp) movq $0, 1128(%rsp) movq $0, 1136(%rsp) movq $0, 1144(%rsp) movq $0, 1152(%rsp) movq $0, 1160(%rsp) movq $0, 1168(%rsp) movq $0, 1176(%rsp) movq $0, 1184(%rsp) movq $0, 1192(%rsp) movq $0, 1200(%rsp) movq $0, 1208(%rsp) movq $0, 1216(%rsp) movq $0, 1224(%rsp) movq $0, 1232(%rsp) movq $0, 1240(%rsp) movq $0, 1248(%rsp) movq $0, 1256(%rsp) movq $0, 1264(%rsp) movq $0, 1272(%rsp) movq $0, 1274(%rsp) movq $0, 1282(%rsp) movabsq $8313491476389718132, %rax movabsq $8391171981113061224, %rdx movq %rax, 1296(%rsp) movq %rdx, 1304(%rsp) movabsq $8386094131573449313, %rax movl $0, %edx movq %rax, 1312(%rsp) movq %rdx, 1320(%rsp) movq $0, 1328(%rsp) movq $0, 1336(%rsp) movq $0, 1344(%rsp) movq $0, 1352(%rsp) movq $0, 1360(%rsp) movq $0, 1368(%rsp) movq $0, 1376(%rsp) movq $0, 1384(%rsp) movq $0, 1392(%rsp) movq $0, 1400(%rsp) movq $0, 1408(%rsp) movq $0, 1416(%rsp) movq $0, 1424(%rsp) movq $0, 1432(%rsp) movq $0, 1440(%rsp) movq $0, 1448(%rsp) movq $0, 1456(%rsp) movq $0, 1464(%rsp) movq $0, 1472(%rsp) movq $0, 1480(%rsp) movq $0, 1488(%rsp) movq $0, 1496(%rsp) movq $0, 1504(%rsp) movq $0, 1512(%rsp) movq $0, 1520(%rsp) movq $0, 1528(%rsp) movq $0, 1530(%rsp) movq $0, 1538(%rsp) movabsq $8313491476389718132, %rcx movabsq $8391171981112795502, %rbx movq %rcx, 1552(%rsp) movq %rbx, 1560(%rsp) movq %rax, 1568(%rsp) movq %rdx, 1576(%rsp) movq $0, 1584(%rsp) movq $0, 1592(%rsp) movq $0, 1600(%rsp) movq $0, 1608(%rsp) movq $0, 1616(%rsp) movq $0, 1624(%rsp) movq $0, 1632(%rsp) movq $0, 1640(%rsp) movq $0, 1648(%rsp) movq $0, 1656(%rsp) movq $0, 1664(%rsp) movq $0, 1672(%rsp) movq $0, 1680(%rsp) movq $0, 1688(%rsp) movq $0, 1696(%rsp) movq $0, 1704(%rsp) movq $0, 1712(%rsp) movq $0, 1720(%rsp) movq $0, 1728(%rsp) movq $0, 1736(%rsp) movq $0, 1744(%rsp) movq $0, 1752(%rsp) movq $0, 1760(%rsp) movq $0, 1768(%rsp) movq $0, 1776(%rsp) movq $0, 1784(%rsp) movq $0, 1786(%rsp) movq $0, 1794(%rsp) leaq 1296(%rsp), %rdi leaq .LC5(%rip), %rbx movq %rbx, %rsi call fopen@PLT movq %rax, 8(%rsp) leaq 1552(%rsp), %rdi movq %rbx, %rsi call fopen@PLT movq %rax, %r13 movl $1120000, %edi call malloc@PLT movq %rax, %r15 movl $1120000, %edi call malloc@PLT movq %rax, %r12 movl $1120000, %edi call malloc@PLT movq %rax, %r14 movl $1120000, %edi call malloc@PLT movq %rax, %rbp movl $1922400, %edi call malloc@PLT movq %rax, 16(%rsp) leaq 1040(%rsp), %rcx leaq 784(%rsp), %rdx leaq 528(%rsp), %rsi leaq 272(%rsp), %rdi subq $8, %rsp .cfi_def_cfa_offset 1896 pushq $50 .cfi_def_cfa_offset 1904 pushq %rbp .cfi_def_cfa_offset 1912 pushq %r14 .cfi_def_cfa_offset 1920 pushq %r12 .cfi_def_cfa_offset 1928 pushq %r15 .cfi_def_cfa_offset 1936 pushq $400 .cfi_def_cfa_offset 1944 pushq $700 .cfi_def_cfa_offset 1952 movl $300, %r9d movl $600, %r8d call _Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i addq $64, %rsp .cfi_def_cfa_offset 1888 movq %r12, %r9 movl $50, %r8d movl $400, %ecx movl $700, %edx movl $300, %esi movl $600, %edi call _Z6pad_vviiiiiPf movq %r14, %r9 movl $50, %r8d movl $400, %ecx movl $700, %edx movl $300, %esi movl $600, %edi call _Z6pad_vviiiiiPf movq %r15, %r9 movl $50, %r8d movl $400, %ecx movl $700, %edx movl $300, %esi movl $600, %edi call _Z6pad_vviiiiiPf movq %rbp, %r9 movl $50, %r8d movl $400, %ecx movl $700, %edx movl $300, %esi movl $600, %edi call _Z6pad_vviiiiiPf movl $0, %edi call cudaSetDevice@PLT leaq .LC6(%rip), %rdi call _Z15check_gpu_errorPKc leaq 32(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 40(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 48(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 56(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT movl $1, %ecx movl $1120000, %edx movq %r15, %rsi movq 32(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $1120000, %edx movq %r12, %rsi movq 40(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $1120000, %edx movq %r14, %rsi movq 48(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $1120000, %edx movq %rbp, %rsi movq 56(%rsp), %rdi call cudaMemcpy@PLT leaq 64(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 72(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 112(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 120(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 160(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 168(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 80(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 96(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 128(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 144(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 88(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 104(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 136(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 152(%rsp), %rdi movl $1120000, %esi call cudaMalloc@PLT leaq 184(%rsp), %rdi movl $2800, %esi call cudaMalloc@PLT leaq 192(%rsp), %rdi movl $2800, %esi call cudaMalloc@PLT leaq 200(%rsp), %rdi movl $1600, %esi call cudaMalloc@PLT leaq 208(%rsp), %rdi movl $1600, %esi call cudaMalloc@PLT leaq 216(%rsp), %rdi movl $2800, %esi call cudaMalloc@PLT leaq 224(%rsp), %rdi movl $2800, %esi call cudaMalloc@PLT leaq 232(%rsp), %rdi movl $1600, %esi call cudaMalloc@PLT leaq 240(%rsp), %rdi movl $1600, %esi call cudaMalloc@PLT leaq 176(%rsp), %rdi movl $1922400, %esi call cudaMalloc@PLT leaq .LC7(%rip), %rdi call _Z15check_gpu_errorPKc movl $1, 260(%rsp) movl $1, 264(%rsp) movl $1, 268(%rsp) movl $1, 248(%rsp) movl $1, 252(%rsp) movl $1, 256(%rsp) movl $0, %r9d movl $0, %r8d movq 260(%rsp), %rdx movl $1, %ecx movq 248(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L101 .L88: movl $512, 260(%rsp) movl $1, 264(%rsp) movl $1, 268(%rsp) movl $2, 248(%rsp) movl $1, 252(%rsp) movl $1, 256(%rsp) movl $0, %r9d movl $0, %r8d movq 260(%rsp), %rdx movl $1, %ecx movq 248(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L102 .L89: movl $512, 260(%rsp) movl $1, 264(%rsp) movl $1, 268(%rsp) movl $1, 248(%rsp) movl $1, 252(%rsp) movl $1, 256(%rsp) movl $0, %r9d movl $0, %r8d movq 260(%rsp), %rdx movl $1, %ecx movq 248(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L90 movl $50, %r9d movq 240(%rsp), %r8 movq 232(%rsp), %rcx movq 208(%rsp), %rdx movq 200(%rsp), %rsi movl $300, %edi movss .LC4(%rip), %xmm0 call _Z42__device_stub__Z13initial_coffefiPfS_S_S_ifiPfS_S_S_i .L90: leaq .LC9(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC10(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT call clock@PLT movq %rax, 24(%rsp) movl $1, %edx leaq .LC11(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1120000, %edx movl $0, %esi movq 64(%rsp), %rdi call cudaMemset@PLT movl $1120000, %edx movl $0, %esi movq 72(%rsp), %rdi call cudaMemset@PLT movl $1120000, %edx movl $0, %esi movq 112(%rsp), %rdi call cudaMemset@PLT movl $1120000, %edx movl $0, %esi movq 120(%rsp), %rdi call cudaMemset@PLT movl $1120000, %edx movl $0, %esi movq 160(%rsp), %rdi call cudaMemset@PLT movl $1120000, %edx movl $0, %esi movq 168(%rsp), %rdi call cudaMemset@PLT movl $1120000, %edx movl $0, %esi movq 80(%rsp), %rdi call cudaMemset@PLT movl $1120000, %edx movl $0, %esi movq 96(%rsp), %rdi call cudaMemset@PLT movl $1120000, %edx movl $0, %esi movq 128(%rsp), %rdi call cudaMemset@PLT movl $1120000, %edx movl $0, %esi movq 144(%rsp), %rdi call cudaMemset@PLT movl $1120000, %edx movl $0, %esi movq 88(%rsp), %rdi call cudaMemset@PLT movl $1120000, %edx movl $0, %esi movq 104(%rsp), %rdi call cudaMemset@PLT movl $1120000, %edx movl $0, %esi movq 136(%rsp), %rdi call cudaMemset@PLT movl $1120000, %edx movl $0, %esi movq 152(%rsp), %rdi call cudaMemset@PLT movl $1922400, %edx movl $0, %esi movq 176(%rsp), %rdi call cudaMemset@PLT movss .LC4(%rip), %xmm7 movss %xmm7, 4(%rsp) movl $0, %ebx jmp .L97 .L101: movq 32(%rsp), %rcx movl $50, %edx movl $400, %esi movl $700, %edi movss .LC8(%rip), %xmm1 movaps %xmm1, %xmm0 call _Z30__device_stub__Z6get_d0ffiiiPfffiiiPf jmp .L88 .L102: movl $50, %r9d movq 224(%rsp), %r8 movq 216(%rsp), %rcx movq 192(%rsp), %rdx movq 184(%rsp), %rsi movl $600, %edi movss .LC4(%rip), %xmm0 call _Z42__device_stub__Z13initial_coffefiPfS_S_S_ifiPfS_S_S_i jmp .L89 .L104: movl %ebx, %ecx movl $1, %edx leaq .LC12(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L91 .L105: pushq 168(%rsp) .cfi_def_cfa_offset 1896 pushq 168(%rsp) .cfi_def_cfa_offset 1904 pushq $0 .cfi_def_cfa_offset 1912 pushq $1 .cfi_def_cfa_offset 1920 movl $50, %r9d movl $1, %r8d movss .LC13(%rip), %xmm5 movss 36(%rsp), %xmm4 movss .LC4(%rip), %xmm3 movl $400, %ecx movl $700, %edx movl $300, %esi movl $600, %edi movss .LC14(%rip), %xmm2 movss .LC15(%rip), %xmm1 movss .LC16(%rip), %xmm0 call _Z46__device_stub__Z10add_sourcefffiiiifffiiiiPfS_fffiiiifffiiiiPfS_ addq $32, %rsp .cfi_def_cfa_offset 1888 jmp .L92 .L106: pushq 56(%rsp) .cfi_def_cfa_offset 1896 pushq 216(%rsp) .cfi_def_cfa_offset 1904 pushq 216(%rsp) .cfi_def_cfa_offset 1912 pushq 216(%rsp) .cfi_def_cfa_offset 1920 pushq 216(%rsp) .cfi_def_cfa_offset 1928 pushq 208(%rsp) .cfi_def_cfa_offset 1936 pushq 208(%rsp) .cfi_def_cfa_offset 1944 pushq 176(%rsp) .cfi_def_cfa_offset 1952 pushq 136(%rsp) .cfi_def_cfa_offset 1960 pushq 184(%rsp) .cfi_def_cfa_offset 1968 movq 144(%rsp), %r9 movss .LC8(%rip), %xmm2 movaps %xmm2, %xmm1 movss .LC4(%rip), %xmm0 movl $50, %r8d movl $400, %ecx movl $700, %edx movl $300, %esi movl $600, %edi call _Z58__device_stub__Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_iiiiifffPfS_S_S_S_S_S_S_S_S_S_ addq $80, %rsp .cfi_def_cfa_offset 1888 jmp .L93 .L107: pushq $0 .cfi_def_cfa_offset 1896 pushq $1 .cfi_def_cfa_offset 1904 pushq $140 .cfi_def_cfa_offset 1912 pushq $0 .cfi_def_cfa_offset 1920 pushq $200 .cfi_def_cfa_offset 1928 pushq 96(%rsp) .cfi_def_cfa_offset 1936 pushq 88(%rsp) .cfi_def_cfa_offset 1944 pushq 104(%rsp) .cfi_def_cfa_offset 1952 pushq 304(%rsp) .cfi_def_cfa_offset 1960 pushq 304(%rsp) .cfi_def_cfa_offset 1968 pushq 304(%rsp) .cfi_def_cfa_offset 1976 pushq 304(%rsp) .cfi_def_cfa_offset 1984 pushq 232(%rsp) .cfi_def_cfa_offset 1992 pushq 256(%rsp) .cfi_def_cfa_offset 2000 pushq 200(%rsp) .cfi_def_cfa_offset 2008 pushq 224(%rsp) .cfi_def_cfa_offset 2016 pushq 256(%rsp) .cfi_def_cfa_offset 2024 pushq 280(%rsp) .cfi_def_cfa_offset 2032 pushq 224(%rsp) .cfi_def_cfa_offset 2040 pushq 248(%rsp) .cfi_def_cfa_offset 2048 pushq $50 .cfi_def_cfa_offset 2056 pushq 200(%rsp) .cfi_def_cfa_offset 2064 pushq 344(%rsp) .cfi_def_cfa_offset 2072 pushq 344(%rsp) .cfi_def_cfa_offset 2080 movq 312(%rsp), %r9 movq 264(%rsp), %r8 movss .LC8(%rip), %xmm2 movaps %xmm2, %xmm1 movss .LC4(%rip), %xmm0 movl $400, %ecx movl $700, %edx movl $300, %esi movl $600, %edi call _Z84__device_stub__Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiibiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib addq $192, %rsp .cfi_def_cfa_offset 1888 jmp .L94 .L108: subq $8, %rsp .cfi_def_cfa_offset 1896 pushq 184(%rsp) .cfi_def_cfa_offset 1904 pushq 176(%rsp) .cfi_def_cfa_offset 1912 pushq $801 .cfi_def_cfa_offset 1920 movl %ebx, %r9d movl $50, %r8d movl $300, %ecx movl $600, %edx movl $400, %esi movl $700, %edi call _Z40__device_stub__Z11shot_recordiiiiiiiPfS_iiiiiiiPfS_ addq $32, %rsp .cfi_def_cfa_offset 1888 jmp .L95 .L96: addl $1, %ebx movss 4(%rsp), %xmm6 addss .LC4(%rip), %xmm6 movss %xmm6, 4(%rsp) cmpl $801, %ebx je .L103 .L97: movslq %ebx, %rax imulq $274877907, %rax, %rax sarq $38, %rax movl %ebx, %edx sarl $31, %edx subl %edx, %eax imull $1000, %eax, %eax cmpl %eax, %ebx je .L104 .L91: movl $1, 260(%rsp) movl $1, 264(%rsp) movl $1, 268(%rsp) movl $1, 248(%rsp) movl $1, 252(%rsp) movl $1, 256(%rsp) movl $0, %r9d movl $0, %r8d movq 260(%rsp), %rdx movl $1, %ecx movq 248(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L105 .L92: movl $512, 260(%rsp) movl $1, 264(%rsp) movl $1, 268(%rsp) movl $547, 248(%rsp) movl $1, 252(%rsp) movl $1, 256(%rsp) movl $0, %r9d movl $0, %r8d movq 260(%rsp), %rdx movl $1, %ecx movq 248(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L106 .L93: movl $512, 260(%rsp) movl $1, 264(%rsp) movl $1, 268(%rsp) movl $547, 248(%rsp) movl $1, 252(%rsp) movl $1, 256(%rsp) movl $0, %r9d movl $0, %r8d movq 260(%rsp), %rdx movl $1, %ecx movq 248(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L107 .L94: movq 72(%rsp), %rax movq %rax, 64(%rsp) movq 120(%rsp), %rax movq %rax, 112(%rsp) movq 96(%rsp), %rax movq %rax, 80(%rsp) movq 144(%rsp), %rax movq %rax, 128(%rsp) movq 104(%rsp), %rax movq %rax, 88(%rsp) movq 152(%rsp), %rax movq %rax, 136(%rsp) movl $512, 260(%rsp) movl $1, 264(%rsp) movl $1, 268(%rsp) movl $2, 248(%rsp) movl $1, 252(%rsp) movl $1, 256(%rsp) movl $0, %r9d movl $0, %r8d movq 260(%rsp), %rdx movl $1, %ecx movq 248(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L108 .L95: movslq %ebx, %rax imulq $1374389535, %rax, %rax sarq $37, %rax movl %ebx, %edx sarl $31, %edx subl %edx, %eax imull $100, %eax, %eax cmpl %eax, %ebx jne .L96 testl %ebx, %ebx je .L96 movl $2, %ecx movl $1120000, %edx movq 160(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT movq %r13, %rcx movl $280000, %edx movl $4, %esi movq %r12, %rdi call fwrite@PLT jmp .L96 .L103: movl $2, %ecx movl $1922400, %edx movq 176(%rsp), %rsi movq 16(%rsp), %rbx movq %rbx, %rdi call cudaMemcpy@PLT movl $0, %edx movl $0, %esi movq 8(%rsp), %rdi call fseek@PLT movq 8(%rsp), %rcx movl $480600, %edx movl $4, %esi movq %rbx, 16(%rsp) movq %rbx, %rdi call fwrite@PLT call clock@PLT movq %rax, %rbx leaq .LC17(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC18(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 24(%rsp), %rax subq %rax, %rbx pxor %xmm0, %xmm0 cvtsi2ssq %rbx, %xmm0 divss .LC19(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movl $1, %edx leaq .LC20(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq %r13, %rdi call fclose@PLT movq 8(%rsp), %rdi call fclose@PLT movq 184(%rsp), %rdi call cudaFree@PLT movq 192(%rsp), %rdi call cudaFree@PLT movq 200(%rsp), %rdi call cudaFree@PLT movq 208(%rsp), %rdi call cudaFree@PLT movq 216(%rsp), %rdi call cudaFree@PLT movq 224(%rsp), %rdi call cudaFree@PLT movq 232(%rsp), %rdi call cudaFree@PLT movq 240(%rsp), %rdi call cudaFree@PLT movq 64(%rsp), %rdi call cudaFree@PLT movq 72(%rsp), %rdi call cudaFree@PLT movq 112(%rsp), %rdi call cudaFree@PLT movq 120(%rsp), %rdi call cudaFree@PLT movq 160(%rsp), %rdi call cudaFree@PLT movq 168(%rsp), %rdi call cudaFree@PLT movq 80(%rsp), %rdi call cudaFree@PLT movq 96(%rsp), %rdi call cudaFree@PLT movq 128(%rsp), %rdi call cudaFree@PLT movq 144(%rsp), %rdi call cudaFree@PLT movq 88(%rsp), %rdi call cudaFree@PLT movq 104(%rsp), %rdi call cudaFree@PLT movq 136(%rsp), %rdi call cudaFree@PLT movq 152(%rsp), %rdi call cudaFree@PLT movq 176(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq 48(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rdi call cudaFree@PLT movq %r15, %rdi call free@PLT movq %r12, %rdi call free@PLT movq %r14, %rdi call free@PLT movq %rbp, %rdi call free@PLT movq 16(%rsp), %rdi call free@PLT movq 1816(%rsp), %rax subq %fs:40, %rax jne .L109 movl $0, %eax addq $1832, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L109: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2060: .size main, .-main .globl _Z52__device_stub__Z15mute_directwaveiiffffiiiiPfS_S_S_iiiffffiiiiPfS_S_S_i .type _Z52__device_stub__Z15mute_directwaveiiffffiiiiPfS_S_S_iiiffffiiiiPfS_S_S_i, @function _Z52__device_stub__Z15mute_directwaveiiffffiiiiPfS_S_S_iiiffffiiiiPfS_S_S_i: .LFB2097: .cfi_startproc endbr64 subq $280, %rsp .cfi_def_cfa_offset 288 movl %edi, 76(%rsp) movl %esi, 72(%rsp) movss %xmm0, 68(%rsp) movss %xmm1, 64(%rsp) movss %xmm2, 60(%rsp) movss %xmm3, 56(%rsp) movl %edx, 52(%rsp) movl %ecx, 48(%rsp) movl %r8d, 44(%rsp) movl %r9d, 40(%rsp) movq 288(%rsp), %rax movq %rax, 32(%rsp) movq 296(%rsp), %rax movq %rax, 24(%rsp) movq 304(%rsp), %rax movq %rax, 16(%rsp) movq 312(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 264(%rsp) xorl %eax, %eax leaq 76(%rsp), %rax movq %rax, 144(%rsp) leaq 72(%rsp), %rax movq %rax, 152(%rsp) leaq 68(%rsp), %rax movq %rax, 160(%rsp) leaq 64(%rsp), %rax movq %rax, 168(%rsp) leaq 60(%rsp), %rax movq %rax, 176(%rsp) leaq 56(%rsp), %rax movq %rax, 184(%rsp) leaq 52(%rsp), %rax movq %rax, 192(%rsp) leaq 48(%rsp), %rax movq %rax, 200(%rsp) leaq 44(%rsp), %rax movq %rax, 208(%rsp) leaq 40(%rsp), %rax movq %rax, 216(%rsp) leaq 32(%rsp), %rax movq %rax, 224(%rsp) leaq 24(%rsp), %rax movq %rax, 232(%rsp) leaq 16(%rsp), %rax movq %rax, 240(%rsp) leaq 8(%rsp), %rax movq %rax, 248(%rsp) leaq 320(%rsp), %rax movq %rax, 256(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) movl $1, 104(%rsp) movl $1, 108(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) leaq 88(%rsp), %rcx leaq 80(%rsp), %rdx leaq 108(%rsp), %rsi leaq 96(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L114 .L110: movq 264(%rsp), %rax subq %fs:40, %rax jne .L115 addq $280, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L114: .cfi_restore_state pushq 88(%rsp) .cfi_def_cfa_offset 296 pushq 88(%rsp) .cfi_def_cfa_offset 304 leaq 160(%rsp), %r9 movq 124(%rsp), %rcx movl 132(%rsp), %r8d movq 112(%rsp), %rsi movl 120(%rsp), %edx leaq _Z15mute_directwaveiiffffiiiiPfS_S_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 288 jmp .L110 .L115: call __stack_chk_fail@PLT .cfi_endproc .LFE2097: .size _Z52__device_stub__Z15mute_directwaveiiffffiiiiPfS_S_S_iiiffffiiiiPfS_S_S_i, .-_Z52__device_stub__Z15mute_directwaveiiffffiiiiPfS_S_S_iiiffffiiiiPfS_S_S_i .globl _Z15mute_directwaveiiffffiiiiPfS_S_S_i .type _Z15mute_directwaveiiffffiiiiPfS_S_S_i, @function _Z15mute_directwaveiiffffiiiiPfS_S_S_i: .LFB2098: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 movl 56(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 pushq 56(%rsp) .cfi_def_cfa_offset 40 pushq 56(%rsp) .cfi_def_cfa_offset 48 pushq 56(%rsp) .cfi_def_cfa_offset 56 pushq 56(%rsp) .cfi_def_cfa_offset 64 call _Z52__device_stub__Z15mute_directwaveiiffffiiiiPfS_S_S_iiiffffiiiiPfS_S_S_i addq $56, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2098: .size _Z15mute_directwaveiiffffiiiiPfS_S_S_i, .-_Z15mute_directwaveiiffffiiiiPfS_S_S_i .section .rodata.str1.8 .align 8 .LC21: .string "_Z15mute_directwaveiiffffiiiiPfS_S_S_i" .section .rodata.str1.1 .LC22: .string "_Z11shot_recordiiiiiiiPfS_" .LC23: .string "_Z13initial_coffefiPfS_S_S_i" .LC24: .string "_Z6get_d0ffiiiPf" .section .rodata.str1.8 .align 8 .LC25: .string "_Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib" .align 8 .LC26: .string "_Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_" .align 8 .LC27: .string "_Z10add_sourcefffiiiifffiiiiPfS_" .section .rodata.str1.1 .LC28: .string "d0" .LC29: .string "c" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2100: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC21(%rip), %rdx movq %rdx, %rcx leaq _Z15mute_directwaveiiffffiiiiPfS_S_S_i(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC22(%rip), %rdx movq %rdx, %rcx leaq _Z11shot_recordiiiiiiiPfS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC23(%rip), %rdx movq %rdx, %rcx leaq _Z13initial_coffefiPfS_S_S_i(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC24(%rip), %rdx movq %rdx, %rcx leaq _Z6get_d0ffiiiPf(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC25(%rip), %rdx movq %rdx, %rcx leaq _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC26(%rip), %rdx movq %rdx, %rcx leaq _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC27(%rip), %rdx movq %rdx, %rcx leaq _Z10add_sourcefffiiiifffiiiiPfS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC28(%rip), %rdx movq %rdx, %rcx leaq _ZL2d0(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $16, %r9d movl $0, %r8d leaq .LC29(%rip), %rdx movq %rdx, %rcx leaq _ZL1c(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2100: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL1c .comm _ZL1c,16,16 .local _ZL2d0 .comm _ZL2d0,4,4 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC3: .long -1572588527 .long 1066524486 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC4: .long 973279855 .align 4 .LC8: .long 1084227584 .align 4 .LC13: .long 1109393408 .align 4 .LC14: .long 1124859904 .align 4 .LC15: .long 1128792064 .align 4 .LC16: .long 1092616192 .align 4 .LC19: .long 1232348160 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z10add_sourcefffiiiifffiiiiPfS_ ; -- Begin function _Z10add_sourcefffiiiifffiiiiPfS_ .globl _Z10add_sourcefffiiiifffiiiiPfS_ .p2align 8 .type _Z10add_sourcefffiiiifffiiiiPfS_,@function _Z10add_sourcefffiiiifffiiiiPfS_: ; @_Z10add_sourcefffiiiifffiiiiPfS_ ; %bb.0: s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x20 s_load_b32 s2, s[0:1], 0x28 s_waitcnt lgkmcnt(0) v_div_scale_f32 v0, null, s5, s5, 1.0 s_cmp_lt_i32 s2, 2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f32_e32 v1, v0 s_waitcnt_depctr 0xfff v_fma_f32 v2, -v0, v1, 1.0 v_fmac_f32_e32 v1, v2, v1 v_div_scale_f32 v2, vcc_lo, 1.0, s5, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v3, v2, v1 v_fma_f32 v4, -v0, v3, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v3, v4, v1 v_fma_f32 v0, -v0, v3, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f32 v0, v0, v1, v3 v_div_fixup_f32 v0, v0, s5, 1.0 s_delay_alu instid0(VALU_DEP_1) v_sub_f32_e32 v1, s4, v0 s_cbranch_scc1 .LBB0_5 ; %bb.1: ; %NodeBlock s_cmp_lt_i32 s2, 3 s_cbranch_scc1 .LBB0_6 ; %bb.2: ; %LeafBlock69 v_mov_b32_e32 v2, 0 s_cmp_eq_u32 s2, 3 s_cbranch_scc0 .LBB0_4 ; %bb.3: v_mul_f32_e64 v2, s5, s5 s_mov_b32 s7, 0x400921fb s_mov_b32 s6, 0x542fe938 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_f64_f32_e32 v[2:3], v2 v_mul_f64 v[2:3], v[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[2:3], v[2:3], s[6:7] s_mov_b32 s7, 0xc0026bb1 s_mov_b32 s6, 0xbbb55515 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_div_scale_f64 v[4:5], null, s[6:7], s[6:7], v[2:3] v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[6:7], v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[6:7], v[4:5] s_waitcnt_depctr 0xfff v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[8:9], v[10:11], v[6:7] v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9] v_div_fixup_f64 v[2:3], v[4:5], s[6:7], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_f32_f64_e32 v2, v[2:3] v_mul_f32_e32 v2, v1, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v2, v1, v2 v_mul_f32_e32 v3, 0x3fb8aa3b, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f32 v4, v2, 0x3fb8aa3b, -v3 v_rndne_f32_e32 v5, v3 v_dual_fmamk_f32 v4, v2, 0x32a5705f, v4 :: v_dual_sub_f32 v3, v3, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_f32_e32 v3, v3, v4 v_cvt_i32_f32_e32 v4, v5 v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2 v_exp_f32_e32 v3, v3 s_waitcnt_depctr 0xfff v_ldexp_f32 v3, v3, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v3, 0, v3, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2 v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo .LBB0_4: ; %Flow s_cbranch_execz .LBB0_7 s_branch .LBB0_8 .LBB0_5: ; implicit-def: $vgpr2 s_branch .LBB0_9 .LBB0_6: ; implicit-def: $vgpr2 .LBB0_7: v_mul_f32_e64 v2, s5, -4.0 s_mov_b32 s7, 0x400921fb s_mov_b32 s6, 0x542fe938 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v2, s5, v2 v_cvt_f64_f32_e32 v[2:3], v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[2:3], v[2:3], s[6:7] v_mul_f64 v[2:3], v[2:3], s[6:7] s_mov_b32 s7, 0x40026bb1 s_mov_b32 s6, 0xbbb55515 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_div_scale_f64 v[4:5], null, s[6:7], s[6:7], v[2:3] v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[6:7], v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[6:7], v[4:5] s_waitcnt_depctr 0xfff v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[8:9], v[10:11], v[6:7] v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9] v_div_fixup_f64 v[2:3], v[4:5], s[6:7], v[2:3] s_mov_b32 s7, 0xc033bd3c s_mov_b32 s6, 0xc99e70c6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_f32_f64_e32 v2, v[2:3] v_mul_f32_e32 v2, v1, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f32_e32 v4, v1, v2 v_cvt_f64_f32_e32 v[2:3], v1 v_mul_f32_e32 v5, 0x3fb8aa3b, v4 v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f32 v6, v4, 0x3fb8aa3b, -v5 v_rndne_f32_e32 v7, v5 v_dual_fmamk_f32 v6, v4, 0x32a5705f, v6 :: v_dual_sub_f32 v5, v5, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f32_e32 v5, v5, v6 v_cvt_i32_f32_e32 v6, v7 v_exp_f32_e32 v5, v5 s_waitcnt_depctr 0xfff v_ldexp_f32 v5, v5, v6 v_mul_f64 v[2:3], v[2:3], s[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v5, 0, v5, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4 v_cndmask_b32_e32 v4, 0x7f800000, v5, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_f64_f32_e32 v[4:5], v4 v_mul_f64 v[2:3], v[2:3], v[4:5] s_delay_alu instid0(VALU_DEP_1) v_cvt_f32_f64_e32 v2, v[2:3] .LBB0_8: ; %Flow74 s_cbranch_execnz .LBB0_11 .LBB0_9: ; %LeafBlock v_mov_b32_e32 v2, 0 s_cmp_lg_u32 s2, 1 s_cbranch_scc1 .LBB0_11 ; %bb.10: v_mul_f32_e32 v1, s5, v1 s_mov_b32 s3, 0xc033bd3c s_mov_b32 s2, 0xc99e70c6 s_mov_b32 s7, 0x3e5ade15 s_mov_b32 s6, 0x6a5dcb37 v_mul_f32_e32 v1, v1, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_f64_f32_e32 v[1:2], v1 v_fma_f64 v[3:4], v[1:2], s[2:3], 1.0 s_mov_b32 s3, 0xc023bd3c s_delay_alu instid0(SALU_CYCLE_1) v_mul_f64 v[1:2], v[1:2], s[2:3] s_mov_b32 s3, 0x3ff71547 s_mov_b32 s2, 0x652b82fe s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mul_f64 v[5:6], v[1:2], s[2:3] s_mov_b32 s3, 0xbfe62e42 s_mov_b32 s2, 0xfefa39ef v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f64_e32 v[5:6], v[5:6] v_fma_f64 v[7:8], v[5:6], s[2:3], v[1:2] s_mov_b32 s3, 0xbc7abc9e s_mov_b32 s2, 0x3b39803f v_cvt_i32_f64_e32 v11, v[5:6] s_delay_alu instid0(VALU_DEP_2) v_fma_f64 v[7:8], v[5:6], s[2:3], v[7:8] s_mov_b32 s3, 0x3e928af3 s_mov_b32 s2, 0xfca7ab0c s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[9:10], v[7:8], s[6:7], s[2:3] s_mov_b32 s3, 0x3ec71dee s_mov_b32 s2, 0x623fde64 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[9:10], v[7:8], v[9:10], s[2:3] s_mov_b32 s3, 0x3efa0199 s_mov_b32 s2, 0x7c89e6b0 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[9:10], v[7:8], v[9:10], s[2:3] s_mov_b32 s3, 0x3f2a01a0 s_mov_b32 s2, 0x14761f6e s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[9:10], v[7:8], v[9:10], s[2:3] s_mov_b32 s3, 0x3f56c16c s_mov_b32 s2, 0x1852b7b0 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[9:10], v[7:8], v[9:10], s[2:3] s_mov_b32 s3, 0x3f811111 s_mov_b32 s2, 0x11122322 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[9:10], v[7:8], v[9:10], s[2:3] s_mov_b32 s3, 0x3fa55555 s_mov_b32 s2, 0x555502a1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[9:10], v[7:8], v[9:10], s[2:3] s_mov_b32 s3, 0x3fc55555 s_mov_b32 s2, 0x55555511 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[9:10], v[7:8], v[9:10], s[2:3] s_mov_b32 s3, 0x3fe00000 s_mov_b32 s2, 11 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[9:10], v[7:8], v[9:10], s[2:3] v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[9:10], v[7:8], v[9:10], 1.0 v_fma_f64 v[5:6], v[7:8], v[9:10], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[5:6], v[5:6], v11 v_cndmask_b32_e32 v6, 0x7ff00000, v6, vcc_lo s_and_b32 vcc_lo, s2, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v1, 0, v5, vcc_lo v_cndmask_b32_e64 v2, 0, v6, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[1:2], v[3:4], v[1:2] v_cvt_f32_f64_e32 v2, v[1:2] .LBB0_11: v_add_f32_e32 v0, v0, v0 s_delay_alu instid0(VALU_DEP_1) v_cmp_nle_f32_e32 vcc_lo, s4, v0 s_cbranch_vccnz .LBB0_13 ; %bb.12: s_clause 0x5 s_load_b64 s[2:3], s[0:1], 0x2c s_load_b32 s10, s[0:1], 0x34 s_load_b64 s[8:9], s[0:1], 0x0 s_load_b32 s11, s[0:1], 0x8 s_load_b128 s[4:7], s[0:1], 0x38 s_load_b32 s0, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_add_i32 s3, s3, -1 s_add_i32 s2, s2, -1 s_mul_i32 s3, s3, s10 v_cvt_f64_f32_e32 v[3:4], s11 v_cvt_f32_i32_e32 v0, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v0, s9, v0 v_cvt_f64_f32_e32 v[0:1], v0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[3:4], v[3:4], 0.5 v_add_f64 v[0:1], v[0:1], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cvt_i32_f64_e32 v0, v[0:1] v_cvt_i32_f64_e32 v1, v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_readfirstlane_b32 s1, v0 v_readfirstlane_b32 s3, v1 v_mov_b32_e32 v0, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s1, s2, s1 s_mul_i32 s1, s1, s0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s0, s2, s3 s_add_i32 s0, s0, s1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_ashr_i32 s1, s0, 31 s_lshl_b64 s[0:1], s[0:1], 2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s2, s4, s0 s_addc_u32 s3, s5, s1 s_add_u32 s0, s6, s0 s_load_b32 s4, s[2:3], 0x0 s_addc_u32 s1, s7, s1 s_waitcnt lgkmcnt(0) v_fma_f32 v1, v2, s8, s4 global_store_b32 v0, v1, s[2:3] global_load_b32 v1, v0, s[0:1] s_waitcnt vmcnt(0) v_fmac_f32_e32 v1, s8, v2 global_store_b32 v0, v1, s[0:1] .LBB0_13: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10add_sourcefffiiiifffiiiiPfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 72 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 12 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z10add_sourcefffiiiifffiiiiPfS_, .Lfunc_end0-_Z10add_sourcefffiiiifffiiiiPfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1612 ; NumSgprs: 14 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 14 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ ; -- Begin function _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .globl _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .p2align 8 .type _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_,@function _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_: ; @_Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ ; %bb.0: s_load_b32 s2, s[0:1], 0x84 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_mul_i32 s15, s15, s2 s_mov_b32 s2, exec_lo v_add_nc_u32_e32 v1, s15, v0 v_cmpx_lt_i32_e32 3, v1 s_cbranch_execz .LBB1_22 ; %bb.1: s_load_b64 s[8:9], s[0:1], 0x8 v_ashrrev_i32_e32 v4, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v5, v1, v4 v_xor_b32_e32 v5, v5, v4 s_waitcnt lgkmcnt(0) s_ashr_i32 s2, s9, 31 s_delay_alu instid0(SALU_CYCLE_1) s_add_i32 s3, s9, s2 v_xor_b32_e32 v4, s2, v4 s_xor_b32 s3, s3, s2 s_mul_i32 s2, s9, s8 v_cvt_f32_u32_e32 v2, s3 s_sub_i32 s4, 0, s3 s_add_i32 s2, s2, -4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v2, v2 s_waitcnt_depctr 0xfff v_mul_f32_e32 v2, 0x4f7ffffe, v2 v_cvt_u32_f32_e32 v2, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v3, s4, v2 v_mul_hi_u32 v3, v2, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v6, v2, v3 v_mad_u64_u32 v[2:3], null, v5, v6, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, v3, s3 v_sub_nc_u32_e32 v2, v5, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v6, s3, v2 v_cmp_le_u32_e32 vcc_lo, s3, v2 v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v5, 1, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v3, v3, v5, vcc_lo v_cmp_le_u32_e32 vcc_lo, s3, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v5, 1, v3 v_cndmask_b32_e32 v2, v3, v5, vcc_lo v_cmp_gt_i32_e32 vcc_lo, s2, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v2, v2, v4 v_sub_nc_u32_e32 v3, v2, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_lt_i32_e64 s2, 3, v3 s_and_b32 s2, s2, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 exec_lo, exec_lo, s2 s_cbranch_execz .LBB1_22 ; %bb.2: v_mul_lo_u32 v2, v3, s9 s_add_i32 s2, s8, -4 s_add_i32 s3, s9, -4 v_cmp_gt_i32_e32 vcc_lo, s2, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v5, v1, v2 v_cmp_gt_i32_e64 s2, s3, v5 v_cmp_lt_i32_e64 s3, 3, v5 s_delay_alu instid0(VALU_DEP_2) s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_b32 s2, s2, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 exec_lo, exec_lo, s2 s_cbranch_execz .LBB1_22 ; %bb.3: ; %.preheader s_load_b128 s[4:7], s[0:1], 0x40 v_ashrrev_i32_e32 v2, 31, v1 s_ashr_i32 s11, s9, 31 s_mov_b32 s10, s9 v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v6, 1, v1 s_delay_alu instid0(VALU_DEP_2) v_lshlrev_b64 v[10:11], 2, v[1:2] v_add3_u32 v8, s15, s9, v0 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v13, 0 v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v15, 0 s_lshl_b64 s[10:11], s[10:11], 2 s_mov_b64 s[2:3], 0 s_sub_u32 s8, 0, s10 s_subb_u32 s18, 0, s11 s_waitcnt lgkmcnt(0) s_mov_b64 s[10:11], s[6:7] s_mov_b64 s[12:13], s[4:5] s_mov_b64 s[14:15], s[6:7] s_mov_b64 s[16:17], s[4:5] .LBB1_4: ; =>This Inner Loop Header: Depth=1 v_add_co_u32 v16, vcc_lo, s12, v10 v_add_co_ci_u32_e32 v17, vcc_lo, s13, v11, vcc_lo v_add_co_u32 v20, vcc_lo, s16, v10 v_add_co_ci_u32_e32 v21, vcc_lo, s17, v11, vcc_lo v_lshlrev_b64 v[18:19], 2, v[6:7] v_add_co_u32 v22, vcc_lo, s14, v10 v_ashrrev_i32_e32 v9, 31, v8 v_add_co_ci_u32_e32 v23, vcc_lo, s15, v11, vcc_lo v_add_co_u32 v24, vcc_lo, s10, v10 v_add_co_ci_u32_e32 v25, vcc_lo, s11, v11, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_lshlrev_b64 v[26:27], 2, v[8:9] global_load_b32 v2, v[16:17], off global_load_b32 v4, v[20:21], off global_load_b32 v9, v[22:23], off v_add_co_u32 v16, vcc_lo, s4, v18 v_add_co_ci_u32_e32 v17, vcc_lo, s5, v19, vcc_lo v_add_co_u32 v18, vcc_lo, s6, v18 v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo v_add_co_u32 v20, vcc_lo, s4, v26 v_add_co_ci_u32_e32 v21, vcc_lo, s5, v27, vcc_lo v_add_co_u32 v22, vcc_lo, s6, v26 v_add_co_ci_u32_e32 v23, vcc_lo, s7, v27, vcc_lo global_load_b32 v12, v[24:25], off global_load_b32 v16, v[16:17], off global_load_b32 v17, v[18:19], off global_load_b32 v18, v[20:21], off global_load_b32 v19, v[22:23], off s_getpc_b64 s[20:21] s_add_u32 s20, s20, c@rel32@lo+4 s_addc_u32 s21, s21, c@rel32@hi+12 s_add_u32 s20, s2, s20 s_addc_u32 s21, s3, s21 s_add_u32 s16, s16, -4 s_load_b32 s19, s[20:21], 0x0 s_addc_u32 s17, s17, -1 v_add_nc_u32_e32 v6, 1, v6 s_add_u32 s14, s14, -4 s_addc_u32 s15, s15, -1 s_add_u32 s12, s12, s8 s_addc_u32 s13, s13, s18 s_add_u32 s10, s10, s8 s_addc_u32 s11, s11, s18 s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 s_cmp_lg_u32 s2, 16 s_waitcnt vmcnt(1) v_dual_sub_f32 v9, v17, v9 :: v_dual_sub_f32 v2, v18, v2 v_sub_f32_e32 v4, v16, v4 s_waitcnt vmcnt(0) v_sub_f32_e32 v12, v19, v12 s_waitcnt lgkmcnt(0) v_dual_fmac_f32 v13, s19, v9 :: v_dual_add_nc_u32 v8, s9, v8 v_dual_fmac_f32 v15, s19, v2 :: v_dual_fmac_f32 v14, s19, v4 s_delay_alu instid0(VALU_DEP_3) v_fmac_f32_e32 v0, s19, v12 s_cbranch_scc1 .LBB1_4 ; %bb.5: s_load_b256 s[4:11], s[0:1], 0x50 v_mov_b32_e32 v4, 0 s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x20 s_load_b64 s[12:13], s[0:1], 0x70 ; implicit-def: $vgpr24 ; implicit-def: $vgpr23 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_mov_b32_e32 v6, v4 v_lshlrev_b64 v[7:8], 2, v[3:4] v_mov_b32_e32 v2, v4 v_lshlrev_b64 v[11:12], 2, v[5:6] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_lshlrev_b64 v[9:10], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v3, vcc_lo, s6, v7 v_add_co_ci_u32_e32 v4, vcc_lo, s7, v8, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v5, vcc_lo, s10, v11 v_add_co_ci_u32_e32 v6, vcc_lo, s11, v12, vcc_lo v_add_co_u32 v19, vcc_lo, s2, v9 v_add_co_ci_u32_e32 v20, vcc_lo, s3, v10, vcc_lo v_add_co_u32 v9, vcc_lo, s12, v9 v_add_co_ci_u32_e32 v10, vcc_lo, s13, v10, vcc_lo v_add_co_u32 v7, vcc_lo, s4, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo v_add_co_u32 v11, vcc_lo, s8, v11 global_load_b32 v21, v[9:10], off v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo global_load_b32 v17, v[3:4], off global_load_b32 v18, v[5:6], off global_load_b32 v16, v[19:20], off global_load_b32 v19, v[7:8], off global_load_b32 v20, v[11:12], off s_waitcnt vmcnt(5) v_and_b32_e32 v22, 0x7fffffff, v21 v_cmp_ngt_f32_e64 s4, 0x48000000, |v21| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s2, s4 s_xor_b32 s5, exec_lo, s2 s_cbranch_execz .LBB1_7 ; %bb.6: s_mov_b32 s2, 0x7fffff v_mov_b32_e32 v25, 0 v_and_or_b32 v33, v22, s2, 0x800000 v_lshrrev_b32_e32 v30, 23, v22 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[23:24], null, v33, 0xfe5163ab, 0 v_add_nc_u32_e32 v31, 0xffffff88, v30 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_lt_u32_e32 vcc_lo, 63, v31 v_mad_u64_u32 v[26:27], null, v33, 0x3c439041, v[24:25] v_cndmask_b32_e64 v32, 0, 0xffffffc0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mov_b32_e32 v24, v27 v_add_nc_u32_e32 v32, v32, v31 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[27:28], null, v33, 0xdb629599, v[24:25] v_cmp_lt_u32_e64 s2, 31, v32 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v34, 0, 0xffffffe0, s2 v_dual_mov_b32 v24, v28 :: v_dual_cndmask_b32 v23, v27, v23 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v34, v34, v32 v_mad_u64_u32 v[28:29], null, v33, 0xf534ddc0, v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_lt_u32_e64 s3, 31, v34 v_mov_b32_e32 v24, v29 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v26, v28, v26, vcc_lo v_mad_u64_u32 v[29:30], null, v33, 0xfc2757d1, v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v23, v26, v23, s2 v_mov_b32_e32 v24, v30 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[30:31], null, v33, 0x4e441529, v[24:25] v_mov_b32_e32 v24, v31 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[31:32], null, v33, 0xa2f9836e, v[24:25] v_cndmask_b32_e64 v24, 0, 0xffffffe0, s3 v_dual_cndmask_b32 v25, v30, v28 :: v_dual_add_nc_u32 v24, v24, v34 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v31, v31, v29 :: v_dual_cndmask_b32 v30, v32, v30 v_cndmask_b32_e32 v29, v29, v27, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v24 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v28, v31, v25, s2 v_cndmask_b32_e64 v30, v30, v31, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v25, v25, v29, s2 v_sub_nc_u32_e32 v31, 32, v24 v_cndmask_b32_e64 v29, v29, v26, s2 v_cndmask_b32_e64 v30, v30, v28, s3 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v28, v28, v25, s3 v_cndmask_b32_e64 v25, v25, v29, s3 v_cndmask_b32_e64 v23, v29, v23, s3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v32, v30, v28, v31 v_alignbit_b32 v27, v28, v25, v31 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v24, v32, v30, vcc_lo v_alignbit_b32 v30, v25, v23, v31 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v26, v27, v28, vcc_lo v_bfe_u32 v27, v24, 29, 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v25, v30, v25, vcc_lo v_alignbit_b32 v28, v24, v26, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_sub_nc_u32_e32 v29, 0, v27 v_alignbit_b32 v26, v26, v25, 30 v_alignbit_b32 v23, v25, v23, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v28, v28, v29 v_xor_b32_e32 v25, v26, v29 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v23, v23, v29 v_clz_i32_u32_e32 v30, v28 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_min_u32_e32 v30, 32, v30 v_sub_nc_u32_e32 v26, 31, v30 v_lshlrev_b32_e32 v32, 23, v30 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_alignbit_b32 v28, v28, v25, v26 v_alignbit_b32 v23, v25, v23, v26 v_lshrrev_b32_e32 v26, 29, v24 v_alignbit_b32 v25, v28, v23, 9 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b32_e32 v26, 31, v26 v_lshrrev_b32_e32 v28, 9, v28 v_clz_i32_u32_e32 v29, v25 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_or_b32_e32 v31, 0.5, v26 v_min_u32_e32 v29, 32, v29 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v31, v31, v32 v_sub_nc_u32_e32 v33, 31, v29 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v23, v25, v23, v33 v_or_b32_e32 v25, v28, v31 v_add_lshl_u32 v28, v29, v30, 23 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshrrev_b32_e32 v23, 9, v23 v_mul_f32_e32 v29, 0x3fc90fda, v25 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v23, v23, v28 v_fma_f32 v28, v25, 0x3fc90fda, -v29 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v23, 0x33000000, v23 v_fmamk_f32 v25, v25, 0x33a22168, v28 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_or_b32_e32 v23, v23, v26 v_fmac_f32_e32 v25, 0x3fc90fda, v23 v_lshrrev_b32_e32 v24, 30, v24 s_delay_alu instid0(VALU_DEP_1) v_dual_add_f32 v23, v29, v25 :: v_dual_add_nc_u32 v24, v27, v24 .LBB1_7: ; %Flow211 s_and_not1_saveexec_b32 s2, s5 ; %bb.8: v_mul_f32_e64 v23, 0x3f22f983, |v21| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f32_e32 v24, v23 v_fma_f32 v23, v24, 0xbfc90fda, |v21| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v23, v24, 0xb3a22168, v23 v_fmamk_f32 v23, v24, 0xa7c234c4, v23 v_cvt_i32_f32_e32 v24, v24 ; %bb.9: ; %_ZL3cosf.exit s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $vgpr26 ; implicit-def: $vgpr25 s_and_saveexec_b32 s2, s4 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s4, exec_lo, s2 s_cbranch_execz .LBB1_11 ; %bb.10: s_mov_b32 s2, 0x7fffff v_mov_b32_e32 v27, 0 v_and_or_b32 v35, v22, s2, 0x800000 v_lshrrev_b32_e32 v32, 23, v22 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[25:26], null, v35, 0xfe5163ab, 0 v_add_nc_u32_e32 v33, 0xffffff88, v32 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_lt_u32_e32 vcc_lo, 63, v33 v_mad_u64_u32 v[28:29], null, v35, 0x3c439041, v[26:27] v_cndmask_b32_e64 v34, 0, 0xffffffc0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mov_b32_e32 v26, v29 v_add_nc_u32_e32 v34, v34, v33 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[29:30], null, v35, 0xdb629599, v[26:27] v_cmp_lt_u32_e64 s2, 31, v34 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v36, 0, 0xffffffe0, s2 v_dual_mov_b32 v26, v30 :: v_dual_cndmask_b32 v25, v29, v25 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v36, v36, v34 v_mad_u64_u32 v[30:31], null, v35, 0xf534ddc0, v[26:27] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_lt_u32_e64 s3, 31, v36 v_mov_b32_e32 v26, v31 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v28, v30, v28, vcc_lo v_mad_u64_u32 v[31:32], null, v35, 0xfc2757d1, v[26:27] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v25, v28, v25, s2 v_mov_b32_e32 v26, v32 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[32:33], null, v35, 0x4e441529, v[26:27] v_mov_b32_e32 v26, v33 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[33:34], null, v35, 0xa2f9836e, v[26:27] v_cndmask_b32_e64 v26, 0, 0xffffffe0, s3 v_dual_cndmask_b32 v27, v32, v30 :: v_dual_add_nc_u32 v26, v26, v36 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v33, v33, v31 :: v_dual_cndmask_b32 v32, v34, v32 v_cndmask_b32_e32 v31, v31, v29, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v26 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v30, v33, v27, s2 v_cndmask_b32_e64 v32, v32, v33, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v27, v27, v31, s2 v_sub_nc_u32_e32 v33, 32, v26 v_cndmask_b32_e64 v31, v31, v28, s2 v_cndmask_b32_e64 v32, v32, v30, s3 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v30, v30, v27, s3 v_cndmask_b32_e64 v27, v27, v31, s3 v_cndmask_b32_e64 v25, v31, v25, s3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v34, v32, v30, v33 v_alignbit_b32 v29, v30, v27, v33 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v26, v34, v32, vcc_lo v_alignbit_b32 v32, v27, v25, v33 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v28, v29, v30, vcc_lo v_bfe_u32 v29, v26, 29, 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v27, v32, v27, vcc_lo v_alignbit_b32 v30, v26, v28, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_sub_nc_u32_e32 v31, 0, v29 v_alignbit_b32 v28, v28, v27, 30 v_alignbit_b32 v25, v27, v25, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v30, v30, v31 v_xor_b32_e32 v27, v28, v31 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v25, v25, v31 v_clz_i32_u32_e32 v32, v30 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_min_u32_e32 v32, 32, v32 v_sub_nc_u32_e32 v28, 31, v32 v_lshlrev_b32_e32 v34, 23, v32 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_alignbit_b32 v30, v30, v27, v28 v_alignbit_b32 v25, v27, v25, v28 v_lshrrev_b32_e32 v28, 29, v26 v_alignbit_b32 v27, v30, v25, 9 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b32_e32 v28, 31, v28 v_lshrrev_b32_e32 v30, 9, v30 v_clz_i32_u32_e32 v31, v27 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_or_b32_e32 v33, 0.5, v28 v_min_u32_e32 v31, 32, v31 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v33, v33, v34 v_sub_nc_u32_e32 v35, 31, v31 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v25, v27, v25, v35 v_or_b32_e32 v27, v30, v33 v_add_lshl_u32 v30, v31, v32, 23 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshrrev_b32_e32 v25, 9, v25 v_mul_f32_e32 v31, 0x3fc90fda, v27 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v25, v25, v30 v_fma_f32 v30, v27, 0x3fc90fda, -v31 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v25, 0x33000000, v25 v_fmamk_f32 v27, v27, 0x33a22168, v30 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_or_b32_e32 v25, v25, v28 v_fmac_f32_e32 v27, 0x3fc90fda, v25 v_lshrrev_b32_e32 v26, 30, v26 s_delay_alu instid0(VALU_DEP_1) v_dual_add_f32 v25, v31, v27 :: v_dual_add_nc_u32 v26, v29, v26 .LBB1_11: ; %Flow210 s_and_not1_saveexec_b32 s2, s4 ; %bb.12: v_mul_f32_e64 v25, 0x3f22f983, |v21| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f32_e32 v26, v25 v_fma_f32 v25, v26, 0xbfc90fda, |v21| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v25, v26, 0xb3a22168, v25 v_fmamk_f32 v25, v26, 0xa7c234c4, v25 v_cvt_i32_f32_e32 v26, v26 ; %bb.13: ; %_ZL3sinf.exit s_or_b32 exec_lo, exec_lo, s2 s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x14 s_load_b32 s6, s[0:1], 0x1c v_dual_mul_f32 v27, v23, v23 :: v_dual_and_b32 v28, 1, v24 s_mov_b32 s2, 0xb94c1982 v_dual_mul_f32 v29, v25, v25 :: v_dual_lshlrev_b32 v24, 30, v24 s_delay_alu instid0(VALU_DEP_2) v_dual_fmaak_f32 v31, s2, v27, 0x3c0881c4 :: v_dual_and_b32 v30, 1, v26 v_lshlrev_b32_e32 v26, 30, v26 s_mov_b32 s3, 0x37d75334 v_xor_b32_e32 v22, v22, v21 s_load_b128 s[8:11], s[0:1], 0x28 v_fmaak_f32 v31, v27, v31, 0xbe2aaa9d v_and_b32_e32 v24, 0x80000000, v24 s_waitcnt vmcnt(0) v_mul_f32_e32 v19, v19, v20 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_dual_mul_f32 v31, v27, v31 :: v_dual_fmaak_f32 v38, s3, v29, 0xbab64f3b s_waitcnt lgkmcnt(0) v_div_scale_f32 v32, null, s5, s5, s4 v_div_scale_f32 v33, null, s6, s6, s4 v_fmac_f32_e32 v23, v23, v31 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_rcp_f32_e32 v35, v32 v_div_scale_f32 v41, vcc_lo, s4, s5, s4 v_rcp_f32_e32 v37, v33 s_waitcnt_depctr 0xfff v_fma_f32 v39, -v32, v35, 1.0 v_fmaak_f32 v36, s2, v29, 0x3c0881c4 v_fma_f32 v40, -v33, v37, 1.0 v_fmaak_f32 v34, s3, v27, 0xbab64f3b s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_dual_fmac_f32 v35, v39, v35 :: v_dual_fmaak_f32 v36, v29, v36, 0xbe2aaa9d v_div_scale_f32 v39, s2, s4, s6, s4 v_dual_fmac_f32 v37, v40, v37 :: v_dual_and_b32 v26, 0x80000000, v26 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mul_f32_e32 v36, v29, v36 v_fmaak_f32 v34, v27, v34, 0x3d2aabf7 v_dual_mul_f32 v40, v41, v35 :: v_dual_mul_f32 v31, v39, v37 v_cmp_eq_u32_e64 s3, 0, v28 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_fmac_f32 v25, v25, v36 :: v_dual_fmaak_f32 v34, v27, v34, 0xbf000004 v_fma_f32 v36, -v33, v31, v39 v_fmaak_f32 v38, v29, v38, 0x3d2aabf7 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f32 v27, v27, v34, 1.0 v_fma_f32 v34, -v32, v40, v41 v_dual_fmac_f32 v31, v36, v37 :: v_dual_fmaak_f32 v38, v29, v38, 0xbf000004 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v23, -v23, v27, s3 v_cmp_eq_u32_e64 s3, 0, v30 v_fmac_f32_e32 v40, v34, v35 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f32 v29, v29, v38, 1.0 v_xor_b32_e32 v23, v24, v23 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f32 v24, -v32, v40, v41 v_cndmask_b32_e64 v25, v29, v25, s3 v_cmp_class_f32_e64 s3, v21, 0x1f8 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_div_fmas_f32 v24, v24, v35, v40 v_xor3_b32 v22, v22, v26, v25 v_fma_f32 v25, -v33, v31, v39 s_mov_b32 vcc_lo, s2 v_cndmask_b32_e64 v23, 0x7fc00000, v23, s3 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fmas_f32 v21, v25, v37, v31 v_cndmask_b32_e64 v25, 0x7fc00000, v22, s3 v_div_fixup_f32 v22, v21, s6, s4 v_div_fixup_f32 v21, v24, s5, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mul_f32 v24, v22, v25 :: v_dual_mul_f32 v23, v21, v23 v_mul_f32_e32 v14, v14, v24 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f32 v20, v15, v23, -v14 v_mul_f32_e32 v23, v17, v18 v_lshlrev_b64 v[14:15], 2, v[1:2] v_mul_f32_e32 v19, v19, v20 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v17, vcc_lo, s10, v14 v_add_co_ci_u32_e32 v18, vcc_lo, s11, v15, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_fma_f32 v16, v23, v16, -v19 v_add_co_u32 v14, vcc_lo, s8, v14 v_add_co_ci_u32_e32 v15, vcc_lo, s9, v15, vcc_lo global_store_b32 v[17:18], v16, off global_load_b32 v9, v[9:10], off global_load_b32 v4, v[3:4], off global_load_b32 v5, v[5:6], off global_load_b32 v3, v[14:15], off global_load_b32 v6, v[7:8], off global_load_b32 v7, v[11:12], off ; implicit-def: $vgpr11 ; implicit-def: $vgpr10 s_waitcnt vmcnt(5) v_and_b32_e32 v8, 0x7fffffff, v9 v_cmp_ngt_f32_e64 s4, 0x48000000, |v9| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s2, s4 s_xor_b32 s5, exec_lo, s2 s_cbranch_execz .LBB1_15 ; %bb.14: s_mov_b32 s2, 0x7fffff v_mov_b32_e32 v12, 0 v_and_or_b32 v23, v8, s2, 0x800000 v_lshrrev_b32_e32 v18, 23, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[10:11], null, v23, 0xfe5163ab, 0 v_add_nc_u32_e32 v19, 0xffffff88, v18 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_lt_u32_e32 vcc_lo, 63, v19 v_mad_u64_u32 v[14:15], null, v23, 0x3c439041, v[11:12] v_cndmask_b32_e64 v20, 0, 0xffffffc0, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v11, v15 :: v_dual_add_nc_u32 v20, v20, v19 v_mad_u64_u32 v[15:16], null, v23, 0xdb629599, v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_lt_u32_e64 s2, 31, v20 v_cndmask_b32_e64 v24, 0, 0xffffffe0, s2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_mov_b32 v11, v16 :: v_dual_cndmask_b32 v10, v15, v10 v_add_nc_u32_e32 v24, v24, v20 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[16:17], null, v23, 0xf534ddc0, v[11:12] v_cmp_lt_u32_e64 s3, 31, v24 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v11, v17 :: v_dual_cndmask_b32 v14, v16, v14 v_mad_u64_u32 v[17:18], null, v23, 0xfc2757d1, v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v10, v14, v10, s2 v_mov_b32_e32 v11, v18 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[18:19], null, v23, 0x4e441529, v[11:12] v_mov_b32_e32 v11, v19 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_mad_u64_u32 v[19:20], null, v23, 0xa2f9836e, v[11:12] v_cndmask_b32_e64 v11, 0, 0xffffffe0, s3 v_cndmask_b32_e32 v12, v18, v16, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_nc_u32_e32 v11, v11, v24 v_dual_cndmask_b32 v19, v19, v17 :: v_dual_cndmask_b32 v18, v20, v18 v_cndmask_b32_e32 v17, v17, v15, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_eq_u32_e32 vcc_lo, 0, v11 v_cndmask_b32_e64 v16, v19, v12, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v18, v18, v19, s2 v_cndmask_b32_e64 v12, v12, v17, s2 v_sub_nc_u32_e32 v19, 32, v11 v_cndmask_b32_e64 v17, v17, v14, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v18, v18, v16, s3 v_cndmask_b32_e64 v16, v16, v12, s3 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v12, v12, v17, s3 v_cndmask_b32_e64 v10, v17, v10, s3 v_alignbit_b32 v20, v18, v16, v19 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_alignbit_b32 v15, v16, v12, v19 v_cndmask_b32_e32 v11, v20, v18, vcc_lo s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v18, v12, v10, v19 v_cndmask_b32_e32 v14, v15, v16, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v12, v18, v12, vcc_lo v_bfe_u32 v15, v11, 29, 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v16, v11, v14, 30 v_alignbit_b32 v14, v14, v12, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v17, 0, v15 v_alignbit_b32 v10, v12, v10, 30 v_xor_b32_e32 v16, v16, v17 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v12, v14, v17 v_xor_b32_e32 v10, v10, v17 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_clz_i32_u32_e32 v18, v16 v_min_u32_e32 v18, 32, v18 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v14, 31, v18 v_lshlrev_b32_e32 v20, 23, v18 v_alignbit_b32 v16, v16, v12, v14 v_alignbit_b32 v10, v12, v10, v14 v_lshrrev_b32_e32 v14, 29, v11 v_lshrrev_b32_e32 v11, 30, v11 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v12, v16, v10, 9 v_lshlrev_b32_e32 v14, 31, v14 v_lshrrev_b32_e32 v16, 9, v16 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_nc_u32_e32 v11, v15, v11 v_clz_i32_u32_e32 v17, v12 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_or_b32_e32 v19, 0.5, v14 v_min_u32_e32 v17, 32, v17 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v19, v19, v20 v_sub_nc_u32_e32 v23, 31, v17 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v10, v12, v10, v23 v_or_b32_e32 v12, v16, v19 v_add_lshl_u32 v16, v17, v18, 23 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshrrev_b32_e32 v10, 9, v10 v_mul_f32_e32 v17, 0x3fc90fda, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v10, v10, v16 v_fma_f32 v16, v12, 0x3fc90fda, -v17 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v10, 0x33000000, v10 v_fmamk_f32 v12, v12, 0x33a22168, v16 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_or_b32_e32 v10, v10, v14 v_fmac_f32_e32 v12, 0x3fc90fda, v10 s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v10, v17, v12 .LBB1_15: ; %Flow209 s_and_not1_saveexec_b32 s2, s5 ; %bb.16: v_mul_f32_e64 v10, 0x3f22f983, |v9| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f32_e32 v11, v10 v_fma_f32 v10, v11, 0xbfc90fda, |v9| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v10, v11, 0xb3a22168, v10 v_fmamk_f32 v10, v11, 0xa7c234c4, v10 v_cvt_i32_f32_e32 v11, v11 ; %bb.17: ; %_ZL3sinf.exit128 s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $vgpr14 ; implicit-def: $vgpr12 s_and_saveexec_b32 s2, s4 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s4, exec_lo, s2 s_cbranch_execz .LBB1_19 ; %bb.18: s_mov_b32 s2, 0x7fffff v_mov_b32_e32 v16, 0 v_and_or_b32 v12, v8, s2, 0x800000 v_lshrrev_b32_e32 v23, 23, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[14:15], null, v12, 0xfe5163ab, 0 v_mad_u64_u32 v[17:18], null, v12, 0x3c439041, v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mov_b32_e32 v15, v18 v_mad_u64_u32 v[18:19], null, v12, 0xdb629599, v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mov_b32_e32 v15, v19 v_mad_u64_u32 v[19:20], null, v12, 0xf534ddc0, v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v15, v20 :: v_dual_add_nc_u32 v20, 0xffffff88, v23 v_cmp_lt_u32_e32 vcc_lo, 63, v20 v_cndmask_b32_e64 v25, 0, 0xffffffc0, vcc_lo s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v14, v18, v14 :: v_dual_cndmask_b32 v17, v19, v17 v_add_nc_u32_e32 v20, v25, v20 v_mad_u64_u32 v[23:24], null, v12, 0xfc2757d1, v[15:16] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_lt_u32_e64 s2, 31, v20 v_cndmask_b32_e64 v26, 0, 0xffffffe0, s2 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mov_b32_e32 v15, v24 v_cndmask_b32_e64 v14, v17, v14, s2 v_add_nc_u32_e32 v20, v26, v20 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[24:25], null, v12, 0x4e441529, v[15:16] v_cmp_lt_u32_e64 s3, 31, v20 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mov_b32_e32 v15, v25 v_mad_u64_u32 v[25:26], null, v12, 0xa2f9836e, v[15:16] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v12, 0, 0xffffffe0, s3 v_cndmask_b32_e32 v15, v24, v19, vcc_lo v_add_nc_u32_e32 v12, v12, v20 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v16, v25, v23 :: v_dual_cndmask_b32 v23, v23, v18 v_cndmask_b32_e32 v24, v26, v24, vcc_lo v_sub_nc_u32_e32 v20, 32, v12 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v19, v16, v15, s2 v_cndmask_b32_e64 v15, v15, v23, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v16, v24, v16, s2 v_cndmask_b32_e64 v23, v23, v17, s2 v_cmp_eq_u32_e32 vcc_lo, 0, v12 v_cndmask_b32_e64 v16, v16, v19, s3 v_cndmask_b32_e64 v19, v19, v15, s3 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v15, v15, v23, s3 v_cndmask_b32_e64 v14, v23, v14, s3 v_alignbit_b32 v24, v16, v19, v20 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v18, v19, v15, v20 v_alignbit_b32 v20, v15, v14, v20 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v12, v24, v16, vcc_lo v_cndmask_b32_e32 v16, v18, v19, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v15, v20, v15, vcc_lo v_bfe_u32 v17, v12, 29, 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v18, v12, v16, 30 v_alignbit_b32 v16, v16, v15, 30 v_alignbit_b32 v14, v15, v14, 30 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v19, 0, v17 v_xor_b32_e32 v18, v18, v19 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_xor_b32_e32 v15, v16, v19 v_xor_b32_e32 v14, v14, v19 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_clz_i32_u32_e32 v20, v18 v_min_u32_e32 v20, 32, v20 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v16, 31, v20 v_lshlrev_b32_e32 v24, 23, v20 v_alignbit_b32 v18, v18, v15, v16 v_alignbit_b32 v14, v15, v14, v16 v_lshrrev_b32_e32 v16, 29, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_alignbit_b32 v15, v18, v14, 9 v_lshlrev_b32_e32 v16, 31, v16 v_lshrrev_b32_e32 v18, 9, v18 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_clz_i32_u32_e32 v19, v15 v_or_b32_e32 v23, 0.5, v16 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_min_u32_e32 v19, 32, v19 v_sub_nc_u32_e32 v23, v23, v24 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v25, 31, v19 v_alignbit_b32 v14, v15, v14, v25 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_or_b32_e32 v15, v18, v23 v_add_lshl_u32 v18, v19, v20, 23 v_lshrrev_b32_e32 v14, 9, v14 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f32_e32 v19, 0x3fc90fda, v15 v_sub_nc_u32_e32 v14, v14, v18 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v18, v15, 0x3fc90fda, -v19 v_add_nc_u32_e32 v14, 0x33000000, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmamk_f32 v15, v15, 0x33a22168, v18 v_or_b32_e32 v14, v14, v16 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fmac_f32_e32 v15, 0x3fc90fda, v14 v_lshrrev_b32_e32 v14, 30, v12 v_add_f32_e32 v12, v19, v15 s_delay_alu instid0(VALU_DEP_2) v_add_nc_u32_e32 v14, v17, v14 .LBB1_19: ; %Flow s_and_not1_saveexec_b32 s2, s4 ; %bb.20: v_mul_f32_e64 v12, 0x3f22f983, |v9| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f32_e32 v14, v12 v_fma_f32 v12, v14, 0xbfc90fda, |v9| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v12, v14, 0xb3a22168, v12 v_fmamk_f32 v12, v14, 0xa7c234c4, v12 v_cvt_i32_f32_e32 v14, v14 ; %bb.21: ; %_ZL3cosf.exit134 s_or_b32 exec_lo, exec_lo, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_dual_mul_f32 v15, v10, v10 :: v_dual_mul_f32 v16, v12, v12 s_mov_b32 s2, 0xb94c1982 s_mov_b32 s3, 0x37d75334 s_load_b64 s[0:1], s[0:1], 0x38 v_fmaak_f32 v17, s2, v15, 0x3c0881c4 v_dual_fmaak_f32 v20, s3, v16, 0xbab64f3b :: v_dual_and_b32 v23, 1, v11 s_waitcnt vmcnt(3) v_dual_mul_f32 v4, v4, v5 :: v_dual_lshlrev_b32 v11, 30, v11 s_delay_alu instid0(VALU_DEP_3) v_fmaak_f32 v17, v15, v17, 0xbe2aaa9d v_fmaak_f32 v18, s3, v15, 0xbab64f3b v_fmaak_f32 v20, v16, v20, 0x3d2aabf7 v_cmp_eq_u32_e32 vcc_lo, 0, v23 v_and_b32_e32 v11, 0x80000000, v11 v_mul_f32_e32 v17, v15, v17 v_fmaak_f32 v18, v15, v18, 0x3d2aabf7 s_waitcnt vmcnt(0) v_dual_fmaak_f32 v19, s2, v16, 0x3c0881c4 :: v_dual_mul_f32 v6, v6, v7 v_xor_b32_e32 v11, v11, v9 v_fmac_f32_e32 v10, v10, v17 v_fmaak_f32 v18, v15, v18, 0xbf000004 v_dual_fmaak_f32 v20, v16, v20, 0xbf000004 :: v_dual_and_b32 v17, 1, v14 v_lshlrev_b32_e32 v14, 30, v14 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f32 v15, v15, v18, 1.0 v_fmaak_f32 v19, v16, v19, 0xbe2aaa9d v_and_b32_e32 v14, 0x80000000, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v10, v15, v10 :: v_dual_mul_f32 v19, v16, v19 v_fma_f32 v16, v16, v20, 1.0 v_cmp_eq_u32_e32 vcc_lo, 0, v17 v_xor3_b32 v8, v11, v10, v8 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v12, v12, v19 v_cndmask_b32_e64 v12, -v12, v16, vcc_lo v_cmp_class_f32_e64 vcc_lo, v9, 0x1f8 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_xor_b32_e32 v10, v14, v12 v_cndmask_b32_e32 v8, 0x7fc00000, v8, vcc_lo v_dual_cndmask_b32 v9, 0x7fc00000, v10 :: v_dual_mul_f32 v8, v21, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v9, v22, v9 v_mul_f32_e32 v9, v13, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fmac_f32_e32 v9, v0, v8 v_lshlrev_b64 v[0:1], 2, v[1:2] v_mul_f32_e32 v5, v6, v9 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_fma_f32 v2, v4, v3, -v5 global_store_b32 v[0:1], v2, off .LBB1_22: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 376 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 42 .amdhsa_next_free_sgpr 22 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_, .Lfunc_end1-_Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 5084 ; NumSgprs: 24 ; NumVgprs: 42 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 5 ; NumSGPRsForWavesPerEU: 24 ; NumVGPRsForWavesPerEU: 42 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib ; -- Begin function _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .globl _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .p2align 8 .type _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib,@function _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib: ; @_Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib ; %bb.0: s_load_b32 s2, s[0:1], 0xec s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_mul_i32 s15, s15, s2 s_mov_b32 s2, exec_lo v_add_nc_u32_e32 v1, s15, v0 v_cmpx_lt_i32_e32 3, v1 s_cbranch_execz .LBB2_58 ; %bb.1: s_load_b64 s[8:9], s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_mul_i32 s2, s9, s8 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s2, s2, -4 v_cmp_gt_i32_e32 vcc_lo, s2, v1 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB2_58 ; %bb.2: s_ashr_i32 s2, s9, 31 v_ashrrev_i32_e32 v4, 31, v1 s_add_i32 s3, s9, s2 s_load_b32 s10, s[0:1], 0xd8 s_xor_b32 s3, s3, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cvt_f32_u32_e32 v2, s3 s_sub_i32 s4, 0, s3 v_add_nc_u32_e32 v5, v1, v4 v_rcp_iflag_f32_e32 v2, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_xor_b32_e32 v5, v5, v4 v_xor_b32_e32 v4, s2, v4 s_mov_b32 s2, 0 s_waitcnt_depctr 0xfff v_mul_f32_e32 v2, 0x4f7ffffe, v2 v_cvt_u32_f32_e32 v2, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_mul_lo_u32 v3, s4, v2 s_load_b128 s[4:7], s[0:1], 0xb0 s_waitcnt lgkmcnt(0) s_bitcmp0_b32 s10, 0 v_mul_hi_u32 v3, v2, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v6, v2, v3 v_mad_u64_u32 v[2:3], null, v5, v6, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, v3, s3 v_sub_nc_u32_e32 v2, v5, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v6, s3, v2 v_cmp_le_u32_e32 vcc_lo, s3, v2 v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v5, 1, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v3, v3, v5, vcc_lo v_cmp_le_u32_e32 vcc_lo, s3, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v5, 1, v3 v_cndmask_b32_e32 v2, v3, v5, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v2, v2, v4 v_sub_nc_u32_e32 v3, v2, v4 s_delay_alu instid0(VALU_DEP_1) v_mul_lo_u32 v4, v3, s9 s_cbranch_scc0 .LBB2_4 ; %bb.3: v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[5:6], 2, v[1:2] v_add_co_u32 v7, vcc_lo, s6, v5 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo v_add_co_u32 v5, vcc_lo, s4, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo global_load_b32 v15, v[7:8], off global_load_b32 v17, v[5:6], off s_branch .LBB2_5 .LBB2_4: s_mov_b32 s2, -1 ; implicit-def: $vgpr17 ; implicit-def: $vgpr15 .LBB2_5: ; %Flow420 s_delay_alu instid0(VALU_DEP_1) v_sub_nc_u32_e32 v5, v1, v4 s_and_not1_b32 vcc_lo, exec_lo, s2 s_cbranch_vccnz .LBB2_21 ; %bb.6: s_clause 0x1 s_load_b128 s[16:19], s[0:1], 0xc8 s_load_b32 s2, s[0:1], 0x48 ; implicit-def: $vgpr17 ; implicit-def: $vgpr15 s_waitcnt lgkmcnt(0) s_sub_i32 s3, 1, s19 s_add_i32 s10, s16, s2 s_mul_i32 s3, s3, s17 s_add_i32 s2, s18, s2 s_sub_i32 s3, s3, s10 v_subrev_nc_u32_e32 v4, s2, v5 v_add_nc_u32_e32 v2, s3, v3 s_mov_b32 s2, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, v2, v2 v_mad_u64_u32 v[6:7], null, v4, v4, v[2:3] s_delay_alu instid0(VALU_DEP_1) v_cmpx_lt_u32_e32 0xe1, v6 s_xor_b32 s2, exec_lo, s2 s_cbranch_execz .LBB2_8 ; %bb.7: v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 2, v[1:2] v_add_co_u32 v8, vcc_lo, s6, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo v_add_co_u32 v6, vcc_lo, s4, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo global_load_b32 v15, v[8:9], off global_load_b32 v17, v[6:7], off ; implicit-def: $vgpr6_vgpr7 .LBB2_8: ; %Flow418 s_and_not1_saveexec_b32 s10, s2 s_cbranch_execz .LBB2_20 ; %bb.9: s_waitcnt vmcnt(0) v_mov_b32_e32 v17, 0 v_mov_b32_e32 v15, 0 s_mov_b32 s11, exec_lo v_cmpx_lt_u32_e32 16, v6 s_cbranch_execz .LBB2_19 ; %bb.10: v_cvt_f32_i32_e32 v2, v6 s_mov_b32 s3, 0x400921fb s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f32_e32 v4, 0x4f800000, v2 v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2 v_cndmask_b32_e32 v2, v2, v4, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_sqrt_f32_e32 v4, v2 s_waitcnt_depctr 0xfff v_add_nc_u32_e32 v6, -1, v4 v_add_nc_u32_e32 v7, 1, v4 v_fma_f32 v8, -v6, v4, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v9, -v7, v4, v2 v_cmp_ge_f32_e64 s2, 0, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v4, v4, v6, s2 v_cmp_lt_f32_e64 s2, 0, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v4, v4, v7, s2 s_mov_b32 s2, 0x542fe938 v_mul_f32_e32 v6, 0x37800000, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v4, v4, v6, vcc_lo v_cmp_class_f32_e64 vcc_lo, v2, 0x260 v_cndmask_b32_e32 v2, v4, v2, vcc_lo ; implicit-def: $vgpr4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v2, -4.0, v2 v_cvt_f64_f32_e32 v[6:7], v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[6:7], v[6:7], 4.0 v_div_scale_f64 v[8:9], null, 0x40460000, 0x40460000, v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[10:11], v[8:9] s_waitcnt_depctr 0xfff v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0 v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0 v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] v_div_scale_f64 v[12:13], vcc_lo, v[6:7], 0x40460000, v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[14:15], v[12:13], v[10:11] v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15] ; implicit-def: $vgpr10_vgpr11 v_div_fixup_f64 v[6:7], v[8:9], 0x40460000, v[6:7] ; implicit-def: $vgpr8_vgpr9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[6:7], v[6:7], s[2:3] v_cmp_ngt_f64_e64 s3, 0x41d00000, |v[6:7]| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s2, s3 s_xor_b32 s12, exec_lo, s2 s_cbranch_execz .LBB2_12 ; %bb.11: v_ldexp_f64 v[8:9], |v[6:7]|, 0xffffff80 v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[6:7]| v_trig_preop_f64 v[10:11], |v[6:7]|, 0 v_and_b32_e32 v2, 0x7fffffff, v7 v_trig_preop_f64 v[12:13], |v[6:7]|, 1 v_trig_preop_f64 v[22:23], |v[6:7]|, 2 v_mov_b32_e32 v30, 0 s_mov_b32 s17, 0x3ff921fb s_mov_b32 s16, 0x54442d18 s_mov_b32 s19, 0x3c91a626 s_mov_b32 s18, 0x33145c07 v_cndmask_b32_e32 v9, v2, v9, vcc_lo v_cndmask_b32_e32 v8, v6, v8, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f64 v[14:15], v[10:11], v[8:9] v_mul_f64 v[16:17], v[12:13], v[8:9] v_fma_f64 v[10:11], v[10:11], v[8:9], -v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[12:13], v[12:13], v[8:9], -v[16:17] v_add_f64 v[18:19], v[16:17], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[18:19], -v[16:17] v_add_f64 v[26:27], v[14:15], v[18:19] v_add_f64 v[24:25], v[18:19], -v[20:21] v_add_f64 v[10:11], v[10:11], -v[20:21] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_ldexp_f64 v[20:21], v[26:27], -2 v_add_f64 v[14:15], v[26:27], -v[14:15] v_add_f64 v[16:17], v[16:17], -v[24:25] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[20:21]| v_add_f64 v[14:15], v[18:19], -v[14:15] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[10:11], v[10:11], v[16:17] v_fract_f64_e32 v[16:17], v[20:21] v_cndmask_b32_e32 v16, 0, v16, vcc_lo v_mul_f64 v[28:29], v[22:23], v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v17, 0, v17, vcc_lo v_ldexp_f64 v[16:17], v[16:17], 2 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[24:25], v[28:29], v[12:13] v_fma_f64 v[8:9], v[22:23], v[8:9], -v[28:29] v_add_f64 v[18:19], v[24:25], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[14:15], v[18:19] v_add_f64 v[26:27], v[20:21], v[16:17] v_add_f64 v[14:15], v[20:21], -v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cmp_gt_f64_e32 vcc_lo, 0, v[26:27] v_add_f64 v[26:27], v[24:25], -v[28:29] v_add_f64 v[14:15], v[18:19], -v[14:15] v_cndmask_b32_e64 v31, 0, 0x40100000, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[35:36], v[24:25], -v[26:27] v_add_f64 v[12:13], v[12:13], -v[26:27] v_add_f64 v[16:17], v[16:17], v[30:31] v_add_f64 v[31:32], v[18:19], -v[24:25] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[26:27], v[28:29], -v[35:36] v_add_f64 v[33:34], v[20:21], v[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[37:38], v[18:19], -v[31:32] v_add_f64 v[10:11], v[10:11], -v[31:32] v_add_f64 v[12:13], v[12:13], v[26:27] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cvt_i32_f64_e32 v2, v[33:34] v_add_f64 v[24:25], v[24:25], -v[37:38] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_f64_i32_e32 v[31:32], v2 v_add_f64 v[10:11], v[10:11], v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[16:17], -v[31:32] v_add_f64 v[10:11], v[12:13], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[12:13], v[20:21], v[16:17] v_add_f64 v[8:9], v[8:9], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[10:11], v[12:13], -v[16:17] v_cmp_le_f64_e32 vcc_lo, 0.5, v[12:13] v_add_f64 v[8:9], v[14:15], v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_f64 v[10:11], v[20:21], -v[10:11] v_cndmask_b32_e64 v31, 0, 0x3ff00000, vcc_lo v_add_co_ci_u32_e64 v4, s2, 0, v2, vcc_lo v_add_f64 v[8:9], v[8:9], v[10:11] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[10:11], v[12:13], -v[30:31] v_add_f64 v[12:13], v[10:11], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f64 v[14:15], v[12:13], s[16:17] v_add_f64 v[10:11], v[12:13], -v[10:11] v_fma_f64 v[16:17], v[12:13], s[16:17], -v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[8:9], v[8:9], -v[10:11] v_fma_f64 v[10:11], v[12:13], s[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[10:11], v[8:9], s[16:17], v[10:11] v_add_f64 v[8:9], v[14:15], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[12:13], v[8:9], -v[14:15] v_add_f64 v[10:11], v[10:11], -v[12:13] .LBB2_12: ; %Flow416 s_and_not1_saveexec_b32 s2, s12 s_cbranch_execz .LBB2_14 ; %bb.13: s_mov_b32 s13, 0x3fe45f30 s_mov_b32 s12, 0x6dc9c883 s_mov_b32 s17, 0xbc91a626 v_mul_f64 v[8:9], |v[6:7]|, s[12:13] s_mov_b32 s13, 0xbff921fb s_mov_b32 s12, 0x54442d18 s_mov_b32 s16, 0x33145c00 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f64_e32 v[12:13], v[8:9] v_fma_f64 v[8:9], v[12:13], s[12:13], |v[6:7]| v_mul_f64 v[10:11], v[12:13], s[16:17] s_mov_b32 s13, 0xb97b839a s_mov_b32 s12, 0x252049c0 v_cvt_i32_f64_e32 v4, v[12:13] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[16:17], v[12:13], s[16:17], v[8:9] v_add_f64 v[14:15], v[8:9], v[10:11] s_mov_b32 s17, 0x3c91a626 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[8:9], v[8:9], -v[14:15] v_add_f64 v[14:15], v[14:15], -v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[8:9], v[8:9], v[10:11] v_fma_f64 v[10:11], v[12:13], s[16:17], v[10:11] v_add_f64 v[8:9], v[14:15], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[8:9], -v[10:11] v_fma_f64 v[10:11], v[12:13], s[12:13], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[16:17], v[10:11] v_add_f64 v[14:15], v[8:9], -v[16:17] s_delay_alu instid0(VALU_DEP_1) v_add_f64 v[10:11], v[10:11], -v[14:15] .LBB2_14: ; %_ZL3cosd.exit s_or_b32 exec_lo, exec_lo, s2 v_mov_b32_e32 v2, 0 ; implicit-def: $vgpr17 ; implicit-def: $vgpr14_vgpr15 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[12:13], 2, v[1:2] v_add_co_u32 v12, vcc_lo, s6, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo global_load_b32 v16, v[12:13], off ; implicit-def: $vgpr12_vgpr13 s_and_saveexec_b32 s2, s3 s_xor_b32 s3, exec_lo, s2 s_cbranch_execz .LBB2_16 ; %bb.15: v_ldexp_f64 v[12:13], |v[6:7]|, 0xffffff80 v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[6:7]| v_trig_preop_f64 v[14:15], |v[6:7]|, 0 v_and_b32_e32 v17, 0x7fffffff, v7 v_trig_preop_f64 v[27:28], |v[6:7]|, 2 v_mov_b32_e32 v35, 0 s_mov_b32 s7, 0x3ff921fb s_mov_b32 s6, 0x54442d18 s_mov_b32 s13, 0x3c91a626 s_mov_b32 s12, 0x33145c07 v_dual_cndmask_b32 v12, v6, v12 :: v_dual_cndmask_b32 v13, v17, v13 v_trig_preop_f64 v[17:18], |v[6:7]|, 1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[19:20], v[14:15], v[12:13] v_mul_f64 v[21:22], v[17:18], v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[14:15], v[14:15], v[12:13], -v[19:20] v_fma_f64 v[17:18], v[17:18], v[12:13], -v[21:22] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[23:24], v[21:22], v[14:15] v_add_f64 v[25:26], v[23:24], -v[21:22] v_add_f64 v[31:32], v[19:20], v[23:24] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[29:30], v[23:24], -v[25:26] v_add_f64 v[14:15], v[14:15], -v[25:26] v_ldexp_f64 v[25:26], v[31:32], -2 v_add_f64 v[19:20], v[31:32], -v[19:20] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[21:22], v[21:22], -v[29:30] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[25:26]| s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[19:20], v[23:24], -v[19:20] v_add_f64 v[14:15], v[14:15], v[21:22] v_fract_f64_e32 v[21:22], v[25:26] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v22, 0, v22, vcc_lo v_mul_f64 v[33:34], v[27:28], v[12:13] v_cndmask_b32_e32 v21, 0, v21, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_ldexp_f64 v[21:22], v[21:22], 2 v_add_f64 v[29:30], v[33:34], v[17:18] v_fma_f64 v[12:13], v[27:28], v[12:13], -v[33:34] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[23:24], v[29:30], v[14:15] v_add_f64 v[25:26], v[19:20], v[23:24] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[31:32], v[25:26], v[21:22] v_add_f64 v[19:20], v[25:26], -v[19:20] v_cmp_gt_f64_e32 vcc_lo, 0, v[31:32] v_add_f64 v[31:32], v[29:30], -v[33:34] v_cndmask_b32_e64 v36, 0, 0x40100000, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[40:41], v[29:30], -v[31:32] v_add_f64 v[17:18], v[17:18], -v[31:32] v_add_f64 v[21:22], v[21:22], v[35:36] v_add_f64 v[36:37], v[23:24], -v[29:30] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[31:32], v[33:34], -v[40:41] v_add_f64 v[38:39], v[25:26], v[21:22] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[42:43], v[23:24], -v[36:37] v_add_f64 v[14:15], v[14:15], -v[36:37] v_add_f64 v[17:18], v[17:18], v[31:32] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cvt_i32_f64_e32 v38, v[38:39] v_add_f64 v[29:30], v[29:30], -v[42:43] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_f64_i32_e32 v[36:37], v38 v_add_f64 v[14:15], v[14:15], v[29:30] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[21:22], v[21:22], -v[36:37] v_add_f64 v[14:15], v[17:18], v[14:15] v_add_f64 v[17:18], v[23:24], -v[19:20] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[27:28], v[25:26], v[21:22] v_add_f64 v[12:13], v[12:13], v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[14:15], v[27:28], -v[21:22] v_cmp_le_f64_e32 vcc_lo, 0.5, v[27:28] v_add_f64 v[12:13], v[17:18], v[12:13] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_f64 v[14:15], v[25:26], -v[14:15] v_cndmask_b32_e64 v36, 0, 0x3ff00000, vcc_lo v_add_co_ci_u32_e64 v17, s2, 0, v38, vcc_lo v_add_f64 v[12:13], v[12:13], v[14:15] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[14:15], v[27:28], -v[35:36] v_add_f64 v[18:19], v[14:15], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f64 v[20:21], v[18:19], s[6:7] v_add_f64 v[14:15], v[18:19], -v[14:15] v_fma_f64 v[22:23], v[18:19], s[6:7], -v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[12:13], v[12:13], -v[14:15] v_fma_f64 v[14:15], v[18:19], s[12:13], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], v[12:13], s[6:7], v[14:15] v_add_f64 v[12:13], v[20:21], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[12:13], -v[20:21] v_add_f64 v[14:15], v[14:15], -v[18:19] .LBB2_16: ; %Flow415 s_and_not1_saveexec_b32 s2, s3 s_cbranch_execz .LBB2_18 ; %bb.17: s_mov_b32 s7, 0x3fe45f30 s_mov_b32 s6, 0x6dc9c883 s_mov_b32 s13, 0xbc91a626 v_mul_f64 v[12:13], |v[6:7]|, s[6:7] s_mov_b32 s7, 0xbff921fb s_mov_b32 s6, 0x54442d18 s_mov_b32 s12, 0x33145c00 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f64_e32 v[17:18], v[12:13] v_fma_f64 v[12:13], v[17:18], s[6:7], |v[6:7]| v_mul_f64 v[14:15], v[17:18], s[12:13] s_mov_b32 s7, 0xb97b839a s_mov_b32 s6, 0x252049c0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[21:22], v[17:18], s[12:13], v[12:13] v_add_f64 v[19:20], v[12:13], v[14:15] s_mov_b32 s13, 0x3c91a626 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[12:13], v[12:13], -v[19:20] v_add_f64 v[19:20], v[19:20], -v[21:22] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[12:13], v[12:13], v[14:15] v_fma_f64 v[14:15], v[17:18], s[12:13], v[14:15] v_add_f64 v[12:13], v[19:20], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[12:13], v[12:13], -v[14:15] v_fma_f64 v[14:15], v[17:18], s[6:7], v[12:13] v_cvt_i32_f64_e32 v17, v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[12:13], v[21:22], v[14:15] v_add_f64 v[19:20], v[12:13], -v[21:22] s_delay_alu instid0(VALU_DEP_1) v_add_f64 v[14:15], v[14:15], -v[19:20] .LBB2_18: ; %_ZL3cosd.exit248 s_or_b32 exec_lo, exec_lo, s2 v_mul_f64 v[18:19], v[8:9], v[8:9] v_mul_f64 v[20:21], v[12:13], v[12:13] s_mov_b32 s3, 0xbe5ae600 s_mov_b32 s2, 0xb42fdfa7 s_mov_b32 s7, 0x3de5e0b2 s_mov_b32 s6, 0xf9a43bb8 s_mov_b32 s13, 0x3ec71de3 s_mov_b32 s12, 0x796cde01 v_lshlrev_b64 v[30:31], 2, v[1:2] v_mul_f64 v[38:39], v[10:11], 0.5 v_mul_f64 v[44:45], v[14:15], 0.5 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v30, vcc_lo, s4, v30 v_add_co_ci_u32_e32 v31, vcc_lo, s5, v31, vcc_lo s_mov_b32 s5, 0xbf2a01a0 s_mov_b32 s4, 0x19e83e5c global_load_b32 v2, v[30:31], off v_fma_f64 v[22:23], v[18:19], s[6:7], s[2:3] v_fma_f64 v[24:25], v[20:21], s[6:7], s[2:3] v_mul_f64 v[28:29], v[18:19], 0.5 s_mov_b32 s3, 0x3e21eeb6 s_mov_b32 s2, 0x9037ab78 s_mov_b32 s7, 0xbda907db s_mov_b32 s6, 0x46cc5e42 v_mul_f64 v[32:33], v[20:21], 0.5 v_fma_f64 v[26:27], v[18:19], s[6:7], s[2:3] v_fma_f64 v[30:31], v[20:21], s[6:7], s[2:3] s_mov_b32 s3, 0xbe927e4f s_mov_b32 s2, 0xa17f65f6 v_mul_f64 v[40:41], v[8:9], -v[18:19] v_mul_f64 v[46:47], v[12:13], -v[20:21] v_fma_f64 v[22:23], v[18:19], v[22:23], s[12:13] v_fma_f64 v[24:25], v[20:21], v[24:25], s[12:13] v_add_f64 v[34:35], -v[28:29], 1.0 v_add_f64 v[36:37], -v[32:33], 1.0 v_fma_f64 v[26:27], v[18:19], v[26:27], s[2:3] v_fma_f64 v[30:31], v[20:21], v[30:31], s[2:3] s_mov_b32 s3, 0x3f811111 s_mov_b32 s2, 0x11110bb3 v_fma_f64 v[22:23], v[18:19], v[22:23], s[4:5] v_fma_f64 v[24:25], v[20:21], v[24:25], s[4:5] v_add_f64 v[42:43], -v[34:35], 1.0 s_mov_b32 s5, 0x3efa01a0 s_mov_b32 s4, 0x19f4ec90 v_add_f64 v[48:49], -v[36:37], 1.0 v_fma_f64 v[26:27], v[18:19], v[26:27], s[4:5] v_fma_f64 v[30:31], v[20:21], v[30:31], s[4:5] v_fma_f64 v[22:23], v[18:19], v[22:23], s[2:3] v_fma_f64 v[24:25], v[20:21], v[24:25], s[2:3] v_add_f64 v[28:29], v[42:43], -v[28:29] s_mov_b32 s3, 0xbf56c16c s_mov_b32 s2, 0x16c16967 v_add_f64 v[32:33], v[48:49], -v[32:33] v_fma_f64 v[26:27], v[18:19], v[26:27], s[2:3] v_fma_f64 v[30:31], v[20:21], v[30:31], s[2:3] s_mov_b32 s3, 0x3fa55555 s_mov_b32 s2, 0x55555555 v_fma_f64 v[22:23], v[40:41], v[22:23], v[38:39] v_fma_f64 v[24:25], v[46:47], v[24:25], v[44:45] v_fma_f64 v[28:29], v[8:9], -v[10:11], v[28:29] v_mul_f64 v[38:39], v[18:19], v[18:19] v_fma_f64 v[26:27], v[18:19], v[26:27], s[2:3] v_fma_f64 v[10:11], v[18:19], v[22:23], -v[10:11] v_fma_f64 v[18:19], v[20:21], v[24:25], -v[14:15] v_mul_f64 v[22:23], v[20:21], v[20:21] v_fma_f64 v[20:21], v[20:21], v[30:31], s[2:3] v_fma_f64 v[14:15], v[12:13], -v[14:15], v[32:33] s_mov_b32 s3, 0xbfc55555 v_fma_f64 v[24:25], v[38:39], v[26:27], v[28:29] v_fma_f64 v[10:11], v[40:41], s[2:3], v[10:11] v_fma_f64 v[18:19], v[46:47], s[2:3], v[18:19] v_cmp_class_f64_e64 s2, v[6:7], 0x1f8 v_and_b32_e32 v6, 1, v17 v_fma_f64 v[14:15], v[22:23], v[20:21], v[14:15] v_lshlrev_b32_e32 v7, 30, v17 v_add_f64 v[20:21], v[34:35], v[24:25] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_eq_u32_e64 s3, 0, v6 v_and_b32_e32 v6, 0x80000000, v7 v_add_f64 v[8:9], v[8:9], -v[10:11] v_add_f64 v[10:11], v[12:13], -v[18:19] v_add_f64 v[12:13], v[36:37], v[14:15] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_xor_b32_e32 v9, 0x80000000, v9 v_and_b32_e32 v14, 1, v4 v_lshlrev_b32_e32 v4, 30, v4 v_xor_b32_e32 v11, 0x80000000, v11 v_cmp_eq_u32_e32 vcc_lo, 0, v14 s_delay_alu instid0(VALU_DEP_3) v_dual_cndmask_b32 v7, v9, v21 :: v_dual_and_b32 v4, 0x80000000, v4 v_cndmask_b32_e32 v8, v8, v20, vcc_lo v_cndmask_b32_e64 v9, v10, v12, s3 v_cndmask_b32_e64 v10, v11, v13, s3 s_waitcnt vmcnt(0) v_cvt_f64_f32_e32 v[12:13], v2 v_xor_b32_e32 v4, v7, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_xor_b32_e32 v10, v10, v6 v_cndmask_b32_e64 v6, 0, v8, s2 v_cndmask_b32_e64 v8, 0, v9, s2 v_cndmask_b32_e64 v7, 0x7ff80000, v4, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v9, 0x7ff80000, v10, s2 v_cvt_f64_f32_e32 v[10:11], v16 v_add_f64 v[6:7], -v[6:7], 1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[8:9], -v[8:9], 1.0 v_mul_f64 v[6:7], v[6:7], 0.5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[8:9], v[8:9], 0.5 v_mul_f64 v[6:7], v[6:7], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[8:9], v[8:9], v[12:13] v_cvt_f32_f64_e32 v15, v[6:7] s_delay_alu instid0(VALU_DEP_2) v_cvt_f32_f64_e32 v17, v[8:9] .LBB2_19: ; %Flow417 s_or_b32 exec_lo, exec_lo, s11 .LBB2_20: ; %Flow419 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s10 .LBB2_21: v_cmp_lt_i32_e32 vcc_lo, 3, v3 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB2_58 ; %bb.22: s_add_i32 s2, s8, -4 s_add_i32 s3, s9, -4 v_cmp_gt_i32_e32 vcc_lo, s2, v3 v_cmp_gt_i32_e64 s2, s3, v5 v_cmp_lt_i32_e64 s3, 3, v5 s_delay_alu instid0(VALU_DEP_2) s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_b32 s2, s2, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 exec_lo, exec_lo, s2 s_cbranch_execz .LBB2_58 ; %bb.23: ; %.preheader.preheader s_load_b128 s[4:7], s[0:1], 0x20 v_ashrrev_i32_e32 v2, 31, v1 s_ashr_i32 s3, s9, 31 s_mov_b32 s2, s9 v_dual_mov_b32 v9, v0 :: v_dual_mov_b32 v20, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) v_lshlrev_b64 v[6:7], 2, v[1:2] s_lshl_b64 s[2:3], s[2:3], 2 v_dual_mov_b32 v21, 0 :: v_dual_add_nc_u32 v2, -1, v0 v_mov_b32_e32 v19, 0 s_mov_b64 s[10:11], 0 v_sub_co_u32 v4, vcc_lo, v6, s2 v_subrev_co_ci_u32_e32 v8, vcc_lo, s3, v7, vcc_lo v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v22, 0 .LBB2_24: ; %.preheader ; =>This Inner Loop Header: Depth=1 v_add_nc_u32_e32 v6, s15, v9 v_add_nc_u32_e32 v10, s15, v0 v_add_nc_u32_e32 v23, s15, v2 s_waitcnt lgkmcnt(0) v_add_co_u32 v12, vcc_lo, s4, v4 v_lshlrev_b64 v[27:28], 2, v[6:7] v_ashrrev_i32_e32 v11, 31, v10 v_add_co_ci_u32_e32 v13, vcc_lo, s5, v8, vcc_lo v_add_co_u32 v25, vcc_lo, s6, v4 v_ashrrev_i32_e32 v24, 31, v23 v_add_co_ci_u32_e32 v26, vcc_lo, s7, v8, vcc_lo v_lshlrev_b64 v[10:11], 2, v[10:11] v_add_co_u32 v29, vcc_lo, s4, v27 v_add_co_ci_u32_e32 v30, vcc_lo, s5, v28, vcc_lo v_lshlrev_b64 v[23:24], 2, v[23:24] v_add_co_u32 v27, vcc_lo, s6, v27 v_add_co_ci_u32_e32 v28, vcc_lo, s7, v28, vcc_lo v_add_co_u32 v31, vcc_lo, s4, v10 v_add_co_ci_u32_e32 v32, vcc_lo, s5, v11, vcc_lo v_add_co_u32 v33, vcc_lo, s4, v23 v_add_co_ci_u32_e32 v34, vcc_lo, s5, v24, vcc_lo v_add_co_u32 v23, vcc_lo, s6, v23 v_add_co_ci_u32_e32 v24, vcc_lo, s7, v24, vcc_lo v_add_co_u32 v10, vcc_lo, s6, v10 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo global_load_b32 v6, v[27:28], off s_clause 0x3 global_load_b32 v14, v[31:32], off global_load_b32 v12, v[12:13], off global_load_b32 v13, v[29:30], off global_load_b32 v16, v[33:34], off s_clause 0x2 global_load_b32 v18, v[23:24], off global_load_b32 v10, v[10:11], off global_load_b32 v11, v[25:26], off s_getpc_b64 s[12:13] s_add_u32 s12, s12, c@rel32@lo+4 s_addc_u32 s13, s13, c@rel32@hi+12 s_add_u32 s12, s10, s12 s_addc_u32 s13, s11, s13 v_add_nc_u32_e32 v9, 1, v9 s_load_b32 s8, s[12:13], 0x0 v_sub_co_u32 v4, vcc_lo, v4, s2 v_subrev_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo s_add_u32 s10, s10, 4 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s10, 16 s_waitcnt vmcnt(5) v_sub_f32_e32 v12, v14, v12 s_waitcnt vmcnt(3) v_dual_sub_f32 v13, v13, v16 :: v_dual_add_nc_u32 v2, -1, v2 s_waitcnt vmcnt(2) lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) v_dual_sub_f32 v6, v6, v18 :: v_dual_fmac_f32 v19, s8, v12 s_waitcnt vmcnt(0) v_sub_f32_e32 v10, v10, v11 v_add_nc_u32_e32 v0, s9, v0 v_fmac_f32_e32 v20, s8, v13 v_fmac_f32_e32 v22, s8, v6 s_delay_alu instid0(VALU_DEP_4) v_fmac_f32_e32 v21, s8, v10 s_cbranch_scc1 .LBB2_24 ; %bb.25: s_clause 0x1 s_load_b256 s[4:11], s[0:1], 0x90 s_load_b64 s[2:3], s[0:1], 0x58 v_mov_b32_e32 v4, 0 s_clause 0x1 s_load_b64 s[12:13], s[0:1], 0x40 s_load_b64 s[14:15], s[0:1], 0xc0 ; implicit-def: $vgpr29 ; implicit-def: $vgpr28 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_mov_b32_e32 v6, v4 v_lshlrev_b64 v[7:8], 2, v[3:4] v_mov_b32_e32 v2, v4 v_lshlrev_b64 v[9:10], 2, v[5:6] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_lshlrev_b64 v[13:14], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v3, vcc_lo, s6, v7 v_add_co_ci_u32_e32 v4, vcc_lo, s7, v8, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v5, vcc_lo, s10, v9 v_add_co_ci_u32_e32 v6, vcc_lo, s11, v10, vcc_lo v_add_co_u32 v25, vcc_lo, s2, v13 v_add_co_ci_u32_e32 v26, vcc_lo, s3, v14, vcc_lo v_add_co_u32 v7, vcc_lo, s4, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo v_add_co_u32 v11, vcc_lo, s14, v13 v_add_co_ci_u32_e32 v12, vcc_lo, s15, v14, vcc_lo v_add_co_u32 v9, vcc_lo, s8, v9 v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo v_add_co_u32 v13, vcc_lo, s12, v13 global_load_b32 v0, v[11:12], off v_add_co_ci_u32_e32 v14, vcc_lo, s13, v14, vcc_lo global_load_b32 v16, v[3:4], off global_load_b32 v24, v[5:6], off global_load_b32 v18, v[25:26], off global_load_b32 v23, v[7:8], off global_load_b32 v26, v[9:10], off global_load_b32 v25, v[13:14], off s_waitcnt vmcnt(6) v_and_b32_e32 v27, 0x7fffffff, v0 v_cmp_ngt_f32_e64 s4, 0x48000000, |v0| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s2, s4 s_xor_b32 s5, exec_lo, s2 s_cbranch_execz .LBB2_27 ; %bb.26: s_mov_b32 s2, 0x7fffff v_mov_b32_e32 v30, 0 v_and_or_b32 v38, v27, s2, 0x800000 v_lshrrev_b32_e32 v35, 23, v27 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[28:29], null, v38, 0xfe5163ab, 0 v_add_nc_u32_e32 v36, 0xffffff88, v35 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_lt_u32_e32 vcc_lo, 63, v36 v_mad_u64_u32 v[31:32], null, v38, 0x3c439041, v[29:30] v_cndmask_b32_e64 v37, 0, 0xffffffc0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mov_b32_e32 v29, v32 v_add_nc_u32_e32 v37, v37, v36 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[32:33], null, v38, 0xdb629599, v[29:30] v_cmp_lt_u32_e64 s2, 31, v37 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v39, 0, 0xffffffe0, s2 v_dual_mov_b32 v29, v33 :: v_dual_cndmask_b32 v28, v32, v28 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v39, v39, v37 v_mad_u64_u32 v[33:34], null, v38, 0xf534ddc0, v[29:30] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_lt_u32_e64 s3, 31, v39 v_mov_b32_e32 v29, v34 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v31, v33, v31, vcc_lo v_mad_u64_u32 v[34:35], null, v38, 0xfc2757d1, v[29:30] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v28, v31, v28, s2 v_mov_b32_e32 v29, v35 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[35:36], null, v38, 0x4e441529, v[29:30] v_mov_b32_e32 v29, v36 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[36:37], null, v38, 0xa2f9836e, v[29:30] v_cndmask_b32_e64 v29, 0, 0xffffffe0, s3 v_dual_cndmask_b32 v30, v35, v33 :: v_dual_add_nc_u32 v29, v29, v39 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v36, v36, v34 :: v_dual_cndmask_b32 v35, v37, v35 v_cndmask_b32_e32 v34, v34, v32, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v29 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v33, v36, v30, s2 v_cndmask_b32_e64 v35, v35, v36, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v30, v30, v34, s2 v_sub_nc_u32_e32 v36, 32, v29 v_cndmask_b32_e64 v34, v34, v31, s2 v_cndmask_b32_e64 v35, v35, v33, s3 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v33, v33, v30, s3 v_cndmask_b32_e64 v30, v30, v34, s3 v_cndmask_b32_e64 v28, v34, v28, s3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v37, v35, v33, v36 v_alignbit_b32 v32, v33, v30, v36 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v29, v37, v35, vcc_lo v_alignbit_b32 v35, v30, v28, v36 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v31, v32, v33, vcc_lo v_bfe_u32 v32, v29, 29, 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v30, v35, v30, vcc_lo v_alignbit_b32 v33, v29, v31, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_sub_nc_u32_e32 v34, 0, v32 v_alignbit_b32 v31, v31, v30, 30 v_alignbit_b32 v28, v30, v28, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v33, v33, v34 v_xor_b32_e32 v30, v31, v34 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v28, v28, v34 v_clz_i32_u32_e32 v35, v33 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_min_u32_e32 v35, 32, v35 v_sub_nc_u32_e32 v31, 31, v35 v_lshlrev_b32_e32 v37, 23, v35 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_alignbit_b32 v33, v33, v30, v31 v_alignbit_b32 v28, v30, v28, v31 v_lshrrev_b32_e32 v31, 29, v29 v_alignbit_b32 v30, v33, v28, 9 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b32_e32 v31, 31, v31 v_lshrrev_b32_e32 v33, 9, v33 v_clz_i32_u32_e32 v34, v30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_or_b32_e32 v36, 0.5, v31 v_min_u32_e32 v34, 32, v34 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v36, v36, v37 v_sub_nc_u32_e32 v38, 31, v34 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v28, v30, v28, v38 v_or_b32_e32 v30, v33, v36 v_add_lshl_u32 v33, v34, v35, 23 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshrrev_b32_e32 v28, 9, v28 v_mul_f32_e32 v34, 0x3fc90fda, v30 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v28, v28, v33 v_fma_f32 v33, v30, 0x3fc90fda, -v34 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v28, 0x33000000, v28 v_fmamk_f32 v30, v30, 0x33a22168, v33 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_or_b32_e32 v28, v28, v31 v_fmac_f32_e32 v30, 0x3fc90fda, v28 v_lshrrev_b32_e32 v29, 30, v29 s_delay_alu instid0(VALU_DEP_1) v_dual_add_f32 v28, v34, v30 :: v_dual_add_nc_u32 v29, v32, v29 .LBB2_27: ; %Flow412 s_and_not1_saveexec_b32 s2, s5 ; %bb.28: v_mul_f32_e64 v28, 0x3f22f983, |v0| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f32_e32 v29, v28 v_fma_f32 v28, v29, 0xbfc90fda, |v0| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v28, v29, 0xb3a22168, v28 v_fmamk_f32 v28, v29, 0xa7c234c4, v28 v_cvt_i32_f32_e32 v29, v29 ; %bb.29: ; %_ZL3cosf.exit s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $vgpr31 ; implicit-def: $vgpr30 s_and_saveexec_b32 s2, s4 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s4, exec_lo, s2 s_cbranch_execz .LBB2_31 ; %bb.30: s_mov_b32 s2, 0x7fffff v_mov_b32_e32 v32, 0 v_and_or_b32 v40, v27, s2, 0x800000 v_lshrrev_b32_e32 v37, 23, v27 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[30:31], null, v40, 0xfe5163ab, 0 v_add_nc_u32_e32 v38, 0xffffff88, v37 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_lt_u32_e32 vcc_lo, 63, v38 v_mad_u64_u32 v[33:34], null, v40, 0x3c439041, v[31:32] v_cndmask_b32_e64 v39, 0, 0xffffffc0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mov_b32_e32 v31, v34 v_add_nc_u32_e32 v39, v39, v38 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[34:35], null, v40, 0xdb629599, v[31:32] v_cmp_lt_u32_e64 s2, 31, v39 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v41, 0, 0xffffffe0, s2 v_dual_mov_b32 v31, v35 :: v_dual_cndmask_b32 v30, v34, v30 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v41, v41, v39 v_mad_u64_u32 v[35:36], null, v40, 0xf534ddc0, v[31:32] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_lt_u32_e64 s3, 31, v41 v_mov_b32_e32 v31, v36 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v33, v35, v33, vcc_lo v_mad_u64_u32 v[36:37], null, v40, 0xfc2757d1, v[31:32] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v30, v33, v30, s2 v_mov_b32_e32 v31, v37 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[37:38], null, v40, 0x4e441529, v[31:32] v_mov_b32_e32 v31, v38 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[38:39], null, v40, 0xa2f9836e, v[31:32] v_cndmask_b32_e64 v31, 0, 0xffffffe0, s3 v_dual_cndmask_b32 v32, v37, v35 :: v_dual_add_nc_u32 v31, v31, v41 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v38, v38, v36 :: v_dual_cndmask_b32 v37, v39, v37 v_cndmask_b32_e32 v36, v36, v34, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v31 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v35, v38, v32, s2 v_cndmask_b32_e64 v37, v37, v38, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v32, v32, v36, s2 v_sub_nc_u32_e32 v38, 32, v31 v_cndmask_b32_e64 v36, v36, v33, s2 v_cndmask_b32_e64 v37, v37, v35, s3 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v35, v35, v32, s3 v_cndmask_b32_e64 v32, v32, v36, s3 v_cndmask_b32_e64 v30, v36, v30, s3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v39, v37, v35, v38 v_alignbit_b32 v34, v35, v32, v38 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v31, v39, v37, vcc_lo v_alignbit_b32 v37, v32, v30, v38 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v33, v34, v35, vcc_lo v_bfe_u32 v34, v31, 29, 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v32, v37, v32, vcc_lo v_alignbit_b32 v35, v31, v33, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_sub_nc_u32_e32 v36, 0, v34 v_alignbit_b32 v33, v33, v32, 30 v_alignbit_b32 v30, v32, v30, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v35, v35, v36 v_xor_b32_e32 v32, v33, v36 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v30, v30, v36 v_clz_i32_u32_e32 v37, v35 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_min_u32_e32 v37, 32, v37 v_sub_nc_u32_e32 v33, 31, v37 v_lshlrev_b32_e32 v39, 23, v37 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_alignbit_b32 v35, v35, v32, v33 v_alignbit_b32 v30, v32, v30, v33 v_lshrrev_b32_e32 v33, 29, v31 v_alignbit_b32 v32, v35, v30, 9 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b32_e32 v33, 31, v33 v_lshrrev_b32_e32 v35, 9, v35 v_clz_i32_u32_e32 v36, v32 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_or_b32_e32 v38, 0.5, v33 v_min_u32_e32 v36, 32, v36 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v38, v38, v39 v_sub_nc_u32_e32 v40, 31, v36 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v30, v32, v30, v40 v_or_b32_e32 v32, v35, v38 v_add_lshl_u32 v35, v36, v37, 23 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshrrev_b32_e32 v30, 9, v30 v_mul_f32_e32 v36, 0x3fc90fda, v32 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v30, v30, v35 v_fma_f32 v35, v32, 0x3fc90fda, -v36 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v30, 0x33000000, v30 v_fmamk_f32 v32, v32, 0x33a22168, v35 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_or_b32_e32 v30, v30, v33 v_fmac_f32_e32 v32, 0x3fc90fda, v30 v_lshrrev_b32_e32 v31, 30, v31 s_delay_alu instid0(VALU_DEP_1) v_dual_add_f32 v30, v36, v32 :: v_dual_add_nc_u32 v31, v34, v31 .LBB2_31: ; %Flow411 s_and_not1_saveexec_b32 s2, s4 ; %bb.32: v_mul_f32_e64 v30, 0x3f22f983, |v0| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f32_e32 v31, v30 v_fma_f32 v30, v31, 0xbfc90fda, |v0| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v30, v31, 0xb3a22168, v30 v_fmamk_f32 v30, v31, 0xa7c234c4, v30 v_cvt_i32_f32_e32 v31, v31 ; %bb.33: ; %_ZL3sinf.exit s_or_b32 exec_lo, exec_lo, s2 s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x10 s_load_b32 s10, s[0:1], 0x18 v_dual_mul_f32 v32, v28, v28 :: v_dual_and_b32 v33, 1, v29 s_mov_b32 s2, 0xb94c1982 v_dual_mul_f32 v34, v30, v30 :: v_dual_lshlrev_b32 v29, 30, v29 s_delay_alu instid0(VALU_DEP_2) v_dual_fmaak_f32 v36, s2, v32, 0x3c0881c4 :: v_dual_and_b32 v35, 1, v31 v_lshlrev_b32_e32 v31, 30, v31 s_mov_b32 s3, 0x37d75334 v_xor_b32_e32 v27, v27, v0 s_clause 0x1 s_load_b64 s[8:9], s[0:1], 0x50 s_load_b64 s[6:7], s[0:1], 0x68 v_fmaak_f32 v36, v32, v36, 0xbe2aaa9d v_and_b32_e32 v29, 0x80000000, v29 v_fma_f32 v15, v15, 2.0, 1.0 s_waitcnt vmcnt(1) v_mul_f32_e32 v26, v23, v26 v_mul_f32_e32 v24, v16, v24 v_dual_mul_f32 v36, v32, v36 :: v_dual_fmaak_f32 v43, s3, v34, 0xbab64f3b s_waitcnt lgkmcnt(0) v_div_scale_f32 v37, null, s5, s5, s4 v_div_scale_f32 v38, null, s10, s10, s4 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fmac_f32_e32 v28, v28, v36 v_rcp_f32_e32 v40, v37 v_div_scale_f32 v46, vcc_lo, s4, s5, s4 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f32_e32 v42, v38 s_waitcnt vmcnt(0) v_mul_f32_e32 v26, v26, v25 v_mul_f32_e32 v25, v25, v26 s_waitcnt_depctr 0xfff v_fma_f32 v44, -v37, v40, 1.0 v_fmaak_f32 v41, s2, v34, 0x3c0881c4 v_fma_f32 v45, -v38, v42, 1.0 v_fmaak_f32 v39, s3, v32, 0xbab64f3b s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_dual_fmac_f32 v40, v44, v40 :: v_dual_fmaak_f32 v41, v34, v41, 0xbe2aaa9d v_div_scale_f32 v44, s2, s4, s10, s4 v_dual_fmac_f32 v42, v45, v42 :: v_dual_and_b32 v31, 0x80000000, v31 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mul_f32_e32 v41, v34, v41 v_fmaak_f32 v39, v32, v39, 0x3d2aabf7 v_dual_mul_f32 v45, v46, v40 :: v_dual_mul_f32 v36, v44, v42 v_cmp_eq_u32_e64 s3, 0, v33 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_dual_fmac_f32 v30, v30, v41 :: v_dual_fmaak_f32 v39, v32, v39, 0xbf000004 v_mul_f32_e32 v15, v15, v25 v_fma_f32 v41, -v38, v36, v44 v_fmaak_f32 v43, v34, v43, 0x3d2aabf7 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f32 v32, v32, v39, 1.0 v_fma_f32 v39, -v37, v45, v46 v_dual_fmac_f32 v36, v41, v42 :: v_dual_fmaak_f32 v43, v34, v43, 0xbf000004 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v28, -v28, v32, s3 v_cmp_eq_u32_e64 s3, 0, v35 v_fmac_f32_e32 v45, v39, v40 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f32 v34, v34, v43, 1.0 ; implicit-def: $vgpr32 v_xor_b32_e32 v28, v29, v28 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f32 v29, -v37, v45, v46 v_cndmask_b32_e64 v30, v34, v30, s3 v_cmp_class_f32_e64 s3, v0, 0x1f8 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_div_fmas_f32 v29, v29, v40, v45 v_xor3_b32 v27, v27, v31, v30 v_fma_f32 v30, -v38, v36, v44 s_mov_b32 vcc_lo, s2 v_cndmask_b32_e64 v28, 0x7fc00000, v28, s3 ; implicit-def: $vgpr31 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v27, 0x7fc00000, v27, s3 v_div_fmas_f32 v0, v30, v42, v36 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f32 v23, v0, s10, s4 v_div_fixup_f32 v0, v29, s5, s4 v_dual_mul_f32 v27, v23, v27 :: v_dual_mul_f32 v26, v0, v28 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v27, v20, v27 v_fma_f32 v27, v19, v26, -v27 v_lshlrev_b64 v[25:26], 2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f32_e32 v27, v15, v27 v_add_co_u32 v15, vcc_lo, s8, v25 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v16, vcc_lo, s9, v26, vcc_lo v_fma_f32 v18, v24, v18, -v27 v_add_co_u32 v28, vcc_lo, s6, v25 v_add_co_ci_u32_e32 v29, vcc_lo, s7, v26, vcc_lo global_store_b32 v[15:16], v18, off global_load_b32 v27, v[11:12], off global_load_b32 v18, v[3:4], off global_load_b32 v25, v[5:6], off global_load_b32 v24, v[28:29], off global_load_b32 v28, v[7:8], off global_load_b32 v29, v[9:10], off global_load_b32 v26, v[13:14], off s_waitcnt vmcnt(6) v_and_b32_e32 v30, 0x7fffffff, v27 v_cmp_ngt_f32_e64 s4, 0x48000000, |v27| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s2, s4 s_xor_b32 s5, exec_lo, s2 s_cbranch_execz .LBB2_35 ; %bb.34: s_mov_b32 s2, 0x7fffff v_mov_b32_e32 v33, 0 v_and_or_b32 v41, v30, s2, 0x800000 v_lshrrev_b32_e32 v38, 23, v30 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[31:32], null, v41, 0xfe5163ab, 0 v_add_nc_u32_e32 v39, 0xffffff88, v38 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_lt_u32_e32 vcc_lo, 63, v39 v_mad_u64_u32 v[34:35], null, v41, 0x3c439041, v[32:33] v_cndmask_b32_e64 v40, 0, 0xffffffc0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mov_b32_e32 v32, v35 v_add_nc_u32_e32 v40, v40, v39 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[35:36], null, v41, 0xdb629599, v[32:33] v_cmp_lt_u32_e64 s2, 31, v40 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v42, 0, 0xffffffe0, s2 v_dual_mov_b32 v32, v36 :: v_dual_cndmask_b32 v31, v35, v31 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v42, v42, v40 v_mad_u64_u32 v[36:37], null, v41, 0xf534ddc0, v[32:33] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_lt_u32_e64 s3, 31, v42 v_mov_b32_e32 v32, v37 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v34, v36, v34, vcc_lo v_mad_u64_u32 v[37:38], null, v41, 0xfc2757d1, v[32:33] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v31, v34, v31, s2 v_mov_b32_e32 v32, v38 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[38:39], null, v41, 0x4e441529, v[32:33] v_mov_b32_e32 v32, v39 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[39:40], null, v41, 0xa2f9836e, v[32:33] v_cndmask_b32_e64 v32, 0, 0xffffffe0, s3 v_dual_cndmask_b32 v33, v38, v36 :: v_dual_add_nc_u32 v32, v32, v42 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v39, v39, v37 :: v_dual_cndmask_b32 v38, v40, v38 v_cndmask_b32_e32 v37, v37, v35, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v32 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v36, v39, v33, s2 v_cndmask_b32_e64 v38, v38, v39, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v33, v33, v37, s2 v_sub_nc_u32_e32 v39, 32, v32 v_cndmask_b32_e64 v37, v37, v34, s2 v_cndmask_b32_e64 v38, v38, v36, s3 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v36, v36, v33, s3 v_cndmask_b32_e64 v33, v33, v37, s3 v_cndmask_b32_e64 v31, v37, v31, s3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v40, v38, v36, v39 v_alignbit_b32 v35, v36, v33, v39 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v32, v40, v38, vcc_lo v_alignbit_b32 v38, v33, v31, v39 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v34, v35, v36, vcc_lo v_bfe_u32 v35, v32, 29, 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v33, v38, v33, vcc_lo v_alignbit_b32 v36, v32, v34, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_sub_nc_u32_e32 v37, 0, v35 v_alignbit_b32 v34, v34, v33, 30 v_alignbit_b32 v31, v33, v31, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v36, v36, v37 v_xor_b32_e32 v33, v34, v37 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v31, v31, v37 v_clz_i32_u32_e32 v38, v36 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_min_u32_e32 v38, 32, v38 v_sub_nc_u32_e32 v34, 31, v38 v_lshlrev_b32_e32 v40, 23, v38 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_alignbit_b32 v36, v36, v33, v34 v_alignbit_b32 v31, v33, v31, v34 v_lshrrev_b32_e32 v34, 29, v32 v_alignbit_b32 v33, v36, v31, 9 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b32_e32 v34, 31, v34 v_lshrrev_b32_e32 v36, 9, v36 v_clz_i32_u32_e32 v37, v33 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_or_b32_e32 v39, 0.5, v34 v_min_u32_e32 v37, 32, v37 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v39, v39, v40 v_sub_nc_u32_e32 v41, 31, v37 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v31, v33, v31, v41 v_or_b32_e32 v33, v36, v39 v_add_lshl_u32 v36, v37, v38, 23 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshrrev_b32_e32 v31, 9, v31 v_mul_f32_e32 v37, 0x3fc90fda, v33 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v31, v31, v36 v_fma_f32 v36, v33, 0x3fc90fda, -v37 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v31, 0x33000000, v31 v_fmamk_f32 v33, v33, 0x33a22168, v36 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_or_b32_e32 v31, v31, v34 v_fmac_f32_e32 v33, 0x3fc90fda, v31 v_lshrrev_b32_e32 v32, 30, v32 s_delay_alu instid0(VALU_DEP_1) v_dual_add_f32 v31, v37, v33 :: v_dual_add_nc_u32 v32, v35, v32 .LBB2_35: ; %Flow410 s_and_not1_saveexec_b32 s2, s5 ; %bb.36: v_mul_f32_e64 v31, 0x3f22f983, |v27| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f32_e32 v32, v31 v_fma_f32 v31, v32, 0xbfc90fda, |v27| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v31, v32, 0xb3a22168, v31 v_fmamk_f32 v31, v32, 0xa7c234c4, v31 v_cvt_i32_f32_e32 v32, v32 ; %bb.37: ; %_ZL3sinf.exit259 s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $vgpr34 ; implicit-def: $vgpr33 s_and_saveexec_b32 s2, s4 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s4, exec_lo, s2 s_cbranch_execz .LBB2_39 ; %bb.38: s_mov_b32 s2, 0x7fffff v_mov_b32_e32 v35, 0 v_and_or_b32 v43, v30, s2, 0x800000 v_lshrrev_b32_e32 v40, 23, v30 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[33:34], null, v43, 0xfe5163ab, 0 v_add_nc_u32_e32 v41, 0xffffff88, v40 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_lt_u32_e32 vcc_lo, 63, v41 v_mad_u64_u32 v[36:37], null, v43, 0x3c439041, v[34:35] v_cndmask_b32_e64 v42, 0, 0xffffffc0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mov_b32_e32 v34, v37 v_add_nc_u32_e32 v42, v42, v41 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[37:38], null, v43, 0xdb629599, v[34:35] v_cmp_lt_u32_e64 s2, 31, v42 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v44, 0, 0xffffffe0, s2 v_dual_mov_b32 v34, v38 :: v_dual_cndmask_b32 v33, v37, v33 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v44, v44, v42 v_mad_u64_u32 v[38:39], null, v43, 0xf534ddc0, v[34:35] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_lt_u32_e64 s3, 31, v44 v_mov_b32_e32 v34, v39 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v36, v38, v36, vcc_lo v_mad_u64_u32 v[39:40], null, v43, 0xfc2757d1, v[34:35] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v33, v36, v33, s2 v_mov_b32_e32 v34, v40 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[40:41], null, v43, 0x4e441529, v[34:35] v_mov_b32_e32 v34, v41 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[41:42], null, v43, 0xa2f9836e, v[34:35] v_cndmask_b32_e64 v34, 0, 0xffffffe0, s3 v_dual_cndmask_b32 v35, v40, v38 :: v_dual_add_nc_u32 v34, v34, v44 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v41, v41, v39 :: v_dual_cndmask_b32 v40, v42, v40 v_cndmask_b32_e32 v39, v39, v37, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v34 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v38, v41, v35, s2 v_cndmask_b32_e64 v40, v40, v41, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v35, v35, v39, s2 v_sub_nc_u32_e32 v41, 32, v34 v_cndmask_b32_e64 v39, v39, v36, s2 v_cndmask_b32_e64 v40, v40, v38, s3 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v38, v38, v35, s3 v_cndmask_b32_e64 v35, v35, v39, s3 v_cndmask_b32_e64 v33, v39, v33, s3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v42, v40, v38, v41 v_alignbit_b32 v37, v38, v35, v41 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v34, v42, v40, vcc_lo v_alignbit_b32 v40, v35, v33, v41 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v36, v37, v38, vcc_lo v_bfe_u32 v37, v34, 29, 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v35, v40, v35, vcc_lo v_alignbit_b32 v38, v34, v36, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_sub_nc_u32_e32 v39, 0, v37 v_alignbit_b32 v36, v36, v35, 30 v_alignbit_b32 v33, v35, v33, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v38, v38, v39 v_xor_b32_e32 v35, v36, v39 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v33, v33, v39 v_clz_i32_u32_e32 v40, v38 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_min_u32_e32 v40, 32, v40 v_sub_nc_u32_e32 v36, 31, v40 v_lshlrev_b32_e32 v42, 23, v40 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_alignbit_b32 v38, v38, v35, v36 v_alignbit_b32 v33, v35, v33, v36 v_lshrrev_b32_e32 v36, 29, v34 v_alignbit_b32 v35, v38, v33, 9 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b32_e32 v36, 31, v36 v_lshrrev_b32_e32 v38, 9, v38 v_clz_i32_u32_e32 v39, v35 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_or_b32_e32 v41, 0.5, v36 v_min_u32_e32 v39, 32, v39 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v41, v41, v42 v_sub_nc_u32_e32 v43, 31, v39 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v33, v35, v33, v43 v_or_b32_e32 v35, v38, v41 v_add_lshl_u32 v38, v39, v40, 23 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshrrev_b32_e32 v33, 9, v33 v_mul_f32_e32 v39, 0x3fc90fda, v35 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v33, v33, v38 v_fma_f32 v38, v35, 0x3fc90fda, -v39 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v33, 0x33000000, v33 v_fmamk_f32 v35, v35, 0x33a22168, v38 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_or_b32_e32 v33, v33, v36 v_fmac_f32_e32 v35, 0x3fc90fda, v33 v_lshrrev_b32_e32 v34, 30, v34 s_delay_alu instid0(VALU_DEP_1) v_dual_add_f32 v33, v39, v35 :: v_dual_add_nc_u32 v34, v37, v34 .LBB2_39: ; %Flow409 s_and_not1_saveexec_b32 s2, s4 ; %bb.40: v_mul_f32_e64 v33, 0x3f22f983, |v27| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f32_e32 v34, v33 v_fma_f32 v33, v34, 0xbfc90fda, |v27| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v33, v34, 0xb3a22168, v33 v_fmamk_f32 v33, v34, 0xa7c234c4, v33 v_cvt_i32_f32_e32 v34, v34 ; %bb.41: ; %_ZL3cosf.exit265 s_or_b32 exec_lo, exec_lo, s2 v_fma_f32 v17, v17, 2.0, 1.0 v_dual_mul_f32 v35, v31, v31 :: v_dual_and_b32 v36, 1, v32 s_mov_b32 s2, 0xb94c1982 s_mov_b32 s3, 0x37d75334 s_delay_alu instid0(VALU_DEP_2) v_dual_mul_f32 v37, 0x4f800000, v17 :: v_dual_lshlrev_b32 v32, 30, v32 v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v17 s_waitcnt vmcnt(4) v_dual_fmaak_f32 v38, s2, v35, 0x3c0881c4 :: v_dual_mul_f32 v25, v18, v25 s_load_b64 s[4:5], s[0:1], 0x78 v_dual_cndmask_b32 v17, v17, v37 :: v_dual_and_b32 v32, 0x80000000, v32 v_mul_f32_e32 v37, v33, v33 v_fmaak_f32 v39, s3, v35, 0xbab64f3b s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_xor_b32_e32 v32, v32, v27 v_sqrt_f32_e32 v40, v17 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fmaak_f32 v42, s3, v37, 0xbab64f3b v_fmaak_f32 v39, v35, v39, 0x3d2aabf7 v_fmaak_f32 v41, s2, v37, 0x3c0881c4 v_fmaak_f32 v38, v35, v38, 0xbe2aaa9d v_cmp_eq_u32_e64 s2, 0, v36 v_fmaak_f32 v42, v37, v42, 0x3d2aabf7 v_fmaak_f32 v39, v35, v39, 0xbf000004 s_delay_alu instid0(VALU_DEP_4) v_dual_fmaak_f32 v41, v37, v41, 0xbe2aaa9d :: v_dual_mul_f32 v38, v35, v38 s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1) v_dual_fmac_f32 v31, v31, v38 :: v_dual_add_nc_u32 v36, 1, v40 v_add_nc_u32_e32 v38, -1, v40 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f32 v35, v35, v39, 1.0 v_mul_f32_e32 v39, v37, v41 v_fmaak_f32 v41, v37, v42, 0xbf000004 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v31, v35, v31, s2 v_fma_f32 v35, -v38, v40, v17 v_fmac_f32_e32 v33, v33, v39 v_and_b32_e32 v39, 1, v34 v_fma_f32 v37, v37, v41, 1.0 v_lshlrev_b32_e32 v34, 30, v34 v_cmp_ge_f32_e64 s2, 0, v35 v_xor3_b32 v30, v32, v31, v30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_and_b32_e32 v34, 0x80000000, v34 v_cndmask_b32_e64 v35, v40, v38, s2 v_fma_f32 v38, -v36, v40, v17 v_cmp_eq_u32_e64 s2, 0, v39 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v33, -v33, v37, s2 v_cmp_lt_f32_e64 s2, 0, v38 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v32, v34, v33 v_cndmask_b32_e64 v31, v35, v36, s2 v_cmp_class_f32_e64 s2, v27, 0x1f8 s_waitcnt vmcnt(1) v_mul_f32_e32 v27, v28, v29 ; implicit-def: $vgpr34 ; implicit-def: $vgpr33 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f32_e32 v29, 0x37800000, v31 v_cndmask_b32_e64 v28, 0x7fc00000, v30, s2 v_cndmask_b32_e64 v30, 0x7fc00000, v32, s2 s_load_b64 s[2:3], s[0:1], 0x60 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v29, v31, v29, vcc_lo v_cmp_class_f32_e64 vcc_lo, v17, 0x260 v_mul_f32_e32 v30, v23, v30 s_waitcnt vmcnt(0) v_dual_mul_f32 v27, v27, v26 :: v_dual_mul_f32 v28, v0, v28 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_mul_f32 v27, v26, v27 :: v_dual_cndmask_b32 v26, v29, v17 v_mul_f32_e32 v17, v22, v30 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f32_e32 v29, v26, v27 v_fmac_f32_e32 v17, v21, v28 v_lshlrev_b64 v[27:28], 2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f32_e32 v29, v29, v17 s_waitcnt lgkmcnt(0) v_add_co_u32 v17, vcc_lo, s2, v27 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v18, vcc_lo, s3, v28, vcc_lo v_fma_f32 v24, v25, v24, -v29 v_add_co_u32 v30, vcc_lo, s4, v27 v_add_co_ci_u32_e32 v31, vcc_lo, s5, v28, vcc_lo global_store_b32 v[17:18], v24, off global_load_b32 v29, v[11:12], off global_load_b32 v25, v[3:4], off global_load_b32 v27, v[5:6], off global_load_b32 v24, v[30:31], off global_load_b32 v30, v[7:8], off global_load_b32 v31, v[9:10], off global_load_b32 v28, v[13:14], off s_waitcnt vmcnt(6) v_and_b32_e32 v32, 0x7fffffff, v29 v_cmp_ngt_f32_e64 s4, 0x48000000, |v29| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s2, s4 s_xor_b32 s5, exec_lo, s2 s_cbranch_execz .LBB2_43 ; %bb.42: s_mov_b32 s2, 0x7fffff v_mov_b32_e32 v35, 0 v_and_or_b32 v43, v32, s2, 0x800000 v_lshrrev_b32_e32 v40, 23, v32 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[33:34], null, v43, 0xfe5163ab, 0 v_add_nc_u32_e32 v41, 0xffffff88, v40 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_lt_u32_e32 vcc_lo, 63, v41 v_mad_u64_u32 v[36:37], null, v43, 0x3c439041, v[34:35] v_cndmask_b32_e64 v42, 0, 0xffffffc0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mov_b32_e32 v34, v37 v_add_nc_u32_e32 v42, v42, v41 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[37:38], null, v43, 0xdb629599, v[34:35] v_cmp_lt_u32_e64 s2, 31, v42 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v44, 0, 0xffffffe0, s2 v_dual_mov_b32 v34, v38 :: v_dual_cndmask_b32 v33, v37, v33 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v44, v44, v42 v_mad_u64_u32 v[38:39], null, v43, 0xf534ddc0, v[34:35] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_lt_u32_e64 s3, 31, v44 v_mov_b32_e32 v34, v39 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v36, v38, v36, vcc_lo v_mad_u64_u32 v[39:40], null, v43, 0xfc2757d1, v[34:35] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v33, v36, v33, s2 v_mov_b32_e32 v34, v40 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[40:41], null, v43, 0x4e441529, v[34:35] v_mov_b32_e32 v34, v41 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[41:42], null, v43, 0xa2f9836e, v[34:35] v_cndmask_b32_e64 v34, 0, 0xffffffe0, s3 v_dual_cndmask_b32 v35, v40, v38 :: v_dual_add_nc_u32 v34, v34, v44 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v41, v41, v39 :: v_dual_cndmask_b32 v40, v42, v40 v_cndmask_b32_e32 v39, v39, v37, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v34 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v38, v41, v35, s2 v_cndmask_b32_e64 v40, v40, v41, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v35, v35, v39, s2 v_sub_nc_u32_e32 v41, 32, v34 v_cndmask_b32_e64 v39, v39, v36, s2 v_cndmask_b32_e64 v40, v40, v38, s3 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v38, v38, v35, s3 v_cndmask_b32_e64 v35, v35, v39, s3 v_cndmask_b32_e64 v33, v39, v33, s3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v42, v40, v38, v41 v_alignbit_b32 v37, v38, v35, v41 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v34, v42, v40, vcc_lo v_alignbit_b32 v40, v35, v33, v41 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v36, v37, v38, vcc_lo v_bfe_u32 v37, v34, 29, 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v35, v40, v35, vcc_lo v_alignbit_b32 v38, v34, v36, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_sub_nc_u32_e32 v39, 0, v37 v_alignbit_b32 v36, v36, v35, 30 v_alignbit_b32 v33, v35, v33, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v38, v38, v39 v_xor_b32_e32 v35, v36, v39 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v33, v33, v39 v_clz_i32_u32_e32 v40, v38 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_min_u32_e32 v40, 32, v40 v_sub_nc_u32_e32 v36, 31, v40 v_lshlrev_b32_e32 v42, 23, v40 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_alignbit_b32 v38, v38, v35, v36 v_alignbit_b32 v33, v35, v33, v36 v_lshrrev_b32_e32 v36, 29, v34 v_alignbit_b32 v35, v38, v33, 9 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b32_e32 v36, 31, v36 v_lshrrev_b32_e32 v38, 9, v38 v_clz_i32_u32_e32 v39, v35 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_or_b32_e32 v41, 0.5, v36 v_min_u32_e32 v39, 32, v39 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v41, v41, v42 v_sub_nc_u32_e32 v43, 31, v39 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v33, v35, v33, v43 v_or_b32_e32 v35, v38, v41 v_add_lshl_u32 v38, v39, v40, 23 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshrrev_b32_e32 v33, 9, v33 v_mul_f32_e32 v39, 0x3fc90fda, v35 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v33, v33, v38 v_fma_f32 v38, v35, 0x3fc90fda, -v39 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v33, 0x33000000, v33 v_fmamk_f32 v35, v35, 0x33a22168, v38 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_or_b32_e32 v33, v33, v36 v_fmac_f32_e32 v35, 0x3fc90fda, v33 v_lshrrev_b32_e32 v34, 30, v34 s_delay_alu instid0(VALU_DEP_1) v_dual_add_f32 v33, v39, v35 :: v_dual_add_nc_u32 v34, v37, v34 .LBB2_43: ; %Flow408 s_and_not1_saveexec_b32 s2, s5 ; %bb.44: v_mul_f32_e64 v33, 0x3f22f983, |v29| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f32_e32 v34, v33 v_fma_f32 v33, v34, 0xbfc90fda, |v29| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v33, v34, 0xb3a22168, v33 v_fmamk_f32 v33, v34, 0xa7c234c4, v33 v_cvt_i32_f32_e32 v34, v34 ; %bb.45: ; %_ZL3cosf.exit271 s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $vgpr36 ; implicit-def: $vgpr35 s_and_saveexec_b32 s2, s4 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s4, exec_lo, s2 s_cbranch_execz .LBB2_47 ; %bb.46: s_mov_b32 s2, 0x7fffff v_mov_b32_e32 v37, 0 v_and_or_b32 v45, v32, s2, 0x800000 v_lshrrev_b32_e32 v42, 23, v32 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[35:36], null, v45, 0xfe5163ab, 0 v_add_nc_u32_e32 v43, 0xffffff88, v42 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_lt_u32_e32 vcc_lo, 63, v43 v_mad_u64_u32 v[38:39], null, v45, 0x3c439041, v[36:37] v_cndmask_b32_e64 v44, 0, 0xffffffc0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mov_b32_e32 v36, v39 v_add_nc_u32_e32 v44, v44, v43 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[39:40], null, v45, 0xdb629599, v[36:37] v_cmp_lt_u32_e64 s2, 31, v44 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v46, 0, 0xffffffe0, s2 v_dual_mov_b32 v36, v40 :: v_dual_cndmask_b32 v35, v39, v35 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v46, v46, v44 v_mad_u64_u32 v[40:41], null, v45, 0xf534ddc0, v[36:37] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_lt_u32_e64 s3, 31, v46 v_mov_b32_e32 v36, v41 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v38, v40, v38, vcc_lo v_mad_u64_u32 v[41:42], null, v45, 0xfc2757d1, v[36:37] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v35, v38, v35, s2 v_mov_b32_e32 v36, v42 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[42:43], null, v45, 0x4e441529, v[36:37] v_mov_b32_e32 v36, v43 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[43:44], null, v45, 0xa2f9836e, v[36:37] v_cndmask_b32_e64 v36, 0, 0xffffffe0, s3 v_dual_cndmask_b32 v37, v42, v40 :: v_dual_add_nc_u32 v36, v36, v46 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v43, v43, v41 :: v_dual_cndmask_b32 v42, v44, v42 v_cndmask_b32_e32 v41, v41, v39, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v36 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v40, v43, v37, s2 v_cndmask_b32_e64 v42, v42, v43, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v37, v37, v41, s2 v_sub_nc_u32_e32 v43, 32, v36 v_cndmask_b32_e64 v41, v41, v38, s2 v_cndmask_b32_e64 v42, v42, v40, s3 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v40, v40, v37, s3 v_cndmask_b32_e64 v37, v37, v41, s3 v_cndmask_b32_e64 v35, v41, v35, s3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v44, v42, v40, v43 v_alignbit_b32 v39, v40, v37, v43 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v36, v44, v42, vcc_lo v_alignbit_b32 v42, v37, v35, v43 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v38, v39, v40, vcc_lo v_bfe_u32 v39, v36, 29, 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v37, v42, v37, vcc_lo v_alignbit_b32 v40, v36, v38, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_sub_nc_u32_e32 v41, 0, v39 v_alignbit_b32 v38, v38, v37, 30 v_alignbit_b32 v35, v37, v35, 30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v40, v40, v41 v_xor_b32_e32 v37, v38, v41 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v35, v35, v41 v_clz_i32_u32_e32 v42, v40 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_min_u32_e32 v42, 32, v42 v_sub_nc_u32_e32 v38, 31, v42 v_lshlrev_b32_e32 v44, 23, v42 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_alignbit_b32 v40, v40, v37, v38 v_alignbit_b32 v35, v37, v35, v38 v_lshrrev_b32_e32 v38, 29, v36 v_alignbit_b32 v37, v40, v35, 9 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b32_e32 v38, 31, v38 v_lshrrev_b32_e32 v40, 9, v40 v_clz_i32_u32_e32 v41, v37 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_or_b32_e32 v43, 0.5, v38 v_min_u32_e32 v41, 32, v41 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v43, v43, v44 v_sub_nc_u32_e32 v45, 31, v41 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v35, v37, v35, v45 v_or_b32_e32 v37, v40, v43 v_add_lshl_u32 v40, v41, v42, 23 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshrrev_b32_e32 v35, 9, v35 v_mul_f32_e32 v41, 0x3fc90fda, v37 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v35, v35, v40 v_fma_f32 v40, v37, 0x3fc90fda, -v41 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v35, 0x33000000, v35 v_fmamk_f32 v37, v37, 0x33a22168, v40 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_or_b32_e32 v35, v35, v38 v_fmac_f32_e32 v37, 0x3fc90fda, v35 v_lshrrev_b32_e32 v36, 30, v36 s_delay_alu instid0(VALU_DEP_1) v_dual_add_f32 v35, v41, v37 :: v_dual_add_nc_u32 v36, v39, v36 .LBB2_47: ; %Flow407 s_and_not1_saveexec_b32 s2, s4 ; %bb.48: v_mul_f32_e64 v35, 0x3f22f983, |v29| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f32_e32 v36, v35 v_fma_f32 v35, v36, 0xbfc90fda, |v29| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v35, v36, 0xb3a22168, v35 v_fmamk_f32 v35, v36, 0xa7c234c4, v35 v_cvt_i32_f32_e32 v36, v36 ; %bb.49: ; %_ZL3sinf.exit277 s_or_b32 exec_lo, exec_lo, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_dual_mul_f32 v37, v33, v33 :: v_dual_mul_f32 v38, v35, v35 s_mov_b32 s2, 0xb94c1982 s_mov_b32 s3, 0x37d75334 v_xor_b32_e32 v32, v32, v29 v_dual_fmaak_f32 v39, s2, v37, 0x3c0881c4 :: v_dual_fmaak_f32 v42, s2, v38, 0x3c0881c4 v_dual_fmaak_f32 v40, s3, v37, 0xbab64f3b :: v_dual_and_b32 v41, 1, v34 v_dual_fmaak_f32 v43, s3, v38, 0xbab64f3b :: v_dual_and_b32 v44, 1, v36 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_fmaak_f32 v39, v37, v39, 0xbe2aaa9d :: v_dual_lshlrev_b32 v34, 30, v34 v_dual_fmaak_f32 v40, v37, v40, 0x3d2aabf7 :: v_dual_fmaak_f32 v43, v38, v43, 0x3d2aabf7 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_fmaak_f32 v42, v38, v42, 0xbe2aaa9d :: v_dual_mul_f32 v39, v37, v39 v_cmp_eq_u32_e32 vcc_lo, 0, v41 v_dual_fmaak_f32 v40, v37, v40, 0xbf000004 :: v_dual_fmaak_f32 v43, v38, v43, 0xbf000004 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_mul_f32 v42, v38, v42 :: v_dual_fmac_f32 v33, v33, v39 v_lshlrev_b32_e32 v36, 30, v36 v_fma_f32 v37, v37, v40, 1.0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f32 v38, v38, v43, 1.0 v_fmac_f32_e32 v35, v35, v42 s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x70 s_load_b64 s[4:5], s[0:1], 0x88 v_cndmask_b32_e64 v33, -v33, v37, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v44 v_and_b32_e32 v34, 0x80000000, v34 s_waitcnt vmcnt(4) v_dual_mul_f32 v25, v25, v27 :: v_dual_and_b32 v36, 0x80000000, v36 v_cndmask_b32_e32 v35, v38, v35, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_xor_b32_e32 v33, v34, v33 v_cmp_class_f32_e64 vcc_lo, v29, 0x1f8 s_waitcnt vmcnt(1) v_mul_f32_e32 v29, v30, v31 v_xor3_b32 v32, v32, v36, v35 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v30, 0x7fc00000, v33 :: v_dual_mul_f32 v29, v29, v28 v_dual_cndmask_b32 v31, 0x7fc00000, v32 :: v_dual_mul_f32 v28, v28, v29 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_mul_f32 v31, v23, v31 :: v_dual_mul_f32 v26, v26, v28 v_mul_f32_e32 v29, v0, v30 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v20, v20, v31 v_fma_f32 v19, v19, v29, -v20 v_lshlrev_b64 v[28:29], 2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f32_e32 v26, v26, v19 s_waitcnt lgkmcnt(0) v_add_co_u32 v19, vcc_lo, s2, v28 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v20, vcc_lo, s3, v29, vcc_lo v_fma_f32 v26, v25, v24, -v26 v_add_co_u32 v24, vcc_lo, s4, v28 v_add_co_ci_u32_e32 v25, vcc_lo, s5, v29, vcc_lo global_store_b32 v[19:20], v26, off global_load_b32 v11, v[11:12], off global_load_b32 v4, v[3:4], off global_load_b32 v5, v[5:6], off global_load_b32 v3, v[24:25], off global_load_b32 v7, v[7:8], off global_load_b32 v8, v[9:10], off global_load_b32 v6, v[13:14], off ; implicit-def: $vgpr12 ; implicit-def: $vgpr10 s_waitcnt vmcnt(6) v_and_b32_e32 v9, 0x7fffffff, v11 v_cmp_ngt_f32_e64 s4, 0x48000000, |v11| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_saveexec_b32 s2, s4 s_xor_b32 s5, exec_lo, s2 s_cbranch_execz .LBB2_51 ; %bb.50: s_mov_b32 s2, 0x7fffff v_mov_b32_e32 v14, 0 v_and_or_b32 v10, v9, s2, 0x800000 v_lshrrev_b32_e32 v28, 23, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[12:13], null, v10, 0xfe5163ab, 0 v_add_nc_u32_e32 v29, 0xffffff88, v28 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_lt_u32_e32 vcc_lo, 63, v29 v_mad_u64_u32 v[24:25], null, v10, 0x3c439041, v[13:14] v_cndmask_b32_e64 v30, 0, 0xffffffc0, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v13, v25 :: v_dual_add_nc_u32 v30, v30, v29 v_mad_u64_u32 v[25:26], null, v10, 0xdb629599, v[13:14] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_lt_u32_e64 s2, 31, v30 v_cndmask_b32_e64 v31, 0, 0xffffffe0, s2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v13, v26 :: v_dual_cndmask_b32 v12, v25, v12 v_mad_u64_u32 v[26:27], null, v10, 0xf534ddc0, v[13:14] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v24, v26, v24 :: v_dual_add_nc_u32 v31, v31, v30 v_mov_b32_e32 v13, v27 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_lt_u32_e64 s3, 31, v31 v_cndmask_b32_e64 v12, v24, v12, s2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[27:28], null, v10, 0xfc2757d1, v[13:14] v_mov_b32_e32 v13, v28 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[28:29], null, v10, 0x4e441529, v[13:14] v_mov_b32_e32 v13, v29 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_mad_u64_u32 v[29:30], null, v10, 0xa2f9836e, v[13:14] v_cndmask_b32_e32 v13, v28, v26, vcc_lo v_cndmask_b32_e64 v10, 0, 0xffffffe0, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_nc_u32_e32 v10, v10, v31 v_cndmask_b32_e32 v14, v29, v27, vcc_lo v_cndmask_b32_e32 v28, v30, v28, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v26, v14, v13, s2 v_cndmask_b32_e64 v14, v28, v14, s2 v_sub_nc_u32_e32 v28, 32, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v14, v14, v26, s3 v_cndmask_b32_e32 v27, v27, v25, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v10 v_cndmask_b32_e64 v13, v13, v27, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v26, v26, v13, s3 v_alignbit_b32 v29, v14, v26, v28 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v10, v29, v14, vcc_lo v_cndmask_b32_e64 v27, v27, v24, s2 v_bfe_u32 v24, v10, 29, 1 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v13, v13, v27, s3 v_cndmask_b32_e64 v12, v27, v12, s3 v_alignbit_b32 v25, v26, v13, v28 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_alignbit_b32 v27, v13, v12, v28 v_cndmask_b32_e32 v14, v25, v26, vcc_lo v_sub_nc_u32_e32 v26, 0, v24 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v13, v27, v13, vcc_lo v_alignbit_b32 v25, v10, v14, 30 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_alignbit_b32 v14, v14, v13, 30 v_alignbit_b32 v12, v13, v12, 30 v_xor_b32_e32 v25, v25, v26 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v13, v14, v26 v_xor_b32_e32 v12, v12, v26 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_clz_i32_u32_e32 v27, v25 v_min_u32_e32 v27, 32, v27 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v14, 31, v27 v_lshlrev_b32_e32 v29, 23, v27 v_alignbit_b32 v25, v25, v13, v14 v_alignbit_b32 v12, v13, v12, v14 v_lshrrev_b32_e32 v14, 29, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_alignbit_b32 v13, v25, v12, 9 v_lshlrev_b32_e32 v14, 31, v14 v_lshrrev_b32_e32 v25, 9, v25 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_clz_i32_u32_e32 v26, v13 v_or_b32_e32 v28, 0.5, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_min_u32_e32 v26, 32, v26 v_sub_nc_u32_e32 v28, v28, v29 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v30, 31, v26 v_alignbit_b32 v12, v13, v12, v30 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_or_b32_e32 v13, v25, v28 v_add_lshl_u32 v25, v26, v27, 23 v_lshrrev_b32_e32 v12, 9, v12 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f32_e32 v26, 0x3fc90fda, v13 v_sub_nc_u32_e32 v12, v12, v25 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v25, v13, 0x3fc90fda, -v26 v_add_nc_u32_e32 v12, 0x33000000, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmamk_f32 v13, v13, 0x33a22168, v25 v_or_b32_e32 v12, v12, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fmac_f32_e32 v13, 0x3fc90fda, v12 v_lshrrev_b32_e32 v12, 30, v10 v_add_f32_e32 v10, v26, v13 s_delay_alu instid0(VALU_DEP_2) v_add_nc_u32_e32 v12, v24, v12 .LBB2_51: ; %Flow406 s_and_not1_saveexec_b32 s2, s5 ; %bb.52: v_mul_f32_e64 v10, 0x3f22f983, |v11| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f32_e32 v12, v10 v_fma_f32 v10, v12, 0xbfc90fda, |v11| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v10, v12, 0xb3a22168, v10 v_fmamk_f32 v10, v12, 0xa7c234c4, v10 v_cvt_i32_f32_e32 v12, v12 ; %bb.53: ; %_ZL3sinf.exit283 s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $vgpr14 ; implicit-def: $vgpr13 s_and_saveexec_b32 s2, s4 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s4, exec_lo, s2 s_cbranch_execz .LBB2_55 ; %bb.54: s_mov_b32 s2, 0x7fffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_or_b32 v33, v9, s2, 0x800000 v_mad_u64_u32 v[13:14], null, v33, 0xfe5163ab, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v24, v14 v_lshrrev_b32_e32 v14, 23, v9 v_mad_u64_u32 v[26:27], null, v33, 0x3c439041, v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v14, 0xffffff88, v14 v_cmp_lt_u32_e32 vcc_lo, 63, v14 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mov_b32_e32 v24, v27 v_cndmask_b32_e64 v31, 0, 0xffffffc0, vcc_lo v_mad_u64_u32 v[27:28], null, v33, 0xdb629599, v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v14, v31, v14 v_mov_b32_e32 v24, v28 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_lt_u32_e64 s2, 31, v14 v_cndmask_b32_e32 v13, v27, v13, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_mad_u64_u32 v[28:29], null, v33, 0xf534ddc0, v[24:25] v_cndmask_b32_e64 v32, 0, 0xffffffe0, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_nc_u32_e32 v14, v32, v14 v_mov_b32_e32 v24, v29 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_lt_u32_e64 s3, 31, v14 v_mad_u64_u32 v[29:30], null, v33, 0xfc2757d1, v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mov_b32_e32 v24, v30 v_mad_u64_u32 v[30:31], null, v33, 0x4e441529, v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mov_b32_e32 v24, v31 v_mad_u64_u32 v[31:32], null, v33, 0xa2f9836e, v[24:25] v_cndmask_b32_e64 v24, 0, 0xffffffe0, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v25, v30, v28 :: v_dual_add_nc_u32 v14, v24, v14 v_dual_cndmask_b32 v31, v31, v29 :: v_dual_cndmask_b32 v30, v32, v30 v_dual_cndmask_b32 v29, v29, v27 :: v_dual_cndmask_b32 v24, v28, v26 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_eq_u32_e32 vcc_lo, 0, v14 v_cndmask_b32_e64 v26, v31, v25, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v28, v30, v31, s2 v_cndmask_b32_e64 v25, v25, v29, s2 v_sub_nc_u32_e32 v30, 32, v14 v_cndmask_b32_e64 v29, v29, v24, s2 v_cndmask_b32_e64 v13, v24, v13, s2 v_cndmask_b32_e64 v28, v28, v26, s3 v_cndmask_b32_e64 v26, v26, v25, s3 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v25, v25, v29, s3 v_cndmask_b32_e64 v13, v29, v13, s3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v31, v28, v26, v30 v_alignbit_b32 v27, v26, v25, v30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v29, v25, v13, v30 v_cndmask_b32_e32 v14, v31, v28, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v24, v27, v26 :: v_dual_cndmask_b32 v25, v29, v25 v_bfe_u32 v26, v14, 29, 1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v27, v14, v24, 30 v_alignbit_b32 v24, v24, v25, 30 v_alignbit_b32 v13, v25, v13, 30 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v28, 0, v26 v_xor_b32_e32 v27, v27, v28 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_xor_b32_e32 v24, v24, v28 v_xor_b32_e32 v13, v13, v28 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_clz_i32_u32_e32 v29, v27 v_min_u32_e32 v29, 32, v29 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v25, 31, v29 v_lshlrev_b32_e32 v31, 23, v29 v_alignbit_b32 v27, v27, v24, v25 v_alignbit_b32 v13, v24, v13, v25 v_lshrrev_b32_e32 v25, 29, v14 v_lshrrev_b32_e32 v14, 30, v14 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v24, v27, v13, 9 v_lshlrev_b32_e32 v25, 31, v25 v_lshrrev_b32_e32 v27, 9, v27 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_nc_u32_e32 v14, v26, v14 v_clz_i32_u32_e32 v28, v24 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_or_b32_e32 v30, 0.5, v25 v_min_u32_e32 v28, 32, v28 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v30, v30, v31 v_sub_nc_u32_e32 v32, 31, v28 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_alignbit_b32 v13, v24, v13, v32 v_or_b32_e32 v24, v27, v30 v_add_lshl_u32 v27, v28, v29, 23 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshrrev_b32_e32 v13, 9, v13 v_mul_f32_e32 v28, 0x3fc90fda, v24 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v13, v13, v27 v_fma_f32 v27, v24, 0x3fc90fda, -v28 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v13, 0x33000000, v13 v_fmamk_f32 v24, v24, 0x33a22168, v27 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_or_b32_e32 v13, v13, v25 v_fmac_f32_e32 v24, 0x3fc90fda, v13 s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v13, v28, v24 .LBB2_55: ; %Flow s_and_not1_saveexec_b32 s2, s4 ; %bb.56: v_mul_f32_e64 v13, 0x3f22f983, |v11| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f32_e32 v14, v13 v_fma_f32 v13, v14, 0xbfc90fda, |v11| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v13, v14, 0xb3a22168, v13 v_fmamk_f32 v13, v14, 0xa7c234c4, v13 v_cvt_i32_f32_e32 v14, v14 ; %bb.57: ; %_ZL3cosf.exit289 s_or_b32 exec_lo, exec_lo, s2 s_delay_alu instid0(VALU_DEP_2) v_dual_mul_f32 v24, v10, v10 :: v_dual_mul_f32 v25, v13, v13 s_mov_b32 s2, 0xb94c1982 s_mov_b32 s3, 0x37d75334 s_waitcnt vmcnt(1) v_mul_f32_e32 v7, v7, v8 v_fmaak_f32 v26, s2, v24, 0x3c0881c4 v_fmaak_f32 v28, s2, v25, 0x3c0881c4 v_dual_fmaak_f32 v29, s3, v25, 0xbab64f3b :: v_dual_and_b32 v30, 1, v12 s_waitcnt vmcnt(0) v_dual_mul_f32 v7, v7, v6 :: v_dual_lshlrev_b32 v12, 30, v12 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fmaak_f32 v28, v25, v28, 0xbe2aaa9d v_cmp_eq_u32_e32 vcc_lo, 0, v30 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_mul_f32_e32 v6, v6, v7 v_and_b32_e32 v12, 0x80000000, v12 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mul_f32_e32 v28, v25, v28 v_fmaak_f32 v26, v24, v26, 0xbe2aaa9d v_xor_b32_e32 v12, v12, v11 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fmac_f32_e32 v13, v13, v28 v_dual_fmaak_f32 v27, s3, v24, 0xbab64f3b :: v_dual_mul_f32 v26, v24, v26 v_fmaak_f32 v29, v25, v29, 0x3d2aabf7 s_load_b64 s[2:3], s[0:1], 0x80 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_fmaak_f32 v27, v24, v27, 0x3d2aabf7 :: v_dual_fmac_f32 v10, v10, v26 v_dual_fmaak_f32 v29, v25, v29, 0xbf000004 :: v_dual_and_b32 v26, 1, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_fmaak_f32 v27, v24, v27, 0xbf000004 :: v_dual_lshlrev_b32 v14, 30, v14 v_fma_f32 v25, v25, v29, 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_and_b32_e32 v14, 0x80000000, v14 v_fma_f32 v24, v24, v27, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v10, v24, v10, vcc_lo v_cmp_eq_u32_e32 vcc_lo, 0, v26 v_xor3_b32 v9, v12, v10, v9 v_cndmask_b32_e64 v13, -v13, v25, vcc_lo v_cmp_class_f32_e64 vcc_lo, v11, 0x1f8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_xor_b32_e32 v10, v14, v13 v_cndmask_b32_e32 v9, 0x7fc00000, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v10, 0x7fc00000, v10, vcc_lo v_mul_f32_e32 v0, v0, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v8, v23, v10 v_mul_f32_e32 v8, v22, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fmac_f32_e32 v8, v21, v0 v_lshlrev_b64 v[0:1], 2, v[1:2] v_mul_f32_e32 v2, v4, v5 v_mul_f32_e32 v6, v6, v8 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v4, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_fma_f32 v2, v2, v3, -v6 s_load_b128 s[0:3], s[0:1], 0x30 global_store_b32 v[4:5], v2, off global_load_b32 v6, v[15:16], off global_load_b32 v7, v[17:18], off s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo s_waitcnt vmcnt(0) v_add_f32_e32 v6, v6, v7 global_store_b32 v[2:3], v6, off global_load_b32 v2, v[19:20], off global_load_b32 v3, v[4:5], off s_waitcnt vmcnt(0) v_add_f32_e32 v2, v2, v3 global_store_b32 v[0:1], v2, off .LBB2_58: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 480 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 50 .amdhsa_next_free_sgpr 20 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib, .Lfunc_end2-_Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 12892 ; NumSgprs: 22 ; NumVgprs: 50 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 6 ; NumSGPRsForWavesPerEU: 22 ; NumVGPRsForWavesPerEU: 50 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z6get_d0ffiiiPf ; -- Begin function _Z6get_d0ffiiiPf .globl _Z6get_d0ffiiiPf .p2align 8 .type _Z6get_d0ffiiiPf,@function _Z6get_d0ffiiiPf: ; @_Z6get_d0ffiiiPf ; %bb.0: s_clause 0x2 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[2:3], s[0:1], 0x18 s_load_b32 s8, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_mul_i32 s0, s7, s6 v_add_f32_e64 v2, s4, s5 s_lshr_b32 s1, s0, 31 v_cvt_f64_i32_e32 v[0:1], s8 s_add_i32 s0, s0, s1 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cvt_f64_f32_e32 v[2:3], v2 s_ashr_i32 s0, s0, 1 s_ashr_i32 s1, s0, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[0:1], s[0:1], 2 s_add_u32 s0, s2, s0 s_addc_u32 s1, s3, s1 s_load_b32 s0, s[0:1], 0x0 s_mov_b32 s1, 0x4027069e s_waitcnt lgkmcnt(0) v_cvt_f64_f32_e32 v[4:5], s0 s_mov_b32 s0, 0x2aa2aa5b s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[0:1], v[0:1], v[0:1] v_mul_f64 v[2:3], v[2:3], 0.5 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[4:5], v[4:5], 0x40240000 v_mul_f64 v[0:1], v[2:3], v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_mul_f64 v[2:3], v[4:5], s[0:1] s_getpc_b64 s[0:1] s_add_u32 s0, s0, d0@rel32@lo+4 s_addc_u32 s1, s1, d0@rel32@hi+12 v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[6:7], v[4:5] s_waitcnt_depctr 0xfff v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] v_div_scale_f64 v[8:9], vcc_lo, v[2:3], v[0:1], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[10:11], v[8:9], v[6:7] v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11] v_div_fixup_f64 v[0:1], v[4:5], v[0:1], v[2:3] s_delay_alu instid0(VALU_DEP_1) v_cvt_f32_f64_e32 v0, v[0:1] v_mov_b32_e32 v1, 0 global_store_b32 v1, v0, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6get_d0ffiiiPf .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 9 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end3: .size _Z6get_d0ffiiiPf, .Lfunc_end3-_Z6get_d0ffiiiPf ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 332 ; NumSgprs: 11 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 11 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z13initial_coffefiPfS_S_S_i ; -- Begin function _Z13initial_coffefiPfS_S_S_i .globl _Z13initial_coffefiPfS_S_S_i .p2align 8 .type _Z13initial_coffefiPfS_S_S_i,@function _Z13initial_coffefiPfS_S_S_i: ; @_Z13initial_coffefiPfS_S_S_i ; %bb.0: s_clause 0x2 s_load_b32 s3, s[0:1], 0x3c s_load_b32 s68, s[0:1], 0x28 s_load_b32 s2, s[0:1], 0x4 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1] s_lshl_b32 s3, s68, 1 s_add_i32 s3, s3, s2 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s3, v1 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB4_10 ; %bb.1: s_clause 0x2 s_load_b32 s33, s[0:1], 0x0 s_load_b128 s[4:7], s[0:1], 0x8 s_load_b64 s[8:9], s[0:1], 0x18 ; implicit-def: $vgpr0 s_mov_b32 s3, exec_lo v_cmpx_le_i32_e64 s68, v1 s_xor_b32 s69, exec_lo, s3 s_cbranch_execz .LBB4_7 ; %bb.2: s_add_i32 s71, s68, s2 ; implicit-def: $vgpr0 s_mov_b32 s3, exec_lo v_cmpx_le_i32_e64 s71, v1 s_xor_b32 s70, exec_lo, s3 s_cbranch_execz .LBB4_4 ; %bb.3: v_cvt_f64_i32_e32 v[2:3], v1 v_cvt_f64_i32_e32 v[7:8], s2 v_cvt_f64_i32_e32 v[5:6], s68 s_mov_b32 s11, 0x3fe55555 s_mov_b32 s10, 0x55555555 s_mov_b32 s13, 0x3fba6564 s_mov_b32 s12, 0x968915a9 s_mov_b32 s15, 0x3fbdee67 s_mov_b32 s14, 0x4222de17 s_mov_b32 s17, 0x3fbe25e4 s_mov_b32 s16, 0x3abe935a s_mov_b32 s19, 0x3fc110ef s_mov_b32 s18, 0x47e6c9c2 s_mov_b32 s21, 0x3fc3b13b s_mov_b32 s20, 0xcfa74449 s_mov_b32 s23, 0x3fc745d1 s_mov_b32 s22, 0x71bf3c30 s_mov_b32 s25, 0x3fcc71c7 s_mov_b32 s24, 0x1c7792ce s_mov_b32 s27, 0x3fd24924 s_mov_b32 s26, 0x924920da s_mov_b32 s29, 0x3fd99999 s_mov_b32 s28, 0x9999999c s_mov_b32 s31, 0xbfe55555 s_mov_b32 s30, s10 s_mov_b32 s35, 0x3c8543b0 s_mov_b32 s34, 0xd5df274d s_mov_b32 s37, 0x3fe62e42 s_mov_b32 s36, 0xfefa39ef s_mov_b32 s45, 0x3c7abc9e s_mov_b32 s44, 0x3b39803f s_mov_b32 s39, 0x3ff71547 s_mov_b32 s38, 0x652b82fe s_mov_b32 s43, 0xbfe62e42 s_mov_b32 s42, s36 s_mov_b32 s47, 0xbc7abc9e s_mov_b32 s46, s44 s_mov_b32 s49, 0x3e928af3 v_add_f64 v[2:3], v[2:3], 0.5 s_mov_b32 s48, 0xfca7ab0c s_mov_b32 s51, 0x3e5ade15 s_mov_b32 s50, 0x6a5dcb37 s_mov_b32 s53, 0x3ec71dee s_mov_b32 s52, 0x623fde64 s_mov_b32 s55, 0x3efa0199 s_mov_b32 s54, 0x7c89e6b0 s_mov_b32 s57, 0x3f2a01a0 s_mov_b32 s56, 0x14761f6e s_mov_b32 s59, 0x3f56c16c s_mov_b32 s58, 0x1852b7b0 s_mov_b32 s61, 0x3f811111 s_mov_b32 s60, 0x11122322 s_mov_b32 s63, 0x3fa55555 s_mov_b32 s62, 0x555502a1 s_mov_b32 s65, 0x3fc55555 s_mov_b32 s64, 0x55555511 s_mov_b32 s67, 0x3fe00000 s_mov_b32 s66, 11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[2:3], v[2:3], -v[7:8] v_add_f64 v[2:3], v[2:3], -v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], v[2:3] v_div_scale_f64 v[13:14], vcc_lo, v[2:3], v[5:6], v[2:3] v_rcp_f64_e32 v[9:10], v[7:8] s_waitcnt_depctr 0xfff v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10] v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10] v_mul_f64 v[11:12], v[13:14], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14] v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fixup_f64 v[7:8], v[7:8], v[5:6], v[2:3] v_frexp_mant_f64_e64 v[2:3], |v[7:8]| v_cmp_class_f64_e64 s72, v[7:8], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, s[10:11], v[2:3] v_cndmask_b32_e64 v0, 0, 1, vcc_lo v_ldexp_f64 v[2:3], v[2:3], v0 v_frexp_exp_i32_f64_e32 v0, v[7:8] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[9:10], v[2:3], 1.0 v_add_f64 v[15:16], v[2:3], -1.0 v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo v_cmp_eq_f64_e32 vcc_lo, 1.0, v[7:8] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_rcp_f64_e32 v[11:12], v[9:10] v_add_f64 v[17:18], v[9:10], -1.0 v_cndmask_b32_e64 v4, 2.0, 0x3ff00000, vcc_lo v_add_f64 v[2:3], v[2:3], -v[17:18] s_waitcnt_depctr 0xfff v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], v[13:14], v[11:12], v[11:12] v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], v[13:14], v[11:12], v[11:12] v_mul_f64 v[13:14], v[15:16], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[19:20], v[9:10], v[13:14] v_fma_f64 v[9:10], v[13:14], v[9:10], -v[19:20] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[2:3], v[13:14], v[2:3], v[9:10] v_add_f64 v[9:10], v[19:20], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[17:18], v[15:16], -v[9:10] v_add_f64 v[19:20], v[9:10], -v[19:20] v_add_f64 v[15:16], v[15:16], -v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[2:3], v[19:20], -v[2:3] v_add_f64 v[9:10], v[15:16], -v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[2:3], v[2:3], v[9:10] v_add_f64 v[2:3], v[17:18], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[2:3], v[11:12], v[2:3] v_add_f64 v[9:10], v[13:14], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[11:12], v[9:10], -v[13:14] v_mul_f64 v[13:14], v[9:10], v[9:10] v_add_f64 v[2:3], v[2:3], -v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[11:12], v[9:10], v[9:10], -v[13:14] v_add_f64 v[15:16], v[2:3], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], v[9:10], v[15:16], v[11:12] v_add_f64 v[15:16], v[13:14], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[17:18], v[15:16], s[14:15], s[12:13] v_add_f64 v[13:14], v[15:16], -v[13:14] v_mul_f64 v[23:24], v[9:10], v[15:16] v_fma_f64 v[17:18], v[15:16], v[17:18], s[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[11:12], v[11:12], -v[13:14] v_fma_f64 v[17:18], v[15:16], v[17:18], s[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[17:18], v[15:16], v[17:18], s[20:21] v_fma_f64 v[17:18], v[15:16], v[17:18], s[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[17:18], v[15:16], v[17:18], s[24:25] v_fma_f64 v[17:18], v[15:16], v[17:18], s[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[17:18], v[15:16], v[17:18], s[28:29] v_mul_f64 v[19:20], v[15:16], v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[13:14], v[15:16], v[17:18], -v[19:20] v_fma_f64 v[13:14], v[11:12], v[17:18], v[13:14] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[17:18], v[19:20], v[13:14] v_add_f64 v[21:22], v[17:18], s[10:11] v_add_f64 v[19:20], v[17:18], -v[19:20] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[25:26], v[21:22], s[30:31] v_add_f64 v[13:14], v[13:14], -v[19:20] v_fma_f64 v[19:20], v[15:16], v[9:10], -v[23:24] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[17:18], v[17:18], -v[25:26] v_add_f64 v[13:14], v[13:14], s[34:35] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[15:16], v[15:16], v[2:3], v[19:20] v_ldexp_f64 v[2:3], v[2:3], 1 v_add_f64 v[13:14], v[13:14], v[17:18] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[11:12], v[11:12], v[9:10], v[15:16] v_ldexp_f64 v[9:10], v[9:10], 1 v_add_f64 v[15:16], v[21:22], v[13:14] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[17:18], v[23:24], v[11:12] v_add_f64 v[19:20], v[21:22], -v[15:16] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mul_f64 v[21:22], v[17:18], v[15:16] v_add_f64 v[23:24], v[17:18], -v[23:24] v_add_f64 v[13:14], v[13:14], v[19:20] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[19:20], v[17:18], v[15:16], -v[21:22] v_add_f64 v[11:12], v[11:12], -v[23:24] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[13:14], v[17:18], v[13:14], v[19:20] v_fma_f64 v[11:12], v[11:12], v[15:16], v[13:14] v_cvt_f64_i32_e32 v[15:16], v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[13:14], v[21:22], v[11:12] v_add_f64 v[17:18], v[9:10], v[13:14] v_add_f64 v[19:20], v[13:14], -v[21:22] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f64 v[21:22], v[15:16], s[36:37] v_add_f64 v[9:10], v[17:18], -v[9:10] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[11:12], v[11:12], -v[19:20] v_fma_f64 v[19:20], v[15:16], s[36:37], -v[21:22] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[9:10], v[13:14], -v[9:10] v_add_f64 v[2:3], v[2:3], v[11:12] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[11:12], v[15:16], s[44:45], v[19:20] v_add_f64 v[2:3], v[2:3], v[9:10] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[9:10], v[21:22], v[11:12] v_add_f64 v[13:14], v[17:18], v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[21:22], v[9:10], -v[21:22] v_add_f64 v[15:16], v[9:10], v[13:14] v_add_f64 v[17:18], v[13:14], -v[17:18] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[11:12], v[11:12], -v[21:22] v_add_f64 v[19:20], v[15:16], -v[9:10] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[2:3], v[2:3], -v[17:18] v_add_f64 v[23:24], v[15:16], -v[19:20] v_add_f64 v[13:14], v[13:14], -v[19:20] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[17:18], v[11:12], v[2:3] v_add_f64 v[9:10], v[9:10], -v[23:24] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[9:10], v[13:14], v[9:10] v_add_f64 v[13:14], v[17:18], -v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[9:10], v[17:18], v[9:10] v_add_f64 v[17:18], v[17:18], -v[13:14] v_add_f64 v[2:3], v[2:3], -v[13:14] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[19:20], v[15:16], v[9:10] v_add_f64 v[11:12], v[11:12], -v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[13:14], v[19:20], -v[15:16] v_add_f64 v[2:3], v[2:3], v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[9:10], v[9:10], -v[13:14] v_add_f64 v[9:10], v[2:3], v[9:10] v_mov_b32_e32 v3, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[11:12], v[19:20], v[9:10] v_add_f64 v[13:14], v[11:12], -v[19:20] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[15:16], v[3:4], v[11:12] v_add_f64 v[9:10], v[9:10], -v[13:14] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[11:12], v[3:4], v[11:12], -v[15:16] v_cmp_class_f64_e64 vcc_lo, v[15:16], 0x204 v_fma_f64 v[9:10], v[3:4], v[9:10], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[11:12], v[15:16], v[9:10] v_dual_cndmask_b32 v14, v12, v16 :: v_dual_cndmask_b32 v13, v11, v15 v_add_f64 v[11:12], v[11:12], -v[15:16] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[13:14]| v_add_f64 v[9:10], v[9:10], -v[11:12] v_trunc_f64_e32 v[11:12], v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v10, 0, v10, vcc_lo v_mul_f64 v[17:18], v[13:14], s[38:39] v_cmp_nlt_f64_e64 s2, 0x40900000, v[13:14] v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[13:14] v_cndmask_b32_e32 v9, 0, v9, vcc_lo v_rndne_f64_e32 v[17:18], v[17:18] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) s_and_b32 vcc_lo, s3, s2 v_fma_f64 v[19:20], v[17:18], s[42:43], v[13:14] v_cvt_i32_f64_e32 v0, v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[19:20], v[17:18], s[46:47], v[19:20] v_fma_f64 v[21:22], v[19:20], s[50:51], s[48:49] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[52:53] v_fma_f64 v[21:22], v[19:20], v[21:22], s[54:55] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[56:57] v_fma_f64 v[21:22], v[19:20], v[21:22], s[58:59] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[60:61] v_fma_f64 v[21:22], v[19:20], v[21:22], s[62:63] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[64:65] v_fma_f64 v[21:22], v[19:20], v[21:22], s[66:67] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[21:22], v[19:20], v[21:22], 1.0 v_fma_f64 v[17:18], v[19:20], v[21:22], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[15:16], v[17:18], v0 v_mul_f64 v[17:18], v[3:4], 0.5 v_cndmask_b32_e64 v0, 0x7ff00000, v16, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_trunc_f64_e32 v[13:14], v[17:18] v_cndmask_b32_e32 v15, 0, v15, vcc_lo v_cmp_eq_f64_e32 vcc_lo, v[11:12], v[3:4] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v16, 0, v0, s3 v_fma_f64 v[9:10], v[15:16], v[9:10], v[15:16] v_cmp_class_f64_e64 s3, v[15:16], 0x204 v_cmp_neq_f64_e64 s2, v[13:14], v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v4, v10, v16, s3 v_cndmask_b32_e64 v2, v9, v15, s3 v_cmp_eq_f64_e64 s3, 0, v[7:8] s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e32 v9, 0, v2, vcc_lo s_and_b32 s2, vcc_lo, s2 s_getpc_b64 s[40:41] s_add_u32 s40, s40, d0@rel32@lo+4 s_addc_u32 s41, s41, d0@rel32@hi+12 v_cndmask_b32_e64 v0, 0x3ff00000, v8, s2 s_load_b32 s73, s[40:41], 0x0 v_cndmask_b32_e64 v11, 0, v8, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_bfi_b32 v0, 0x7fffffff, v4, v0 v_cndmask_b32_e32 v4, 0x7ff80000, v0, vcc_lo v_cmp_gt_f64_e32 vcc_lo, 0, v[7:8] v_cndmask_b32_e64 v10, 0x7ff00000, 0, s3 s_delay_alu instid0(VALU_DEP_1) v_bfi_b32 v10, 0x7fffffff, v10, v11 v_cndmask_b32_e32 v2, v2, v9, vcc_lo v_cndmask_b32_e32 v0, v0, v4, vcc_lo s_or_b32 vcc_lo, s3, s72 s_waitcnt lgkmcnt(0) v_mul_f32_e64 v4, s73, s33 v_cndmask_b32_e64 v2, v2, 0, vcc_lo v_cndmask_b32_e32 v0, v0, v10, vcc_lo v_cmp_o_f64_e32 vcc_lo, v[7:8], v[7:8] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cvt_f64_f32_e32 v[7:8], v4 v_cndmask_b32_e32 v9, 0, v2, vcc_lo s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v10, 0x7ff80000, v0, vcc_lo v_subrev_nc_u32_e32 v0, s71, v1 v_ashrrev_i32_e32 v2, 31, v1 v_mul_f64 v[7:8], v[9:10], v[7:8] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_f64_i32_e32 v[11:12], v0 v_fma_f64 v[7:8], v[7:8], 0.5, 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_scale_f64 v[15:16], null, v[5:6], v[5:6], v[11:12] v_div_scale_f64 v[13:14], null, v[7:8], v[7:8], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_rcp_f64_e32 v[19:20], v[15:16] v_div_scale_f64 v[25:26], vcc_lo, 1.0, v[7:8], 1.0 v_rcp_f64_e32 v[17:18], v[13:14] s_waitcnt_depctr 0xfff v_fma_f64 v[23:24], -v[15:16], v[19:20], 1.0 v_fma_f64 v[21:22], -v[13:14], v[17:18], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20] v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[23:24], -v[15:16], v[19:20], 1.0 v_fma_f64 v[21:22], -v[13:14], v[17:18], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20] v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18] v_div_scale_f64 v[21:22], s2, v[11:12], v[5:6], v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[23:24], v[25:26], v[17:18] v_mul_f64 v[27:28], v[21:22], v[19:20] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[13:14], -v[13:14], v[23:24], v[25:26] v_fma_f64 v[15:16], -v[15:16], v[27:28], v[21:22] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fmas_f64 v[13:14], v[13:14], v[17:18], v[23:24] s_mov_b32 vcc_lo, s2 v_div_fmas_f64 v[15:16], v[15:16], v[19:20], v[27:28] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_fixup_f64 v[7:8], v[13:14], v[7:8], 1.0 v_div_fixup_f64 v[5:6], v[15:16], v[5:6], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_frexp_mant_f64_e64 v[11:12], |v[5:6]| v_cmp_gt_f64_e32 vcc_lo, s[10:11], v[11:12] v_cndmask_b32_e64 v0, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[11:12], v[11:12], v0 v_frexp_exp_i32_f64_e32 v0, v[5:6] v_add_f64 v[15:16], v[11:12], 1.0 v_add_f64 v[21:22], v[11:12], -1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo v_cmp_eq_f64_e32 vcc_lo, 1.0, v[5:6] v_rcp_f64_e32 v[17:18], v[15:16] v_add_f64 v[23:24], v[15:16], -1.0 v_cndmask_b32_e64 v4, 2.0, 0x3ff00000, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_f64 v[11:12], v[11:12], -v[23:24] s_waitcnt_depctr 0xfff v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0 v_fma_f64 v[17:18], v[19:20], v[17:18], v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0 v_fma_f64 v[17:18], v[19:20], v[17:18], v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[19:20], v[21:22], v[17:18] v_mul_f64 v[25:26], v[15:16], v[19:20] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[15:16], v[19:20], v[15:16], -v[25:26] v_fma_f64 v[11:12], v[19:20], v[11:12], v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[15:16], v[25:26], v[11:12] v_add_f64 v[23:24], v[21:22], -v[15:16] v_add_f64 v[25:26], v[15:16], -v[25:26] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[21:22], v[21:22], -v[23:24] v_add_f64 v[11:12], v[25:26], -v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[15:16], v[21:22], -v[15:16] v_add_f64 v[11:12], v[11:12], v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[11:12], v[23:24], v[11:12] v_mul_f64 v[11:12], v[17:18], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[15:16], v[19:20], v[11:12] v_add_f64 v[17:18], v[15:16], -v[19:20] v_mul_f64 v[19:20], v[15:16], v[15:16] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[11:12], v[11:12], -v[17:18] v_fma_f64 v[17:18], v[15:16], v[15:16], -v[19:20] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[21:22], v[11:12], v[11:12] v_fma_f64 v[17:18], v[15:16], v[21:22], v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[21:22], v[19:20], v[17:18] v_fma_f64 v[23:24], v[21:22], s[14:15], s[12:13] v_add_f64 v[19:20], v[21:22], -v[19:20] v_mul_f64 v[29:30], v[15:16], v[21:22] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[23:24], v[21:22], v[23:24], s[16:17] v_add_f64 v[17:18], v[17:18], -v[19:20] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], v[21:22], v[23:24], s[18:19] v_fma_f64 v[23:24], v[21:22], v[23:24], s[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], v[21:22], v[23:24], s[22:23] v_fma_f64 v[23:24], v[21:22], v[23:24], s[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], v[21:22], v[23:24], s[26:27] v_fma_f64 v[23:24], v[21:22], v[23:24], s[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[25:26], v[21:22], v[23:24] v_fma_f64 v[19:20], v[21:22], v[23:24], -v[25:26] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[19:20], v[17:18], v[23:24], v[19:20] v_add_f64 v[23:24], v[25:26], v[19:20] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_f64 v[27:28], v[23:24], s[10:11] v_add_f64 v[25:26], v[23:24], -v[25:26] v_cmp_class_f64_e64 s10, v[5:6], 0x204 v_add_f64 v[31:32], v[27:28], s[30:31] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[19:20], v[19:20], -v[25:26] v_fma_f64 v[25:26], v[21:22], v[15:16], -v[29:30] v_add_f64 v[23:24], v[23:24], -v[31:32] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[19:20], v[19:20], s[34:35] v_fma_f64 v[21:22], v[21:22], v[11:12], v[25:26] v_ldexp_f64 v[11:12], v[11:12], 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[19:20], v[19:20], v[23:24] v_fma_f64 v[17:18], v[17:18], v[15:16], v[21:22] v_ldexp_f64 v[15:16], v[15:16], 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[21:22], v[27:28], v[19:20] v_add_f64 v[23:24], v[29:30], v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[25:26], v[27:28], -v[21:22] v_mul_f64 v[27:28], v[23:24], v[21:22] v_add_f64 v[29:30], v[23:24], -v[29:30] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[19:20], v[19:20], v[25:26] v_fma_f64 v[25:26], v[23:24], v[21:22], -v[27:28] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[17:18], v[17:18], -v[29:30] v_fma_f64 v[19:20], v[23:24], v[19:20], v[25:26] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[17:18], v[17:18], v[21:22], v[19:20] v_cvt_f64_i32_e32 v[21:22], v0 v_cvt_f32_f64_e32 v0, v[7:8] v_add_f64 v[19:20], v[27:28], v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_f64 v[23:24], v[15:16], v[19:20] v_add_f64 v[25:26], v[19:20], -v[27:28] v_mul_f64 v[27:28], v[21:22], s[36:37] v_add_f64 v[15:16], v[23:24], -v[15:16] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[17:18], v[17:18], -v[25:26] v_fma_f64 v[25:26], v[21:22], s[36:37], -v[27:28] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[15:16], v[19:20], -v[15:16] v_add_f64 v[11:12], v[11:12], v[17:18] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[17:18], v[21:22], s[44:45], v[25:26] v_add_f64 v[11:12], v[11:12], v[15:16] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[15:16], v[27:28], v[17:18] v_add_f64 v[19:20], v[23:24], v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[27:28], v[15:16], -v[27:28] v_add_f64 v[21:22], v[15:16], v[19:20] v_add_f64 v[23:24], v[19:20], -v[23:24] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[17:18], v[17:18], -v[27:28] v_mov_b32_e32 v27, 0 v_add_f64 v[25:26], v[21:22], -v[15:16] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[11:12], v[11:12], -v[23:24] v_add_f64 v[29:30], v[21:22], -v[25:26] v_add_f64 v[19:20], v[19:20], -v[25:26] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[23:24], v[17:18], v[11:12] v_add_f64 v[15:16], v[15:16], -v[29:30] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[15:16], v[19:20], v[15:16] v_add_f64 v[19:20], v[23:24], -v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[15:16], v[23:24], v[15:16] v_add_f64 v[23:24], v[23:24], -v[19:20] v_add_f64 v[11:12], v[11:12], -v[19:20] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[25:26], v[21:22], v[15:16] v_add_f64 v[17:18], v[17:18], -v[23:24] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[19:20], v[25:26], -v[21:22] v_add_f64 v[11:12], v[11:12], v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[15:16], v[15:16], -v[19:20] v_add_f64 v[11:12], v[11:12], v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[15:16], v[25:26], v[11:12] v_add_f64 v[13:14], v[15:16], -v[25:26] v_mul_f64 v[17:18], v[3:4], v[15:16] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[7:8], v[11:12], -v[13:14] v_lshlrev_b64 v[13:14], 2, v[1:2] v_fma_f64 v[11:12], v[3:4], v[15:16], -v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v15, vcc_lo, s4, v13 v_add_co_ci_u32_e32 v16, vcc_lo, s5, v14, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[17:18], 0x204 global_store_b32 v[15:16], v0, off global_load_b32 v25, v27, s[40:41] v_fma_f64 v[7:8], v[3:4], v[7:8], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[11:12], v[17:18], v[7:8] v_dual_cndmask_b32 v16, v12, v18 :: v_dual_cndmask_b32 v15, v11, v17 v_add_f64 v[11:12], v[11:12], -v[17:18] v_mul_f64 v[17:18], v[3:4], 0.5 s_delay_alu instid0(VALU_DEP_2) v_add_f64 v[7:8], v[7:8], -v[11:12] s_waitcnt vmcnt(0) v_mul_f32_e32 v25, s33, v25 v_mul_f64 v[19:20], v[15:16], s[38:39] v_cmp_nlt_f64_e64 s2, 0x40900000, v[15:16] v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[15:16] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cvt_f64_f32_e32 v[25:26], v25 v_rndne_f64_e32 v[19:20], v[19:20] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mul_f64 v[9:10], v[9:10], v[25:26] v_cvt_f64_f32_e32 v[25:26], v0 v_fma_f64 v[21:22], v[19:20], s[42:43], v[15:16] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[9:10], v[9:10], -0.5, 1.0 v_fma_f64 v[21:22], v[19:20], s[46:47], v[21:22] v_cvt_i32_f64_e32 v19, v[19:20] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f64 v[9:10], v[9:10], v[25:26] v_fma_f64 v[23:24], v[21:22], s[50:51], s[48:49] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_f32_f64_e32 v0, v[9:10] v_fma_f64 v[23:24], v[21:22], v[23:24], s[52:53] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], v[21:22], v[23:24], s[54:55] v_fma_f64 v[23:24], v[21:22], v[23:24], s[56:57] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], v[21:22], v[23:24], s[58:59] v_fma_f64 v[23:24], v[21:22], v[23:24], s[60:61] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], v[21:22], v[23:24], s[62:63] v_fma_f64 v[9:10], v[21:22], v[23:24], s[64:65] v_add_co_u32 v23, vcc_lo, s6, v13 v_add_co_ci_u32_e32 v24, vcc_lo, s7, v14, vcc_lo v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[15:16]| v_trunc_f64_e32 v[15:16], v[17:18] global_store_b32 v[23:24], v0, off global_load_b32 v0, v27, s[40:41] v_fma_f64 v[9:10], v[21:22], v[9:10], s[66:67] v_dual_cndmask_b32 v8, 0, v8 :: v_dual_cndmask_b32 v7, 0, v7 s_and_b32 vcc_lo, s3, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[9:10], v[21:22], v[9:10], 1.0 v_fma_f64 v[9:10], v[21:22], v[9:10], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[9:10], v[9:10], v19 v_cndmask_b32_e64 v12, 0x7ff00000, v10, s2 v_trunc_f64_e32 v[10:11], v[3:4] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v19, 0, v9, vcc_lo v_cmp_neq_f64_e64 s2, v[15:16], v[17:18] v_cndmask_b32_e64 v20, 0, v12, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_cmp_class_f64_e64 s3, v[19:20], 0x204 v_cmp_eq_f64_e32 vcc_lo, v[10:11], v[3:4] s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v10, 0, v6, s2 s_waitcnt vmcnt(0) v_mul_f32_e32 v0, s33, v0 v_fma_f64 v[3:4], v[19:20], v[7:8], v[19:20] v_cndmask_b32_e64 v7, 0x3ff00000, v6, s2 v_cndmask_b32_e64 v4, v4, v20, s3 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v3, v3, v19, s3 v_cmp_eq_f64_e64 s3, 0, v[5:6] v_bfi_b32 v4, 0x7fffffff, v4, v7 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v8, 0, v3, vcc_lo v_cndmask_b32_e32 v7, 0x7ff80000, v4, vcc_lo v_cmp_gt_f64_e32 vcc_lo, 0, v[5:6] v_cndmask_b32_e64 v9, 0x7ff00000, 0, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_bfi_b32 v9, 0x7fffffff, v9, v10 v_dual_cndmask_b32 v4, v4, v7 :: v_dual_cndmask_b32 v3, v3, v8 s_or_b32 vcc_lo, s3, s10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v7, v4, v9, vcc_lo v_cndmask_b32_e64 v8, v3, 0, vcc_lo v_cmp_o_f64_e32 vcc_lo, v[5:6], v[5:6] v_cvt_f64_f32_e32 v[3:4], v0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v5, 0, v8, vcc_lo v_cndmask_b32_e32 v6, 0x7ff80000, v7, vcc_lo v_mul_f64 v[3:4], v[5:6], v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[3:4], v[3:4], 0.5, 1.0 v_div_scale_f64 v[7:8], null, v[3:4], v[3:4], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[9:10], v[7:8] s_waitcnt_depctr 0xfff v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10] v_div_scale_f64 v[11:12], vcc_lo, 1.0, v[3:4], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[15:16], v[11:12], v[9:10] v_fma_f64 v[7:8], -v[7:8], v[15:16], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[15:16] v_div_fixup_f64 v[3:4], v[7:8], v[3:4], 1.0 s_delay_alu instid0(VALU_DEP_1) v_cvt_f32_f64_e32 v0, v[3:4] v_add_co_u32 v3, vcc_lo, s8, v13 v_add_co_ci_u32_e32 v4, vcc_lo, s9, v14, vcc_lo global_store_b32 v[3:4], v0, off global_load_b32 v3, v27, s[40:41] s_waitcnt vmcnt(0) v_mul_f32_e32 v3, s33, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_f64_f32_e32 v[3:4], v3 v_mul_f64 v[3:4], v[5:6], v[3:4] v_cvt_f64_f32_e32 v[5:6], v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[3:4], v[3:4], -0.5, 1.0 v_mul_f64 v[3:4], v[3:4], v[5:6] s_delay_alu instid0(VALU_DEP_1) v_cvt_f32_f64_e32 v0, v[3:4] .LBB4_4: ; %Flow s_and_not1_saveexec_b32 s2, s70 s_cbranch_execz .LBB4_6 ; %bb.5: v_ashrrev_i32_e32 v2, 31, v1 v_mov_b32_e32 v0, 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[3:4], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v5, vcc_lo, s4, v3 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo v_add_co_u32 v7, vcc_lo, s6, v3 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo v_add_co_u32 v3, vcc_lo, s8, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo global_store_b32 v[5:6], v0, off global_store_b32 v[7:8], v0, off global_store_b32 v[3:4], v0, off .LBB4_6: ; %Flow97 s_or_b32 exec_lo, exec_lo, s2 .LBB4_7: ; %Flow98 s_and_not1_saveexec_b32 s69, s69 s_cbranch_execz .LBB4_9 ; %bb.8: v_cvt_f64_i32_e32 v[5:6], s68 v_cvt_f64_i32_e32 v[2:3], v1 s_mov_b32 s11, 0x3fe55555 s_mov_b32 s10, 0x55555555 s_mov_b32 s15, 0x3fba6564 s_mov_b32 s14, 0x968915a9 s_mov_b32 s17, 0x3fbdee67 s_mov_b32 s16, 0x4222de17 s_mov_b32 s19, 0x3fbe25e4 s_mov_b32 s18, 0x3abe935a s_mov_b32 s21, 0x3fc110ef s_mov_b32 s20, 0x47e6c9c2 s_mov_b32 s23, 0x3fc3b13b s_mov_b32 s22, 0xcfa74449 s_mov_b32 s25, 0x3fc745d1 s_mov_b32 s24, 0x71bf3c30 s_mov_b32 s27, 0x3fcc71c7 s_mov_b32 s26, 0x1c7792ce s_mov_b32 s29, 0x3fd24924 s_mov_b32 s28, 0x924920da s_mov_b32 s31, 0x3fd99999 s_mov_b32 s30, 0x9999999c s_mov_b32 s35, 0xbfe55555 s_mov_b32 s34, s10 s_mov_b32 s37, 0x3c8543b0 s_mov_b32 s36, 0xd5df274d s_mov_b32 s39, 0x3fe62e42 s_mov_b32 s38, 0xfefa39ef s_mov_b32 s45, 0x3c7abc9e s_mov_b32 s44, 0x3b39803f s_mov_b32 s41, 0x3ff71547 s_mov_b32 s40, 0x652b82fe s_mov_b32 s43, 0xbfe62e42 s_mov_b32 s42, s38 s_mov_b32 s47, 0xbc7abc9e s_mov_b32 s46, s44 s_mov_b32 s49, 0x3e928af3 s_mov_b32 s48, 0xfca7ab0c v_add_f64 v[7:8], v[5:6], -0.5 s_mov_b32 s51, 0x3e5ade15 s_mov_b32 s50, 0x6a5dcb37 s_mov_b32 s53, 0x3ec71dee s_mov_b32 s52, 0x623fde64 s_mov_b32 s55, 0x3efa0199 s_mov_b32 s54, 0x7c89e6b0 s_mov_b32 s57, 0x3f2a01a0 s_mov_b32 s56, 0x14761f6e s_mov_b32 s59, 0x3f56c16c s_mov_b32 s58, 0x1852b7b0 s_mov_b32 s61, 0x3f811111 s_mov_b32 s60, 0x11122322 s_mov_b32 s63, 0x3fa55555 s_mov_b32 s62, 0x555502a1 s_getpc_b64 s[12:13] s_add_u32 s12, s12, d0@rel32@lo+4 s_addc_u32 s13, s13, d0@rel32@hi+12 s_mov_b32 s65, 0x3fc55555 s_mov_b32 s64, 0x55555511 s_mov_b32 s67, 0x3fe00000 s_mov_b32 s66, 11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[2:3], v[7:8], -v[2:3] v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], v[2:3] v_div_scale_f64 v[13:14], vcc_lo, v[2:3], v[5:6], v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[9:10], v[7:8] s_waitcnt_depctr 0xfff v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[11:12], v[13:14], v[9:10] v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12] v_div_fixup_f64 v[7:8], v[7:8], v[5:6], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_frexp_mant_f64_e64 v[2:3], |v[7:8]| v_cmp_class_f64_e64 s70, v[7:8], 0x204 v_cmp_gt_f64_e32 vcc_lo, s[10:11], v[2:3] v_cndmask_b32_e64 v0, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[2:3], v[2:3], v0 v_frexp_exp_i32_f64_e32 v0, v[7:8] v_add_f64 v[9:10], v[2:3], 1.0 v_add_f64 v[15:16], v[2:3], -1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo v_cmp_eq_f64_e32 vcc_lo, 1.0, v[7:8] v_rcp_f64_e32 v[11:12], v[9:10] v_add_f64 v[17:18], v[9:10], -1.0 v_cndmask_b32_e64 v4, 2.0, 0x3ff00000, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_f64 v[2:3], v[2:3], -v[17:18] s_waitcnt_depctr 0xfff v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0 v_fma_f64 v[11:12], v[13:14], v[11:12], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0 v_fma_f64 v[11:12], v[13:14], v[11:12], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[13:14], v[15:16], v[11:12] v_mul_f64 v[19:20], v[9:10], v[13:14] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[9:10], v[13:14], v[9:10], -v[19:20] v_fma_f64 v[2:3], v[13:14], v[2:3], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[9:10], v[19:20], v[2:3] v_add_f64 v[17:18], v[15:16], -v[9:10] v_add_f64 v[19:20], v[9:10], -v[19:20] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[15:16], v[15:16], -v[17:18] v_add_f64 v[2:3], v[19:20], -v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[9:10], v[15:16], -v[9:10] v_add_f64 v[2:3], v[2:3], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[2:3], v[17:18], v[2:3] v_mul_f64 v[2:3], v[11:12], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[9:10], v[13:14], v[2:3] v_add_f64 v[11:12], v[9:10], -v[13:14] v_mul_f64 v[13:14], v[9:10], v[9:10] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[2:3], v[2:3], -v[11:12] v_fma_f64 v[11:12], v[9:10], v[9:10], -v[13:14] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[15:16], v[2:3], v[2:3] v_fma_f64 v[11:12], v[9:10], v[15:16], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[15:16], v[13:14], v[11:12] v_fma_f64 v[17:18], v[15:16], s[16:17], s[14:15] v_add_f64 v[13:14], v[15:16], -v[13:14] v_mul_f64 v[23:24], v[9:10], v[15:16] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[17:18], v[15:16], v[17:18], s[18:19] v_add_f64 v[11:12], v[11:12], -v[13:14] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[17:18], v[15:16], v[17:18], s[20:21] v_fma_f64 v[17:18], v[15:16], v[17:18], s[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[17:18], v[15:16], v[17:18], s[24:25] v_fma_f64 v[17:18], v[15:16], v[17:18], s[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[17:18], v[15:16], v[17:18], s[28:29] v_fma_f64 v[17:18], v[15:16], v[17:18], s[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[19:20], v[15:16], v[17:18] v_fma_f64 v[13:14], v[15:16], v[17:18], -v[19:20] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[13:14], v[11:12], v[17:18], v[13:14] v_add_f64 v[17:18], v[19:20], v[13:14] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[21:22], v[17:18], s[10:11] v_add_f64 v[19:20], v[17:18], -v[19:20] v_add_f64 v[25:26], v[21:22], s[34:35] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[13:14], v[13:14], -v[19:20] v_fma_f64 v[19:20], v[15:16], v[9:10], -v[23:24] v_add_f64 v[17:18], v[17:18], -v[25:26] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[13:14], v[13:14], s[36:37] v_fma_f64 v[15:16], v[15:16], v[2:3], v[19:20] v_ldexp_f64 v[2:3], v[2:3], 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[13:14], v[13:14], v[17:18] v_fma_f64 v[11:12], v[11:12], v[9:10], v[15:16] v_ldexp_f64 v[9:10], v[9:10], 1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[15:16], v[21:22], v[13:14] v_add_f64 v[17:18], v[23:24], v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[19:20], v[21:22], -v[15:16] v_mul_f64 v[21:22], v[17:18], v[15:16] v_add_f64 v[23:24], v[17:18], -v[23:24] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[13:14], v[13:14], v[19:20] v_fma_f64 v[19:20], v[17:18], v[15:16], -v[21:22] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[11:12], v[11:12], -v[23:24] v_fma_f64 v[13:14], v[17:18], v[13:14], v[19:20] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[11:12], v[11:12], v[15:16], v[13:14] v_cvt_f64_i32_e32 v[15:16], v0 v_mov_b32_e32 v0, 0 v_add_f64 v[13:14], v[21:22], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_f64 v[17:18], v[9:10], v[13:14] v_add_f64 v[19:20], v[13:14], -v[21:22] v_mul_f64 v[21:22], v[15:16], s[38:39] v_add_f64 v[9:10], v[17:18], -v[9:10] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[11:12], v[11:12], -v[19:20] v_fma_f64 v[19:20], v[15:16], s[38:39], -v[21:22] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[9:10], v[13:14], -v[9:10] v_add_f64 v[2:3], v[2:3], v[11:12] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[11:12], v[15:16], s[44:45], v[19:20] v_add_f64 v[2:3], v[2:3], v[9:10] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[9:10], v[21:22], v[11:12] v_add_f64 v[13:14], v[17:18], v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[21:22], v[9:10], -v[21:22] v_add_f64 v[15:16], v[9:10], v[13:14] v_add_f64 v[17:18], v[13:14], -v[17:18] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[11:12], v[11:12], -v[21:22] v_add_f64 v[19:20], v[15:16], -v[9:10] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[2:3], v[2:3], -v[17:18] v_add_f64 v[23:24], v[15:16], -v[19:20] v_add_f64 v[13:14], v[13:14], -v[19:20] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[17:18], v[11:12], v[2:3] v_add_f64 v[9:10], v[9:10], -v[23:24] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[9:10], v[13:14], v[9:10] v_add_f64 v[13:14], v[17:18], -v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[9:10], v[17:18], v[9:10] v_add_f64 v[17:18], v[17:18], -v[13:14] v_add_f64 v[2:3], v[2:3], -v[13:14] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[19:20], v[15:16], v[9:10] v_add_f64 v[11:12], v[11:12], -v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[13:14], v[19:20], -v[15:16] v_add_f64 v[2:3], v[2:3], v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[9:10], v[9:10], -v[13:14] v_add_f64 v[9:10], v[2:3], v[9:10] v_mov_b32_e32 v3, 0 global_load_b32 v2, v0, s[12:13] v_add_f64 v[11:12], v[19:20], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[13:14], v[11:12], -v[19:20] v_mul_f64 v[15:16], v[3:4], v[11:12] v_add_f64 v[9:10], v[9:10], -v[13:14] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[11:12], v[3:4], v[11:12], -v[15:16] v_cmp_class_f64_e64 vcc_lo, v[15:16], 0x204 v_fma_f64 v[9:10], v[3:4], v[9:10], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[11:12], v[15:16], v[9:10] v_dual_cndmask_b32 v14, v12, v16 :: v_dual_cndmask_b32 v13, v11, v15 v_add_f64 v[11:12], v[11:12], -v[15:16] s_delay_alu instid0(VALU_DEP_2) v_mul_f64 v[17:18], v[13:14], s[40:41] v_cmp_nlt_f64_e64 s2, 0x40900000, v[13:14] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[13:14]| v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[13:14] v_add_f64 v[9:10], v[9:10], -v[11:12] v_trunc_f64_e32 v[11:12], v[3:4] v_rndne_f64_e32 v[17:18], v[17:18] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v10, 0, v10 :: v_dual_cndmask_b32 v9, 0, v9 s_and_b32 vcc_lo, s3, s2 v_fma_f64 v[19:20], v[17:18], s[42:43], v[13:14] v_cvt_i32_f64_e32 v23, v[17:18] s_waitcnt vmcnt(0) lgkmcnt(0) v_mul_f32_e32 v2, s33, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[19:20], v[17:18], s[46:47], v[19:20] v_fma_f64 v[21:22], v[19:20], s[50:51], s[48:49] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[52:53] v_fma_f64 v[21:22], v[19:20], v[21:22], s[54:55] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[56:57] v_fma_f64 v[21:22], v[19:20], v[21:22], s[58:59] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[60:61] v_fma_f64 v[21:22], v[19:20], v[21:22], s[62:63] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[21:22], v[19:20], v[21:22], s[64:65] v_fma_f64 v[21:22], v[19:20], v[21:22], s[66:67] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[21:22], v[19:20], v[21:22], 1.0 v_fma_f64 v[17:18], v[19:20], v[21:22], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[15:16], v[17:18], v23 v_mul_f64 v[17:18], v[3:4], 0.5 v_cndmask_b32_e64 v16, 0x7ff00000, v16, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_trunc_f64_e32 v[13:14], v[17:18] v_cndmask_b32_e32 v15, 0, v15, vcc_lo v_cmp_eq_f64_e32 vcc_lo, v[11:12], v[3:4] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v16, 0, v16, s3 v_fma_f64 v[9:10], v[15:16], v[9:10], v[15:16] v_cmp_class_f64_e64 s3, v[15:16], 0x204 v_cmp_neq_f64_e64 s2, v[13:14], v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v10, v10, v16, s3 v_cndmask_b32_e64 v9, v9, v15, s3 v_cmp_eq_f64_e64 s3, 0, v[7:8] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cndmask_b32_e32 v11, 0, v9, vcc_lo s_and_b32 s2, vcc_lo, s2 v_cndmask_b32_e64 v4, 0x3ff00000, v8, s2 v_cndmask_b32_e64 v13, 0, v8, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_bfi_b32 v4, 0x7fffffff, v10, v4 v_cndmask_b32_e32 v10, 0x7ff80000, v4, vcc_lo v_cmp_gt_f64_e32 vcc_lo, 0, v[7:8] v_cndmask_b32_e64 v12, 0x7ff00000, 0, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_bfi_b32 v12, 0x7fffffff, v12, v13 v_dual_cndmask_b32 v4, v4, v10 :: v_dual_cndmask_b32 v9, v9, v11 s_or_b32 vcc_lo, s3, s70 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v4, v4, v12, vcc_lo v_cndmask_b32_e64 v9, v9, 0, vcc_lo v_cmp_o_f64_e32 vcc_lo, v[7:8], v[7:8] v_cvt_f64_f32_e32 v[7:8], v2 v_sub_nc_u32_e32 v2, s68, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cvt_f64_i32_e32 v[11:12], v2 v_cndmask_b32_e32 v9, 0, v9, vcc_lo v_cndmask_b32_e32 v10, 0x7ff80000, v4, vcc_lo v_mul_f64 v[7:8], v[9:10], v[7:8] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_scale_f64 v[15:16], null, v[5:6], v[5:6], v[11:12] v_fma_f64 v[7:8], v[7:8], 0.5, 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[19:20], v[15:16] v_div_scale_f64 v[13:14], null, v[7:8], v[7:8], 1.0 v_div_scale_f64 v[25:26], vcc_lo, 1.0, v[7:8], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[23:24], -v[15:16], v[19:20], 1.0 v_rcp_f64_e32 v[17:18], v[13:14] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20] s_waitcnt_depctr 0xfff v_fma_f64 v[21:22], -v[13:14], v[17:18], 1.0 v_fma_f64 v[23:24], -v[15:16], v[19:20], 1.0 v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20] v_fma_f64 v[21:22], -v[13:14], v[17:18], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18] v_div_scale_f64 v[21:22], s2, v[11:12], v[5:6], v[11:12] v_mul_f64 v[23:24], v[25:26], v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[27:28], v[21:22], v[19:20] v_fma_f64 v[13:14], -v[13:14], v[23:24], v[25:26] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[15:16], -v[15:16], v[27:28], v[21:22] v_div_fmas_f64 v[13:14], v[13:14], v[17:18], v[23:24] s_mov_b32 vcc_lo, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_fmas_f64 v[15:16], v[15:16], v[19:20], v[27:28] v_div_fixup_f64 v[7:8], v[13:14], v[7:8], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fixup_f64 v[5:6], v[15:16], v[5:6], v[11:12] v_frexp_mant_f64_e64 v[11:12], |v[5:6]| s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, s[10:11], v[11:12] v_cndmask_b32_e64 v2, 0, 1, vcc_lo v_ldexp_f64 v[11:12], v[11:12], v2 v_frexp_exp_i32_f64_e32 v2, v[5:6] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[15:16], v[11:12], 1.0 v_add_f64 v[21:22], v[11:12], -1.0 v_subrev_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo v_cmp_eq_f64_e32 vcc_lo, 1.0, v[5:6] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_rcp_f64_e32 v[17:18], v[15:16] v_add_f64 v[23:24], v[15:16], -1.0 v_cndmask_b32_e64 v4, 2.0, 0x3ff00000, vcc_lo v_add_f64 v[11:12], v[11:12], -v[23:24] s_waitcnt_depctr 0xfff v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[17:18], v[19:20], v[17:18], v[17:18] v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[17:18], v[19:20], v[17:18], v[17:18] v_mul_f64 v[19:20], v[21:22], v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[25:26], v[15:16], v[19:20] v_fma_f64 v[15:16], v[19:20], v[15:16], -v[25:26] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], v[19:20], v[11:12], v[15:16] v_add_f64 v[15:16], v[25:26], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[23:24], v[21:22], -v[15:16] v_add_f64 v[25:26], v[15:16], -v[25:26] v_add_f64 v[21:22], v[21:22], -v[23:24] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[11:12], v[25:26], -v[11:12] v_add_f64 v[15:16], v[21:22], -v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[11:12], v[11:12], v[15:16] v_add_f64 v[11:12], v[23:24], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[11:12], v[17:18], v[11:12] v_add_f64 v[15:16], v[19:20], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[17:18], v[15:16], -v[19:20] v_mul_f64 v[19:20], v[15:16], v[15:16] v_add_f64 v[11:12], v[11:12], -v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[17:18], v[15:16], v[15:16], -v[19:20] v_add_f64 v[21:22], v[11:12], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[17:18], v[15:16], v[21:22], v[17:18] v_add_f64 v[21:22], v[19:20], v[17:18] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[23:24], v[21:22], s[16:17], s[14:15] v_add_f64 v[19:20], v[21:22], -v[19:20] v_mul_f64 v[29:30], v[15:16], v[21:22] v_fma_f64 v[23:24], v[21:22], v[23:24], s[18:19] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[17:18], v[17:18], -v[19:20] v_fma_f64 v[23:24], v[21:22], v[23:24], s[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], v[21:22], v[23:24], s[22:23] v_fma_f64 v[23:24], v[21:22], v[23:24], s[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], v[21:22], v[23:24], s[26:27] v_fma_f64 v[23:24], v[21:22], v[23:24], s[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], v[21:22], v[23:24], s[30:31] v_mul_f64 v[25:26], v[21:22], v[23:24] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[19:20], v[21:22], v[23:24], -v[25:26] v_fma_f64 v[19:20], v[17:18], v[23:24], v[19:20] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[23:24], v[25:26], v[19:20] v_add_f64 v[27:28], v[23:24], s[10:11] v_add_f64 v[25:26], v[23:24], -v[25:26] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[31:32], v[27:28], s[34:35] v_add_f64 v[19:20], v[19:20], -v[25:26] v_fma_f64 v[25:26], v[21:22], v[15:16], -v[29:30] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[23:24], v[23:24], -v[31:32] v_add_f64 v[19:20], v[19:20], s[36:37] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[21:22], v[21:22], v[11:12], v[25:26] v_ldexp_f64 v[11:12], v[11:12], 1 v_add_f64 v[19:20], v[19:20], v[23:24] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[17:18], v[17:18], v[15:16], v[21:22] v_ldexp_f64 v[15:16], v[15:16], 1 v_add_f64 v[21:22], v[27:28], v[19:20] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[23:24], v[29:30], v[17:18] v_add_f64 v[25:26], v[27:28], -v[21:22] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mul_f64 v[27:28], v[23:24], v[21:22] v_add_f64 v[29:30], v[23:24], -v[29:30] v_add_f64 v[19:20], v[19:20], v[25:26] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[25:26], v[23:24], v[21:22], -v[27:28] v_add_f64 v[17:18], v[17:18], -v[29:30] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[19:20], v[23:24], v[19:20], v[25:26] v_fma_f64 v[17:18], v[17:18], v[21:22], v[19:20] v_cvt_f64_i32_e32 v[21:22], v2 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[19:20], v[27:28], v[17:18] v_add_f64 v[23:24], v[15:16], v[19:20] v_add_f64 v[25:26], v[19:20], -v[27:28] v_mul_f64 v[27:28], v[21:22], s[38:39] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[15:16], v[23:24], -v[15:16] v_add_f64 v[17:18], v[17:18], -v[25:26] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[25:26], v[21:22], s[38:39], -v[27:28] v_add_f64 v[15:16], v[19:20], -v[15:16] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[11:12], v[11:12], v[17:18] v_fma_f64 v[17:18], v[21:22], s[44:45], v[25:26] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[11:12], v[11:12], v[15:16] v_add_f64 v[15:16], v[27:28], v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[19:20], v[23:24], v[11:12] v_add_f64 v[27:28], v[15:16], -v[27:28] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[21:22], v[15:16], v[19:20] v_add_f64 v[23:24], v[19:20], -v[23:24] v_add_f64 v[17:18], v[17:18], -v[27:28] v_cvt_f32_f64_e32 v27, v[7:8] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[25:26], v[21:22], -v[15:16] v_add_f64 v[11:12], v[11:12], -v[23:24] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[29:30], v[21:22], -v[25:26] v_add_f64 v[19:20], v[19:20], -v[25:26] v_add_f64 v[23:24], v[17:18], v[11:12] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[15:16], v[15:16], -v[29:30] v_add_f64 v[15:16], v[19:20], v[15:16] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[19:20], v[23:24], -v[17:18] v_add_f64 v[15:16], v[23:24], v[15:16] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[23:24], v[23:24], -v[19:20] v_add_f64 v[11:12], v[11:12], -v[19:20] v_add_f64 v[25:26], v[21:22], v[15:16] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[17:18], v[17:18], -v[23:24] v_add_f64 v[19:20], v[25:26], -v[21:22] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[11:12], v[11:12], v[17:18] v_add_f64 v[15:16], v[15:16], -v[19:20] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[11:12], v[11:12], v[15:16] v_add_f64 v[15:16], v[25:26], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[13:14], v[15:16], -v[25:26] v_mul_f64 v[17:18], v[3:4], v[15:16] v_add_f64 v[7:8], v[11:12], -v[13:14] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], v[3:4], v[15:16], -v[17:18] v_lshlrev_b64 v[13:14], 2, v[1:2] v_add_co_u32 v15, vcc_lo, s4, v13 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v16, vcc_lo, s5, v14, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[17:18], 0x204 v_cmp_class_f64_e64 s4, v[5:6], 0x204 global_store_b32 v[15:16], v27, off global_load_b32 v25, v0, s[12:13] v_fma_f64 v[7:8], v[3:4], v[7:8], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[11:12], v[17:18], v[7:8] v_dual_cndmask_b32 v16, v12, v18 :: v_dual_cndmask_b32 v15, v11, v17 v_add_f64 v[11:12], v[11:12], -v[17:18] v_mul_f64 v[17:18], v[3:4], 0.5 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f64 v[19:20], v[15:16], s[40:41] v_add_f64 v[7:8], v[7:8], -v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f64_e32 v[19:20], v[19:20] v_fma_f64 v[21:22], v[19:20], s[42:43], v[15:16] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[21:22], v[19:20], s[46:47], v[21:22] v_cvt_i32_f64_e32 v19, v[19:20] v_fma_f64 v[23:24], v[21:22], s[50:51], s[48:49] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], v[21:22], v[23:24], s[52:53] s_waitcnt vmcnt(0) v_mul_f32_e32 v25, s33, v25 v_cvt_f64_f32_e32 v[25:26], v25 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[23:24], v[21:22], v[23:24], s[54:55] v_mul_f64 v[9:10], v[9:10], v[25:26] v_cvt_f64_f32_e32 v[25:26], v27 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[23:24], v[21:22], v[23:24], s[56:57] v_fma_f64 v[9:10], v[9:10], -0.5, 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[23:24], v[21:22], v[23:24], s[58:59] v_mul_f64 v[9:10], v[9:10], v[25:26] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[23:24], v[21:22], v[23:24], s[60:61] v_cvt_f32_f64_e32 v25, v[9:10] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[23:24], v[21:22], v[23:24], s[62:63] v_fma_f64 v[9:10], v[21:22], v[23:24], s[64:65] v_add_co_u32 v23, vcc_lo, s6, v13 v_add_co_ci_u32_e32 v24, vcc_lo, s7, v14, vcc_lo v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[15:16]| global_store_b32 v[23:24], v25, off global_load_b32 v23, v0, s[12:13] v_fma_f64 v[9:10], v[21:22], v[9:10], s[66:67] v_cndmask_b32_e32 v8, 0, v8, vcc_lo v_cmp_nlt_f64_e64 s2, 0x40900000, v[15:16] v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[15:16] v_trunc_f64_e32 v[15:16], v[17:18] v_cndmask_b32_e32 v7, 0, v7, vcc_lo v_fma_f64 v[9:10], v[21:22], v[9:10], 1.0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) s_and_b32 vcc_lo, s3, s2 v_fma_f64 v[9:10], v[21:22], v[9:10], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[9:10], v[9:10], v19 v_cndmask_b32_e64 v12, 0x7ff00000, v10, s2 v_trunc_f64_e32 v[10:11], v[3:4] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v19, 0, v9, vcc_lo v_cmp_neq_f64_e64 s2, v[15:16], v[17:18] v_cndmask_b32_e64 v20, 0, v12, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_cmp_class_f64_e64 s3, v[19:20], 0x204 v_cmp_eq_f64_e32 vcc_lo, v[10:11], v[3:4] v_fma_f64 v[3:4], v[19:20], v[7:8], v[19:20] s_and_b32 s2, vcc_lo, s2 v_cndmask_b32_e64 v4, v4, v20, s3 v_cndmask_b32_e64 v7, 0x3ff00000, v6, s2 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v3, v3, v19, s3 v_cmp_eq_f64_e64 s3, 0, v[5:6] v_cndmask_b32_e64 v10, 0, v6, s2 v_bfi_b32 v4, 0x7fffffff, v4, v7 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v8, 0, v3, vcc_lo v_cndmask_b32_e32 v7, 0x7ff80000, v4, vcc_lo v_cmp_gt_f64_e32 vcc_lo, 0, v[5:6] v_cndmask_b32_e64 v9, 0x7ff00000, 0, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_bfi_b32 v9, 0x7fffffff, v9, v10 v_dual_cndmask_b32 v4, v4, v7 :: v_dual_cndmask_b32 v3, v3, v8 s_or_b32 vcc_lo, s3, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v8, v4, v9, vcc_lo v_cndmask_b32_e64 v9, v3, 0, vcc_lo v_cmp_o_f64_e32 vcc_lo, v[5:6], v[5:6] s_waitcnt vmcnt(0) v_mul_f32_e32 v7, s33, v23 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cvt_f64_f32_e32 v[3:4], v7 v_cndmask_b32_e32 v5, 0, v9, vcc_lo v_cndmask_b32_e32 v6, 0x7ff80000, v8, vcc_lo v_mul_f64 v[3:4], v[5:6], v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[3:4], v[3:4], 0.5, 1.0 v_div_scale_f64 v[7:8], null, v[3:4], v[3:4], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[9:10], v[7:8] s_waitcnt_depctr 0xfff v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0 v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10] v_div_scale_f64 v[11:12], vcc_lo, 1.0, v[3:4], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[15:16], v[11:12], v[9:10] v_fma_f64 v[7:8], -v[7:8], v[15:16], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[15:16] v_div_fixup_f64 v[3:4], v[7:8], v[3:4], 1.0 s_delay_alu instid0(VALU_DEP_1) v_cvt_f32_f64_e32 v7, v[3:4] v_add_co_u32 v3, vcc_lo, s8, v13 v_add_co_ci_u32_e32 v4, vcc_lo, s9, v14, vcc_lo global_store_b32 v[3:4], v7, off global_load_b32 v0, v0, s[12:13] s_waitcnt vmcnt(0) v_mul_f32_e32 v0, s33, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_f64_f32_e32 v[3:4], v0 v_mul_f64 v[3:4], v[5:6], v[3:4] v_cvt_f64_f32_e32 v[5:6], v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[3:4], v[3:4], -0.5, 1.0 v_mul_f64 v[3:4], v[3:4], v[5:6] s_delay_alu instid0(VALU_DEP_1) v_cvt_f32_f64_e32 v0, v[3:4] .LBB4_9: ; %.sink.split s_or_b32 exec_lo, exec_lo, s69 s_load_b64 s[0:1], s[0:1], 0x20 v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, s0, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo global_store_b32 v[1:2], v0, off .LBB4_10: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13initial_coffefiPfS_S_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 304 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 33 .amdhsa_next_free_sgpr 74 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end4: .size _Z13initial_coffefiPfS_S_S_i, .Lfunc_end4-_Z13initial_coffefiPfS_S_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 9172 ; NumSgprs: 76 ; NumVgprs: 33 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 9 ; VGPRBlocks: 4 ; NumSGPRsForWavesPerEU: 76 ; NumVGPRsForWavesPerEU: 33 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z11shot_recordiiiiiiiPfS_ ; -- Begin function _Z11shot_recordiiiiiiiPfS_ .globl _Z11shot_recordiiiiiiiPfS_ .p2align 8 .type _Z11shot_recordiiiiiiiPfS_,@function _Z11shot_recordiiiiiiiPfS_: ; @_Z11shot_recordiiiiiiiPfS_ ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x3c s_load_b32 s3, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB5_2 ; %bb.1: s_clause 0x3 s_load_b64 s[4:5], s[0:1], 0x10 s_load_b32 s6, s[0:1], 0x4 s_load_b32 s7, s[0:1], 0x18 s_load_b128 s[0:3], s[0:1], 0x20 s_waitcnt lgkmcnt(0) v_add_nc_u32_e32 v0, s4, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v0, s6, s[4:5] v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[2:3] v_add_co_u32 v2, vcc_lo, s0, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo s_mov_b32 s0, s5 global_load_b32 v4, v[2:3], off v_mad_u64_u32 v[2:3], null, v1, s7, s[0:1] v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[2:3] v_add_co_u32 v0, vcc_lo, s2, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo s_waitcnt vmcnt(0) global_store_b32 v[0:1], v4, off .LBB5_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11shot_recordiiiiiiiPfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 304 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end5: .size _Z11shot_recordiiiiiiiPfS_, .Lfunc_end5-_Z11shot_recordiiiiiiiPfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 224 ; NumSgprs: 18 ; NumVgprs: 5 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 5 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z15mute_directwaveiiffffiiiiPfS_S_S_i ; -- Begin function _Z15mute_directwaveiiffffiiiiPfS_S_S_i .globl _Z15mute_directwaveiiffffiiiiPfS_S_S_i .p2align 8 .type _Z15mute_directwaveiiffffiiiiPfS_S_S_i,@function _Z15mute_directwaveiiffffiiiiPfS_S_S_i: ; @_Z15mute_directwaveiiffffiiiiPfS_S_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x5c s_load_b64 s[8:9], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mul_i32 s2, s9, s8 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s2, v1 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB6_9 ; %bb.1: s_ashr_i32 s12, s9, 31 v_ashrrev_i32_e32 v4, 31, v1 s_add_i32 s2, s9, s12 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) s_xor_b32 s13, s2, s12 s_load_b64 s[2:3], s[0:1], 0x38 v_cvt_f32_u32_e32 v0, s13 s_sub_i32 s4, 0, s13 v_add_nc_u32_e32 v3, v1, v4 v_rcp_iflag_f32_e32 v0, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_xor_b32_e32 v5, v3, v4 s_waitcnt_depctr 0xfff v_mul_f32_e32 v0, 0x4f7ffffe, v0 v_cvt_u32_f32_e32 v0, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, s4, v0 s_load_b128 s[4:7], s[0:1], 0x28 s_waitcnt lgkmcnt(0) s_load_b32 s8, s[2:3], 0x4 v_mul_hi_u32 v2, v0, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v0, v0, v2 v_mad_u64_u32 v[2:3], null, v5, v0, 0 s_waitcnt lgkmcnt(0) v_cmp_ngt_f32_e64 s2, 0x48000000, |s8| s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s2 s_cbranch_vccz .LBB6_3 ; %bb.2: s_and_b32 s2, s8, 0x7fffffff s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 s3, s2, 0x7fffff s_lshr_b32 s2, s2, 23 s_bitset1_b32 s3, 23 s_addk_i32 s2, 0xff88 s_mul_hi_u32 s10, s3, 0xfe5163ab s_mul_i32 s11, s3, 0x3c439041 s_mul_hi_u32 s14, s3, 0x3c439041 s_add_u32 s10, s10, s11 s_addc_u32 s11, 0, s14 s_mul_i32 s14, s3, 0xdb629599 s_mul_hi_u32 s15, s3, 0xdb629599 s_add_u32 s11, s11, s14 s_addc_u32 s14, 0, s15 s_mul_i32 s15, s3, 0xf534ddc0 s_mul_hi_u32 s16, s3, 0xf534ddc0 s_add_u32 s14, s14, s15 s_addc_u32 s15, 0, s16 s_mul_i32 s16, s3, 0xfc2757d1 s_mul_hi_u32 s17, s3, 0xfc2757d1 s_add_u32 s15, s15, s16 s_addc_u32 s16, 0, s17 s_mul_i32 s17, s3, 0x4e441529 s_mul_hi_u32 s18, s3, 0x4e441529 s_add_u32 s16, s16, s17 s_addc_u32 s17, 0, s18 s_cmp_gt_u32 s2, 63 s_mul_i32 s18, s3, 0xfe5163ab s_mul_hi_u32 s19, s3, 0xa2f9836e s_mul_i32 s3, s3, 0xa2f9836e s_cselect_b32 s20, s11, s15 s_cselect_b32 s10, s10, s14 s_cselect_b32 s11, s18, s11 s_add_u32 s3, s17, s3 s_addc_u32 s17, 0, s19 s_cmp_gt_u32 s2, 63 s_cselect_b32 s18, 0xffffffc0, 0 s_cselect_b32 s14, s14, s16 s_cselect_b32 s3, s15, s3 s_cselect_b32 s15, s16, s17 s_add_i32 s18, s18, s2 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_gt_u32 s18, 31 s_cselect_b32 s2, 0xffffffe0, 0 s_cselect_b32 s16, s14, s3 s_cselect_b32 s3, s3, s15 s_cselect_b32 s14, s20, s14 s_cselect_b32 s15, s10, s20 s_cselect_b32 s10, s11, s10 s_add_i32 s2, s2, s18 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_gt_u32 s2, 31 s_cselect_b32 s11, 0xffffffe0, 0 s_cselect_b32 s3, s16, s3 s_cselect_b32 s16, s14, s16 s_cselect_b32 s14, s15, s14 s_cselect_b32 s10, s10, s15 s_add_i32 s11, s11, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_sub_i32 s2, 32, s11 s_cmp_eq_u32 s11, 0 v_mov_b32_e32 v0, s2 s_cselect_b32 s11, -1, 0 v_alignbit_b32 v2, s3, s16, v0 v_alignbit_b32 v6, s16, s14, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_readfirstlane_b32 s2, v2 v_cndmask_b32_e64 v2, v6, s16, s11 s_delay_alu instid0(VALU_DEP_2) s_cselect_b32 s2, s3, s2 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_alignbit_b32 v6, s2, v2, 30 s_bfe_u32 s3, s2, 0x1001d s_delay_alu instid0(SALU_CYCLE_1) s_sub_i32 s15, 0, s3 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_xor_b32_e32 v6, s15, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_clz_i32_u32_e32 v7, v6 v_min_u32_e32 v7, 32, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_lshlrev_b32_e32 v9, 23, v7 v_alignbit_b32 v0, s14, s10, v0 v_sub_nc_u32_e32 v8, 31, v7 v_cndmask_b32_e64 v0, v0, s14, s11 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_alignbit_b32 v2, v2, v0, 30 v_alignbit_b32 v0, v0, s10, 30 s_lshr_b32 s10, s2, 29 s_lshl_b32 s10, s10, 31 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v2, s15, v2 v_xor_b32_e32 v0, s15, v0 s_or_b32 s11, s10, 0.5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_sub_nc_u32_e32 v9, s11, v9 v_alignbit_b32 v6, v6, v2, v8 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_alignbit_b32 v0, v2, v0, v8 v_alignbit_b32 v2, v6, v0, 9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_clz_i32_u32_e32 v8, v2 v_min_u32_e32 v8, 32, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v10, 31, v8 v_alignbit_b32 v0, v2, v0, v10 v_lshrrev_b32_e32 v2, 9, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v0, 9, v0 v_or_b32_e32 v2, v2, v9 v_add_nc_u32_e32 v7, v8, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b32_e32 v6, 23, v7 v_sub_nc_u32_e32 v0, v0, v6 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f32_e32 v6, 0x3fc90fda, v2 v_add_nc_u32_e32 v0, 0x33000000, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v7, v2, 0x3fc90fda, -v6 v_or_b32_e32 v0, s10, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_fmamk_f32 v2, v2, 0x33a22168, v7 s_lshr_b32 s10, s2, 30 s_mov_b32 s2, 0 s_add_i32 s3, s3, s10 v_fmac_f32_e32 v2, 0x3fc90fda, v0 s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v0, v6, v2 s_branch .LBB6_4 .LBB6_3: s_mov_b32 s2, -1 ; implicit-def: $sgpr3 ; implicit-def: $vgpr0 .LBB6_4: ; %Flow73 s_load_b32 s10, s[4:5], 0x4 s_load_b32 s11, s[6:7], 0x4 v_mov_b32_e32 v2, s3 s_and_not1_b32 vcc_lo, exec_lo, s2 s_cbranch_vccnz .LBB6_6 ; %bb.5: v_mul_f32_e64 v0, 0x3f22f983, |s8| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f32_e32 v2, v0 v_fma_f32 v0, v2, 0xbfc90fda, |s8| s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmamk_f32 v0, v2, 0xb3a22168, v0 v_fmamk_f32 v0, v2, 0xa7c234c4, v0 v_cvt_i32_f32_e32 v2, v2 .LBB6_6: ; %_ZL3cosf.exit v_mul_lo_u32 v6, v3, s13 s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x20 s_load_b128 s[4:7], s[0:1], 0x10 v_xor_b32_e32 v4, s12, v4 s_load_b32 s12, s[0:1], 0x48 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v5, v5, v6 v_add_nc_u32_e32 v6, 1, v3 v_subrev_nc_u32_e32 v7, s13, v5 v_cmp_le_u32_e32 vcc_lo, s13, v5 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v3, v3, v6, vcc_lo v_cndmask_b32_e32 v5, v5, v7, vcc_lo s_waitcnt lgkmcnt(0) s_sub_i32 s3, 1, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) s_mul_i32 s3, s3, s7 v_add_nc_u32_e32 v6, 1, v3 v_cmp_le_u32_e32 vcc_lo, s13, v5 s_sub_i32 s3, s3, s6 v_cndmask_b32_e32 v3, v3, v6, vcc_lo v_cvt_f32_i32_e32 v6, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v3, v3, v4 v_sub_nc_u32_e32 v3, v3, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v4, s3, v3 s_mov_b32 s3, 0x3e76c4e1 v_mul_lo_u32 v3, v3, s9 v_sub_nc_u32_e32 v5, 0, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_max_i32_e32 v4, v4, v5 v_mul_f32_e32 v5, s5, v6 v_cvt_f32_i32_e32 v4, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_frexp_mant_f32_e64 v6, |v5| v_mul_f32_e32 v4, s4, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v6 v_frexp_mant_f32_e64 v8, |v4| v_cndmask_b32_e64 v7, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v8 v_ldexp_f32 v6, v6, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v7, 0, 1, s2 v_ldexp_f32 v7, v8, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_add_f32 v9, 1.0, v6 :: v_dual_add_f32 v14, -1.0, v7 v_rcp_f32_e32 v8, v9 v_dual_add_f32 v10, 1.0, v7 :: v_dual_add_f32 v11, -1.0, v6 v_add_f32_e32 v15, -1.0, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_rcp_f32_e32 v12, v10 v_dual_sub_f32 v6, v6, v15 :: v_dual_add_f32 v15, -1.0, v10 s_waitcnt_depctr 0xfff v_mul_f32_e32 v13, v11, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mul_f32 v16, v9, v13 :: v_dual_mul_f32 v17, v14, v12 v_fma_f32 v9, v13, v9, -v16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_fmac_f32 v9, v13, v6 :: v_dual_sub_f32 v6, v7, v15 v_mul_f32_e32 v18, v10, v17 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v7, v17, v10, -v18 v_dual_add_f32 v10, v16, v9 :: v_dual_fmac_f32 v7, v17, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_sub_f32_e32 v6, v11, v10 v_sub_f32_e32 v16, v10, v16 v_add_f32_e32 v15, v18, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v19, v14, v15 v_dual_sub_f32 v11, v11, v6 :: v_dual_sub_f32 v14, v14, v19 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v9, v16, v9 :: v_dual_sub_f32 v10, v11, v10 v_add_f32_e32 v9, v9, v10 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v11, v15, v18 :: v_dual_sub_f32 v10, v14, v15 v_dual_add_f32 v6, v6, v9 :: v_dual_sub_f32 v7, v11, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v6, v8, v6 v_add_f32_e32 v8, v13, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v9, v8, v13 v_dual_add_f32 v7, v7, v10 :: v_dual_sub_f32 v6, v6, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v7, v19, v7 v_mul_f32_e32 v7, v12, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_add_f32 v13, v6, v6 :: v_dual_add_f32 v10, v17, v7 v_dual_mul_f32 v14, v10, v10 :: v_dual_mul_f32 v11, v8, v8 v_sub_f32_e32 v9, v10, v17 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v12, v8, v8, -v11 v_sub_f32_e32 v7, v7, v9 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v9, v10, v10, -v14 v_dual_fmac_f32 v12, v8, v13 :: v_dual_add_f32 v13, v7, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v9, v10, v13 v_dual_add_f32 v16, v14, v9 :: v_dual_add_f32 v15, v11, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_dual_sub_f32 v14, v16, v14 :: v_dual_fmaak_f32 v13, s3, v15, 0x3e91f4c4 v_sub_f32_e32 v11, v15, v11 v_mul_f32_e32 v25, v10, v16 v_sub_f32_e32 v9, v9, v14 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_fmaak_f32 v13, v15, v13, 0x3ecccdef v_fmaak_f32 v17, s3, v16, 0x3e91f4c4 s_mov_b32 s3, 0x37d75334 v_mul_f32_e32 v18, v15, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmaak_f32 v17, v16, v17, 0x3ecccdef v_mul_f32_e32 v19, v16, v17 v_sub_f32_e32 v11, v12, v11 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v12, v15, v13, -v18 v_fmac_f32_e32 v12, v11, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v14, v18, v12 v_sub_f32_e32 v18, v14, v18 v_add_f32_e32 v21, 0x3f2aaaaa, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_f32_e32 v12, v12, v18 v_add_f32_e32 v18, 0xbf2aaaaa, v21 v_mul_f32_e32 v20, v8, v15 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f32_e32 v12, 0x31739010, v12 v_fma_f32 v13, v16, v17, -v19 v_sub_f32_e32 v14, v14, v18 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v23, v15, v8, -v20 v_dual_fmac_f32 v13, v9, v17 :: v_dual_add_f32 v12, v12, v14 v_frexp_exp_i32_f32_e32 v17, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f32_e32 v22, v19, v13 v_subrev_co_ci_u32_e32 v17, vcc_lo, 0, v17, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_dual_sub_f32 v19, v22, v19 :: v_dual_add_f32 v24, 0x3f2aaaaa, v22 v_fmac_f32_e32 v23, v15, v6 v_ldexp_f32 v6, v6, 1 v_dual_add_f32 v18, 0xbf2aaaaa, v24 :: v_dual_sub_f32 v13, v13, v19 v_fma_f32 v19, v16, v10, -v25 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_sub_f32 v14, v22, v18 :: v_dual_fmac_f32 v19, v16, v7 v_ldexp_f32 v7, v7, 1 v_fmac_f32_e32 v19, v9, v10 v_ldexp_f32 v10, v10, 1 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_dual_add_f32 v18, v25, v19 :: v_dual_fmac_f32 v23, v11, v8 v_add_f32_e32 v15, v21, v12 v_cvt_f32_i32_e32 v11, v17 v_ldexp_f32 v8, v8, 1 v_add_f32_e32 v9, v20, v23 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_f32_e32 v16, v21, v15 v_sub_f32_e32 v20, v9, v20 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_add_f32 v12, v12, v16 :: v_dual_add_f32 v13, 0x31739010, v13 v_dual_mul_f32 v21, v9, v15 :: v_dual_sub_f32 v20, v23, v20 v_sub_f32_e32 v23, v18, v25 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f32_e32 v13, v13, v14 v_frexp_exp_i32_f32_e32 v14, v4 v_add_f32_e32 v17, v24, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_sub_f32_e32 v16, v24, v17 v_fma_f32 v24, v9, v15, -v21 v_fmac_f32_e32 v24, v9, v12 v_mul_f32_e32 v22, v18, v17 v_sub_f32_e32 v12, v19, v23 v_subrev_co_ci_u32_e64 v9, vcc_lo, 0, v14, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_dual_fmac_f32 v24, v20, v15 :: v_dual_add_f32 v13, v13, v16 v_fma_f32 v16, v18, v17, -v22 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cvt_f32_i32_e32 v9, v9 v_cmp_neq_f32_e64 s2, 0x7f800000, |v5| v_fmac_f32_e32 v16, v18, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fmac_f32_e32 v16, v12, v17 v_add_f32_e32 v12, v21, v24 v_add_f32_e32 v15, v22, v16 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_f32_e32 v18, v8, v12 v_sub_f32_e32 v19, v12, v21 v_mul_f32_e32 v13, 0x3f317218, v11 v_dual_sub_f32 v21, v15, v22 :: v_dual_sub_f32 v8, v18, v8 v_mul_f32_e32 v17, 0x3f317218, v9 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f32 v14, v11, 0x3f317218, -v13 v_sub_f32_e32 v16, v16, v21 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_sub_f32_e32 v8, v12, v8 v_add_f32_e32 v20, v10, v15 v_fma_f32 v12, v9, 0x3f317218, -v17 v_dual_fmac_f32 v14, 0xb102e308, v11 :: v_dual_add_f32 v7, v7, v16 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v10, v20, v10 v_dual_sub_f32 v10, v15, v10 :: v_dual_sub_f32 v19, v24, v19 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_fmac_f32 v12, 0xb102e308, v9 :: v_dual_add_f32 v7, v7, v10 v_add_f32_e32 v6, v6, v19 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_add_f32 v10, v17, v12 :: v_dual_add_f32 v11, v20, v7 v_add_f32_e32 v6, v6, v8 v_add_f32_e32 v8, v13, v14 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f32_e32 v16, v10, v11 v_add_f32_e32 v9, v18, v6 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_sub_f32_e32 v13, v8, v13 v_dual_sub_f32 v17, v10, v17 :: v_dual_sub_f32 v20, v11, v20 v_add_f32_e32 v15, v8, v9 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_sub_f32 v13, v14, v13 :: v_dual_sub_f32 v14, v9, v18 v_sub_f32_e32 v18, v16, v10 v_dual_sub_f32 v12, v12, v17 :: v_dual_sub_f32 v19, v15, v8 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_sub_f32 v7, v7, v20 :: v_dual_sub_f32 v6, v6, v14 v_dual_sub_f32 v14, v16, v18 :: v_dual_sub_f32 v9, v9, v19 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v17, v15, v19 :: v_dual_sub_f32 v10, v10, v14 v_dual_sub_f32 v8, v8, v17 :: v_dual_sub_f32 v11, v11, v18 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_add_f32 v8, v9, v8 :: v_dual_add_f32 v9, v12, v7 v_sub_f32_e32 v17, v9, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_add_f32 v14, v13, v6 :: v_dual_sub_f32 v7, v7, v17 v_dual_add_f32 v10, v11, v10 :: v_dual_sub_f32 v11, v14, v13 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f32_e32 v8, v14, v8 v_add_f32_e32 v10, v9, v10 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v14, v14, v11 :: v_dual_sub_f32 v9, v9, v17 v_dual_sub_f32 v6, v6, v11 :: v_dual_sub_f32 v13, v13, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_dual_sub_f32 v9, v12, v9 :: v_dual_add_f32 v18, v15, v8 v_add_f32_e32 v11, v16, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_add_f32 v7, v7, v9 :: v_dual_sub_f32 v14, v18, v15 v_sub_f32_e32 v12, v11, v16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v8, v8, v14 :: v_dual_sub_f32 v9, v10, v12 v_add_f32_e32 v7, v7, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_add_f32 v6, v6, v13 :: v_dual_add_f32 v9, v11, v7 v_dual_sub_f32 v11, v9, v11 :: v_dual_add_f32 v6, v6, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_mul_f32 v14, 0, v9 :: v_dual_sub_f32 v7, v7, v11 v_add_f32_e32 v8, v18, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmac_f32_e32 v14, 2.0, v7 v_dual_sub_f32 v10, v8, v18 :: v_dual_mul_f32 v13, 0, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v6, v6, v10 v_dual_add_f32 v12, v8, v8 :: v_dual_fmac_f32 v13, 2.0, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f32 v8, v8, 2.0, -v12 v_cmp_class_f32_e64 vcc_lo, v12, 0x204 v_add_f32_e32 v7, v8, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v8, v12, v7 v_dual_add_f32 v10, v9, v9 :: v_dual_cndmask_b32 v11, v8, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f32 v6, v9, 2.0, -v10 v_cmp_class_f32_e64 vcc_lo, v10, 0x204 v_add_f32_e32 v6, v6, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v9, v10, v6 v_cndmask_b32_e32 v13, v9, v10, vcc_lo v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v11 v_sub_f32_e32 v9, v9, v10 v_cndmask_b32_e64 v14, 0, 0x37000000, vcc_lo s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v13 v_cndmask_b32_e64 v15, 0, 0x37000000, vcc_lo v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v11| v_dual_sub_f32 v17, v13, v15 :: v_dual_sub_f32 v6, v6, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mul_f32 v19, 0x3fb8aa3b, v17 :: v_dual_sub_f32 v8, v8, v12 v_fma_f32 v22, v17, 0x3fb8aa3b, -v19 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_sub_f32_e32 v7, v7, v8 v_sub_f32_e32 v16, v11, v14 v_rndne_f32_e32 v23, v19 v_dual_fmac_f32 v22, 0x32a5705f, v17 :: v_dual_cndmask_b32 v7, 0, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_dual_mul_f32 v18, 0x3fb8aa3b, v16 :: v_dual_sub_f32 v19, v19, v23 v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v13| v_cvt_i32_f32_e32 v11, v23 v_add_f32_e32 v7, v14, v7 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_fma_f32 v20, v16, 0x3fb8aa3b, -v18 v_rndne_f32_e32 v21, v18 v_cndmask_b32_e32 v6, 0, v6, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v16 v_fmac_f32_e32 v20, 0x32a5705f, v16 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_sub_f32_e32 v18, v18, v21 v_cvt_i32_f32_e32 v10, v21 v_add_f32_e32 v6, v15, v6 v_add_f32_e32 v12, v18, v20 v_add_f32_e32 v18, v19, v22 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_exp_f32_e32 v8, v12 v_exp_f32_e32 v12, v18 s_waitcnt_depctr 0xfff v_ldexp_f32 v8, v8, v10 v_ldexp_f32 v9, v12, v11 v_fma_f32 v10, s11, 2.0, 1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v8, 0, v8, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v17 v_cndmask_b32_e32 v9, 0, v9, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v16 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v8, 0x7f800000, v8, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v17 v_fma_f32 v7, v8, v7, v8 v_cndmask_b32_e32 v9, 0x7f800000, v9, vcc_lo v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f32 v6, v9, v6, v9 v_cndmask_b32_e32 v7, v7, v8, vcc_lo v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v9 v_mul_f32_e32 v8, 0x4f800000, v10 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v7, 0x7f800000, |v7|, s2 v_cndmask_b32_e32 v6, v6, v9, vcc_lo v_cmp_neq_f32_e64 s2, 0x7f800000, |v4| v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v10 v_cndmask_b32_e64 v6, 0x7f800000, |v6|, s2 v_cmp_neq_f32_e64 s2, 0, v5 v_cndmask_b32_e32 v8, v10, v8, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v5, 0, v7, s2 v_cmp_neq_f32_e64 s2, 0, v4 v_and_b32_e32 v7, 1, v2 v_lshlrev_b32_e32 v2, 30, v2 v_cndmask_b32_e64 v4, 0, v6, s2 v_sqrt_f32_e32 v6, v8 s_mov_b32 s2, 0xb94c1982 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, 0x80000000, v2 v_add_f32_e32 v4, v5, v4 v_mul_f32_e32 v5, v0, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) v_mul_f32_e32 v9, 0x4f800000, v4 s_waitcnt_depctr 0xfff v_dual_fmaak_f32 v10, s2, v5, 0x3c0881c4 :: v_dual_add_nc_u32 v11, -1, v6 v_cmp_gt_f32_e64 s2, 0xf800000, v4 v_fmaak_f32 v12, s3, v5, 0xbab64f3b v_fmaak_f32 v10, v5, v10, 0xbe2aaa9d s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v4, v4, v9, s2 v_add_nc_u32_e32 v9, 1, v6 v_fma_f32 v13, -v11, v6, v8 v_mul_f32_e32 v10, v5, v10 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_sqrt_f32_e32 v14, v4 v_fma_f32 v15, -v9, v6, v8 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_ge_f32_e64 s3, 0, v13 v_fmac_f32_e32 v0, v0, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v6, v6, v11, s3 v_cmp_lt_f32_e64 s3, 0, v15 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1) v_cndmask_b32_e64 v6, v6, v9, s3 v_add_nc_u32_e32 v9, -1, v14 v_cmp_eq_u32_e64 s3, 0, v7 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mul_f32_e32 v10, 0x37800000, v6 v_fmaak_f32 v12, v5, v12, 0x3d2aabf7 v_fmaak_f32 v11, v5, v12, 0xbf000004 v_fma_f32 v12, -v9, v14, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f32 v5, v5, v11, 1.0 v_add_nc_u32_e32 v11, 1, v14 v_cndmask_b32_e64 v0, -v0, v5, s3 v_cndmask_b32_e32 v5, v6, v10, vcc_lo v_cmp_ge_f32_e32 vcc_lo, 0, v12 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f32 v6, -v11, v14, v4 v_xor_b32_e32 v0, v2, v0 v_cndmask_b32_e32 v7, v14, v9, vcc_lo v_cmp_class_f32_e64 vcc_lo, v8, 0x260 v_cndmask_b32_e32 v2, v5, v8, vcc_lo v_cmp_lt_f32_e32 vcc_lo, 0, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_add_f32 v2, -1.0, v2 :: v_dual_cndmask_b32 v5, v7, v11 v_cmp_class_f32_e64 vcc_lo, s8, 0x1f8 v_mul_f32_e32 v6, 0x37800000, v5 v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo v_cmp_class_f32_e64 vcc_lo, v4, 0x260 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f32 v0, v2, v0, 1.0 v_cndmask_b32_e64 v2, v5, v6, s2 s_load_b32 s2, s[0:1], 0x8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f32_e32 v0, s10, v0 v_cndmask_b32_e32 v2, v2, v4, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f32 v4, null, v0, v0, v2 v_div_scale_f32 v7, vcc_lo, v2, v0, v2 v_rcp_f32_e32 v5, v4 s_waitcnt_depctr 0xfff v_fma_f32 v6, -v4, v5, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v5, v6, v5 v_mul_f32_e32 v6, v7, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v8, -v4, v6, v7 v_fmac_f32_e32 v6, v8, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v4, -v4, v6, v7 v_div_fmas_f32 v4, v4, v5, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f32 v0, v4, v0, v2 s_waitcnt lgkmcnt(0) v_div_scale_f32 v2, null, s2, s2, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f32_e32 v4, v2 s_waitcnt_depctr 0xfff v_fma_f32 v5, -v2, v4, 1.0 v_fmac_f32_e32 v4, v5, v4 v_div_scale_f32 v5, vcc_lo, v0, s2, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v6, v5, v4 v_fma_f32 v7, -v2, v6, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v6, v7, v4 v_fma_f32 v2, -v2, v6, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f32 v2, v2, v4, v6 v_div_fixup_f32 v0, v2, s2, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cvt_i32_f32_e32 v2, v0 v_sub_nc_u32_e32 v0, v1, v3 v_subrev_nc_u32_e32 v3, s12, v2 s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_i32_e32 vcc_lo, v0, v3 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_9 ; %bb.7: s_load_b32 s3, s[0:1], 0xc s_waitcnt lgkmcnt(0) v_mul_f32_e64 v3, s2, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_f64_f32_e32 v[3:4], v3 v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], 2.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[7:8], v[5:6] s_waitcnt_depctr 0xfff v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0 v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0 v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8] v_div_scale_f64 v[9:10], vcc_lo, 2.0, v[3:4], 2.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[11:12], v[9:10], v[7:8] v_fma_f64 v[5:6], -v[5:6], v[11:12], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[11:12] v_div_fixup_f64 v[3:4], v[5:6], v[3:4], 2.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_i32_f64_e32 v3, v[3:4] v_add3_u32 v2, v3, s12, v2 s_delay_alu instid0(VALU_DEP_1) v_cmp_lt_i32_e32 vcc_lo, v0, v2 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB6_9 ; %bb.8: s_load_b64 s[0:1], s[0:1], 0x40 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_lshlrev_b64 v[0:1], 2, v[1:2] v_mov_b32_e32 v2, 0 s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB6_9: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15mute_directwaveiiffffiiiiPfS_S_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 336 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 26 .amdhsa_next_free_sgpr 21 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end6: .size _Z15mute_directwaveiiffffiiiiPfS_S_S_i, .Lfunc_end6-_Z15mute_directwaveiiffffiiiiPfS_S_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 3808 ; NumSgprs: 23 ; NumVgprs: 26 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 3 ; NumSGPRsForWavesPerEU: 23 ; NumVGPRsForWavesPerEU: 26 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .protected d0 ; @d0 .type d0,@object .section .bss,"aw",@nobits .globl d0 .p2align 2, 0x0 d0: .long 0x00000000 ; float 0 .size d0, 4 .protected c ; @c .type c,@object .data .globl c .p2align 4, 0x0 c: .long 0x3f991fff ; float 1.19628894 .long 0xbda35555 ; float -0.0797526016 .long 0x3c1ccccd ; float 0.00957031269 .long 0xba36db6f ; float -6.97544718E-4 .size c, 16 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym d0 .addrsig_sym c .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: by_value - .offset: 44 .size: 4 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: by_value - .offset: 52 .size: 4 .value_kind: by_value - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 72 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10add_sourcefffiiiifffiiiiPfS_ .private_segment_fixed_size: 0 .sgpr_count: 14 .sgpr_spill_count: 0 .symbol: _Z10add_sourcefffiiiifffiiiiPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 88 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 96 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 104 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 112 .size: 8 .value_kind: global_buffer - .offset: 120 .size: 4 .value_kind: hidden_block_count_x - .offset: 124 .size: 4 .value_kind: hidden_block_count_y - .offset: 128 .size: 4 .value_kind: hidden_block_count_z - .offset: 132 .size: 2 .value_kind: hidden_group_size_x - .offset: 134 .size: 2 .value_kind: hidden_group_size_y - .offset: 136 .size: 2 .value_kind: hidden_group_size_z - .offset: 138 .size: 2 .value_kind: hidden_remainder_x - .offset: 140 .size: 2 .value_kind: hidden_remainder_y - .offset: 142 .size: 2 .value_kind: hidden_remainder_z - .offset: 160 .size: 8 .value_kind: hidden_global_offset_x - .offset: 168 .size: 8 .value_kind: hidden_global_offset_y - .offset: 176 .size: 8 .value_kind: hidden_global_offset_z - .offset: 184 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 376 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .private_segment_fixed_size: 0 .sgpr_count: 24 .sgpr_spill_count: 0 .symbol: _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 42 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .offset: 72 .size: 4 .value_kind: by_value - .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 88 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 96 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 104 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 112 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 120 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 128 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 136 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 144 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 152 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 160 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 168 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 176 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 184 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 192 .size: 8 .value_kind: global_buffer - .offset: 200 .size: 4 .value_kind: by_value - .offset: 204 .size: 4 .value_kind: by_value - .offset: 208 .size: 4 .value_kind: by_value - .offset: 212 .size: 4 .value_kind: by_value - .offset: 216 .size: 1 .value_kind: by_value - .offset: 224 .size: 4 .value_kind: hidden_block_count_x - .offset: 228 .size: 4 .value_kind: hidden_block_count_y - .offset: 232 .size: 4 .value_kind: hidden_block_count_z - .offset: 236 .size: 2 .value_kind: hidden_group_size_x - .offset: 238 .size: 2 .value_kind: hidden_group_size_y - .offset: 240 .size: 2 .value_kind: hidden_group_size_z - .offset: 242 .size: 2 .value_kind: hidden_remainder_x - .offset: 244 .size: 2 .value_kind: hidden_remainder_y - .offset: 246 .size: 2 .value_kind: hidden_remainder_z - .offset: 264 .size: 8 .value_kind: hidden_global_offset_x - .offset: 272 .size: 8 .value_kind: hidden_global_offset_y - .offset: 280 .size: 8 .value_kind: hidden_global_offset_z - .offset: 288 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 480 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .private_segment_fixed_size: 0 .sgpr_count: 22 .sgpr_spill_count: 0 .symbol: _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 50 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6get_d0ffiiiPf .private_segment_fixed_size: 0 .sgpr_count: 11 .sgpr_spill_count: 0 .symbol: _Z6get_d0ffiiiPf.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: hidden_block_count_x - .offset: 52 .size: 4 .value_kind: hidden_block_count_y - .offset: 56 .size: 4 .value_kind: hidden_block_count_z - .offset: 60 .size: 2 .value_kind: hidden_group_size_x - .offset: 62 .size: 2 .value_kind: hidden_group_size_y - .offset: 64 .size: 2 .value_kind: hidden_group_size_z - .offset: 66 .size: 2 .value_kind: hidden_remainder_x - .offset: 68 .size: 2 .value_kind: hidden_remainder_y - .offset: 70 .size: 2 .value_kind: hidden_remainder_z - .offset: 88 .size: 8 .value_kind: hidden_global_offset_x - .offset: 96 .size: 8 .value_kind: hidden_global_offset_y - .offset: 104 .size: 8 .value_kind: hidden_global_offset_z - .offset: 112 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 304 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13initial_coffefiPfS_S_S_i .private_segment_fixed_size: 0 .sgpr_count: 76 .sgpr_spill_count: 0 .symbol: _Z13initial_coffefiPfS_S_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 33 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .offset: 48 .size: 4 .value_kind: hidden_block_count_x - .offset: 52 .size: 4 .value_kind: hidden_block_count_y - .offset: 56 .size: 4 .value_kind: hidden_block_count_z - .offset: 60 .size: 2 .value_kind: hidden_group_size_x - .offset: 62 .size: 2 .value_kind: hidden_group_size_y - .offset: 64 .size: 2 .value_kind: hidden_group_size_z - .offset: 66 .size: 2 .value_kind: hidden_remainder_x - .offset: 68 .size: 2 .value_kind: hidden_remainder_y - .offset: 70 .size: 2 .value_kind: hidden_remainder_z - .offset: 88 .size: 8 .value_kind: hidden_global_offset_x - .offset: 96 .size: 8 .value_kind: hidden_global_offset_y - .offset: 104 .size: 8 .value_kind: hidden_global_offset_z - .offset: 112 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 304 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11shot_recordiiiiiiiPfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z11shot_recordiiiiiiiPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .offset: 72 .size: 4 .value_kind: by_value - .offset: 80 .size: 4 .value_kind: hidden_block_count_x - .offset: 84 .size: 4 .value_kind: hidden_block_count_y - .offset: 88 .size: 4 .value_kind: hidden_block_count_z - .offset: 92 .size: 2 .value_kind: hidden_group_size_x - .offset: 94 .size: 2 .value_kind: hidden_group_size_y - .offset: 96 .size: 2 .value_kind: hidden_group_size_z - .offset: 98 .size: 2 .value_kind: hidden_remainder_x - .offset: 100 .size: 2 .value_kind: hidden_remainder_y - .offset: 102 .size: 2 .value_kind: hidden_remainder_z - .offset: 120 .size: 8 .value_kind: hidden_global_offset_x - .offset: 128 .size: 8 .value_kind: hidden_global_offset_y - .offset: 136 .size: 8 .value_kind: hidden_global_offset_z - .offset: 144 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 336 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15mute_directwaveiiffffiiiiPfS_S_S_i .private_segment_fixed_size: 0 .sgpr_count: 23 .sgpr_spill_count: 0 .symbol: _Z15mute_directwaveiiffffiiiiPfS_S_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 26 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "297789cdb8cb1e88d34425cfd19a9286e06b9395.hip" .globl _Z15check_gpu_errorPKc # -- Begin function _Z15check_gpu_errorPKc .p2align 4, 0x90 .type _Z15check_gpu_errorPKc,@function _Z15check_gpu_errorPKc: # @_Z15check_gpu_errorPKc .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq %rdi, %rbx callq hipGetLastError testl %eax, %eax jne .LBB0_2 # %bb.1: popq %rbx .cfi_def_cfa_offset 8 retq .LBB0_2: .cfi_def_cfa_offset 16 movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movq %rbx, %rsi movq %rax, %rdx xorl %eax, %eax callq printf xorl %edi, %edi callq exit .Lfunc_end0: .size _Z15check_gpu_errorPKc, .Lfunc_end0-_Z15check_gpu_errorPKc .cfi_endproc # -- End function .globl _Z25__device_stub__add_sourcefffiiiifffiiiiPfS_ # -- Begin function _Z25__device_stub__add_sourcefffiiiifffiiiiPfS_ .p2align 4, 0x90 .type _Z25__device_stub__add_sourcefffiiiifffiiiiPfS_,@function _Z25__device_stub__add_sourcefffiiiifffiiiiPfS_: # @_Z25__device_stub__add_sourcefffiiiifffiiiiPfS_ .cfi_startproc # %bb.0: subq $232, %rsp .cfi_def_cfa_offset 240 movss %xmm0, 44(%rsp) movss %xmm1, 40(%rsp) movss %xmm2, 36(%rsp) movl %edi, 32(%rsp) movl %esi, 28(%rsp) movl %edx, 24(%rsp) movl %ecx, 20(%rsp) movss %xmm3, 16(%rsp) movss %xmm4, 12(%rsp) movss %xmm5, 8(%rsp) movl %r8d, 4(%rsp) movl %r9d, (%rsp) leaq 44(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rax movq %rax, 104(%rsp) leaq 36(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 28(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 20(%rsp), %rax movq %rax, 144(%rsp) leaq 16(%rsp), %rax movq %rax, 152(%rsp) leaq 12(%rsp), %rax movq %rax, 160(%rsp) leaq 8(%rsp), %rax movq %rax, 168(%rsp) leaq 4(%rsp), %rax movq %rax, 176(%rsp) movq %rsp, %rax movq %rax, 184(%rsp) leaq 240(%rsp), %rax movq %rax, 192(%rsp) leaq 248(%rsp), %rax movq %rax, 200(%rsp) leaq 256(%rsp), %rax movq %rax, 208(%rsp) leaq 264(%rsp), %rax movq %rax, 216(%rsp) leaq 80(%rsp), %rdi leaq 64(%rsp), %rsi leaq 56(%rsp), %rdx leaq 48(%rsp), %rcx callq __hipPopCallConfiguration movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 64(%rsp), %rcx movl 72(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z10add_sourcefffiiiifffiiiiPfS_, %edi pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $248, %rsp .cfi_adjust_cfa_offset -248 retq .Lfunc_end1: .size _Z25__device_stub__add_sourcefffiiiifffiiiiPfS_, .Lfunc_end1-_Z25__device_stub__add_sourcefffiiiifffiiiiPfS_ .cfi_endproc # -- End function .globl _Z25__device_stub__update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ # -- Begin function _Z25__device_stub__update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .p2align 4, 0x90 .type _Z25__device_stub__update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_,@function _Z25__device_stub__update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_: # @_Z25__device_stub__update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .cfi_startproc # %bb.0: subq $248, %rsp .cfi_def_cfa_offset 256 movl %edi, 36(%rsp) movl %esi, 32(%rsp) movl %edx, 28(%rsp) movl %ecx, 24(%rsp) movl %r8d, 20(%rsp) movss %xmm0, 16(%rsp) movss %xmm1, 12(%rsp) movss %xmm2, 8(%rsp) movq %r9, 88(%rsp) leaq 36(%rsp), %rax movq %rax, 96(%rsp) leaq 32(%rsp), %rax movq %rax, 104(%rsp) leaq 28(%rsp), %rax movq %rax, 112(%rsp) leaq 24(%rsp), %rax movq %rax, 120(%rsp) leaq 20(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 12(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) leaq 88(%rsp), %rax movq %rax, 160(%rsp) leaq 256(%rsp), %rax movq %rax, 168(%rsp) leaq 264(%rsp), %rax movq %rax, 176(%rsp) leaq 272(%rsp), %rax movq %rax, 184(%rsp) leaq 280(%rsp), %rax movq %rax, 192(%rsp) leaq 288(%rsp), %rax movq %rax, 200(%rsp) leaq 296(%rsp), %rax movq %rax, 208(%rsp) leaq 304(%rsp), %rax movq %rax, 216(%rsp) leaq 312(%rsp), %rax movq %rax, 224(%rsp) leaq 320(%rsp), %rax movq %rax, 232(%rsp) leaq 328(%rsp), %rax movq %rax, 240(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_, %edi pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $264, %rsp # imm = 0x108 .cfi_adjust_cfa_offset -264 retq .Lfunc_end2: .size _Z25__device_stub__update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_, .Lfunc_end2-_Z25__device_stub__update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .cfi_endproc # -- End function .globl _Z28__device_stub__update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib # -- Begin function _Z28__device_stub__update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .p2align 4, 0x90 .type _Z28__device_stub__update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib,@function _Z28__device_stub__update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib: # @_Z28__device_stub__update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .cfi_startproc # %bb.0: subq $360, %rsp # imm = 0x168 .cfi_def_cfa_offset 368 movzbl 552(%rsp), %eax movl %edi, 28(%rsp) movl %esi, 24(%rsp) movl %edx, 20(%rsp) movl %ecx, 16(%rsp) movss %xmm0, 12(%rsp) movss %xmm1, 8(%rsp) movss %xmm2, 4(%rsp) movq %r8, 88(%rsp) movq %r9, 80(%rsp) movb %al, 3(%rsp) leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 24(%rsp), %rax movq %rax, 104(%rsp) leaq 20(%rsp), %rax movq %rax, 112(%rsp) leaq 16(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) leaq 8(%rsp), %rax movq %rax, 136(%rsp) leaq 4(%rsp), %rax movq %rax, 144(%rsp) leaq 88(%rsp), %rax movq %rax, 152(%rsp) leaq 80(%rsp), %rax movq %rax, 160(%rsp) leaq 368(%rsp), %rax movq %rax, 168(%rsp) leaq 376(%rsp), %rax movq %rax, 176(%rsp) leaq 384(%rsp), %rax movq %rax, 184(%rsp) leaq 392(%rsp), %rax movq %rax, 192(%rsp) leaq 400(%rsp), %rax movq %rax, 200(%rsp) leaq 408(%rsp), %rax movq %rax, 208(%rsp) leaq 416(%rsp), %rax movq %rax, 216(%rsp) leaq 424(%rsp), %rax movq %rax, 224(%rsp) leaq 432(%rsp), %rax movq %rax, 232(%rsp) leaq 440(%rsp), %rax movq %rax, 240(%rsp) leaq 448(%rsp), %rax movq %rax, 248(%rsp) leaq 456(%rsp), %rax movq %rax, 256(%rsp) leaq 464(%rsp), %rax movq %rax, 264(%rsp) leaq 472(%rsp), %rax movq %rax, 272(%rsp) leaq 480(%rsp), %rax movq %rax, 280(%rsp) leaq 488(%rsp), %rax movq %rax, 288(%rsp) leaq 496(%rsp), %rax movq %rax, 296(%rsp) leaq 504(%rsp), %rax movq %rax, 304(%rsp) leaq 512(%rsp), %rax movq %rax, 312(%rsp) leaq 520(%rsp), %rax movq %rax, 320(%rsp) leaq 528(%rsp), %rax movq %rax, 328(%rsp) leaq 536(%rsp), %rax movq %rax, 336(%rsp) leaq 544(%rsp), %rax movq %rax, 344(%rsp) leaq 3(%rsp), %rax movq %rax, 352(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $376, %rsp # imm = 0x178 .cfi_adjust_cfa_offset -376 retq .Lfunc_end3: .size _Z28__device_stub__update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib, .Lfunc_end3-_Z28__device_stub__update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .cfi_endproc # -- End function .globl _Z21__device_stub__get_d0ffiiiPf # -- Begin function _Z21__device_stub__get_d0ffiiiPf .p2align 4, 0x90 .type _Z21__device_stub__get_d0ffiiiPf,@function _Z21__device_stub__get_d0ffiiiPf: # @_Z21__device_stub__get_d0ffiiiPf .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movss %xmm0, 20(%rsp) movss %xmm1, 16(%rsp) movl %edi, 12(%rsp) movl %esi, 8(%rsp) movl %edx, 4(%rsp) movq %rcx, 72(%rsp) leaq 20(%rsp), %rax movq %rax, 80(%rsp) leaq 16(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 4(%rsp), %rax movq %rax, 112(%rsp) leaq 72(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6get_d0ffiiiPf, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end4: .size _Z21__device_stub__get_d0ffiiiPf, .Lfunc_end4-_Z21__device_stub__get_d0ffiiiPf .cfi_endproc # -- End function .globl _Z6pad_vviiiiiPf # -- Begin function _Z6pad_vviiiiiPf .p2align 4, 0x90 .type _Z6pad_vviiiiiPf,@function _Z6pad_vviiiiiPf: # @_Z6pad_vviiiiiPf .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset %rbx, -24 .cfi_offset %rbp, -16 movl %ecx, %r11d imull %edx, %r11d movl %r11d, %r10d testl %r11d, %r11d jle .LBB5_6 # %bb.1: # %.lr.ph movl %edx, %esi subl %r8d, %esi leal -1(%rsi), %ebx xorl %edi, %edi jmp .LBB5_2 .p2align 4, 0x90 .LBB5_4: # %.sink.split # in Loop: Header=BB5_2 Depth=1 imull %ecx, %ebp addl %ebp, %edx movslq %edx, %rax movss (%r9,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%r9,%rdi,4) .LBB5_5: # in Loop: Header=BB5_2 Depth=1 incq %rdi cmpq %rdi, %r10 je .LBB5_6 .LBB5_2: # =>This Inner Loop Header: Depth=1 movl %edi, %eax cltd idivl %ecx movl %r8d, %ebp cmpl %r8d, %eax jl .LBB5_4 # %bb.3: # in Loop: Header=BB5_2 Depth=1 movl %ebx, %ebp cmpl %esi, %eax jge .LBB5_4 jmp .LBB5_5 .LBB5_6: # %.preheader testl %r11d, %r11d jle .LBB5_13 # %bb.7: # %.lr.ph60 movl %ecx, %edi subl %r8d, %edi movl %r8d, %r11d notl %r11d xorl %esi, %esi jmp .LBB5_8 .p2align 4, 0x90 .LBB5_11: # %.sink.split70 # in Loop: Header=BB5_8 Depth=1 imull %ecx, %eax addl %ebx, %eax cltq movss (%r9,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%r9,%rsi,4) .LBB5_12: # in Loop: Header=BB5_8 Depth=1 incq %rsi cmpq %rsi, %r10 je .LBB5_13 .LBB5_8: # =>This Inner Loop Header: Depth=1 movl %esi, %eax cltd idivl %ecx movl %r8d, %ebx cmpl %r8d, %edx jl .LBB5_11 # %bb.9: # in Loop: Header=BB5_8 Depth=1 cmpl %edi, %edx jl .LBB5_12 # %bb.10: # in Loop: Header=BB5_8 Depth=1 incl %eax movl %r11d, %ebx jmp .LBB5_11 .LBB5_13: # %._crit_edge popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end5: .size _Z6pad_vviiiiiPf, .Lfunc_end5-_Z6pad_vviiiiiPf .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function _Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i .LCPI6_0: .quad 0x3f91df46a2443411 # double 0.017453292516666667 .text .globl _Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i .p2align 4, 0x90 .type _Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i,@function _Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i: # @_Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $120, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %r9d, 12(%rsp) # 4-byte Spill movl %r8d, %ebp movq %rcx, 24(%rsp) # 8-byte Spill movq %rdx, %r13 movq %rsi, %r12 movq %rdi, %r15 movl 224(%rsp), %ebx movq 216(%rsp), %rax movq %rax, 64(%rsp) # 8-byte Spill movq 208(%rsp), %rax movq %rax, 56(%rsp) # 8-byte Spill movq 200(%rsp), %rax movq %rax, 48(%rsp) # 8-byte Spill movq 192(%rsp), %rax movq %rax, 40(%rsp) # 8-byte Spill movl 184(%rsp), %eax movl %eax, 16(%rsp) # 4-byte Spill movl $.L.str.1, %esi callq fopen movq %rax, 32(%rsp) # 8-byte Spill testq %rax, %rax jne .LBB6_2 # %bb.1: movl $.L.str.2, %edi movq %r15, %rsi xorl %eax, %eax callq printf .LBB6_2: movl $.L.str.1, %esi movq %r12, %rdi callq fopen movq %rax, %r14 testq %rax, %rax jne .LBB6_4 # %bb.3: movl $.L.str.2, %edi movq %r12, %rsi xorl %eax, %eax callq printf .LBB6_4: movl $.L.str.1, %esi movq %r13, %rdi callq fopen movq %rax, %r15 testq %rax, %rax jne .LBB6_6 # %bb.5: movl $.L.str.2, %edi movq %r13, %rsi xorl %eax, %eax callq printf .LBB6_6: movq %r15, 80(%rsp) # 8-byte Spill movq %r14, 88(%rsp) # 8-byte Spill movl $.L.str.1, %esi movq 24(%rsp), %r14 # 8-byte Reload movq %r14, %rdi callq fopen movq %rax, 72(%rsp) # 8-byte Spill testq %rax, %rax jne .LBB6_8 # %bb.7: movl $.L.str.2, %edi movq %r14, %rsi xorl %eax, %eax callq printf .LBB6_8: testl %ebp, %ebp movq 32(%rsp), %rdi # 8-byte Reload jle .LBB6_14 # %bb.9: # %.preheader.lr.ph addl %ebx, %ebp movslq %ebx, %rax addl 12(%rsp), %ebx # 4-byte Folded Reload movslq %ebx, %rcx movslq 16(%rsp), %rdx # 4-byte Folded Reload movslq %ebp, %rsi movq %rsi, 104(%rsp) # 8-byte Spill leaq 1(%rdx), %rbx imulq %rax, %rbx shlq $2, %rbx shlq $2, %rdx movq %rdx, 112(%rsp) # 8-byte Spill movq %rax, 96(%rsp) # 8-byte Spill movq %rax, %rdx movq %rcx, 24(%rsp) # 8-byte Spill jmp .LBB6_10 .p2align 4, 0x90 .LBB6_13: # %._crit_edge # in Loop: Header=BB6_10 Depth=1 movq 16(%rsp), %rdx # 8-byte Reload incq %rdx movq 112(%rsp), %rax # 8-byte Reload addq %rax, 40(%rsp) # 8-byte Folded Spill addq %rax, 48(%rsp) # 8-byte Folded Spill addq %rax, 56(%rsp) # 8-byte Folded Spill addq %rax, 64(%rsp) # 8-byte Folded Spill cmpq 104(%rsp), %rdx # 8-byte Folded Reload jge .LBB6_14 .LBB6_10: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB6_12 Depth 2 movq %rdx, 16(%rsp) # 8-byte Spill cmpl $0, 12(%rsp) # 4-byte Folded Reload jle .LBB6_13 # %bb.11: # %.lr.ph # in Loop: Header=BB6_10 Depth=1 movq 64(%rsp), %r14 # 8-byte Reload movq 56(%rsp), %r15 # 8-byte Reload movq 48(%rsp), %r12 # 8-byte Reload movq 40(%rsp), %r13 # 8-byte Reload movq 96(%rsp), %rbp # 8-byte Reload .p2align 4, 0x90 .LBB6_12: # Parent Loop BB6_10 Depth=1 # => This Inner Loop Header: Depth=2 leaq (%rbx,%r13), %rdi movl $4, %esi movl $1, %edx movq 32(%rsp), %rcx # 8-byte Reload callq fread leaq (%r12,%rbx), %rdi movl $4, %esi movl $1, %edx movq 88(%rsp), %rcx # 8-byte Reload callq fread leaq (%r15,%rbx), %rdi movl $4, %esi movl $1, %edx movq 80(%rsp), %rcx # 8-byte Reload callq fread leaq (%r14,%rbx), %rdi movl $4, %esi movl $1, %edx movq 72(%rsp), %rcx # 8-byte Reload callq fread movsd .LCPI6_0(%rip), %xmm1 # xmm1 = mem[0],zero movq 24(%rsp), %rcx # 8-byte Reload movq 32(%rsp), %rdi # 8-byte Reload movss (%r14,%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 mulsd %xmm1, %xmm0 cvtsd2ss %xmm0, %xmm0 movss %xmm0, (%r14,%rbx) incq %rbp addq $4, %r13 addq $4, %r12 addq $4, %r15 addq $4, %r14 cmpq %rcx, %rbp jl .LBB6_12 jmp .LBB6_13 .LBB6_14: # %._crit_edge41 callq fclose movq 88(%rsp), %rdi # 8-byte Reload callq fclose movq 80(%rsp), %rdi # 8-byte Reload callq fclose movq 72(%rsp), %rdi # 8-byte Reload addq $120, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 jmp fclose # TAILCALL .Lfunc_end6: .size _Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i, .Lfunc_end6-_Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i .cfi_endproc # -- End function .globl _Z28__device_stub__initial_coffefiPfS_S_S_i # -- Begin function _Z28__device_stub__initial_coffefiPfS_S_S_i .p2align 4, 0x90 .type _Z28__device_stub__initial_coffefiPfS_S_S_i,@function _Z28__device_stub__initial_coffefiPfS_S_S_i: # @_Z28__device_stub__initial_coffefiPfS_S_S_i .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movss %xmm0, 12(%rsp) movl %edi, 8(%rsp) movq %rsi, 88(%rsp) movq %rdx, 80(%rsp) movq %rcx, 72(%rsp) movq %r8, 64(%rsp) movl %r9d, 4(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 88(%rsp), %rax movq %rax, 112(%rsp) leaq 80(%rsp), %rax movq %rax, 120(%rsp) leaq 72(%rsp), %rax movq %rax, 128(%rsp) leaq 64(%rsp), %rax movq %rax, 136(%rsp) leaq 4(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z13initial_coffefiPfS_S_S_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end7: .size _Z28__device_stub__initial_coffefiPfS_S_S_i, .Lfunc_end7-_Z28__device_stub__initial_coffefiPfS_S_S_i .cfi_endproc # -- End function .globl _Z26__device_stub__shot_recordiiiiiiiPfS_ # -- Begin function _Z26__device_stub__shot_recordiiiiiiiPfS_ .p2align 4, 0x90 .type _Z26__device_stub__shot_recordiiiiiiiPfS_,@function _Z26__device_stub__shot_recordiiiiiiiPfS_: # @_Z26__device_stub__shot_recordiiiiiiiPfS_ .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 28(%rsp) movl %esi, 24(%rsp) movl %edx, 20(%rsp) movl %ecx, 16(%rsp) movl %r8d, 12(%rsp) movl %r9d, 8(%rsp) leaq 28(%rsp), %rax movq %rax, 80(%rsp) leaq 24(%rsp), %rax movq %rax, 88(%rsp) leaq 20(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 160(%rsp), %rax movq %rax, 128(%rsp) leaq 168(%rsp), %rax movq %rax, 136(%rsp) leaq 176(%rsp), %rax movq %rax, 144(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z11shot_recordiiiiiiiPfS_, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end8: .size _Z26__device_stub__shot_recordiiiiiiiPfS_, .Lfunc_end8-_Z26__device_stub__shot_recordiiiiiiiPfS_ .cfi_endproc # -- End function .globl _Z30__device_stub__mute_directwaveiiffffiiiiPfS_S_S_i # -- Begin function _Z30__device_stub__mute_directwaveiiffffiiiiPfS_S_S_i .p2align 4, 0x90 .type _Z30__device_stub__mute_directwaveiiffffiiiiPfS_S_S_i,@function _Z30__device_stub__mute_directwaveiiffffiiiiPfS_S_S_i: # @_Z30__device_stub__mute_directwaveiiffffiiiiPfS_S_S_i .cfi_startproc # %bb.0: subq $216, %rsp .cfi_def_cfa_offset 224 movl %edi, 44(%rsp) movl %esi, 40(%rsp) movss %xmm0, 36(%rsp) movss %xmm1, 32(%rsp) movss %xmm2, 28(%rsp) movss %xmm3, 24(%rsp) movl %edx, 20(%rsp) movl %ecx, 16(%rsp) movl %r8d, 12(%rsp) movl %r9d, 8(%rsp) leaq 44(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rax movq %rax, 104(%rsp) leaq 36(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 28(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 20(%rsp), %rax movq %rax, 144(%rsp) leaq 16(%rsp), %rax movq %rax, 152(%rsp) leaq 12(%rsp), %rax movq %rax, 160(%rsp) leaq 8(%rsp), %rax movq %rax, 168(%rsp) leaq 224(%rsp), %rax movq %rax, 176(%rsp) leaq 232(%rsp), %rax movq %rax, 184(%rsp) leaq 240(%rsp), %rax movq %rax, 192(%rsp) leaq 248(%rsp), %rax movq %rax, 200(%rsp) leaq 256(%rsp), %rax movq %rax, 208(%rsp) leaq 80(%rsp), %rdi leaq 64(%rsp), %rsi leaq 56(%rsp), %rdx leaq 48(%rsp), %rcx callq __hipPopCallConfiguration movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 64(%rsp), %rcx movl 72(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z15mute_directwaveiiffffiiiiPfS_S_S_i, %edi pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $232, %rsp .cfi_adjust_cfa_offset -232 retq .Lfunc_end9: .size _Z30__device_stub__mute_directwaveiiffffiiiiPfS_S_S_i, .Lfunc_end9-_Z30__device_stub__mute_directwaveiiffffiiiiPfS_S_S_i .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI10_0: .long 0x3a03126f # float 5.00000024E-4 .LCPI10_1: .long 0x40a00000 # float 5 .LCPI10_2: .long 0x49742400 # float 1.0E+6 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $1640, %rsp # imm = 0x668 .cfi_def_cfa_offset 1696 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 leaq 1120(%rsp), %rdi movl $.L__const.main.FN1, %esi movl $250, %edx callq memcpy@PLT leaq 864(%rsp), %rdi movl $.L__const.main.FN2, %esi movl $250, %edx callq memcpy@PLT leaq 608(%rsp), %rdi movl $.L__const.main.FN3, %esi movl $250, %edx callq memcpy@PLT leaq 1376(%rsp), %rbp movl $.L__const.main.FN4, %esi movl $250, %edx movq %rbp, %rdi callq memcpy@PLT movl $.L__const.main.FN5, %edi movl $.L.str.3, %esi callq fopen movq %rax, 592(%rsp) # 8-byte Spill movl $.L__const.main.FN6, %edi movl $.L.str.3, %esi callq fopen movq %rax, 576(%rsp) # 8-byte Spill movl $1120000, %edi # imm = 0x111700 callq malloc movq %rax, %r13 movq %rax, 568(%rsp) # 8-byte Spill movl $1120000, %edi # imm = 0x111700 callq malloc movq %rax, %r12 movq %rax, %r14 movl $1120000, %edi # imm = 0x111700 callq malloc movq %rax, %r15 movq %rax, 560(%rsp) # 8-byte Spill movl $1120000, %edi # imm = 0x111700 callq malloc movq %rax, %rbx movq %rax, 552(%rsp) # 8-byte Spill movl $1922400, %edi # imm = 0x1D5560 callq malloc movq %rax, 600(%rsp) # 8-byte Spill subq $64, %rsp .cfi_adjust_cfa_offset 64 movq %rbx, 40(%rsp) movq %r15, 32(%rsp) movq %r12, 24(%rsp) movq %r13, 16(%rsp) movl $50, 48(%rsp) movl $400, 8(%rsp) # imm = 0x190 leaq 1184(%rsp), %rdi leaq 928(%rsp), %rsi leaq 672(%rsp), %rdx movq %rbp, %rcx movl $600, %r8d # imm = 0x258 movl $300, %r9d # imm = 0x12C callq _Z9read_filePcS_S_S_iiiiPfS0_S0_S0_i addq $64, %rsp .cfi_adjust_cfa_offset -64 leaq 80000(%r12), %rsi movl $1038400, %edi # imm = 0xFD840 xorl %r8d, %r8d movabsq $737869762948382065, %rcx # imm = 0xA3D70A3D70A3D71 jmp .LBB10_1 .p2align 4, 0x90 .LBB10_2: # in Loop: Header=BB10_1 Depth=1 movl %r8d, %eax imulq $1374389535, %rax, %rax # imm = 0x51EB851F shrq $39, %rax imull $-400, %eax, %eax # imm = 0xFE70 addq %r8, %rax cltq leaq (%rsi,%rax,4), %rax .LBB10_5: # %.sink.split # in Loop: Header=BB10_1 Depth=1 movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%r14,%r8,4) .LBB10_6: # in Loop: Header=BB10_1 Depth=1 incq %r8 addq $4, %rdi cmpq $280000, %r8 # imm = 0x445C0 je .LBB10_7 .LBB10_1: # =>This Inner Loop Header: Depth=1 movq %r8, %rax shrq $4, %rax mulq %rcx cmpl $19999, %r8d # imm = 0x4E1F jle .LBB10_2 # %bb.3: # in Loop: Header=BB10_1 Depth=1 cmpl $260000, %r8d # imm = 0x3F7A0 jl .LBB10_6 # %bb.4: # in Loop: Header=BB10_1 Depth=1 imulq $1600, %rdx, %rdx # imm = 0x640 movq %rdi, %rax subq %rdx, %rax addq %r12, %rax jmp .LBB10_5 .LBB10_7: # %.preheader.i.preheader addq $200, %r12 xorl %eax, %eax jmp .LBB10_8 .p2align 4, 0x90 .LBB10_9: # in Loop: Header=BB10_8 Depth=1 imull $400, %edx, %edx # imm = 0x190 movq %r12, %rsi .LBB10_12: # %.sink.split406 # in Loop: Header=BB10_8 Depth=1 movslq %edx, %rdx movss (%rsi,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%r14,%rax,4) .LBB10_13: # in Loop: Header=BB10_8 Depth=1 incq %rax cmpq $280000, %rax # imm = 0x445C0 je .LBB10_14 .LBB10_8: # %.preheader.i # =>This Inner Loop Header: Depth=1 movl %eax, %edx imulq $1374389535, %rdx, %rdx # imm = 0x51EB851F shrq $39, %rdx imull $-400, %edx, %esi # imm = 0xFE70 movslq %eax, %rdx imulq $1374389535, %rdx, %rdx # imm = 0x51EB851F movq %rdx, %rdi shrq $63, %rdi sarq $39, %rdx addl %edi, %edx addq %rax, %rsi cmpl $49, %esi jle .LBB10_9 # %bb.10: # in Loop: Header=BB10_8 Depth=1 cmpl $350, %esi # imm = 0x15E jl .LBB10_13 # %bb.11: # in Loop: Header=BB10_8 Depth=1 imull $400, %edx, %edx # imm = 0x190 addl $349, %edx # imm = 0x15D movq %r14, %rsi jmp .LBB10_12 .LBB10_14: # %_Z6pad_vviiiiiPf.exit.preheader leaq 80000(%r15), %rsi movl $1038400, %edi # imm = 0xFD840 xorl %r8d, %r8d movq 560(%rsp), %r12 # 8-byte Reload jmp .LBB10_15 .p2align 4, 0x90 .LBB10_16: # in Loop: Header=BB10_15 Depth=1 movl %r8d, %eax imulq $1374389535, %rax, %rax # imm = 0x51EB851F shrq $39, %rax imull $-400, %eax, %eax # imm = 0xFE70 addq %r8, %rax cltq leaq (%rsi,%rax,4), %rax .LBB10_19: # %.sink.split411 # in Loop: Header=BB10_15 Depth=1 movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%r12,%r8,4) .LBB10_20: # in Loop: Header=BB10_15 Depth=1 incq %r8 addq $4, %rdi cmpq $280000, %r8 # imm = 0x445C0 je .LBB10_21 .LBB10_15: # %_Z6pad_vviiiiiPf.exit # =>This Inner Loop Header: Depth=1 movq %r8, %rax shrq $4, %rax mulq %rcx cmpl $19999, %r8d # imm = 0x4E1F jle .LBB10_16 # %bb.17: # in Loop: Header=BB10_15 Depth=1 cmpl $260000, %r8d # imm = 0x3F7A0 jl .LBB10_20 # %bb.18: # in Loop: Header=BB10_15 Depth=1 imulq $1600, %rdx, %rdx # imm = 0x640 movq %rdi, %rax subq %rdx, %rax addq %r15, %rax jmp .LBB10_19 .LBB10_21: # %.preheader.i283.preheader addq $200, %r15 xorl %eax, %eax jmp .LBB10_22 .p2align 4, 0x90 .LBB10_23: # in Loop: Header=BB10_22 Depth=1 imull $400, %edx, %edx # imm = 0x190 movq %r15, %rsi .LBB10_26: # %.sink.split414 # in Loop: Header=BB10_22 Depth=1 movslq %edx, %rdx movss (%rsi,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%r12,%rax,4) .LBB10_27: # in Loop: Header=BB10_22 Depth=1 incq %rax cmpq $280000, %rax # imm = 0x445C0 je .LBB10_28 .LBB10_22: # %.preheader.i283 # =>This Inner Loop Header: Depth=1 movl %eax, %edx imulq $1374389535, %rdx, %rdx # imm = 0x51EB851F shrq $39, %rdx imull $-400, %edx, %esi # imm = 0xFE70 movslq %eax, %rdx imulq $1374389535, %rdx, %rdx # imm = 0x51EB851F movq %rdx, %rdi shrq $63, %rdi sarq $39, %rdx addl %edi, %edx addq %rax, %rsi cmpl $49, %esi jle .LBB10_23 # %bb.24: # in Loop: Header=BB10_22 Depth=1 cmpl $350, %esi # imm = 0x15E jl .LBB10_27 # %bb.25: # in Loop: Header=BB10_22 Depth=1 imull $400, %edx, %edx # imm = 0x190 addl $349, %edx # imm = 0x15D movq %r12, %rsi jmp .LBB10_26 .LBB10_28: # %_Z6pad_vviiiiiPf.exit288.preheader leaq 80000(%r13), %rsi movl $1038400, %edi # imm = 0xFD840 xorl %r8d, %r8d movq 568(%rsp), %r15 # 8-byte Reload jmp .LBB10_29 .p2align 4, 0x90 .LBB10_30: # in Loop: Header=BB10_29 Depth=1 movl %r8d, %eax imulq $1374389535, %rax, %rax # imm = 0x51EB851F shrq $39, %rax imull $-400, %eax, %eax # imm = 0xFE70 addq %r8, %rax cltq leaq (%rsi,%rax,4), %rax .LBB10_33: # %.sink.split421 # in Loop: Header=BB10_29 Depth=1 movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%r15,%r8,4) .LBB10_34: # in Loop: Header=BB10_29 Depth=1 incq %r8 addq $4, %rdi cmpq $280000, %r8 # imm = 0x445C0 je .LBB10_35 .LBB10_29: # %_Z6pad_vviiiiiPf.exit288 # =>This Inner Loop Header: Depth=1 movq %r8, %rax shrq $4, %rax mulq %rcx cmpl $19999, %r8d # imm = 0x4E1F jle .LBB10_30 # %bb.31: # in Loop: Header=BB10_29 Depth=1 cmpl $260000, %r8d # imm = 0x3F7A0 jl .LBB10_34 # %bb.32: # in Loop: Header=BB10_29 Depth=1 imulq $1600, %rdx, %rdx # imm = 0x640 movq %rdi, %rax subq %rdx, %rax addq %r13, %rax jmp .LBB10_33 .LBB10_35: # %.preheader.i293.preheader addq $200, %r13 xorl %eax, %eax jmp .LBB10_36 .p2align 4, 0x90 .LBB10_37: # in Loop: Header=BB10_36 Depth=1 imull $400, %edx, %edx # imm = 0x190 movq %r13, %rsi .LBB10_40: # %.sink.split424 # in Loop: Header=BB10_36 Depth=1 movslq %edx, %rdx movss (%rsi,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%r15,%rax,4) .LBB10_41: # in Loop: Header=BB10_36 Depth=1 incq %rax cmpq $280000, %rax # imm = 0x445C0 je .LBB10_42 .LBB10_36: # %.preheader.i293 # =>This Inner Loop Header: Depth=1 movl %eax, %edx imulq $1374389535, %rdx, %rdx # imm = 0x51EB851F shrq $39, %rdx imull $-400, %edx, %esi # imm = 0xFE70 movslq %eax, %rdx imulq $1374389535, %rdx, %rdx # imm = 0x51EB851F movq %rdx, %rdi shrq $63, %rdi sarq $39, %rdx addl %edi, %edx addq %rax, %rsi cmpl $49, %esi jle .LBB10_37 # %bb.38: # in Loop: Header=BB10_36 Depth=1 cmpl $350, %esi # imm = 0x15E jl .LBB10_41 # %bb.39: # in Loop: Header=BB10_36 Depth=1 imull $400, %edx, %edx # imm = 0x190 addl $349, %edx # imm = 0x15D movq %r15, %rsi jmp .LBB10_40 .LBB10_42: # %_Z6pad_vviiiiiPf.exit298.preheader leaq 80000(%rbx), %rsi movl $1038400, %edi # imm = 0xFD840 xorl %r8d, %r8d movq 552(%rsp), %r13 # 8-byte Reload jmp .LBB10_43 .p2align 4, 0x90 .LBB10_44: # in Loop: Header=BB10_43 Depth=1 movl %r8d, %eax imulq $1374389535, %rax, %rax # imm = 0x51EB851F shrq $39, %rax imull $-400, %eax, %eax # imm = 0xFE70 addq %r8, %rax cltq leaq (%rsi,%rax,4), %rax .LBB10_47: # %.sink.split431 # in Loop: Header=BB10_43 Depth=1 movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%r13,%r8,4) .LBB10_48: # in Loop: Header=BB10_43 Depth=1 incq %r8 addq $4, %rdi cmpq $280000, %r8 # imm = 0x445C0 je .LBB10_49 .LBB10_43: # %_Z6pad_vviiiiiPf.exit298 # =>This Inner Loop Header: Depth=1 movq %r8, %rax shrq $4, %rax mulq %rcx cmpl $19999, %r8d # imm = 0x4E1F jle .LBB10_44 # %bb.45: # in Loop: Header=BB10_43 Depth=1 cmpl $260000, %r8d # imm = 0x3F7A0 jl .LBB10_48 # %bb.46: # in Loop: Header=BB10_43 Depth=1 imulq $1600, %rdx, %rdx # imm = 0x640 movq %rdi, %rax subq %rdx, %rax addq %rbx, %rax jmp .LBB10_47 .LBB10_49: # %.preheader.i303.preheader addq $200, %rbx xorl %eax, %eax jmp .LBB10_50 .p2align 4, 0x90 .LBB10_51: # in Loop: Header=BB10_50 Depth=1 imull $400, %ecx, %ecx # imm = 0x190 movq %rbx, %rdx .LBB10_54: # %.sink.split434 # in Loop: Header=BB10_50 Depth=1 movslq %ecx, %rcx movss (%rdx,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%r13,%rax,4) .LBB10_55: # in Loop: Header=BB10_50 Depth=1 incq %rax cmpq $280000, %rax # imm = 0x445C0 je .LBB10_56 .LBB10_50: # %.preheader.i303 # =>This Inner Loop Header: Depth=1 movl %eax, %ecx imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F shrq $39, %rcx imull $-400, %ecx, %edx # imm = 0xFE70 movslq %eax, %rcx imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F movq %rcx, %rsi shrq $63, %rsi sarq $39, %rcx addl %esi, %ecx addq %rax, %rdx cmpl $49, %edx jle .LBB10_51 # %bb.52: # in Loop: Header=BB10_50 Depth=1 cmpl $350, %edx # imm = 0x15E jl .LBB10_55 # %bb.53: # in Loop: Header=BB10_50 Depth=1 imull $400, %ecx, %ecx # imm = 0x190 addl $349, %ecx # imm = 0x15D movq %r13, %rdx jmp .LBB10_54 .LBB10_56: # %_Z6pad_vviiiiiPf.exit308 xorl %edi, %edi callq hipSetDevice callq hipGetLastError testl %eax, %eax jne .LBB10_57 # %bb.59: # %_Z15check_gpu_errorPKc.exit leaq 280(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 360(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 352(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 272(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc movq 280(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 movq %r15, %rsi movl $1, %ecx callq hipMemcpy movq 360(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movq 352(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 movq %r12, %rsi movl $1, %ecx callq hipMemcpy movq 272(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 movq %r13, %rsi movl $1, %ecx callq hipMemcpy leaq 264(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 160(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 224(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 152(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 112(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 144(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 256(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 240(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 216(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 200(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 248(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 232(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 208(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 192(%rsp), %rdi movl $1120000, %esi # imm = 0x111700 callq hipMalloc leaq 344(%rsp), %rdi movl $2800, %esi # imm = 0xAF0 callq hipMalloc leaq 336(%rsp), %rdi movl $2800, %esi # imm = 0xAF0 callq hipMalloc leaq 328(%rsp), %rdi movl $1600, %esi # imm = 0x640 callq hipMalloc leaq 320(%rsp), %rdi movl $1600, %esi # imm = 0x640 callq hipMalloc leaq 312(%rsp), %rdi movl $2800, %esi # imm = 0xAF0 callq hipMalloc leaq 304(%rsp), %rdi movl $2800, %esi # imm = 0xAF0 callq hipMalloc leaq 296(%rsp), %rdi movl $1600, %esi # imm = 0x640 callq hipMalloc leaq 288(%rsp), %rdi movl $1600, %esi # imm = 0x640 callq hipMalloc leaq 184(%rsp), %rdi movl $1922400, %esi # imm = 0x1D5560 callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB10_60 # %bb.61: # %_Z15check_gpu_errorPKc.exit311 movabsq $4294967297, %r15 # imm = 0x100000001 movq %r15, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_63 # %bb.62: movq 280(%rsp), %rax movl $1084227584, 40(%rsp) # imm = 0x40A00000 movl $1084227584, 32(%rsp) # imm = 0x40A00000 movl $700, 24(%rsp) # imm = 0x2BC movl $400, 16(%rsp) # imm = 0x190 movl $50, 8(%rsp) movq %rax, 96(%rsp) leaq 40(%rsp), %rax movq %rax, 400(%rsp) leaq 32(%rsp), %rax movq %rax, 408(%rsp) leaq 24(%rsp), %rax movq %rax, 416(%rsp) leaq 16(%rsp), %rax movq %rax, 424(%rsp) leaq 8(%rsp), %rax movq %rax, 432(%rsp) leaq 96(%rsp), %rax movq %rax, 440(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 88(%rsp), %rdx leaq 48(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 400(%rsp), %r9 movl $_Z6get_d0ffiiiPf, %edi pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 96(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_63: leaq 1(%r15), %r13 leaq 511(%r15), %rbx movq %r13, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_65 # %bb.64: movq 344(%rsp), %rax movq 336(%rsp), %rcx movq 312(%rsp), %rdx movq 304(%rsp), %rsi movl $973279855, 16(%rsp) # imm = 0x3A03126F movl $600, 8(%rsp) # imm = 0x258 movq %rax, 96(%rsp) movq %rcx, 88(%rsp) movq %rdx, 48(%rsp) movq %rsi, 40(%rsp) movl $50, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 400(%rsp) leaq 8(%rsp), %rax movq %rax, 408(%rsp) leaq 96(%rsp), %rax movq %rax, 416(%rsp) leaq 88(%rsp), %rax movq %rax, 424(%rsp) leaq 48(%rsp), %rax movq %rax, 432(%rsp) leaq 40(%rsp), %rax movq %rax, 440(%rsp) leaq 104(%rsp), %rax movq %rax, 448(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 400(%rsp), %r9 movl $_Z13initial_coffefiPfS_S_S_i, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_65: movq %r15, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_67 # %bb.66: movq 328(%rsp), %rax movq 320(%rsp), %rcx movq 296(%rsp), %rdx movq 288(%rsp), %rsi movl $973279855, 16(%rsp) # imm = 0x3A03126F movl $300, 8(%rsp) # imm = 0x12C movq %rax, 96(%rsp) movq %rcx, 88(%rsp) movq %rdx, 48(%rsp) movq %rsi, 40(%rsp) movl $50, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 400(%rsp) leaq 8(%rsp), %rax movq %rax, 408(%rsp) leaq 96(%rsp), %rax movq %rax, 416(%rsp) leaq 88(%rsp), %rax movq %rax, 424(%rsp) leaq 48(%rsp), %rax movq %rax, 432(%rsp) leaq 40(%rsp), %rax movq %rax, 440(%rsp) leaq 104(%rsp), %rax movq %rax, 448(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 400(%rsp), %r9 movl $_Z13initial_coffefiPfS_S_S_i, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_67: # %.critedge movl $.Lstr, %edi callq puts@PLT movl $.Lstr.1, %edi callq puts@PLT callq clock movq %rax, 584(%rsp) # 8-byte Spill movl $.L.str.8, %edi movl $1, %esi xorl %eax, %eax callq printf movq 264(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 160(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 224(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 152(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 112(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 144(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 256(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 240(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 216(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 200(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 248(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 232(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 208(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 192(%rsp), %rdi movl $1120000, %edx # imm = 0x111700 xorl %esi, %esi callq hipMemset movq 184(%rsp), %rdi movl $1922400, %edx # imm = 0x1D5560 xorl %esi, %esi callq hipMemset movss .LCPI10_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, 120(%rsp) # 4-byte Spill leaq 400(%rsp), %r12 leaq 546(%r15), %rbp xorl %r15d, %r15d jmp .LBB10_68 .p2align 4, 0x90 .LBB10_81: # in Loop: Header=BB10_68 Depth=1 incl %r15d movss 120(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero addss .LCPI10_0(%rip), %xmm0 movss %xmm0, 120(%rsp) # 4-byte Spill cmpl $801, %r15d # imm = 0x321 je .LBB10_82 .LBB10_68: # =>This Inner Loop Header: Depth=1 testl %r15d, %r15d jne .LBB10_70 # %bb.69: # in Loop: Header=BB10_68 Depth=1 movl $.L.str.9, %edi movl $1, %esi movl %r15d, %edx xorl %eax, %eax callq printf .LBB10_70: # in Loop: Header=BB10_68 Depth=1 movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_72 # %bb.71: # in Loop: Header=BB10_68 Depth=1 movq 112(%rsp), %rax movq %rax, 96(%rsp) movq 144(%rsp), %rax movq %rax, 88(%rsp) movl $1092616192, 32(%rsp) # imm = 0x41200000 movl $1128792064, 24(%rsp) # imm = 0x43480000 movl $1124859904, 16(%rsp) # imm = 0x430C0000 movl $600, 8(%rsp) # imm = 0x258 movl $300, 104(%rsp) # imm = 0x12C movl $700, 176(%rsp) # imm = 0x2BC movl $400, 168(%rsp) # imm = 0x190 movl $973279855, 376(%rsp) # imm = 0x3A03126F movss 120(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, 368(%rsp) movl $1109393408, 140(%rsp) # imm = 0x42200000 movl $1, 136(%rsp) movl $50, 132(%rsp) movl $1, 128(%rsp) movl $0, 124(%rsp) leaq 32(%rsp), %rax movq %rax, 400(%rsp) leaq 24(%rsp), %rax movq %rax, 408(%rsp) leaq 16(%rsp), %rax movq %rax, 416(%rsp) leaq 8(%rsp), %rax movq %rax, 424(%rsp) leaq 104(%rsp), %rax movq %rax, 432(%rsp) leaq 176(%rsp), %rax movq %rax, 440(%rsp) leaq 168(%rsp), %rax movq %rax, 448(%rsp) leaq 376(%rsp), %rax movq %rax, 456(%rsp) leaq 368(%rsp), %rax movq %rax, 464(%rsp) leaq 140(%rsp), %rax movq %rax, 472(%rsp) leaq 136(%rsp), %rax movq %rax, 480(%rsp) leaq 132(%rsp), %rax movq %rax, 488(%rsp) leaq 128(%rsp), %rax movq %rax, 496(%rsp) leaq 124(%rsp), %rax movq %rax, 504(%rsp) leaq 96(%rsp), %rax movq %rax, 512(%rsp) leaq 88(%rsp), %rax movq %rax, 520(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d movl $_Z10add_sourcefffiiiifffiiiiPfS_, %edi movq %r12, %r9 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_72: # in Loop: Header=BB10_68 Depth=1 movq %rbp, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_74 # %bb.73: # in Loop: Header=BB10_68 Depth=1 movq 264(%rsp), %rax movq %rax, 96(%rsp) movq 224(%rsp), %rax movq %rax, 88(%rsp) movq 160(%rsp), %rax movq %rax, 48(%rsp) movq 152(%rsp), %rax movq %rax, 40(%rsp) movq 112(%rsp), %rax movq %rax, 32(%rsp) movq 144(%rsp), %rax movq %rax, 24(%rsp) movq 344(%rsp), %rax movq %rax, 16(%rsp) movq 336(%rsp), %rax movq %rax, 8(%rsp) movq 328(%rsp), %rax movq %rax, 104(%rsp) movq 320(%rsp), %rax movq %rax, 176(%rsp) movq 272(%rsp), %rax movq %rax, 168(%rsp) movl $600, 140(%rsp) # imm = 0x258 movl $300, 136(%rsp) # imm = 0x12C movl $700, 132(%rsp) # imm = 0x2BC movl $400, 128(%rsp) # imm = 0x190 movl $50, 124(%rsp) movl $973279855, 396(%rsp) # imm = 0x3A03126F movl $1084227584, 392(%rsp) # imm = 0x40A00000 movl $1084227584, 388(%rsp) # imm = 0x40A00000 leaq 140(%rsp), %rax movq %rax, 400(%rsp) leaq 136(%rsp), %rax movq %rax, 408(%rsp) leaq 132(%rsp), %rax movq %rax, 416(%rsp) leaq 128(%rsp), %rax movq %rax, 424(%rsp) leaq 124(%rsp), %rax movq %rax, 432(%rsp) leaq 396(%rsp), %rax movq %rax, 440(%rsp) leaq 392(%rsp), %rax movq %rax, 448(%rsp) leaq 388(%rsp), %rax movq %rax, 456(%rsp) leaq 96(%rsp), %rax movq %rax, 464(%rsp) leaq 88(%rsp), %rax movq %rax, 472(%rsp) leaq 48(%rsp), %rax movq %rax, 480(%rsp) leaq 40(%rsp), %rax movq %rax, 488(%rsp) leaq 32(%rsp), %rax movq %rax, 496(%rsp) leaq 24(%rsp), %rax movq %rax, 504(%rsp) leaq 16(%rsp), %rax movq %rax, 512(%rsp) leaq 8(%rsp), %rax movq %rax, 520(%rsp) leaq 104(%rsp), %rax movq %rax, 528(%rsp) leaq 176(%rsp), %rax movq %rax, 536(%rsp) leaq 168(%rsp), %rax movq %rax, 544(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 376(%rsp), %rdx leaq 368(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d movl $_Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_, %edi movq %r12, %r9 pushq 368(%rsp) .cfi_adjust_cfa_offset 8 pushq 384(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_74: # in Loop: Header=BB10_68 Depth=1 movq %rbp, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_76 # %bb.75: # in Loop: Header=BB10_68 Depth=1 movq 160(%rsp), %r8 movq 152(%rsp), %r9 movl $600, %edi # imm = 0x258 movl $300, %esi # imm = 0x12C movl $700, %edx # imm = 0x2BC movl $400, %ecx # imm = 0x190 movss .LCPI10_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movss .LCPI10_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero movaps %xmm1, %xmm2 pushq $0 .cfi_adjust_cfa_offset 8 pushq $1 .cfi_adjust_cfa_offset 8 pushq $140 .cfi_adjust_cfa_offset 8 pushq $0 .cfi_adjust_cfa_offset 8 pushq $200 .cfi_adjust_cfa_offset 8 pushq 312(%rsp) .cfi_adjust_cfa_offset 8 pushq 408(%rsp) .cfi_adjust_cfa_offset 8 pushq 408(%rsp) .cfi_adjust_cfa_offset 8 pushq 352(%rsp) .cfi_adjust_cfa_offset 8 pushq 368(%rsp) .cfi_adjust_cfa_offset 8 pushq 384(%rsp) .cfi_adjust_cfa_offset 8 pushq 400(%rsp) .cfi_adjust_cfa_offset 8 pushq 304(%rsp) .cfi_adjust_cfa_offset 8 pushq 296(%rsp) .cfi_adjust_cfa_offset 8 pushq 360(%rsp) .cfi_adjust_cfa_offset 8 pushq 352(%rsp) .cfi_adjust_cfa_offset 8 pushq 344(%rsp) .cfi_adjust_cfa_offset 8 pushq 336(%rsp) .cfi_adjust_cfa_offset 8 pushq 400(%rsp) .cfi_adjust_cfa_offset 8 pushq 392(%rsp) .cfi_adjust_cfa_offset 8 pushq $50 .cfi_adjust_cfa_offset 8 pushq 448(%rsp) .cfi_adjust_cfa_offset 8 pushq 320(%rsp) .cfi_adjust_cfa_offset 8 pushq 296(%rsp) .cfi_adjust_cfa_offset 8 callq _Z28__device_stub__update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib addq $192, %rsp .cfi_adjust_cfa_offset -192 .LBB10_76: # in Loop: Header=BB10_68 Depth=1 movq 160(%rsp), %rax movq %rax, 264(%rsp) movq 152(%rsp), %rax movq %rax, 224(%rsp) movq 240(%rsp), %rax movq %rax, 256(%rsp) movq 200(%rsp), %rax movq %rax, 216(%rsp) movq 232(%rsp), %rax movq %rax, 248(%rsp) movq 192(%rsp), %rax movq %rax, 208(%rsp) movq %r13, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_78 # %bb.77: # in Loop: Header=BB10_68 Depth=1 movq 112(%rsp), %rax movq 184(%rsp), %rcx movl $700, 32(%rsp) # imm = 0x2BC movl $400, 24(%rsp) # imm = 0x190 movl $600, 16(%rsp) # imm = 0x258 movl $300, 8(%rsp) # imm = 0x12C movl $50, 104(%rsp) movl %r15d, 176(%rsp) movl $801, 168(%rsp) # imm = 0x321 movq %rax, 96(%rsp) movq %rcx, 88(%rsp) leaq 32(%rsp), %rax movq %rax, 400(%rsp) leaq 24(%rsp), %rax movq %rax, 408(%rsp) leaq 16(%rsp), %rax movq %rax, 416(%rsp) leaq 8(%rsp), %rax movq %rax, 424(%rsp) leaq 104(%rsp), %rax movq %rax, 432(%rsp) leaq 176(%rsp), %rax movq %rax, 440(%rsp) leaq 168(%rsp), %rax movq %rax, 448(%rsp) leaq 96(%rsp), %rax movq %rax, 456(%rsp) leaq 88(%rsp), %rax movq %rax, 464(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d movl $_Z11shot_recordiiiiiiiPfS_, %edi movq %r12, %r9 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_78: # in Loop: Header=BB10_68 Depth=1 testl %r15d, %r15d je .LBB10_81 # %bb.79: # in Loop: Header=BB10_68 Depth=1 movl %r15d, %eax imulq $1374389535, %rax, %rax # imm = 0x51EB851F shrq $37, %rax imull $100, %eax, %eax cmpl %r15d, %eax jne .LBB10_81 # %bb.80: # in Loop: Header=BB10_68 Depth=1 movq 112(%rsp), %rsi movl $1120000, %edx # imm = 0x111700 movq %r14, %rdi movl $2, %ecx callq hipMemcpy movl $4, %esi movl $280000, %edx # imm = 0x445C0 movq %r14, %rdi movq 576(%rsp), %rcx # 8-byte Reload callq fwrite jmp .LBB10_81 .LBB10_82: movq 184(%rsp), %rsi movl $1922400, %edx # imm = 0x1D5560 movq 600(%rsp), %r15 # 8-byte Reload movq %r15, %rdi movl $2, %ecx callq hipMemcpy movq 592(%rsp), %r12 # 8-byte Reload movq %r12, %rdi xorl %esi, %esi xorl %edx, %edx callq fseek movl $4, %esi movl $480600, %edx # imm = 0x75558 movq %r15, %rdi movq %r12, %rcx callq fwrite callq clock movq %rax, %rbx movl $.Lstr.2, %edi callq puts@PLT movl $.Lstr.3, %edi callq puts@PLT subq 584(%rsp), %rbx # 8-byte Folded Reload xorps %xmm0, %xmm0 cvtsi2ss %rbx, %xmm0 divss .LCPI10_2(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movl $.L.str.12, %edi movl $1, %esi movb $1, %al callq printf movq 576(%rsp), %rdi # 8-byte Reload callq fclose movq %r12, %rdi callq fclose movq 344(%rsp), %rdi callq hipFree movq 336(%rsp), %rdi callq hipFree movq 328(%rsp), %rdi callq hipFree movq 320(%rsp), %rdi callq hipFree movq 312(%rsp), %rdi callq hipFree movq 304(%rsp), %rdi callq hipFree movq 296(%rsp), %rdi callq hipFree movq 288(%rsp), %rdi callq hipFree movq 264(%rsp), %rdi callq hipFree movq 160(%rsp), %rdi callq hipFree movq 224(%rsp), %rdi callq hipFree movq 152(%rsp), %rdi callq hipFree movq 112(%rsp), %rdi callq hipFree movq 144(%rsp), %rdi callq hipFree movq 256(%rsp), %rdi callq hipFree movq 240(%rsp), %rdi callq hipFree movq 216(%rsp), %rdi callq hipFree movq 200(%rsp), %rdi callq hipFree movq 248(%rsp), %rdi callq hipFree movq 232(%rsp), %rdi callq hipFree movq 208(%rsp), %rdi callq hipFree movq 192(%rsp), %rdi callq hipFree movq 184(%rsp), %rdi callq hipFree movq 280(%rsp), %rdi callq hipFree movq 360(%rsp), %rdi callq hipFree movq 352(%rsp), %rdi callq hipFree movq 272(%rsp), %rdi callq hipFree movq 568(%rsp), %rdi # 8-byte Reload callq free movq %r14, %rdi callq free movq 560(%rsp), %rdi # 8-byte Reload callq free movq 552(%rsp), %rdi # 8-byte Reload callq free movq %r15, %rdi callq free xorl %eax, %eax addq $1640, %rsp # imm = 0x668 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB10_57: .cfi_def_cfa_offset 1696 movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.4, %esi jmp .LBB10_58 .LBB10_60: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.5, %esi .LBB10_58: movq %rax, %rdx xorl %eax, %eax callq printf xorl %edi, %edi callq exit .Lfunc_end10: .size main, .Lfunc_end10-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB11_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB11_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10add_sourcefffiiiifffiiiiPfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6get_d0ffiiiPf, %esi movl $.L__unnamed_4, %edx movl $.L__unnamed_4, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13initial_coffefiPfS_S_S_i, %esi movl $.L__unnamed_5, %edx movl $.L__unnamed_5, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11shot_recordiiiiiiiPfS_, %esi movl $.L__unnamed_6, %edx movl $.L__unnamed_6, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15mute_directwaveiiffffiiiiPfS_S_S_i, %esi movl $.L__unnamed_7, %edx movl $.L__unnamed_7, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $0, 8(%rsp) movl $0, (%rsp) movl $d0, %esi movl $.L__unnamed_8, %edx movl $.L__unnamed_8, %ecx movl $4, %r9d movq %rbx, %rdi xorl %r8d, %r8d callq __hipRegisterVar movl $0, 8(%rsp) movl $1, (%rsp) movl $c, %esi movl $.L__unnamed_9, %edx movl $.L__unnamed_9, %ecx movl $16, %r9d movq %rbx, %rdi xorl %r8d, %r8d callq __hipRegisterVar movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end11: .size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB12_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB12_2: retq .Lfunc_end12: .size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor .cfi_endproc # -- End function .type d0,@object # @d0 .local d0 .comm d0,4,4 .type c,@object # @c .local c .comm c,16,16 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Cuda error: %s: %s\n" .size .L.str, 20 .type _Z10add_sourcefffiiiifffiiiiPfS_,@object # @_Z10add_sourcefffiiiifffiiiiPfS_ .section .rodata,"a",@progbits .globl _Z10add_sourcefffiiiifffiiiiPfS_ .p2align 3, 0x0 _Z10add_sourcefffiiiifffiiiiPfS_: .quad _Z25__device_stub__add_sourcefffiiiifffiiiiPfS_ .size _Z10add_sourcefffiiiifffiiiiPfS_, 8 .type _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_,@object # @_Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .globl _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .p2align 3, 0x0 _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_: .quad _Z25__device_stub__update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .size _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_, 8 .type _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib,@object # @_Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .globl _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .p2align 3, 0x0 _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib: .quad _Z28__device_stub__update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .size _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib, 8 .type _Z6get_d0ffiiiPf,@object # @_Z6get_d0ffiiiPf .globl _Z6get_d0ffiiiPf .p2align 3, 0x0 _Z6get_d0ffiiiPf: .quad _Z21__device_stub__get_d0ffiiiPf .size _Z6get_d0ffiiiPf, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "rb" .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "error open <%s>!\n" .size .L.str.2, 18 .type _Z13initial_coffefiPfS_S_S_i,@object # @_Z13initial_coffefiPfS_S_S_i .section .rodata,"a",@progbits .globl _Z13initial_coffefiPfS_S_S_i .p2align 3, 0x0 _Z13initial_coffefiPfS_S_S_i: .quad _Z28__device_stub__initial_coffefiPfS_S_S_i .size _Z13initial_coffefiPfS_S_S_i, 8 .type _Z11shot_recordiiiiiiiPfS_,@object # @_Z11shot_recordiiiiiiiPfS_ .globl _Z11shot_recordiiiiiiiPfS_ .p2align 3, 0x0 _Z11shot_recordiiiiiiiPfS_: .quad _Z26__device_stub__shot_recordiiiiiiiPfS_ .size _Z11shot_recordiiiiiiiPfS_, 8 .type _Z15mute_directwaveiiffffiiiiPfS_S_S_i,@object # @_Z15mute_directwaveiiffffiiiiPfS_S_S_i .globl _Z15mute_directwaveiiffffiiiiPfS_S_S_i .p2align 3, 0x0 _Z15mute_directwaveiiffffiiiiPfS_S_S_i: .quad _Z30__device_stub__mute_directwaveiiffffiiiiPfS_S_S_i .size _Z15mute_directwaveiiffffiiiiPfS_S_S_i, 8 .type .L__const.main.FN1,@object # @__const.main.FN1 .p2align 4, 0x0 .L__const.main.FN1: .asciz "thrust_vel_711_300.dat\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000" .size .L__const.main.FN1, 250 .type .L__const.main.FN2,@object # @__const.main.FN2 .p2align 4, 0x0 .L__const.main.FN2: .asciz "thrust_epsilon_711_300.dat\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000" .size .L__const.main.FN2, 250 .type .L__const.main.FN3,@object # @__const.main.FN3 .p2align 4, 0x0 .L__const.main.FN3: .asciz "thrust_delta_711_300.dat\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000" .size .L__const.main.FN3, 250 .type .L__const.main.FN4,@object # @__const.main.FN4 .p2align 4, 0x0 .L__const.main.FN4: .asciz "thrust_theta_711_300.dat\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000" .size .L__const.main.FN4, 250 .type .L__const.main.FN5,@object # @__const.main.FN5 .p2align 4, 0x0 .L__const.main.FN5: .asciz "thrust_shot_unstable.dat\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000" .size .L__const.main.FN5, 250 .type .L__const.main.FN6,@object # @__const.main.FN6 .p2align 4, 0x0 .L__const.main.FN6: .asciz "thrust_snap_unstable.dat\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000" .size .L__const.main.FN6, 250 .type .L.str.3,@object # @.str.3 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.3: .asciz "wb" .size .L.str.3, 3 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to initialize device!" .size .L.str.4, 29 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to allocate memory for variables!" .size .L.str.5, 41 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "--- IS=%3d \n" .size .L.str.8, 16 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "--- is===%d it===%d\n" .size .L.str.9, 25 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz "total %d shots: %f (s)\n" .size .L.str.12, 24 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z10add_sourcefffiiiifffiiiiPfS_" .size .L__unnamed_1, 33 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_" .size .L__unnamed_2, 45 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib" .size .L__unnamed_3, 71 .type .L__unnamed_4,@object # @3 .L__unnamed_4: .asciz "_Z6get_d0ffiiiPf" .size .L__unnamed_4, 17 .type .L__unnamed_5,@object # @4 .L__unnamed_5: .asciz "_Z13initial_coffefiPfS_S_S_i" .size .L__unnamed_5, 29 .type .L__unnamed_6,@object # @5 .L__unnamed_6: .asciz "_Z11shot_recordiiiiiiiPfS_" .size .L__unnamed_6, 27 .type .L__unnamed_7,@object # @6 .L__unnamed_7: .asciz "_Z15mute_directwaveiiffffiiiiPfS_S_S_i" .size .L__unnamed_7, 39 .type .L__unnamed_8,@object # @7 .L__unnamed_8: .asciz "d0" .size .L__unnamed_8, 3 .type .L__unnamed_9,@object # @8 .L__unnamed_9: .asciz "c" .size .L__unnamed_9, 2 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "--------------------------------------------------------" .size .Lstr, 57 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "--- " .size .Lstr.1, 7 .type .Lstr.2,@object # @str.2 .Lstr.2: .asciz "--- The forward is over " .size .Lstr.2, 30 .type .Lstr.3,@object # @str.3 .Lstr.3: .asciz "--- Complete!!!!!!!!! " .size .Lstr.3, 25 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__add_sourcefffiiiifffiiiiPfS_ .addrsig_sym _Z25__device_stub__update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .addrsig_sym _Z28__device_stub__update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .addrsig_sym _Z21__device_stub__get_d0ffiiiPf .addrsig_sym _Z28__device_stub__initial_coffefiPfS_S_S_i .addrsig_sym _Z26__device_stub__shot_recordiiiiiiiPfS_ .addrsig_sym _Z30__device_stub__mute_directwaveiiffffiiiiPfS_S_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym d0 .addrsig_sym c .addrsig_sym _Z10add_sourcefffiiiifffiiiiPfS_ .addrsig_sym _Z10update_veliiiiifffPfS_S_S_S_S_S_S_S_S_S_ .addrsig_sym _Z13update_stressiiiifffPfS_S_S_S_iS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiib .addrsig_sym _Z6get_d0ffiiiPf .addrsig_sym _Z13initial_coffefiPfS_S_S_i .addrsig_sym _Z11shot_recordiiiiiiiPfS_ .addrsig_sym _Z15mute_directwaveiiffffiiiiPfS_S_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z15my_first_kernelPf .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_TID.X ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R3, SR_CTAID.X ; I2F.U32 R5, R0 ; IMAD R2, R3, c[0x0][0x0], R0 ; IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; STG.E [R2.64], R5 ; EXIT ; BRA 0xa0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000f3fff_00000000-6_611cb18ae9d74125c2b2c416e874d30d89c3b879.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z35__device_stub__Z15my_first_kernelPfPf .type _Z35__device_stub__Z15my_first_kernelPfPf, @function _Z35__device_stub__Z15my_first_kernelPfPf: .LFB2082: .cfi_startproc endbr64 subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 8(%rsp) movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 88(%rsp), %rax subq %fs:40, %rax jne .L8 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 120 pushq 24(%rsp) .cfi_def_cfa_offset 128 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z15my_first_kernelPf(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 112 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z35__device_stub__Z15my_first_kernelPfPf, .-_Z35__device_stub__Z15my_first_kernelPfPf .globl _Z15my_first_kernelPf .type _Z15my_first_kernelPf, @function _Z15my_first_kernelPf: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z15my_first_kernelPfPf addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z15my_first_kernelPf, .-_Z15my_first_kernelPf .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "INFO: thread count, thread ID = %d %f \n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $48, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $64, %edi call malloc@PLT movq %rax, %rbp leaq 8(%rsp), %rdi movl $64, %esi call cudaMalloc@PLT movl $8, 28(%rsp) movl $1, 32(%rsp) movl $2, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L17 .L12: movl $2, %ecx movl $64, %edx movq 8(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT movl $0, %ebx leaq .LC0(%rip), %r12 .L13: pxor %xmm0, %xmm0 cvtss2sd 0(%rbp,%rbx,4), %xmm0 movl %ebx, %edx movq %r12, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $1, %rbx cmpq $16, %rbx jne .L13 movq 8(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call free@PLT call cudaDeviceReset@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L18 movl $0, %eax addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L17: .cfi_restore_state movq 8(%rsp), %rdi call _Z35__device_stub__Z15my_first_kernelPfPf jmp .L12 .L18: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "_Z15my_first_kernelPf" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z15my_first_kernelPf(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15my_first_kernelPf ; -- Begin function _Z15my_first_kernelPf .globl _Z15my_first_kernelPf .p2align 8 .type _Z15my_first_kernelPf,@function _Z15my_first_kernelPf: ; @_Z15my_first_kernelPf ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x14 s_load_b64 s[0:1], s[0:1], 0x0 v_cvt_f32_u32_e32 v3, v0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v0, vcc_lo, s0, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo global_store_b32 v[0:1], v3, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15my_first_kernelPf .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 264 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15my_first_kernelPf, .Lfunc_end0-_Z15my_first_kernelPf ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 100 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: hidden_block_count_x - .offset: 12 .size: 4 .value_kind: hidden_block_count_y - .offset: 16 .size: 4 .value_kind: hidden_block_count_z - .offset: 20 .size: 2 .value_kind: hidden_group_size_x - .offset: 22 .size: 2 .value_kind: hidden_group_size_y - .offset: 24 .size: 2 .value_kind: hidden_group_size_z - .offset: 26 .size: 2 .value_kind: hidden_remainder_x - .offset: 28 .size: 2 .value_kind: hidden_remainder_y - .offset: 30 .size: 2 .value_kind: hidden_remainder_z - .offset: 48 .size: 8 .value_kind: hidden_global_offset_x - .offset: 56 .size: 8 .value_kind: hidden_global_offset_y - .offset: 64 .size: 8 .value_kind: hidden_global_offset_z - .offset: 72 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 264 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15my_first_kernelPf .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15my_first_kernelPf.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "611cb18ae9d74125c2b2c416e874d30d89c3b879.hip" .globl _Z30__device_stub__my_first_kernelPf # -- Begin function _Z30__device_stub__my_first_kernelPf .p2align 4, 0x90 .type _Z30__device_stub__my_first_kernelPf,@function _Z30__device_stub__my_first_kernelPf: # @_Z30__device_stub__my_first_kernelPf .cfi_startproc # %bb.0: subq $72, %rsp .cfi_def_cfa_offset 80 movq %rdi, 64(%rsp) leaq 64(%rsp), %rax movq %rax, (%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d movq %rsp, %r9 movl $_Z15my_first_kernelPf, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $88, %rsp .cfi_adjust_cfa_offset -88 retq .Lfunc_end0: .size _Z30__device_stub__my_first_kernelPf, .Lfunc_end0-_Z30__device_stub__my_first_kernelPf .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $88, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movl $64, %edi callq malloc movq %rax, %rbx leaq 8(%rsp), %rdi movl $64, %esi callq hipMalloc movabsq $4294967298, %rdi # imm = 0x100000002 leaq 6(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 80(%rsp), %rax movq %rax, 16(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 16(%rsp), %r9 movl $_Z15my_first_kernelPf, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq 8(%rsp), %rsi movl $64, %edx movq %rbx, %rdi movl $2, %ecx callq hipMemcpy xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_3: # =>This Inner Loop Header: Depth=1 movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str, %edi movl %r14d, %esi movb $1, %al callq printf incq %r14 cmpq $16, %r14 jne .LBB1_3 # %bb.4: movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free callq hipDeviceReset xorl %eax, %eax addq $88, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15my_first_kernelPf, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z15my_first_kernelPf,@object # @_Z15my_first_kernelPf .section .rodata,"a",@progbits .globl _Z15my_first_kernelPf .p2align 3, 0x0 _Z15my_first_kernelPf: .quad _Z30__device_stub__my_first_kernelPf .size _Z15my_first_kernelPf, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "INFO: thread count, thread ID = %d %f \n" .size .L.str, 44 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15my_first_kernelPf" .size .L__unnamed_1, 22 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__my_first_kernelPf .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15my_first_kernelPf .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z13step_periodicPiS_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; ULDC.64 UR4, c[0x0][0x170] ; UIMAD UR4, UR5, UR4, URZ ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R0, UR4, PT ; @P0 EXIT ; IABS R3, c[0x0][0x170] ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IABS R10, R0 ; ULDC.64 UR4, c[0x0][0x118] ; I2F.RP R2, R3 ; ISETP.GE.AND P3, PT, R0, RZ, PT ; MUFU.RCP R2, R2 ; IADD3 R7, R2, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R7, R7 ; IMAD.MOV R4, RZ, RZ, -R7 ; IMAD R5, R4, R3, RZ ; IMAD.HI.U32 R6, R7, R5, R6 ; IABS R5, c[0x0][0x174] ; I2F.RP R7, R5 ; IMAD.HI.U32 R4, R6, R10, RZ ; IMAD.MOV R2, RZ, RZ, -R4 ; IMAD R2, R3, R2, R10 ; ISETP.GT.U32.AND P1, PT, R3, R2, PT ; MUFU.RCP R7, R7 ; @!P1 IMAD.IADD R2, R2, 0x1, -R3 ; @!P1 IADD3 R4, R4, 0x1, RZ ; ISETP.GE.U32.AND P0, PT, R2, R3, PT ; LOP3.LUT R2, R0, c[0x0][0x170], RZ, 0x3c, !PT ; IADD3 R8, R7, 0xffffffe, RZ ; ISETP.GE.AND P2, PT, R2, RZ, PT ; LOP3.LUT R2, RZ, c[0x0][0x170], RZ, 0x33, !PT ; @P0 IADD3 R4, R4, 0x1, RZ ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; SEL R4, R2, R4, !P0 ; IADD3 R11, R4, -0x1, RZ ; IABS R12, R11 ; ISETP.GE.AND P2, PT, R11, RZ, PT ; IADD3 R11, R4, 0x1, RZ ; IMAD.HI.U32 R9, R6, R12, RZ ; IMAD.MOV R13, RZ, RZ, -R9 ; F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; IMAD R12, R3, R13, R12 ; ISETP.GT.U32.AND P1, PT, R3, R12, PT ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; IMAD.MOV R14, RZ, RZ, -R9 ; @!P1 IMAD.IADD R12, R12, 0x1, -R3 ; IMAD R7, R14, R5, RZ ; ISETP.GT.U32.AND P1, PT, R3, R12, PT ; IMAD.HI.U32 R9, R9, R7, R8 ; IABS R8, R11 ; IMAD.HI.U32 R9, R9, R10, RZ ; IMAD.MOV R9, RZ, RZ, -R9 ; @!P1 IMAD.IADD R12, R12, 0x1, -R3 ; IMAD R10, R5.reuse, R9, R10 ; @!P2 IMAD.MOV R12, RZ, RZ, -R12 ; ISETP.NE.AND P2, PT, RZ, c[0x0][0x174], PT ; IMAD.HI.U32 R7, R6, R8, RZ ; ISETP.GT.U32.AND P1, PT, R5, R10, PT ; SEL R12, R2, R12, !P0 ; IMAD.MOV R7, RZ, RZ, -R7 ; IADD3 R12, R12, c[0x0][0x170], RZ ; IABS R9, R12 ; ISETP.GE.AND P6, PT, R12, RZ, PT ; @!P1 IMAD.IADD R10, R10, 0x1, -R5 ; IMAD.HI.U32 R6, R6, R9, RZ ; ISETP.GT.U32.AND P1, PT, R5, R10, PT ; IMAD.MOV R14, RZ, RZ, -R6 ; IMAD R6, R3.reuse, R7, R8 ; IMAD R8, R3, R14, R9 ; ISETP.GT.U32.AND P4, PT, R3.reuse, R6, PT ; ISETP.GT.U32.AND P5, PT, R3, R8, PT ; @!P1 IMAD.IADD R10, R10, 0x1, -R5 ; @!P3 IMAD.MOV R10, RZ, RZ, -R10 ; @!P2 LOP3.LUT R10, RZ, c[0x0][0x174], RZ, 0x33, !PT ; @!P4 IMAD.IADD R6, R6, 0x1, -R3.reuse ; ISETP.GE.AND P4, PT, R11, RZ, PT ; @!P5 IMAD.IADD R8, R8, 0x1, -R3 ; IADD3 R5, R10.reuse, 0x1, RZ ; ISETP.GT.U32.AND P1, PT, R3.reuse, R6, PT ; ISETP.GT.U32.AND P5, PT, R3, R8, PT ; ISETP.GE.AND P2, PT, R10, 0x1, PT ; ISETP.NE.AND P3, PT, R5, c[0x0][0x174], PT ; SEL R11, R10, c[0x0][0x174], P2 ; SEL R7, R5, RZ, P3 ; @!P1 IMAD.IADD R6, R6, 0x1, -R3.reuse ; @!P5 IMAD.IADD R8, R8, 0x1, -R3 ; IMAD.MOV.U32 R9, RZ, RZ, R6 ; IMAD R5, R4, c[0x0][0x174], R11 ; IMAD.MOV.U32 R11, RZ, RZ, R8 ; @!P4 IMAD.MOV R9, RZ, RZ, -R9 ; @!P6 IMAD.MOV R11, RZ, RZ, -R11 ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; SEL R9, R2, R9, !P0 ; IMAD R6, R4, c[0x0][0x174], R7 ; SEL R2, R2, R11, !P0 ; IADD3 R4, R5, -0x1, RZ ; IMAD.WIDE R6, R6, R3, c[0x0][0x168] ; IMAD R8, R9, c[0x0][0x174], R10.reuse ; IMAD R2, R2, c[0x0][0x174], R10 ; LDG.E R7, [R6.64] ; IMAD.WIDE R4, R4, R3, c[0x0][0x168] ; IMAD.WIDE R8, R8, R3.reuse, c[0x0][0x168] ; LDG.E R4, [R4.64] ; IMAD.WIDE R10, R2, R3, c[0x0][0x168] ; LDG.E R8, [R8.64] ; LDG.E R10, [R10.64] ; ISETP.NE.AND P0, PT, R7, 0xa, PT ; LOP3.LUT R2, R7, 0x2, RZ, 0xfc, !PT ; ISETP.EQ.OR P0, PT, R2, 0x6, !P0 ; LOP3.LUT R2, R4, 0x2, RZ, 0xfc, !PT ; ISETP.EQ.OR P0, PT, R7, 0xc, P0 ; LOP3.LUT R12, R8, 0x1, RZ, 0xfc, !PT ; IADD3 R6, R4, -0x9, RZ ; ISETP.NE.AND P3, PT, R10, 0x5, PT ; LOP3.LUT R9, R10, 0x4, RZ, 0xfc, !PT ; ISETP.NE.AND P1, PT, R2, 0x3, PT ; IADD3 R5, R8, -0x5, RZ ; ISETP.NE.AND P2, PT, R12, 0x3, PT ; ISETP.EQ.OR P0, PT, R7, 0x7, P0 ; ISETP.EQ.OR P3, PT, R9, 0xc, !P3 ; IADD3 R7, R7, -0xd, RZ ; ISETP.LT.U32.OR P1, PT, R6, 0x2, !P1 ; ISETP.LT.U32.OR P2, PT, R5, 0x3, !P2 ; ISETP.EQ.OR P3, PT, R10, 0x9, P3 ; ISETP.LT.U32.OR P0, PT, R7, 0x3, P0 ; ISETP.EQ.OR P1, PT, R4, 0x7, P1 ; ISETP.EQ.OR P2, PT, R8, 0xb, P2 ; IADD3 R10, R10, -0xd, RZ ; ISETP.EQ.OR P1, PT, R4, 0xb, P1 ; ISETP.EQ.OR P2, PT, R12, 0xf, P2 ; ISETP.LT.U32.OR P3, PT, R10, 0x2, P3 ; ISETP.EQ.OR P1, PT, R2, 0xf, P1 ; ISETP.EQ.OR P3, PT, R9, 0xf, P3 ; SEL R5, RZ, 0x1, !P1 ; @P0 SEL R5, R3, 0x5, !P1 ; IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; @P2 IADD3 R5, R5, 0x2, RZ ; @P3 IADD3 R5, R5, 0x8, RZ ; STG.E [R2.64], R5 ; EXIT ; BRA 0x900; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000c4b43_00000000-6_548ef0e2317565fde7ae34d065477dd9a56c013e.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "r" .LC1: .string "%d %d" .LC2: .string "%d " .text .globl _Z9readInputPKcPPiS1_S1_ .type _Z9readInputPKcPPiS1_S1_, @function _Z9readInputPKcPPiS1_S1_: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %rsi, %rbx movq %rdx, %r12 movq %rcx, %r13 leaq .LC0(%rip), %rsi call fopen@PLT movq %rax, %r14 movq %r13, %rcx movq %r12, %rdx leaq .LC1(%rip), %rsi movq %rax, %rdi movl $0, %eax call __isoc23_fscanf@PLT movl (%r12), %edi imull 0(%r13), %edi sall $2, %edi movslq %edi, %rdi salq $2, %rdi call malloc@PLT movq %rax, %rbp movl (%r12), %edi imull 0(%r13), %edi movslq %edi, %rdi salq $2, %rdi call malloc@PLT movq %rax, 16(%rsp) movq %rbp, %rsi movl $0, %ecx leaq .LC2(%rip), %r15 movq %rbp, 24(%rsp) movq %rbx, 32(%rsp) movq %rbp, 40(%rsp) .L4: movl 0(%r13), %eax imull (%r12), %eax movq %rsi, %rbp movl $0, %ebx testl %eax, %eax jle .L7 movl %ecx, 4(%rsp) movq %rsi, 8(%rsp) .L5: movq %rbp, %rdx movq %r15, %rsi movq %r14, %rdi movl $0, %eax call __isoc23_fscanf@PLT addl $1, %ebx addq $16, %rbp movl 0(%r13), %eax imull (%r12), %eax cmpl %ebx, %eax jg .L5 movl 4(%rsp), %ecx movq 8(%rsp), %rsi .L7: addl $1, %ecx addq $4, %rsi cmpl $4, %ecx jne .L4 movq 24(%rsp), %rax movq 32(%rsp), %rbx movq 40(%rsp), %rbp movl 0(%r13), %ecx imull (%r12), %ecx testl %ecx, %ecx jle .L8 movq 16(%rsp), %rdx movslq %ecx, %rcx salq $4, %rcx addq %rcx, %rbp .L9: movl 4(%rax), %esi movl (%rax), %ecx leal (%rcx,%rsi,2), %ecx movl 8(%rax), %esi leal (%rcx,%rsi,4), %ecx movl 12(%rax), %esi leal (%rcx,%rsi,8), %ecx movl %ecx, (%rdx) addq $16, %rax addq $4, %rdx cmpq %rbp, %rax jne .L9 .L8: movq 16(%rsp), %rax movq %rax, (%rbx) addq $56, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z9readInputPKcPPiS1_S1_, .-_Z9readInputPKcPPiS1_S1_ .section .rodata.str1.1 .LC3: .string "%i " .LC4: .string "\n" .text .globl _Z11printMatrixPiii .type _Z11printMatrixPiii, @function _Z11printMatrixPiii: .LFB2058: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 imull %edx, %esi testl %esi, %esi jle .L17 movq %rdi, %rbx movslq %esi, %rsi leaq (%rdi,%rsi,4), %r12 leaq .LC3(%rip), %rbp .L18: movl (%rbx), %edx movq %rbp, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %r12, %rbx jne .L18 .L17: leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z11printMatrixPiii, .-_Z11printMatrixPiii .globl _Z37__device_stub__Z13step_periodicPiS_iiPiS_ii .type _Z37__device_stub__Z13step_periodicPiS_iiPiS_ii, @function _Z37__device_stub__Z13step_periodicPiS_iiPiS_ii: .LFB2084: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L25 .L21: movq 136(%rsp), %rax subq %fs:40, %rax jne .L26 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L25: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z13step_periodicPiS_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L21 .L26: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z37__device_stub__Z13step_periodicPiS_iiPiS_ii, .-_Z37__device_stub__Z13step_periodicPiS_iiPiS_ii .globl _Z13step_periodicPiS_ii .type _Z13step_periodicPiS_ii, @function _Z13step_periodicPiS_ii: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z37__device_stub__Z13step_periodicPiS_iiPiS_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z13step_periodicPiS_ii, .-_Z13step_periodicPiS_ii .section .rodata.str1.1 .LC5: .string "../initial.txt" .text .globl main .type main, @function main: .LFB2059: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $64, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leaq 4(%rsp), %rcx movq %rsp, %rdx leaq 8(%rsp), %rsi leaq .LC5(%rip), %rdi call _Z9readInputPKcPPiS1_S1_ movl (%rsp), %eax imull 4(%rsp), %eax pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 mulss .LC6(%rip), %xmm0 movaps %xmm0, %xmm3 movss .LC10(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC7(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L30 cvttss2sil %xmm0, %edx pxor %xmm1, %xmm1 cvtsi2ssl %edx, %xmm1 cmpnless %xmm1, %xmm3 movss .LC9(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L30: cvttss2sil %xmm3, %ebp cltq leaq 0(,%rax,4), %rsi leaq 16(%rsp), %rdi call cudaMalloc@PLT movl (%rsp), %esi imull 4(%rsp), %esi movslq %esi, %rsi salq $2, %rsi leaq 24(%rsp), %rdi call cudaMalloc@PLT movq 8(%rsp), %r12 movl (%rsp), %edx imull 4(%rsp), %edx movslq %edx, %rdx salq $2, %rdx movl $1, %ecx movq %r12, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl (%rsp), %edx imull 4(%rsp), %edx movslq %edx, %rdx salq $2, %rdx movl $1, %ecx movq %r12, %rsi movq 24(%rsp), %rdi call cudaMemcpy@PLT movl $1000, %ebx jmp .L32 .L31: movl (%rsp), %edx imull 4(%rsp), %edx movslq %edx, %rdx salq $2, %rdx movl $3, %ecx movq 16(%rsp), %rsi movq 24(%rsp), %rdi call cudaMemcpy@PLT subl $1, %ebx je .L36 .L32: movl $256, 44(%rsp) movl $1, 48(%rsp) movl %ebp, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L31 movl 4(%rsp), %ecx movl (%rsp), %edx movq 24(%rsp), %rsi movq 16(%rsp), %rdi call _Z37__device_stub__Z13step_periodicPiS_iiPiS_ii jmp .L31 .L36: movl (%rsp), %edx imull 4(%rsp), %edx movslq %edx, %rdx salq $2, %rdx movl $2, %ecx movq 16(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L37 movl $0, %eax addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L37: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size main, .-main .section .rodata.str1.1 .LC11: .string "_Z13step_periodicPiS_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC11(%rip), %rdx movq %rdx, %rcx leaq _Z13step_periodicPiS_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC6: .long 998244352 .align 4 .LC7: .long 1258291200 .align 4 .LC9: .long 1065353216 .align 4 .LC10: .long 2147483647 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13step_periodicPiS_ii ; -- Begin function _Z13step_periodicPiS_ii .globl _Z13step_periodicPiS_ii .p2align 8 .type _Z13step_periodicPiS_ii,@function _Z13step_periodicPiS_ii: ; @_Z13step_periodicPiS_ii ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b64 s[4:5], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mul_i32 s2, s5, s4 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s2, v1 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_62 ; %bb.1: s_ashr_i32 s2, s5, 31 s_ashr_i32 s7, s4, 31 s_add_i32 s3, s5, s2 s_add_i32 s6, s4, s7 s_xor_b32 s3, s3, s2 s_xor_b32 s8, s6, s7 v_cvt_f32_u32_e32 v0, s3 v_cvt_f32_u32_e32 v2, s8 s_sub_i32 s2, 0, s3 s_sub_i32 s6, 0, s8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v0, v0 v_rcp_iflag_f32_e32 v2, v2 s_waitcnt_depctr 0xfff v_mul_f32_e32 v0, 0x4f7ffffe, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_cvt_u32_f32_e32 v3, v0 v_ashrrev_i32_e32 v0, 31, v1 v_mul_f32_e32 v2, 0x4f7ffffe, v2 v_mul_lo_u32 v4, s2, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v2, v2 v_mul_lo_u32 v5, s6, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v4, v3, v4 s_mov_b32 s6, 0 v_mul_hi_u32 v6, v2, v5 v_add_nc_u32_e32 v5, v1, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, v3, v4 v_xor_b32_e32 v5, v5, v0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v6, v2, v6 v_mad_u64_u32 v[3:4], null, v5, v7, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[2:3], null, v5, v6, 0 v_mul_lo_u32 v2, v4, s3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v4, v3, s8 v_sub_nc_u32_e32 v2, v5, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_sub_nc_u32_e32 v4, v5, v4 v_add_nc_u32_e32 v5, 1, v3 v_subrev_nc_u32_e32 v6, s3, v2 v_cmp_le_u32_e64 s2, s3, v2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cmp_le_u32_e32 vcc_lo, s8, v4 v_subrev_nc_u32_e32 v7, s8, v4 v_cndmask_b32_e64 v2, v2, v6, s2 v_cndmask_b32_e32 v3, v3, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v6, s3, v2 v_add_nc_u32_e32 v5, 1, v3 v_cndmask_b32_e32 v4, v4, v7, vcc_lo v_xor_b32_e32 v7, s7, v0 s_mov_b32 s7, exec_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_cmp_le_u32_e32 vcc_lo, s8, v4 v_cndmask_b32_e32 v3, v3, v5, vcc_lo v_cmp_le_u32_e32 vcc_lo, s3, v2 s_load_b64 s[2:3], s[0:1], 0x8 v_xor_b32_e32 v3, v3, v7 v_cndmask_b32_e32 v2, v2, v6, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v5, v3, v7 v_xor_b32_e32 v2, v2, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_sub_nc_u32_e32 v0, v2, v0 v_mul_lo_u32 v2, v5, s5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_i32_e32 vcc_lo, 1, v0 v_cndmask_b32_e64 v3, v0, s5, vcc_lo v_add3_u32 v3, v3, v2, -1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[3:4], 2, v[3:4] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s2, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo global_load_b32 v3, v[3:4], off ; implicit-def: $vgpr4 s_waitcnt vmcnt(0) v_cmpx_lt_i32_e32 8, v3 s_xor_b32 s7, exec_lo, s7 s_cbranch_execz .LBB0_11 ; %bb.2: ; %NodeBlock173 s_mov_b32 s8, 0 s_mov_b32 s6, exec_lo ; implicit-def: $vgpr4 v_cmpx_lt_i32_e32 12, v3 s_xor_b32 s6, exec_lo, s6 s_cbranch_execz .LBB0_8 ; %bb.3: ; %NodeBlock171 s_mov_b32 s9, exec_lo ; implicit-def: $sgpr10 v_cmpx_lt_i32_e32 14, v3 s_xor_b32 s9, exec_lo, s9 ; %bb.4: ; %LeafBlock169 v_cmp_ne_u32_e32 vcc_lo, 15, v3 s_mov_b32 s10, 1 ; implicit-def: $vgpr3 s_and_b32 s8, vcc_lo, exec_lo ; %bb.5: ; %Flow232 s_or_saveexec_b32 s9, s9 v_mov_b32_e32 v4, s10 s_xor_b32 exec_lo, exec_lo, s9 ; %bb.6: ; %LeafBlock167 v_cmp_ne_u32_e32 vcc_lo, 13, v3 v_mov_b32_e32 v4, 1 s_and_not1_b32 s8, s8, exec_lo s_and_b32 s10, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s8, s8, s10 ; %bb.7: ; %Flow233 s_or_b32 exec_lo, exec_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 s8, s8, exec_lo ; implicit-def: $vgpr3 .LBB0_8: ; %Flow231 s_and_not1_saveexec_b32 s6, s6 ; %bb.9: ; %LeafBlock165 v_cmp_lt_i32_e32 vcc_lo, 11, v3 v_mov_b32_e32 v4, 1 s_and_not1_b32 s8, s8, exec_lo s_and_b32 s9, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s8, s8, s9 ; %bb.10: ; %Flow234 s_or_b32 exec_lo, exec_lo, s6 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 s6, s8, exec_lo ; implicit-def: $vgpr3 .LBB0_11: ; %Flow230 s_and_not1_saveexec_b32 s7, s7 s_cbranch_execz .LBB0_21 ; %bb.12: ; %NodeBlock163 s_mov_b32 s9, s6 s_mov_b32 s8, exec_lo ; implicit-def: $vgpr4 v_cmpx_lt_i32_e32 2, v3 s_xor_b32 s8, exec_lo, s8 s_cbranch_execz .LBB0_18 ; %bb.13: ; %NodeBlock s_mov_b32 s9, s6 s_mov_b32 s10, exec_lo ; implicit-def: $sgpr11 v_cmpx_lt_i32_e32 6, v3 s_xor_b32 s10, exec_lo, s10 ; %bb.14: ; %LeafBlock161 v_cmp_ne_u32_e32 vcc_lo, 7, v3 s_and_not1_b32 s9, s6, exec_lo s_mov_b32 s11, 1 ; implicit-def: $vgpr3 s_and_b32 s12, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s9, s9, s12 ; %bb.15: ; %Flow237 s_or_saveexec_b32 s10, s10 v_mov_b32_e32 v4, s11 s_xor_b32 exec_lo, exec_lo, s10 ; %bb.16: ; %LeafBlock159 v_cmp_ne_u32_e32 vcc_lo, 3, v3 v_mov_b32_e32 v4, 1 s_and_not1_b32 s9, s9, exec_lo s_and_b32 s11, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s9, s9, s11 ; %bb.17: ; %Flow238 s_or_b32 exec_lo, exec_lo, s10 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_and_not1_b32 s10, s6, exec_lo s_and_b32 s9, s9, exec_lo ; implicit-def: $vgpr3 s_or_b32 s9, s10, s9 .LBB0_18: ; %Flow236 s_and_not1_saveexec_b32 s8, s8 ; %bb.19: ; %LeafBlock v_cmp_ne_u32_e32 vcc_lo, 1, v3 v_mov_b32_e32 v4, 1 s_and_not1_b32 s9, s9, exec_lo s_and_b32 s10, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s9, s9, s10 ; %bb.20: ; %Flow239 s_or_b32 exec_lo, exec_lo, s8 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_and_not1_b32 s6, s6, exec_lo s_and_b32 s8, s9, exec_lo s_or_b32 s6, s6, s8 .LBB0_21: ; %Flow235 s_or_b32 exec_lo, exec_lo, s7 s_and_saveexec_b32 s7, s6 ; %bb.22: v_mov_b32_e32 v4, 0 ; %bb.23: s_or_b32 exec_lo, exec_lo, s7 v_add_nc_u32_e32 v3, 1, v0 s_mov_b32 s6, 0 s_mov_b32 s7, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_ne_u32_e32 vcc_lo, s5, v3 v_cndmask_b32_e32 v3, 0, v3, vcc_lo v_add_nc_u32_e32 v2, v3, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[2:3], 2, v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_load_b32 v2, v[2:3], off s_waitcnt vmcnt(0) v_cmpx_lt_i32_e32 9, v2 s_xor_b32 s7, exec_lo, s7 s_cbranch_execz .LBB0_29 ; %bb.24: ; %NodeBlock187 s_mov_b32 s8, exec_lo v_cmpx_lt_i32_e32 11, v2 s_xor_b32 s8, exec_lo, s8 ; %bb.25: ; %LeafBlock185 v_cmp_gt_i32_e32 vcc_lo, 16, v2 ; implicit-def: $vgpr2 s_and_b32 s6, vcc_lo, exec_lo ; %bb.26: ; %Flow225 s_and_not1_saveexec_b32 s8, s8 ; %bb.27: ; %LeafBlock183 v_cmp_eq_u32_e32 vcc_lo, 10, v2 s_and_not1_b32 s6, s6, exec_lo s_and_b32 s9, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s6, s6, s9 ; %bb.28: ; %Flow226 s_or_b32 exec_lo, exec_lo, s8 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 s6, s6, exec_lo ; implicit-def: $vgpr2 .LBB0_29: ; %Flow224 s_and_not1_saveexec_b32 s7, s7 s_cbranch_execz .LBB0_35 ; %bb.30: ; %NodeBlock181 s_mov_b32 s8, s6 s_mov_b32 s9, exec_lo v_cmpx_lt_i32_e32 5, v2 s_xor_b32 s9, exec_lo, s9 ; %bb.31: ; %LeafBlock179 v_cmp_gt_i32_e32 vcc_lo, 8, v2 s_and_not1_b32 s8, s6, exec_lo ; implicit-def: $vgpr2 s_and_b32 s10, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s8, s8, s10 ; %bb.32: ; %Flow228 s_and_not1_saveexec_b32 s9, s9 ; %bb.33: ; %LeafBlock177 v_cmp_eq_u32_e32 vcc_lo, 4, v2 s_and_not1_b32 s8, s8, exec_lo s_and_b32 s10, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s8, s8, s10 ; %bb.34: ; %Flow229 s_or_b32 exec_lo, exec_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_and_not1_b32 s6, s6, exec_lo s_and_b32 s8, s8, exec_lo s_or_b32 s6, s6, s8 .LBB0_35: ; %Flow227 s_or_b32 exec_lo, exec_lo, s7 s_and_saveexec_b32 s7, s6 ; %bb.36: v_or_b32_e32 v4, 4, v4 ; %bb.37: s_or_b32 exec_lo, exec_lo, s7 s_ashr_i32 s6, s4, 31 v_add_nc_u32_e32 v3, 1, v5 s_add_i32 s7, s4, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_xor_b32 s7, s7, s6 v_cvt_f32_u32_e32 v2, s7 s_sub_i32 s6, 0, s7 v_ashrrev_i32_e32 v6, 31, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v2, v2 v_add_nc_u32_e32 v3, v3, v6 s_waitcnt_depctr 0xfff v_mul_f32_e32 v2, 0x4f7ffffe, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v2, v2 v_mul_lo_u32 v7, s6, v2 s_mov_b32 s6, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v8, v2, v7 v_xor_b32_e32 v7, v3, v6 v_add_nc_u32_e32 v8, v2, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, v8, 0 v_mul_lo_u32 v2, v3, s7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v2, v7, v2 v_subrev_nc_u32_e32 v3, s7, v2 v_cmp_le_u32_e32 vcc_lo, s7, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v2, v2, v3, vcc_lo v_subrev_nc_u32_e32 v3, s7, v2 v_cmp_le_u32_e32 vcc_lo, s7, v2 s_mov_b32 s7, exec_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v2, v2, v3, vcc_lo v_xor_b32_e32 v2, v2, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v6, v2, v6 v_mad_u64_u32 v[2:3], null, v6, s5, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[2:3], 2, v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_load_b32 v2, v[2:3], off s_waitcnt vmcnt(0) v_cmpx_lt_i32_e32 10, v2 s_xor_b32 s7, exec_lo, s7 s_cbranch_execz .LBB0_43 ; %bb.38: ; %NodeBlock201 s_mov_b32 s8, exec_lo v_cmpx_lt_i32_e32 13, v2 s_xor_b32 s8, exec_lo, s8 ; %bb.39: ; %LeafBlock199 v_cmp_gt_i32_e32 vcc_lo, 16, v2 ; implicit-def: $vgpr2 s_and_b32 s6, vcc_lo, exec_lo ; %bb.40: ; %Flow219 s_and_not1_saveexec_b32 s8, s8 ; %bb.41: ; %LeafBlock197 v_cmp_eq_u32_e32 vcc_lo, 11, v2 s_and_not1_b32 s6, s6, exec_lo s_and_b32 s9, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s6, s6, s9 ; %bb.42: ; %Flow220 s_or_b32 exec_lo, exec_lo, s8 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 s6, s6, exec_lo ; implicit-def: $vgpr2 .LBB0_43: ; %Flow218 s_and_not1_saveexec_b32 s7, s7 s_cbranch_execz .LBB0_49 ; %bb.44: ; %NodeBlock195 s_mov_b32 s8, s6 s_mov_b32 s9, exec_lo v_cmpx_lt_i32_e32 4, v2 s_xor_b32 s9, exec_lo, s9 ; %bb.45: ; %LeafBlock193 v_cmp_gt_i32_e32 vcc_lo, 8, v2 s_and_not1_b32 s8, s6, exec_lo ; implicit-def: $vgpr2 s_and_b32 s10, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s8, s8, s10 ; %bb.46: ; %Flow222 s_and_not1_saveexec_b32 s9, s9 ; %bb.47: ; %LeafBlock191 v_add_nc_u32_e32 v2, -2, v2 s_and_not1_b32 s8, s8, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, 2, v2 s_and_b32 s10, vcc_lo, exec_lo s_or_b32 s8, s8, s10 ; %bb.48: ; %Flow223 s_or_b32 exec_lo, exec_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_and_not1_b32 s6, s6, exec_lo s_and_b32 s8, s8, exec_lo s_or_b32 s6, s6, s8 .LBB0_49: ; %Flow221 s_or_b32 exec_lo, exec_lo, s7 s_and_saveexec_b32 s7, s6 ; %bb.50: v_add_nc_u32_e32 v4, 2, v4 ; %bb.51: s_or_b32 exec_lo, exec_lo, s7 s_ashr_i32 s6, s4, 31 v_add_nc_u32_e32 v3, -1, v5 s_add_i32 s7, s4, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_xor_b32 s6, s7, s6 v_cvt_f32_u32_e32 v2, s6 s_sub_i32 s7, 0, s6 v_ashrrev_i32_e32 v6, 31, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v2, v2 v_add_nc_u32_e32 v3, v3, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_xor_b32_e32 v3, v3, v6 s_waitcnt_depctr 0xfff v_mul_f32_e32 v2, 0x4f7ffffe, v2 v_cvt_u32_f32_e32 v2, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v5, s7, v2 v_mul_hi_u32 v5, v2, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v7, v2, v5 v_mul_hi_u32 v2, v3, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, v2, s6 v_sub_nc_u32_e32 v2, v3, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v3, s6, v2 v_cmp_le_u32_e32 vcc_lo, s6, v2 v_cndmask_b32_e32 v2, v2, v3, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v3, s6, v2 v_cmp_le_u32_e32 vcc_lo, s6, v2 v_cndmask_b32_e32 v2, v2, v3, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v2, v2, v6 v_sub_nc_u32_e32 v2, v2, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, s4, v2 s_mov_b32 s4, 0 v_ashrrev_i32_e32 v5, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, v2, v5 v_xor_b32_e32 v6, v2, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v6, v7, 0 v_mul_lo_u32 v2, v3, s6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v2, v6, v2 v_subrev_nc_u32_e32 v3, s6, v2 v_cmp_le_u32_e32 vcc_lo, s6, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v2, v2, v3, vcc_lo v_subrev_nc_u32_e32 v3, s6, v2 v_cmp_le_u32_e32 vcc_lo, s6, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v2, v2, v3, vcc_lo v_xor_b32_e32 v2, v2, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v5, v2, v5 v_mad_u64_u32 v[2:3], null, v5, s5, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[2:3], 2, v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo s_mov_b32 s2, exec_lo global_load_b32 v0, v[2:3], off s_waitcnt vmcnt(0) v_cmpx_lt_i32_e32 7, v0 s_xor_b32 s2, exec_lo, s2 s_cbranch_execz .LBB0_57 ; %bb.52: ; %NodeBlock211 s_mov_b32 s3, 0 s_mov_b32 s4, exec_lo v_cmpx_lt_i32_e32 10, v0 s_xor_b32 s4, exec_lo, s4 ; %bb.53: ; %LeafBlock209 v_cmp_gt_i32_e32 vcc_lo, 16, v0 ; implicit-def: $vgpr0 s_and_b32 s3, vcc_lo, exec_lo ; %bb.54: ; %Flow215 s_and_not1_saveexec_b32 s4, s4 ; %bb.55: ; %LeafBlock207 v_cmp_gt_i32_e32 vcc_lo, 10, v0 s_and_not1_b32 s3, s3, exec_lo s_and_b32 s5, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s3, s3, s5 ; %bb.56: ; %Flow216 s_or_b32 exec_lo, exec_lo, s4 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 s4, s3, exec_lo ; implicit-def: $vgpr0 .LBB0_57: ; %Flow s_and_not1_saveexec_b32 s2, s2 ; %bb.58: ; %LeafBlock205 v_cmp_eq_u32_e32 vcc_lo, 5, v0 s_and_not1_b32 s3, s4, exec_lo s_and_b32 s4, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s4, s3, s4 ; %bb.59: ; %Flow217 s_or_b32 exec_lo, exec_lo, s2 s_and_saveexec_b32 s2, s4 ; %bb.60: v_add_nc_u32_e32 v4, 8, v4 ; %bb.61: s_or_b32 exec_lo, exec_lo, s2 s_load_b64 s[0:1], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v4, off .LBB0_62: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13step_periodicPiS_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13step_periodicPiS_ii, .Lfunc_end0-_Z13step_periodicPiS_ii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1940 ; NumSgprs: 18 ; NumVgprs: 9 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 9 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13step_periodicPiS_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13step_periodicPiS_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "548ef0e2317565fde7ae34d065477dd9a56c013e.hip" .globl _Z9readInputPKcPPiS1_S1_ # -- Begin function _Z9readInputPKcPPiS1_S1_ .p2align 4, 0x90 .type _Z9readInputPKcPPiS1_S1_,@function _Z9readInputPKcPPiS1_S1_: # @_Z9readInputPKcPPiS1_S1_ .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rcx, %r14 movq %rdx, %r12 movq %rsi, 16(%rsp) # 8-byte Spill movl $.L.str, %esi callq fopen movq %rax, %rbp movl $.L.str.1, %esi movq %rax, %rdi movq %r12, %rdx movq %r14, %rcx xorl %eax, %eax callq __isoc23_fscanf movslq (%r12), %rax movslq (%r14), %rbx imulq %rax, %rbx movq %rbx, %rdi shlq $4, %rdi callq malloc movq %rax, %r15 movslq %ebx, %rdi shlq $2, %rdi callq malloc movq %rax, 8(%rsp) # 8-byte Spill movl $0, 4(%rsp) # 4-byte Folded Spill jmp .LBB0_1 .p2align 4, 0x90 .LBB0_4: # %._crit_edge # in Loop: Header=BB0_1 Depth=1 movl 4(%rsp), %eax # 4-byte Reload incl %eax movl %eax, 4(%rsp) # 4-byte Spill cmpl $4, %eax je .LBB0_5 .LBB0_1: # %.preheader39 # =>This Loop Header: Depth=1 # Child Loop BB0_3 Depth 2 movl (%r12), %eax imull (%r14), %eax testl %eax, %eax jle .LBB0_4 # %bb.2: # %.lr.ph.preheader # in Loop: Header=BB0_1 Depth=1 xorl %r13d, %r13d movl 4(%rsp), %ebx # 4-byte Reload .p2align 4, 0x90 .LBB0_3: # %.lr.ph # Parent Loop BB0_1 Depth=1 # => This Inner Loop Header: Depth=2 movl %ebx, %eax leaq (%r15,%rax,4), %rdx movl $.L.str.2, %esi movq %rbp, %rdi xorl %eax, %eax callq __isoc23_fscanf incl %r13d movl (%r12), %eax imull (%r14), %eax addl $4, %ebx cmpl %eax, %r13d jl .LBB0_3 jmp .LBB0_4 .LBB0_5: # %.preheader movl (%r12), %eax imull (%r14), %eax testl %eax, %eax movq 8(%rsp), %rdi # 8-byte Reload jle .LBB0_8 # %bb.6: # %.lr.ph45.preheader movl %eax, %eax shlq $2, %rax xorl %ecx, %ecx .p2align 4, 0x90 .LBB0_7: # %.lr.ph45 # =>This Inner Loop Header: Depth=1 movl 4(%r15,%rcx,4), %edx movl 8(%r15,%rcx,4), %esi addl %edx, %edx addl (%r15,%rcx,4), %edx leal (%rdx,%rsi,4), %edx movl 12(%r15,%rcx,4), %esi leal (%rdx,%rsi,8), %edx movl %edx, (%rdi,%rcx) addq $4, %rcx cmpq %rcx, %rax jne .LBB0_7 .LBB0_8: # %._crit_edge46 movq 16(%rsp), %rax # 8-byte Reload movq %rdi, (%rax) addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z9readInputPKcPPiS1_S1_, .Lfunc_end0-_Z9readInputPKcPPiS1_S1_ .cfi_endproc # -- End function .globl _Z11printMatrixPiii # -- Begin function _Z11printMatrixPiii .p2align 4, 0x90 .type _Z11printMatrixPiii,@function _Z11printMatrixPiii: # @_Z11printMatrixPiii .cfi_startproc # %bb.0: imull %edx, %esi testl %esi, %esi jle .LBB1_4 # %bb.1: # %.lr.ph.preheader pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx movl %esi, %r14d xorl %r15d, %r15d .p2align 4, 0x90 .LBB1_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movl (%rbx,%r15,4), %esi movl $.L.str.3, %edi xorl %eax, %eax callq printf incq %r15 cmpq %r15, %r14 jne .LBB1_2 # %bb.3: popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 .cfi_restore %rbx .cfi_restore %r14 .cfi_restore %r15 .LBB1_4: # %._crit_edge movl $10, %edi jmp putchar@PLT # TAILCALL .Lfunc_end1: .size _Z11printMatrixPiii, .Lfunc_end1-_Z11printMatrixPiii .cfi_endproc # -- End function .globl _Z28__device_stub__step_periodicPiS_ii # -- Begin function _Z28__device_stub__step_periodicPiS_ii .p2align 4, 0x90 .type _Z28__device_stub__step_periodicPiS_ii,@function _Z28__device_stub__step_periodicPiS_ii: # @_Z28__device_stub__step_periodicPiS_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z13step_periodicPiS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end2: .size _Z28__device_stub__step_periodicPiS_ii, .Lfunc_end2-_Z28__device_stub__step_periodicPiS_ii .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI3_0: .long 0x3b800000 # float 0.00390625 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $152, %rsp .cfi_def_cfa_offset 208 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movabsq $4294967296, %rbx # imm = 0x100000000 leaq 40(%rsp), %rsi leaq 4(%rsp), %rdx movq %rsp, %rcx movl $.L.str.5, %edi callq _Z9readInputPKcPPiS1_S1_ movslq 4(%rsp), %rax movslq (%rsp), %r15 imulq %rax, %r15 cvtsi2ss %r15d, %xmm0 mulss .LCPI3_0(%rip), %xmm0 callq ceilf@PLT cvttss2si %xmm0, %r14d shlq $2, %r15 leaq 8(%rsp), %rdi movq %r15, %rsi callq hipMalloc movslq 4(%rsp), %rax movslq (%rsp), %rsi imulq %rax, %rsi shlq $2, %rsi leaq 16(%rsp), %rdi callq hipMalloc movq 8(%rsp), %rdi movq 40(%rsp), %r15 movslq 4(%rsp), %rax movslq (%rsp), %rdx imulq %rax, %rdx shlq $2, %rdx movq %r15, %rsi movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi movslq 4(%rsp), %rax movslq (%rsp), %rdx imulq %rax, %rdx shlq $2, %rdx movq %r15, 32(%rsp) # 8-byte Spill movq %r15, %rsi movl $1, %ecx callq hipMemcpy orq %rbx, %r14 movl $1000, %r13d # imm = 0x3E8 addq $256, %rbx # imm = 0x100 leaq 56(%rsp), %rbp leaq 48(%rsp), %r15 leaq 112(%rsp), %r12 jmp .LBB3_1 .p2align 4, 0x90 .LBB3_3: # in Loop: Header=BB3_1 Depth=1 movq 16(%rsp), %rdi movq 8(%rsp), %rsi movslq 4(%rsp), %rax movslq (%rsp), %rdx imulq %rax, %rdx shlq $2, %rdx movl $3, %ecx callq hipMemcpy decl %r13d je .LBB3_4 .LBB3_1: # =>This Inner Loop Header: Depth=1 movq %r14, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_3 # %bb.2: # in Loop: Header=BB3_1 Depth=1 movq 8(%rsp), %rax movq 16(%rsp), %rcx movl 4(%rsp), %edx movl (%rsp), %esi movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movl %edx, 28(%rsp) movl %esi, 24(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 28(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 80(%rsp), %rdi leaq 64(%rsp), %rsi movq %rbp, %rdx movq %r15, %rcx callq __hipPopCallConfiguration movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 64(%rsp), %rcx movl 72(%rsp), %r8d movl $_Z13step_periodicPiS_ii, %edi movq %r12, %r9 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 jmp .LBB3_3 .LBB3_4: movq 8(%rsp), %rsi movslq 4(%rsp), %rax movslq (%rsp), %rdx imulq %rax, %rdx shlq $2, %rdx movq 32(%rsp), %rdi # 8-byte Reload movl $2, %ecx callq hipMemcpy movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree xorl %eax, %eax addq $152, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13step_periodicPiS_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "r" .size .L.str, 2 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "%d %d" .size .L.str.1, 6 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "%d " .size .L.str.2, 4 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "%i " .size .L.str.3, 4 .type _Z13step_periodicPiS_ii,@object # @_Z13step_periodicPiS_ii .section .rodata,"a",@progbits .globl _Z13step_periodicPiS_ii .p2align 3, 0x0 _Z13step_periodicPiS_ii: .quad _Z28__device_stub__step_periodicPiS_ii .size _Z13step_periodicPiS_ii, 8 .type .L.str.5,@object # @.str.5 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.5: .asciz "../initial.txt" .size .L.str.5, 15 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z13step_periodicPiS_ii" .size .L__unnamed_1, 24 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__step_periodicPiS_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13step_periodicPiS_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z29test_restrict_self_assignmentPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; MOV R2, c[0x0][0x168] ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E.CONSTANT R3, [R2.64] ; MOV R4, c[0x0][0x160] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; STG.E [R4.64], R3 ; EXIT ; BRA 0x90; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z17test_restrict_sumPiS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; HFMA2.MMA R11, -RZ, RZ, 0, 3.5762786865234375e-07 ; IMAD.MOV.U32 R9, RZ, RZ, 0x5 ; MOV R2, c[0x0][0x160] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; MOV R4, c[0x0][0x168] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; MOV R6, c[0x0][0x170] ; IMAD.MOV.U32 R13, RZ, RZ, 0xb ; MOV R7, c[0x0][0x174] ; ULDC.64 UR4, c[0x0][0x118] ; STG.E [R2.64], R9 ; STG.E [R4.64], R11 ; STG.E [R6.64], R13 ; EXIT ; BRA 0xf0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z31test_restrict_builtin_var_writePiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R2, SR_TID.X ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; MOV R5, 0x2a ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; STG.E [R2.64], R5 ; EXIT ; BRA 0x80; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z30test_restrict_builtin_var_readPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R5, RZ, RZ, 0x2a ; MOV R2, c[0x0][0x160] ; ULDC.64 UR4, c[0x0][0x118] ; MOV R3, c[0x0][0x164] ; STG.E [R2.64+0xc], R5 ; EXIT ; BRA 0x70; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z37test_restrict_read_in_while_conditionPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R7, RZ, RZ, 0x2a ; MOV R2, c[0x0][0x160] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; MOV R4, c[0x0][0x168] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; ULDC.64 UR6, c[0x0][0x118] ; STG.E [R2.64+0xc], R7 ; ULDC.64 UR4, c[0x0][0x168] ; LDG.E R4, [R4.64+0xc] ; UIADD3 UR4, UP0, UR4, 0xc, URZ ; UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; ISETP.NE.AND P0, PT, R4, 0x2a, PT ; @P0 EXIT ; MOV R2, UR4 ; MOV R3, UR5 ; STG.E [R2.64], RZ ; EXIT ; BRA 0x120; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z29test_restrict_writes_in_whilePiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R5, RZ, RZ, 0x2a ; MOV R2, c[0x0][0x168] ; ULDC.64 UR4, c[0x0][0x118] ; MOV R3, c[0x0][0x16c] ; STG.E [R2.64+0x4], R5 ; STG.E [R2.64+0x8], R5 ; STG.E [R2.64+0xc], R5 ; STG.E [R2.64+0x10], R5 ; EXIT ; BRA 0xa0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z27test_restrict_writes_in_forPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R5, RZ, RZ, 0x2a ; MOV R2, c[0x0][0x168] ; ULDC.64 UR4, c[0x0][0x118] ; MOV R3, c[0x0][0x16c] ; STG.E [R2.64+0x4], R5 ; STG.E [R2.64+0x8], R5 ; STG.E [R2.64+0xc], R5 ; STG.E [R2.64+0x10], R5 ; EXIT ; BRA 0xa0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z32test_restrict_conditional_writesPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R5, RZ, RZ, 0x2a ; MOV R2, c[0x0][0x168] ; ULDC.64 UR4, c[0x0][0x118] ; MOV R3, c[0x0][0x16c] ; STG.E [R2.64+0x8], R5 ; STG.E [R2.64+0xc], R5 ; EXIT ; BRA 0x80; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z23test_restrict_no_writesPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; EXIT ; BRA 0x20; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z31test_restrict_read_in_conditionPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R5, RZ, RZ, 0x2a ; MOV R2, c[0x0][0x160] ; ULDC.64 UR4, c[0x0][0x118] ; MOV R3, c[0x0][0x164] ; STG.E [R2.64+0xc], R5 ; EXIT ; BRA 0x70; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z28test_restrict_reads_in_whilePiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R5, RZ, RZ, 0x2a ; MOV R2, c[0x0][0x160] ; ULDC.64 UR4, c[0x0][0x118] ; MOV R3, c[0x0][0x164] ; STG.E [R2.64+0xc], R5 ; EXIT ; BRA 0x70; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z26test_restrict_reads_in_forPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R5, RZ, RZ, 0x2a ; MOV R2, c[0x0][0x160] ; ULDC.64 UR4, c[0x0][0x118] ; MOV R3, c[0x0][0x164] ; STG.E [R2.64+0xc], R5 ; EXIT ; BRA 0x70; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z31test_restrict_conditional_readsPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; HFMA2.MMA R5, -RZ, RZ, 0, 2.50339508056640625e-06 ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; MOV R3, c[0x0][0x164] ; IMAD.MOV.U32 R7, RZ, RZ, 0x5 ; ULDC.64 UR4, c[0x0][0x118] ; STG.E [R2.64+0xc], R5 ; STG.E [R2.64], R7 ; EXIT ; BRA 0x90; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z22test_restrict_no_readsPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; HFMA2.MMA R5, -RZ, RZ, 0, 2.50339508056640625e-06 ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; MOV R3, c[0x0][0x164] ; IMAD.MOV.U32 R7, RZ, RZ, 0x5 ; ULDC.64 UR4, c[0x0][0x118] ; STG.E [R2.64+0xc], R5 ; STG.E [R2.64], R7 ; EXIT ; BRA 0x90; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z26test_no_restrict_violationPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; ISETP.GE.AND P0, PT, R0, 0x1, PT ; @!P0 EXIT ; IADD3 R2, R0.reuse, -0x1, RZ ; UMOV UR4, URZ ; LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; ULDC.64 UR12, c[0x0][0x118] ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; @!P0 BRA 0xaf0 ; IADD3 R8, -R0, c[0x0][0x178], RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; MOV R5, c[0x0][0x164] ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; ISETP.GT.AND P0, PT, R8, RZ, PT ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; MOV R7, c[0x0][0x16c] ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; @!P0 BRA 0x930 ; ISETP.GT.AND P1, PT, R8, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x640 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E.CONSTANT R13, [R2.64] ; LDG.E.CONSTANT R14, [R6.64] ; LDG.E.CONSTANT R15, [R2.64+0x4] ; LDG.E.CONSTANT R16, [R6.64+0x4] ; LDG.E.CONSTANT R17, [R2.64+0x8] ; LDG.E.CONSTANT R18, [R6.64+0x8] ; LDG.E.CONSTANT R21, [R2.64+0x10] ; LDG.E.CONSTANT R22, [R6.64+0x10] ; LDG.E.CONSTANT R9, [R2.64+0x1c] ; LDG.E.CONSTANT R10, [R6.64+0x1c] ; LDG.E.CONSTANT R19, [R2.64+0xc] ; LDG.E.CONSTANT R20, [R6.64+0xc] ; LDG.E.CONSTANT R23, [R2.64+0x14] ; LDG.E.CONSTANT R24, [R6.64+0x14] ; LDG.E.CONSTANT R11, [R2.64+0x18] ; LDG.E.CONSTANT R12, [R6.64+0x18] ; LDG.E.CONSTANT R27, [R6.64+0x20] ; LDG.E.CONSTANT R29, [R6.64+0x24] ; LDG.E.CONSTANT R26, [R2.64+0x2c] ; IMAD.IADD R13, R13, 0x1, R14 ; LDG.E.CONSTANT R14, [R2.64+0x3c] ; IMAD.IADD R15, R15, 0x1, R16 ; STG.E [R4.64], R13 ; IMAD.IADD R17, R17, 0x1, R18 ; STG.E [R4.64+0x4], R15 ; LDG.E.CONSTANT R13, [R2.64+0x38] ; IMAD.IADD R21, R21, 0x1, R22 ; STG.E [R4.64+0x8], R17 ; STG.E [R4.64+0x10], R21 ; IADD3 R25, R9, R10, RZ ; LDG.E.CONSTANT R18, [R2.64+0x20] ; LDG.E.CONSTANT R10, [R6.64+0x38] ; IADD3 R19, R19, R20, RZ ; LDG.E.CONSTANT R22, [R2.64+0x28] ; LDG.E.CONSTANT R20, [R2.64+0x24] ; IMAD.IADD R23, R23, 0x1, R24 ; LDG.E.CONSTANT R21, [R6.64+0x2c] ; LDG.E.CONSTANT R24, [R6.64+0x28] ; IMAD.IADD R11, R11, 0x1, R12 ; LDG.E.CONSTANT R16, [R2.64+0x30] ; LDG.E.CONSTANT R17, [R6.64+0x30] ; LDG.E.CONSTANT R15, [R2.64+0x34] ; LDG.E.CONSTANT R12, [R6.64+0x34] ; LDG.E.CONSTANT R9, [R6.64+0x3c] ; IADD3 R2, P1, R2, 0x40, RZ ; IADD3 R8, R8, -0x10, RZ ; IMAD.X R3, RZ, RZ, R3, P1 ; ISETP.GT.AND P1, PT, R8, 0xc, PT ; STG.E [R4.64+0xc], R19 ; IADD3 R6, P2, R6, 0x40, RZ ; UIADD3 UR4, UR4, 0x10, URZ ; STG.E [R4.64+0x18], R11 ; STG.E [R4.64+0x14], R23 ; IMAD.X R7, RZ, RZ, R7, P2 ; STG.E [R4.64+0x1c], R25 ; IMAD.IADD R27, R18, 0x1, R27 ; IMAD.IADD R13, R13, 0x1, R10 ; IADD3 R10, P3, R4, 0x40, RZ ; STG.E [R4.64+0x20], R27 ; IMAD.IADD R29, R20, 0x1, R29 ; IADD3 R21, R26, R21, RZ ; IMAD.IADD R19, R22, 0x1, R24 ; STG.E [R4.64+0x24], R29 ; IMAD.X R11, RZ, RZ, R5, P3 ; IMAD.IADD R17, R16, 0x1, R17 ; STG.E [R4.64+0x28], R19 ; IMAD.IADD R15, R15, 0x1, R12 ; IADD3 R9, R14, R9, RZ ; STG.E [R4.64+0x2c], R21 ; STG.E [R4.64+0x30], R17 ; STG.E [R4.64+0x34], R15 ; STG.E [R4.64+0x38], R13 ; STG.E [R4.64+0x3c], R9 ; MOV R4, R10 ; IMAD.MOV.U32 R5, RZ, RZ, R11 ; @P1 BRA 0x180 ; ISETP.GT.AND P1, PT, R8, 0x4, PT ; @!P1 BRA 0x910 ; LDG.E.CONSTANT R13, [R2.64] ; LDG.E.CONSTANT R14, [R6.64] ; LDG.E.CONSTANT R10, [R2.64+0x1c] ; LDG.E.CONSTANT R9, [R6.64+0x1c] ; LDG.E.CONSTANT R15, [R2.64+0x4] ; LDG.E.CONSTANT R16, [R6.64+0x4] ; LDG.E.CONSTANT R17, [R2.64+0x8] ; LDG.E.CONSTANT R18, [R6.64+0x8] ; LDG.E.CONSTANT R19, [R2.64+0xc] ; LDG.E.CONSTANT R20, [R6.64+0xc] ; LDG.E.CONSTANT R21, [R2.64+0x10] ; LDG.E.CONSTANT R22, [R6.64+0x10] ; LDG.E.CONSTANT R23, [R2.64+0x14] ; LDG.E.CONSTANT R24, [R6.64+0x14] ; LDG.E.CONSTANT R11, [R2.64+0x18] ; LDG.E.CONSTANT R12, [R6.64+0x18] ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R2, P2, R2, 0x20, RZ ; IADD3 R6, P1, R6, 0x20, RZ ; IADD3.X R3, RZ, R3, RZ, P2, !PT ; IADD3 R8, R8, -0x8, RZ ; IMAD.X R7, RZ, RZ, R7, P1 ; UIADD3 UR4, UR4, 0x8, URZ ; IMAD.IADD R13, R13, 0x1, R14 ; IMAD.IADD R9, R10, 0x1, R9 ; IADD3 R10, P3, R4, 0x20, RZ ; STG.E [R4.64], R13 ; IMAD.IADD R15, R15, 0x1, R16 ; STG.E [R4.64+0x1c], R9 ; IMAD.X R13, RZ, RZ, R5, P3 ; IADD3 R17, R17, R18, RZ ; STG.E [R4.64+0x4], R15 ; IMAD.IADD R19, R19, 0x1, R20 ; STG.E [R4.64+0x8], R17 ; IMAD.IADD R21, R21, 0x1, R22 ; STG.E [R4.64+0xc], R19 ; IMAD.IADD R23, R23, 0x1, R24 ; STG.E [R4.64+0x10], R21 ; IADD3 R11, R11, R12, RZ ; STG.E [R4.64+0x14], R23 ; STG.E [R4.64+0x18], R11 ; IMAD.MOV.U32 R4, RZ, RZ, R10 ; MOV R5, R13 ; ISETP.NE.OR P0, PT, R8, RZ, P0 ; @!P0 BRA 0xaf0 ; LDG.E.CONSTANT R9, [R2.64] ; LDG.E.CONSTANT R10, [R6.64] ; LDG.E.CONSTANT R12, [R2.64+0x4] ; LDG.E.CONSTANT R13, [R6.64+0x4] ; LDG.E.CONSTANT R14, [R2.64+0x8] ; LDG.E.CONSTANT R15, [R6.64+0x8] ; LDG.E.CONSTANT R16, [R2.64+0xc] ; LDG.E.CONSTANT R17, [R6.64+0xc] ; IADD3 R8, R8, -0x4, RZ ; UIADD3 UR4, UR4, 0x4, URZ ; IADD3 R2, P0, R2, 0x10, RZ ; IADD3 R6, P1, R6, 0x10, RZ ; IMAD.X R3, RZ, RZ, R3, P0 ; ISETP.NE.AND P0, PT, R8, RZ, PT ; IADD3.X R7, RZ, R7, RZ, P1, !PT ; IMAD.IADD R11, R9, 0x1, R10 ; IADD3 R9, P2, R4, 0x10, RZ ; STG.E [R4.64], R11 ; IMAD.X R10, RZ, RZ, R5, P2 ; IMAD.IADD R13, R12, 0x1, R13 ; STG.E [R4.64+0x4], R13 ; IADD3 R15, R14, R15, RZ ; STG.E [R4.64+0x8], R15 ; IMAD.IADD R17, R16, 0x1, R17 ; STG.E [R4.64+0xc], R17 ; IMAD.MOV.U32 R4, RZ, RZ, R9 ; MOV R5, R10 ; @P0 BRA 0x930 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P0 EXIT ; UMOV UR5, 0x4 ; ULDC.64 UR6, c[0x0][0x160] ; ULDC.64 UR8, c[0x0][0x170] ; ULDC.64 UR10, c[0x0][0x168] ; UIMAD.WIDE UR6, UR4, UR5, UR6 ; UIMAD.WIDE UR8, UR4, UR5, UR8 ; UIMAD.WIDE UR4, UR4, UR5, UR10 ; IMAD.U32 R2, RZ, RZ, UR8 ; MOV R4, UR4 ; IMAD.U32 R5, RZ, RZ, UR5 ; IMAD.U32 R3, RZ, RZ, UR9 ; LDG.E.CONSTANT R5, [R4.64] ; LDG.E.CONSTANT R2, [R2.64] ; IADD3 R0, R0, -0x1, RZ ; ISETP.NE.AND P0, PT, R0, RZ, PT ; IMAD.U32 R6, RZ, RZ, UR6 ; MOV R7, UR7 ; UIADD3 UR6, UP0, UR6, 0x4, URZ ; UIADD3 UR8, UP1, UR8, 0x4, URZ ; UIADD3 UR4, UP2, UR4, 0x4, URZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; UIADD3.X UR5, URZ, UR5, URZ, UP2, !UPT ; IMAD.IADD R9, R2, 0x1, R5 ; STG.E [R6.64], R9 ; @P0 BRA 0xb80 ; EXIT ; BRA 0xcc0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z18test_restrict_argsPiS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; ISETP.GE.AND P0, PT, R0, 0x1, PT ; @!P0 EXIT ; IADD3 R2, R0.reuse, -0x1, RZ ; UMOV UR4, URZ ; LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; ULDC.64 UR10, c[0x0][0x118] ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; @!P0 BRA 0x710 ; IADD3 R6, -R0, c[0x0][0x170], RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; ISETP.GT.AND P0, PT, R6, RZ, PT ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; @!P0 BRA 0x5d0 ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x400 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E.CONSTANT R7, [R2.64] ; LDG.E.CONSTANT R9, [R2.64+0x4] ; LDG.E.CONSTANT R11, [R2.64+0x8] ; LDG.E.CONSTANT R13, [R2.64+0xc] ; LDG.E.CONSTANT R15, [R2.64+0x10] ; LDG.E.CONSTANT R17, [R2.64+0x14] ; LDG.E.CONSTANT R19, [R2.64+0x18] ; LDG.E.CONSTANT R21, [R2.64+0x1c] ; LDG.E.CONSTANT R23, [R2.64+0x20] ; LDG.E.CONSTANT R25, [R2.64+0x24] ; LDG.E.CONSTANT R27, [R2.64+0x28] ; LDG.E.CONSTANT R29, [R2.64+0x2c] ; LDG.E.CONSTANT R8, [R2.64+0x30] ; LDG.E.CONSTANT R10, [R2.64+0x34] ; LDG.E.CONSTANT R12, [R2.64+0x38] ; LDG.E.CONSTANT R14, [R2.64+0x3c] ; IADD3 R6, R6, -0x10, RZ ; UIADD3 UR4, UR4, 0x10, URZ ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; IADD3 R2, P2, R2, 0x40, RZ ; IMAD.X R3, RZ, RZ, R3, P2 ; STG.E [R4.64], R7 ; STG.E [R4.64+0x4], R9 ; STG.E [R4.64+0x8], R11 ; IADD3 R7, P3, R4, 0x40, RZ ; STG.E [R4.64+0xc], R13 ; IMAD.X R16, RZ, RZ, R5, P3 ; STG.E [R4.64+0x10], R15 ; STG.E [R4.64+0x14], R17 ; STG.E [R4.64+0x18], R19 ; STG.E [R4.64+0x1c], R21 ; STG.E [R4.64+0x20], R23 ; STG.E [R4.64+0x24], R25 ; STG.E [R4.64+0x28], R27 ; STG.E [R4.64+0x2c], R29 ; STG.E [R4.64+0x30], R8 ; STG.E [R4.64+0x34], R10 ; STG.E [R4.64+0x38], R12 ; STG.E [R4.64+0x3c], R14 ; IMAD.MOV.U32 R4, RZ, RZ, R7 ; IMAD.MOV.U32 R5, RZ, RZ, R16 ; @P1 BRA 0x160 ; ISETP.GT.AND P1, PT, R6, 0x4, PT ; @!P1 BRA 0x5b0 ; LDG.E.CONSTANT R9, [R2.64+0x4] ; LDG.E.CONSTANT R7, [R2.64] ; LDG.E.CONSTANT R11, [R2.64+0x8] ; LDG.E.CONSTANT R13, [R2.64+0xc] ; LDG.E.CONSTANT R15, [R2.64+0x10] ; LDG.E.CONSTANT R17, [R2.64+0x14] ; LDG.E.CONSTANT R19, [R2.64+0x18] ; LDG.E.CONSTANT R21, [R2.64+0x1c] ; IADD3 R8, P2, R4, 0x20, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R6, R6, -0x8, RZ ; IADD3 R2, P1, R2, 0x20, RZ ; UIADD3 UR4, UR4, 0x8, URZ ; IMAD.X R3, RZ, RZ, R3, P1 ; STG.E [R4.64+0x4], R9 ; STG.E [R4.64], R7 ; STG.E [R4.64+0x8], R11 ; IMAD.X R9, RZ, RZ, R5, P2 ; STG.E [R4.64+0xc], R13 ; STG.E [R4.64+0x10], R15 ; STG.E [R4.64+0x14], R17 ; STG.E [R4.64+0x18], R19 ; STG.E [R4.64+0x1c], R21 ; IMAD.MOV.U32 R4, RZ, RZ, R8 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; ISETP.NE.OR P0, PT, R6, RZ, P0 ; @!P0 BRA 0x710 ; LDG.E.CONSTANT R11, [R2.64] ; LDG.E.CONSTANT R13, [R2.64+0x4] ; LDG.E.CONSTANT R15, [R2.64+0x8] ; LDG.E.CONSTANT R17, [R2.64+0xc] ; IADD3 R6, R6, -0x4, RZ ; UIADD3 UR4, UR4, 0x4, URZ ; IADD3 R9, P1, R2, 0x10, RZ ; ISETP.NE.AND P0, PT, R6, RZ, PT ; IADD3 R7, P2, R4, 0x10, RZ ; IMAD.X R10, RZ, RZ, R3, P1 ; IMAD.MOV.U32 R2, RZ, RZ, R9 ; IMAD.X R8, RZ, RZ, R5, P2 ; IMAD.MOV.U32 R3, RZ, RZ, R10 ; STG.E [R4.64], R11 ; STG.E [R4.64+0x4], R13 ; STG.E [R4.64+0x8], R15 ; STG.E [R4.64+0xc], R17 ; IMAD.MOV.U32 R4, RZ, RZ, R7 ; IMAD.MOV.U32 R5, RZ, RZ, R8 ; @P0 BRA 0x5d0 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P0 EXIT ; UMOV UR5, 0x4 ; ULDC.64 UR6, c[0x0][0x160] ; ULDC.64 UR8, c[0x0][0x168] ; UIMAD.WIDE UR6, UR4, UR5, UR6 ; UIMAD.WIDE UR4, UR4, UR5, UR8 ; IMAD.U32 R3, RZ, RZ, UR5 ; IMAD.U32 R2, RZ, RZ, UR4 ; LDG.E.CONSTANT R3, [R2.64] ; IADD3 R0, R0, -0x1, RZ ; IMAD.U32 R4, RZ, RZ, UR6 ; UIADD3 UR6, UP0, UR6, 0x4, URZ ; IMAD.U32 R5, RZ, RZ, UR7 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; UIADD3 UR4, UP1, UR4, 0x4, URZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; UIADD3.X UR5, URZ, UR5, URZ, UP1, !UPT ; STG.E [R4.64], R3 ; @P0 BRA 0x780 ; EXIT ; BRA 0x860; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z13test_restrictv .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; EXIT ; BRA 0x20; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00082afa_00000000-6_855437ff996d1109c16f6f0a09f89110a3ed81bc.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z32__device_stub__Z13test_restrictvv .type _Z32__device_stub__Z13test_restrictvv, @function _Z32__device_stub__Z13test_restrictvv: .LFB2051: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 72(%rsp), %rax subq %fs:40, %rax jne .L8 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z13test_restrictv(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z32__device_stub__Z13test_restrictvv, .-_Z32__device_stub__Z13test_restrictvv .globl _Z13test_restrictv .type _Z13test_restrictv, @function _Z13test_restrictv: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z32__device_stub__Z13test_restrictvv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z13test_restrictv, .-_Z13test_restrictv .globl _Z41__device_stub__Z18test_restrict_argsPiS_iPiS_i .type _Z41__device_stub__Z18test_restrict_argsPiS_iPiS_i, @function _Z41__device_stub__Z18test_restrict_argsPiS_iPiS_i: .LFB2053: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax movq %rdi, 16(%rsp) leaq 16(%rsp), %rax movq %rax, 96(%rsp) movq %rsi, 24(%rsp) leaq 24(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 120(%rsp), %rax subq %fs:40, %rax jne .L16 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z18test_restrict_argsPiS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2053: .size _Z41__device_stub__Z18test_restrict_argsPiS_iPiS_i, .-_Z41__device_stub__Z18test_restrict_argsPiS_iPiS_i .globl _Z18test_restrict_argsPiS_i .type _Z18test_restrict_argsPiS_i, @function _Z18test_restrict_argsPiS_i: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z41__device_stub__Z18test_restrict_argsPiS_iPiS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _Z18test_restrict_argsPiS_i, .-_Z18test_restrict_argsPiS_i .globl _Z51__device_stub__Z26test_no_restrict_violationPiS_S_iPiS_S_i .type _Z51__device_stub__Z26test_no_restrict_violationPiS_S_iPiS_S_i, @function _Z51__device_stub__Z26test_no_restrict_violationPiS_S_iPiS_S_i: .LFB2055: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movl %ecx, 12(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax movq %rdi, 24(%rsp) leaq 24(%rsp), %rax movq %rax, 112(%rsp) movq %rsi, 32(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) movq %rdx, 40(%rsp) leaq 40(%rsp), %rax movq %rax, 128(%rsp) leaq 12(%rsp), %rax movq %rax, 136(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L23 .L19: movq 152(%rsp), %rax subq %fs:40, %rax jne .L24 addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 184 pushq 56(%rsp) .cfi_def_cfa_offset 192 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z26test_no_restrict_violationPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 176 jmp .L19 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE2055: .size _Z51__device_stub__Z26test_no_restrict_violationPiS_S_iPiS_S_i, .-_Z51__device_stub__Z26test_no_restrict_violationPiS_S_iPiS_S_i .globl _Z26test_no_restrict_violationPiS_S_i .type _Z26test_no_restrict_violationPiS_S_i, @function _Z26test_no_restrict_violationPiS_S_i: .LFB2056: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z51__device_stub__Z26test_no_restrict_violationPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2056: .size _Z26test_no_restrict_violationPiS_S_i, .-_Z26test_no_restrict_violationPiS_S_i .globl _Z44__device_stub__Z22test_restrict_no_readsPiS_PiS_ .type _Z44__device_stub__Z22test_restrict_no_readsPiS_PiS_, @function _Z44__device_stub__Z22test_restrict_no_readsPiS_PiS_: .LFB2057: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsp, %rax movq %rax, 80(%rsp) movq %rsi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L31 .L27: movq 104(%rsp), %rax subq %fs:40, %rax jne .L32 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L31: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z22test_restrict_no_readsPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L27 .L32: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z44__device_stub__Z22test_restrict_no_readsPiS_PiS_, .-_Z44__device_stub__Z22test_restrict_no_readsPiS_PiS_ .globl _Z22test_restrict_no_readsPiS_ .type _Z22test_restrict_no_readsPiS_, @function _Z22test_restrict_no_readsPiS_: .LFB2058: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z44__device_stub__Z22test_restrict_no_readsPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z22test_restrict_no_readsPiS_, .-_Z22test_restrict_no_readsPiS_ .globl _Z53__device_stub__Z31test_restrict_conditional_readsPiS_PiS_ .type _Z53__device_stub__Z31test_restrict_conditional_readsPiS_PiS_, @function _Z53__device_stub__Z31test_restrict_conditional_readsPiS_PiS_: .LFB2059: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsp, %rax movq %rax, 80(%rsp) movq %rsi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L39 .L35: movq 104(%rsp), %rax subq %fs:40, %rax jne .L40 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L39: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z31test_restrict_conditional_readsPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L35 .L40: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size _Z53__device_stub__Z31test_restrict_conditional_readsPiS_PiS_, .-_Z53__device_stub__Z31test_restrict_conditional_readsPiS_PiS_ .globl _Z31test_restrict_conditional_readsPiS_ .type _Z31test_restrict_conditional_readsPiS_, @function _Z31test_restrict_conditional_readsPiS_: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z53__device_stub__Z31test_restrict_conditional_readsPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _Z31test_restrict_conditional_readsPiS_, .-_Z31test_restrict_conditional_readsPiS_ .globl _Z48__device_stub__Z26test_restrict_reads_in_forPiS_PiS_ .type _Z48__device_stub__Z26test_restrict_reads_in_forPiS_PiS_, @function _Z48__device_stub__Z26test_restrict_reads_in_forPiS_PiS_: .LFB2061: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsp, %rax movq %rax, 80(%rsp) movq %rsi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L47 .L43: movq 104(%rsp), %rax subq %fs:40, %rax jne .L48 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L47: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z26test_restrict_reads_in_forPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L43 .L48: call __stack_chk_fail@PLT .cfi_endproc .LFE2061: .size _Z48__device_stub__Z26test_restrict_reads_in_forPiS_PiS_, .-_Z48__device_stub__Z26test_restrict_reads_in_forPiS_PiS_ .globl _Z26test_restrict_reads_in_forPiS_ .type _Z26test_restrict_reads_in_forPiS_, @function _Z26test_restrict_reads_in_forPiS_: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z48__device_stub__Z26test_restrict_reads_in_forPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _Z26test_restrict_reads_in_forPiS_, .-_Z26test_restrict_reads_in_forPiS_ .globl _Z50__device_stub__Z28test_restrict_reads_in_whilePiS_PiS_ .type _Z50__device_stub__Z28test_restrict_reads_in_whilePiS_PiS_, @function _Z50__device_stub__Z28test_restrict_reads_in_whilePiS_PiS_: .LFB2063: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsp, %rax movq %rax, 80(%rsp) movq %rsi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L55 .L51: movq 104(%rsp), %rax subq %fs:40, %rax jne .L56 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L55: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z28test_restrict_reads_in_whilePiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L51 .L56: call __stack_chk_fail@PLT .cfi_endproc .LFE2063: .size _Z50__device_stub__Z28test_restrict_reads_in_whilePiS_PiS_, .-_Z50__device_stub__Z28test_restrict_reads_in_whilePiS_PiS_ .globl _Z28test_restrict_reads_in_whilePiS_ .type _Z28test_restrict_reads_in_whilePiS_, @function _Z28test_restrict_reads_in_whilePiS_: .LFB2064: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z50__device_stub__Z28test_restrict_reads_in_whilePiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2064: .size _Z28test_restrict_reads_in_whilePiS_, .-_Z28test_restrict_reads_in_whilePiS_ .globl _Z53__device_stub__Z31test_restrict_read_in_conditionPiS_PiS_ .type _Z53__device_stub__Z31test_restrict_read_in_conditionPiS_PiS_, @function _Z53__device_stub__Z31test_restrict_read_in_conditionPiS_PiS_: .LFB2065: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsp, %rax movq %rax, 80(%rsp) movq %rsi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L63 .L59: movq 104(%rsp), %rax subq %fs:40, %rax jne .L64 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L63: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z31test_restrict_read_in_conditionPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L59 .L64: call __stack_chk_fail@PLT .cfi_endproc .LFE2065: .size _Z53__device_stub__Z31test_restrict_read_in_conditionPiS_PiS_, .-_Z53__device_stub__Z31test_restrict_read_in_conditionPiS_PiS_ .globl _Z31test_restrict_read_in_conditionPiS_ .type _Z31test_restrict_read_in_conditionPiS_, @function _Z31test_restrict_read_in_conditionPiS_: .LFB2066: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z53__device_stub__Z31test_restrict_read_in_conditionPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2066: .size _Z31test_restrict_read_in_conditionPiS_, .-_Z31test_restrict_read_in_conditionPiS_ .globl _Z45__device_stub__Z23test_restrict_no_writesPiS_PiS_ .type _Z45__device_stub__Z23test_restrict_no_writesPiS_PiS_, @function _Z45__device_stub__Z23test_restrict_no_writesPiS_PiS_: .LFB2067: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsp, %rax movq %rax, 80(%rsp) movq %rsi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L71 .L67: movq 104(%rsp), %rax subq %fs:40, %rax jne .L72 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L71: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z23test_restrict_no_writesPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L67 .L72: call __stack_chk_fail@PLT .cfi_endproc .LFE2067: .size _Z45__device_stub__Z23test_restrict_no_writesPiS_PiS_, .-_Z45__device_stub__Z23test_restrict_no_writesPiS_PiS_ .globl _Z23test_restrict_no_writesPiS_ .type _Z23test_restrict_no_writesPiS_, @function _Z23test_restrict_no_writesPiS_: .LFB2068: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z45__device_stub__Z23test_restrict_no_writesPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2068: .size _Z23test_restrict_no_writesPiS_, .-_Z23test_restrict_no_writesPiS_ .globl _Z54__device_stub__Z32test_restrict_conditional_writesPiS_PiS_ .type _Z54__device_stub__Z32test_restrict_conditional_writesPiS_PiS_, @function _Z54__device_stub__Z32test_restrict_conditional_writesPiS_PiS_: .LFB2069: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsp, %rax movq %rax, 80(%rsp) movq %rsi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L79 .L75: movq 104(%rsp), %rax subq %fs:40, %rax jne .L80 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L79: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z32test_restrict_conditional_writesPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L75 .L80: call __stack_chk_fail@PLT .cfi_endproc .LFE2069: .size _Z54__device_stub__Z32test_restrict_conditional_writesPiS_PiS_, .-_Z54__device_stub__Z32test_restrict_conditional_writesPiS_PiS_ .globl _Z32test_restrict_conditional_writesPiS_ .type _Z32test_restrict_conditional_writesPiS_, @function _Z32test_restrict_conditional_writesPiS_: .LFB2070: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z54__device_stub__Z32test_restrict_conditional_writesPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2070: .size _Z32test_restrict_conditional_writesPiS_, .-_Z32test_restrict_conditional_writesPiS_ .globl _Z49__device_stub__Z27test_restrict_writes_in_forPiS_PiS_ .type _Z49__device_stub__Z27test_restrict_writes_in_forPiS_PiS_, @function _Z49__device_stub__Z27test_restrict_writes_in_forPiS_PiS_: .LFB2071: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsp, %rax movq %rax, 80(%rsp) movq %rsi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L87 .L83: movq 104(%rsp), %rax subq %fs:40, %rax jne .L88 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L87: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z27test_restrict_writes_in_forPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L83 .L88: call __stack_chk_fail@PLT .cfi_endproc .LFE2071: .size _Z49__device_stub__Z27test_restrict_writes_in_forPiS_PiS_, .-_Z49__device_stub__Z27test_restrict_writes_in_forPiS_PiS_ .globl _Z27test_restrict_writes_in_forPiS_ .type _Z27test_restrict_writes_in_forPiS_, @function _Z27test_restrict_writes_in_forPiS_: .LFB2072: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z49__device_stub__Z27test_restrict_writes_in_forPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2072: .size _Z27test_restrict_writes_in_forPiS_, .-_Z27test_restrict_writes_in_forPiS_ .globl _Z51__device_stub__Z29test_restrict_writes_in_whilePiS_PiS_ .type _Z51__device_stub__Z29test_restrict_writes_in_whilePiS_PiS_, @function _Z51__device_stub__Z29test_restrict_writes_in_whilePiS_PiS_: .LFB2073: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsp, %rax movq %rax, 80(%rsp) movq %rsi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L95 .L91: movq 104(%rsp), %rax subq %fs:40, %rax jne .L96 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L95: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z29test_restrict_writes_in_whilePiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L91 .L96: call __stack_chk_fail@PLT .cfi_endproc .LFE2073: .size _Z51__device_stub__Z29test_restrict_writes_in_whilePiS_PiS_, .-_Z51__device_stub__Z29test_restrict_writes_in_whilePiS_PiS_ .globl _Z29test_restrict_writes_in_whilePiS_ .type _Z29test_restrict_writes_in_whilePiS_, @function _Z29test_restrict_writes_in_whilePiS_: .LFB2074: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z51__device_stub__Z29test_restrict_writes_in_whilePiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2074: .size _Z29test_restrict_writes_in_whilePiS_, .-_Z29test_restrict_writes_in_whilePiS_ .globl _Z59__device_stub__Z37test_restrict_read_in_while_conditionPiS_PiS_ .type _Z59__device_stub__Z37test_restrict_read_in_while_conditionPiS_PiS_, @function _Z59__device_stub__Z37test_restrict_read_in_while_conditionPiS_PiS_: .LFB2075: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsp, %rax movq %rax, 80(%rsp) movq %rsi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L103 .L99: movq 104(%rsp), %rax subq %fs:40, %rax jne .L104 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L103: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z37test_restrict_read_in_while_conditionPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L99 .L104: call __stack_chk_fail@PLT .cfi_endproc .LFE2075: .size _Z59__device_stub__Z37test_restrict_read_in_while_conditionPiS_PiS_, .-_Z59__device_stub__Z37test_restrict_read_in_while_conditionPiS_PiS_ .globl _Z37test_restrict_read_in_while_conditionPiS_ .type _Z37test_restrict_read_in_while_conditionPiS_, @function _Z37test_restrict_read_in_while_conditionPiS_: .LFB2076: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z59__device_stub__Z37test_restrict_read_in_while_conditionPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2076: .size _Z37test_restrict_read_in_while_conditionPiS_, .-_Z37test_restrict_read_in_while_conditionPiS_ .globl _Z52__device_stub__Z30test_restrict_builtin_var_readPiS_PiS_ .type _Z52__device_stub__Z30test_restrict_builtin_var_readPiS_PiS_, @function _Z52__device_stub__Z30test_restrict_builtin_var_readPiS_PiS_: .LFB2077: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsp, %rax movq %rax, 80(%rsp) movq %rsi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L111 .L107: movq 104(%rsp), %rax subq %fs:40, %rax jne .L112 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L111: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z30test_restrict_builtin_var_readPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L107 .L112: call __stack_chk_fail@PLT .cfi_endproc .LFE2077: .size _Z52__device_stub__Z30test_restrict_builtin_var_readPiS_PiS_, .-_Z52__device_stub__Z30test_restrict_builtin_var_readPiS_PiS_ .globl _Z30test_restrict_builtin_var_readPiS_ .type _Z30test_restrict_builtin_var_readPiS_, @function _Z30test_restrict_builtin_var_readPiS_: .LFB2078: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z52__device_stub__Z30test_restrict_builtin_var_readPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2078: .size _Z30test_restrict_builtin_var_readPiS_, .-_Z30test_restrict_builtin_var_readPiS_ .globl _Z53__device_stub__Z31test_restrict_builtin_var_writePiS_PiS_ .type _Z53__device_stub__Z31test_restrict_builtin_var_writePiS_PiS_, @function _Z53__device_stub__Z31test_restrict_builtin_var_writePiS_PiS_: .LFB2079: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsp, %rax movq %rax, 80(%rsp) movq %rsi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L119 .L115: movq 104(%rsp), %rax subq %fs:40, %rax jne .L120 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L119: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z31test_restrict_builtin_var_writePiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L115 .L120: call __stack_chk_fail@PLT .cfi_endproc .LFE2079: .size _Z53__device_stub__Z31test_restrict_builtin_var_writePiS_PiS_, .-_Z53__device_stub__Z31test_restrict_builtin_var_writePiS_PiS_ .globl _Z31test_restrict_builtin_var_writePiS_ .type _Z31test_restrict_builtin_var_writePiS_, @function _Z31test_restrict_builtin_var_writePiS_: .LFB2080: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z53__device_stub__Z31test_restrict_builtin_var_writePiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2080: .size _Z31test_restrict_builtin_var_writePiS_, .-_Z31test_restrict_builtin_var_writePiS_ .globl _Z41__device_stub__Z17test_restrict_sumPiS_S_PiS_S_ .type _Z41__device_stub__Z17test_restrict_sumPiS_S_PiS_S_, @function _Z41__device_stub__Z17test_restrict_sumPiS_S_PiS_S_: .LFB2081: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax movq %rdi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 96(%rsp) movq %rsi, 16(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) movq %rdx, 24(%rsp) leaq 24(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L127 .L123: movq 120(%rsp), %rax subq %fs:40, %rax jne .L128 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L127: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z17test_restrict_sumPiS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L123 .L128: call __stack_chk_fail@PLT .cfi_endproc .LFE2081: .size _Z41__device_stub__Z17test_restrict_sumPiS_S_PiS_S_, .-_Z41__device_stub__Z17test_restrict_sumPiS_S_PiS_S_ .globl _Z17test_restrict_sumPiS_S_ .type _Z17test_restrict_sumPiS_S_, @function _Z17test_restrict_sumPiS_S_: .LFB2082: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z41__device_stub__Z17test_restrict_sumPiS_S_PiS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2082: .size _Z17test_restrict_sumPiS_S_, .-_Z17test_restrict_sumPiS_S_ .globl _Z51__device_stub__Z29test_restrict_self_assignmentPiS_PiS_ .type _Z51__device_stub__Z29test_restrict_self_assignmentPiS_PiS_, @function _Z51__device_stub__Z29test_restrict_self_assignmentPiS_PiS_: .LFB2083: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsp, %rax movq %rax, 80(%rsp) movq %rsi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L135 .L131: movq 104(%rsp), %rax subq %fs:40, %rax jne .L136 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L135: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z29test_restrict_self_assignmentPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L131 .L136: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z51__device_stub__Z29test_restrict_self_assignmentPiS_PiS_, .-_Z51__device_stub__Z29test_restrict_self_assignmentPiS_PiS_ .globl _Z29test_restrict_self_assignmentPiS_ .type _Z29test_restrict_self_assignmentPiS_, @function _Z29test_restrict_self_assignmentPiS_: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z51__device_stub__Z29test_restrict_self_assignmentPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z29test_restrict_self_assignmentPiS_, .-_Z29test_restrict_self_assignmentPiS_ .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z29test_restrict_self_assignmentPiS_" .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "_Z17test_restrict_sumPiS_S_" .section .rodata.str1.8 .align 8 .LC2: .string "_Z31test_restrict_builtin_var_writePiS_" .align 8 .LC3: .string "_Z30test_restrict_builtin_var_readPiS_" .align 8 .LC4: .string "_Z37test_restrict_read_in_while_conditionPiS_" .align 8 .LC5: .string "_Z29test_restrict_writes_in_whilePiS_" .align 8 .LC6: .string "_Z27test_restrict_writes_in_forPiS_" .align 8 .LC7: .string "_Z32test_restrict_conditional_writesPiS_" .align 8 .LC8: .string "_Z23test_restrict_no_writesPiS_" .align 8 .LC9: .string "_Z31test_restrict_read_in_conditionPiS_" .align 8 .LC10: .string "_Z28test_restrict_reads_in_whilePiS_" .align 8 .LC11: .string "_Z26test_restrict_reads_in_forPiS_" .align 8 .LC12: .string "_Z31test_restrict_conditional_readsPiS_" .align 8 .LC13: .string "_Z22test_restrict_no_readsPiS_" .align 8 .LC14: .string "_Z26test_no_restrict_violationPiS_S_i" .section .rodata.str1.1 .LC15: .string "_Z18test_restrict_argsPiS_i" .LC16: .string "_Z13test_restrictv" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z29test_restrict_self_assignmentPiS_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z17test_restrict_sumPiS_S_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z31test_restrict_builtin_var_writePiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _Z30test_restrict_builtin_var_readPiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC4(%rip), %rdx movq %rdx, %rcx leaq _Z37test_restrict_read_in_while_conditionPiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _Z29test_restrict_writes_in_whilePiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z27test_restrict_writes_in_forPiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _Z32test_restrict_conditional_writesPiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC8(%rip), %rdx movq %rdx, %rcx leaq _Z23test_restrict_no_writesPiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC9(%rip), %rdx movq %rdx, %rcx leaq _Z31test_restrict_read_in_conditionPiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC10(%rip), %rdx movq %rdx, %rcx leaq _Z28test_restrict_reads_in_whilePiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC11(%rip), %rdx movq %rdx, %rcx leaq _Z26test_restrict_reads_in_forPiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _Z31test_restrict_conditional_readsPiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC13(%rip), %rdx movq %rdx, %rcx leaq _Z22test_restrict_no_readsPiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC14(%rip), %rdx movq %rdx, %rcx leaq _Z26test_no_restrict_violationPiS_S_i(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC15(%rip), %rdx movq %rdx, %rcx leaq _Z18test_restrict_argsPiS_i(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC16(%rip), %rdx movq %rdx, %rcx leaq _Z13test_restrictv(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13test_restrictv ; -- Begin function _Z13test_restrictv .globl _Z13test_restrictv .p2align 8 .type _Z13test_restrictv,@function _Z13test_restrictv: ; @_Z13test_restrictv ; %bb.0: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13test_restrictv .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 0 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 0 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 1 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13test_restrictv, .Lfunc_end0-_Z13test_restrictv ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 4 ; NumSgprs: 0 ; NumVgprs: 0 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 1 ; NumVGPRsForWavesPerEU: 1 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z18test_restrict_argsPiS_i ; -- Begin function _Z18test_restrict_argsPiS_i .globl _Z18test_restrict_argsPiS_i .p2align 8 .type _Z18test_restrict_argsPiS_i,@function _Z18test_restrict_argsPiS_i: ; @_Z18test_restrict_argsPiS_i ; %bb.0: s_load_b32 s4, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s4, 1 s_cbranch_scc1 .LBB1_3 ; %bb.1: s_load_b128 s[0:3], s[0:1], 0x0 v_mov_b32_e32 v0, 0 .LBB1_2: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_waitcnt lgkmcnt(0) s_load_b32 s5, s[2:3], 0x0 s_add_i32 s4, s4, -1 s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 s_waitcnt lgkmcnt(0) v_mov_b32_e32 v1, s5 global_store_b32 v0, v1, s[0:1] s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmp_eq_u32 s4, 0 s_cbranch_scc0 .LBB1_2 .LBB1_3: ; %._crit_edge s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z18test_restrict_argsPiS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 20 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 6 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z18test_restrict_argsPiS_i, .Lfunc_end1-_Z18test_restrict_argsPiS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 100 ; NumSgprs: 6 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 6 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z26test_no_restrict_violationPiS_S_i ; -- Begin function _Z26test_no_restrict_violationPiS_S_i .globl _Z26test_no_restrict_violationPiS_S_i .p2align 8 .type _Z26test_no_restrict_violationPiS_S_i,@function _Z26test_no_restrict_violationPiS_S_i: ; @_Z26test_no_restrict_violationPiS_S_i ; %bb.0: s_load_b32 s2, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s2, 1 s_cbranch_scc1 .LBB2_3 ; %bb.1: s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 v_mov_b32_e32 v0, 0 .p2align 6 .LBB2_2: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_waitcnt lgkmcnt(0) s_load_b32 s3, s[6:7], 0x0 s_load_b32 s8, s[0:1], 0x0 s_add_i32 s2, s2, -1 s_waitcnt lgkmcnt(0) s_add_i32 s3, s8, s3 s_add_u32 s6, s6, 4 v_mov_b32_e32 v1, s3 s_addc_u32 s7, s7, 0 s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 global_store_b32 v0, v1, s[4:5] s_add_u32 s4, s4, 4 s_addc_u32 s5, s5, 0 s_cmp_eq_u32 s2, 0 s_cbranch_scc0 .LBB2_2 .LBB2_3: ; %._crit_edge s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z26test_no_restrict_violationPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 28 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 9 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z26test_no_restrict_violationPiS_S_i, .Lfunc_end2-_Z26test_no_restrict_violationPiS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 132 ; NumSgprs: 9 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 9 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z22test_restrict_no_readsPiS_ ; -- Begin function _Z22test_restrict_no_readsPiS_ .globl _Z22test_restrict_no_readsPiS_ .p2align 8 .type _Z22test_restrict_no_readsPiS_,@function _Z22test_restrict_no_readsPiS_: ; @_Z22test_restrict_no_readsPiS_ ; %bb.0: s_load_b64 s[0:1], s[0:1], 0x0 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 42 v_mov_b32_e32 v2, 5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_store_b32 v0, v1, s[0:1] offset:12 global_store_b32 v0, v2, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z22test_restrict_no_readsPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 2 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end3: .size _Z22test_restrict_no_readsPiS_, .Lfunc_end3-_Z22test_restrict_no_readsPiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 56 ; NumSgprs: 2 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 2 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z31test_restrict_conditional_readsPiS_ ; -- Begin function _Z31test_restrict_conditional_readsPiS_ .globl _Z31test_restrict_conditional_readsPiS_ .p2align 8 .type _Z31test_restrict_conditional_readsPiS_,@function _Z31test_restrict_conditional_readsPiS_: ; @_Z31test_restrict_conditional_readsPiS_ ; %bb.0: s_load_b64 s[0:1], s[0:1], 0x0 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 42 v_mov_b32_e32 v2, 5 s_waitcnt lgkmcnt(0) s_clause 0x1 global_store_b32 v0, v1, s[0:1] offset:12 global_store_b32 v0, v2, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z31test_restrict_conditional_readsPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 2 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end4: .size _Z31test_restrict_conditional_readsPiS_, .Lfunc_end4-_Z31test_restrict_conditional_readsPiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 56 ; NumSgprs: 2 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 2 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z26test_restrict_reads_in_forPiS_ ; -- Begin function _Z26test_restrict_reads_in_forPiS_ .globl _Z26test_restrict_reads_in_forPiS_ .p2align 8 .type _Z26test_restrict_reads_in_forPiS_,@function _Z26test_restrict_reads_in_forPiS_: ; @_Z26test_restrict_reads_in_forPiS_ ; %bb.0: s_load_b64 s[0:1], s[0:1], 0x0 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 42 s_waitcnt lgkmcnt(0) global_store_b32 v0, v1, s[0:1] offset:12 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z26test_restrict_reads_in_forPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 2 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end5: .size _Z26test_restrict_reads_in_forPiS_, .Lfunc_end5-_Z26test_restrict_reads_in_forPiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 40 ; NumSgprs: 2 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 2 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z28test_restrict_reads_in_whilePiS_ ; -- Begin function _Z28test_restrict_reads_in_whilePiS_ .globl _Z28test_restrict_reads_in_whilePiS_ .p2align 8 .type _Z28test_restrict_reads_in_whilePiS_,@function _Z28test_restrict_reads_in_whilePiS_: ; @_Z28test_restrict_reads_in_whilePiS_ ; %bb.0: s_load_b64 s[0:1], s[0:1], 0x0 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 42 s_waitcnt lgkmcnt(0) global_store_b32 v0, v1, s[0:1] offset:12 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z28test_restrict_reads_in_whilePiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 2 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end6: .size _Z28test_restrict_reads_in_whilePiS_, .Lfunc_end6-_Z28test_restrict_reads_in_whilePiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 40 ; NumSgprs: 2 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 2 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z31test_restrict_read_in_conditionPiS_ ; -- Begin function _Z31test_restrict_read_in_conditionPiS_ .globl _Z31test_restrict_read_in_conditionPiS_ .p2align 8 .type _Z31test_restrict_read_in_conditionPiS_,@function _Z31test_restrict_read_in_conditionPiS_: ; @_Z31test_restrict_read_in_conditionPiS_ ; %bb.0: s_load_b64 s[0:1], s[0:1], 0x0 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 42 s_waitcnt lgkmcnt(0) global_store_b32 v0, v1, s[0:1] offset:12 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z31test_restrict_read_in_conditionPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 2 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end7: .size _Z31test_restrict_read_in_conditionPiS_, .Lfunc_end7-_Z31test_restrict_read_in_conditionPiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 40 ; NumSgprs: 2 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 2 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z23test_restrict_no_writesPiS_ ; -- Begin function _Z23test_restrict_no_writesPiS_ .globl _Z23test_restrict_no_writesPiS_ .p2align 8 .type _Z23test_restrict_no_writesPiS_,@function _Z23test_restrict_no_writesPiS_: ; @_Z23test_restrict_no_writesPiS_ ; %bb.0: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z23test_restrict_no_writesPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 1 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end8: .size _Z23test_restrict_no_writesPiS_, .Lfunc_end8-_Z23test_restrict_no_writesPiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 4 ; NumSgprs: 0 ; NumVgprs: 0 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 1 ; NumVGPRsForWavesPerEU: 1 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z32test_restrict_conditional_writesPiS_ ; -- Begin function _Z32test_restrict_conditional_writesPiS_ .globl _Z32test_restrict_conditional_writesPiS_ .p2align 8 .type _Z32test_restrict_conditional_writesPiS_,@function _Z32test_restrict_conditional_writesPiS_: ; @_Z32test_restrict_conditional_writesPiS_ ; %bb.0: s_load_b64 s[0:1], s[0:1], 0x8 v_mov_b32_e32 v0, 42 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, v0 s_waitcnt lgkmcnt(0) global_store_b64 v2, v[0:1], s[0:1] offset:8 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z32test_restrict_conditional_writesPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 2 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end9: .size _Z32test_restrict_conditional_writesPiS_, .Lfunc_end9-_Z32test_restrict_conditional_writesPiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 48 ; NumSgprs: 2 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 2 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z27test_restrict_writes_in_forPiS_ ; -- Begin function _Z27test_restrict_writes_in_forPiS_ .globl _Z27test_restrict_writes_in_forPiS_ .p2align 8 .type _Z27test_restrict_writes_in_forPiS_,@function _Z27test_restrict_writes_in_forPiS_: ; @_Z27test_restrict_writes_in_forPiS_ ; %bb.0: s_load_b64 s[0:1], s[0:1], 0x8 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 42 s_waitcnt lgkmcnt(0) s_add_u32 s2, s0, 4 s_addc_u32 s3, s1, 0 s_mov_b64 s[0:1], 0 .LBB10_1: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s4, s2, s0 s_addc_u32 s5, s3, s1 s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmp_eq_u32 s0, 16 global_store_b32 v0, v1, s[4:5] s_cbranch_scc0 .LBB10_1 ; %bb.2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z27test_restrict_writes_in_forPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 6 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end10: .size _Z27test_restrict_writes_in_forPiS_, .Lfunc_end10-_Z27test_restrict_writes_in_forPiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 80 ; NumSgprs: 6 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 6 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z29test_restrict_writes_in_whilePiS_ ; -- Begin function _Z29test_restrict_writes_in_whilePiS_ .globl _Z29test_restrict_writes_in_whilePiS_ .p2align 8 .type _Z29test_restrict_writes_in_whilePiS_,@function _Z29test_restrict_writes_in_whilePiS_: ; @_Z29test_restrict_writes_in_whilePiS_ ; %bb.0: s_load_b64 s[0:1], s[0:1], 0x8 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 42 s_waitcnt lgkmcnt(0) s_add_u32 s2, s0, 4 s_addc_u32 s3, s1, 0 s_mov_b64 s[0:1], 0 .LBB11_1: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s4, s2, s0 s_addc_u32 s5, s3, s1 s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmp_lg_u32 s0, 16 global_store_b32 v0, v1, s[4:5] s_cbranch_scc1 .LBB11_1 ; %bb.2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z29test_restrict_writes_in_whilePiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 6 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end11: .size _Z29test_restrict_writes_in_whilePiS_, .Lfunc_end11-_Z29test_restrict_writes_in_whilePiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 80 ; NumSgprs: 6 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 6 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z37test_restrict_read_in_while_conditionPiS_ ; -- Begin function _Z37test_restrict_read_in_while_conditionPiS_ .globl _Z37test_restrict_read_in_while_conditionPiS_ .p2align 8 .type _Z37test_restrict_read_in_while_conditionPiS_,@function _Z37test_restrict_read_in_while_conditionPiS_: ; @_Z37test_restrict_read_in_while_conditionPiS_ ; %bb.0: s_load_b128 s[0:3], s[0:1], 0x0 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 42 s_waitcnt lgkmcnt(0) s_load_b32 s4, s[2:3], 0xc global_store_b32 v0, v1, s[0:1] offset:12 s_waitcnt lgkmcnt(0) s_cmp_lg_u32 s4, 42 s_cbranch_scc1 .LBB12_2 ; %bb.1: ; %.lr.ph global_store_b32 v0, v0, s[2:3] offset:12 .LBB12_2: ; %._crit_edge s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z37test_restrict_read_in_while_conditionPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 5 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end12: .size _Z37test_restrict_read_in_while_conditionPiS_, .Lfunc_end12-_Z37test_restrict_read_in_while_conditionPiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 68 ; NumSgprs: 5 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 5 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z30test_restrict_builtin_var_readPiS_ ; -- Begin function _Z30test_restrict_builtin_var_readPiS_ .globl _Z30test_restrict_builtin_var_readPiS_ .p2align 8 .type _Z30test_restrict_builtin_var_readPiS_,@function _Z30test_restrict_builtin_var_readPiS_: ; @_Z30test_restrict_builtin_var_readPiS_ ; %bb.0: s_load_b64 s[0:1], s[0:1], 0x0 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 42 s_waitcnt lgkmcnt(0) global_store_b32 v0, v1, s[0:1] offset:12 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z30test_restrict_builtin_var_readPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 2 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end13: .size _Z30test_restrict_builtin_var_readPiS_, .Lfunc_end13-_Z30test_restrict_builtin_var_readPiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 40 ; NumSgprs: 2 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 2 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z31test_restrict_builtin_var_writePiS_ ; -- Begin function _Z31test_restrict_builtin_var_writePiS_ .globl _Z31test_restrict_builtin_var_writePiS_ .p2align 8 .type _Z31test_restrict_builtin_var_writePiS_,@function _Z31test_restrict_builtin_var_writePiS_: ; @_Z31test_restrict_builtin_var_writePiS_ ; %bb.0: s_load_b64 s[0:1], s[0:1], 0x8 v_dual_mov_b32 v1, 42 :: v_dual_lshlrev_b32 v0, 2, v0 s_waitcnt lgkmcnt(0) global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z31test_restrict_builtin_var_writePiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 2 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end14: .size _Z31test_restrict_builtin_var_writePiS_, .Lfunc_end14-_Z31test_restrict_builtin_var_writePiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 40 ; NumSgprs: 2 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 2 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z17test_restrict_sumPiS_S_ ; -- Begin function _Z17test_restrict_sumPiS_S_ .globl _Z17test_restrict_sumPiS_S_ .p2align 8 .type _Z17test_restrict_sumPiS_S_,@function _Z17test_restrict_sumPiS_S_: ; @_Z17test_restrict_sumPiS_S_ ; %bb.0: s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 6 v_dual_mov_b32 v2, 5 :: v_dual_mov_b32 v3, 11 s_waitcnt lgkmcnt(0) s_clause 0x2 global_store_b32 v0, v1, s[6:7] global_store_b32 v0, v2, s[4:5] global_store_b32 v0, v3, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z17test_restrict_sumPiS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 8 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end15: .size _Z17test_restrict_sumPiS_S_, .Lfunc_end15-_Z17test_restrict_sumPiS_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 80 ; NumSgprs: 8 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 8 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z29test_restrict_self_assignmentPiS_ ; -- Begin function _Z29test_restrict_self_assignmentPiS_ .globl _Z29test_restrict_self_assignmentPiS_ .p2align 8 .type _Z29test_restrict_self_assignmentPiS_,@function _Z29test_restrict_self_assignmentPiS_: ; @_Z29test_restrict_self_assignmentPiS_ ; %bb.0: s_load_b128 s[0:3], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_load_b32 s2, s[2:3], 0x0 s_waitcnt lgkmcnt(0) v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z29test_restrict_self_assignmentPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 4 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end16: .size _Z29test_restrict_self_assignmentPiS_, .Lfunc_end16-_Z29test_restrict_self_assignmentPiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 52 ; NumSgprs: 4 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 4 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: [] .group_segment_fixed_size: 0 .kernarg_segment_align: 4 .kernarg_segment_size: 0 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13test_restrictv .private_segment_fixed_size: 0 .sgpr_count: 0 .sgpr_spill_count: 0 .symbol: _Z13test_restrictv.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: write_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 20 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z18test_restrict_argsPiS_i .private_segment_fixed_size: 0 .sgpr_count: 6 .sgpr_spill_count: 0 .symbol: _Z18test_restrict_argsPiS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: write_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 28 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z26test_no_restrict_violationPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 9 .sgpr_spill_count: 0 .symbol: _Z26test_no_restrict_violationPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: write_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z22test_restrict_no_readsPiS_ .private_segment_fixed_size: 0 .sgpr_count: 2 .sgpr_spill_count: 0 .symbol: _Z22test_restrict_no_readsPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: write_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z31test_restrict_conditional_readsPiS_ .private_segment_fixed_size: 0 .sgpr_count: 2 .sgpr_spill_count: 0 .symbol: _Z31test_restrict_conditional_readsPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: write_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z26test_restrict_reads_in_forPiS_ .private_segment_fixed_size: 0 .sgpr_count: 2 .sgpr_spill_count: 0 .symbol: _Z26test_restrict_reads_in_forPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: write_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z28test_restrict_reads_in_whilePiS_ .private_segment_fixed_size: 0 .sgpr_count: 2 .sgpr_spill_count: 0 .symbol: _Z28test_restrict_reads_in_whilePiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: write_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z31test_restrict_read_in_conditionPiS_ .private_segment_fixed_size: 0 .sgpr_count: 2 .sgpr_spill_count: 0 .symbol: _Z31test_restrict_read_in_conditionPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: read_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z23test_restrict_no_writesPiS_ .private_segment_fixed_size: 0 .sgpr_count: 0 .sgpr_spill_count: 0 .symbol: _Z23test_restrict_no_writesPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: read_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z32test_restrict_conditional_writesPiS_ .private_segment_fixed_size: 0 .sgpr_count: 2 .sgpr_spill_count: 0 .symbol: _Z32test_restrict_conditional_writesPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: read_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z27test_restrict_writes_in_forPiS_ .private_segment_fixed_size: 0 .sgpr_count: 6 .sgpr_spill_count: 0 .symbol: _Z27test_restrict_writes_in_forPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: read_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z29test_restrict_writes_in_whilePiS_ .private_segment_fixed_size: 0 .sgpr_count: 6 .sgpr_spill_count: 0 .symbol: _Z29test_restrict_writes_in_whilePiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: write_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z37test_restrict_read_in_while_conditionPiS_ .private_segment_fixed_size: 0 .sgpr_count: 5 .sgpr_spill_count: 0 .symbol: _Z37test_restrict_read_in_while_conditionPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: write_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z30test_restrict_builtin_var_readPiS_ .private_segment_fixed_size: 0 .sgpr_count: 2 .sgpr_spill_count: 0 .symbol: _Z30test_restrict_builtin_var_readPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: read_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z31test_restrict_builtin_var_writePiS_ .private_segment_fixed_size: 0 .sgpr_count: 2 .sgpr_spill_count: 0 .symbol: _Z31test_restrict_builtin_var_writePiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: write_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z17test_restrict_sumPiS_S_ .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z17test_restrict_sumPiS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: write_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z29test_restrict_self_assignmentPiS_ .private_segment_fixed_size: 0 .sgpr_count: 4 .sgpr_spill_count: 0 .symbol: _Z29test_restrict_self_assignmentPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "855437ff996d1109c16f6f0a09f89110a3ed81bc.hip" .globl _Z28__device_stub__test_restrictv # -- Begin function _Z28__device_stub__test_restrictv .p2align 4, 0x90 .type _Z28__device_stub__test_restrictv,@function _Z28__device_stub__test_restrictv: # @_Z28__device_stub__test_restrictv .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z13test_restrictv, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end0: .size _Z28__device_stub__test_restrictv, .Lfunc_end0-_Z28__device_stub__test_restrictv .cfi_endproc # -- End function .globl _Z33__device_stub__test_restrict_argsPiS_i # -- Begin function _Z33__device_stub__test_restrict_argsPiS_i .p2align 4, 0x90 .type _Z33__device_stub__test_restrict_argsPiS_i,@function _Z33__device_stub__test_restrict_argsPiS_i: # @_Z33__device_stub__test_restrict_argsPiS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z18test_restrict_argsPiS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end1: .size _Z33__device_stub__test_restrict_argsPiS_i, .Lfunc_end1-_Z33__device_stub__test_restrict_argsPiS_i .cfi_endproc # -- End function .globl _Z41__device_stub__test_no_restrict_violationPiS_S_i # -- Begin function _Z41__device_stub__test_no_restrict_violationPiS_S_i .p2align 4, 0x90 .type _Z41__device_stub__test_no_restrict_violationPiS_S_i,@function _Z41__device_stub__test_no_restrict_violationPiS_S_i: # @_Z41__device_stub__test_no_restrict_violationPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z26test_no_restrict_violationPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end2: .size _Z41__device_stub__test_no_restrict_violationPiS_S_i, .Lfunc_end2-_Z41__device_stub__test_no_restrict_violationPiS_S_i .cfi_endproc # -- End function .globl _Z37__device_stub__test_restrict_no_readsPiS_ # -- Begin function _Z37__device_stub__test_restrict_no_readsPiS_ .p2align 4, 0x90 .type _Z37__device_stub__test_restrict_no_readsPiS_,@function _Z37__device_stub__test_restrict_no_readsPiS_: # @_Z37__device_stub__test_restrict_no_readsPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z22test_restrict_no_readsPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end3: .size _Z37__device_stub__test_restrict_no_readsPiS_, .Lfunc_end3-_Z37__device_stub__test_restrict_no_readsPiS_ .cfi_endproc # -- End function .globl _Z46__device_stub__test_restrict_conditional_readsPiS_ # -- Begin function _Z46__device_stub__test_restrict_conditional_readsPiS_ .p2align 4, 0x90 .type _Z46__device_stub__test_restrict_conditional_readsPiS_,@function _Z46__device_stub__test_restrict_conditional_readsPiS_: # @_Z46__device_stub__test_restrict_conditional_readsPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z31test_restrict_conditional_readsPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end4: .size _Z46__device_stub__test_restrict_conditional_readsPiS_, .Lfunc_end4-_Z46__device_stub__test_restrict_conditional_readsPiS_ .cfi_endproc # -- End function .globl _Z41__device_stub__test_restrict_reads_in_forPiS_ # -- Begin function _Z41__device_stub__test_restrict_reads_in_forPiS_ .p2align 4, 0x90 .type _Z41__device_stub__test_restrict_reads_in_forPiS_,@function _Z41__device_stub__test_restrict_reads_in_forPiS_: # @_Z41__device_stub__test_restrict_reads_in_forPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z26test_restrict_reads_in_forPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end5: .size _Z41__device_stub__test_restrict_reads_in_forPiS_, .Lfunc_end5-_Z41__device_stub__test_restrict_reads_in_forPiS_ .cfi_endproc # -- End function .globl _Z43__device_stub__test_restrict_reads_in_whilePiS_ # -- Begin function _Z43__device_stub__test_restrict_reads_in_whilePiS_ .p2align 4, 0x90 .type _Z43__device_stub__test_restrict_reads_in_whilePiS_,@function _Z43__device_stub__test_restrict_reads_in_whilePiS_: # @_Z43__device_stub__test_restrict_reads_in_whilePiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z28test_restrict_reads_in_whilePiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end6: .size _Z43__device_stub__test_restrict_reads_in_whilePiS_, .Lfunc_end6-_Z43__device_stub__test_restrict_reads_in_whilePiS_ .cfi_endproc # -- End function .globl _Z46__device_stub__test_restrict_read_in_conditionPiS_ # -- Begin function _Z46__device_stub__test_restrict_read_in_conditionPiS_ .p2align 4, 0x90 .type _Z46__device_stub__test_restrict_read_in_conditionPiS_,@function _Z46__device_stub__test_restrict_read_in_conditionPiS_: # @_Z46__device_stub__test_restrict_read_in_conditionPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z31test_restrict_read_in_conditionPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end7: .size _Z46__device_stub__test_restrict_read_in_conditionPiS_, .Lfunc_end7-_Z46__device_stub__test_restrict_read_in_conditionPiS_ .cfi_endproc # -- End function .globl _Z38__device_stub__test_restrict_no_writesPiS_ # -- Begin function _Z38__device_stub__test_restrict_no_writesPiS_ .p2align 4, 0x90 .type _Z38__device_stub__test_restrict_no_writesPiS_,@function _Z38__device_stub__test_restrict_no_writesPiS_: # @_Z38__device_stub__test_restrict_no_writesPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z23test_restrict_no_writesPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end8: .size _Z38__device_stub__test_restrict_no_writesPiS_, .Lfunc_end8-_Z38__device_stub__test_restrict_no_writesPiS_ .cfi_endproc # -- End function .globl _Z47__device_stub__test_restrict_conditional_writesPiS_ # -- Begin function _Z47__device_stub__test_restrict_conditional_writesPiS_ .p2align 4, 0x90 .type _Z47__device_stub__test_restrict_conditional_writesPiS_,@function _Z47__device_stub__test_restrict_conditional_writesPiS_: # @_Z47__device_stub__test_restrict_conditional_writesPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z32test_restrict_conditional_writesPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end9: .size _Z47__device_stub__test_restrict_conditional_writesPiS_, .Lfunc_end9-_Z47__device_stub__test_restrict_conditional_writesPiS_ .cfi_endproc # -- End function .globl _Z42__device_stub__test_restrict_writes_in_forPiS_ # -- Begin function _Z42__device_stub__test_restrict_writes_in_forPiS_ .p2align 4, 0x90 .type _Z42__device_stub__test_restrict_writes_in_forPiS_,@function _Z42__device_stub__test_restrict_writes_in_forPiS_: # @_Z42__device_stub__test_restrict_writes_in_forPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z27test_restrict_writes_in_forPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end10: .size _Z42__device_stub__test_restrict_writes_in_forPiS_, .Lfunc_end10-_Z42__device_stub__test_restrict_writes_in_forPiS_ .cfi_endproc # -- End function .globl _Z44__device_stub__test_restrict_writes_in_whilePiS_ # -- Begin function _Z44__device_stub__test_restrict_writes_in_whilePiS_ .p2align 4, 0x90 .type _Z44__device_stub__test_restrict_writes_in_whilePiS_,@function _Z44__device_stub__test_restrict_writes_in_whilePiS_: # @_Z44__device_stub__test_restrict_writes_in_whilePiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z29test_restrict_writes_in_whilePiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end11: .size _Z44__device_stub__test_restrict_writes_in_whilePiS_, .Lfunc_end11-_Z44__device_stub__test_restrict_writes_in_whilePiS_ .cfi_endproc # -- End function .globl _Z52__device_stub__test_restrict_read_in_while_conditionPiS_ # -- Begin function _Z52__device_stub__test_restrict_read_in_while_conditionPiS_ .p2align 4, 0x90 .type _Z52__device_stub__test_restrict_read_in_while_conditionPiS_,@function _Z52__device_stub__test_restrict_read_in_while_conditionPiS_: # @_Z52__device_stub__test_restrict_read_in_while_conditionPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z37test_restrict_read_in_while_conditionPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end12: .size _Z52__device_stub__test_restrict_read_in_while_conditionPiS_, .Lfunc_end12-_Z52__device_stub__test_restrict_read_in_while_conditionPiS_ .cfi_endproc # -- End function .globl _Z45__device_stub__test_restrict_builtin_var_readPiS_ # -- Begin function _Z45__device_stub__test_restrict_builtin_var_readPiS_ .p2align 4, 0x90 .type _Z45__device_stub__test_restrict_builtin_var_readPiS_,@function _Z45__device_stub__test_restrict_builtin_var_readPiS_: # @_Z45__device_stub__test_restrict_builtin_var_readPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z30test_restrict_builtin_var_readPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end13: .size _Z45__device_stub__test_restrict_builtin_var_readPiS_, .Lfunc_end13-_Z45__device_stub__test_restrict_builtin_var_readPiS_ .cfi_endproc # -- End function .globl _Z46__device_stub__test_restrict_builtin_var_writePiS_ # -- Begin function _Z46__device_stub__test_restrict_builtin_var_writePiS_ .p2align 4, 0x90 .type _Z46__device_stub__test_restrict_builtin_var_writePiS_,@function _Z46__device_stub__test_restrict_builtin_var_writePiS_: # @_Z46__device_stub__test_restrict_builtin_var_writePiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z31test_restrict_builtin_var_writePiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end14: .size _Z46__device_stub__test_restrict_builtin_var_writePiS_, .Lfunc_end14-_Z46__device_stub__test_restrict_builtin_var_writePiS_ .cfi_endproc # -- End function .globl _Z32__device_stub__test_restrict_sumPiS_S_ # -- Begin function _Z32__device_stub__test_restrict_sumPiS_S_ .p2align 4, 0x90 .type _Z32__device_stub__test_restrict_sumPiS_S_,@function _Z32__device_stub__test_restrict_sumPiS_S_: # @_Z32__device_stub__test_restrict_sumPiS_S_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z17test_restrict_sumPiS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end15: .size _Z32__device_stub__test_restrict_sumPiS_S_, .Lfunc_end15-_Z32__device_stub__test_restrict_sumPiS_S_ .cfi_endproc # -- End function .globl _Z44__device_stub__test_restrict_self_assignmentPiS_ # -- Begin function _Z44__device_stub__test_restrict_self_assignmentPiS_ .p2align 4, 0x90 .type _Z44__device_stub__test_restrict_self_assignmentPiS_,@function _Z44__device_stub__test_restrict_self_assignmentPiS_: # @_Z44__device_stub__test_restrict_self_assignmentPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z29test_restrict_self_assignmentPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end16: .size _Z44__device_stub__test_restrict_self_assignmentPiS_, .Lfunc_end16-_Z44__device_stub__test_restrict_self_assignmentPiS_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB17_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB17_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13test_restrictv, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z18test_restrict_argsPiS_i, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z26test_no_restrict_violationPiS_S_i, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z22test_restrict_no_readsPiS_, %esi movl $.L__unnamed_4, %edx movl $.L__unnamed_4, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z31test_restrict_conditional_readsPiS_, %esi movl $.L__unnamed_5, %edx movl $.L__unnamed_5, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z26test_restrict_reads_in_forPiS_, %esi movl $.L__unnamed_6, %edx movl $.L__unnamed_6, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z28test_restrict_reads_in_whilePiS_, %esi movl $.L__unnamed_7, %edx movl $.L__unnamed_7, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z31test_restrict_read_in_conditionPiS_, %esi movl $.L__unnamed_8, %edx movl $.L__unnamed_8, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z23test_restrict_no_writesPiS_, %esi movl $.L__unnamed_9, %edx movl $.L__unnamed_9, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z32test_restrict_conditional_writesPiS_, %esi movl $.L__unnamed_10, %edx movl $.L__unnamed_10, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z27test_restrict_writes_in_forPiS_, %esi movl $.L__unnamed_11, %edx movl $.L__unnamed_11, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z29test_restrict_writes_in_whilePiS_, %esi movl $.L__unnamed_12, %edx movl $.L__unnamed_12, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z37test_restrict_read_in_while_conditionPiS_, %esi movl $.L__unnamed_13, %edx movl $.L__unnamed_13, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z30test_restrict_builtin_var_readPiS_, %esi movl $.L__unnamed_14, %edx movl $.L__unnamed_14, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z31test_restrict_builtin_var_writePiS_, %esi movl $.L__unnamed_15, %edx movl $.L__unnamed_15, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z17test_restrict_sumPiS_S_, %esi movl $.L__unnamed_16, %edx movl $.L__unnamed_16, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z29test_restrict_self_assignmentPiS_, %esi movl $.L__unnamed_17, %edx movl $.L__unnamed_17, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end17: .size __hip_module_ctor, .Lfunc_end17-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB18_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB18_2: retq .Lfunc_end18: .size __hip_module_dtor, .Lfunc_end18-__hip_module_dtor .cfi_endproc # -- End function .type _Z13test_restrictv,@object # @_Z13test_restrictv .section .rodata,"a",@progbits .globl _Z13test_restrictv .p2align 3, 0x0 _Z13test_restrictv: .quad _Z28__device_stub__test_restrictv .size _Z13test_restrictv, 8 .type _Z18test_restrict_argsPiS_i,@object # @_Z18test_restrict_argsPiS_i .globl _Z18test_restrict_argsPiS_i .p2align 3, 0x0 _Z18test_restrict_argsPiS_i: .quad _Z33__device_stub__test_restrict_argsPiS_i .size _Z18test_restrict_argsPiS_i, 8 .type _Z26test_no_restrict_violationPiS_S_i,@object # @_Z26test_no_restrict_violationPiS_S_i .globl _Z26test_no_restrict_violationPiS_S_i .p2align 3, 0x0 _Z26test_no_restrict_violationPiS_S_i: .quad _Z41__device_stub__test_no_restrict_violationPiS_S_i .size _Z26test_no_restrict_violationPiS_S_i, 8 .type _Z22test_restrict_no_readsPiS_,@object # @_Z22test_restrict_no_readsPiS_ .globl _Z22test_restrict_no_readsPiS_ .p2align 3, 0x0 _Z22test_restrict_no_readsPiS_: .quad _Z37__device_stub__test_restrict_no_readsPiS_ .size _Z22test_restrict_no_readsPiS_, 8 .type _Z31test_restrict_conditional_readsPiS_,@object # @_Z31test_restrict_conditional_readsPiS_ .globl _Z31test_restrict_conditional_readsPiS_ .p2align 3, 0x0 _Z31test_restrict_conditional_readsPiS_: .quad _Z46__device_stub__test_restrict_conditional_readsPiS_ .size _Z31test_restrict_conditional_readsPiS_, 8 .type _Z26test_restrict_reads_in_forPiS_,@object # @_Z26test_restrict_reads_in_forPiS_ .globl _Z26test_restrict_reads_in_forPiS_ .p2align 3, 0x0 _Z26test_restrict_reads_in_forPiS_: .quad _Z41__device_stub__test_restrict_reads_in_forPiS_ .size _Z26test_restrict_reads_in_forPiS_, 8 .type _Z28test_restrict_reads_in_whilePiS_,@object # @_Z28test_restrict_reads_in_whilePiS_ .globl _Z28test_restrict_reads_in_whilePiS_ .p2align 3, 0x0 _Z28test_restrict_reads_in_whilePiS_: .quad _Z43__device_stub__test_restrict_reads_in_whilePiS_ .size _Z28test_restrict_reads_in_whilePiS_, 8 .type _Z31test_restrict_read_in_conditionPiS_,@object # @_Z31test_restrict_read_in_conditionPiS_ .globl _Z31test_restrict_read_in_conditionPiS_ .p2align 3, 0x0 _Z31test_restrict_read_in_conditionPiS_: .quad _Z46__device_stub__test_restrict_read_in_conditionPiS_ .size _Z31test_restrict_read_in_conditionPiS_, 8 .type _Z23test_restrict_no_writesPiS_,@object # @_Z23test_restrict_no_writesPiS_ .globl _Z23test_restrict_no_writesPiS_ .p2align 3, 0x0 _Z23test_restrict_no_writesPiS_: .quad _Z38__device_stub__test_restrict_no_writesPiS_ .size _Z23test_restrict_no_writesPiS_, 8 .type _Z32test_restrict_conditional_writesPiS_,@object # @_Z32test_restrict_conditional_writesPiS_ .globl _Z32test_restrict_conditional_writesPiS_ .p2align 3, 0x0 _Z32test_restrict_conditional_writesPiS_: .quad _Z47__device_stub__test_restrict_conditional_writesPiS_ .size _Z32test_restrict_conditional_writesPiS_, 8 .type _Z27test_restrict_writes_in_forPiS_,@object # @_Z27test_restrict_writes_in_forPiS_ .globl _Z27test_restrict_writes_in_forPiS_ .p2align 3, 0x0 _Z27test_restrict_writes_in_forPiS_: .quad _Z42__device_stub__test_restrict_writes_in_forPiS_ .size _Z27test_restrict_writes_in_forPiS_, 8 .type _Z29test_restrict_writes_in_whilePiS_,@object # @_Z29test_restrict_writes_in_whilePiS_ .globl _Z29test_restrict_writes_in_whilePiS_ .p2align 3, 0x0 _Z29test_restrict_writes_in_whilePiS_: .quad _Z44__device_stub__test_restrict_writes_in_whilePiS_ .size _Z29test_restrict_writes_in_whilePiS_, 8 .type _Z37test_restrict_read_in_while_conditionPiS_,@object # @_Z37test_restrict_read_in_while_conditionPiS_ .globl _Z37test_restrict_read_in_while_conditionPiS_ .p2align 3, 0x0 _Z37test_restrict_read_in_while_conditionPiS_: .quad _Z52__device_stub__test_restrict_read_in_while_conditionPiS_ .size _Z37test_restrict_read_in_while_conditionPiS_, 8 .type _Z30test_restrict_builtin_var_readPiS_,@object # @_Z30test_restrict_builtin_var_readPiS_ .globl _Z30test_restrict_builtin_var_readPiS_ .p2align 3, 0x0 _Z30test_restrict_builtin_var_readPiS_: .quad _Z45__device_stub__test_restrict_builtin_var_readPiS_ .size _Z30test_restrict_builtin_var_readPiS_, 8 .type _Z31test_restrict_builtin_var_writePiS_,@object # @_Z31test_restrict_builtin_var_writePiS_ .globl _Z31test_restrict_builtin_var_writePiS_ .p2align 3, 0x0 _Z31test_restrict_builtin_var_writePiS_: .quad _Z46__device_stub__test_restrict_builtin_var_writePiS_ .size _Z31test_restrict_builtin_var_writePiS_, 8 .type _Z17test_restrict_sumPiS_S_,@object # @_Z17test_restrict_sumPiS_S_ .globl _Z17test_restrict_sumPiS_S_ .p2align 3, 0x0 _Z17test_restrict_sumPiS_S_: .quad _Z32__device_stub__test_restrict_sumPiS_S_ .size _Z17test_restrict_sumPiS_S_, 8 .type _Z29test_restrict_self_assignmentPiS_,@object # @_Z29test_restrict_self_assignmentPiS_ .globl _Z29test_restrict_self_assignmentPiS_ .p2align 3, 0x0 _Z29test_restrict_self_assignmentPiS_: .quad _Z44__device_stub__test_restrict_self_assignmentPiS_ .size _Z29test_restrict_self_assignmentPiS_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z13test_restrictv" .size .L__unnamed_1, 19 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z18test_restrict_argsPiS_i" .size .L__unnamed_2, 28 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z26test_no_restrict_violationPiS_S_i" .size .L__unnamed_3, 38 .type .L__unnamed_4,@object # @3 .L__unnamed_4: .asciz "_Z22test_restrict_no_readsPiS_" .size .L__unnamed_4, 31 .type .L__unnamed_5,@object # @4 .L__unnamed_5: .asciz "_Z31test_restrict_conditional_readsPiS_" .size .L__unnamed_5, 40 .type .L__unnamed_6,@object # @5 .L__unnamed_6: .asciz "_Z26test_restrict_reads_in_forPiS_" .size .L__unnamed_6, 35 .type .L__unnamed_7,@object # @6 .L__unnamed_7: .asciz "_Z28test_restrict_reads_in_whilePiS_" .size .L__unnamed_7, 37 .type .L__unnamed_8,@object # @7 .L__unnamed_8: .asciz "_Z31test_restrict_read_in_conditionPiS_" .size .L__unnamed_8, 40 .type .L__unnamed_9,@object # @8 .L__unnamed_9: .asciz "_Z23test_restrict_no_writesPiS_" .size .L__unnamed_9, 32 .type .L__unnamed_10,@object # @9 .L__unnamed_10: .asciz "_Z32test_restrict_conditional_writesPiS_" .size .L__unnamed_10, 41 .type .L__unnamed_11,@object # @10 .L__unnamed_11: .asciz "_Z27test_restrict_writes_in_forPiS_" .size .L__unnamed_11, 36 .type .L__unnamed_12,@object # @11 .L__unnamed_12: .asciz "_Z29test_restrict_writes_in_whilePiS_" .size .L__unnamed_12, 38 .type .L__unnamed_13,@object # @12 .L__unnamed_13: .asciz "_Z37test_restrict_read_in_while_conditionPiS_" .size .L__unnamed_13, 46 .type .L__unnamed_14,@object # @13 .L__unnamed_14: .asciz "_Z30test_restrict_builtin_var_readPiS_" .size .L__unnamed_14, 39 .type .L__unnamed_15,@object # @14 .L__unnamed_15: .asciz "_Z31test_restrict_builtin_var_writePiS_" .size .L__unnamed_15, 40 .type .L__unnamed_16,@object # @15 .L__unnamed_16: .asciz "_Z17test_restrict_sumPiS_S_" .size .L__unnamed_16, 28 .type .L__unnamed_17,@object # @16 .L__unnamed_17: .asciz "_Z29test_restrict_self_assignmentPiS_" .size .L__unnamed_17, 38 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__test_restrictv .addrsig_sym _Z33__device_stub__test_restrict_argsPiS_i .addrsig_sym _Z41__device_stub__test_no_restrict_violationPiS_S_i .addrsig_sym _Z37__device_stub__test_restrict_no_readsPiS_ .addrsig_sym _Z46__device_stub__test_restrict_conditional_readsPiS_ .addrsig_sym _Z41__device_stub__test_restrict_reads_in_forPiS_ .addrsig_sym _Z43__device_stub__test_restrict_reads_in_whilePiS_ .addrsig_sym _Z46__device_stub__test_restrict_read_in_conditionPiS_ .addrsig_sym _Z38__device_stub__test_restrict_no_writesPiS_ .addrsig_sym _Z47__device_stub__test_restrict_conditional_writesPiS_ .addrsig_sym _Z42__device_stub__test_restrict_writes_in_forPiS_ .addrsig_sym _Z44__device_stub__test_restrict_writes_in_whilePiS_ .addrsig_sym _Z52__device_stub__test_restrict_read_in_while_conditionPiS_ .addrsig_sym _Z45__device_stub__test_restrict_builtin_var_readPiS_ .addrsig_sym _Z46__device_stub__test_restrict_builtin_var_writePiS_ .addrsig_sym _Z32__device_stub__test_restrict_sumPiS_S_ .addrsig_sym _Z44__device_stub__test_restrict_self_assignmentPiS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13test_restrictv .addrsig_sym _Z18test_restrict_argsPiS_i .addrsig_sym _Z26test_no_restrict_violationPiS_S_i .addrsig_sym _Z22test_restrict_no_readsPiS_ .addrsig_sym _Z31test_restrict_conditional_readsPiS_ .addrsig_sym _Z26test_restrict_reads_in_forPiS_ .addrsig_sym _Z28test_restrict_reads_in_whilePiS_ .addrsig_sym _Z31test_restrict_read_in_conditionPiS_ .addrsig_sym _Z23test_restrict_no_writesPiS_ .addrsig_sym _Z32test_restrict_conditional_writesPiS_ .addrsig_sym _Z27test_restrict_writes_in_forPiS_ .addrsig_sym _Z29test_restrict_writes_in_whilePiS_ .addrsig_sym _Z37test_restrict_read_in_while_conditionPiS_ .addrsig_sym _Z30test_restrict_builtin_var_readPiS_ .addrsig_sym _Z31test_restrict_builtin_var_writePiS_ .addrsig_sym _Z17test_restrict_sumPiS_S_ .addrsig_sym _Z29test_restrict_self_assignmentPiS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z3addiPfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_TID.X ; ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; @P0 EXIT ; I2F.U32.RP R5, c[0x0][0x0] ; LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; ULDC.64 UR4, c[0x0][0x118] ; ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; BSSY B0, 0x2d0 ; IADD3 R4, R4, c[0x0][0x160], RZ ; MUFU.RCP R5, R5 ; IADD3 R2, R5, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; HFMA2.MMA R2, -RZ, RZ, 0, 0 ; IMAD.MOV R7, RZ, RZ, -R3 ; IMAD R7, R7, c[0x0][0x0], RZ ; IMAD.HI.U32 R3, R3, R7, R2 ; IMAD.HI.U32 R3, R3, R4, RZ ; IMAD.MOV R5, RZ, RZ, -R3 ; IMAD R4, R5, c[0x0][0x0], R4 ; ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; @P0 IADD3 R3, R3, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; @P1 IADD3 R3, R3, 0x1, RZ ; @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; IADD3 R2, R3.reuse, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0x2c0 ; MOV R9, 0x4 ; IMAD.MOV.U32 R6, RZ, RZ, R2 ; IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; LDG.E R7, [R2.64] ; LDG.E R8, [R4.64] ; IADD3 R6, R6, -0x1, RZ ; IADD3 R0, R0, c[0x0][0x0], RZ ; ISETP.NE.AND P0, PT, R6, RZ, PT ; IMAD.WIDE R4, R9, c[0x0][0x0], R4 ; FADD R7, R7, R8 ; STG.E [R2.64], R7 ; IMAD.WIDE R2, R9, c[0x0][0x0], R2 ; @P0 BRA 0x220 ; BSYNC B0 ; @!P1 EXIT ; HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD.WIDE R2, R0, R21, c[0x0][0x168] ; IMAD.WIDE R4, R0, R21, c[0x0][0x170] ; LDG.E R7, [R2.64] ; LDG.E R6, [R4.64] ; IMAD.WIDE R8, R21, c[0x0][0x0], R4 ; FADD R15, R6, R7 ; IMAD.WIDE R6, R21, c[0x0][0x0], R2 ; STG.E [R4.64], R15 ; LDG.E R10, [R8.64] ; LDG.E R11, [R6.64] ; IMAD.WIDE R12, R21, c[0x0][0x0], R8 ; FADD R17, R10, R11 ; IMAD.WIDE R10, R21, c[0x0][0x0], R6 ; STG.E [R8.64], R17 ; LDG.E R2, [R12.64] ; LDG.E R3, [R10.64] ; IMAD.WIDE R4, R21, c[0x0][0x0], R12 ; FADD R19, R2, R3 ; IMAD.WIDE R2, R21, c[0x0][0x0], R10 ; STG.E [R12.64], R19 ; LDG.E R3, [R2.64] ; LDG.E R6, [R4.64] ; MOV R15, c[0x0][0x0] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; LEA R0, R15, R0, 0x1 ; LEA R0, R9, R0, 0x1 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; FADD R7, R6, R3 ; STG.E [R4.64], R7 ; @!P0 BRA 0x2e0 ; EXIT ; BRA 0x4e0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0002fe5a_00000000-6_ae1cfe96800dc79c3c1ef39331800916d68e3841.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z25__device_stub__Z3addiPfS_iPfS_ .type _Z25__device_stub__Z3addiPfS_iPfS_, @function _Z25__device_stub__Z3addiPfS_iPfS_: .LFB3694: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movl %edi, 28(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z3addiPfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_ .globl _Z3addiPfS_ .type _Z3addiPfS_, @function _Z3addiPfS_: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z25__device_stub__Z3addiPfS_iPfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z3addiPfS_, .-_Z3addiPfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC5: .string "Max error: " .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $72, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leaq 16(%rsp), %rdi movl $1, %edx movl $4194304, %esi call cudaMallocManaged@PLT leaq 24(%rsp), %rdi movl $1, %edx movl $4194304, %esi call cudaMallocManaged@PLT movl $0, %eax movss .LC1(%rip), %xmm1 movss .LC2(%rip), %xmm0 .L12: movq 16(%rsp), %rdx movss %xmm1, (%rdx,%rax) movq 24(%rsp), %rdx movss %xmm0, (%rdx,%rax) addq $4, %rax cmpq $4194304, %rax jne .L12 movl $256, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L19 .L13: call cudaDeviceSynchronize@PLT movq 24(%rsp), %rbx leaq 4194304(%rbx), %rbp movl $0x00000000, 12(%rsp) .L14: movss (%rbx), %xmm0 subss .LC3(%rip), %xmm0 andps .LC4(%rip), %xmm0 movss 12(%rsp), %xmm1 call fmaxf@PLT movss %xmm0, 12(%rsp) addq $4, %rbx cmpq %rbp, %rbx jne .L14 leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd 12(%rsp), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L20 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state movq 24(%rsp), %rdx movq 16(%rsp), %rsi movl $1048576, %edi call _Z25__device_stub__Z3addiPfS_iPfS_ jmp .L13 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1 .LC6: .string "_Z3addiPfS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z3addiPfS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 1065353216 .align 4 .LC2: .long 1073741824 .align 4 .LC3: .long 1077936128 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC4: .long 2147483647 .long 0 .long 0 .long 0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z3addiPfS_ ; -- Begin function _Z3addiPfS_ .globl _Z3addiPfS_ .p2align 8 .type _Z3addiPfS_,@function _Z3addiPfS_: ; @_Z3addiPfS_ ; %bb.0: s_load_b32 s2, s[0:1], 0x0 s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) v_cmpx_gt_i32_e64 s2, v0 s_cbranch_execz .LBB0_3 ; %bb.1: ; %.lr.ph.preheader s_clause 0x1 s_load_b32 s3, s[0:1], 0x24 s_load_b128 s[4:7], s[0:1], 0x8 v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0 s_waitcnt lgkmcnt(0) s_and_b32 s1, s3, 0xffff s_mov_b32 s3, 0 s_lshl_b32 s8, s1, 2 s_mov_b32 s9, s3 .p2align 6 .LBB0_2: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 v_add_co_u32 v3, vcc_lo, s4, v1 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo v_add_co_u32 v5, vcc_lo, s6, v1 v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo v_add_nc_u32_e32 v0, s1, v0 global_load_b32 v3, v[3:4], off global_load_b32 v4, v[5:6], off v_add_co_u32 v1, vcc_lo, v1, s8 v_cmp_le_i32_e64 s0, s2, v0 v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo s_delay_alu instid0(VALU_DEP_2) s_or_b32 s9, s0, s9 s_waitcnt vmcnt(0) v_add_f32_e32 v3, v3, v4 global_store_b32 v[5:6], v3, off s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB0_2 .LBB0_3: ; %Flow19 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z3addiPfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 10 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 188 ; NumSgprs: 12 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 12 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z3addiPfS_ .private_segment_fixed_size: 0 .sgpr_count: 12 .sgpr_spill_count: 0 .symbol: _Z3addiPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "ae1cfe96800dc79c3c1ef39331800916d68e3841.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_ .p2align 4, 0x90 .type _Z18__device_stub__addiPfS_,@function _Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movl %edi, 12(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3addiPfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_ .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI1_0: .long 0xc0400000 # float -3 .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 .LCPI1_1: .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $152, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 leaq 16(%rsp), %rdi movl $4194304, %esi # imm = 0x400000 movl $1, %edx callq hipMallocManaged leaq 8(%rsp), %rdi movl $4194304, %esi # imm = 0x400000 movl $1, %edx callq hipMallocManaged movq 16(%rsp), %rax xorl %ecx, %ecx movq 8(%rsp), %rdx .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000 movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000 incq %rcx cmpq $1048576, %rcx # imm = 0x100000 jne .LBB1_1 # %bb.2: movabsq $4294967297, %rdi # imm = 0x100000001 leaq 255(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 16(%rsp), %rax movq 8(%rsp), %rcx movl $1048576, 28(%rsp) # imm = 0x100000 movq %rax, 88(%rsp) movq %rcx, 80(%rsp) leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 88(%rsp), %rax movq %rax, 104(%rsp) leaq 80(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z3addiPfS_, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: callq hipDeviceSynchronize xorps %xmm2, %xmm2 xorl %eax, %eax movq 8(%rsp), %rcx movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN] movaps %xmm2, %xmm5 .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero addss %xmm0, %xmm3 andps %xmm1, %xmm3 cmpunordss %xmm5, %xmm5 movaps %xmm5, %xmm4 andps %xmm3, %xmm4 maxss %xmm2, %xmm3 andnps %xmm3, %xmm5 orps %xmm4, %xmm5 incq %rax movaps %xmm5, %xmm2 cmpq $1048576, %rax # imm = 0x100000 jne .LBB1_5 # %bb.6: movl $_ZSt4cout, %edi movl $.L.str, %esi movl $11, %edx movaps %xmm5, 128(%rsp) # 16-byte Spill callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movaps 128(%rsp), %xmm0 # 16-byte Reload cvtss2sd %xmm0, %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB1_11 # %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB1_9 # %bb.8: movzbl 67(%rbx), %ecx jmp .LBB1_10 .LBB1_9: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax addq $152, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB1_11: .cfi_def_cfa_offset 176 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3addiPfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z3addiPfS_,@object # @_Z3addiPfS_ .section .rodata,"a",@progbits .globl _Z3addiPfS_ .p2align 3, 0x0 _Z3addiPfS_: .quad _Z18__device_stub__addiPfS_ .size _Z3addiPfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Max error: " .size .L.str, 12 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z3addiPfS_" .size .L__unnamed_1, 12 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__addiPfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3addiPfS_ .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z6kernelPfS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R3, R3, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; @P0 EXIT ; MOV R0, c[0x0][0x0] ; ULDC.64 UR4, c[0x0][0x118] ; BSSY B0, 0x320 ; IMAD R0, R0, c[0x0][0xc], RZ ; I2F.U32.RP R6, R0 ; IMAD.MOV R9, RZ, RZ, -R0 ; IADD3 R2, R0.reuse, R3, RZ ; ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; IADD3 R7, R7, c[0x0][0x170], R0 ; MUFU.RCP R6, R6 ; IADD3 R4, R6, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; HFMA2.MMA R4, -RZ, RZ, 0, 0 ; IMAD R9, R9, R5, RZ ; IMAD.HI.U32 R2, R5, R9, R4 ; IMAD.HI.U32 R2, R2, R7, RZ ; IMAD.MOV R4, RZ, RZ, -R2 ; IMAD R7, R0, R4, R7 ; ISETP.GE.U32.AND P0, PT, R7, R0, PT ; @P0 IADD3 R7, -R0, R7, RZ ; @P0 IADD3 R2, R2, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R7, R0, PT ; @P1 IADD3 R2, R2, 0x1, RZ ; @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; IADD3 R4, R2.reuse, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0x310 ; MOV R6, 0x4 ; IMAD.MOV.U32 R2, RZ, RZ, R4 ; IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; LDG.E R8, [R4.64] ; LDG.E R9, [R6.64] ; IADD3 R2, R2, -0x1, RZ ; IADD3 R3, R0, R3, RZ ; ISETP.NE.AND P0, PT, R2, RZ, PT ; IMAD.WIDE R4, R0, 0x4, R4 ; FMUL R9, R8, R9 ; STG.E [R6.64], R9 ; IMAD.WIDE R6, R0, 0x4, R6 ; @P0 BRA 0x270 ; BSYNC B0 ; @!P1 EXIT ; HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD.WIDE R4, R3, R6, c[0x0][0x160] ; IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; LDG.E R9, [R4.64] ; LDG.E R2, [R6.64] ; IMAD.WIDE R10, R0, 0x4, R6 ; FMUL R17, R2, R9 ; IMAD.WIDE R8, R0, 0x4, R4 ; STG.E [R4.64], R17 ; LDG.E R2, [R10.64] ; LDG.E R13, [R8.64] ; IMAD.WIDE R14, R0, 0x4, R10 ; FMUL R19, R2, R13 ; IMAD.WIDE R12, R0, 0x4, R8 ; STG.E [R8.64], R19 ; LDG.E R2, [R14.64] ; LDG.E R7, [R12.64] ; IMAD.WIDE R4, R0, 0x4, R12 ; FMUL R21, R2, R7 ; IMAD.WIDE R6, R0, 0x4, R14 ; STG.E [R12.64], R21 ; LDG.E R6, [R6.64] ; LDG.E R11, [R4.64] ; IADD3 R3, R0, R3, R0 ; IADD3 R3, R0, R3, R0 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; FMUL R11, R6, R11 ; STG.E [R4.64], R11 ; @!P0 BRA 0x330 ; EXIT ; BRA 0x510; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000daf50_00000000-6_72fc210f6f3b46592062f325ff8c81f2fc475bf5.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z4initPfi .type _Z4initPfi, @function _Z4initPfi: .LFB2057: .cfi_startproc endbr64 testl %esi, %esi jle .L3 movq %rdi, %rax movslq %esi, %rsi leaq (%rdi,%rsi,4), %rdx movss .LC0(%rip), %xmm0 .L5: movss %xmm0, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L5 .L3: ret .cfi_endproc .LFE2057: .size _Z4initPfi, .-_Z4initPfi .globl _Z28__device_stub__Z6kernelPfS_iPfS_i .type _Z28__device_stub__Z6kernelPfS_iPfS_i, @function _Z28__device_stub__Z6kernelPfS_iPfS_i: .LFB2083: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 120(%rsp), %rax subq %fs:40, %rax jne .L12 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6kernelPfS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z28__device_stub__Z6kernelPfS_iPfS_i, .-_Z28__device_stub__Z6kernelPfS_iPfS_i .globl _Z6kernelPfS_i .type _Z6kernelPfS_i, @function _Z6kernelPfS_i: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z28__device_stub__Z6kernelPfS_iPfS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z6kernelPfS_i, .-_Z6kernelPfS_i .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "N is 2<<%d: %d\n" .LC2: .string "Done\n" .text .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $64, %rsp .cfi_def_cfa_offset 96 movl %edi, %ebx movq %rsi, %rbp movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leaq 12(%rsp), %rdi call cudaGetDevice@PLT movl $20, %edx cmpl $1, %ebx jg .L21 .L16: movl $2, %ebp movl %edx, %ecx sall %cl, %ebp movl %ebp, %ecx leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movslq %ebp, %rbx leaq 0(,%rbx,4), %r12 leaq 16(%rsp), %rdi movl $1, %edx movq %r12, %rsi call cudaMallocManaged@PLT leaq 24(%rsp), %rdi movl $1, %edx movq %r12, %rsi call cudaMallocManaged@PLT movl %ebp, %esi movq 16(%rsp), %rdi call _Z4initPfi movl %ebp, %esi movq 24(%rsp), %rdi call _Z4initPfi movl $0, %ecx movl 12(%rsp), %edx movq %rbx, %rsi movq 16(%rsp), %rdi call cudaMemPrefetchAsync@PLT movl $256, 44(%rsp) movl $1, 48(%rsp) addq $255, %rbx shrq $8, %rbx movl %ebx, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L22 .L17: call cudaDeviceSynchronize@PLT leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L23 movl $0, %eax addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L21: .cfi_restore_state movq 8(%rbp), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl %eax, %edx jmp .L16 .L22: movl %ebp, %edx movq 24(%rsp), %rsi movq 16(%rsp), %rdi call _Z28__device_stub__Z6kernelPfS_iPfS_i jmp .L17 .L23: call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z6kernelPfS_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _Z6kernelPfS_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1073741824 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6kernelPfS_i ; -- Begin function _Z6kernelPfS_i .globl _Z6kernelPfS_i .p2align 8 .type _Z6kernelPfS_i,@function _Z6kernelPfS_i: ; @_Z6kernelPfS_i ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x24 s_load_b32 s10, s[0:1], 0x10 s_add_u32 s2, s0, 24 s_addc_u32 s3, s1, 0 s_waitcnt lgkmcnt(0) s_and_b32 s8, s4, 0xffff s_mov_b32 s4, exec_lo v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1] s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s10, v1 s_cbranch_execz .LBB0_3 ; %bb.1: ; %.lr.ph.preheader s_load_b32 s2, s[2:3], 0x0 s_load_b128 s[4:7], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_lshlrev_b64 v[2:3], 2, v[1:2] s_waitcnt lgkmcnt(0) s_mul_i32 s2, s2, s8 s_ashr_i32 s3, s2, 31 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b64 s[8:9], s[2:3], 2 .p2align 6 .LBB0_2: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_1) v_add_co_u32 v4, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo v_add_co_u32 v6, vcc_lo, s6, v2 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo v_add_co_u32 v2, vcc_lo, v2, s8 global_load_b32 v0, v[4:5], off global_load_b32 v6, v[6:7], off v_add_nc_u32_e32 v1, s2, v1 v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo s_waitcnt vmcnt(0) v_mul_f32_e32 v0, v0, v6 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_le_i32_e64 s0, s10, v1 global_store_b32 v[4:5], v0, off s_or_b32 s1, s0, s1 s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB0_2 .LBB0_3: ; %Flow19 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6kernelPfS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6kernelPfS_i, .Lfunc_end0-_Z6kernelPfS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 236 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6kernelPfS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6kernelPfS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "72fc210f6f3b46592062f325ff8c81f2fc475bf5.hip" .globl _Z21__device_stub__kernelPfS_i # -- Begin function _Z21__device_stub__kernelPfS_i .p2align 4, 0x90 .type _Z21__device_stub__kernelPfS_i,@function _Z21__device_stub__kernelPfS_i: # @_Z21__device_stub__kernelPfS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6kernelPfS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z21__device_stub__kernelPfS_i, .Lfunc_end0-_Z21__device_stub__kernelPfS_i .cfi_endproc # -- End function .globl _Z4initPfi # -- Begin function _Z4initPfi .p2align 4, 0x90 .type _Z4initPfi,@function _Z4initPfi: # @_Z4initPfi .cfi_startproc # %bb.0: testl %esi, %esi jle .LBB1_3 # %bb.1: # %.lr.ph.preheader movl %esi, %eax xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movl $1073741824, (%rdi,%rcx,4) # imm = 0x40000000 incq %rcx cmpq %rcx, %rax jne .LBB1_2 .LBB1_3: # %._crit_edge retq .Lfunc_end1: .size _Z4initPfi, .Lfunc_end1-_Z4initPfi .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $120, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %rbx movl %edi, %ebp leaq 8(%rsp), %rdi callq hipGetDevice movl $20, %ecx cmpl $2, %ebp jl .LBB2_2 # %bb.1: movq 8(%rbx), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %rcx .LBB2_2: movl $2, %ebx shll %cl, %ebx movl $.L.str, %edi movl %ecx, %esi movl %ebx, %edx xorl %eax, %eax callq printf movslq %ebx, %r14 leaq (,%r14,4), %r15 leaq 24(%rsp), %rdi movq %r15, %rsi movl $1, %edx callq hipMallocManaged leaq 16(%rsp), %rdi movq %r15, %rsi movl $1, %edx callq hipMallocManaged movq 24(%rsp), %rdi movl %ebx, %eax testl %r14d, %r14d jle .LBB2_5 # %bb.3: # %.lr.ph.preheader.i xorl %ecx, %ecx .p2align 4, 0x90 .LBB2_4: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 movl $1073741824, (%rdi,%rcx,4) # imm = 0x40000000 incq %rcx cmpq %rcx, %rax jne .LBB2_4 .LBB2_5: # %_Z4initPfi.exit testl %ebx, %ebx jle .LBB2_8 # %bb.6: # %.lr.ph.preheader.i19 movq 16(%rsp), %rcx xorl %edx, %edx .p2align 4, 0x90 .LBB2_7: # %.lr.ph.i21 # =>This Inner Loop Header: Depth=1 movl $1073741824, (%rcx,%rdx,4) # imm = 0x40000000 incq %rdx cmpq %rdx, %rax jne .LBB2_7 .LBB2_8: # %_Z4initPfi.exit25 movl 8(%rsp), %edx movq %r14, %rsi xorl %ecx, %ecx callq hipMemPrefetchAsync addq $255, %r14 shrq $8, %r14 movl %r14d, %edi movabsq $4294967296, %rdx # imm = 0x100000000 orq %rdx, %rdi orq $256, %rdx # imm = 0x100 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_10 # %bb.9: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movl %ebx, 12(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z6kernelPfS_i, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_10: callq hipDeviceSynchronize movl $.Lstr, %edi callq puts@PLT xorl %eax, %eax addq $120, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6kernelPfS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z6kernelPfS_i,@object # @_Z6kernelPfS_i .section .rodata,"a",@progbits .globl _Z6kernelPfS_i .p2align 3, 0x0 _Z6kernelPfS_i: .quad _Z21__device_stub__kernelPfS_i .size _Z6kernelPfS_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "N is 2<<%d: %d\n" .size .L.str, 16 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z6kernelPfS_i" .size .L__unnamed_1, 15 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Done" .size .Lstr, 5 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__kernelPfS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z6kernelPfS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
1,905
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code for sm_80 Function : _Z3addPiS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; MOV R5, c[0x0][0x16c] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; MOV R3, c[0x0][0x164] ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E R5, [R4.64] ; LDG.E R2, [R2.64] ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; MOV R7, c[0x0][0x174] ; IADD3 R9, R2, R5, RZ ; STG.E [R6.64], R9 ; EXIT ; BRA 0xd0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00086a5b_00000000-6_40a34459f4d91c9a777c494496492a7e20a1c902.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z26__device_stub__Z3addPiS_S_PiS_S_ .type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function _Z26__device_stub__Z3addPiS_S_PiS_S_: .LFB2082: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z3addPiS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_ .globl _Z3addPiS_S_ .type _Z3addPiS_S_, @function _Z3addPiS_S_: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z3addPiS_S_PiS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z3addPiS_S_, .-_Z3addPiS_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%d\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 subq $72, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leaq 8(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT movl $2, (%rsp) movl $7, 4(%rsp) movq %rsp, %rsi movl $1, %ecx movl $4, %edx movq 8(%rsp), %rdi call cudaMemcpy@PLT leaq 4(%rsp), %rsi movl $1, %ecx movl $4, %edx movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L15 .L12: leaq 44(%rsp), %rdi movl $2, %ecx movl $4, %edx movq 24(%rsp), %rsi call cudaMemcpy@PLT movl 44(%rsp), %edx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L16 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z26__device_stub__Z3addPiS_S_PiS_S_ jmp .L12 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC1: .string "_Z3addPiS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z3addPiS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z3addPiS_S_ ; -- Begin function _Z3addPiS_S_ .globl _Z3addPiS_S_ .p2align 8 .type _Z3addPiS_S_,@function _Z3addPiS_S_: ; @_Z3addPiS_S_ ; %bb.0: s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_load_b32 s2, s[4:5], 0x0 s_load_b32 s3, s[6:7], 0x0 s_waitcnt lgkmcnt(0) s_add_i32 s2, s3, s2 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z3addPiS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 8 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 80 ; NumSgprs: 8 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 8 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z3addPiS_S_ .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z3addPiS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "40a34459f4d91c9a777c494496492a7e20a1c902.hip" .globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_ .p2align 4, 0x90 .type _Z18__device_stub__addPiS_S_,@function _Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3addPiS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 leaq 16(%rsp), %rdi movl $4, %esi callq hipMalloc leaq 8(%rsp), %rdi movl $4, %esi callq hipMalloc movq %rsp, %rdi movl $4, %esi callq hipMalloc movl $2, 28(%rsp) movl $7, 24(%rsp) movq 16(%rsp), %rdi leaq 28(%rsp), %rsi movl $4, %edx movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi leaq 24(%rsp), %rsi movl $4, %edx movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 16(%rsp), %rax movq 8(%rsp), %rcx movq (%rsp), %rdx movq %rax, 128(%rsp) movq %rcx, 120(%rsp) movq %rdx, 112(%rsp) leaq 128(%rsp), %rax movq %rax, 32(%rsp) leaq 120(%rsp), %rax movq %rax, 40(%rsp) leaq 112(%rsp), %rax movq %rax, 48(%rsp) leaq 96(%rsp), %rdi leaq 80(%rsp), %rsi leaq 72(%rsp), %rdx leaq 64(%rsp), %rcx callq __hipPopCallConfiguration movq 96(%rsp), %rsi movl 104(%rsp), %edx movq 80(%rsp), %rcx movl 88(%rsp), %r8d leaq 32(%rsp), %r9 movl $_Z3addPiS_S_, %edi pushq 64(%rsp) .cfi_adjust_cfa_offset 8 pushq 80(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq (%rsp), %rsi leaq 32(%rsp), %rdi movl $4, %edx movl $2, %ecx callq hipMemcpy movl 32(%rsp), %esi movl $.L.str, %edi xorl %eax, %eax callq printf movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree xorl %eax, %eax addq $136, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3addPiS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z3addPiS_S_,@object # @_Z3addPiS_S_ .section .rodata,"a",@progbits .globl _Z3addPiS_S_ .p2align 3, 0x0 _Z3addPiS_S_: .quad _Z18__device_stub__addPiS_S_ .size _Z3addPiS_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%d\n" .size .L.str, 4 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z3addPiS_S_" .size .L__unnamed_1, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__addPiS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3addPiS_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z10SimulationPfS_PKfS1_Pmmjif .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R12, SR_CTAID.X ; S2R R13, SR_TID.X ; IMAD R12, R12, c[0x0][0x0], R13 ; ISETP.GE.U32.AND P0, PT, R12, c[0x0][0x188], PT ; ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x18c], PT, P0 ; @P0 EXIT ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x190], PT ; @!P0 EXIT ; IMAD.SHL.U32 R5, R12, 0x4, RZ ; SHF.R.U32.HI R7, RZ, 0x1e, R12 ; ULDC.64 UR12, c[0x0][0x118] ; ULDC.64 UR10, c[0x0][0x190] ; IADD3 R14, P0, R5.reuse, c[0x0][0x160], RZ ; IADD3 R16, P1, R5, c[0x0][0x168], RZ ; IADD3.X R15, R7.reuse, c[0x0][0x164], RZ, P0, !PT ; IADD3.X R17, R7, c[0x0][0x16c], RZ, P1, !PT ; LDG.E R22, [R14.64] ; LDG.E R21, [R16.64] ; USHF.R.S32.HI UR4, URZ, 0x1f, UR11 ; I2F R4, c[0x0][0x194] ; UISETP.NE.AND UP0, UPT, UR10, 0x1, UPT ; IMAD.WIDE.U32 R18, R12.reuse, c[0x0][0x194], RZ ; ULOP3.LUT UR10, UR10, 0x1, URZ, 0xc0, !UPT ; UMOV UR5, URZ ; IMAD R3, R12, UR4, RZ ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x198] ; IMAD.IADD R0, R19, 0x1, R3 ; FMUL R2, R2, c[0x0][0x198] ; IMAD R3, R0, c[0x0][0x194], RZ ; R2UR UR11, R4 ; IMAD R3, R18.reuse, UR4, R3 ; UMOV UR4, URZ ; IMAD.WIDE.U32 R18, R18, c[0x0][0x194], RZ ; IMAD.IADD R3, R19, 0x1, R3 ; @!P0 BRA 0xcb0 ; IADD3 R4, P0, R5.reuse, c[0x0][0x178], RZ ; ULDC UR6, c[0x0][0x190] ; IADD3 R5, P1, R5, c[0x0][0x170], RZ ; UIADD3 UR6, UP0, UR10, -UR6, URZ ; IADD3.X R6, R7.reuse, c[0x0][0x17c], RZ, P0, !PT ; UMOV UR9, 0x2 ; IADD3.X R7, R7, c[0x0][0x174], RZ, P1, !PT ; UMOV UR8, 0x3 ; ULDC.64 UR4, c[0x0][0x188] ; USHF.L.U64.HI UR9, UR4, UR9, UR5 ; USHF.L.U32 UR17, UR4, 0x2, URZ ; USHF.L.U64.HI UR8, UR4, UR8, UR5 ; USHF.L.U32 UR7, UR4, 0x3, URZ ; UIADD3.X UR16, URZ, -0x1, URZ, UP0, !UPT ; UMOV UR4, URZ ; UMOV UR5, URZ ; IMAD.MOV.U32 R24, RZ, RZ, R5 ; IMAD.MOV.U32 R25, RZ, RZ, R7 ; LDG.E.CONSTANT R8, [R24.64] ; IMAD.MOV.U32 R24, RZ, RZ, R4 ; IMAD.MOV.U32 R25, RZ, RZ, R6 ; LDG.E.CONSTANT R26, [R24.64] ; IMAD.MOV.U32 R11, RZ, RZ, 0x3a83126f ; BSSY B0, 0x4d0 ; IMAD.MOV.U32 R10, RZ, RZ, 0x447a0000 ; FFMA R0, R11, -R10, 1 ; FFMA R0, R0, R11, 0.0010000000474974513054 ; F2I.U64.TRUNC R8, R8 ; I2F.U64 R9, R8 ; F2I.U64.TRUNC R26, R26 ; FCHK P0, R9, 1000 ; FFMA R11, R9, R0, RZ ; FFMA R20, R11, -1000, R9 ; FFMA R0, R0, R20, R11 ; @!P0 BRA 0x4c0 ; IMAD.MOV.U32 R20, RZ, RZ, R9 ; MOV R0, 0x4b0 ; CALL.REL.NOINC 0x11e0 ; IMAD.MOV.U32 R0, RZ, RZ, R8 ; BSYNC B0 ; I2F.U64 R20, R26 ; IMAD.MOV.U32 R9, RZ, RZ, 0x3a83126f ; BSSY B0, 0x5d0 ; IMAD.MOV.U32 R10, RZ, RZ, 0x447a0000 ; FFMA R8, R9, -R10, 1 ; FADD R26, R0, -0.049499999731779098511 ; FFMA R11, R8, R9, 0.0010000000474974513054 ; FCHK P0, R20, 1000 ; FFMA R8, R11, R20, RZ ; FFMA R9, R8, -1000, R20 ; FFMA R0, R11, R9, R8 ; @!P0 BRA 0x5c0 ; MOV R0, 0x5b0 ; CALL.REL.NOINC 0x11e0 ; IMAD.MOV.U32 R0, RZ, RZ, R8 ; BSYNC B0 ; IADD3 R10, P0, R5, UR17, RZ ; IADD3.X R11, R7, UR9, RZ, P0, !PT ; LDG.E.CONSTANT R8, [R10.64] ; IADD3 R24, P0, R4, UR17, RZ ; IADD3.X R25, R6, UR9, RZ, P0, !PT ; LDG.E.CONSTANT R27, [R24.64] ; FADD R22, R26, R22 ; BSSY B0, 0x860 ; FADD R0, R0, -0.049499999731779098511 ; IMAD.MOV.U32 R11, RZ, RZ, 0x3a83126f ; FSETP.GEU.AND P0, PT, R22, UR11, PT ; FADD R21, R0, R21 ; IMAD.MOV.U32 R10, RZ, RZ, 0x447a0000 ; FSETP.GEU.OR P0, PT, R21, UR11, P0 ; FSETP.LTU.OR P0, PT, R22, RZ, P0 ; FSETP.LTU.OR P0, PT, R21, RZ, P0 ; F2I.U64.TRUNC R8, R8 ; I2F.U64 R20, R8 ; @P0 BRA 0x850 ; FRND.TRUNC R0, R21 ; FRND.TRUNC R9, R22 ; FADD R0, R21, -R0 ; FMUL R0, R0, R0 ; FADD R9, R22, -R9 ; FFMA R9, R9, R9, R0 ; FSETP.GTU.AND P0, PT, R9, R2, PT ; @P0 BRA 0x850 ; F2I.FLOOR.NTZ R0, R21 ; F2I.FLOOR.NTZ R8, R22 ; IMAD R9, R0, c[0x0][0x194], RZ ; SHF.R.S32.HI R0, RZ, 0x1f, R9 ; SHF.R.S32.HI R23, RZ, 0x1f, R8.reuse ; IADD3 R8, P0, P1, R9, R18, R8 ; IADD3.X R23, R0, R3, R23, P0, P1 ; LEA R24, P0, R8, c[0x0][0x180], 0x3 ; LEA.HI.X R25, R8, c[0x0][0x184], R23, 0x3, P0 ; LDG.E.64 R8, [R24.64] ; IADD3 R8, P0, R8, 0x1, RZ ; IMAD.X R9, RZ, RZ, R9, P0 ; STG.E.64 [R24.64], R8 ; BSYNC B0 ; FCHK P0, R20, 1000 ; FFMA R0, R11, -R10, 1 ; BSSY B0, 0x920 ; FFMA R11, R0, R11, 0.0010000000474974513054 ; F2I.U64.TRUNC R26, R27 ; FFMA R9, R11, R20, RZ ; FFMA R0, R9, -1000, R20 ; FFMA R8, R11, R0, R9 ; @!P0 BRA 0x910 ; MOV R0, 0x910 ; CALL.REL.NOINC 0x11e0 ; BSYNC B0 ; I2F.U64 R20, R26 ; IMAD.MOV.U32 R9, RZ, RZ, 0x3a83126f ; BSSY B0, 0xa10 ; IMAD.MOV.U32 R10, RZ, RZ, 0x447a0000 ; FFMA R0, R9, -R10, 1 ; FADD R26, R8, -0.049499999731779098511 ; FFMA R11, R0, R9, 0.0010000000474974513054 ; FCHK P0, R20, 1000 ; FFMA R0, R11, R20, RZ ; FFMA R9, R0, -1000, R20 ; FFMA R8, R11, R9, R0 ; @!P0 BRA 0xa00 ; MOV R0, 0xa00 ; CALL.REL.NOINC 0x11e0 ; BSYNC B0 ; FADD R22, R22, R26 ; BSSY B0, 0xc00 ; FADD R8, R8, -0.049499999731779098511 ; FSETP.GEU.AND P0, PT, R22, UR11, PT ; FADD R21, R21, R8 ; FSETP.GEU.OR P0, PT, R21, UR11, P0 ; FSETP.LTU.OR P0, PT, R22, RZ, P0 ; FSETP.LTU.OR P0, PT, R21, RZ, P0 ; @P0 BRA 0xbf0 ; FRND.TRUNC R0, R21 ; FRND.TRUNC R9, R22 ; FADD R0, R21, -R0 ; FMUL R0, R0, R0 ; FADD R9, R22, -R9 ; FFMA R9, R9, R9, R0 ; FSETP.GTU.AND P0, PT, R9, R2, PT ; @P0 BRA 0xbf0 ; F2I.FLOOR.NTZ R0, R21 ; F2I.FLOOR.NTZ R8, R22 ; IMAD R9, R0, c[0x0][0x194], RZ ; SHF.R.S32.HI R0, RZ, 0x1f, R9 ; SHF.R.S32.HI R10, RZ, 0x1f, R8.reuse ; IADD3 R11, P0, P1, R9, R18, R8 ; IADD3.X R0, R0, R3, R10, P0, P1 ; LEA R8, P0, R11, c[0x0][0x180], 0x3 ; LEA.HI.X R9, R11, c[0x0][0x184], R0, 0x3, P0 ; LDG.E.64 R10, [R8.64] ; IADD3 R10, P0, R10, 0x1, RZ ; IMAD.X R11, RZ, RZ, R11, P0 ; STG.E.64 [R8.64], R10 ; BSYNC B0 ; UIADD3 UR4, UP0, UR4, 0x2, URZ ; IADD3 R4, P1, R4, UR7, RZ ; IADD3 R5, P2, R5, UR7, RZ ; UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; IADD3.X R6, R6, UR8, RZ, P1, !PT ; UIADD3 UR14, UP0, UR4, UR6, URZ ; IADD3.X R7, R7, UR8, RZ, P2, !PT ; UIADD3.X UR15, UR5, UR16, URZ, UP0, !UPT ; ISETP.NE.U32.AND P0, PT, RZ, UR14, PT ; ISETP.NE.AND.EX P0, PT, RZ, UR15, PT, P0 ; @P0 BRA 0x350 ; ISETP.NE.U32.AND P0, PT, RZ, UR10, PT ; ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; @!P0 BRA 0x11b0 ; ULDC.64 UR6, c[0x0][0x188] ; IMAD.U32 R5, RZ, RZ, UR4 ; UIMAD UR6, UR5, UR6, URZ ; IMAD.MOV.U32 R13, RZ, RZ, RZ ; UIMAD UR6, UR4, UR7, UR6 ; IMAD.WIDE.U32 R12, R5, c[0x0][0x188], R12 ; IMAD.SHL.U32 R0, R12, 0x4, RZ ; IADD3 R13, R13, UR6, RZ ; IADD3 R8, P0, R0, c[0x0][0x170], RZ ; SHF.L.U64.HI R13, R12, 0x2, R13 ; IADD3.X R9, R13, c[0x0][0x174], RZ, P0, !PT ; LDG.E.CONSTANT R6, [R8.64] ; IADD3 R12, P0, R0, c[0x0][0x178], RZ ; IADD3.X R13, R13, c[0x0][0x17c], RZ, P0, !PT ; LDG.E.CONSTANT R4, [R12.64] ; IMAD.MOV.U32 R11, RZ, RZ, 0x3a83126f ; BSSY B0, 0xed0 ; IMAD.MOV.U32 R10, RZ, RZ, 0x447a0000 ; FFMA R0, R11, -R10, 1 ; FFMA R11, R0, R11, 0.0010000000474974513054 ; F2I.U64.TRUNC R6, R6 ; F2I.U64.TRUNC R4, R4 ; I2F.U64 R20, R6 ; FCHK P0, R20, 1000 ; FFMA R0, R11, R20, RZ ; FFMA R9, R0, -1000, R20 ; FFMA R8, R11, R9, R0 ; @!P0 BRA 0xec0 ; MOV R0, 0xec0 ; CALL.REL.NOINC 0x11e0 ; BSYNC B0 ; I2F.U64 R20, R4 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3a83126f ; BSSY B0, 0xfc0 ; IMAD.MOV.U32 R10, RZ, RZ, 0x447a0000 ; FFMA R0, R7, -R10, 1 ; FADD R4, R8, -0.049499999731779098511 ; FFMA R9, R0, R7, 0.0010000000474974513054 ; FCHK P0, R20, 1000 ; FFMA R0, R9, R20, RZ ; FFMA R7, R0, -1000, R20 ; FFMA R8, R9, R7, R0 ; @!P0 BRA 0xfb0 ; MOV R0, 0xfb0 ; CALL.REL.NOINC 0x11e0 ; BSYNC B0 ; FADD R22, R22, R4 ; BSSY B0, 0x11b0 ; FADD R8, R8, -0.049499999731779098511 ; FSETP.GEU.AND P0, PT, R22, UR11, PT ; FADD R21, R21, R8 ; FSETP.GEU.OR P0, PT, R21, UR11, P0 ; FSETP.LTU.OR P0, PT, R22, RZ, P0 ; FSETP.LTU.OR P0, PT, R21, RZ, P0 ; @P0 BRA 0x11a0 ; FRND.TRUNC R0, R21 ; FRND.TRUNC R5, R22 ; FADD R0, R21, -R0 ; FMUL R0, R0, R0 ; FADD R5, R22, -R5 ; FFMA R5, R5, R5, R0 ; FSETP.GTU.AND P0, PT, R5, R2, PT ; @P0 BRA 0x11a0 ; F2I.FLOOR.NTZ R0, R21 ; F2I.FLOOR.NTZ R2, R22 ; IMAD R5, R0, c[0x0][0x194], RZ ; SHF.R.S32.HI R0, RZ, 0x1f, R5 ; SHF.R.S32.HI R4, RZ, 0x1f, R2.reuse ; IADD3 R2, P0, P1, R5, R18, R2 ; IADD3.X R3, R0, R3, R4, P0, P1 ; LEA R4, P0, R2, c[0x0][0x180], 0x3 ; LEA.HI.X R5, R2, c[0x0][0x184], R3, 0x3, P0 ; LDG.E.64 R2, [R4.64] ; IADD3 R2, P0, R2, 0x1, RZ ; IMAD.X R3, RZ, RZ, R3, P0 ; STG.E.64 [R4.64], R2 ; BSYNC B0 ; STG.E [R14.64], R22 ; STG.E [R16.64], R21 ; EXIT ; SHF.R.U32.HI R8, RZ, 0x17, R10 ; BSSY B1, 0x1820 ; SHF.R.U32.HI R11, RZ, 0x17, R20 ; LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; IADD3 R23, R8, -0x1, RZ ; IADD3 R24, R11, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R23, 0xfd, PT ; ISETP.GT.U32.OR P0, PT, R24, 0xfd, P0 ; @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; @!P0 BRA 0x1400 ; FSETP.GTU.FTZ.AND P0, PT, |R20|, +INF , PT ; FSETP.GTU.FTZ.AND P1, PT, |R10|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0x1800 ; LOP3.LUT P0, RZ, R10, 0x7fffffff, R20, 0xc8, !PT ; @!P0 BRA 0x17e0 ; FSETP.NEU.FTZ.AND P2, PT, |R20|, +INF , PT ; FSETP.NEU.FTZ.AND P1, PT, |R10|, +INF , PT ; FSETP.NEU.FTZ.AND P0, PT, |R20|, +INF , PT ; @!P1 BRA !P2, 0x17e0 ; LOP3.LUT P2, RZ, R20, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; @P1 BRA 0x17c0 ; LOP3.LUT P1, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; @P0 BRA 0x1790 ; ISETP.GE.AND P0, PT, R24, RZ, PT ; ISETP.GE.AND P1, PT, R23, RZ, PT ; @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; @!P0 FFMA R20, R20, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R10, R10, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R9, R9, 0x40, RZ ; LEA R23, R8, 0xc0800000, 0x17 ; BSSY B2, 0x1780 ; IADD3 R11, R11, -0x7f, RZ ; IMAD.IADD R10, R10, 0x1, -R23 ; IMAD R20, R11.reuse, -0x800000, R20 ; IADD3 R11, R11, 0x7f, -R8 ; MUFU.RCP R23, R10 ; IMAD.IADD R9, R11, 0x1, R9 ; FADD.FTZ R10, -R10, -RZ ; FFMA R24, R23, R10, 1 ; FFMA R23, R23, R24, R23 ; FFMA R24, R20, R23, RZ ; FFMA R25, R10, R24, R20 ; FFMA R25, R23, R25, R24 ; FFMA R10, R10, R25, R20 ; FFMA R20, R23, R10, R25 ; SHF.R.U32.HI R8, RZ, 0x17, R20 ; LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; IMAD.IADD R8, R8, 0x1, R9 ; IADD3 R11, R8, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R11, 0xfe, PT ; @!P0 BRA 0x1760 ; ISETP.GT.AND P0, PT, R8, 0xfe, PT ; @P0 BRA 0x1730 ; ISETP.GE.AND P0, PT, R8, 0x1, PT ; @P0 BRA 0x1770 ; ISETP.GE.AND P0, PT, R8, -0x18, PT ; LOP3.LUT R20, R20, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0x1770 ; FFMA.RZ R9, R23.reuse, R10.reuse, R25.reuse ; ISETP.NE.AND P2, PT, R8.reuse, RZ, PT ; FFMA.RP R11, R23.reuse, R10.reuse, R25.reuse ; ISETP.NE.AND P1, PT, R8.reuse, RZ, PT ; FFMA.RM R23, R23, R10, R25 ; LOP3.LUT R9, R9, 0x7fffff, RZ, 0xc0, !PT ; IADD3 R10, R8, 0x20, RZ ; IMAD.MOV R8, RZ, RZ, -R8 ; LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; FSETP.NEU.FTZ.AND P0, PT, R11, R23, PT ; SHF.L.U32 R10, R9, R10, RZ ; SEL R8, R8, RZ, P2 ; ISETP.NE.AND P1, PT, R10, RZ, P1 ; SHF.R.U32.HI R10, RZ, R8, R9 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R9, RZ, 0x1, R10 ; SEL R8, RZ, 0x1, !P0 ; LOP3.LUT R8, R8, 0x1, R9, 0xf8, !PT ; LOP3.LUT R8, R8, R10, RZ, 0xc0, !PT ; IMAD.IADD R8, R9, 0x1, R8 ; LOP3.LUT R20, R8, R20, RZ, 0xfc, !PT ; BRA 0x1770 ; LOP3.LUT R20, R20, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R20, R20, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x1770 ; IMAD R20, R9, 0x800000, R20 ; BSYNC B2 ; BRA 0x1810 ; LOP3.LUT R20, R10, 0x80000000, R20, 0x48, !PT ; LOP3.LUT R20, R20, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x1810 ; LOP3.LUT R20, R10, 0x80000000, R20, 0x48, !PT ; BRA 0x1810 ; MUFU.RSQ R20, -QNAN ; BRA 0x1810 ; FADD.FTZ R20, R20, R10 ; BSYNC B1 ; IMAD.MOV.U32 R10, RZ, RZ, R0 ; IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; IMAD.MOV.U32 R8, RZ, RZ, R20 ; RET.REL.NODEC R10 0x0 ; BRA 0x1860; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0001b8f5_00000000-6_9d107bc548b78ba1b14342243b35f5631d6371a4.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4057: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4057: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string " Incorrect number of parameters " .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string " Usage: " .section .rodata.str1.8 .align 8 .LC2: .string " <Number of iterations within the kernel> " .section .rodata.str1.1 .LC3: .string "<Kernel execution count>\n\n" .text .globl _Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .type _Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function _Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: .LFB4048: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl $32, %edx leaq .LC0(%rip), %rsi leaq _ZSt4cout(%rip), %rbp movq %rbp, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbp,%rax), %rbp testq %rbp, %rbp je .L8 cmpb $0, 56(%rbp) je .L5 movzbl 67(%rbp), %esi .L6: movsbl %sil, %esi leaq _ZSt4cout(%rip), %rbp movq %rbp, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $8, %edx leaq .LC1(%rip), %rsi movq %rbp, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq 8(%rbx), %rdx movq (%rbx), %rsi movq %rbp, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq %rax, %rdi movl $42, %edx leaq .LC2(%rip), %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl $26, %edx leaq .LC3(%rip), %rsi movq %rbp, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L8: .cfi_restore_state call _ZSt16__throw_bad_castv@PLT .L5: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi jmp .L6 .cfi_endproc .LFE4048: .size _Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .globl _Z44__device_stub__Z10SimulationPfS_PKfS1_PmmjifPfS_PKfS1_Pmmjif .type _Z44__device_stub__Z10SimulationPfS_PKfS1_PmmjifPfS_PKfS1_Pmmjif, @function _Z44__device_stub__Z10SimulationPfS_PKfS1_PmmjifPfS_PKfS1_Pmmjif: .LFB4079: .cfi_startproc endbr64 subq $216, %rsp .cfi_def_cfa_offset 224 movq %r9, 8(%rsp) movss %xmm0, 4(%rsp) movq %fs:40, %rax movq %rax, 200(%rsp) xorl %eax, %eax movq %rdi, 24(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) movq %rsi, 32(%rsp) leaq 32(%rsp), %rax movq %rax, 136(%rsp) movq %rdx, 40(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) movq %rcx, 48(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) movq %r8, 56(%rsp) leaq 56(%rsp), %rax movq %rax, 160(%rsp) leaq 8(%rsp), %rax movq %rax, 168(%rsp) leaq 224(%rsp), %rax movq %rax, 176(%rsp) leaq 232(%rsp), %rax movq %rax, 184(%rsp) leaq 4(%rsp), %rax movq %rax, 192(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L13 .L9: movq 200(%rsp), %rax subq %fs:40, %rax jne .L14 addq $216, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L13: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 232 pushq 72(%rsp) .cfi_def_cfa_offset 240 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z10SimulationPfS_PKfS1_Pmmjif(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 224 jmp .L9 .L14: call __stack_chk_fail@PLT .cfi_endproc .LFE4079: .size _Z44__device_stub__Z10SimulationPfS_PKfS1_PmmjifPfS_PKfS1_Pmmjif, .-_Z44__device_stub__Z10SimulationPfS_PKfS1_PmmjifPfS_PKfS1_Pmmjif .globl _Z10SimulationPfS_PKfS1_Pmmjif .type _Z10SimulationPfS_PKfS1_Pmmjif, @function _Z10SimulationPfS_PKfS1_Pmmjif: .LFB4080: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 call _Z44__device_stub__Z10SimulationPfS_PKfS1_PmmjifPfS_PKfS1_Pmmjif addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4080: .size _Z10SimulationPfS_PKfS1_Pmmjif, .-_Z10SimulationPfS_PKfS1_Pmmjif .section .rodata.str1.1 .LC5: .string " Running on " .section .rodata.str1.8 .align 8 .LC6: .string " The Device Max Work Group Size is " .section .rodata.str1.1 .LC7: .string " The number of iterations is " .section .rodata.str1.8 .align 8 .LC8: .string " The number of kernel execution is " .section .rodata.str1.1 .LC9: .string " The number of particles is " .section .rodata.str1.8 .align 8 .LC10: .string "Average kernel execution time: " .section .rodata.str1.1 .LC12: .string " (s)" .text .globl _Z13motion_devicePfS_S_S_PPimmifPmi .type _Z13motion_devicePfS_S_S_PPimmifPmi, @function _Z13motion_devicePfS_S_S_PPimmifPmi: .LFB4051: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $1176, %rsp .cfi_def_cfa_offset 1232 movq %rdi, 16(%rsp) movq %rsi, 24(%rsp) movq %rdx, %r15 movq %rcx, %r14 movq %r8, 48(%rsp) movq %r9, %r13 movss %xmm0, 44(%rsp) movq 1248(%rsp), %rbp movq %fs:40, %rax movq %rax, 1160(%rsp) xorl %eax, %eax leaq 128(%rsp), %r12 movl $0, %esi movq %r12, %rdi call cudaGetDeviceProperties_v2@PLT movl $12, %edx leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq %r12, %rdi call strlen@PLT movq %rax, %rdx movq %r12, %rsi movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbx testq %rbx, %rbx je .L67 cmpb $0, 56(%rbx) je .L20 movzbl 67(%rbx), %eax .L21: movsbl %al, %esi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $35, %edx leaq .LC6(%rip), %rsi movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl 448(%rsp), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %r12 movq (%rax), %rax movq -24(%rax), %rax movq 240(%r12,%rax), %rbx testq %rbx, %rbx je .L68 cmpb $0, 56(%rbx) je .L24 movzbl 67(%rbx), %eax .L25: movsbl %al, %esi movq %r12, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $29, %edx leaq .LC7(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl 1240(%rsp), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %r12 movq (%rax), %rax movq -24(%rax), %rax movq 240(%r12,%rax), %rbx testq %rbx, %rbx je .L69 cmpb $0, 56(%rbx) je .L28 movzbl 67(%rbx), %eax .L29: movsbl %al, %esi movq %r12, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $35, %edx leaq .LC8(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl 1256(%rsp), %esi movq %rbx, %rdi call _ZNSolsEi@PLT movq %rax, %r12 movq (%rax), %rax movq -24(%rax), %rax movq 240(%r12,%rax), %rbx testq %rbx, %rbx je .L70 cmpb $0, 56(%rbx) je .L32 movzbl 67(%rbx), %eax .L33: movsbl %al, %esi movq %r12, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $28, %edx leaq .LC9(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq 1232(%rsp), %rsi movq %rbx, %rdi call _ZNSo9_M_insertImEERSoT_@PLT movq %rax, %r12 movq (%rax), %rax movq -24(%rax), %rax movq 240(%r12,%rax), %rbx testq %rbx, %rbx je .L71 cmpb $0, 56(%rbx) je .L36 movzbl 67(%rbx), %eax .L37: movsbl %al, %esi movq %r12, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $17, %edi call srand@PLT movslq 1240(%rsp), %rcx imulq 1232(%rsp), %rcx testq %rcx, %rcx je .L38 movl $0, %ebx movabsq $2951479051793528259, %r12 movq %r13, (%rsp) movq %rcx, %r13 jmp .L43 .L67: movq 1160(%rsp), %rax subq %fs:40, %rax jne .L72 call _ZSt16__throw_bad_castv@PLT .L72: call __stack_chk_fail@PLT .L20: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) jmp .L21 .L68: movq 1160(%rsp), %rax subq %fs:40, %rax jne .L73 call _ZSt16__throw_bad_castv@PLT .L73: call __stack_chk_fail@PLT .L24: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) jmp .L25 .L69: movq 1160(%rsp), %rax subq %fs:40, %rax jne .L74 call _ZSt16__throw_bad_castv@PLT .L74: call __stack_chk_fail@PLT .L28: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) jmp .L29 .L70: movq 1160(%rsp), %rax subq %fs:40, %rax jne .L75 call _ZSt16__throw_bad_castv@PLT .L75: call __stack_chk_fail@PLT .L32: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) jmp .L33 .L71: movq 1160(%rsp), %rax subq %fs:40, %rax jne .L76 call _ZSt16__throw_bad_castv@PLT .L76: call __stack_chk_fail@PLT .L36: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) jmp .L37 .L39: movq %rcx, %rax shrq %rax andl $1, %ecx orq %rcx, %rax pxor %xmm0, %xmm0 cvtsi2ssq %rax, %xmm0 addss %xmm0, %xmm0 jmp .L40 .L41: movq %rcx, %rax shrq %rax andl $1, %ecx orq %rcx, %rax pxor %xmm0, %xmm0 cvtsi2ssq %rax, %xmm0 addss %xmm0, %xmm0 .L42: movss %xmm0, (%r14,%rbx,4) addq $1, %rbx cmpq %rbx, %r13 je .L77 .L43: call rand@PLT movslq %eax, %rcx movq %rcx, %rdx shrq $2, %rdx movq %rdx, %rax mulq %r12 movq %rdx, %rax shrq $2, %rax andq $-4, %rdx addq %rdx, %rax leaq (%rax,%rax,4), %rax salq $2, %rax subq %rax, %rcx js .L39 pxor %xmm0, %xmm0 cvtsi2ssq %rcx, %xmm0 .L40: movss %xmm0, (%r15,%rbx,4) call rand@PLT movslq %eax, %rcx movq %rcx, %rdx shrq $2, %rdx movq %rdx, %rax mulq %r12 movq %rdx, %rax shrq $2, %rax andq $-4, %rdx addq %rdx, %rax leaq (%rax,%rax,4), %rax salq $2, %rax subq %rax, %rcx js .L41 pxor %xmm0, %xmm0 cvtsi2ssq %rcx, %xmm0 jmp .L42 .L77: movq %r13, %rcx movq (%rsp), %r13 .L38: leaq 0(,%rcx,4), %rbx leaq 64(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 72(%rsp), %rdi movq %rbx, (%rsp) movq %rbx, %rsi call cudaMalloc@PLT movq 1232(%rsp), %rax leaq 0(,%rax,4), %rbx leaq 80(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 88(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movq %r13, %r12 imulq %r13, %r12 movq %r12, %rax imulq 1232(%rsp), %rax salq $3, %rax movq %rax, 8(%rsp) leaq 96(%rsp), %rdi movq %rax, %rsi call cudaMalloc@PLT movl $1, %ecx movq (%rsp), %rdx movq %r15, %rsi movq 64(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq (%rsp), %rdx movq %r14, %rsi movq 72(%rsp), %rdi call cudaMemcpy@PLT cmpl $0, 1256(%rsp) jle .L62 movq 1232(%rsp), %rax addq $255, %rax shrq $8, %rax movl %eax, %r15d movl $0, %r14d movq $0x000000000, (%rsp) movq %r12, 56(%rsp) movq %r13, 32(%rsp) movl 1256(%rsp), %r13d jmp .L46 .L45: call cudaDeviceSynchronize@PLT call _ZNSt6chrono3_V212steady_clock3nowEv@PLT subq %r12, %rax pxor %xmm0, %xmm0 cvtsi2sdq %rax, %xmm0 addsd (%rsp), %xmm0 movsd %xmm0, (%rsp) addl $1, %r14d cmpl %r14d, %r13d je .L78 .L46: movl $1, %ecx movq %rbx, %rdx movq 16(%rsp), %rsi movq 80(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq 24(%rsp), %rsi movq 88(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq 8(%rsp), %rdx movq %rbp, %rsi movq 96(%rsp), %rdi call cudaMemcpy@PLT call cudaDeviceSynchronize@PLT call _ZNSt6chrono3_V212steady_clock3nowEv@PLT movq %rax, %r12 movl $256, 116(%rsp) movl $1, 120(%rsp) movl $1, 124(%rsp) movl %r15d, 104(%rsp) movl $1, 108(%rsp) movl $1, 112(%rsp) movl $0, %r9d movl $0, %r8d movq 116(%rsp), %rdx movl $1, %ecx movq 104(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L45 movl 32(%rsp), %eax pushq %rax .cfi_def_cfa_offset 1240 movl 1248(%rsp), %eax pushq %rax .cfi_def_cfa_offset 1248 movss 60(%rsp), %xmm0 movq 1248(%rsp), %r9 movq 112(%rsp), %r8 movq 88(%rsp), %rcx movq 80(%rsp), %rdx movq 104(%rsp), %rsi movq 96(%rsp), %rdi call _Z44__device_stub__Z10SimulationPfS_PKfS1_PmmjifPfS_PKfS1_Pmmjif addq $16, %rsp .cfi_def_cfa_offset 1232 jmp .L45 .L78: movq 56(%rsp), %r12 movq 32(%rsp), %r13 .L44: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rip), %rdx movq 240(%rdx,%rax), %rbx testq %rbx, %rbx je .L79 cmpb $0, 56(%rbx) je .L49 movzbl 67(%rbx), %eax .L50: movsbl %al, %esi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $31, %edx leaq .LC10(%rip), %rsi movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movsd (%rsp), %xmm0 mulsd .LC11(%rip), %xmm0 pxor %xmm1, %xmm1 cvtsi2sdl 1256(%rsp), %xmm1 divsd %xmm1, %xmm0 movq %rbx, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi movl $4, %edx leaq .LC12(%rip), %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbx testq %rbx, %rbx je .L80 cmpb $0, 56(%rbx) je .L53 movzbl 67(%rbx), %eax .L54: movsbl %al, %esi leaq _ZSt4cout(%rip), %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $2, %ecx movq 8(%rsp), %rdx movq 96(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT cmpq $0, 1232(%rsp) je .L55 leaq 0(,%r13,8), %r9 movq 48(%rsp), %r15 leaq (%r15,%r9), %r10 leaq 0(,%r13,4), %rdi movl $0, %ebx movl $0, %r11d movq 1232(%rsp), %r14 jmp .L56 .L62: movq $0x000000000, (%rsp) jmp .L44 .L79: movq 1160(%rsp), %rax subq %fs:40, %rax jne .L81 call _ZSt16__throw_bad_castv@PLT .L81: call __stack_chk_fail@PLT .L49: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) jmp .L50 .L80: movq 1160(%rsp), %rax subq %fs:40, %rax jne .L82 call _ZSt16__throw_bad_castv@PLT .L82: call __stack_chk_fail@PLT .L53: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) jmp .L54 .L57: addq $4, %rax cmpq %rax, %rdi je .L83 .L58: movq (%rsi,%rax,2), %rdx testq %rdx, %rdx je .L57 movq %rax, %rcx addq (%r8), %rcx addl %edx, (%rcx) jmp .L57 .L83: addq $8, %r8 addq %r9, %rsi cmpq %r10, %r8 je .L59 .L60: movl $0, %eax jmp .L58 .L59: addq $1, %r11 addq %r12, %rbx cmpq %r11, %r14 je .L55 .L56: testq %r13, %r13 je .L59 leaq 0(%rbp,%rbx,8), %rsi movq %r15, %r8 jmp .L60 .L55: movq 64(%rsp), %rdi call cudaFree@PLT movq 72(%rsp), %rdi call cudaFree@PLT movq 80(%rsp), %rdi call cudaFree@PLT movq 88(%rsp), %rdi call cudaFree@PLT movq 96(%rsp), %rdi call cudaFree@PLT movq 1160(%rsp), %rax subq %fs:40, %rax jne .L84 addq $1176, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L84: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE4051: .size _Z13motion_devicePfS_S_S_PPimmifPmi, .-_Z13motion_devicePfS_S_S_PPimmifPmi .section .rodata.str1.8 .align 8 .LC13: .string "_Z10SimulationPfS_PKfS1_Pmmjif" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4082: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC13(%rip), %rdx movq %rdx, %rcx leaq _Z10SimulationPfS_PKfS1_Pmmjif(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4082: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat .weak _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_ .type _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_: .LFB4184: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA4184 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $40, %rsp .cfi_def_cfa_offset 96 movq %rdi, %r13 movq %rsi, 8(%rsp) movq %rdx, %rbp movq %rcx, %r12 movl %r8d, %r14d movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax call __errno_location@PLT movq %rax, %rbx movl (%rax), %r15d movl $0, (%rax) leaq 16(%rsp), %rsi movl %r14d, %edx movq %rbp, %rdi .LEHB0: call *%r13 movq 16(%rsp), %rcx cmpq %rbp, %rcx je .L101 cmpl $34, (%rbx) je .L90 movl $2147483648, %edx addq %rax, %rdx shrq $32, %rdx jne .L90 testq %r12, %r12 je .L93 subq %rbp, %rcx movq %rcx, (%r12) .L93: cmpl $0, (%rbx) jne .L87 movl %r15d, (%rbx) .L87: movq 24(%rsp), %rdx subq %fs:40, %rdx jne .L102 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L101: .cfi_restore_state movq 24(%rsp), %rax subq %fs:40, %rax jne .L103 movq 8(%rsp), %rdi call _ZSt24__throw_invalid_argumentPKc@PLT .L103: call __stack_chk_fail@PLT .L90: movq 24(%rsp), %rax subq %fs:40, %rax jne .L104 movq 8(%rsp), %rdi call _ZSt20__throw_out_of_rangePKc@PLT .LEHE0: .L99: endbr64 movq %rax, %rdi cmpl $0, (%rbx) jne .L96 movl %r15d, (%rbx) .L96: movq 24(%rsp), %rax subq %fs:40, %rax je .L97 call __stack_chk_fail@PLT .L104: call __stack_chk_fail@PLT .L97: .LEHB1: call _Unwind_Resume@PLT .LEHE1: .L102: call __stack_chk_fail@PLT .cfi_endproc .LFE4184: .globl __gxx_personality_v0 .section .gcc_except_table._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat .LLSDA4184: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE4184-.LLSDACSB4184 .LLSDACSB4184: .uleb128 .LEHB0-.LFB4184 .uleb128 .LEHE0-.LEHB0 .uleb128 .L99-.LFB4184 .uleb128 0 .uleb128 .LEHB1-.LFB4184 .uleb128 .LEHE1-.LEHB1 .uleb128 0 .uleb128 0 .LLSDACSE4184: .section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat .size _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_ .section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1 .align 8 .LC14: .string "basic_string: construction from null is not valid" .section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat .align 2 .weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_: .LFB4433: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $24, %rsp .cfi_def_cfa_offset 64 movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax leaq 16(%rdi), %r12 movq %r12, (%rdi) testq %rsi, %rsi je .L114 movq %rdi, %rbx movq %rsi, %r13 movq %rsi, %rdi call strlen@PLT movq %rax, %rbp movq %rax, (%rsp) cmpq $15, %rax ja .L115 cmpq $1, %rax jne .L110 movzbl 0(%r13), %eax movb %al, 16(%rbx) .L111: movq (%rsp), %rax movq %rax, 8(%rbx) movq (%rbx), %rdx movb $0, (%rdx,%rax) movq 8(%rsp), %rax subq %fs:40, %rax jne .L116 addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L114: .cfi_restore_state movq 8(%rsp), %rax subq %fs:40, %rax jne .L117 leaq .LC14(%rip), %rdi call _ZSt19__throw_logic_errorPKc@PLT .L117: call __stack_chk_fail@PLT .L115: movq %rsp, %rsi movl $0, %edx movq %rbx, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT movq %rax, %r12 movq %rax, (%rbx) movq (%rsp), %rax movq %rax, 16(%rbx) .L109: movq %rbp, %rdx movq %r13, %rsi movq %r12, %rdi call memcpy@PLT jmp .L111 .L110: testq %rax, %rax je .L111 jmp .L109 .L116: call __stack_chk_fail@PLT .cfi_endproc .LFE4433: .size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .section .rodata._Z12print_matrixIiEvPPT_mm.str1.1,"aMS",@progbits,1 .LC15: .string " " .section .text._Z12print_matrixIiEvPPT_mm,"axG",@progbits,_Z12print_matrixIiEvPPT_mm,comdat .weak _Z12print_matrixIiEvPPT_mm .type _Z12print_matrixIiEvPPT_mm, @function _Z12print_matrixIiEvPPT_mm: .LFB4435: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $24, %rsp .cfi_def_cfa_offset 80 movq %rsi, 8(%rsp) movq %rdx, %r13 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rip), %rdx movq 240(%rdx,%rax), %rbx testq %rbx, %rbx je .L133 movq %rdi, %r12 cmpb $0, 56(%rbx) je .L120 movzbl 67(%rbx), %eax .L121: movsbl %al, %esi leaq _ZSt4cout(%rip), %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT cmpq $0, 8(%rsp) je .L118 movl $0, %r15d leaq _ZSt4cout(%rip), %rbp leaq .LC15(%rip), %r14 jmp .L123 .L133: call _ZSt16__throw_bad_castv@PLT .L120: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) jmp .L121 .L134: call _ZSt16__throw_bad_castv@PLT .L135: movzbl 67(%rbx), %esi .L127: movsbl %sil, %esi movq %rbp, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT addq $1, %r15 addq $8, %r12 cmpq %r15, 8(%rsp) je .L118 .L123: movl $0, %ebx testq %r13, %r13 je .L128 .L124: movq 0(%rbp), %rax movq -24(%rax), %rax movq $3, 16(%rbp,%rax) movq (%r12), %rax movl (%rax,%rbx,4), %esi movq %rbp, %rdi call _ZNSolsEi@PLT movq %rax, %rdi movl $1, %edx movq %r14, %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT addq $1, %rbx cmpq %rbx, %r13 jne .L124 .L128: movq 0(%rbp), %rax movq -24(%rax), %rax movq 240(%rbp,%rax), %rbx testq %rbx, %rbx je .L134 cmpb $0, 56(%rbx) jne .L135 movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) movl %eax, %esi jmp .L127 .L118: addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4435: .size _Z12print_matrixIiEvPPT_mm, .-_Z12print_matrixIiEvPPT_mm .section .rodata.str1.1 .LC16: .string "stoi" .LC19: .string "Simulation time: " .LC20: .string " (s) " .section .rodata.str1.8 .align 8 .LC21: .string "\n ********************** OUTPUT GRID: " .text .globl main .type main, @function main: .LFB4054: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA4054 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $120, %rsp .cfi_def_cfa_offset 176 movq %rsi, %rbx movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax cmpl $3, %edi je .L137 leaq 63(%rsp), %rdx leaq 64(%rsp), %rbp movq (%rsi), %rsi movq %rbp, %rdi .LEHB2: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .LEHE2: movq %rbp, %rdi .LEHB3: call _Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .LEHE3: movq %rbp, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movl $1, %eax .L136: movq 104(%rsp), %rdx subq %fs:40, %rdx jne .L167 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L137: .cfi_restore_state leaq 63(%rsp), %rdx movq 8(%rsi), %rsi leaq 64(%rsp), %rdi .LEHB4: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .LEHE4: movl $10, %r8d movl $0, %ecx movq 64(%rsp), %rdx leaq .LC16(%rip), %rsi movq __isoc23_strtol@GOTPCREL(%rip), %rdi .LEHB5: call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_ .LEHE5: movl %eax, %r12d leaq 64(%rsp), %rbp movq %rbp, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq 63(%rsp), %rdx movq 16(%rbx), %rsi movq %rbp, %rdi .LEHB6: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .LEHE6: movl $10, %r8d movl $0, %ecx movq 64(%rsp), %rdx leaq .LC16(%rip), %rsi movq __isoc23_strtol@GOTPCREL(%rip), %rdi .LEHB7: call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_ .LEHE7: movl %eax, 32(%rsp) movq %rbp, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movl $168, %edi .LEHB8: call _Znam@PLT movq %rax, %rbx movq %rax, %r13 leaq 168(%rax), %r14 movq %rax, %rbp .L139: movl $84, %edi call _Znam@PLT movq %rax, 0(%rbp) addq $8, %rbp cmpq %r14, %rbp jne .L139 movslq %r12d, %rbp imulq $147456, %rbp, %rax movabsq $2305843009213693950, %rdx cmpq %rax, %rdx jb .L140 imulq $589824, %rbp, %rbp movq %rbp, %rdi call _Znam@PLT movq %rax, 8(%rsp) movq %rbp, %rdi call _Znam@PLT movq %rax, 16(%rsp) movl $589824, %edi call _Znam@PLT movq %rax, %rbp movl $589824, %edi call _Znam@PLT movq %rax, %r15 movl $520224768, %edi call _Znam@PLT movq %rax, 24(%rsp) leaq 168(%rax), %r9 movl $0, %r8d movl $0, %edi movss .LC17(%rip), %xmm0 jmp .L141 .L140: movq 104(%rsp), %rax subq %fs:40, %rax je .L142 call __stack_chk_fail@PLT .L142: call __cxa_throw_bad_array_new_length@PLT .L145: addq $441, %r8 addq $3528, %r9 cmpq $147456, %rdi je .L168 .L141: movss %xmm0, 0(%rbp,%rdi,4) movss %xmm0, (%r15,%rdi,4) addq $1, %rdi imulq $441, %rdi, %rsi movq %r9, %rdx movq %r8, %rcx .L143: leaq -168(%rdx), %rax .L144: movq $0, (%rax) addq $8, %rax cmpq %rdx, %rax jne .L144 addq $21, %rcx addq $168, %rdx cmpq %rsi, %rcx jne .L143 jmp .L145 .L168: movq %rbx, %rcx .L146: movq (%rcx), %rax leaq 84(%rax), %rdx .L147: movl $0, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L147 addq $8, %rcx cmpq %r14, %rcx jne .L146 call _ZNSt6chrono3_V212steady_clock3nowEv@PLT movq %rax, 40(%rsp) movl 32(%rsp), %esi pushq %rsi .cfi_def_cfa_offset 184 pushq 32(%rsp) .cfi_def_cfa_offset 192 pushq %r12 .cfi_def_cfa_offset 200 pushq $147456 .cfi_def_cfa_offset 208 movss .LC18(%rip), %xmm0 movl $21, %r9d movq %rbx, %r8 movq 48(%rsp), %rcx movq 40(%rsp), %rdx movq %r15, %rsi movq %rbp, %rdi call _Z13motion_devicePfS_S_S_PPimmifPmi addq $32, %rsp .cfi_def_cfa_offset 176 call _ZNSt6chrono3_V212steady_clock3nowEv@PLT movq 40(%rsp), %rsi subq %rsi, %rax movq %rax, 32(%rsp) leaq _ZSt4cout(%rip), %r12 movq %r12, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC19(%rip), %rsi movq %r12, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtsi2sdq 32(%rsp), %xmm0 mulsd .LC11(%rip), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC20(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %r12, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC21(%rip), %rsi movq %r12, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $21, %edx movl $21, %esi movq %rbx, %rdi call _Z12print_matrixIiEvPPT_mm jmp .L150 .L170: movl $4, %esi call _ZdlPvm@PLT .L149: addq $8, %r13 cmpq %r14, %r13 je .L169 .L150: movq 0(%r13), %rdi testq %rdi, %rdi jne .L170 jmp .L149 .L169: movq %rbx, %rdi call _ZdaPv@PLT movq %rbp, %rdi call _ZdaPv@PLT movq %r15, %rdi call _ZdaPv@PLT movq 8(%rsp), %rdi call _ZdaPv@PLT movq 16(%rsp), %rdi call _ZdaPv@PLT movq 24(%rsp), %rdi call _ZdaPv@PLT movl $0, %eax jmp .L136 .L158: endbr64 movq %rax, %rbx leaq 64(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq 104(%rsp), %rax subq %fs:40, %rax je .L152 call __stack_chk_fail@PLT .L152: movq %rbx, %rdi call _Unwind_Resume@PLT .L159: endbr64 movq %rax, %rbx leaq 64(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq 104(%rsp), %rax subq %fs:40, %rax je .L154 call __stack_chk_fail@PLT .L154: movq %rbx, %rdi call _Unwind_Resume@PLT .L160: endbr64 movq %rax, %rbx leaq 64(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq 104(%rsp), %rax subq %fs:40, %rax je .L156 call __stack_chk_fail@PLT .L156: movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE8: .L167: call __stack_chk_fail@PLT .cfi_endproc .LFE4054: .section .gcc_except_table,"a",@progbits .LLSDA4054: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE4054-.LLSDACSB4054 .LLSDACSB4054: .uleb128 .LEHB2-.LFB4054 .uleb128 .LEHE2-.LEHB2 .uleb128 0 .uleb128 0 .uleb128 .LEHB3-.LFB4054 .uleb128 .LEHE3-.LEHB3 .uleb128 .L158-.LFB4054 .uleb128 0 .uleb128 .LEHB4-.LFB4054 .uleb128 .LEHE4-.LEHB4 .uleb128 0 .uleb128 0 .uleb128 .LEHB5-.LFB4054 .uleb128 .LEHE5-.LEHB5 .uleb128 .L159-.LFB4054 .uleb128 0 .uleb128 .LEHB6-.LFB4054 .uleb128 .LEHE6-.LEHB6 .uleb128 0 .uleb128 0 .uleb128 .LEHB7-.LFB4054 .uleb128 .LEHE7-.LEHB7 .uleb128 .L160-.LFB4054 .uleb128 0 .uleb128 .LEHB8-.LFB4054 .uleb128 .LEHE8-.LEHB8 .uleb128 0 .uleb128 0 .LLSDACSE4054: .text .size main, .-main .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC11: .long -400107883 .long 1041313291 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC17: .long 1092616192 .align 4 .LC18: .long 1056964608 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z10SimulationPfS_PKfS1_Pmmjif ; -- Begin function _Z10SimulationPfS_PKfS1_Pmmjif .globl _Z10SimulationPfS_PKfS1_Pmmjif .p2align 8 .type _Z10SimulationPfS_PKfS1_Pmmjif,@function _Z10SimulationPfS_PKfS1_Pmmjif: ; @_Z10SimulationPfS_PKfS1_Pmmjif ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x4c s_load_b64 s[2:3], s[0:1], 0x28 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, s15, s4, v[0:1] v_mov_b32_e32 v7, 0 s_mov_b32 s4, exec_lo v_cmpx_gt_u64_e64 s[2:3], v[6:7] s_cbranch_execz .LBB0_8 ; %bb.1: ; %.preheader s_load_b32 s12, s[0:1], 0x30 s_mov_b32 s13, 0 s_waitcnt lgkmcnt(0) s_cmp_eq_u32 s12, 0 s_cbranch_scc1 .LBB0_8 ; %bb.2: ; %.lr.ph s_load_b256 s[4:11], s[0:1], 0x0 v_lshlrev_b64 v[2:3], 2, v[6:7] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v2 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo s_load_b64 s[4:5], s[0:1], 0x34 global_load_b32 v8, v[0:1], off global_load_b32 v7, v[4:5], off s_load_b64 s[0:1], s[0:1], 0x20 s_waitcnt lgkmcnt(0) s_mul_i32 s6, s4, s4 s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[9:10], null, s6, v6, 0 s_mul_hi_i32 s6, s4, s4 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mad_u64_u32 v[11:12], null, s6, v6, v[10:11] v_cvt_f32_i32_e32 v6, s4 s_lshl_b64 s[6:7], s[2:3], 2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mov_b32_e32 v10, v11 v_lshlrev_b64 v[10:11], 3, v[9:10] v_mul_f32_e64 v9, s5, s5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v10, vcc_lo, s0, v10 v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo s_branch .LBB0_4 .LBB0_3: ; in Loop: Header=BB0_4 Depth=1 s_or_b32 exec_lo, exec_lo, s3 v_add_co_u32 v2, vcc_lo, v2, s6 s_add_u32 s12, s12, -1 v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo s_addc_u32 s13, s13, -1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u64 s[12:13], 0 s_cbranch_scc0 .LBB0_7 .LBB0_4: ; =>This Inner Loop Header: Depth=1 v_add_co_u32 v12, vcc_lo, s8, v2 v_add_co_ci_u32_e32 v13, vcc_lo, s9, v3, vcc_lo v_add_co_u32 v14, vcc_lo, s10, v2 v_add_co_ci_u32_e32 v15, vcc_lo, s11, v3, vcc_lo s_mov_b32 s3, exec_lo global_load_b32 v12, v[12:13], off global_load_b32 v13, v[14:15], off s_waitcnt vmcnt(1) v_trunc_f32_e32 v12, v12 s_waitcnt vmcnt(0) v_trunc_f32_e32 v14, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f32_e32 v13, 0x2f800000, v12 v_mul_f32_e32 v15, 0x2f800000, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_floor_f32_e32 v16, v13 v_floor_f32_e32 v17, v15 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_u32_f32_e32 v13, v16 v_cvt_u32_f32_e32 v15, v17 v_fmac_f32_e32 v12, 0xcf800000, v16 v_fmac_f32_e32 v14, 0xcf800000, v17 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_clz_i32_u32_e32 v16, v13 v_clz_i32_u32_e32 v17, v15 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cvt_u32_f32_e32 v12, v12 v_cvt_u32_f32_e32 v14, v14 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_min_u32_e32 v16, 32, v16 v_min_u32_e32 v17, 32, v17 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[12:13], v16, v[12:13] v_lshlrev_b64 v[14:15], v17, v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_min_u32_e32 v12, 1, v12 v_min_u32_e32 v14, 1, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_or_b32_e32 v12, v13, v12 v_or_b32_e32 v13, v15, v14 v_sub_nc_u32_e32 v14, 32, v16 v_sub_nc_u32_e32 v15, 32, v17 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cvt_f32_u32_e32 v12, v12 v_cvt_f32_u32_e32 v13, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ldexp_f32 v12, v12, v14 v_ldexp_f32 v13, v13, v15 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_scale_f32 v14, null, 0x447a0000, 0x447a0000, v12 v_div_scale_f32 v15, null, 0x447a0000, 0x447a0000, v13 v_div_scale_f32 v20, vcc_lo, v12, 0x447a0000, v12 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_rcp_f32_e32 v16, v14 v_rcp_f32_e32 v17, v15 s_waitcnt_depctr 0xfff v_fma_f32 v18, -v14, v16, 1.0 v_fma_f32 v19, -v15, v17, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_fmac_f32 v16, v18, v16 :: v_dual_fmac_f32 v17, v19, v17 v_div_scale_f32 v18, s0, v13, 0x447a0000, v13 v_mul_f32_e32 v19, v20, v16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v22, -v14, v19, v20 v_fmac_f32_e32 v19, v22, v16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v14, -v14, v19, v20 v_div_fmas_f32 v14, v14, v16, v19 s_mov_b32 vcc_lo, s0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fixup_f32 v12, v14, 0x447a0000, v12 v_dual_mul_f32 v21, v18, v17 :: v_dual_add_f32 v12, 0xbd4ac083, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v23, -v15, v21, v18 v_dual_add_f32 v8, v8, v12 :: v_dual_fmac_f32 v21, v23, v17 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v15, -v15, v21, v18 v_div_fmas_f32 v15, v15, v17, v21 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fixup_f32 v13, v15, 0x447a0000, v13 v_add_f32_e32 v13, 0xbd4ac083, v13 s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v7, v7, v13 v_cmpx_lt_f32_e32 v8, v6 s_cbranch_execz .LBB0_3 ; %bb.5: ; in Loop: Header=BB0_4 Depth=1 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4) v_trunc_f32_e32 v12, v7 v_trunc_f32_e32 v13, v8 v_cmp_le_f32_e32 vcc_lo, 0, v8 v_cmp_le_f32_e64 s0, 0, v7 v_cmp_lt_f32_e64 s1, v7, v6 v_dual_sub_f32 v12, v7, v12 :: v_dual_sub_f32 v13, v8, v13 s_delay_alu instid0(VALU_DEP_3) s_and_b32 s0, vcc_lo, s0 s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) s_and_b32 s0, s0, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v12, v12, v12 v_fmac_f32_e32 v12, v13, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_f32_e64 s2, v12, v9 s_and_b32 s0, s0, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 exec_lo, exec_lo, s0 s_cbranch_execz .LBB0_3 ; %bb.6: ; in Loop: Header=BB0_4 Depth=1 v_floor_f32_e32 v12, v7 v_floor_f32_e32 v13, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_i32_f32_e32 v12, v12 v_cvt_i32_f32_e32 v14, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v12, v12, s4 v_ashrrev_i32_e32 v15, 31, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[14:15], 3, v[14:15] v_ashrrev_i32_e32 v13, 31, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[12:13], 3, v[12:13] v_add_co_u32 v12, vcc_lo, v10, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_ci_u32_e32 v13, vcc_lo, v11, v13, vcc_lo v_add_co_u32 v12, vcc_lo, v12, v14 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v13, vcc_lo, v13, v15, vcc_lo global_load_b64 v[14:15], v[12:13], off s_waitcnt vmcnt(0) v_add_co_u32 v14, vcc_lo, v14, 1 v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo global_store_b64 v[12:13], v[14:15], off s_branch .LBB0_3 .LBB0_7: ; %..loopexit_crit_edge global_store_b32 v[0:1], v8, off global_store_b32 v[4:5], v7, off .LBB0_8: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10SimulationPfS_PKfS1_Pmmjif .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 320 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 24 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z10SimulationPfS_PKfS1_Pmmjif, .Lfunc_end0-_Z10SimulationPfS_PKfS1_Pmmjif ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1036 ; NumSgprs: 18 ; NumVgprs: 24 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 24 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 8 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: by_value - .offset: 52 .size: 4 .value_kind: by_value - .offset: 56 .size: 4 .value_kind: by_value - .offset: 64 .size: 4 .value_kind: hidden_block_count_x - .offset: 68 .size: 4 .value_kind: hidden_block_count_y - .offset: 72 .size: 4 .value_kind: hidden_block_count_z - .offset: 76 .size: 2 .value_kind: hidden_group_size_x - .offset: 78 .size: 2 .value_kind: hidden_group_size_y - .offset: 80 .size: 2 .value_kind: hidden_group_size_z - .offset: 82 .size: 2 .value_kind: hidden_remainder_x - .offset: 84 .size: 2 .value_kind: hidden_remainder_y - .offset: 86 .size: 2 .value_kind: hidden_remainder_z - .offset: 104 .size: 8 .value_kind: hidden_global_offset_x - .offset: 112 .size: 8 .value_kind: hidden_global_offset_y - .offset: 120 .size: 8 .value_kind: hidden_global_offset_z - .offset: 128 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 320 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10SimulationPfS_PKfS1_Pmmjif .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z10SimulationPfS_PKfS1_Pmmjif.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 24 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "9d107bc548b78ba1b14342243b35f5631d6371a4.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .p2align 4, 0x90 .type _Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function _Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rdi, %rbx movl $_ZSt4cout, %edi movl $.L.str, %esi movl $32, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB0_5 # %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r14) je .LBB0_3 # %bb.2: movzbl 67(%r14), %eax jmp .LBB0_4 .LBB0_3: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $8, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rsi movq 8(%rbx), %rdx movl $_ZSt4cout, %edi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $.L.str.2, %esi movl $42, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $26, %edx addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL .LBB0_5: .cfi_def_cfa_offset 32 callq _ZSt16__throw_bad_castv .Lfunc_end0: .size _Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end0-_Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .cfi_endproc # -- End function .globl _Z25__device_stub__SimulationPfS_PKfS1_Pmmjif # -- Begin function _Z25__device_stub__SimulationPfS_PKfS1_Pmmjif .p2align 4, 0x90 .type _Z25__device_stub__SimulationPfS_PKfS1_Pmmjif,@function _Z25__device_stub__SimulationPfS_PKfS1_Pmmjif: # @_Z25__device_stub__SimulationPfS_PKfS1_Pmmjif .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 104(%rsp) movq %rsi, 96(%rsp) movq %rdx, 88(%rsp) movq %rcx, 80(%rsp) movq %r8, 72(%rsp) movq %r9, 64(%rsp) movss %xmm0, 12(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 80(%rsp), %rax movq %rax, 136(%rsp) leaq 72(%rsp), %rax movq %rax, 144(%rsp) leaq 64(%rsp), %rax movq %rax, 152(%rsp) leaq 192(%rsp), %rax movq %rax, 160(%rsp) leaq 200(%rsp), %rax movq %rax, 168(%rsp) leaq 12(%rsp), %rax movq %rax, 176(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z10SimulationPfS_PKfS1_Pmmjif, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end1: .size _Z25__device_stub__SimulationPfS_PKfS1_Pmmjif, .Lfunc_end1-_Z25__device_stub__SimulationPfS_PKfS1_Pmmjif .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function _Z13motion_devicePfS_S_S_PPimmifPmi .LCPI2_0: .quad 0x3e112e0be826d695 # double 1.0000000000000001E-9 .text .globl _Z13motion_devicePfS_S_S_PPimmifPmi .p2align 4, 0x90 .type _Z13motion_devicePfS_S_S_PPimmifPmi,@function _Z13motion_devicePfS_S_S_PPimmifPmi: # @_Z13motion_devicePfS_S_S_PPimmifPmi .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $1752, %rsp # imm = 0x6D8 .cfi_def_cfa_offset 1808 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movss %xmm0, 64(%rsp) # 4-byte Spill movq %r9, %rbx movq %r8, %r14 movq %rcx, %r13 movq %rdx, %rbp movq %rsi, 104(%rsp) # 8-byte Spill movq %rdi, 96(%rsp) # 8-byte Spill leaq 280(%rsp), %r15 movq %r15, %rdi xorl %esi, %esi callq hipGetDevicePropertiesR0600 movl $_ZSt4cout, %edi movl $.L.str.4, %esi movl $12, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq %r15, %rdi callq strlen movl $_ZSt4cout, %edi movq %r15, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB2_49 # %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r15) je .LBB2_3 # %bb.2: movzbl 67(%r15), %eax jmp .LBB2_4 .LBB2_3: movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.5, %esi movl $35, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 600(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %r15 testq %r15, %r15 je .LBB2_49 # %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i85 cmpb $0, 56(%r15) je .LBB2_7 # %bb.6: movzbl 67(%r15), %ecx jmp .LBB2_8 .LBB2_7: movq %r15, %rdi movq %rax, %r12 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r12, %rax .LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit88 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.6, %esi movl $29, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl 1816(%rsp), %esi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %r15 testq %r15, %r15 je .LBB2_49 # %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i90 movl 1832(%rsp), %r12d cmpb $0, 56(%r15) movq %rbp, 24(%rsp) # 8-byte Spill je .LBB2_11 # %bb.10: movzbl 67(%r15), %ecx jmp .LBB2_12 .LBB2_11: movq %r15, %rdi movl %r12d, %ebp movq %rax, %r12 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r12, %rax movl %ebp, %r12d .LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit93 movq %r13, %rbp movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.7, %esi movl $35, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %r12d, %esi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %r15 testq %r15, %r15 je .LBB2_49 # %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i95 movq 1808(%rsp), %r13 cmpb $0, 56(%r15) je .LBB2_15 # %bb.14: movzbl 67(%r15), %ecx jmp .LBB2_16 .LBB2_15: movq %r15, %rdi movq %rax, %r12 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r12, %rax .LBB2_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit98 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.8, %esi movl $28, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movq %r13, %rsi callq _ZNSo9_M_insertImEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %r15 testq %r15, %r15 je .LBB2_49 # %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i100 cmpb $0, 56(%r15) je .LBB2_19 # %bb.18: movzbl 67(%r15), %ecx jmp .LBB2_20 .LBB2_19: movq %r15, %rdi movq %rax, %r12 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r12, %rax .LBB2_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit103 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $17, %edi callq srand movslq 1816(%rsp), %r15 movq %r15, 8(%rsp) # 8-byte Spill imulq %r13, %r15 testq %r15, %r15 movq %rbp, (%rsp) # 8-byte Spill movq 24(%rsp), %r12 # 8-byte Reload je .LBB2_23 # %bb.21: # %.lr.ph.preheader xorl %ebp, %ebp movabsq $2951479051793528259, %r13 # imm = 0x28F5C28F5C28F5C3 .p2align 4, 0x90 .LBB2_22: # %.lr.ph # =>This Inner Loop Header: Depth=1 callq rand movslq %eax, %rcx movq %rcx, %rax shrq $2, %rax mulq %r13 shrq $2, %rdx imull $100, %edx, %eax subl %eax, %ecx xorps %xmm0, %xmm0 cvtsi2ss %ecx, %xmm0 movss %xmm0, (%r12,%rbp,4) callq rand movslq %eax, %rcx movq %rcx, %rax shrq $2, %rax mulq %r13 shrq $2, %rdx imull $100, %edx, %eax subl %eax, %ecx xorps %xmm0, %xmm0 cvtsi2ss %ecx, %xmm0 movq (%rsp), %rax # 8-byte Reload movss %xmm0, (%rax,%rbp,4) incq %rbp cmpq %rbp, %r15 jne .LBB2_22 .LBB2_23: # %._crit_edge movq 1824(%rsp), %r15 movq 1808(%rsp), %r13 leaq (,%r13,4), %rbp movq 8(%rsp), %r13 # 8-byte Reload imulq %rbp, %r13 leaq 56(%rsp), %rdi movq %r13, %rsi callq hipMalloc leaq 48(%rsp), %rdi movq %r13, %rsi callq hipMalloc leaq 40(%rsp), %rdi movq %rbp, %rsi callq hipMalloc leaq 32(%rsp), %rdi movq %rbp, %rsi callq hipMalloc movq %rbx, %rax imulq %rbx, %rax movq %rax, 80(%rsp) # 8-byte Spill movq %rax, %rsi imulq 1808(%rsp), %rsi shlq $3, %rsi leaq 16(%rsp), %rdi movq %rsi, 8(%rsp) # 8-byte Spill callq hipMalloc movq 56(%rsp), %rdi movq %r12, %rsi movq %r13, %rdx movl $1, %ecx callq hipMemcpy movq 48(%rsp), %rdi movq (%rsp), %rsi # 8-byte Reload movq %r13, %rdx movl $1, %ecx callq hipMemcpy movl 1832(%rsp), %r12d testl %r12d, %r12d jle .LBB2_24 # %bb.45: # %.lr.ph126 movabsq $4294967296, %rcx # imm = 0x100000000 movq 1808(%rsp), %rax addq $255, %rax shrq $8, %rax movl %eax, %eax orq %rcx, %rax movq %rax, 88(%rsp) # 8-byte Spill xorps %xmm0, %xmm0 addq $256, %rcx # imm = 0x100 movq %rcx, 24(%rsp) # 8-byte Spill jmp .LBB2_46 .p2align 4, 0x90 .LBB2_48: # in Loop: Header=BB2_46 Depth=1 callq hipDeviceSynchronize callq _ZNSt6chrono3_V212steady_clock3nowEv subq %r13, %rax xorps %xmm0, %xmm0 cvtsi2sd %rax, %xmm0 movsd (%rsp), %xmm1 # 8-byte Reload # xmm1 = mem[0],zero addsd %xmm0, %xmm1 movapd %xmm1, %xmm0 decl %r12d je .LBB2_25 .LBB2_46: # =>This Inner Loop Header: Depth=1 movsd %xmm0, (%rsp) # 8-byte Spill movq 40(%rsp), %rdi movq 96(%rsp), %rsi # 8-byte Reload movq %rbp, %rdx movl $1, %ecx callq hipMemcpy movq 32(%rsp), %rdi movq 104(%rsp), %rsi # 8-byte Reload movq %rbp, %rdx movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi movq %r15, %rsi movq 8(%rsp), %rdx # 8-byte Reload movl $1, %ecx callq hipMemcpy callq hipDeviceSynchronize callq _ZNSt6chrono3_V212steady_clock3nowEv movq %rax, %r13 movq 88(%rsp), %rdi # 8-byte Reload movl $1, %esi movq 24(%rsp), %rdx # 8-byte Reload movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_48 # %bb.47: # in Loop: Header=BB2_46 Depth=1 movq 40(%rsp), %rax movq %rax, 200(%rsp) movq 32(%rsp), %rax movq %rax, 192(%rsp) movq 56(%rsp), %rax movq %rax, 184(%rsp) movq 48(%rsp), %rax movq %rax, 176(%rsp) movq 16(%rsp), %rax movq %rax, 168(%rsp) movq 1808(%rsp), %rax movq %rax, 160(%rsp) movl 1816(%rsp), %eax movl %eax, 76(%rsp) movl %ebx, 72(%rsp) movss 64(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, 68(%rsp) leaq 200(%rsp), %rax movq %rax, 208(%rsp) leaq 192(%rsp), %rax movq %rax, 216(%rsp) leaq 184(%rsp), %rax movq %rax, 224(%rsp) leaq 176(%rsp), %rax movq %rax, 232(%rsp) leaq 168(%rsp), %rax movq %rax, 240(%rsp) leaq 160(%rsp), %rax movq %rax, 248(%rsp) leaq 76(%rsp), %rax movq %rax, 256(%rsp) leaq 72(%rsp), %rax movq %rax, 264(%rsp) leaq 68(%rsp), %rax movq %rax, 272(%rsp) leaq 144(%rsp), %rdi leaq 128(%rsp), %rsi leaq 120(%rsp), %rdx leaq 112(%rsp), %rcx callq __hipPopCallConfiguration movq 144(%rsp), %rsi movl 152(%rsp), %edx movq 128(%rsp), %rcx movl 136(%rsp), %r8d movl $_Z10SimulationPfS_PKfS1_Pmmjif, %edi leaq 208(%rsp), %r9 pushq 112(%rsp) .cfi_adjust_cfa_offset 8 pushq 128(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 jmp .LBB2_48 .LBB2_25: # %._crit_edge127.loopexit mulsd .LCPI2_0(%rip), %xmm0 jmp .LBB2_26 .LBB2_24: xorps %xmm0, %xmm0 .LBB2_26: # %._crit_edge127 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r12 testq %r12, %r12 movl 1832(%rsp), %ebp je .LBB2_49 # %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i105 movsd %xmm0, (%rsp) # 8-byte Spill cmpb $0, 56(%r12) je .LBB2_29 # %bb.28: movzbl 67(%r12), %eax jmp .LBB2_30 .LBB2_29: movq %r12, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r12), %rax movq %r12, %rdi movl $10, %esi callq *48(%rax) .LBB2_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit108 movq 1808(%rsp), %r13 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.9, %esi movl $31, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm1, %xmm1 cvtsi2sd %ebp, %xmm1 movsd (%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero divsd %xmm1, %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movl $.L.str.10, %esi movl $4, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r12 testq %r12, %r12 je .LBB2_49 # %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i110 cmpb $0, 56(%r12) je .LBB2_33 # %bb.32: movzbl 67(%r12), %eax jmp .LBB2_34 .LBB2_33: movq %r12, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r12), %rax movq %r12, %rdi movl $10, %esi callq *48(%rax) .LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit113 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 16(%rsp), %rsi movq %r15, %rdi movq 8(%rsp), %rdx # 8-byte Reload movl $2, %ecx callq hipMemcpy testq %r13, %r13 movq 80(%rsp), %r10 # 8-byte Reload je .LBB2_44 # %bb.35: # %.preheader121.lr.ph shlq $3, %r10 leaq (,%rbx,8), %rax xorl %ecx, %ecx jmp .LBB2_36 .p2align 4, 0x90 .LBB2_43: # %._crit_edge131 # in Loop: Header=BB2_36 Depth=1 incq %rcx addq %r10, %r15 cmpq %r13, %rcx je .LBB2_44 .LBB2_36: # %.preheader121 # =>This Loop Header: Depth=1 # Child Loop BB2_38 Depth 2 # Child Loop BB2_39 Depth 3 testq %rbx, %rbx je .LBB2_43 # %bb.37: # %.preheader.lr.ph # in Loop: Header=BB2_36 Depth=1 movq %r15, %rdx xorl %esi, %esi jmp .LBB2_38 .p2align 4, 0x90 .LBB2_42: # in Loop: Header=BB2_38 Depth=2 incq %rsi addq %rax, %rdx cmpq %rbx, %rsi je .LBB2_43 .LBB2_38: # %.preheader # Parent Loop BB2_36 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB2_39 Depth 3 xorl %edi, %edi jmp .LBB2_39 .p2align 4, 0x90 .LBB2_41: # in Loop: Header=BB2_39 Depth=3 incq %rdi cmpq %rdi, %rbx je .LBB2_42 .LBB2_39: # Parent Loop BB2_36 Depth=1 # Parent Loop BB2_38 Depth=2 # => This Inner Loop Header: Depth=3 movq (%rdx,%rdi,8), %r8 testq %r8, %r8 je .LBB2_41 # %bb.40: # in Loop: Header=BB2_39 Depth=3 movq (%r14,%rsi,8), %r9 addl %r8d, (%r9,%rdi,4) jmp .LBB2_41 .LBB2_44: # %._crit_edge133 movq 56(%rsp), %rdi callq hipFree movq 48(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree addq $1752, %rsp # imm = 0x6D8 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_49: .cfi_def_cfa_offset 1808 callq _ZSt16__throw_bad_castv .Lfunc_end2: .size _Z13motion_devicePfS_S_S_PPimmifPmi, .Lfunc_end2-_Z13motion_devicePfS_S_S_PPimmifPmi .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI3_0: .long 0x3f000000 # float 0.5 .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI3_1: .quad 0x3e112e0be826d695 # double 1.0000000000000001E-9 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $104, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %r15 cmpl $3, %edi jne .LBB3_10 # %bb.1: movq 8(%r15), %rbx leaq 16(%rsp), %r13 movq %r13, (%rsp) testq %rbx, %rbx je .LBB3_76 # %bb.2: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq strlen movq %rax, %r14 cmpq $16, %rax jb .LBB3_7 # %bb.3: testq %r14, %r14 js .LBB3_92 # %bb.4: movq %r14, %rdi incq %rdi js .LBB3_71 # %bb.5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i81 .Ltmp3: .cfi_escape 0x2e, 0x00 callq _Znwm .Ltmp4: # %bb.6: # %.noexc87 movq %rax, (%rsp) movq %r14, 16(%rsp) .LBB3_7: testq %r14, %r14 je .LBB3_23 # %bb.8: movq (%rsp), %rdi cmpq $1, %r14 jne .LBB3_22 # %bb.9: movzbl (%rbx), %eax movb %al, (%rdi) jmp .LBB3_23 .LBB3_10: movq (%r15), %rbx leaq 80(%rsp), %r15 movq %r15, 64(%rsp) testq %rbx, %rbx je .LBB3_78 # %bb.11: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq strlen movq %rax, %r14 cmpq $16, %rax jb .LBB3_15 # %bb.12: testq %r14, %r14 js .LBB3_94 # %bb.13: movq %r14, %rdi incq %rdi js .LBB3_73 # %bb.14: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i .cfi_escape 0x2e, 0x00 callq _Znwm movq %rax, 64(%rsp) movq %r14, 80(%rsp) .LBB3_15: testq %r14, %r14 je .LBB3_19 # %bb.16: movq 64(%rsp), %rdi cmpq $1, %r14 jne .LBB3_18 # %bb.17: movzbl (%rbx), %eax movb %al, (%rdi) jmp .LBB3_19 .LBB3_18: .cfi_escape 0x2e, 0x00 movq %rbx, %rsi movq %r14, %rdx callq memcpy@PLT .LBB3_19: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit movq %r14, 72(%rsp) movq 64(%rsp), %rax movb $0, (%rax,%r14) .Ltmp0: .cfi_escape 0x2e, 0x00 leaq 64(%rsp), %rdi callq _Z5usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .Ltmp1: # %bb.20: movq 64(%rsp), %rdi movl $1, %eax cmpq %r15, %rdi je .LBB3_70 # %bb.21: # %.critedge.i.i .cfi_escape 0x2e, 0x00 callq _ZdlPv movl $1, %eax jmp .LBB3_70 .LBB3_22: .cfi_escape 0x2e, 0x00 movq %rbx, %rsi movq %r14, %rdx callq memcpy@PLT .LBB3_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit88 movq %r14, 8(%rsp) movq (%rsp), %rax movb $0, (%rax,%r14) movq (%rsp), %r12 .cfi_escape 0x2e, 0x00 callq __errno_location movq %rax, %rbx movl (%rax), %ebp movl $0, (%rax) .cfi_escape 0x2e, 0x00 leaq 32(%rsp), %rsi movq %r12, %rdi movl $10, %edx callq __isoc23_strtol cmpq %r12, 32(%rsp) je .LBB3_79 # %bb.24: movq %rax, %r14 movslq %r14d, %rax cmpq %r14, %rax jne .LBB3_81 # %bb.25: movl (%rbx), %eax cmpl $34, %eax je .LBB3_81 # %bb.26: testl %eax, %eax jne .LBB3_28 # %bb.27: movl %ebp, (%rbx) .LBB3_28: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit movq (%rsp), %rdi cmpq %r13, %rdi je .LBB3_30 # %bb.29: # %.critedge.i.i90 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB3_30: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit92 movq 16(%r15), %r15 movq %r13, (%rsp) testq %r15, %r15 je .LBB3_83 # %bb.31: .cfi_escape 0x2e, 0x00 movq %r15, %rdi callq strlen movq %rax, %r12 cmpq $16, %rax jb .LBB3_36 # %bb.32: testq %r12, %r12 js .LBB3_95 # %bb.33: movq %r12, %rdi incq %rdi js .LBB3_74 # %bb.34: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i93 .Ltmp5: .cfi_escape 0x2e, 0x00 callq _Znwm .Ltmp6: # %bb.35: # %.noexc99 movq %rax, (%rsp) movq %r12, 16(%rsp) .LBB3_36: testq %r12, %r12 je .LBB3_40 # %bb.37: movq (%rsp), %rdi cmpq $1, %r12 jne .LBB3_39 # %bb.38: movzbl (%r15), %eax movb %al, (%rdi) jmp .LBB3_40 .LBB3_39: .cfi_escape 0x2e, 0x00 movq %r15, %rsi movq %r12, %rdx callq memcpy@PLT .LBB3_40: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit100 movq %r12, 8(%rsp) movq (%rsp), %rax movb $0, (%rax,%r12) movq (%rsp), %r12 movl (%rbx), %ebp movl $0, (%rbx) .cfi_escape 0x2e, 0x00 leaq 32(%rsp), %rsi movq %r12, %rdi movl $10, %edx callq __isoc23_strtol cmpq %r12, 32(%rsp) je .LBB3_85 # %bb.41: movabsq $-4294967296, %rdx # imm = 0xFFFFFFFF00000000 leaq -2147483648(%rax), %rcx cmpq %rdx, %rcx jb .LBB3_87 # %bb.42: movl (%rbx), %ecx cmpl $34, %ecx je .LBB3_87 # %bb.43: movq %rax, 96(%rsp) # 8-byte Spill testl %ecx, %ecx jne .LBB3_45 # %bb.44: movl %ebp, (%rbx) .LBB3_45: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit106 movq (%rsp), %rdi cmpq %r13, %rdi je .LBB3_47 # %bb.46: # %.critedge.i.i107 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB3_47: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit109 .cfi_escape 0x2e, 0x00 movl $168, %edi callq _Znam movq %rax, %rbx xorl %r15d, %r15d .p2align 4, 0x90 .LBB3_48: # =>This Inner Loop Header: Depth=1 .cfi_escape 0x2e, 0x00 movl $84, %edi callq _Znam movq %rax, (%rbx,%r15,8) incq %r15 cmpq $21, %r15 jne .LBB3_48 # %bb.49: movslq %r14d, %rax movq %rax, %rcx shlq $14, %rcx leaq (%rcx,%rcx,8), %rcx shrq $62, %rcx shlq $16, %rax leaq (%rax,%rax,8), %rax xorl %r15d, %r15d negq %rcx movl $0, %r12d sbbq %r12, %r12 orq %rax, %r12 .cfi_escape 0x2e, 0x00 movq %r12, %rdi callq _Znam movq %rax, 56(%rsp) # 8-byte Spill .cfi_escape 0x2e, 0x00 movq %r12, %rdi callq _Znam movq %rax, 48(%rsp) # 8-byte Spill .cfi_escape 0x2e, 0x00 movl $589824, %edi # imm = 0x90000 callq _Znam movq %rax, %r13 .cfi_escape 0x2e, 0x00 movl $589824, %edi # imm = 0x90000 callq _Znam movq %rax, %rbp .cfi_escape 0x2e, 0x00 movl $520224768, %edi # imm = 0x1F020000 callq _Znam .cfi_escape 0x2e, 0x00 movl $520224768, %edx # imm = 0x1F020000 movq %rax, 40(%rsp) # 8-byte Spill movq %rax, %rdi xorl %esi, %esi callq memset@PLT .p2align 4, 0x90 .LBB3_50: # =>This Inner Loop Header: Depth=1 movl $1092616192, (%r13,%r15,4) # imm = 0x41200000 movl $1092616192, (%rbp,%r15,4) # imm = 0x41200000 incq %r15 cmpq $147456, %r15 # imm = 0x24000 jne .LBB3_50 # %bb.51: # %.preheader.preheader xorl %eax, %eax xorps %xmm0, %xmm0 .p2align 4, 0x90 .LBB3_52: # %.preheader # =>This Inner Loop Header: Depth=1 movq (%rbx,%rax,8), %rcx movups %xmm0, 64(%rcx) movups %xmm0, 48(%rcx) movups %xmm0, 32(%rcx) movups %xmm0, 16(%rcx) movups %xmm0, (%rcx) movl $0, 80(%rcx) incq %rax cmpq $21, %rax jne .LBB3_52 # %bb.53: .cfi_escape 0x2e, 0x00 callq _ZNSt6chrono3_V212steady_clock3nowEv movq %rax, %r12 .cfi_escape 0x2e, 0x20 movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movl $21, %r9d movq %r13, %rdi movq %rbp, %rsi movq 56(%rsp), %rdx # 8-byte Reload movq 48(%rsp), %rcx # 8-byte Reload movq %rbx, %r8 pushq 96(%rsp) # 8-byte Folded Reload .cfi_adjust_cfa_offset 8 pushq 48(%rsp) # 8-byte Folded Reload .cfi_adjust_cfa_offset 8 pushq %r14 .cfi_adjust_cfa_offset 8 pushq $147456 # imm = 0x24000 .cfi_adjust_cfa_offset 8 callq _Z13motion_devicePfS_S_S_PPimmifPmi addq $32, %rsp .cfi_adjust_cfa_offset -32 .cfi_escape 0x2e, 0x00 callq _ZNSt6chrono3_V212steady_clock3nowEv movq %rax, %r14 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB3_89 # %bb.54: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i subq %r12, %r14 cmpb $0, 56(%r15) je .LBB3_56 # %bb.55: movzbl 67(%r15), %eax jmp .LBB3_57 .LBB3_56: .cfi_escape 0x2e, 0x00 movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax .cfi_escape 0x2e, 0x00 movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB3_57: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit .cfi_escape 0x2e, 0x00 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq _ZNSo5flushEv .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.11, %esi movl $17, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorps %xmm0, %xmm0 cvtsi2sd %r14, %xmm0 mulsd .LCPI3_1(%rip), %xmm0 .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ .cfi_escape 0x2e, 0x00 movl $.L.str.12, %esi movl $5, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB3_90 # %bb.58: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i117 cmpb $0, 56(%r14) je .LBB3_60 # %bb.59: movzbl 67(%r14), %eax jmp .LBB3_61 .LBB3_60: .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax .cfi_escape 0x2e, 0x00 movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB3_61: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit120 .cfi_escape 0x2e, 0x00 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq _ZNSo5flushEv .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.13, %esi movl $38, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB3_91 # %bb.62: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i122 cmpb $0, 56(%r14) je .LBB3_64 # %bb.63: movzbl 67(%r14), %eax jmp .LBB3_65 .LBB3_64: .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax .cfi_escape 0x2e, 0x00 movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB3_65: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit125 .cfi_escape 0x2e, 0x00 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq _ZNSo5flushEv .cfi_escape 0x2e, 0x00 movl $21, %esi movl $21, %edx movq %rbx, %rdi callq _Z12print_matrixIiEvPPT_mm xorl %r14d, %r14d jmp .LBB3_67 .p2align 4, 0x90 .LBB3_66: # in Loop: Header=BB3_67 Depth=1 incq %r14 cmpq $21, %r14 je .LBB3_69 .LBB3_67: # =>This Inner Loop Header: Depth=1 movq (%rbx,%r14,8), %rdi testq %rdi, %rdi je .LBB3_66 # %bb.68: # in Loop: Header=BB3_67 Depth=1 .cfi_escape 0x2e, 0x00 callq _ZdlPv jmp .LBB3_66 .LBB3_69: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _ZdaPv .cfi_escape 0x2e, 0x00 movq %r13, %rdi callq _ZdaPv .cfi_escape 0x2e, 0x00 movq %rbp, %rdi callq _ZdaPv .cfi_escape 0x2e, 0x00 movq 56(%rsp), %rdi # 8-byte Reload callq _ZdaPv .cfi_escape 0x2e, 0x00 movq 48(%rsp), %rdi # 8-byte Reload callq _ZdaPv .cfi_escape 0x2e, 0x00 movq 40(%rsp), %rdi # 8-byte Reload callq _ZdaPv xorl %eax, %eax .LBB3_70: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit addq $104, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB3_71: # %.noexc11.i82 .cfi_def_cfa_offset 160 .Ltmp24: .cfi_escape 0x2e, 0x00 callq _ZSt17__throw_bad_allocv .Ltmp25: # %bb.72: # %.noexc86 .LBB3_73: # %.noexc11.i .cfi_escape 0x2e, 0x00 callq _ZSt17__throw_bad_allocv .LBB3_74: # %.noexc11.i94 .Ltmp12: .cfi_escape 0x2e, 0x00 callq _ZSt17__throw_bad_allocv .Ltmp13: # %bb.75: # %.noexc98 .LBB3_76: .Ltmp28: .cfi_escape 0x2e, 0x00 movl $.L.str.14, %edi callq _ZSt19__throw_logic_errorPKc .Ltmp29: # %bb.77: # %.noexc84 .LBB3_78: # %.noexc .cfi_escape 0x2e, 0x00 movl $.L.str.14, %edi callq _ZSt19__throw_logic_errorPKc .LBB3_79: .Ltmp21: .cfi_escape 0x2e, 0x00 movl $.L.str.16, %edi callq _ZSt24__throw_invalid_argumentPKc .Ltmp22: # %bb.80: .LBB3_81: # %.critedge.i.i89 .Ltmp19: .cfi_escape 0x2e, 0x00 movl $.L.str.16, %edi callq _ZSt20__throw_out_of_rangePKc .Ltmp20: # %bb.82: .LBB3_83: .Ltmp16: .cfi_escape 0x2e, 0x00 movl $.L.str.14, %edi callq _ZSt19__throw_logic_errorPKc .Ltmp17: # %bb.84: # %.noexc96 .LBB3_85: .Ltmp9: .cfi_escape 0x2e, 0x00 movl $.L.str.16, %edi callq _ZSt24__throw_invalid_argumentPKc .Ltmp10: # %bb.86: .LBB3_87: # %.critedge.i.i102 .Ltmp7: .cfi_escape 0x2e, 0x00 movl $.L.str.16, %edi callq _ZSt20__throw_out_of_rangePKc .Ltmp8: # %bb.88: .LBB3_89: .cfi_escape 0x2e, 0x00 callq _ZSt16__throw_bad_castv .LBB3_90: .cfi_escape 0x2e, 0x00 callq _ZSt16__throw_bad_castv .LBB3_91: .cfi_escape 0x2e, 0x00 callq _ZSt16__throw_bad_castv .LBB3_92: # %.noexc.i83 .Ltmp26: .cfi_escape 0x2e, 0x00 movl $.L.str.15, %edi callq _ZSt20__throw_length_errorPKc .Ltmp27: # %bb.93: # %.noexc85 .LBB3_94: # %.noexc.i .cfi_escape 0x2e, 0x00 movl $.L.str.15, %edi callq _ZSt20__throw_length_errorPKc .LBB3_95: # %.noexc.i95 .Ltmp14: .cfi_escape 0x2e, 0x00 movl $.L.str.15, %edi callq _ZSt20__throw_length_errorPKc .Ltmp15: # %bb.96: # %.noexc97 .LBB3_97: .Ltmp2: movq %rax, %rbx movq 64(%rsp), %rdi cmpq %r15, %rdi je .LBB3_99 # %bb.98: # %.critedge.i.i78 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB3_99: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit80 movq %rbx, %rdi .cfi_escape 0x2e, 0x00 callq _Unwind_Resume@PLT .LBB3_100: .Ltmp11: movq %rax, %r14 cmpl $0, (%rbx) jne .LBB3_102 # %bb.101: movl %ebp, (%rbx) .LBB3_102: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i103 movq (%rsp), %rdi cmpq %r13, %rdi je .LBB3_109 # %bb.103: # %.critedge.i.i113 .cfi_escape 0x2e, 0x00 jmp .LBB3_108 .LBB3_104: .Ltmp23: movq %rax, %r14 cmpl $0, (%rbx) jne .LBB3_106 # %bb.105: movl %ebp, (%rbx) .LBB3_106: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i movq (%rsp), %rdi cmpq %r13, %rdi je .LBB3_109 # %bb.107: # %.critedge.i.i110 .cfi_escape 0x2e, 0x00 .LBB3_108: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit112 callq _ZdlPv .LBB3_109: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit112 movq %r14, %rdi .cfi_escape 0x2e, 0x00 callq _Unwind_Resume@PLT .LBB3_110: .Ltmp18: movq %rax, %rdi .cfi_escape 0x2e, 0x00 callq _Unwind_Resume@PLT .LBB3_111: .Ltmp30: movq %rax, %rdi .cfi_escape 0x2e, 0x00 callq _Unwind_Resume@PLT .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table3: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4 .uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30 .byte 0 # On action: cleanup .uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp0-.Ltmp4 # Call between .Ltmp4 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1 .uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2 .byte 0 # On action: cleanup .uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp5-.Ltmp1 # Call between .Ltmp1 and .Ltmp5 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6 .uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18 .byte 0 # On action: cleanup .uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Ltmp24-.Ltmp6 # Call between .Ltmp6 and .Ltmp24 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 7 << .uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25 .uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30 .byte 0 # On action: cleanup .uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 8 << .uleb128 .Ltmp12-.Ltmp25 # Call between .Ltmp25 and .Ltmp12 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 9 << .uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13 .uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18 .byte 0 # On action: cleanup .uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 10 << .uleb128 .Ltmp29-.Ltmp28 # Call between .Ltmp28 and .Ltmp29 .uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30 .byte 0 # On action: cleanup .uleb128 .Ltmp29-.Lfunc_begin0 # >> Call Site 11 << .uleb128 .Ltmp21-.Ltmp29 # Call between .Ltmp29 and .Ltmp21 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 12 << .uleb128 .Ltmp20-.Ltmp21 # Call between .Ltmp21 and .Ltmp20 .uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23 .byte 0 # On action: cleanup .uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 13 << .uleb128 .Ltmp17-.Ltmp16 # Call between .Ltmp16 and .Ltmp17 .uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18 .byte 0 # On action: cleanup .uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 14 << .uleb128 .Ltmp8-.Ltmp9 # Call between .Ltmp9 and .Ltmp8 .uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11 .byte 0 # On action: cleanup .uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 15 << .uleb128 .Ltmp26-.Ltmp8 # Call between .Ltmp8 and .Ltmp26 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 16 << .uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27 .uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30 .byte 0 # On action: cleanup .uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 17 << .uleb128 .Ltmp14-.Ltmp27 # Call between .Ltmp27 and .Ltmp14 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 18 << .uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15 .uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18 .byte 0 # On action: cleanup .uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 19 << .uleb128 .Lfunc_end3-.Ltmp15 # Call between .Ltmp15 and .Lfunc_end3 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .p2align 2, 0x0 # -- End function .section .text._Z12print_matrixIiEvPPT_mm,"axG",@progbits,_Z12print_matrixIiEvPPT_mm,comdat .weak _Z12print_matrixIiEvPPT_mm # -- Begin function _Z12print_matrixIiEvPPT_mm .p2align 4, 0x90 .type _Z12print_matrixIiEvPPT_mm,@function _Z12print_matrixIiEvPPT_mm: # @_Z12print_matrixIiEvPPT_mm .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r12 testq %r12, %r12 je .LBB4_15 # %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i movq %rdx, %rbx movq %rsi, %r14 movq %rdi, %r15 cmpb $0, 56(%r12) je .LBB4_3 # %bb.2: movzbl 67(%r12), %eax jmp .LBB4_4 .LBB4_3: movq %r12, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r12), %rax movq %r12, %rdi movl $10, %esi callq *48(%rax) .LBB4_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv testq %r14, %r14 je .LBB4_14 # %bb.5: # %.preheader.lr.ph xorl %r13d, %r13d jmp .LBB4_6 .p2align 4, 0x90 .LBB4_12: # in Loop: Header=BB4_6 Depth=1 movq %r12, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r12), %rax movq %r12, %rdi movl $10, %esi callq *48(%rax) .LBB4_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit13 # in Loop: Header=BB4_6 Depth=1 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv incq %r13 cmpq %r14, %r13 je .LBB4_14 .LBB4_6: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB4_8 Depth 2 testq %rbx, %rbx je .LBB4_9 # %bb.7: # %.lr.ph # in Loop: Header=BB4_6 Depth=1 xorl %r12d, %r12d .p2align 4, 0x90 .LBB4_8: # Parent Loop BB4_6 Depth=1 # => This Inner Loop Header: Depth=2 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq $3, _ZSt4cout+16(%rax) movq (%r15,%r13,8), %rax movl (%rax,%r12,4), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movl $.L.str.17, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l incq %r12 cmpq %r12, %rbx jne .LBB4_8 .LBB4_9: # %._crit_edge # in Loop: Header=BB4_6 Depth=1 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r12 testq %r12, %r12 je .LBB4_15 # %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i10 # in Loop: Header=BB4_6 Depth=1 cmpb $0, 56(%r12) je .LBB4_12 # %bb.11: # in Loop: Header=BB4_6 Depth=1 movzbl 67(%r12), %eax jmp .LBB4_13 .LBB4_14: # %._crit_edge17 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB4_15: .cfi_def_cfa_offset 48 callq _ZSt16__throw_bad_castv .Lfunc_end4: .size _Z12print_matrixIiEvPPT_mm, .Lfunc_end4-_Z12print_matrixIiEvPPT_mm .cfi_endproc # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB5_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB5_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10SimulationPfS_PKfS1_Pmmjif, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end5: .size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB6_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB6_2: retq .Lfunc_end6: .size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz " Incorrect number of parameters " .size .L.str, 33 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " Usage: " .size .L.str.1, 9 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz " <Number of iterations within the kernel> " .size .L.str.2, 43 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "<Kernel execution count>\n\n" .size .L.str.3, 27 .type _Z10SimulationPfS_PKfS1_Pmmjif,@object # @_Z10SimulationPfS_PKfS1_Pmmjif .section .rodata,"a",@progbits .globl _Z10SimulationPfS_PKfS1_Pmmjif .p2align 3, 0x0 _Z10SimulationPfS_PKfS1_Pmmjif: .quad _Z25__device_stub__SimulationPfS_PKfS1_Pmmjif .size _Z10SimulationPfS_PKfS1_Pmmjif, 8 .type .L.str.4,@object # @.str.4 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.4: .asciz " Running on " .size .L.str.4, 13 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz " The Device Max Work Group Size is " .size .L.str.5, 36 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz " The number of iterations is " .size .L.str.6, 30 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz " The number of kernel execution is " .size .L.str.7, 36 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz " The number of particles is " .size .L.str.8, 29 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Average kernel execution time: " .size .L.str.9, 32 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz " (s)" .size .L.str.10, 5 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "Simulation time: " .size .L.str.11, 18 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz " (s) " .size .L.str.12, 6 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz "\n ********************** OUTPUT GRID: " .size .L.str.13, 39 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz "basic_string: construction from null is not valid" .size .L.str.14, 50 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "basic_string::_M_create" .size .L.str.15, 24 .type .L.str.16,@object # @.str.16 .L.str.16: .asciz "stoi" .size .L.str.16, 5 .type .L.str.17,@object # @.str.17 .L.str.17: .asciz " " .size .L.str.17, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z10SimulationPfS_PKfS1_Pmmjif" .size .L__unnamed_1, 31 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__SimulationPfS_PKfS1_Pmmjif .addrsig_sym __gxx_personality_v0 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Unwind_Resume .addrsig_sym _ZSt4cout .addrsig_sym _Z10SimulationPfS_PKfS1_Pmmjif .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
9,473
19,099
6,559
24,068
150
code for sm_80 Function : _Z8setValuePcic .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_TID.X ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @P0 EXIT ; LDC.S8 R5, c[0x0][0x16c] ; ULDC UR5, c[0x0][0x168] ; ULDC.64 UR6, c[0x0][0x160] ; UIADD3 UR4, UP0, UR5, UR6, URZ ; ULEA.HI.X.SX32 UR5, UR5, UR7, 0x1, UP0 ; MOV R2, UR4 ; IMAD.U32 R3, RZ, RZ, UR5 ; ULDC.64 UR4, c[0x0][0x118] ; PRMT R5, R5, 0x7710, RZ ; STG.E.U8 [R2.64], R5 ; EXIT ; BRA 0xf0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00027025_00000000-6_231073f531341b9ccd42ab4f67f21af60c51a7df.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4316: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4316: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z29__device_stub__Z8setValuePcicPcic .type _Z29__device_stub__Z8setValuePcicPcic, @function _Z29__device_stub__Z8setValuePcicPcic: .LFB4338: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movb %dl, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z8setValuePcic(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE4338: .size _Z29__device_stub__Z8setValuePcicPcic, .-_Z29__device_stub__Z8setValuePcicPcic .globl _Z8setValuePcic .type _Z8setValuePcic, @function _Z8setValuePcic: .LFB4339: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movsbl %dl, %edx call _Z29__device_stub__Z8setValuePcicPcic addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4339: .size _Z8setValuePcic, .-_Z8setValuePcic .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "hostChars[2] " .text .globl main .type main, @function main: .LFB4313: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $48, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movq %rsp, %rdi movl $1024, %esi call cudaMalloc@PLT movl $32, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $32, 12(%rsp) movl $1, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $0, %r8d movq 24(%rsp), %rdx movl $1, %ecx movq 12(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L16 .L12: leaq 36(%rsp), %rdi movl $2, %ecx movl $4, %edx movq (%rsp), %rsi call cudaMemcpy@PLT leaq .LC0(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movsbl 38(%rsp), %esi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $32, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $32, 12(%rsp) movl $1, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $0, %r8d movq 24(%rsp), %rdx movl $1, %ecx movq 12(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L17 .L13: leaq 36(%rsp), %rbx movl $2, %ecx movl $4, %edx movq (%rsp), %rsi movq %rbx, %rdi call cudaMemcpy@PLT leaq .LC0(%rip), %r12 movq %r12, %rsi leaq _ZSt4cout(%rip), %rbp movq %rbp, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movsbl 38(%rsp), %esi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movb $44, 38(%rsp) movl $1, %ecx movl $4, %edx movq %rbx, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movb $55, 38(%rsp) movl $2, %ecx movl $4, %edx movq (%rsp), %rsi movq %rbx, %rdi call cudaMemcpy@PLT movq %r12, %rsi movq %rbp, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movsbl 38(%rsp), %esi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq (%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L18 movl $0, %eax addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L16: .cfi_restore_state movl $89, %edx movl $2, %esi movq (%rsp), %rdi call _Z29__device_stub__Z8setValuePcicPcic jmp .L12 .L17: movl $23, %edx movl $2, %esi movq (%rsp), %rdi call _Z29__device_stub__Z8setValuePcicPcic jmp .L13 .L18: call __stack_chk_fail@PLT .cfi_endproc .LFE4313: .size main, .-main .section .rodata.str1.1 .LC1: .string "_Z8setValuePcic" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4341: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z8setValuePcic(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4341: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z8setValuePcic ; -- Begin function _Z8setValuePcic .globl _Z8setValuePcic .p2align 8 .type _Z8setValuePcic,@function _Z8setValuePcic: ; @_Z8setValuePcic ; %bb.0: s_mov_b32 s2, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b128 s[0:3], s[0:1], 0x0 s_waitcnt lgkmcnt(0) v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3 s_ashr_i32 s3, s2, 31 s_add_u32 s0, s0, s2 s_addc_u32 s1, s1, s3 global_store_b8 v0, v1, s[0:1] .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z8setValuePcic .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 4 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z8setValuePcic, .Lfunc_end0-_Z8setValuePcic ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 64 ; NumSgprs: 4 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 4 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 1 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z8setValuePcic .private_segment_fixed_size: 0 .sgpr_count: 4 .sgpr_spill_count: 0 .symbol: _Z8setValuePcic.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "231073f531341b9ccd42ab4f67f21af60c51a7df.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z23__device_stub__setValuePcic # -- Begin function _Z23__device_stub__setValuePcic .p2align 4, 0x90 .type _Z23__device_stub__setValuePcic,@function _Z23__device_stub__setValuePcic: # @_Z23__device_stub__setValuePcic .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) movb %dl, 3(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) leaq 3(%rsp), %rax movq %rax, 80(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z8setValuePcic, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z23__device_stub__setValuePcic, .Lfunc_end0-_Z23__device_stub__setValuePcic .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $112, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movabsq $4294967328, %rbx # imm = 0x100000020 leaq 16(%rsp), %rdi movl $1024, %esi # imm = 0x400 callq hipMalloc movq %rbx, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 16(%rsp), %rax movq %rax, 104(%rsp) movl $2, 28(%rsp) movb $89, 11(%rsp) leaq 104(%rsp), %rax movq %rax, 32(%rsp) leaq 28(%rsp), %rax movq %rax, 40(%rsp) leaq 11(%rsp), %rax movq %rax, 48(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 32(%rsp), %r9 movl $_Z8setValuePcic, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq 16(%rsp), %rsi leaq 11(%rsp), %rdi movl $4, %edx movl $2, %ecx callq hipMemcpy movl $_ZSt4cout, %r14d movl $_ZSt4cout, %edi movl $.L.str, %esi movl $13, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movzbl 13(%rsp), %eax movb %al, 32(%rsp) movq _ZSt4cout(%rip), %rcx movq -24(%rcx), %rcx cmpq $0, _ZSt4cout+16(%rcx) je .LBB1_4 # %bb.3: leaq 32(%rsp), %rsi movl $_ZSt4cout, %edi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq %rax, %r14 jmp .LBB1_5 .LBB1_4: movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc .LBB1_5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit movq (%r14), %rax movq -24(%rax), %rax movq 240(%r14,%rax), %r15 testq %r15, %r15 je .LBB1_26 # %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r15) je .LBB1_8 # %bb.7: movzbl 67(%r15), %eax jmp .LBB1_9 .LBB1_8: movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movq %r14, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq %rbx, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_11 # %bb.10: movq 16(%rsp), %rax movq %rax, 104(%rsp) movl $2, 28(%rsp) movb $23, 15(%rsp) leaq 104(%rsp), %rax movq %rax, 32(%rsp) leaq 28(%rsp), %rax movq %rax, 40(%rsp) leaq 15(%rsp), %rax movq %rax, 48(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 32(%rsp), %r9 movl $_Z8setValuePcic, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_11: movq 16(%rsp), %rsi leaq 11(%rsp), %rdi movl $4, %edx movl $2, %ecx callq hipMemcpy movl $_ZSt4cout, %ebx movl $_ZSt4cout, %edi movl $.L.str, %esi movl $13, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movzbl 13(%rsp), %eax movb %al, 32(%rsp) movq _ZSt4cout(%rip), %rcx movq -24(%rcx), %rcx cmpq $0, _ZSt4cout+16(%rcx) je .LBB1_13 # %bb.12: leaq 32(%rsp), %rsi movl $_ZSt4cout, %edi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq %rax, %rbx jmp .LBB1_14 .LBB1_13: movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc .LBB1_14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit16 movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB1_26 # %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21 cmpb $0, 56(%r14) je .LBB1_17 # %bb.16: movzbl 67(%r14), %eax jmp .LBB1_18 .LBB1_17: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24 movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movb $44, 13(%rsp) movq 16(%rsp), %rdi leaq 11(%rsp), %rbx movl $4, %edx movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movb $55, 13(%rsp) movq 16(%rsp), %rsi movl $4, %edx movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movl $_ZSt4cout, %ebx movl $_ZSt4cout, %edi movl $.L.str, %esi movl $13, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movzbl 13(%rsp), %eax movb %al, 32(%rsp) movq _ZSt4cout(%rip), %rcx movq -24(%rcx), %rcx cmpq $0, _ZSt4cout+16(%rcx) je .LBB1_20 # %bb.19: leaq 32(%rsp), %rsi movl $_ZSt4cout, %edi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq %rax, %rbx jmp .LBB1_21 .LBB1_20: movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc .LBB1_21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit19 movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB1_26 # %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26 cmpb $0, 56(%r14) je .LBB1_24 # %bb.23: movzbl 67(%r14), %eax jmp .LBB1_25 .LBB1_24: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29 movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 16(%rsp), %rdi callq hipFree xorl %eax, %eax addq $112, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB1_26: .cfi_def_cfa_offset 144 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z8setValuePcic, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z8setValuePcic,@object # @_Z8setValuePcic .section .rodata,"a",@progbits .globl _Z8setValuePcic .p2align 3, 0x0 _Z8setValuePcic: .quad _Z23__device_stub__setValuePcic .size _Z8setValuePcic, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "hostChars[2] " .size .L.str, 14 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z8setValuePcic" .size .L__unnamed_1, 16 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z23__device_stub__setValuePcic .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z8setValuePcic .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
433
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code for sm_80 Function : _Z3addPiS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R6, SR_CTAID.X ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; LDG.E R2, [R2.64] ; LDG.E R5, [R4.64] ; IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; IADD3 R9, R2, R5, RZ ; STG.E [R6.64], R9 ; EXIT ; BRA 0xc0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0003ae77_00000000-6_6e1143df97b0125e2089b1f980c35fdd24ee9419.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4035: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4035: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z26__device_stub__Z3addPiS_S_PiS_S_ .type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function _Z26__device_stub__Z3addPiS_S_PiS_S_: .LFB4057: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z3addPiS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE4057: .size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_ .globl _Z3addPiS_S_ .type _Z3addPiS_S_, @function _Z3addPiS_S_: .LFB4058: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z3addPiS_S_PiS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4058: .size _Z3addPiS_S_, .-_Z3addPiS_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Elapsed Time: " .LC1: .string "ms" .text .globl main .type main, @function main: .LFB4032: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 subq $320, %rsp .cfi_def_cfa_offset 336 movq %fs:40, %rax movq %rax, 312(%rsp) xorl %eax, %eax movl $0, %edi call time@PLT movl %eax, %edi call srand@PLT movl $0, %ebx .L12: call rand@PLT movl %eax, 64(%rsp,%rbx) call rand@PLT movl %eax, 144(%rsp,%rbx) addq $4, %rbx cmpq $80, %rbx jne .L12 movq %rsp, %rdi movl $80, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $80, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $80, %esi call cudaMalloc@PLT leaq 64(%rsp), %rsi movl $1, %ecx movl $80, %edx movq (%rsp), %rdi call cudaMemcpy@PLT leaq 144(%rsp), %rsi movl $1, %ecx movl $80, %edx movq 8(%rsp), %rdi call cudaMemcpy@PLT leaq 24(%rsp), %rdi call cudaEventCreate@PLT leaq 32(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 24(%rsp), %rdi call cudaEventRecord@PLT movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $20, 40(%rsp) movl $1, 44(%rsp) movl $0, %r9d movl $0, %r8d movq 52(%rsp), %rdx movl $1, %ecx movq 40(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L17 .L13: call cudaDeviceSynchronize@PLT leaq 224(%rsp), %rdi movl $2, %ecx movl $80, %edx movq 16(%rsp), %rsi call cudaMemcpy@PLT movl $0, %esi movq 32(%rsp), %rdi call cudaEventRecord@PLT movq 32(%rsp), %rdi call cudaEventSynchronize@PLT leaq 52(%rsp), %rdi movq 32(%rsp), %rdx movq 24(%rsp), %rsi call cudaEventElapsedTime@PLT movq 24(%rsp), %rdi call cudaEventDestroy@PLT movq 32(%rsp), %rdi call cudaEventDestroy@PLT leaq .LC0(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd 52(%rsp), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC1(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 312(%rsp), %rax subq %fs:40, %rax jne .L18 movl $0, %eax addq $320, %rsp .cfi_remember_state .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 ret .L17: .cfi_restore_state movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z26__device_stub__Z3addPiS_S_PiS_S_ jmp .L13 .L18: call __stack_chk_fail@PLT .cfi_endproc .LFE4032: .size main, .-main .section .rodata.str1.1 .LC2: .string "_Z3addPiS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z3addPiS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4060: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z3addPiS_S_ ; -- Begin function _Z3addPiS_S_ .globl _Z3addPiS_S_ .p2align 8 .type _Z3addPiS_S_,@function _Z3addPiS_S_: ; @_Z3addPiS_S_ ; %bb.0: s_load_b128 s[4:7], s[0:1], 0x0 s_mov_b32 s2, s15 s_ashr_i32 s3, s15, 31 s_load_b64 s[0:1], s[0:1], 0x10 s_lshl_b64 s[2:3], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s4, s4, s2 s_addc_u32 s5, s5, s3 s_add_u32 s6, s6, s2 s_addc_u32 s7, s7, s3 s_load_b32 s4, s[4:5], 0x0 s_load_b32 s5, s[6:7], 0x0 s_waitcnt lgkmcnt(0) s_add_i32 s4, s5, s4 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4 s_add_u32 s0, s0, s2 s_addc_u32 s1, s1, s3 global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z3addPiS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 16 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 112 ; NumSgprs: 16 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 16 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z3addPiS_S_ .private_segment_fixed_size: 0 .sgpr_count: 16 .sgpr_spill_count: 0 .symbol: _Z3addPiS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "6e1143df97b0125e2089b1f980c35fdd24ee9419.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_ .p2align 4, 0x90 .type _Z18__device_stub__addPiS_S_,@function _Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3addPiS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $360, %rsp # imm = 0x168 .cfi_def_cfa_offset 384 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 xorl %ebx, %ebx xorl %edi, %edi callq time movl %eax, %edi callq srand .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 callq rand movl %eax, 272(%rsp,%rbx,4) callq rand movl %eax, 192(%rsp,%rbx,4) incq %rbx cmpq $20, %rbx jne .LBB1_1 # %bb.2: leaq 32(%rsp), %rdi movl $80, %esi callq hipMalloc leaq 24(%rsp), %rdi movl $80, %esi callq hipMalloc leaq 16(%rsp), %rdi movl $80, %esi callq hipMalloc movq 32(%rsp), %rdi leaq 272(%rsp), %rsi movl $80, %edx movl $1, %ecx callq hipMemcpy movq 24(%rsp), %rdi leaq 192(%rsp), %rsi movl $80, %edx movl $1, %ecx callq hipMemcpy leaq 8(%rsp), %rdi callq hipEventCreate movq %rsp, %rdi callq hipEventCreate movq 8(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movabsq $4294967297, %rdx # imm = 0x100000001 leaq 19(%rdx), %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 32(%rsp), %rax movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 40(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z3addPiS_S_, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: callq hipDeviceSynchronize movq 16(%rsp), %rsi leaq 112(%rsp), %rdi movl $80, %edx movl $2, %ecx callq hipMemcpy movq (%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq (%rsp), %rdi callq hipEventSynchronize movq 8(%rsp), %rsi movq (%rsp), %rdx leaq 40(%rsp), %rdi callq hipEventElapsedTime movq 8(%rsp), %rdi callq hipEventDestroy movq (%rsp), %rdi callq hipEventDestroy movl $_ZSt4cout, %edi movl $.L.str, %esi movl $14, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.1, %esi movl $2, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB1_9 # %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r14) je .LBB1_7 # %bb.6: movzbl 67(%r14), %eax jmp .LBB1_8 .LBB1_7: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 32(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree xorl %eax, %eax addq $360, %rsp # imm = 0x168 .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB1_9: .cfi_def_cfa_offset 384 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3addPiS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z3addPiS_S_,@object # @_Z3addPiS_S_ .section .rodata,"a",@progbits .globl _Z3addPiS_S_ .p2align 3, 0x0 _Z3addPiS_S_: .quad _Z18__device_stub__addPiS_S_ .size _Z3addPiS_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Elapsed Time: " .size .L.str, 15 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "ms" .size .L.str.1, 3 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z3addPiS_S_" .size .L__unnamed_1, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__addPiS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3addPiS_S_ .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
424
3,194
1,915
3,787
152
code for sm_80 Function : vectorAddition .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; LDG.E R0, [R2.64] ; LDG.E R5, [R2.64+0x4] ; FADD R5, R0, R5 ; STG.E [R2.64+0x8], R5 ; EXIT ; BRA 0xc0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0000822f_00000000-6_8ac6e313a4e9c718c3b5d7eec86ec42b4a4a67b1.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData .type _Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData, @function _Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData: .LFB2051: .cfi_startproc endbr64 subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 8(%rsp) movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 88(%rsp), %rax subq %fs:40, %rax jne .L8 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 120 pushq 24(%rsp) .cfi_def_cfa_offset 128 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq vectorAddition(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 112 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData, .-_Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData .globl vectorAddition .type vectorAddition, @function vectorAddition: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size vectorAddition, .-vectorAddition .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "vectorAddition" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq vectorAddition(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected vectorAddition ; -- Begin function vectorAddition .globl vectorAddition .p2align 8 .type vectorAddition,@function vectorAddition: ; @vectorAddition ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x14 s_load_b64 s[0:1], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_mad_i64_i32 v[2:3], null, v1, 12, s[0:1] global_load_b64 v[0:1], v[2:3], off s_waitcnt vmcnt(0) v_add_f32_e32 v0, v0, v1 global_store_b32 v[2:3], v0, off offset:8 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel vectorAddition .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 264 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size vectorAddition, .Lfunc_end0-vectorAddition ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 88 ; NumSgprs: 16 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 16 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: hidden_block_count_x - .offset: 12 .size: 4 .value_kind: hidden_block_count_y - .offset: 16 .size: 4 .value_kind: hidden_block_count_z - .offset: 20 .size: 2 .value_kind: hidden_group_size_x - .offset: 22 .size: 2 .value_kind: hidden_group_size_y - .offset: 24 .size: 2 .value_kind: hidden_group_size_z - .offset: 26 .size: 2 .value_kind: hidden_remainder_x - .offset: 28 .size: 2 .value_kind: hidden_remainder_y - .offset: 30 .size: 2 .value_kind: hidden_remainder_z - .offset: 48 .size: 8 .value_kind: hidden_global_offset_x - .offset: 56 .size: 8 .value_kind: hidden_global_offset_y - .offset: 64 .size: 8 .value_kind: hidden_global_offset_z - .offset: 72 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 264 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: vectorAddition .private_segment_fixed_size: 0 .sgpr_count: 16 .sgpr_spill_count: 0 .symbol: vectorAddition.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "8ac6e313a4e9c718c3b5d7eec86ec42b4a4a67b1.hip" .globl __device_stub__vectorAddition # -- Begin function __device_stub__vectorAddition .p2align 4, 0x90 .type __device_stub__vectorAddition,@function __device_stub__vectorAddition: # @__device_stub__vectorAddition .cfi_startproc # %bb.0: subq $72, %rsp .cfi_def_cfa_offset 80 movq %rdi, 64(%rsp) leaq 64(%rsp), %rax movq %rax, (%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d movq %rsp, %r9 movl $vectorAddition, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $88, %rsp .cfi_adjust_cfa_offset -88 retq .Lfunc_end0: .size __device_stub__vectorAddition, .Lfunc_end0-__device_stub__vectorAddition .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $vectorAddition, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type vectorAddition,@object # @vectorAddition .section .rodata,"a",@progbits .globl vectorAddition .p2align 3, 0x0 vectorAddition: .quad __device_stub__vectorAddition .size vectorAddition, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "vectorAddition" .size .L__unnamed_1, 15 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __device_stub__vectorAddition .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym vectorAddition .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
402
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code for sm_80 Function : _Z5helloPcPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_TID.X ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IADD3 R4, P0, R2.reuse, c[0x0][0x160], RZ ; IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; IADD3.X R5, RZ, c[0x0][0x164], RZ, P0, !PT ; LDG.E.U8 R3, [R2.64] ; LDG.E.U8 R0, [R4.64] ; IADD3 R7, R0, R3, RZ ; STG.E.U8 [R4.64], R7 ; EXIT ; BRA 0xc0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0003a245_00000000-6_db18221ef7723fb97317d0fe9da9c9c2a6e46811.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z26__device_stub__Z5helloPcPiPcPi .type _Z26__device_stub__Z5helloPcPiPcPi, @function _Z26__device_stub__Z5helloPcPiPcPi: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z5helloPcPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z26__device_stub__Z5helloPcPiPcPi, .-_Z26__device_stub__Z5helloPcPiPcPi .globl _Z5helloPcPi .type _Z5helloPcPi, @function _Z5helloPcPi: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z5helloPcPiPcPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z5helloPcPi, .-_Z5helloPcPi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%s" .LC1: .string "%s\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 subq $144, %rsp .cfi_def_cfa_offset 160 movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax movabsq $35662932501832, %rax movl $0, %edx movq %rax, 112(%rsp) movq %rdx, 120(%rsp) movl $15, 48(%rsp) movl $10, 52(%rsp) movl $6, 56(%rsp) movl $0, 60(%rsp) movl $-11, 64(%rsp) movl $1, 68(%rsp) movl $0, 72(%rsp) movl $0, 76(%rsp) movl $0, 80(%rsp) movl $0, 84(%rsp) movl $0, 88(%rsp) movl $0, 92(%rsp) movl $0, 96(%rsp) movl $0, 100(%rsp) movl $0, 104(%rsp) movl $0, 108(%rsp) leaq 112(%rsp), %rbx movq %rbx, %rdx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 8(%rsp), %rdi movl $16, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $64, %esi call cudaMalloc@PLT movl $1, %ecx movl $16, %edx movq %rbx, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT leaq 48(%rsp), %rsi movl $1, %ecx movl $64, %edx movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $16, 24(%rsp) movl $1, 28(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $0, %r9d movl $0, %r8d movq 24(%rsp), %rdx movl $1, %ecx movq 36(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L15 .L12: leaq 112(%rsp), %rbx movl $2, %ecx movl $16, %edx movq 8(%rsp), %rsi movq %rbx, %rdi call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdx leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 136(%rsp), %rax subq %fs:40, %rax jne .L16 movl $0, %eax addq $144, %rsp .cfi_remember_state .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z26__device_stub__Z5helloPcPiPcPi jmp .L12 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC2: .string "_Z5helloPcPi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z5helloPcPi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z5helloPcPi ; -- Begin function _Z5helloPcPi .globl _Z5helloPcPi .p2align 8 .type _Z5helloPcPi,@function _Z5helloPcPi: ; @_Z5helloPcPi ; %bb.0: s_load_b128 s[0:3], s[0:1], 0x0 v_lshlrev_b32_e32 v1, 2, v0 s_waitcnt lgkmcnt(0) global_load_b32 v1, v1, s[2:3] global_load_u8 v2, v0, s[0:1] s_waitcnt vmcnt(0) v_add_nc_u16 v1, v2, v1 global_store_b8 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5helloPcPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 4 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z5helloPcPi, .Lfunc_end0-_Z5helloPcPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 64 ; NumSgprs: 4 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 4 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5helloPcPi .private_segment_fixed_size: 0 .sgpr_count: 4 .sgpr_spill_count: 0 .symbol: _Z5helloPcPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "db18221ef7723fb97317d0fe9da9c9c2a6e46811.hip" .globl _Z20__device_stub__helloPcPi # -- Begin function _Z20__device_stub__helloPcPi .p2align 4, 0x90 .type _Z20__device_stub__helloPcPi,@function _Z20__device_stub__helloPcPi: # @_Z20__device_stub__helloPcPi .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z5helloPcPi, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z20__device_stub__helloPcPi, .Lfunc_end0-_Z20__device_stub__helloPcPi .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $176, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -16 movl $1819043144, 16(%rsp) # imm = 0x6C6C6548 movw $8303, 20(%rsp) # imm = 0x206F movq $0, 22(%rsp) movw $0, 30(%rsp) xorps %xmm0, %xmm0 movaps %xmm0, 112(%rsp) movaps %xmm0, 128(%rsp) movaps %xmm0, 160(%rsp) movaps %xmm0, 144(%rsp) movabsq $42949672975, %rax # imm = 0xA0000000F movq %rax, 112(%rsp) movl $6, 120(%rsp) movabsq $8589934581, %rax # imm = 0x1FFFFFFF5 movq %rax, 128(%rsp) leaq 16(%rsp), %rbx movl $.L.str, %edi movq %rbx, %rsi xorl %eax, %eax callq printf movq %rsp, %rdi movl $16, %esi callq hipMalloc leaq 8(%rsp), %rdi movl $64, %esi callq hipMalloc movq (%rsp), %rdi movl $16, %edx movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi leaq 112(%rsp), %rsi movl $64, %edx movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 15(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq (%rsp), %rax movq 8(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z5helloPcPi, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq (%rsp), %rsi leaq 16(%rsp), %rbx movl $16, %edx movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movq (%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq puts@PLT xorl %eax, %eax addq $176, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5helloPcPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z5helloPcPi,@object # @_Z5helloPcPi .section .rodata,"a",@progbits .globl _Z5helloPcPi .p2align 3, 0x0 _Z5helloPcPi: .quad _Z20__device_stub__helloPcPi .size _Z5helloPcPi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%s" .size .L.str, 3 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z5helloPcPi" .size .L__unnamed_1, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z20__device_stub__helloPcPi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z5helloPcPi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
427
2,890
1,686
2,892
154
code for sm_80 Function : _Z20gpu_calcColor_kerneliPfffffffffbbS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; ULDC.64 UR6, c[0x0][0x118] ; BSSY B0, 0x100 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; IMAD R0, R2.reuse, 0x3, RZ ; ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; ISETP.LT.OR P0, PT, R2, 0x1, P0 ; @P0 BRA 0xf0 ; IADD3 R4, R0, 0x2, RZ ; IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; LDG.E R4, [R4.64] ; BSYNC B0 ; FSETP.NEU.AND P0, PT, R4, RZ, PT ; @!P0 EXIT ; MUFU.RCP R3, c[0x0][0x174] ; FADD R9, R4, -c[0x0][0x170] ; MOV R6, c[0x0][0x174] ; BSSY B0, 0x200 ; FCHK P0, R9, c[0x0][0x174] ; FFMA R6, R3, -R6, 1 ; FFMA R6, R3, R6, R3 ; FFMA R3, R9, R6, RZ ; FFMA R4, R3, -c[0x0][0x174], R9 ; FFMA R3, R6, R4, R3 ; @!P0 BRA 0x1f0 ; MOV R4, 0x1f0 ; CALL.REL.NOINC 0xb00 ; BSYNC B0 ; ULDC.S8 UR4, c[0x0][0x190] ; FSETP.GTU.AND P0, PT, R3.reuse, RZ, PT ; BSSY B0, 0x970 ; ISETP.NE.AND P1, PT, RZ, UR4, PT ; FSEL R3, R3, 0.0099999997764825820923, P0 ; FMNMX.NAN R6, R3, 1, PT ; @!P1 BRA 0x900 ; FSETP.NEU.AND P0, PT, R6, RZ, PT ; @!P0 BRA 0x5f0 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x18c] ; FFMA R8, R6.reuse, R3, c[0x0][0x178] ; FFMA R11, R6, R4, c[0x0][0x180] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x188] ; FSETP.GEU.AND P0, PT, R8, RZ, PT ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R5, R11 ; FFMA R10, R6, R3, c[0x0][0x17c] ; IMAD.MOV.U32 R9, RZ, RZ, R11 ; @!P0 BRA 0x960 ; F2F.F64.F32 R4, R8 ; DMUL R4, R4, c[0x2][0x0] ; F2F.F32.F64 R4, R4 ; F2I.FLOOR.NTZ R12, R4 ; I2F R3, R12 ; LOP3.LUT R6, R12, 0x1, RZ, 0xc0, !PT ; ISETP.NE.U32.AND P0, PT, R6, 0x1, PT ; FADD R6, -R10, 1 ; FMUL R6, R11, R6 ; FADD R3, R4, -R3 ; @P0 FADD R3, -R3, 1 ; ISETP.GT.AND P0, PT, R12, 0x2, PT ; FFMA R3, -R10, R3, 1 ; FMUL R3, R11, R3 ; @P0 BRA 0x510 ; ISETP.NE.AND P0, PT, R12, 0x1, PT ; IMAD.MOV.U32 R5, RZ, RZ, R3 ; MOV R7, R11 ; IMAD.MOV.U32 R9, RZ, RZ, R6 ; @!P0 BRA 0x960 ; ISETP.NE.AND P0, PT, R12, 0x2, PT ; IMAD.MOV.U32 R5, RZ, RZ, R11 ; MOV R9, R6 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; @P0 BRA 0x960 ; IMAD.MOV.U32 R5, RZ, RZ, R6 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; IMAD.MOV.U32 R9, RZ, RZ, R3 ; BRA 0x960 ; ISETP.NE.AND P0, PT, R12, 0x4, PT ; IMAD.MOV.U32 R7, RZ, RZ, R6 ; MOV R5, R3 ; IMAD.MOV.U32 R9, RZ, RZ, R11 ; @!P0 BRA 0x960 ; ISETP.NE.AND P0, PT, R12, 0x3, PT ; IMAD.MOV.U32 R5, RZ, RZ, R11 ; MOV R7, R3 ; IMAD.MOV.U32 R9, RZ, RZ, R6 ; @P0 BRA 0x960 ; IMAD.MOV.U32 R5, RZ, RZ, R6 ; MOV R9, R11 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; BRA 0x960 ; FSETP.LEU.AND P0, PT, RZ, c[0x0][0x178], PT ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x180] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x180] ; @!P0 BRA 0x960 ; F2F.F64.F32 R4, c[0x0][0x178] ; MOV R8, c[0x0][0x17c] ; DMUL R4, R4, c[0x2][0x0] ; F2F.F32.F64 R4, R4 ; F2I.FLOOR.NTZ R3, R4 ; I2F R7, R3 ; LOP3.LUT R6, R3, 0x1, RZ, 0xc0, !PT ; ISETP.NE.U32.AND P0, PT, R6, 0x1, PT ; FADD R6, -R8, 1 ; FMUL R6, R6, c[0x0][0x180] ; FADD R7, R4, -R7 ; @P0 FADD R7, -R7, 1 ; ISETP.GT.AND P0, PT, R3, 0x2, PT ; FFMA R7, -R7, R8, 1 ; FMUL R4, R7, c[0x0][0x180] ; @P0 BRA 0x820 ; ISETP.NE.AND P0, PT, R3, 0x1, PT ; IMAD.MOV.U32 R5, RZ, RZ, R4 ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x180] ; IMAD.MOV.U32 R9, RZ, RZ, R6 ; @!P0 BRA 0x960 ; ISETP.NE.AND P0, PT, R3, 0x2, PT ; IMAD.MOV.U32 R7, RZ, RZ, R4 ; MOV R5, c[0x0][0x180] ; IMAD.MOV.U32 R9, RZ, RZ, R6 ; @P0 BRA 0x960 ; IMAD.MOV.U32 R5, RZ, RZ, R6 ; MOV R9, R4 ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x180] ; BRA 0x960 ; ISETP.NE.AND P0, PT, R3, 0x4, PT ; IMAD.MOV.U32 R5, RZ, RZ, R4 ; MOV R9, c[0x0][0x180] ; IMAD.MOV.U32 R7, RZ, RZ, R6 ; @!P0 BRA 0x960 ; ISETP.NE.AND P0, PT, R3, 0x3, PT ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ; IMAD.MOV.U32 R7, RZ, RZ, R4 ; IMAD.MOV.U32 R9, RZ, RZ, R6 ; @P0 BRA 0x960 ; MOV R5, R6 ; IMAD.MOV.U32 R7, RZ, RZ, R4 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x180] ; BRA 0x960 ; MOV R7, c[0x0][0x17c] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x184] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x18c] ; FFMA R5, R6.reuse, R5, c[0x0][0x178] ; FFMA R7, R6, c[0x0][0x188], R7 ; FFMA R9, R6, R9, c[0x0][0x180] ; BSYNC B0 ; ULDC.S8 UR4, c[0x0][0x191] ; ISETP.NE.AND P0, PT, RZ, UR4, PT ; @!P0 BRA 0xaa0 ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; IMAD R2, R2, 0xc, RZ ; IMAD.WIDE R2, R2, R3, c[0x0][0x198] ; STG.E [R2.64], R5 ; STG.E [R2.64+0xc], R5 ; STG.E [R2.64+0x18], R5 ; STG.E [R2.64+0x24], R5 ; STG.E [R2.64+0x4], R7 ; STG.E [R2.64+0x10], R7 ; STG.E [R2.64+0x1c], R7 ; STG.E [R2.64+0x28], R7 ; STG.E [R2.64+0x8], R9 ; STG.E [R2.64+0x14], R9 ; STG.E [R2.64+0x20], R9 ; STG.E [R2.64+0x2c], R9 ; EXIT ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; IMAD.WIDE R2, R0, R3, c[0x0][0x198] ; STG.E [R2.64], R5 ; STG.E [R2.64+0x4], R7 ; STG.E [R2.64+0x8], R9 ; EXIT ; MOV R12, c[0x0][0x174] ; BSSY B1, 0x1180 ; SHF.R.U32.HI R3, RZ, 0x17, R9.reuse ; IMAD.MOV.U32 R6, RZ, RZ, R9 ; SHF.R.U32.HI R5, RZ, 0x17, R12 ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; IADD3 R13, R11, -0x1, RZ ; IADD3 R10, R5, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; ISETP.GT.U32.OR P0, PT, R13, 0xfd, P0 ; @!P0 MOV R8, RZ ; @!P0 BRA 0xd60 ; FSETP.GTU.FTZ.AND P1, PT, |R12|, +INF , PT ; IMAD.MOV.U32 R3, RZ, RZ, R9 ; FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0x1160 ; LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; @!P0 BRA 0x1140 ; FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P1, PT, |R12|, +INF , PT ; FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; @!P1 BRA !P2, 0x1140 ; LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; @P1 BRA 0x1120 ; LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; @P0 BRA 0x10f0 ; ISETP.GE.AND P0, PT, R13, RZ, PT ; ISETP.GE.AND P1, PT, R10, RZ, PT ; @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; @!P0 MOV R8, 0xffffffc0 ; @!P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R7, R12, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R8, R8, 0x40, RZ ; LEA R10, R5, 0xc0800000, 0x17 ; BSSY B2, 0x10e0 ; IMAD.IADD R10, R7, 0x1, -R10 ; IADD3 R7, R11, -0x7f, RZ ; MUFU.RCP R3, R10 ; FADD.FTZ R9, -R10, -RZ ; IMAD R6, R7.reuse, -0x800000, R6 ; IADD3 R7, R7, 0x7f, -R5 ; IMAD.IADD R8, R7, 0x1, R8 ; FFMA R12, R3, R9, 1 ; FFMA R11, R3, R12, R3 ; FFMA R3, R6, R11, RZ ; FFMA R12, R9, R3, R6 ; FFMA R12, R11, R12, R3 ; FFMA R6, R9, R12, R6 ; FFMA R3, R11, R6, R12 ; SHF.R.U32.HI R5, RZ, 0x17, R3 ; LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; IADD3 R9, R5, R8, RZ ; IADD3 R5, R9, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; @!P0 BRA 0x10c0 ; ISETP.GT.AND P0, PT, R9, 0xfe, PT ; @P0 BRA 0x1090 ; ISETP.GE.AND P0, PT, R9, 0x1, PT ; @P0 BRA 0x10d0 ; ISETP.GE.AND P0, PT, R9, -0x18, PT ; LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0x10d0 ; FFMA.RZ R5, R11, R6.reuse, R12.reuse ; IADD3 R8, R9.reuse, 0x20, RZ ; ISETP.NE.AND P2, PT, R9, RZ, PT ; LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; FFMA.RP R5, R11, R6.reuse, R12.reuse ; ISETP.NE.AND P1, PT, R9, RZ, PT ; FFMA.RM R6, R11, R6, R12 ; LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; IMAD.MOV R9, RZ, RZ, -R9 ; SHF.L.U32 R8, R7, R8, RZ ; FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; SEL R6, R9, RZ, P2 ; ISETP.NE.AND P1, PT, R8, RZ, P1 ; SHF.R.U32.HI R6, RZ, R6, R7 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R8, RZ, 0x1, R6 ; SEL R5, RZ, 0x1, !P0 ; LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; IMAD.IADD R8, R8, 0x1, R5 ; LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; BRA 0x10d0 ; LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x10d0 ; LEA R3, R8, R3, 0x17 ; BSYNC B2 ; BRA 0x1170 ; LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ; LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x1170 ; LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ; BRA 0x1170 ; MUFU.RSQ R3, -QNAN ; BRA 0x1170 ; FADD.FTZ R3, R3, c[0x0][0x174] ; BSYNC B1 ; IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; RET.REL.NODEC R4 0x0 ; BRA 0x11a0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000c7615_00000000-6_c720ca84927897e8b3bc2ff5183b0190a7e1ea92.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2031: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2031: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z7HSV2RGBfffRfS_S_ .type _Z7HSV2RGBfffRfS_S_, @function _Z7HSV2RGBfffRfS_S_: .LFB2027: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2027: .size _Z7HSV2RGBfffRfS_S_, .-_Z7HSV2RGBfffRfS_S_ .globl _Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_ .type _Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_, @function _Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_: .LFB2053: .cfi_startproc endbr64 subq $248, %rsp .cfi_def_cfa_offset 256 movl %edi, 60(%rsp) movq %rsi, 48(%rsp) movss %xmm0, 56(%rsp) movss %xmm1, 44(%rsp) movss %xmm2, 40(%rsp) movss %xmm3, 36(%rsp) movss %xmm4, 32(%rsp) movss %xmm5, 28(%rsp) movss %xmm6, 24(%rsp) movss %xmm7, 20(%rsp) movq %r8, (%rsp) movb %dl, 16(%rsp) movb %cl, 12(%rsp) movq %fs:40, %rax movq %rax, 232(%rsp) xorl %eax, %eax leaq 60(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 56(%rsp), %rax movq %rax, 144(%rsp) leaq 44(%rsp), %rax movq %rax, 152(%rsp) leaq 40(%rsp), %rax movq %rax, 160(%rsp) leaq 36(%rsp), %rax movq %rax, 168(%rsp) leaq 32(%rsp), %rax movq %rax, 176(%rsp) leaq 28(%rsp), %rax movq %rax, 184(%rsp) leaq 24(%rsp), %rax movq %rax, 192(%rsp) leaq 20(%rsp), %rax movq %rax, 200(%rsp) leaq 16(%rsp), %rax movq %rax, 208(%rsp) leaq 12(%rsp), %rax movq %rax, 216(%rsp) movq %rsp, %rax movq %rax, 224(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L9 .L5: movq 232(%rsp), %rax subq %fs:40, %rax jne .L10 addq $248, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L9: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 264 pushq 72(%rsp) .cfi_def_cfa_offset 272 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z20gpu_calcColor_kerneliPfffffffffbbS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 256 jmp .L5 .L10: call __stack_chk_fail@PLT .cfi_endproc .LFE2053: .size _Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_, .-_Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_ .globl _Z20gpu_calcColor_kerneliPfffffffffbbS_ .type _Z20gpu_calcColor_kerneliPfffffffffbbS_, @function _Z20gpu_calcColor_kerneliPfffffffffbbS_: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movzbl %cl, %ecx movzbl %dl, %edx call _Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _Z20gpu_calcColor_kerneliPfffffffffbbS_, .-_Z20gpu_calcColor_kerneliPfffffffffbbS_ .globl gpu_calcColor .type gpu_calcColor, @function gpu_calcColor: .LFB2028: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $64, %rsp .cfi_def_cfa_offset 112 movl %edi, %ebx movq %rsi, %r13 movss %xmm0, (%rsp) movss %xmm1, 4(%rsp) movss %xmm2, 8(%rsp) movss %xmm3, 12(%rsp) movss %xmm4, 16(%rsp) movss %xmm5, 20(%rsp) movss %xmm6, 24(%rsp) movss %xmm7, 28(%rsp) movl %edx, %ebp movl %ecx, %r12d movq %r8, %r14 pxor %xmm0, %xmm0 cvtsi2ssl %edi, %xmm0 mulss .LC0(%rip), %xmm0 movaps %xmm0, %xmm3 movss .LC4(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC1(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L14 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC3(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L14: movl $256, 52(%rsp) movl $1, 56(%rsp) cvttss2sil %xmm3, %eax movl %eax, 40(%rsp) movl $1, 44(%rsp) movl $0, %r9d movl $0, %r8d movq 52(%rsp), %rdx movl $1, %ecx movq 40(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L17 .L13: addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L17: .cfi_restore_state movzbl %r12b, %ecx movzbl %bpl, %edx movq %r14, %r8 movss 28(%rsp), %xmm7 movss 24(%rsp), %xmm6 movss 20(%rsp), %xmm5 movss 16(%rsp), %xmm4 movss 12(%rsp), %xmm3 movss 8(%rsp), %xmm2 movss 4(%rsp), %xmm1 movss (%rsp), %xmm0 movq %r13, %rsi movl %ebx, %edi call _Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_ jmp .L13 .cfi_endproc .LFE2028: .size gpu_calcColor, .-gpu_calcColor .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC5: .string "_Z20gpu_calcColor_kerneliPfffffffffbbS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2056: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _Z20gpu_calcColor_kerneliPfffffffffbbS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2056: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 998244352 .align 4 .LC1: .long 1258291200 .align 4 .LC3: .long 1065353216 .align 4 .LC4: .long 2147483647 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z20gpu_calcColor_kerneliPfffffffffbbS_ ; -- Begin function _Z20gpu_calcColor_kerneliPfffffffffbbS_ .globl _Z20gpu_calcColor_kerneliPfffffffffbbS_ .p2align 8 .type _Z20gpu_calcColor_kerneliPfffffffffbbS_,@function _Z20gpu_calcColor_kerneliPfffffffffbbS_: ; @_Z20gpu_calcColor_kerneliPfffffffffbbS_ ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x4c s_load_b32 s3, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_mov_b32_e32 v0, 0 v_cmp_lt_i32_e32 vcc_lo, 0, v1 v_cmp_gt_i32_e64 s2, s3, v1 v_lshl_add_u32 v4, v1, 1, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s3, vcc_lo, s2 s_and_saveexec_b32 s2, s3 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b64 s[4:5], s[0:1], 0x8 v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[4:5] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo global_load_b32 v0, v[2:3], off offset:8 .LBB0_2: s_or_b32 exec_lo, exec_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s2, exec_lo s_waitcnt vmcnt(0) v_cmpx_neq_f32_e32 0, v0 s_cbranch_execz .LBB0_30 ; %bb.3: s_clause 0x1 s_load_b256 s[4:11], s[0:1], 0x10 s_load_b32 s2, s[0:1], 0x30 s_mov_b32 s3, 0 s_waitcnt lgkmcnt(0) v_subrev_f32_e32 v0, s4, v0 s_bitcmp0_b32 s2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f32 v2, null, s5, s5, v0 v_rcp_f32_e32 v3, v2 s_waitcnt_depctr 0xfff v_fma_f32 v5, -v2, v3, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fmac_f32_e32 v3, v5, v3 v_div_scale_f32 v6, vcc_lo, v0, s5, v0 v_mul_f32_e32 v5, v6, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v7, -v2, v5, v6 v_fmac_f32_e32 v5, v7, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v2, -v2, v5, v6 v_div_fmas_f32 v2, v2, v3, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fixup_f32 v0, v2, s5, v0 v_cmp_nge_f32_e32 vcc_lo, 0, v0 v_cndmask_b32_e32 v0, 0x3c23d70a, v0, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_nle_f32_e32 vcc_lo, 1.0, v0 v_cndmask_b32_e32 v5, 1.0, v0, vcc_lo v_fma_f32 v2, v5, s9, s6 s_cbranch_scc0 .LBB0_5 ; %bb.4: v_fma_f32 v3, v5, s10, s7 v_fma_f32 v0, v5, s11, s8 s_and_not1_b32 vcc_lo, exec_lo, s3 s_cbranch_vccz .LBB0_6 s_branch .LBB0_25 .LBB0_5: ; implicit-def: $vgpr0 .LBB0_6: v_fma_f32 v0, v5, s11, s8 s_mov_b32 s3, exec_lo s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v3, v0 v_mov_b32_e32 v7, v0 v_cmpx_ngt_f32_e32 0, v2 s_cbranch_execz .LBB0_24 ; %bb.7: ; %NodeBlock116 v_cvt_f64_f32_e32 v[2:3], v2 s_mov_b32 s5, 0x3f911111 s_mov_b32 s4, 0x1111111b v_fma_f32 v5, v5, s10, s7 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mul_f64 v[2:3], v[2:3], s[4:5] s_mov_b32 s4, exec_lo v_cvt_f32_f64_e32 v2, v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_floor_f32_e32 v3, v2 v_cvt_i32_f32_e32 v7, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_f32_i32_e32 v3, v7 v_sub_f32_e32 v2, v2, v3 v_and_b32_e32 v3, 1, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_eq_u32_e32 vcc_lo, 0, v3 v_dual_sub_f32 v3, 1.0, v5 :: v_dual_sub_f32 v6, 1.0, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v2, v2, v6, vcc_lo ; implicit-def: $vgpr6 v_fma_f32 v5, -v5, v2, 1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f32_e32 v2, v0, v3 ; implicit-def: $vgpr3 v_mul_f32_e32 v5, v0, v5 v_cmpx_lt_i32_e32 2, v7 s_xor_b32 s4, exec_lo, s4 s_cbranch_execz .LBB0_15 ; %bb.8: ; %NodeBlock114 s_mov_b32 s5, exec_lo ; implicit-def: $vgpr6 ; implicit-def: $vgpr3 v_cmpx_lt_i32_e32 3, v7 s_xor_b32 s5, exec_lo, s5 s_cbranch_execz .LBB0_12 ; %bb.9: ; %LeafBlock112 v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v3, v5 s_mov_b32 s6, exec_lo v_cmpx_eq_u32_e32 4, v7 ; %bb.10: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v3, v2 v_mov_b32_e32 v0, v5 ; %bb.11: ; %Flow118 s_or_b32 exec_lo, exec_lo, s6 ; implicit-def: $vgpr5 ; implicit-def: $vgpr2 .LBB0_12: ; %Flow119 s_and_not1_saveexec_b32 s5, s5 ; %bb.13: s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v3, v5 v_mov_b32_e32 v0, v2 ; %bb.14: ; %Flow120 s_or_b32 exec_lo, exec_lo, s5 ; implicit-def: $vgpr2 ; implicit-def: $vgpr5 ; implicit-def: $vgpr7 .LBB0_15: ; %Flow124 s_and_not1_saveexec_b32 s4, s4 s_cbranch_execz .LBB0_23 ; %bb.16: ; %NodeBlock s_mov_b32 s5, exec_lo v_cmpx_lt_i32_e32 1, v7 s_xor_b32 s5, exec_lo, s5 ; %bb.17: ; implicit-def: $vgpr7 ; %bb.18: ; %Flow122 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_saveexec_b32 s5, s5 s_cbranch_execz .LBB0_22 ; %bb.19: ; %LeafBlock v_mov_b32_e32 v3, v5 s_mov_b32 s6, exec_lo v_cmpx_eq_u32_e32 1, v7 ; %bb.20: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v0, v5 ; %bb.21: ; %Flow121 s_or_b32 exec_lo, exec_lo, s6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v5, v2 v_mov_b32_e32 v0, v3 s_delay_alu instid0(VALU_DEP_2) v_mov_b32_e32 v2, v6 .LBB0_22: ; %Flow123 s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v3, v0 v_mov_b32_e32 v0, v2 .LBB0_23: ; %Flow125 s_or_b32 exec_lo, exec_lo, s4 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v7, v0 :: v_dual_mov_b32 v0, v6 .LBB0_24: ; %Flow127 s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v2, v7 .LBB0_25: ; %_Z7HSV2RGBfffRfS_S_.exit s_load_b64 s[0:1], s[0:1], 0x38 s_bfe_u32 s2, s2, 0x10008 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s2, 0 s_mov_b32 s2, 0 s_cbranch_scc0 .LBB0_27 ; %bb.26: v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], 2, v[4:5] s_waitcnt lgkmcnt(0) v_add_co_u32 v6, vcc_lo, s0, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo v_add_co_u32 v4, vcc_lo, v6, 8 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, 0, v7, vcc_lo global_store_b64 v[6:7], v[2:3], off s_and_not1_b32 vcc_lo, exec_lo, s2 s_cbranch_vccz .LBB0_28 s_branch .LBB0_29 .LBB0_27: ; implicit-def: $vgpr4_vgpr5 .LBB0_28: v_mul_lo_u32 v4, v1, 12 s_delay_alu instid0(VALU_DEP_1) v_or_b32_e32 v6, 1, v4 v_ashrrev_i32_e32 v5, 31, v4 v_or_b32_e32 v8, 2, v4 v_or_b32_e32 v10, 3, v4 v_add_nc_u32_e32 v12, 4, v4 v_ashrrev_i32_e32 v7, 31, v6 v_lshlrev_b64 v[15:16], 2, v[4:5] v_ashrrev_i32_e32 v9, 31, v8 v_ashrrev_i32_e32 v11, 31, v10 v_ashrrev_i32_e32 v13, 31, v12 v_lshlrev_b64 v[5:6], 2, v[6:7] v_add_nc_u32_e32 v14, 5, v4 v_lshlrev_b64 v[7:8], 2, v[8:9] s_waitcnt lgkmcnt(0) v_add_co_u32 v17, vcc_lo, s0, v15 v_add_co_ci_u32_e32 v18, vcc_lo, s1, v16, vcc_lo v_lshlrev_b64 v[9:10], 2, v[10:11] v_add_co_u32 v19, vcc_lo, s0, v5 v_add_co_ci_u32_e32 v20, vcc_lo, s1, v6, vcc_lo v_add_co_u32 v6, vcc_lo, s0, v7 v_lshlrev_b64 v[11:12], 2, v[12:13] v_ashrrev_i32_e32 v15, 31, v14 v_add_co_ci_u32_e32 v7, vcc_lo, s1, v8, vcc_lo v_add_nc_u32_e32 v8, 6, v4 v_add_co_u32 v21, vcc_lo, s0, v9 v_add_co_ci_u32_e32 v22, vcc_lo, s1, v10, vcc_lo v_add_nc_u32_e32 v10, 7, v4 v_lshlrev_b64 v[13:14], 2, v[14:15] v_add_co_u32 v15, vcc_lo, s0, v11 v_ashrrev_i32_e32 v9, 31, v8 v_add_co_ci_u32_e32 v16, vcc_lo, s1, v12, vcc_lo v_add_nc_u32_e32 v12, 8, v4 v_ashrrev_i32_e32 v11, 31, v10 v_add_nc_u32_e32 v25, 9, v4 v_lshlrev_b64 v[8:9], 2, v[8:9] v_add_co_u32 v23, vcc_lo, s0, v13 v_ashrrev_i32_e32 v13, 31, v12 v_add_nc_u32_e32 v27, 10, v4 v_lshlrev_b64 v[10:11], 2, v[10:11] v_ashrrev_i32_e32 v26, 31, v25 v_add_co_ci_u32_e32 v24, vcc_lo, s1, v14, vcc_lo v_add_nc_u32_e32 v4, 11, v4 v_add_co_u32 v8, vcc_lo, s0, v8 v_lshlrev_b64 v[12:13], 2, v[12:13] v_ashrrev_i32_e32 v28, 31, v27 v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo v_add_co_u32 v10, vcc_lo, s0, v10 v_lshlrev_b64 v[25:26], 2, v[25:26] v_ashrrev_i32_e32 v5, 31, v4 v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo v_add_co_u32 v12, vcc_lo, s0, v12 v_lshlrev_b64 v[27:28], 2, v[27:28] v_add_co_ci_u32_e32 v13, vcc_lo, s1, v13, vcc_lo v_add_co_u32 v25, vcc_lo, s0, v25 v_lshlrev_b64 v[4:5], 2, v[4:5] v_add_co_ci_u32_e32 v26, vcc_lo, s1, v26, vcc_lo v_add_co_u32 v27, vcc_lo, s0, v27 v_add_co_ci_u32_e32 v28, vcc_lo, s1, v28, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v4, vcc_lo, s0, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo s_clause 0xa global_store_b32 v[17:18], v2, off global_store_b32 v[19:20], v3, off global_store_b32 v[6:7], v0, off global_store_b32 v[21:22], v2, off global_store_b32 v[15:16], v3, off global_store_b32 v[23:24], v0, off global_store_b32 v[8:9], v2, off global_store_b32 v[10:11], v3, off global_store_b32 v[12:13], v0, off global_store_b32 v[25:26], v2, off global_store_b32 v[27:28], v3, off .LBB0_29: ; %.sink.split global_store_b32 v[4:5], v0, off .LBB0_30: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z20gpu_calcColor_kerneliPfffffffffbbS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 320 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 29 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z20gpu_calcColor_kerneliPfffffffffbbS_, .Lfunc_end0-_Z20gpu_calcColor_kerneliPfffffffffbbS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1288 ; NumSgprs: 18 ; NumVgprs: 29 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 3 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 29 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: by_value - .offset: 44 .size: 4 .value_kind: by_value - .offset: 48 .size: 1 .value_kind: by_value - .offset: 49 .size: 1 .value_kind: by_value - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .offset: 64 .size: 4 .value_kind: hidden_block_count_x - .offset: 68 .size: 4 .value_kind: hidden_block_count_y - .offset: 72 .size: 4 .value_kind: hidden_block_count_z - .offset: 76 .size: 2 .value_kind: hidden_group_size_x - .offset: 78 .size: 2 .value_kind: hidden_group_size_y - .offset: 80 .size: 2 .value_kind: hidden_group_size_z - .offset: 82 .size: 2 .value_kind: hidden_remainder_x - .offset: 84 .size: 2 .value_kind: hidden_remainder_y - .offset: 86 .size: 2 .value_kind: hidden_remainder_z - .offset: 104 .size: 8 .value_kind: hidden_global_offset_x - .offset: 112 .size: 8 .value_kind: hidden_global_offset_y - .offset: 120 .size: 8 .value_kind: hidden_global_offset_z - .offset: 128 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 320 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z20gpu_calcColor_kerneliPfffffffffbbS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z20gpu_calcColor_kerneliPfffffffffbbS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 29 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "c720ca84927897e8b3bc2ff5183b0190a7e1ea92.hip" .globl _Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_ # -- Begin function _Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_ .p2align 4, 0x90 .type _Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_,@function _Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_: # @_Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_ .cfi_startproc # %bb.0: subq $216, %rsp .cfi_def_cfa_offset 224 movl %edi, 44(%rsp) movq %rsi, 104(%rsp) movss %xmm0, 40(%rsp) movss %xmm1, 36(%rsp) movss %xmm2, 32(%rsp) movss %xmm3, 28(%rsp) movss %xmm4, 24(%rsp) movss %xmm5, 20(%rsp) movss %xmm6, 16(%rsp) movss %xmm7, 12(%rsp) movb %dl, 11(%rsp) movb %cl, 10(%rsp) movq %r8, 96(%rsp) leaq 44(%rsp), %rax movq %rax, 112(%rsp) leaq 104(%rsp), %rax movq %rax, 120(%rsp) leaq 40(%rsp), %rax movq %rax, 128(%rsp) leaq 36(%rsp), %rax movq %rax, 136(%rsp) leaq 32(%rsp), %rax movq %rax, 144(%rsp) leaq 28(%rsp), %rax movq %rax, 152(%rsp) leaq 24(%rsp), %rax movq %rax, 160(%rsp) leaq 20(%rsp), %rax movq %rax, 168(%rsp) leaq 16(%rsp), %rax movq %rax, 176(%rsp) leaq 12(%rsp), %rax movq %rax, 184(%rsp) leaq 11(%rsp), %rax movq %rax, 192(%rsp) leaq 10(%rsp), %rax movq %rax, 200(%rsp) leaq 96(%rsp), %rax movq %rax, 208(%rsp) leaq 80(%rsp), %rdi leaq 64(%rsp), %rsi leaq 56(%rsp), %rdx leaq 48(%rsp), %rcx callq __hipPopCallConfiguration movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 64(%rsp), %rcx movl 72(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z20gpu_calcColor_kerneliPfffffffffbbS_, %edi pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $232, %rsp .cfi_adjust_cfa_offset -232 retq .Lfunc_end0: .size _Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_, .Lfunc_end0-_Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_ .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function gpu_calcColor .LCPI1_0: .long 0x3b800000 # float 0.00390625 .text .globl gpu_calcColor .p2align 4, 0x90 .type gpu_calcColor,@function gpu_calcColor: # @gpu_calcColor .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $256, %rsp # imm = 0x100 .cfi_def_cfa_offset 304 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r8, %rbx movl %ecx, %ebp movl %edx, %r14d movss %xmm7, 40(%rsp) # 4-byte Spill movss %xmm6, 36(%rsp) # 4-byte Spill movss %xmm5, 32(%rsp) # 4-byte Spill movss %xmm4, 28(%rsp) # 4-byte Spill movss %xmm3, 24(%rsp) # 4-byte Spill movss %xmm2, 20(%rsp) # 4-byte Spill movss %xmm1, 16(%rsp) # 4-byte Spill movl %edi, %r15d xorps %xmm1, %xmm1 cvtsi2ss %edi, %xmm1 movss %xmm0, 12(%rsp) # 4-byte Spill movq %rsi, %r12 mulss .LCPI1_0(%rip), %xmm1 movaps %xmm1, %xmm0 callq ceilf@PLT cvttss2si %xmm0, %edi movabsq $4294967296, %rdx # imm = 0x100000000 orq %rdx, %rdi orq $256, %rdx # imm = 0x100 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movl %r15d, 76(%rsp) movq %r12, 136(%rsp) movss 12(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, 72(%rsp) movss 16(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, 68(%rsp) movss 20(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, 64(%rsp) movss 24(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, 60(%rsp) movss 28(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, 56(%rsp) movss 32(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, 52(%rsp) movss 36(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, 48(%rsp) movss 40(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, 44(%rsp) movb %r14b, 11(%rsp) movb %bpl, 10(%rsp) movq %rbx, 128(%rsp) leaq 76(%rsp), %rax movq %rax, 144(%rsp) leaq 136(%rsp), %rax movq %rax, 152(%rsp) leaq 72(%rsp), %rax movq %rax, 160(%rsp) leaq 68(%rsp), %rax movq %rax, 168(%rsp) leaq 64(%rsp), %rax movq %rax, 176(%rsp) leaq 60(%rsp), %rax movq %rax, 184(%rsp) leaq 56(%rsp), %rax movq %rax, 192(%rsp) leaq 52(%rsp), %rax movq %rax, 200(%rsp) leaq 48(%rsp), %rax movq %rax, 208(%rsp) leaq 44(%rsp), %rax movq %rax, 216(%rsp) leaq 11(%rsp), %rax movq %rax, 224(%rsp) leaq 10(%rsp), %rax movq %rax, 232(%rsp) leaq 128(%rsp), %rax movq %rax, 240(%rsp) leaq 112(%rsp), %rdi leaq 96(%rsp), %rsi leaq 88(%rsp), %rdx leaq 80(%rsp), %rcx callq __hipPopCallConfiguration movq 112(%rsp), %rsi movl 120(%rsp), %edx movq 96(%rsp), %rcx movl 104(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z20gpu_calcColor_kerneliPfffffffffbbS_, %edi pushq 80(%rsp) .cfi_adjust_cfa_offset 8 pushq 96(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: addq $256, %rsp # imm = 0x100 .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size gpu_calcColor, .Lfunc_end1-gpu_calcColor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z20gpu_calcColor_kerneliPfffffffffbbS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z20gpu_calcColor_kerneliPfffffffffbbS_,@object # @_Z20gpu_calcColor_kerneliPfffffffffbbS_ .section .rodata,"a",@progbits .globl _Z20gpu_calcColor_kerneliPfffffffffbbS_ .p2align 3, 0x0 _Z20gpu_calcColor_kerneliPfffffffffbbS_: .quad _Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_ .size _Z20gpu_calcColor_kerneliPfffffffffbbS_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z20gpu_calcColor_kerneliPfffffffffbbS_" .size .L__unnamed_1, 40 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z20gpu_calcColor_kerneliPfffffffffbbS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
6,646
3,743
7,472
4,140
155
code for sm_80 Function : _Z8postScanPfS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R7, SR_CTAID.X ; IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; ULDC.64 UR6, c[0x0][0x118] ; S2R R6, SR_TID.X ; IMAD R0, R7, c[0x0][0x0], R6 ; IMAD.WIDE R2, R0, R8, c[0x0][0x160] ; LDG.E R19, [R2.64] ; IMAD.SHL.U32 R4, R6.reuse, 0x2, RZ ; LEA.HI R6, R6, R6, RZ, 0x1b ; BSSY B0, 0x2a0 ; IADD3 R5, R4, 0x2, RZ ; IMAD.SHL.U32 R21, R5.reuse, 0x200, RZ ; IMAD.SHL.U32 R18, R5.reuse, 0x100, RZ ; IMAD.SHL.U32 R9, R5, 0x80, RZ ; IADD3 R23, R21, -0x1, RZ ; IMAD.SHL.U32 R10, R5.reuse, 0x40, RZ ; IMAD.SHL.U32 R12, R5, 0x20, RZ ; ISETP.GT.AND P0, PT, R23.reuse, 0x3ff, PT ; IMAD.IADD R20, R23, 0x1, -R18 ; IMAD.SHL.U32 R14, R5.reuse, 0x10, RZ ; IMAD.IADD R11, R20.reuse, 0x1, -R9 ; ISETP.GT.AND P1, PT, R20, 0x3ff, PT ; IMAD.SHL.U32 R16, R5, 0x8, RZ ; IMAD.IADD R13, R11, 0x1, -R10 ; IMAD.IADD R15, R13, 0x1, -R12 ; IMAD.IADD R17, R15, 0x1, -R14 ; STS [R6.X4], R19 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P0 BRA 0x290 ; IADD3 R19, R21, 0x1ff, RZ ; SHF.R.S32.HI R22, RZ, 0x1f, R23 ; SHF.R.S32.HI R24, RZ, 0x1f, R19 ; LEA.HI R22, R22, R23, RZ, 0x5 ; LEA.HI R24, R24, R19, RZ, 0x5 ; LEA.HI.SX32 R22, R22, R23, 0x1b ; LEA.HI.SX32 R24, R24, R21, 0x1b ; LDS R22, [R22.X4] ; LDS R19, [R24.X4+0x7fc] ; FADD R19, R19, R22 ; STS [R24.X4+0x7fc], R19 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; IMAD.SHL.U32 R19, R5, 0x4, RZ ; IMAD.IADD R22, R17, 0x1, -R16 ; BSSY B0, 0x3b0 ; @P1 BRA 0x3a0 ; IADD3 R23, R18, 0xff, RZ ; SHF.R.S32.HI R21, RZ, 0x1f, R20 ; SHF.R.S32.HI R24, RZ, 0x1f, R23 ; LEA.HI R21, R21, R20.reuse, RZ, 0x5 ; LEA.HI R23, R24, R23, RZ, 0x5 ; LEA.HI.SX32 R21, R21, R20, 0x1b ; LEA.HI.SX32 R23, R23, R18, 0x1b ; LDS R21, [R21.X4] ; LDS R18, [R23.X4+0x3fc] ; FADD R18, R18, R21 ; STS [R23.X4+0x3fc], R18 ; BSYNC B0 ; ISETP.GT.AND P6, PT, R11, 0x3ff, PT ; IMAD.SHL.U32 R18, R5, 0x2, RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GT.AND P3, PT, R13, 0x3ff, PT ; IMAD.IADD R21, R22, 0x1, -R19 ; ISETP.GT.AND P0, PT, R4, 0x3fe, PT ; P2R R20, PR, RZ, 0x8 ; IMAD.IADD R20, R21, 0x1, -R18 ; BSSY B0, 0x560 ; ISETP.GT.AND P1, PT, R15, 0x3ff, PT ; ISETP.GT.AND P2, PT, R17, 0x3ff, PT ; ISETP.GT.AND P3, PT, R22, 0x3ff, PT ; ISETP.GT.AND P4, PT, R21, 0x3ff, PT ; ISETP.GT.AND P5, PT, R20, 0x3ff, PT ; @P6 BRA 0x550 ; IADD3 R23, R9, 0x7f, RZ ; SHF.R.S32.HI R24, RZ, 0x1f, R11 ; SHF.R.S32.HI R26, RZ, 0x1f, R23 ; LEA.HI R24, R24, R11, RZ, 0x5 ; LEA.HI R26, R26, R23, RZ, 0x5 ; LEA.HI.SX32 R24, R24, R11, 0x1b ; LEA.HI.SX32 R26, R26, R9, 0x1b ; LDS R24, [R24.X4] ; LDS R9, [R26.X4+0x1fc] ; FADD R9, R9, R24 ; STS [R26.X4+0x1fc], R9 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GT.AND P6, PT, R13, 0x3ff, PT ; BSSY B0, 0x660 ; @P6 BRA 0x650 ; IADD3 R9, R10, 0x3f, RZ ; SHF.R.S32.HI R24, RZ, 0x1f, R13 ; SHF.R.S32.HI R26, RZ, 0x1f, R9 ; LEA.HI R24, R24, R13, RZ, 0x5 ; LEA.HI R9, R26, R9, RZ, 0x5 ; LEA.HI.SX32 R24, R24, R13, 0x1b ; LEA.HI.SX32 R9, R9, R10, 0x1b ; LDS R11, [R24.X4] ; LDS R10, [R9.X4+0xfc] ; FADD R10, R10, R11 ; STS [R9.X4+0xfc], R10 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0x750 ; @P1 BRA 0x740 ; IADD3 R9, R12, 0x1f, RZ ; SHF.R.S32.HI R10, RZ, 0x1f, R15 ; SHF.R.S32.HI R24, RZ, 0x1f, R9 ; LEA.HI R10, R10, R15, RZ, 0x5 ; LEA.HI R9, R24, R9, RZ, 0x5 ; LEA.HI.SX32 R10, R10, R15, 0x1b ; LEA.HI.SX32 R9, R9, R12, 0x1b ; LDS R10, [R10.X4] ; LDS R11, [R9.X4+0x7c] ; FADD R12, R11, R10 ; STS [R9.X4+0x7c], R12 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0x840 ; @P2 BRA 0x830 ; IADD3 R9, R14, 0xf, RZ ; SHF.R.S32.HI R10, RZ, 0x1f, R17 ; SHF.R.S32.HI R12, RZ, 0x1f, R9 ; LEA.HI R10, R10, R17, RZ, 0x5 ; LEA.HI R9, R12, R9, RZ, 0x5 ; LEA.HI.SX32 R10, R10, R17, 0x1b ; LEA.HI.SX32 R9, R9, R14, 0x1b ; LDS R10, [R10.X4] ; LDS R11, [R9.X4+0x3c] ; FADD R12, R11, R10 ; STS [R9.X4+0x3c], R12 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0x930 ; @P3 BRA 0x920 ; IADD3 R10, R16, 0x7, RZ ; SHF.R.S32.HI R9, RZ, 0x1f, R22 ; SHF.R.S32.HI R11, RZ, 0x1f, R10 ; LEA.HI R9, R9, R22, RZ, 0x5 ; LEA.HI R11, R11, R10, RZ, 0x5 ; LEA.HI.SX32 R9, R9, R22, 0x1b ; LEA.HI.SX32 R11, R11, R16, 0x1b ; LDS R9, [R9.X4] ; LDS R10, [R11.X4+0x1c] ; FADD R10, R10, R9 ; STS [R11.X4+0x1c], R10 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0xa20 ; @P4 BRA 0xa10 ; IADD3 R9, R19, 0x3, RZ ; SHF.R.S32.HI R10, RZ, 0x1f, R21 ; SHF.R.S32.HI R12, RZ, 0x1f, R9 ; LEA.HI R10, R10, R21, RZ, 0x5 ; LEA.HI R12, R12, R9, RZ, 0x5 ; LEA.HI.SX32 R10, R10, R21, 0x1b ; LEA.HI.SX32 R12, R12, R19, 0x1b ; LDS R10, [R10.X4] ; LDS R9, [R12.X4+0xc] ; FADD R9, R9, R10 ; STS [R12.X4+0xc], R9 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; IMAD.WIDE.U32 R8, R7, R8, c[0x0][0x168] ; BSSY B0, 0xb20 ; @P5 BRA 0xb10 ; IADD3 R10, R18, 0x1, RZ ; SHF.R.S32.HI R7, RZ, 0x1f, R20 ; SHF.R.S32.HI R11, RZ, 0x1f, R10 ; LEA.HI R7, R7, R20, RZ, 0x5 ; LEA.HI R11, R11, R10, RZ, 0x5 ; LEA.HI.SX32 R7, R7, R20, 0x1b ; LEA.HI.SX32 R11, R11, R18, 0x1b ; LDS R7, [R7.X4] ; LDS R10, [R11.X4+0x4] ; FADD R10, R10, R7 ; STS [R11.X4+0x4], R10 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0xc10 ; @P0 BRA 0xc00 ; IADD3 R7, R4, 0x1, RZ ; SHF.R.S32.HI R12, RZ, 0x1f, R5 ; SHF.R.S32.HI R10, RZ, 0x1f, R7 ; LEA.HI R12, R12, R5, RZ, 0x5 ; LEA.HI R7, R10, R7, RZ, 0x5 ; LEA.HI.SX32 R12, R12, R5, 0x1b ; LEA.HI.SX32 R7, R7, R4, 0x1b ; LDS R4, [R12.X4] ; LDS R7, [R7.X4+0x4] ; FADD R5, R4, R7 ; STS [R12.X4], R5 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDG.E R9, [R8.64] ; ULDC UR4, c[0x0][0x170] ; ISETP.NE.AND P1, PT, R0.reuse, RZ, PT ; UIADD3 UR4, UR4, -0x1, URZ ; LDS R4, [R6.X4] ; ISETP.GE.AND P0, PT, R0, UR4, PT ; FADD R5, R4, R9 ; STS [R6.X4], R5 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P0 LDS R7, [R6.X4] ; @!P0 STG.E [R2.64+0x4], R7 ; @P1 EXIT ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; STG.E [R2.64], RZ ; EXIT ; BRA 0xd20; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z16fixBetweenBlocksPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; MOV R2, c[0x0][0x170] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; ULDC.64 UR10, c[0x0][0x118] ; ISETP.GE.AND P0, PT, R0, 0x2, PT ; STG.E [R2.64], RZ ; @!P0 EXIT ; IADD3 R2, R0.reuse, -0x2, RZ ; UMOV UR4, 0x1 ; IADD3 R0, R0, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0x980 ; IADD3 R6, -R0, c[0x0][0x178], RZ ; UMOV UR4, 0x1 ; HFMA2.MMA R7, -RZ, RZ, 0, 0 ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; ISETP.GT.AND P0, PT, R6, 0x1, PT ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; MOV R3, c[0x0][0x16c] ; MOV R5, c[0x0][0x174] ; @!P0 BRA 0x800 ; IADD3 R8, R6, -0x1, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; ISETP.GT.AND P1, PT, R8, 0xc, PT ; @!P1 BRA 0x580 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E R8, [R2.64] ; FADD R7, R8, R7 ; STG.E [R4.64+0x4], R7 ; LDG.E R8, [R2.64+0x4] ; FADD R9, R7, R8 ; STG.E [R4.64+0x8], R9 ; LDG.E R8, [R2.64+0x8] ; FADD R11, R9, R8 ; STG.E [R4.64+0xc], R11 ; LDG.E R8, [R2.64+0xc] ; FADD R13, R11, R8 ; STG.E [R4.64+0x10], R13 ; LDG.E R8, [R2.64+0x10] ; FADD R7, R13, R8 ; STG.E [R4.64+0x14], R7 ; LDG.E R8, [R2.64+0x14] ; FADD R9, R7, R8 ; STG.E [R4.64+0x18], R9 ; LDG.E R8, [R2.64+0x18] ; FADD R11, R9, R8 ; STG.E [R4.64+0x1c], R11 ; LDG.E R8, [R2.64+0x1c] ; FADD R13, R11, R8 ; STG.E [R4.64+0x20], R13 ; LDG.E R8, [R2.64+0x20] ; FADD R7, R13, R8 ; STG.E [R4.64+0x24], R7 ; LDG.E R8, [R2.64+0x24] ; FADD R9, R7, R8 ; STG.E [R4.64+0x28], R9 ; LDG.E R8, [R2.64+0x28] ; FADD R11, R9, R8 ; STG.E [R4.64+0x2c], R11 ; LDG.E R8, [R2.64+0x2c] ; FADD R13, R11, R8 ; STG.E [R4.64+0x30], R13 ; LDG.E R8, [R2.64+0x30] ; FADD R15, R13, R8 ; STG.E [R4.64+0x34], R15 ; LDG.E R8, [R2.64+0x34] ; FADD R9, R15, R8 ; STG.E [R4.64+0x38], R9 ; LDG.E R8, [R2.64+0x38] ; IADD3 R6, R6, -0x10, RZ ; FADD R11, R9, R8 ; STG.E [R4.64+0x3c], R11 ; LDG.E R8, [R2.64+0x3c] ; ISETP.GT.AND P1, PT, R6, 0xd, PT ; UIADD3 UR4, UR4, 0x10, URZ ; IADD3 R10, P2, R4, 0x40, RZ ; IADD3.X R13, RZ, R5, RZ, P2, !PT ; FADD R7, R11, R8 ; IADD3 R8, P3, R2, 0x40, RZ ; STG.E [R4.64+0x40], R7 ; IMAD.X R9, RZ, RZ, R3, P3 ; IMAD.MOV.U32 R2, RZ, RZ, R8 ; MOV R3, R9 ; IMAD.MOV.U32 R4, RZ, RZ, R10 ; MOV R5, R13 ; @P1 BRA 0x1c0 ; IADD3 R8, R6, -0x1, RZ ; ISETP.GT.AND P1, PT, R8, 0x4, PT ; @!P1 BRA 0x7e0 ; LDG.E R8, [R2.64] ; FADD R7, R7, R8 ; STG.E [R4.64+0x4], R7 ; LDG.E R8, [R2.64+0x4] ; FADD R9, R7, R8 ; STG.E [R4.64+0x8], R9 ; LDG.E R8, [R2.64+0x8] ; FADD R11, R9, R8 ; STG.E [R4.64+0xc], R11 ; LDG.E R8, [R2.64+0xc] ; FADD R13, R11, R8 ; STG.E [R4.64+0x10], R13 ; LDG.E R8, [R2.64+0x10] ; FADD R15, R13, R8 ; STG.E [R4.64+0x14], R15 ; LDG.E R8, [R2.64+0x14] ; FADD R9, R15, R8 ; STG.E [R4.64+0x18], R9 ; LDG.E R8, [R2.64+0x18] ; FADD R11, R9, R8 ; STG.E [R4.64+0x1c], R11 ; LDG.E R8, [R2.64+0x1c] ; IADD3 R10, P1, R4, 0x20, RZ ; UIADD3 UR4, UR4, 0x8, URZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3.X R13, RZ, R5, RZ, P1, !PT ; IADD3 R6, R6, -0x8, RZ ; FADD R7, R11, R8 ; IADD3 R8, P2, R2, 0x20, RZ ; STG.E [R4.64+0x20], R7 ; IMAD.X R9, RZ, RZ, R3, P2 ; IMAD.MOV.U32 R2, RZ, RZ, R8 ; MOV R3, R9 ; IMAD.MOV.U32 R4, RZ, RZ, R10 ; MOV R5, R13 ; ISETP.NE.OR P0, PT, R6, 0x1, P0 ; @!P0 BRA 0x980 ; LDG.E R8, [R2.64] ; FADD R9, R8, R7 ; STG.E [R4.64+0x4], R9 ; LDG.E R8, [R2.64+0x4] ; FADD R11, R9, R8 ; STG.E [R4.64+0x8], R11 ; LDG.E R8, [R2.64+0x8] ; IADD3 R6, R6, -0x4, RZ ; FADD R13, R11, R8 ; STG.E [R4.64+0xc], R13 ; LDG.E R8, [R2.64+0xc] ; ISETP.NE.AND P0, PT, R6, 0x1, PT ; UIADD3 UR4, UR4, 0x4, URZ ; IADD3 R10, P1, R4, 0x10, RZ ; IADD3.X R11, RZ, R5, RZ, P1, !PT ; FADD R7, R13, R8 ; IADD3 R8, P2, R2, 0x10, RZ ; STG.E [R4.64+0x10], R7 ; IMAD.X R9, RZ, RZ, R3, P2 ; IMAD.MOV.U32 R2, RZ, RZ, R8 ; MOV R3, R9 ; IMAD.MOV.U32 R4, RZ, RZ, R10 ; MOV R5, R11 ; @P0 BRA 0x800 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P0 EXIT ; UIADD3 UR8, UR4, -0x1, URZ ; UMOV UR9, 0x4 ; ULDC.64 UR6, c[0x0][0x170] ; UIMAD.WIDE UR6, UR8, UR9, UR6 ; ULDC.64 UR4, c[0x0][0x168] ; UIMAD.WIDE UR4, UR8, UR9, UR4 ; IMAD.U32 R2, RZ, RZ, UR6 ; MOV R5, UR7 ; IMAD.U32 R4, RZ, RZ, UR6 ; MOV R3, UR7 ; IMAD.MOV.U32 R6, RZ, RZ, R2 ; MOV R9, R5 ; IMAD.U32 R4, RZ, RZ, UR4 ; MOV R5, UR5 ; IMAD.MOV.U32 R2, RZ, RZ, R6 ; MOV R3, R9 ; LDG.E R4, [R4.64] ; LDG.E R7, [R2.64] ; IADD3 R0, R0, -0x1, RZ ; ISETP.NE.AND P0, PT, R0, RZ, PT ; UIADD3 UR4, UP0, UR4, 0x4, URZ ; IADD3 R6, P1, R2, 0x4, RZ ; UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; IADD3.X R9, RZ, R3, RZ, P1, !PT ; FADD R7, R4, R7 ; STG.E [R2.64+0x4], R7 ; @P0 BRA 0xa60 ; EXIT ; BRA 0xb60; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z9reductionPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R3, SR_TID.X ; IMAD R2, R0, c[0x0][0x0], R3 ; IMAD.WIDE R12, R2, R5, c[0x0][0x168] ; LDG.E R19, [R12.64] ; IMAD.SHL.U32 R10, R3.reuse, 0x2, RZ ; LEA.HI R6, R3, R3, RZ, 0x1b ; BSSY B0, 0x250 ; IADD3 R4, R10.reuse, 0x2, RZ ; ISETP.GT.AND P0, PT, R10, 0x3fe, PT ; IMAD.SHL.U32 R8, R4, 0x2, RZ ; IADD3 R17, R8, -0x1, RZ ; ISETP.GT.AND P1, PT, R17, 0x3ff, PT ; IMAD.IADD R7, R8, 0x1, R17 ; IMAD R9, R4, 0x4, R7 ; ISETP.GE.AND P6, PT, R7, 0x400, PT ; IMAD R11, R4, 0x8, R9 ; IMAD R13, R4, 0x10, R11 ; IMAD R15, R4, 0x20, R13 ; STS [R6.X4], R19 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P0 BRA 0x240 ; IADD3 R12, R10, 0x1, RZ ; SHF.R.S32.HI R19, RZ, 0x1f, R10 ; SHF.R.S32.HI R21, RZ, 0x1f, R12 ; LEA.HI R19, R19, R10, RZ, 0x5 ; LEA.HI R21, R21, R12, RZ, 0x5 ; LEA.HI.SX32 R19, R19, R10.reuse, 0x1b ; LEA.HI.SX32 R21, R21, R10, 0x1b ; LDS R19, [R19.X4] ; LDS R10, [R21.X4+0x4] ; FADD R10, R10, R19 ; STS [R21.X4+0x4], R10 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; IMAD R19, R4, 0x40, R15 ; BSSY B0, 0x350 ; @P1 BRA 0x340 ; IADD3 R10, R8, -0x3, RZ ; SHF.R.S32.HI R12, RZ, 0x1f, R17 ; SHF.R.S32.HI R21, RZ, 0x1f, R10 ; LEA.HI R12, R12, R17.reuse, RZ, 0x5 ; LEA.HI R21, R21, R10, RZ, 0x5 ; LEA.HI.SX32 R12, R12, R17, 0x1b ; LEA.HI.SX32 R21, R21, R8, 0x1b ; LDS R8, [R12.X4] ; LDS R21, [R21.X4+-0xc] ; FADD R17, R8, R21 ; STS [R12.X4], R17 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P1, PT, R9, 0x400, PT ; IMAD R17, R4.reuse, 0x80, R19 ; ISETP.GE.AND P0, PT, R11, 0x400, PT ; P2R R8, PR, RZ, 0x2 ; IMAD R8, R4, 0x100, R17 ; BSSY B0, 0x4f0 ; ISETP.GE.AND P1, PT, R13, 0x400, PT ; ISETP.GE.AND P2, PT, R15, 0x400, PT ; ISETP.GE.AND P3, PT, R19, 0x400, PT ; ISETP.GE.AND P4, PT, R17, 0x400, PT ; ISETP.GT.AND P5, PT, R8, 0x3ff, PT ; @P6 BRA 0x4e0 ; IADD3 R12, R7, -0x4, RZ ; IMAD.SHL.U32 R10, R4, 0x4, RZ ; SHF.R.S32.HI R14, RZ, 0x1f, R7 ; SHF.R.S32.HI R21, RZ, 0x1f, R12 ; LEA.HI R14, R14, R7, RZ, 0x5 ; LEA.HI R21, R21, R12, RZ, 0x5 ; LEA.HI.SX32 R14, R14, R7, 0x1b ; LEA.HI.SX32 R10, R21, R10, 0x1b ; LDS R7, [R14.X4] ; LDS R10, [R10.X4+-0x14] ; FADD R7, R7, R10 ; STS [R14.X4], R7 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P6, PT, R9, 0x400, PT ; BSSY B0, 0x600 ; @P6 BRA 0x5f0 ; IADD3 R10, R9, -0x8, RZ ; IMAD.SHL.U32 R7, R4, 0x8, RZ ; SHF.R.S32.HI R12, RZ, 0x1f, R9 ; SHF.R.S32.HI R21, RZ, 0x1f, R10 ; LEA.HI R12, R12, R9.reuse, RZ, 0x5 ; LEA.HI R10, R21, R10, RZ, 0x5 ; LEA.HI.SX32 R12, R12, R9, 0x1b ; LEA.HI.SX32 R7, R10, R7, 0x1b ; LDS R9, [R12.X4] ; LDS R10, [R7.X4+-0x24] ; FADD R9, R9, R10 ; STS [R12.X4], R9 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0x700 ; @P0 BRA 0x6f0 ; IADD3 R9, R11, -0x10, RZ ; IMAD.SHL.U32 R7, R4, 0x10, RZ ; SHF.R.S32.HI R12, RZ, 0x1f, R11 ; SHF.R.S32.HI R10, RZ, 0x1f, R9 ; LEA.HI R12, R12, R11, RZ, 0x5 ; LEA.HI R10, R10, R9, RZ, 0x5 ; LEA.HI.SX32 R12, R12, R11, 0x1b ; LEA.HI.SX32 R7, R10, R7, 0x1b ; LDS R9, [R12.X4] ; LDS R10, [R7.X4+-0x44] ; FADD R9, R9, R10 ; STS [R12.X4], R9 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0x800 ; @P1 BRA 0x7f0 ; IADD3 R9, R13, -0x20, RZ ; IMAD.SHL.U32 R7, R4, 0x20, RZ ; SHF.R.S32.HI R12, RZ, 0x1f, R13 ; SHF.R.S32.HI R10, RZ, 0x1f, R9 ; LEA.HI R12, R12, R13, RZ, 0x5 ; LEA.HI R10, R10, R9, RZ, 0x5 ; LEA.HI.SX32 R12, R12, R13, 0x1b ; LEA.HI.SX32 R7, R10, R7, 0x1b ; LDS R9, [R12.X4] ; LDS R10, [R7.X4+-0x84] ; FADD R9, R9, R10 ; STS [R12.X4], R9 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0x900 ; @P2 BRA 0x8f0 ; IADD3 R9, R15, -0x40, RZ ; IMAD.SHL.U32 R7, R4, 0x40, RZ ; SHF.R.S32.HI R12, RZ, 0x1f, R15 ; SHF.R.S32.HI R10, RZ, 0x1f, R9 ; LEA.HI R12, R12, R15, RZ, 0x5 ; LEA.HI R10, R10, R9, RZ, 0x5 ; LEA.HI.SX32 R12, R12, R15, 0x1b ; LEA.HI.SX32 R7, R10, R7, 0x1b ; LDS R9, [R12.X4] ; LDS R10, [R7.X4+-0x104] ; FADD R9, R9, R10 ; STS [R12.X4], R9 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0xa00 ; @P3 BRA 0x9f0 ; IADD3 R9, R19, -0x80, RZ ; IMAD.SHL.U32 R7, R4, 0x80, RZ ; SHF.R.S32.HI R12, RZ, 0x1f, R19 ; SHF.R.S32.HI R10, RZ, 0x1f, R9 ; LEA.HI R12, R12, R19, RZ, 0x5 ; LEA.HI R10, R10, R9, RZ, 0x5 ; LEA.HI.SX32 R12, R12, R19, 0x1b ; LEA.HI.SX32 R7, R10, R7, 0x1b ; LDS R9, [R12.X4] ; LDS R10, [R7.X4+-0x204] ; FADD R9, R9, R10 ; STS [R12.X4], R9 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0xb00 ; @P4 BRA 0xaf0 ; IADD3 R9, R17, -0x100, RZ ; IMAD.SHL.U32 R7, R4, 0x100, RZ ; SHF.R.S32.HI R12, RZ, 0x1f, R17 ; SHF.R.S32.HI R10, RZ, 0x1f, R9 ; LEA.HI R12, R12, R17, RZ, 0x5 ; LEA.HI R10, R10, R9, RZ, 0x5 ; LEA.HI.SX32 R12, R12, R17, 0x1b ; LEA.HI.SX32 R7, R10, R7, 0x1b ; LDS R9, [R12.X4] ; LDS R10, [R7.X4+-0x404] ; FADD R9, R9, R10 ; STS [R12.X4], R9 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; BSSY B0, 0xc00 ; @P5 BRA 0xbf0 ; IADD3 R7, R8, -0x200, RZ ; IMAD.SHL.U32 R4, R4, 0x200, RZ ; SHF.R.S32.HI R9, RZ, 0x1f, R8 ; SHF.R.S32.HI R10, RZ, 0x1f, R7 ; LEA.HI R9, R9, R8.reuse, RZ, 0x5 ; LEA.HI R7, R10, R7, RZ, 0x5 ; LEA.HI.SX32 R9, R9, R8, 0x1b ; LEA.HI.SX32 R4, R7, R4, 0x1b ; LDS R7, [R9.X4] ; LDS R4, [R4.X4+-0x804] ; FADD R8, R7, R4 ; STS [R9.X4], R8 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.AND P0, PT, R3, 0x3ff, PT ; SHF.R.S32.HI R9, RZ, 0x1f, R2 ; LEA R8, P1, R2, c[0x0][0x160], 0x2 ; LEA.HI.X R9, R2, c[0x0][0x164], R9, 0x2, P1 ; LDS R7, [R6.X4] ; STG.E [R8.64], R7 ; @P0 EXIT ; LDS R7, [0x1078] ; IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x170] ; STG.E [R2.64], R7 ; EXIT ; BRA 0xcc0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00098f35_00000000-6_90df690bfb2d3a55886b1aa9fb7123429190df55.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2030: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2030: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z33__device_stub__Z9reductionPfS_S_iPfS_S_i .type _Z33__device_stub__Z9reductionPfS_S_iPfS_S_i, @function _Z33__device_stub__Z9reductionPfS_S_iPfS_S_i: .LFB2052: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z9reductionPfS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2052: .size _Z33__device_stub__Z9reductionPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9reductionPfS_S_iPfS_S_i .globl _Z9reductionPfS_S_i .type _Z9reductionPfS_S_i, @function _Z9reductionPfS_S_i: .LFB2053: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z33__device_stub__Z9reductionPfS_S_iPfS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2053: .size _Z9reductionPfS_S_i, .-_Z9reductionPfS_S_i .globl _Z41__device_stub__Z16fixBetweenBlocksPfS_S_iPfS_S_i .type _Z41__device_stub__Z16fixBetweenBlocksPfS_S_iPfS_S_i, @function _Z41__device_stub__Z16fixBetweenBlocksPfS_S_iPfS_S_i: .LFB2054: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 136(%rsp), %rax subq %fs:40, %rax jne .L16 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z16fixBetweenBlocksPfS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2054: .size _Z41__device_stub__Z16fixBetweenBlocksPfS_S_iPfS_S_i, .-_Z41__device_stub__Z16fixBetweenBlocksPfS_S_iPfS_S_i .globl _Z16fixBetweenBlocksPfS_S_i .type _Z16fixBetweenBlocksPfS_S_i, @function _Z16fixBetweenBlocksPfS_S_i: .LFB2055: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z41__device_stub__Z16fixBetweenBlocksPfS_S_iPfS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2055: .size _Z16fixBetweenBlocksPfS_S_i, .-_Z16fixBetweenBlocksPfS_S_i .globl _Z30__device_stub__Z8postScanPfS_iPfS_i .type _Z30__device_stub__Z8postScanPfS_iPfS_i, @function _Z30__device_stub__Z8postScanPfS_iPfS_i: .LFB2056: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L23 .L19: movq 120(%rsp), %rax subq %fs:40, %rax jne .L24 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z8postScanPfS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L19 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE2056: .size _Z30__device_stub__Z8postScanPfS_iPfS_i, .-_Z30__device_stub__Z8postScanPfS_iPfS_i .globl _Z8postScanPfS_i .type _Z8postScanPfS_i, @function _Z8postScanPfS_i: .LFB2057: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z8postScanPfS_iPfS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z8postScanPfS_i, .-_Z8postScanPfS_i .globl _Z12prescanArrayPfS_S_S_i .type _Z12prescanArrayPfS_S_S_i, @function _Z12prescanArrayPfS_S_S_i: .LFB2027: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %rdi, %r12 movq %rsi, %r15 movq %rdx, %r14 movq %rcx, %r13 movl %r8d, %ebp leal 1022(%r8), %ebx movl %r8d, %eax subl $1, %eax cmovns %eax, %ebx sarl $10, %ebx addl $1, %ebx movl %ebx, (%rsp) movl $1, 4(%rsp) movl $1, 8(%rsp) movl $1024, 12(%rsp) movl $1, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $4096, %r8d movq 12(%rsp), %rdx movl $1, %ecx movq (%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L32 .L28: movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $0, %r9d movl $0, %r8d movq 36(%rsp), %rdx movl $1, %ecx movq 24(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L33 .L29: movl 20(%rsp), %ecx movl $0, %r9d movl $4096, %r8d movq 12(%rsp), %rdx movq (%rsp), %rdi movl 8(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L34 .L27: addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L32: .cfi_restore_state movl %ebp, %ecx movq %r14, %rdx movq %r15, %rsi movq %r12, %rdi call _Z33__device_stub__Z9reductionPfS_S_iPfS_S_i jmp .L28 .L33: movl %ebx, %ecx movq %r13, %rdx movq %r14, %rsi movq %r12, %rdi call _Z41__device_stub__Z16fixBetweenBlocksPfS_S_iPfS_S_i jmp .L29 .L34: movl %ebp, %edx movq %r13, %rsi movq %r12, %rdi call _Z30__device_stub__Z8postScanPfS_iPfS_i jmp .L27 .cfi_endproc .LFE2027: .size _Z12prescanArrayPfS_S_S_i, .-_Z12prescanArrayPfS_S_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z8postScanPfS_i" .LC1: .string "_Z16fixBetweenBlocksPfS_S_i" .LC2: .string "_Z9reductionPfS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2059: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z8postScanPfS_i(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z16fixBetweenBlocksPfS_S_i(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z9reductionPfS_S_i(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2059: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9reductionPfS_S_i ; -- Begin function _Z9reductionPfS_S_i .globl _Z9reductionPfS_S_i .p2align 8 .type _Z9reductionPfS_S_i,@function _Z9reductionPfS_S_i: ; @_Z9reductionPfS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s3, s[0:1], 0x2c s_load_b64 s[4:5], s[0:1], 0x8 s_mov_b32 s2, s15 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1] s_mov_b32 s3, exec_lo v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[3:4], 2, v[1:2] v_add_co_u32 v3, vcc_lo, s4, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo global_load_b32 v6, v[3:4], off v_lshlrev_b32_e32 v4, 1, v0 v_lshrrev_b32_e32 v3, 5, v0 v_or_b32_e32 v5, 1, v4 s_delay_alu instid0(VALU_DEP_2) v_add_lshl_u32 v3, v3, v0, 2 s_waitcnt vmcnt(0) ds_store_b32 v3, v6 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 0x400, v5 s_cbranch_execz .LBB0_2 ; %bb.1: v_lshrrev_b32_e32 v6, 4, v0 s_delay_alu instid0(VALU_DEP_1) v_add_lshl_u32 v7, v6, v4, 2 v_add_lshl_u32 v5, v6, v5, 2 ds_load_b32 v6, v7 ds_load_b32 v7, v5 s_waitcnt lgkmcnt(0) v_add_f32_e32 v6, v6, v7 ds_store_b32 v5, v6 .LBB0_2: s_or_b32 exec_lo, exec_lo, s3 v_add_nc_u32_e32 v4, 2, v4 s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 0x100, v0 s_cbranch_execz .LBB0_4 ; %bb.3: v_lshlrev_b32_e32 v5, 1, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v6, -3, v5 v_add_nc_u32_e32 v5, -1, v5 v_lshrrev_b32_e32 v7, 5, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v8, 5, v5 v_add_lshl_u32 v6, v7, v6, 2 s_delay_alu instid0(VALU_DEP_2) v_add_lshl_u32 v5, v8, v5, 2 ds_load_b32 v6, v6 ds_load_b32 v7, v5 s_waitcnt lgkmcnt(0) v_add_f32_e32 v6, v6, v7 ds_store_b32 v5, v6 .LBB0_4: s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 0x80, v0 s_cbranch_execz .LBB0_6 ; %bb.5: v_lshlrev_b32_e32 v5, 2, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v6, -5, v5 v_add_nc_u32_e32 v5, -1, v5 v_lshrrev_b32_e32 v7, 5, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v8, 5, v5 v_add_lshl_u32 v6, v7, v6, 2 s_delay_alu instid0(VALU_DEP_2) v_add_lshl_u32 v5, v8, v5, 2 ds_load_b32 v6, v6 ds_load_b32 v7, v5 s_waitcnt lgkmcnt(0) v_add_f32_e32 v6, v6, v7 ds_store_b32 v5, v6 .LBB0_6: s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 64, v0 s_cbranch_execz .LBB0_8 ; %bb.7: v_lshlrev_b32_e32 v5, 3, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v6, -9, v5 v_add_nc_u32_e32 v5, -1, v5 v_lshrrev_b32_e32 v7, 5, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v8, 5, v5 v_add_lshl_u32 v6, v7, v6, 2 s_delay_alu instid0(VALU_DEP_2) v_add_lshl_u32 v5, v8, v5, 2 ds_load_b32 v6, v6 ds_load_b32 v7, v5 s_waitcnt lgkmcnt(0) v_add_f32_e32 v6, v6, v7 ds_store_b32 v5, v6 .LBB0_8: s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 32, v0 s_cbranch_execz .LBB0_10 ; %bb.9: v_lshlrev_b32_e32 v5, 4, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v6, 17, v5 v_add_nc_u32_e32 v5, -1, v5 v_lshrrev_b32_e32 v7, 5, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v8, 5, v5 v_add_lshl_u32 v6, v7, v6, 2 s_delay_alu instid0(VALU_DEP_2) v_add_lshl_u32 v5, v8, v5, 2 ds_load_b32 v6, v6 ds_load_b32 v7, v5 s_waitcnt lgkmcnt(0) v_add_f32_e32 v6, v6, v7 ds_store_b32 v5, v6 .LBB0_10: s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 16, v0 s_cbranch_execz .LBB0_12 ; %bb.11: v_lshlrev_b32_e32 v5, 5, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v6, 33, v5 v_add_nc_u32_e32 v5, -1, v5 v_lshrrev_b32_e32 v7, 5, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v8, 5, v5 v_add_lshl_u32 v6, v7, v6, 2 s_delay_alu instid0(VALU_DEP_2) v_add_lshl_u32 v5, v8, v5, 2 ds_load_b32 v6, v6 ds_load_b32 v7, v5 s_waitcnt lgkmcnt(0) v_add_f32_e32 v6, v6, v7 ds_store_b32 v5, v6 .LBB0_12: s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 8, v0 s_cbranch_execz .LBB0_14 ; %bb.13: v_lshlrev_b32_e32 v5, 6, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v6, 0xffffffbf, v5 v_add_nc_u32_e32 v5, -1, v5 v_lshrrev_b32_e32 v7, 5, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v8, 5, v5 v_add_lshl_u32 v6, v7, v6, 2 s_delay_alu instid0(VALU_DEP_2) v_add_lshl_u32 v5, v8, v5, 2 ds_load_b32 v6, v6 ds_load_b32 v7, v5 s_waitcnt lgkmcnt(0) v_add_f32_e32 v6, v6, v7 ds_store_b32 v5, v6 .LBB0_14: s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 4, v0 s_cbranch_execz .LBB0_16 ; %bb.15: v_lshlrev_b32_e32 v5, 7, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v6, 0xffffff7f, v5 v_add_nc_u32_e32 v5, -1, v5 v_lshrrev_b32_e32 v7, 5, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v8, 5, v5 v_add_lshl_u32 v6, v7, v6, 2 s_delay_alu instid0(VALU_DEP_2) v_add_lshl_u32 v5, v8, v5, 2 ds_load_b32 v6, v6 ds_load_b32 v7, v5 s_waitcnt lgkmcnt(0) v_add_f32_e32 v6, v6, v7 ds_store_b32 v5, v6 .LBB0_16: s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 2, v0 s_cbranch_execz .LBB0_18 ; %bb.17: v_lshlrev_b32_e32 v4, 8, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v5, 0xfffffeff, v4 v_add_nc_u32_e32 v4, -1, v4 v_lshrrev_b32_e32 v6, 5, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v7, 5, v4 v_add_lshl_u32 v5, v6, v5, 2 s_delay_alu instid0(VALU_DEP_2) v_add_lshl_u32 v4, v7, v4, 2 ds_load_b32 v5, v5 ds_load_b32 v6, v4 s_waitcnt lgkmcnt(0) v_add_f32_e32 v5, v5, v6 ds_store_b32 v4, v5 .LBB0_18: s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_20 ; %bb.19: v_mov_b32_e32 v4, 0 ds_load_b32 v5, v4 offset:2104 ds_load_b32 v6, v4 offset:4216 s_waitcnt lgkmcnt(0) v_add_f32_e32 v5, v5, v6 ds_store_b32 v4, v5 offset:4216 .LBB0_20: s_or_b32 exec_lo, exec_lo, s3 s_load_b64 s[4:5], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv ds_load_b32 v3, v3 v_lshlrev_b64 v[1:2], 2, v[1:2] s_mov_b32 s3, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, s4, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo s_waitcnt lgkmcnt(0) global_store_b32 v[1:2], v3, off v_cmpx_eq_u32_e32 0x3ff, v0 s_cbranch_execz .LBB0_22 ; %bb.21: s_load_b64 s[0:1], s[0:1], 0x10 s_mov_b32 s3, 0 v_mov_b32_e32 v0, 0 s_lshl_b64 s[2:3], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s0, s0, s2 s_addc_u32 s1, s1, s3 global_store_b32 v0, v3, s[0:1] .LBB0_22: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9reductionPfS_S_i .amdhsa_group_segment_fixed_size 4224 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9reductionPfS_S_i, .Lfunc_end0-_Z9reductionPfS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1372 ; NumSgprs: 18 ; NumVgprs: 9 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 4224 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 9 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z16fixBetweenBlocksPfS_S_i ; -- Begin function _Z16fixBetweenBlocksPfS_S_i .globl _Z16fixBetweenBlocksPfS_S_i .p2align 8 .type _Z16fixBetweenBlocksPfS_S_i,@function _Z16fixBetweenBlocksPfS_S_i: ; @_Z16fixBetweenBlocksPfS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x18 s_load_b64 s[2:3], s[0:1], 0x10 v_mov_b32_e32 v0, 0 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s4, 2 global_store_b32 v0, v0, s[2:3] s_cbranch_scc1 .LBB1_3 ; %bb.1: ; %.lr.ph.preheader global_load_b32 v1, v0, s[2:3] s_load_b64 s[0:1], s[0:1], 0x8 s_add_i32 s4, s4, -1 s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 .LBB1_2: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_waitcnt lgkmcnt(0) global_load_b32 v2, v0, s[0:1] s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_add_i32 s4, s4, -1 s_waitcnt vmcnt(0) v_add_f32_e32 v1, v1, v2 global_store_b32 v0, v1, s[2:3] s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 s_cmp_lg_u32 s4, 0 s_cbranch_scc1 .LBB1_2 .LBB1_3: ; %._crit_edge s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z16fixBetweenBlocksPfS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 28 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 5 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z16fixBetweenBlocksPfS_S_i, .Lfunc_end1-_Z16fixBetweenBlocksPfS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 140 ; NumSgprs: 5 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 5 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z8postScanPfS_i ; -- Begin function _Z8postScanPfS_i .globl _Z8postScanPfS_i .p2align 8 .type _Z8postScanPfS_i,@function _Z8postScanPfS_i: ; @_Z8postScanPfS_i ; %bb.0: s_clause 0x1 s_load_b32 s5, s[0:1], 0x24 s_load_b64 s[2:3], s[0:1], 0x0 s_mov_b32 s4, s15 v_lshrrev_b32_e32 v4, 5, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_lshl_u32 v4, v4, v0, 2 s_waitcnt lgkmcnt(0) s_and_b32 s5, s5, 0xffff v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1] s_mov_b32 s5, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[2:3], 2, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_load_b32 v5, v[2:3], off s_waitcnt vmcnt(0) ds_store_b32 v4, v5 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB2_2 ; %bb.1: v_mov_b32_e32 v5, 0 ds_load_b32 v6, v5 offset:4216 ds_load_b32 v7, v5 offset:6328 s_waitcnt lgkmcnt(0) v_add_f32_e32 v6, v6, v7 ds_store_b32 v5, v6 offset:6328 .LBB2_2: s_or_b32 exec_lo, exec_lo, s5 v_add_nc_u32_e32 v5, 1, v0 s_mov_b32 s5, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 2, v0 s_cbranch_execz .LBB2_4 ; %bb.3: v_lshlrev_b32_e32 v6, 9, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, -1, v6 v_or_b32_e32 v6, 0xff, v6 v_lshrrev_b32_e32 v8, 5, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v9, 5, v6 v_add_lshl_u32 v7, v8, v7, 2 s_delay_alu instid0(VALU_DEP_2) v_add_lshl_u32 v6, v9, v6, 2 ds_load_b32 v7, v7 ds_load_b32 v8, v6 s_waitcnt lgkmcnt(0) v_add_f32_e32 v7, v7, v8 ds_store_b32 v6, v7 .LBB2_4: s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s5, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 4, v0 s_cbranch_execz .LBB2_6 ; %bb.5: v_lshlrev_b32_e32 v6, 8, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, -1, v6 v_or_b32_e32 v6, 0x7f, v6 v_lshrrev_b32_e32 v8, 5, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v9, 5, v6 v_add_lshl_u32 v7, v8, v7, 2 s_delay_alu instid0(VALU_DEP_2) v_add_lshl_u32 v6, v9, v6, 2 ds_load_b32 v7, v7 ds_load_b32 v8, v6 s_waitcnt lgkmcnt(0) v_add_f32_e32 v7, v7, v8 ds_store_b32 v6, v7 .LBB2_6: s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s5, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 8, v0 s_cbranch_execz .LBB2_8 ; %bb.7: v_lshlrev_b32_e32 v6, 7, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, -1, v6 v_or_b32_e32 v6, 63, v6 v_lshrrev_b32_e32 v8, 5, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v9, 5, v6 v_add_lshl_u32 v7, v8, v7, 2 s_delay_alu instid0(VALU_DEP_2) v_add_lshl_u32 v6, v9, v6, 2 ds_load_b32 v7, v7 ds_load_b32 v8, v6 s_waitcnt lgkmcnt(0) v_add_f32_e32 v7, v7, v8 ds_store_b32 v6, v7 .LBB2_8: s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s5, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 16, v0 s_cbranch_execz .LBB2_10 ; %bb.9: v_lshlrev_b32_e32 v6, 6, v5 v_lshlrev_b32_e32 v9, 1, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, -1, v6 v_add_lshl_u32 v6, v9, v6, 2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshrrev_b32_e32 v8, 5, v7 v_add_lshl_u32 v7, v8, v7, 2 ds_load_b32 v7, v7 ds_load_b32 v8, v6 offset:124 s_waitcnt lgkmcnt(0) v_add_f32_e32 v7, v7, v8 ds_store_b32 v6, v7 offset:124 .LBB2_10: s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s5, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 32, v0 s_cbranch_execz .LBB2_12 ; %bb.11: v_lshlrev_b32_e32 v6, 5, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, -1, v6 v_add_lshl_u32 v6, v5, v6, 2 v_lshrrev_b32_e32 v8, 5, v7 s_delay_alu instid0(VALU_DEP_1) v_add_lshl_u32 v7, v8, v7, 2 ds_load_b32 v7, v7 ds_load_b32 v8, v6 offset:60 s_waitcnt lgkmcnt(0) v_add_f32_e32 v7, v7, v8 ds_store_b32 v6, v7 offset:60 .LBB2_12: s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s5, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 64, v0 s_cbranch_execz .LBB2_14 ; %bb.13: v_lshlrev_b32_e32 v6, 4, v5 v_lshrrev_b32_e32 v9, 1, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, -1, v6 v_add_lshl_u32 v6, v9, v6, 2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshrrev_b32_e32 v8, 5, v7 v_add_lshl_u32 v7, v8, v7, 2 ds_load_b32 v7, v7 ds_load_b32 v8, v6 offset:28 s_waitcnt lgkmcnt(0) v_add_f32_e32 v7, v7, v8 ds_store_b32 v6, v7 offset:28 .LBB2_14: s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s5, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 0x80, v0 s_cbranch_execz .LBB2_16 ; %bb.15: v_lshlrev_b32_e32 v6, 3, v5 v_lshrrev_b32_e32 v9, 2, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, -1, v6 v_add_lshl_u32 v6, v9, v6, 2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshrrev_b32_e32 v8, 5, v7 v_add_lshl_u32 v7, v8, v7, 2 ds_load_b32 v7, v7 ds_load_b32 v8, v6 offset:12 s_waitcnt lgkmcnt(0) v_add_f32_e32 v7, v7, v8 ds_store_b32 v6, v7 offset:12 .LBB2_16: s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s5, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 0x100, v0 s_cbranch_execz .LBB2_18 ; %bb.17: v_lshlrev_b32_e32 v6, 2, v5 v_lshrrev_b32_e32 v9, 3, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v7, -1, v6 v_add_lshl_u32 v6, v9, v6, 2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshrrev_b32_e32 v8, 5, v7 v_add_lshl_u32 v7, v8, v7, 2 ds_load_b32 v7, v7 ds_load_b32 v8, v6 offset:4 s_waitcnt lgkmcnt(0) v_add_f32_e32 v7, v7, v8 ds_store_b32 v6, v7 offset:4 .LBB2_18: s_or_b32 exec_lo, exec_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s5, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e32 0x200, v0 s_cbranch_execz .LBB2_20 ; %bb.19: v_lshlrev_b32_e32 v0, 1, v5 v_lshrrev_b32_e32 v5, 4, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v6, -1, v0 v_add_lshl_u32 v0, v5, v0, 2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshrrev_b32_e32 v7, 5, v6 v_add_lshl_u32 v6, v7, v6, 2 ds_load_b32 v5, v6 ds_load_b32 v6, v0 s_waitcnt lgkmcnt(0) v_add_f32_e32 v5, v5, v6 ds_store_b32 v0, v5 .LBB2_20: s_or_b32 exec_lo, exec_lo, s5 s_clause 0x1 s_load_b64 s[6:7], s[0:1], 0x8 s_load_b32 s8, s[0:1], 0x10 s_mov_b32 s5, 0 s_waitcnt lgkmcnt(0) s_lshl_b64 s[0:1], s[4:5], 2 s_barrier buffer_gl0_inv ds_load_b32 v0, v4 s_add_u32 s0, s6, s0 s_addc_u32 s1, s7, s1 s_add_i32 s8, s8, -1 s_load_b32 s0, s[0:1], 0x0 s_waitcnt lgkmcnt(0) v_add_f32_e32 v0, s0, v0 s_mov_b32 s0, exec_lo ds_store_b32 v4, v0 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_i32_e64 s8, v1 s_cbranch_execz .LBB2_22 ; %bb.21: ds_load_b32 v0, v4 s_waitcnt lgkmcnt(0) global_store_b32 v[2:3], v0, off offset:4 .LBB2_22: s_or_b32 exec_lo, exec_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s0, exec_lo v_cmpx_eq_u32_e32 0, v1 s_cbranch_execz .LBB2_24 ; %bb.23: v_mov_b32_e32 v0, 0 global_store_b32 v0, v0, s[2:3] .LBB2_24: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z8postScanPfS_i .amdhsa_group_segment_fixed_size 4224 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z8postScanPfS_i, .Lfunc_end2-_Z8postScanPfS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1376 ; NumSgprs: 18 ; NumVgprs: 10 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 4224 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 10 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 4224 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9reductionPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z9reductionPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 28 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z16fixBetweenBlocksPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 5 .sgpr_spill_count: 0 .symbol: _Z16fixBetweenBlocksPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 4224 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z8postScanPfS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z8postScanPfS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "90df690bfb2d3a55886b1aa9fb7123429190df55.hip" .globl _Z24__device_stub__reductionPfS_S_i # -- Begin function _Z24__device_stub__reductionPfS_S_i .p2align 4, 0x90 .type _Z24__device_stub__reductionPfS_S_i,@function _Z24__device_stub__reductionPfS_S_i: # @_Z24__device_stub__reductionPfS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9reductionPfS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z24__device_stub__reductionPfS_S_i, .Lfunc_end0-_Z24__device_stub__reductionPfS_S_i .cfi_endproc # -- End function .globl _Z31__device_stub__fixBetweenBlocksPfS_S_i # -- Begin function _Z31__device_stub__fixBetweenBlocksPfS_S_i .p2align 4, 0x90 .type _Z31__device_stub__fixBetweenBlocksPfS_S_i,@function _Z31__device_stub__fixBetweenBlocksPfS_S_i: # @_Z31__device_stub__fixBetweenBlocksPfS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z16fixBetweenBlocksPfS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end1: .size _Z31__device_stub__fixBetweenBlocksPfS_S_i, .Lfunc_end1-_Z31__device_stub__fixBetweenBlocksPfS_S_i .cfi_endproc # -- End function .globl _Z23__device_stub__postScanPfS_i # -- Begin function _Z23__device_stub__postScanPfS_i .p2align 4, 0x90 .type _Z23__device_stub__postScanPfS_i,@function _Z23__device_stub__postScanPfS_i: # @_Z23__device_stub__postScanPfS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z8postScanPfS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end2: .size _Z23__device_stub__postScanPfS_i, .Lfunc_end2-_Z23__device_stub__postScanPfS_i .cfi_endproc # -- End function .globl _Z12prescanArrayPfS_S_S_i # -- Begin function _Z12prescanArrayPfS_S_S_i .p2align 4, 0x90 .type _Z12prescanArrayPfS_S_S_i,@function _Z12prescanArrayPfS_S_S_i: # @_Z12prescanArrayPfS_S_S_i .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $152, %rsp .cfi_def_cfa_offset 208 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %r8d, %ebx movq %rcx, 144(%rsp) # 8-byte Spill movq %rdx, 136(%rsp) # 8-byte Spill movq %rsi, %r15 movq %rdi, 88(%rsp) # 8-byte Spill movabsq $4294967297, %r14 # imm = 0x100000001 leal -1(%rbx), %eax leal 1022(%rbx), %ebp testl %eax, %eax cmovnsl %eax, %ebp sarl $10, %ebp incl %ebp leaq (%r14,%rbp), %r13 decq %r13 leaq 1023(%r14), %r12 movl $4096, %r8d # imm = 0x1000 movq %r13, %rdi movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_2 # %bb.1: movq 88(%rsp), %rax # 8-byte Reload movq %rax, 80(%rsp) movq %r15, 72(%rsp) movq 136(%rsp), %rax # 8-byte Reload movq %rax, 32(%rsp) movl %ebx, 12(%rsp) leaq 80(%rsp), %rax movq %rax, 96(%rsp) leaq 72(%rsp), %rax movq %rax, 104(%rsp) leaq 32(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z9reductionPfS_S_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_2: movq %r14, %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_4 # %bb.3: movq 88(%rsp), %rax # 8-byte Reload movq %rax, 80(%rsp) movq 136(%rsp), %rax # 8-byte Reload movq %rax, 72(%rsp) movq 144(%rsp), %rax # 8-byte Reload movq %rax, 32(%rsp) movl %ebp, 12(%rsp) leaq 80(%rsp), %rax movq %rax, 96(%rsp) leaq 72(%rsp), %rax movq %rax, 104(%rsp) leaq 32(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z16fixBetweenBlocksPfS_S_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_4: movl $4096, %r8d # imm = 0x1000 movq %r13, %rdi movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_6 # %bb.5: movq 88(%rsp), %rax # 8-byte Reload movq %rax, 80(%rsp) movq 144(%rsp), %rax # 8-byte Reload movq %rax, 72(%rsp) movl %ebx, 16(%rsp) leaq 80(%rsp), %rax movq %rax, 96(%rsp) leaq 72(%rsp), %rax movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z8postScanPfS_i, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_6: addq $152, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size _Z12prescanArrayPfS_S_S_i, .Lfunc_end3-_Z12prescanArrayPfS_S_S_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9reductionPfS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z16fixBetweenBlocksPfS_S_i, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z8postScanPfS_i, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z9reductionPfS_S_i,@object # @_Z9reductionPfS_S_i .section .rodata,"a",@progbits .globl _Z9reductionPfS_S_i .p2align 3, 0x0 _Z9reductionPfS_S_i: .quad _Z24__device_stub__reductionPfS_S_i .size _Z9reductionPfS_S_i, 8 .type _Z16fixBetweenBlocksPfS_S_i,@object # @_Z16fixBetweenBlocksPfS_S_i .globl _Z16fixBetweenBlocksPfS_S_i .p2align 3, 0x0 _Z16fixBetweenBlocksPfS_S_i: .quad _Z31__device_stub__fixBetweenBlocksPfS_S_i .size _Z16fixBetweenBlocksPfS_S_i, 8 .type _Z8postScanPfS_i,@object # @_Z8postScanPfS_i .globl _Z8postScanPfS_i .p2align 3, 0x0 _Z8postScanPfS_i: .quad _Z23__device_stub__postScanPfS_i .size _Z8postScanPfS_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z9reductionPfS_S_i" .size .L__unnamed_1, 20 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z16fixBetweenBlocksPfS_S_i" .size .L__unnamed_2, 28 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z8postScanPfS_i" .size .L__unnamed_3, 17 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__reductionPfS_S_i .addrsig_sym _Z31__device_stub__fixBetweenBlocksPfS_S_i .addrsig_sym _Z23__device_stub__postScanPfS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9reductionPfS_S_i .addrsig_sym _Z16fixBetweenBlocksPfS_S_i .addrsig_sym _Z8postScanPfS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z4calcPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R5, SR_CTAID.X ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R0, SR_TID.X ; IMAD R2, R5.reuse, c[0x0][0x0], R0 ; IADD3 R5, R5, R0, RZ ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; STG.E [R2.64], R5 ; EXIT ; BRA 0xa0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000141be_00000000-6_cfe6d9012104a4f1f51eaa6abc604b2884973169.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z23__device_stub__Z4calcPiPi .type _Z23__device_stub__Z4calcPiPi, @function _Z23__device_stub__Z4calcPiPi: .LFB3694: .cfi_startproc endbr64 subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 8(%rsp) movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 88(%rsp), %rax subq %fs:40, %rax jne .L8 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 120 pushq 24(%rsp) .cfi_def_cfa_offset 128 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z4calcPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 112 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z23__device_stub__Z4calcPiPi, .-_Z23__device_stub__Z4calcPiPi .globl _Z4calcPi .type _Z4calcPi, @function _Z4calcPi: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z23__device_stub__Z4calcPiPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z4calcPi, .-_Z4calcPi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string " " .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax leaq 8(%rsp), %rdi movl $64, %esi call cudaMalloc@PLT movl $8, 28(%rsp) movl $1, 32(%rsp) movl $2, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L19 .L12: call cudaDeviceSynchronize@PLT movl $64, %edi call malloc@PLT movq %rax, %r15 movl $2, %ecx movl $64, %edx movq 8(%rsp), %rsi movq %rax, %rdi call cudaMemcpy@PLT movq %r15, %rbx leaq 60(%r15), %r14 leaq 64(%r15), %r13 leaq _ZSt4cout(%rip), %r12 leaq .LC0(%rip), %rbp .L13: movl (%rbx), %esi movq %r12, %rdi call _ZNSolsEi@PLT movq %rax, %rdi movl $1, %edx movq %rbp, %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT addq $4, %rbx cmpq %r13, %rbx je .L16 cmpq %r14, %rbx jne .L13 movl 60(%r15), %esi leaq _ZSt4cout(%rip), %rdi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT .L16: movq %r15, %rdi call free@PLT leaq 8(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L20 movl $0, %eax addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state movq 8(%rsp), %rdi call _Z23__device_stub__Z4calcPiPi jmp .L12 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1 .LC1: .string "_Z4calcPi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z4calcPi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z4calcPi ; -- Begin function _Z4calcPi .globl _Z4calcPi .p2align 8 .type _Z4calcPi,@function _Z4calcPi: ; @_Z4calcPi ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x14 s_load_b64 s[0:1], s[0:1], 0x0 v_add_nc_u32_e32 v3, s15, v0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v0, vcc_lo, s0, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo global_store_b32 v[0:1], v3, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z4calcPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 264 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z4calcPi, .Lfunc_end0-_Z4calcPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 100 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: hidden_block_count_x - .offset: 12 .size: 4 .value_kind: hidden_block_count_y - .offset: 16 .size: 4 .value_kind: hidden_block_count_z - .offset: 20 .size: 2 .value_kind: hidden_group_size_x - .offset: 22 .size: 2 .value_kind: hidden_group_size_y - .offset: 24 .size: 2 .value_kind: hidden_group_size_z - .offset: 26 .size: 2 .value_kind: hidden_remainder_x - .offset: 28 .size: 2 .value_kind: hidden_remainder_y - .offset: 30 .size: 2 .value_kind: hidden_remainder_z - .offset: 48 .size: 8 .value_kind: hidden_global_offset_x - .offset: 56 .size: 8 .value_kind: hidden_global_offset_y - .offset: 64 .size: 8 .value_kind: hidden_global_offset_z - .offset: 72 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 264 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z4calcPi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z4calcPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "cfe6d9012104a4f1f51eaa6abc604b2884973169.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z19__device_stub__calcPi # -- Begin function _Z19__device_stub__calcPi .p2align 4, 0x90 .type _Z19__device_stub__calcPi,@function _Z19__device_stub__calcPi: # @_Z19__device_stub__calcPi .cfi_startproc # %bb.0: subq $72, %rsp .cfi_def_cfa_offset 80 movq %rdi, 64(%rsp) leaq 64(%rsp), %rax movq %rax, (%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d movq %rsp, %r9 movl $_Z4calcPi, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $88, %rsp .cfi_adjust_cfa_offset -88 retq .Lfunc_end0: .size _Z19__device_stub__calcPi, .Lfunc_end0-_Z19__device_stub__calcPi .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $88, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 8(%rsp), %rdi movl $64, %esi callq hipMalloc movabsq $4294967298, %rdi # imm = 0x100000002 leaq 6(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 80(%rsp), %rax movq %rax, 16(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 16(%rsp), %r9 movl $_Z4calcPi, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: callq hipDeviceSynchronize movl $64, %edi callq malloc movq %rax, %rbx movq 8(%rsp), %rsi movl $64, %edx movq %rax, %rdi movl $2, %ecx callq hipMemcpy movq $-16, %r15 jmp .LBB1_3 .p2align 4, 0x90 .LBB1_4: # in Loop: Header=BB1_3 Depth=1 movl 64(%rbx,%r15,4), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movl $.L.str, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l incq %r15 je .LBB1_11 .LBB1_3: # =>This Inner Loop Header: Depth=1 cmpq $-1, %r15 jne .LBB1_4 # %bb.5: # in Loop: Header=BB1_3 Depth=1 movl 60(%rbx), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %r14 testq %r14, %r14 je .LBB1_12 # %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i # in Loop: Header=BB1_3 Depth=1 cmpb $0, 56(%r14) je .LBB1_8 # %bb.7: # in Loop: Header=BB1_3 Depth=1 movzbl 67(%r14), %ecx jmp .LBB1_9 .LBB1_8: # in Loop: Header=BB1_3 Depth=1 movq %r14, %rdi movq %rax, %r12 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r12, %rax .LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit # in Loop: Header=BB1_3 Depth=1 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv incq %r15 jne .LBB1_3 .LBB1_11: movq %rbx, %rdi callq free leaq 8(%rsp), %rdi callq hipFree xorl %eax, %eax addq $88, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB1_12: .cfi_def_cfa_offset 128 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z4calcPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z4calcPi,@object # @_Z4calcPi .section .rodata,"a",@progbits .globl _Z4calcPi .p2align 3, 0x0 _Z4calcPi: .quad _Z19__device_stub__calcPi .size _Z4calcPi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz " " .size .L.str, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z4calcPi" .size .L__unnamed_1, 10 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z19__device_stub__calcPi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z4calcPi .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z3addPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R6, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R6, R6, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; @P0 EXIT ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; LDG.E R4, [R4.64] ; LDG.E R3, [R2.64] ; IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; IADD3 R9, R4, R3, RZ ; STG.E [R6.64], R9 ; EXIT ; BRA 0x100; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000ba75e_00000000-6_04e0a69437e1d8a60010ac003f8aac55d3002af3.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2067: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2067: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z8new_nodei .type _Z8new_nodei, @function _Z8new_nodei: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movl %edi, %ebx movl $16, %edi call malloc@PLT movl %ebx, (%rax) movq $0, 8(%rax) popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z8new_nodei, .-_Z8new_nodei .globl _Z9new_graphi .type _Z9new_graphi, @function _Z9new_graphi: .LFB2058: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movl %edi, %ebp movl $16, %edi call malloc@PLT movq %rax, %rbx movl %ebp, (%rax) movslq %ebp, %r12 salq $3, %r12 movq %r12, %rdi call malloc@PLT movq %rax, 8(%rbx) testl %ebp, %ebp jle .L5 movq %rax, %rdx addq %r12, %rax .L7: movq $0, (%rdx) addq $8, %rdx cmpq %rax, %rdx jne .L7 .L5: movq %rbx, %rax popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z9new_graphi, .-_Z9new_graphi .globl _Z7addEdgeP5graphii .type _Z7addEdgeP5graphii, @function _Z7addEdgeP5graphii: .LFB2059: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbp movl %esi, %r12d movl %edx, %ebx movl %edx, %edi call _Z8new_nodei movslq %r12d, %rdx movq 8(%rbp), %rcx movq (%rcx,%rdx,8), %rcx movq %rcx, 8(%rax) movq 8(%rbp), %rcx movq %rax, (%rcx,%rdx,8) movl %r12d, %edi call _Z8new_nodei movslq %ebx, %rbx movq 8(%rbp), %rdx movq (%rdx,%rbx,8), %rdx movq %rdx, 8(%rax) movq 8(%rbp), %rdx movq %rax, (%rdx,%rbx,8) popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2059: .size _Z7addEdgeP5graphii, .-_Z7addEdgeP5graphii .globl _Z8get_vertPc .type _Z8get_vertPc, @function _Z8get_vertPc: .LFB2060: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax movzbl (%rdi), %eax cmpb $10, %al je .L20 addq $1, %rdi movl $0, %ecx movl $0, %edx jmp .L17 .L25: addl $1, %edx cmpl $2, %edx je .L18 jle .L16 .L13: movslq %ecx, %rcx movb $0, (%rsp,%rcx) movq %rsp, %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT cltq movq 24(%rsp), %rdx subq %fs:40, %rdx jne .L24 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L18: .cfi_restore_state movslq %ecx, %rdx movb %al, (%rsp,%rdx) addl $1, %ecx movl $2, %edx .L16: addq $1, %rdi movzbl -1(%rdi), %eax cmpb $10, %al je .L13 .L17: cmpb $32, %al je .L25 cmpl $2, %edx jne .L16 jmp .L18 .L20: movl $0, %ecx jmp .L13 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE2060: .size _Z8get_vertPc, .-_Z8get_vertPc .globl _Z7get_srcPc .type _Z7get_srcPc, @function _Z7get_srcPc: .LFB2061: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax movzbl (%rdi), %eax cmpb $10, %al je .L31 movl $1, %edx leaq -1(%rsp), %rsi jmp .L29 .L31: movl $0, %edx jmp .L27 .L28: movb %al, (%rsi,%rdx) leaq 1(%rdx), %rcx movzbl -1(%rdi,%rcx), %eax cmpb $10, %al je .L27 movq %rcx, %rdx .L29: cmpb $32, %al jne .L28 subl $1, %edx .L27: movslq %edx, %rdx movb $0, (%rsp,%rdx) movq %rsp, %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq 24(%rsp), %rdx subq %fs:40, %rdx jne .L35 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L35: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2061: .size _Z7get_srcPc, .-_Z7get_srcPc .globl _Z7get_dstPc .type _Z7get_dstPc, @function _Z7get_dstPc: .LFB2062: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax movzbl (%rdi), %eax cmpb $10, %al je .L44 addq $1, %rdi movl $0, %ecx movl $0, %edx jmp .L41 .L49: addl $1, %edx cmpl $1, %edx je .L42 jle .L40 .L37: movslq %ecx, %rcx movb $0, (%rsp,%rcx) movq %rsp, %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq 24(%rsp), %rdx subq %fs:40, %rdx jne .L48 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L42: .cfi_restore_state movslq %ecx, %rdx movb %al, (%rsp,%rdx) addl $1, %ecx movl $1, %edx .L40: addq $1, %rdi movzbl -1(%rdi), %eax cmpb $10, %al je .L37 .L41: cmpb $32, %al je .L49 cmpl $1, %edx jne .L40 jmp .L42 .L44: movl $0, %ecx jmp .L37 .L48: call __stack_chk_fail@PLT .cfi_endproc .LFE2062: .size _Z7get_dstPc, .-_Z7get_dstPc .globl _Z7comparePKvS0_ .type _Z7comparePKvS0_, @function _Z7comparePKvS0_: .LFB2063: .cfi_startproc endbr64 movl (%rsi), %eax subl (%rdi), %eax ret .cfi_endproc .LFE2063: .size _Z7comparePKvS0_, .-_Z7comparePKvS0_ .globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i .type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function _Z27__device_stub__Z3addPiS_S_iPiS_S_i: .LFB2089: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L55 .L51: movq 136(%rsp), %rax subq %fs:40, %rax jne .L56 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L55: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z3addPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L51 .L56: call __stack_chk_fail@PLT .cfi_endproc .LFE2089: .size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i .globl _Z3addPiS_S_i .type _Z3addPiS_S_i, @function _Z3addPiS_S_i: .LFB2090: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z3addPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2090: .size _Z3addPiS_S_i, .-_Z3addPiS_S_i .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "Usage: %s vector_size block_size\n" .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Initializing input arrays.\n" .LC2: .string "Running sequential job.\n" .section .rodata.str1.8 .align 8 .LC3: .string "\tSequential Job Time: %.2f ms\n" .section .rodata.str1.1 .LC4: .string "Running parallel job.\n" .LC5: .string "\tParallel Job Time: %.2f ms\n" .section .rodata.str1.8 .align 8 .LC6: .string "Error starting element %d, %d != %d\n" .align 8 .LC7: .string "Correct result. No errors were found.\n" .text .globl main .type main, @function main: .LFB2064: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $104, %rsp .cfi_def_cfa_offset 160 movq %rsi, %rbx movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax cmpl $3, %edi je .L60 movq (%rsi), %rdx leaq .LC0(%rip), %rsi movl $2, %edi call __printf_chk@PLT movl $1, %eax .L59: movq 88(%rsp), %rdx subq %fs:40, %rdx jne .L80 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L60: .cfi_restore_state movq 8(%rsi), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %r15 movq %rax, (%rsp) movq 16(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl $0, %edi call cudaSetDevice@PLT leaq 24(%rsp), %rdi call cudaEventCreate@PLT leaq 32(%rsp), %rdi call cudaEventCreate@PLT movslq %r15d, %rax movq %rax, %rsi movq %rax, 8(%rsp) movabsq $2305843009213693950, %rax cmpq %rsi, %rax jb .L62 leaq 0(,%rsi,4), %rbx movq %rbx, %rdi call _Znam@PLT movq %rax, %r12 movq %rbx, %rdi call _Znam@PLT movq %rax, %r13 movq %rbx, %rdi call _Znam@PLT movq %rax, %rbp movq %rbx, %rdi call _Znam@PLT movq %rax, %r14 leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT testl %r15d, %r15d jle .L81 movq (%rsp), %rax leal -1(%rax), %r15d movl $0, %ebx .L66: call rand@PLT movslq %eax, %rdx imulq $1717986919, %rdx, %rdx sarq $34, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx leal (%rdx,%rdx,4), %edx addl %edx, %edx subl %edx, %eax movl %eax, (%r12,%rbx,4) call rand@PLT movslq %eax, %rdx imulq $1717986919, %rdx, %rdx sarq $34, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx leal (%rdx,%rdx,4), %edx addl %edx, %edx subl %edx, %eax movl %eax, 0(%r13,%rbx,4) movq %rbx, %rax addq $1, %rbx cmpq %r15, %rax jne .L66 leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %esi movq 24(%rsp), %rdi call cudaEventRecord@PLT movl $0, %eax .L67: movl 0(%r13,%rax,4), %edx addl (%r12,%rax,4), %edx movl %edx, 0(%rbp,%rax,4) movq %rax, %rdx addq $1, %rax cmpq %r15, %rdx jne .L67 .L73: movl $0, %esi movq 32(%rsp), %rdi call cudaEventRecord@PLT movq 32(%rsp), %rdi call cudaEventSynchronize@PLT leaq 20(%rsp), %rdi movq 32(%rsp), %rdx movq 24(%rsp), %rsi call cudaEventElapsedTime@PLT pxor %xmm0, %xmm0 cvtss2sd 20(%rsp), %xmm0 leaq .LC3(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl 8(%rsp), %r15d sall $2, %r15d movslq %r15d, %rbx leaq 40(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 48(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 56(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movl $1, %ecx movq %rbx, %rdx movq %r12, %rsi movq 40(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq %r13, %rsi movq 48(%rsp), %rdi call cudaMemcpy@PLT leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %esi movq 24(%rsp), %rdi call cudaEventRecord@PLT movl $1, 76(%rsp) movl $1, 80(%rsp) movl (%rsp), %eax movl %eax, 64(%rsp) movl $1, 68(%rsp) movl $0, %r9d movl $0, %r8d movq 76(%rsp), %rdx movl $1, %ecx movq 64(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L82 .L68: movl $0, %esi movq 32(%rsp), %rdi call cudaEventRecord@PLT movq 32(%rsp), %rdi call cudaEventSynchronize@PLT leaq 20(%rsp), %rdi movq 32(%rsp), %rdx movq 24(%rsp), %rsi call cudaEventElapsedTime@PLT pxor %xmm0, %xmm0 cvtss2sd 20(%rsp), %xmm0 leaq .LC5(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl $2, %ecx movq %rbx, %rdx movq 56(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT movq (%rsp), %rax testl %eax, %eax jle .L69 movl %eax, %eax movl $0, %edx .L72: movl 0(%rbp,%rdx,4), %r8d movl (%r14,%rdx,4), %ecx cmpl %ecx, %r8d jne .L83 addq $1, %rdx cmpq %rax, %rdx jne .L72 .L69: leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L71 .L62: movq 88(%rsp), %rax subq %fs:40, %rax je .L65 call __stack_chk_fail@PLT .L65: call __cxa_throw_bad_array_new_length@PLT .L82: movl %r15d, %ecx movq 56(%rsp), %rdx movq 48(%rsp), %rsi movq 40(%rsp), %rdi call _Z27__device_stub__Z3addPiS_S_iPiS_S_i jmp .L68 .L83: leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L71: movq %r12, %rdi call free@PLT movq %r13, %rdi call free@PLT movq %rbp, %rdi call free@PLT movq %r14, %rdi call free@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq 48(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rdi call cudaFree@PLT movl $0, %eax jmp .L59 .L81: leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %esi movq 24(%rsp), %rdi call cudaEventRecord@PLT jmp .L73 .L80: call __stack_chk_fail@PLT .cfi_endproc .LFE2064: .size main, .-main .section .rodata.str1.1 .LC8: .string "_Z3addPiS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2092: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC8(%rip), %rdx movq %rdx, %rcx leaq _Z3addPiS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2092: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z3addPiS_S_i ; -- Begin function _Z3addPiS_S_i .globl _Z3addPiS_S_i .p2align 8 .type _Z3addPiS_S_i,@function _Z3addPiS_S_i: ; @_Z3addPiS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_add_nc_u32_e32 v2, v3, v2 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z3addPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 180 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z3addPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z3addPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "04e0a69437e1d8a60010ac003f8aac55d3002af3.hip" .globl _Z8new_nodei # -- Begin function _Z8new_nodei .p2align 4, 0x90 .type _Z8new_nodei,@function _Z8new_nodei: # @_Z8new_nodei .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movl %edi, %ebx movl $16, %edi callq malloc movl %ebx, (%rax) movq $0, 8(%rax) popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z8new_nodei, .Lfunc_end0-_Z8new_nodei .cfi_endproc # -- End function .globl _Z9new_graphi # -- Begin function _Z9new_graphi .p2align 4, 0x90 .type _Z9new_graphi,@function _Z9new_graphi: # @_Z9new_graphi .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movl %edi, %ebp movl $16, %edi callq malloc movq %rax, %rbx movl %ebp, (%rax) movslq %ebp, %r14 leaq (,%r14,8), %rdi callq malloc movq %rax, 8(%rbx) testl %r14d, %r14d jle .LBB1_2 # %bb.1: # %.lr.ph.preheader movl %ebp, %edx shlq $3, %rdx movq %rax, %rdi xorl %esi, %esi callq memset@PLT .LBB1_2: # %._crit_edge movq %rbx, %rax popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z9new_graphi, .Lfunc_end1-_Z9new_graphi .cfi_endproc # -- End function .globl _Z7addEdgeP5graphii # -- Begin function _Z7addEdgeP5graphii .p2align 4, 0x90 .type _Z7addEdgeP5graphii,@function _Z7addEdgeP5graphii: # @_Z7addEdgeP5graphii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 pushq %rax .cfi_def_cfa_offset 48 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %edx, %ebx movl %esi, %ebp movq %rdi, %r14 movl $16, %edi callq malloc movl %ebx, (%rax) movq $0, 8(%rax) movq 8(%r14), %r14 movslq %ebp, %r15 movq (%r14,%r15,8), %rcx movq %rcx, 8(%rax) movq %rax, (%r14,%r15,8) movl $16, %edi callq malloc movl %r15d, (%rax) movq $0, 8(%rax) movslq %ebx, %rcx movq (%r14,%rcx,8), %rdx movq %rdx, 8(%rax) movq %rax, (%r14,%rcx,8) addq $8, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z7addEdgeP5graphii, .Lfunc_end2-_Z7addEdgeP5graphii .cfi_endproc # -- End function .globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i .p2align 4, 0x90 .type _Z18__device_stub__addPiS_S_i,@function _Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3addPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end3: .size _Z18__device_stub__addPiS_S_i, .Lfunc_end3-_Z18__device_stub__addPiS_S_i .cfi_endproc # -- End function .globl _Z8get_vertPc # -- Begin function _Z8get_vertPc .p2align 4, 0x90 .type _Z8get_vertPc,@function _Z8get_vertPc: # @_Z8get_vertPc .cfi_startproc # %bb.0: subq $24, %rsp .cfi_def_cfa_offset 32 xorl %eax, %eax xorl %ecx, %ecx jmp .LBB4_1 .p2align 4, 0x90 .LBB4_6: # in Loop: Header=BB4_1 Depth=1 movslq %ecx, %rsi movb %dl, (%rsp,%rsi) incl %ecx incq %rdi .LBB4_1: # =>This Inner Loop Header: Depth=1 movzbl (%rdi), %edx cmpl $32, %edx je .LBB4_4 # %bb.2: # in Loop: Header=BB4_1 Depth=1 cmpl $10, %edx je .LBB4_3 # %bb.5: # in Loop: Header=BB4_1 Depth=1 cmpl $2, %eax je .LBB4_6 jmp .LBB4_7 .p2align 4, 0x90 .LBB4_4: # in Loop: Header=BB4_1 Depth=1 incl %eax cmpl $2, %eax je .LBB4_6 .LBB4_7: # in Loop: Header=BB4_1 Depth=1 jg .LBB4_3 # %bb.8: # in Loop: Header=BB4_1 Depth=1 incq %rdi jmp .LBB4_1 .LBB4_3: movslq %ecx, %rax movb $0, (%rsp,%rax) movq %rsp, %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol cltq addq $24, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end4: .size _Z8get_vertPc, .Lfunc_end4-_Z8get_vertPc .cfi_endproc # -- End function .globl _Z7get_srcPc # -- Begin function _Z7get_srcPc .p2align 4, 0x90 .type _Z7get_srcPc,@function _Z7get_srcPc: # @_Z7get_srcPc .cfi_startproc # %bb.0: subq $24, %rsp .cfi_def_cfa_offset 32 xorl %eax, %eax .p2align 4, 0x90 .LBB5_1: # =>This Inner Loop Header: Depth=1 movzbl (%rdi,%rax), %ecx cmpl $10, %ecx je .LBB5_4 # %bb.2: # in Loop: Header=BB5_1 Depth=1 cmpl $32, %ecx je .LBB5_4 # %bb.3: # in Loop: Header=BB5_1 Depth=1 movb %cl, (%rsp,%rax) incq %rax jmp .LBB5_1 .LBB5_4: movl %eax, %eax movb $0, (%rsp,%rax) movq %rsp, %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol # kill: def $eax killed $eax killed $rax addq $24, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end5: .size _Z7get_srcPc, .Lfunc_end5-_Z7get_srcPc .cfi_endproc # -- End function .globl _Z7get_dstPc # -- Begin function _Z7get_dstPc .p2align 4, 0x90 .type _Z7get_dstPc,@function _Z7get_dstPc: # @_Z7get_dstPc .cfi_startproc # %bb.0: subq $24, %rsp .cfi_def_cfa_offset 32 xorl %eax, %eax xorl %ecx, %ecx jmp .LBB6_1 .p2align 4, 0x90 .LBB6_6: # in Loop: Header=BB6_1 Depth=1 movslq %ecx, %rsi movb %dl, (%rsp,%rsi) incl %ecx incq %rdi .LBB6_1: # =>This Inner Loop Header: Depth=1 movzbl (%rdi), %edx cmpl $32, %edx je .LBB6_4 # %bb.2: # in Loop: Header=BB6_1 Depth=1 cmpl $10, %edx je .LBB6_3 # %bb.5: # in Loop: Header=BB6_1 Depth=1 cmpl $1, %eax je .LBB6_6 jmp .LBB6_7 .p2align 4, 0x90 .LBB6_4: # in Loop: Header=BB6_1 Depth=1 incl %eax cmpl $1, %eax je .LBB6_6 .LBB6_7: # in Loop: Header=BB6_1 Depth=1 jg .LBB6_3 # %bb.8: # in Loop: Header=BB6_1 Depth=1 incq %rdi jmp .LBB6_1 .LBB6_3: movslq %ecx, %rax movb $0, (%rsp,%rax) movq %rsp, %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol # kill: def $eax killed $eax killed $rax addq $24, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end6: .size _Z7get_dstPc, .Lfunc_end6-_Z7get_dstPc .cfi_endproc # -- End function .globl _Z7comparePKvS0_ # -- Begin function _Z7comparePKvS0_ .p2align 4, 0x90 .type _Z7comparePKvS0_,@function _Z7comparePKvS0_: # @_Z7comparePKvS0_ .cfi_startproc # %bb.0: movl (%rsi), %eax subl (%rdi), %eax retq .Lfunc_end7: .size _Z7comparePKvS0_, .Lfunc_end7-_Z7comparePKvS0_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $184, %rsp .cfi_def_cfa_offset 240 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 cmpl $3, %edi jne .LBB8_1 # %bb.2: movq 8(%rsi), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %rbx xorl %edi, %edi callq hipSetDevice leaq 24(%rsp), %rdi callq hipEventCreate leaq 16(%rsp), %rdi callq hipEventCreate movq %rbx, 64(%rsp) # 8-byte Spill movslq %ebx, %r13 leaq (,%r13,4), %rax testl %r13d, %r13d movq $-1, %r12 cmovnsq %rax, %r12 movq %r12, %rdi callq _Znam movq %rax, %rbx movq %r12, %rdi callq _Znam movq %rax, %r14 movq %r12, %rdi callq _Znam movq %rax, %r15 movq %r12, %rdi callq _Znam movq %rax, %r12 movl $.Lstr, %edi callq puts@PLT testl %r13d, %r13d jle .LBB8_5 # %bb.3: # %.lr.ph.preheader movl 64(%rsp), %r13d # 4-byte Reload xorl %ebp, %ebp .p2align 4, 0x90 .LBB8_4: # %.lr.ph # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx subl %ecx, %eax movl %eax, (%rbx,%rbp,4) callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx subl %ecx, %eax movl %eax, (%r14,%rbp,4) incq %rbp cmpq %rbp, %r13 jne .LBB8_4 .LBB8_5: # %._crit_edge movl $.Lstr.1, %edi callq puts@PLT movq 24(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 64(%rsp), %r13 # 8-byte Reload testl %r13d, %r13d jle .LBB8_8 # %bb.6: # %.lr.ph82.preheader movl %r13d, %eax xorl %ecx, %ecx .p2align 4, 0x90 .LBB8_7: # %.lr.ph82 # =>This Inner Loop Header: Depth=1 movl (%r14,%rcx,4), %edx addl (%rbx,%rcx,4), %edx movl %edx, (%r15,%rcx,4) incq %rcx cmpq %rcx, %rax jne .LBB8_7 .LBB8_8: # %._crit_edge83 movq 16(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 16(%rsp), %rdi callq hipEventSynchronize movq 24(%rsp), %rsi movq 16(%rsp), %rdx leaq 12(%rsp), %rdi callq hipEventElapsedTime movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.3, %edi movb $1, %al callq printf leal (,%r13,4), %eax movl %eax, 56(%rsp) # 4-byte Spill movslq %eax, %rbp leaq 48(%rsp), %rdi movq %rbp, %rsi callq hipMalloc leaq 40(%rsp), %rdi movq %rbp, %rsi callq hipMalloc leaq 32(%rsp), %rdi movq %rbp, %rsi callq hipMalloc movq 48(%rsp), %rdi movq %rbx, %rsi movq %rbp, %rdx movl $1, %ecx callq hipMemcpy movq 40(%rsp), %rdi movq %r14, %rsi movq %rbp, %rdx movl $1, %ecx callq hipMemcpy movl $.Lstr.2, %edi callq puts@PLT movq 24(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movl %r13d, %edi movabsq $4294967296, %rdx # imm = 0x100000000 orq %rdx, %rdi orq $1, %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB8_10 # %bb.9: movq 48(%rsp), %rax movq 40(%rsp), %rcx movq 32(%rsp), %rdx movq %rax, 136(%rsp) movq %rcx, 128(%rsp) movq %rdx, 120(%rsp) movl 56(%rsp), %eax # 4-byte Reload movl %eax, 60(%rsp) leaq 136(%rsp), %rax movq %rax, 144(%rsp) leaq 128(%rsp), %rax movq %rax, 152(%rsp) leaq 120(%rsp), %rax movq %rax, 160(%rsp) leaq 60(%rsp), %rax movq %rax, 168(%rsp) leaq 104(%rsp), %rdi leaq 88(%rsp), %rsi leaq 80(%rsp), %rdx leaq 72(%rsp), %rcx callq __hipPopCallConfiguration movq 104(%rsp), %rsi movl 112(%rsp), %edx movq 88(%rsp), %rcx movl 96(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z3addPiS_S_i, %edi pushq 72(%rsp) .cfi_adjust_cfa_offset 8 pushq 88(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB8_10: movq 16(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 16(%rsp), %rdi callq hipEventSynchronize movq 24(%rsp), %rsi movq 16(%rsp), %rdx leaq 12(%rsp), %rdi callq hipEventElapsedTime movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.5, %edi movb $1, %al callq printf movq 32(%rsp), %rsi movq %r12, %rdi movq %rbp, %rdx movl $2, %ecx callq hipMemcpy testl %r13d, %r13d jle .LBB8_15 # %bb.11: # %.lr.ph87.preheader movl %r13d, %eax xorl %esi, %esi .p2align 4, 0x90 .LBB8_12: # %.lr.ph87 # =>This Inner Loop Header: Depth=1 movl (%r15,%rsi,4), %ecx movl (%r12,%rsi,4), %edx cmpl %edx, %ecx jne .LBB8_13 # %bb.14: # %.critedge # in Loop: Header=BB8_12 Depth=1 incq %rsi cmpq %rsi, %rax jne .LBB8_12 .LBB8_15: # %.critedge73 movl $.Lstr.3, %edi callq puts@PLT jmp .LBB8_16 .LBB8_1: movq (%rsi), %rsi movl $.L.str, %edi xorl %eax, %eax callq printf movl $1, %eax jmp .LBB8_17 .LBB8_13: movl $.L.str.6, %edi # kill: def $esi killed $esi killed $rsi xorl %eax, %eax callq printf .LBB8_16: movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free movq %r12, %rdi callq free movq 48(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree xorl %eax, %eax .LBB8_17: addq $184, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end8: .size main, .Lfunc_end8-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB9_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB9_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3addPiS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end9: .size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB10_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB10_2: retq .Lfunc_end10: .size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor .cfi_endproc # -- End function .type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i .section .rodata,"a",@progbits .globl _Z3addPiS_S_i .p2align 3, 0x0 _Z3addPiS_S_i: .quad _Z18__device_stub__addPiS_S_i .size _Z3addPiS_S_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Usage: %s vector_size block_size\n" .size .L.str, 34 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "\tSequential Job Time: %.2f ms\n" .size .L.str.3, 31 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "\tParallel Job Time: %.2f ms\n" .size .L.str.5, 29 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Error starting element %d, %d != %d\n" .size .L.str.6, 37 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z3addPiS_S_i" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Initializing input arrays." .size .Lstr, 27 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "Running sequential job." .size .Lstr.1, 24 .type .Lstr.2,@object # @str.2 .Lstr.2: .asciz "Running parallel job." .size .Lstr.2, 22 .type .Lstr.3,@object # @str.3 .Lstr.3: .asciz "Correct result. No errors were found." .size .Lstr.3, 38 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__addPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3addPiS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
539
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8,372
158
code for sm_80
.file "tmpxft_0004ca57_00000000-6_7d4c6adc2754598db52fac9a6da677e428325d4c.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "7d4c6adc2754598db52fac9a6da677e428325d4c.hip" .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z9incrementPddj .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; @P0 EXIT ; HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; LDG.E.64 R4, [R2.64] ; DADD R4, R4, c[0x0][0x168] ; STG.E.64 [R2.64], R4 ; EXIT ; BRA 0xd0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000b6bfa_00000000-6_fda2529b3718e534061038b1bbfff5b187818d6c.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z30__device_stub__Z9incrementPddjPddj .type _Z30__device_stub__Z9incrementPddjPddj, @function _Z30__device_stub__Z9incrementPddjPddj: .LFB3694: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movsd %xmm0, 16(%rsp) movl %esi, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z9incrementPddj(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z30__device_stub__Z9incrementPddjPddj, .-_Z30__device_stub__Z9incrementPddjPddj .globl _Z9incrementPddj .type _Z9incrementPddj, @function _Z9incrementPddj: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z9incrementPddjPddj addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z9incrementPddj, .-_Z9incrementPddj .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Passed" .LC2: .string "Failed" .LC5: .string "Test: " .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 subq $72, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leaq 24(%rsp), %rdi movl $1, %edx movl $8000, %esi call cudaMallocManaged@PLT movl $0, %eax .L12: pxor %xmm0, %xmm0 cvtsi2sdl %eax, %xmm0 movq 24(%rsp), %rdx movsd %xmm0, (%rdx,%rax,8) addq $1, %rax cmpq $1000, %rax jne .L12 movl $512, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $2, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L23 .L13: call cudaDeviceSynchronize@PLT movq 24(%rsp), %rdx movl $0, %eax movq $0x000000000, 8(%rsp) movsd .LC3(%rip), %xmm3 movq .LC4(%rip), %xmm2 .L14: pxor %xmm1, %xmm1 cvtsi2sdl %eax, %xmm1 addsd %xmm3, %xmm1 movsd (%rdx,%rax,8), %xmm0 subsd %xmm1, %xmm0 andpd %xmm2, %xmm0 addsd 8(%rsp), %xmm0 movsd %xmm0, 8(%rsp) addq $1, %rax cmpq $1000, %rax jne .L14 leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movsd .LC6(%rip), %xmm0 comisd 8(%rsp), %xmm0 leaq .LC1(%rip), %rsi leaq .LC2(%rip), %rax cmovbe %rax, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L24 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state movl $1000, %esi movsd .LC3(%rip), %xmm0 movq 24(%rsp), %rdi call _Z30__device_stub__Z9incrementPddjPddj jmp .L13 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z9incrementPddj" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _Z9incrementPddj(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC3: .long 0 .long 1073741824 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC4: .long -1 .long 2147483647 .long 0 .long 0 .section .rodata.cst8 .align 8 .LC6: .long -400107883 .long 1041313291 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9incrementPddj ; -- Begin function _Z9incrementPddj .globl _Z9incrementPddj .p2align 8 .type _Z9incrementPddj,@function _Z9incrementPddj: ; @_Z9incrementPddj ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b32 s3, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_u32_e64 s3, v1 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b128 s[0:3], s[0:1], 0x0 v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b64 v[2:3], v[0:1], off s_waitcnt vmcnt(0) v_add_f64 v[2:3], v[2:3], s[2:3] global_store_b64 v[0:1], v[2:3], off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9incrementPddj .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9incrementPddj, .Lfunc_end0-_Z9incrementPddj ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 144 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 8 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9incrementPddj .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z9incrementPddj.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "fda2529b3718e534061038b1bbfff5b187818d6c.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z24__device_stub__incrementPddj # -- Begin function _Z24__device_stub__incrementPddj .p2align 4, 0x90 .type _Z24__device_stub__incrementPddj,@function _Z24__device_stub__incrementPddj: # @_Z24__device_stub__incrementPddj .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movsd %xmm0, 64(%rsp) movl %esi, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9incrementPddj, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z24__device_stub__incrementPddj, .Lfunc_end0-_Z24__device_stub__incrementPddj .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI1_0: .quad 0x7fffffffffffffff # double NaN .quad 0x7fffffffffffffff # double NaN .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI1_1: .quad 0x3e112e0be826d695 # double 1.0000000000000001E-9 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $128, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -16 leaq 8(%rsp), %rdi movl $8000, %esi # imm = 0x1F40 movl $1, %edx callq hipMallocManaged xorl %eax, %eax movq 8(%rsp), %rcx .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtsi2sd %eax, %xmm0 movsd %xmm0, (%rcx,%rax,8) incq %rax cmpq $1000, %rax # imm = 0x3E8 jne .LBB1_1 # %bb.2: movabsq $4294967298, %rdi # imm = 0x100000002 leaq 510(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 8(%rsp), %rax movq %rax, 88(%rsp) movabsq $4611686018427387904, %rax # imm = 0x4000000000000000 movq %rax, 80(%rsp) movl $1000, 20(%rsp) # imm = 0x3E8 leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 20(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z9incrementPddj, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: callq hipDeviceSynchronize xorpd %xmm3, %xmm3 xorl %eax, %eax movq 8(%rsp), %rcx movapd .LCPI1_0(%rip), %xmm0 # xmm0 = [NaN,NaN] .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 movsd (%rcx,%rax,8), %xmm1 # xmm1 = mem[0],zero leal 2(%rax), %edx xorps %xmm2, %xmm2 cvtsi2sd %edx, %xmm2 subsd %xmm2, %xmm1 andpd %xmm0, %xmm1 addsd %xmm1, %xmm3 incq %rax cmpq $1000, %rax # imm = 0x3E8 jne .LBB1_5 # %bb.6: movl $_ZSt4cout, %edi movl $.L.str, %esi movl $6, %edx movsd %xmm3, 24(%rsp) # 8-byte Spill callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero ucomisd 24(%rsp), %xmm0 # 8-byte Folded Reload movl $.L.str.1, %eax movl $.L.str.2, %esi cmovaq %rax, %rsi movl $_ZSt4cout, %edi movl $6, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB1_11 # %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB1_9 # %bb.8: movzbl 67(%rbx), %eax jmp .LBB1_10 .LBB1_9: movq %rbx, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) .LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax addq $128, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .LBB1_11: .cfi_def_cfa_offset 144 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9incrementPddj, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z9incrementPddj,@object # @_Z9incrementPddj .section .rodata,"a",@progbits .globl _Z9incrementPddj .p2align 3, 0x0 _Z9incrementPddj: .quad _Z24__device_stub__incrementPddj .size _Z9incrementPddj, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Test: " .size .L.str, 7 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Passed" .size .L.str.1, 7 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed" .size .L.str.2, 7 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9incrementPddj" .size .L__unnamed_1, 17 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__incrementPddj .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9incrementPddj .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
433
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code for sm_80 Function : _Z8sayHellov .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; MOV R2, 0x0 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; IADD3 R1, R1, -0x8, RZ ; S2R R3, SR_TID.X ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; IADD3 R6, P0, R1, c[0x0][0x20], RZ ; IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; IMAD R0, R0, c[0x0][0x0], R3 ; LDC.64 R2, c[0x4][R2] ; STL [R1], R0 ; LEPC R8 ; MOV R11, 0x140 ; MOV R20, 0xc0 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R11, R8 ; IADD3.X R21, ~R0, R21, R9, P0, P1 ; CALL.ABS.NOINC R2 ; EXIT ; BRA 0x150; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0009a189_00000000-6_e813c08b4cb1d77e65f076469758fdaa895b7c04.cudafe1.cpp" .text #APP #NO_APP .type _ZL8sayHellov, @function _ZL8sayHellov: .LFB2083: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L5 .L1: movq 72(%rsp), %rax subq %fs:40, %rax jne .L6 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L5: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _ZL8sayHellov(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L1 .L6: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _ZL8sayHellov, .-_ZL8sayHellov .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Please enter the grid size: " .LC1: .string "%d" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC2: .string "\nPlease enter the threads per block: " .section .rodata.str1.1 .LC3: .string "\n" .LC4: .string "cudaDeviceReset failed!" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 subq $48, %rsp .cfi_def_cfa_offset 64 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax leaq .LC0(%rip), %rdi call puts@PLT leaq 8(%rsp), %rsi leaq .LC1(%rip), %rbx movq %rbx, %rdi movl $0, %eax call __isoc23_scanf@PLT leaq .LC2(%rip), %rdi call puts@PLT leaq 12(%rsp), %rsi movq %rbx, %rdi movl $0, %eax call __isoc23_scanf@PLT leaq .LC3(%rip), %rdi call puts@PLT movl 12(%rsp), %eax movl %eax, 28(%rsp) movl $1, 32(%rsp) movl 8(%rsp), %eax movl %eax, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L15 .L10: call cudaDeviceReset@PLT movl %eax, %edx movl $0, %eax testl %edx, %edx jne .L16 .L9: movq 40(%rsp), %rdx subq %fs:40, %rdx jne .L17 addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state call _ZL8sayHellov jmp .L10 .L16: leaq .LC4(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi call __fprintf_chk@PLT movl $1, %eax jmp .L9 .L17: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC5: .string "_Z8sayHellov" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _ZL8sayHellov(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .section .text._ZL8sayHellov,"axG",@progbits,_ZL8sayHellov,comdat .globl _ZL8sayHellov ; -- Begin function _ZL8sayHellov .p2align 8 .type _ZL8sayHellov,@function _ZL8sayHellov: ; @_ZL8sayHellov ; %bb.0: s_clause 0x1 s_load_b32 s14, s[0:1], 0xc s_load_b64 s[2:3], s[0:1], 0x50 v_mbcnt_lo_u32_b32 v21, -1, 0 v_mov_b32_e32 v7, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v5, v21 ;;#ASMSTART ;;#ASMEND v_readfirstlane_b32 s0, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s0, s0, v5 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_6 ; %bb.1: v_mov_b32_e32 v1, 0 s_mov_b32 s4, exec_lo s_waitcnt lgkmcnt(0) global_load_b64 v[9:10], v1, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[2:3], v1, s[2:3] offset:40 global_load_b64 v[6:7], v1, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v2, v2, v9 v_and_b32_e32 v3, v3, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v4, v2, 24 v_mul_lo_u32 v3, v3, 24 v_mul_lo_u32 v2, v2, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v3, v4, v3 s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v6, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo global_load_b64 v[7:8], v[2:3], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[7:8], v[9:10] s_cbranch_execz .LBB0_5 ; %bb.2: ; %.preheader3.i.i.i.preheader s_mov_b32 s5, 0 .p2align 6 .LBB0_3: ; %.preheader3.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[2:3], v1, s[2:3] offset:40 global_load_b64 v[11:12], v1, s[2:3] v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v2, v9 v_and_b32_e32 v8, v3, v10 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, v2, 24, v[11:12] v_mov_b32_e32 v2, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[3:4], null, v8, 24, v[2:3] v_mov_b32_e32 v7, v3 global_load_b64 v[7:8], v[6:7], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_3 ; %bb.4: ; %Flow292 s_or_b32 exec_lo, exec_lo, s5 .LBB0_5: ; %Flow294 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB0_6: ; %.loopexit4.i.i.i s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v6, 0 v_readfirstlane_b32 s4, v7 v_readfirstlane_b32 s5, v8 s_mov_b32 s8, exec_lo s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[9:10], v6, s[2:3] offset:40 global_load_b128 v[1:4], v6, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v9 v_readfirstlane_b32 s7, v10 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_8 ; %bb.7: v_dual_mov_b32 v7, s8 :: v_dual_mov_b32 v8, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v9, 2 :: v_dual_mov_b32 v10, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v11, vcc_lo, v1, s8 v_add_co_ci_u32_e32 v12, vcc_lo, s9, v2, vcc_lo global_store_b128 v[11:12], v[7:10], off offset:8 .LBB0_8: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 v_lshlrev_b64 v[5:6], 6, v[5:6] s_waitcnt vmcnt(0) v_add_co_u32 v3, vcc_lo, v3, s8 v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo v_mov_b32_e32 v4, 0 s_mov_b32 s8, 0 s_delay_alu instid0(VALU_DEP_3) v_add_co_u32 v7, vcc_lo, v3, v5 v_mov_b32_e32 v3, 33 s_mov_b32 s11, s8 s_mov_b32 s9, s8 s_mov_b32 s10, s8 v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v12, s11 v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v11, s10 v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v9, s8 s_clause 0x3 global_store_b128 v[7:8], v[3:6], off global_store_b128 v[7:8], v[9:12], off offset:16 global_store_b128 v[7:8], v[9:12], off offset:32 global_store_b128 v[7:8], v[9:12], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_16 ; %bb.9: v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, s4 v_mov_b32_e32 v13, s5 s_clause 0x1 global_load_b64 v[14:15], v11, s[2:3] offset:32 glc global_load_b64 v[3:4], v11, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v3 v_readfirstlane_b32 s9, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v9, vcc_lo, v1, s8 v_add_co_ci_u32_e32 v10, vcc_lo, s10, v2, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[9:10], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[5:6], v11, v[12:15], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[5:6], v[14:15] s_cbranch_execz .LBB0_12 ; %bb.10: ; %.preheader1.i.i.i.preheader s_mov_b32 s9, 0 .LBB0_11: ; %.preheader1.i.i.i ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5 s_sleep 1 global_store_b64 v[9:10], v[5:6], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[3:4], v11, v[3:6], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6] v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB0_11 .LBB0_12: ; %Flow290 s_or_b32 exec_lo, exec_lo, s8 v_mov_b32_e32 v3, 0 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v5, s9, 0 global_load_b64 v[3:4], v3, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v5 s_cbranch_execz .LBB0_14 ; %bb.13: s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v5, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[3:4], v[5:6], off offset:8 .LBB0_14: s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[5:6], v[3:4], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6] s_cbranch_vccnz .LBB0_16 ; %bb.15: global_load_b32 v3, v[3:4], off offset:24 v_mov_b32_e32 v4, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v3 s_waitcnt_vscnt null, 0x0 global_store_b64 v[5:6], v[3:4], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_16: ; %Flow291 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v1, vcc_lo, v1, s1 v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, v1, 20 v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo s_branch .LBB0_20 .p2align 6 .LBB0_17: ; in Loop: Header=BB0_20 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v3 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_19 ; %bb.18: ; in Loop: Header=BB0_20 Depth=1 s_sleep 1 s_cbranch_execnz .LBB0_20 s_branch .LBB0_22 .p2align 6 .LBB0_19: s_branch .LBB0_22 .LBB0_20: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v3, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_17 ; %bb.21: ; in Loop: Header=BB0_20 Depth=1 global_load_b32 v3, v[1:2], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v3, 1, v3 s_branch .LBB0_17 .LBB0_22: global_load_b64 v[22:23], v[7:8], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_26 ; %bb.23: v_mov_b32_e32 v7, 0 s_clause 0x2 global_load_b64 v[3:4], v7, s[2:3] offset:40 global_load_b64 v[8:9], v7, s[2:3] offset:24 glc global_load_b64 v[5:6], v7, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v10, vcc_lo, v3, 1 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, v10, s4 v_add_co_ci_u32_e32 v2, vcc_lo, s5, v11, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[1:2] v_dual_cndmask_b32 v2, v2, v11 :: v_dual_cndmask_b32 v1, v1, v10 v_and_b32_e32 v4, v2, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v3, v1, v3 v_mul_lo_u32 v4, v4, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v10, v3, 24 v_mul_lo_u32 v3, v3, 24 v_add_nc_u32_e32 v4, v10, v4 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v5, vcc_lo, v5, v3 v_mov_b32_e32 v3, v8 v_add_co_ci_u32_e32 v6, vcc_lo, v6, v4, vcc_lo v_mov_b32_e32 v4, v9 global_store_b64 v[5:6], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[3:4], v7, v[1:4], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[3:4], v[8:9] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_26 ; %bb.24: ; %.preheader.i.i.i.preheader s_mov_b32 s0, 0 .LBB0_25: ; %.preheader.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[5:6], v[3:4], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v7, v[1:4], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[3:4] v_dual_mov_b32 v3, v8 :: v_dual_mov_b32 v4, v9 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_25 .LBB0_26: ; %__ockl_printf_begin.exit s_or_b32 exec_lo, exec_lo, s1 s_getpc_b64 s[4:5] s_add_u32 s4, s4, .str@rel32@lo+4 s_addc_u32 s5, s5, .str@rel32@hi+12 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u64 s[4:5], 0 s_cbranch_scc0 .LBB0_104 ; %bb.27: s_waitcnt vmcnt(0) v_dual_mov_b32 v25, 0 :: v_dual_and_b32 v24, 2, v22 v_and_b32_e32 v1, -3, v22 s_mov_b64 s[6:7], 23 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_mov_b32 v2, v23 :: v_dual_mov_b32 v27, v25 v_mov_b32_e32 v26, v24 s_branch .LBB0_29 .LBB0_28: ; %__ockl_hostcall_preview.exit20.i ; in Loop: Header=BB0_29 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_sub_u32 s6, s6, s8 s_subb_u32 s7, s7, s9 s_add_u32 s4, s4, s8 s_addc_u32 s5, s5, s9 s_cmp_lg_u64 s[6:7], 0 s_cbranch_scc0 .LBB0_105 .LBB0_29: ; =>This Loop Header: Depth=1 ; Child Loop BB0_32 Depth 2 ; Child Loop BB0_39 Depth 2 ; Child Loop BB0_46 Depth 2 ; Child Loop BB0_53 Depth 2 ; Child Loop BB0_60 Depth 2 ; Child Loop BB0_67 Depth 2 ; Child Loop BB0_74 Depth 2 ; Child Loop BB0_81 Depth 2 ; Child Loop BB0_89 Depth 2 ; Child Loop BB0_98 Depth 2 ; Child Loop BB0_103 Depth 2 v_cmp_lt_u64_e64 s0, s[6:7], 56 ; implicit-def: $vgpr3_vgpr4 ; implicit-def: $sgpr17 s_delay_alu instid0(VALU_DEP_1) s_and_b32 s0, s0, exec_lo s_cselect_b32 s8, s6, 56 s_cselect_b32 s9, s7, 0 s_cmp_gt_u32 s8, 7 s_mov_b32 s0, -1 s_cbranch_scc1 .LBB0_34 ; %bb.30: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v3, 0 v_mov_b32_e32 v4, 0 s_cmp_eq_u32 s8, 0 s_cbranch_scc1 .LBB0_33 ; %bb.31: ; %.preheader31.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_lshl_b64 s[0:1], s[8:9], 3 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], s[4:5] .LBB0_32: ; %.preheader31.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v5, v25, s[12:13] s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v5 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[5:6], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_add_u32 s12, s12, 1 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s0, s10 v_or_b32_e32 v3, v5, v3 v_or_b32_e32 v4, v6, v4 s_cbranch_scc1 .LBB0_32 .LBB0_33: ; %Flow261 ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s0, 0 s_mov_b32 s17, 0 .LBB0_34: ; %Flow263 ; in Loop: Header=BB0_29 Depth=1 s_and_not1_b32 vcc_lo, exec_lo, s0 s_mov_b64 s[0:1], s[4:5] s_cbranch_vccnz .LBB0_36 ; %bb.35: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[3:4], v25, s[4:5] s_add_i32 s17, s8, -8 s_add_u32 s0, s4, 8 s_addc_u32 s1, s5, 0 .LBB0_36: ; %.loopexit32.i ; in Loop: Header=BB0_29 Depth=1 s_cmp_gt_u32 s17, 7 s_cbranch_scc1 .LBB0_41 ; %bb.37: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v5, 0 v_mov_b32_e32 v6, 0 s_cmp_eq_u32 s17, 0 s_cbranch_scc1 .LBB0_40 ; %bb.38: ; %.preheader29.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_39: ; %.preheader29.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s18, s0, s12 s_addc_u32 s19, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v7, v25, s[18:19] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s17, s12 v_or_b32_e32 v5, v7, v5 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v6, v8, v6 s_cbranch_scc1 .LBB0_39 .LBB0_40: ; %Flow256 ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s16, 0 s_cbranch_execz .LBB0_42 s_branch .LBB0_43 .LBB0_41: ; in Loop: Header=BB0_29 Depth=1 ; implicit-def: $vgpr5_vgpr6 ; implicit-def: $sgpr16 .LBB0_42: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[5:6], v25, s[0:1] s_add_i32 s16, s17, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_43: ; %.loopexit30.i ; in Loop: Header=BB0_29 Depth=1 s_cmp_gt_u32 s16, 7 s_cbranch_scc1 .LBB0_48 ; %bb.44: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v7, 0 v_mov_b32_e32 v8, 0 s_cmp_eq_u32 s16, 0 s_cbranch_scc1 .LBB0_47 ; %bb.45: ; %.preheader27.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_46: ; %.preheader27.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s18, s0, s12 s_addc_u32 s19, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v9, v25, s[18:19] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[9:10], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s16, s12 v_or_b32_e32 v7, v9, v7 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v8, v10, v8 s_cbranch_scc1 .LBB0_46 .LBB0_47: ; %Flow251 ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s17, 0 s_cbranch_execz .LBB0_49 s_branch .LBB0_50 .LBB0_48: ; in Loop: Header=BB0_29 Depth=1 ; implicit-def: $sgpr17 .LBB0_49: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[7:8], v25, s[0:1] s_add_i32 s17, s16, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_50: ; %.loopexit28.i ; in Loop: Header=BB0_29 Depth=1 s_cmp_gt_u32 s17, 7 s_cbranch_scc1 .LBB0_55 ; %bb.51: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v9, 0 v_mov_b32_e32 v10, 0 s_cmp_eq_u32 s17, 0 s_cbranch_scc1 .LBB0_54 ; %bb.52: ; %.preheader25.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_53: ; %.preheader25.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s18, s0, s12 s_addc_u32 s19, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v11, v25, s[18:19] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[11:12], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s17, s12 v_or_b32_e32 v9, v11, v9 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v10, v12, v10 s_cbranch_scc1 .LBB0_53 .LBB0_54: ; %Flow246 ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s16, 0 s_cbranch_execz .LBB0_56 s_branch .LBB0_57 .LBB0_55: ; in Loop: Header=BB0_29 Depth=1 ; implicit-def: $vgpr9_vgpr10 ; implicit-def: $sgpr16 .LBB0_56: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[9:10], v25, s[0:1] s_add_i32 s16, s17, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_57: ; %.loopexit26.i ; in Loop: Header=BB0_29 Depth=1 s_cmp_gt_u32 s16, 7 s_cbranch_scc1 .LBB0_62 ; %bb.58: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v11, 0 v_mov_b32_e32 v12, 0 s_cmp_eq_u32 s16, 0 s_cbranch_scc1 .LBB0_61 ; %bb.59: ; %.preheader23.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_60: ; %.preheader23.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s18, s0, s12 s_addc_u32 s19, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v13, v25, s[18:19] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[13:14], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s16, s12 v_or_b32_e32 v11, v13, v11 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v12, v14, v12 s_cbranch_scc1 .LBB0_60 .LBB0_61: ; %Flow241 ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s17, 0 s_cbranch_execz .LBB0_63 s_branch .LBB0_64 .LBB0_62: ; in Loop: Header=BB0_29 Depth=1 ; implicit-def: $sgpr17 .LBB0_63: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[11:12], v25, s[0:1] s_add_i32 s17, s16, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_64: ; %.loopexit24.i ; in Loop: Header=BB0_29 Depth=1 s_cmp_gt_u32 s17, 7 s_cbranch_scc1 .LBB0_69 ; %bb.65: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v13, 0 v_mov_b32_e32 v14, 0 s_cmp_eq_u32 s17, 0 s_cbranch_scc1 .LBB0_68 ; %bb.66: ; %.preheader21.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_67: ; %.preheader21.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s18, s0, s12 s_addc_u32 s19, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v15, v25, s[18:19] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v15 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[15:16], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s17, s12 v_or_b32_e32 v13, v15, v13 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v14, v16, v14 s_cbranch_scc1 .LBB0_67 .LBB0_68: ; %Flow236 ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s16, 0 s_cbranch_execz .LBB0_70 s_branch .LBB0_71 .LBB0_69: ; in Loop: Header=BB0_29 Depth=1 ; implicit-def: $vgpr13_vgpr14 ; implicit-def: $sgpr16 .LBB0_70: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[13:14], v25, s[0:1] s_add_i32 s16, s17, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_71: ; %.loopexit22.i ; in Loop: Header=BB0_29 Depth=1 s_cmp_gt_u32 s16, 7 s_cbranch_scc1 .LBB0_76 ; %bb.72: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v15, 0 v_mov_b32_e32 v16, 0 s_cmp_eq_u32 s16, 0 s_cbranch_scc1 .LBB0_75 ; %bb.73: ; %.preheader.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], s[0:1] .LBB0_74: ; %.preheader.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v17, v25, s[12:13] s_add_i32 s16, s16, -1 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v17 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[17:18], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_add_u32 s12, s12, 1 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s16, 0 v_or_b32_e32 v15, v17, v15 v_or_b32_e32 v16, v18, v16 s_cbranch_scc1 .LBB0_74 .LBB0_75: ; %Flow231 ; in Loop: Header=BB0_29 Depth=1 s_cbranch_execz .LBB0_77 s_branch .LBB0_78 .LBB0_76: ; in Loop: Header=BB0_29 Depth=1 .LBB0_77: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[15:16], v25, s[0:1] .LBB0_78: ; %.loopexit.i ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v24, v21 v_mov_b32_e32 v28, 0 v_mov_b32_e32 v29, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v24 v_cmp_eq_u32_e64 s0, s0, v24 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_84 ; %bb.79: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[19:20], v25, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[17:18], v25, s[2:3] offset:40 global_load_b64 v[28:29], v25, s[2:3] s_mov_b32 s10, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v18, v18, v20 v_and_b32_e32 v17, v17, v19 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v18, v18, 24 v_mul_hi_u32 v30, v17, 24 v_mul_lo_u32 v17, v17, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v18, v30, v18 s_waitcnt vmcnt(0) v_add_co_u32 v17, vcc_lo, v28, v17 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v18, vcc_lo, v29, v18, vcc_lo global_load_b64 v[17:18], v[17:18], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[28:29], v25, v[17:20], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[28:29], v[19:20] s_cbranch_execz .LBB0_83 ; %bb.80: ; %.preheader3.i.i19.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s11, 0 .p2align 6 .LBB0_81: ; %.preheader3.i.i19.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 s_clause 0x1 global_load_b64 v[17:18], v25, s[2:3] offset:40 global_load_b64 v[30:31], v25, s[2:3] v_dual_mov_b32 v19, v28 :: v_dual_mov_b32 v20, v29 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v17, v17, v19 s_waitcnt vmcnt(0) v_mad_u64_u32 v[28:29], null, v17, 24, v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v17, v29 :: v_dual_and_b32 v18, v18, v20 v_mad_u64_u32 v[29:30], null, v18, 24, v[17:18] global_load_b64 v[17:18], v[28:29], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[28:29], v25, v[17:20], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[28:29], v[19:20] s_or_b32 s11, vcc_lo, s11 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s11 s_cbranch_execnz .LBB0_81 ; %bb.82: ; %Flow226 ; in Loop: Header=BB0_29 Depth=1 s_or_b32 exec_lo, exec_lo, s11 .LBB0_83: ; %Flow228 ; in Loop: Header=BB0_29 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s10 .LBB0_84: ; %.loopexit4.i.i14.i ; in Loop: Header=BB0_29 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_clause 0x1 global_load_b64 v[30:31], v25, s[2:3] offset:40 global_load_b128 v[17:20], v25, s[2:3] v_readfirstlane_b32 s10, v28 v_readfirstlane_b32 s11, v29 s_mov_b32 s16, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s12, v30 v_readfirstlane_b32 s13, v31 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[12:13], s[10:11], s[12:13] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_86 ; %bb.85: ; in Loop: Header=BB0_29 Depth=1 v_dual_mov_b32 v28, s16 :: v_dual_mov_b32 v29, 0 s_mul_i32 s16, s13, 24 s_mul_hi_u32 s17, s12, 24 v_dual_mov_b32 v30, 2 :: v_dual_mov_b32 v31, 1 s_add_i32 s17, s17, s16 s_mul_i32 s16, s12, 24 s_waitcnt vmcnt(0) v_add_co_u32 v32, vcc_lo, v17, s16 v_add_co_ci_u32_e32 v33, vcc_lo, s17, v18, vcc_lo global_store_b128 v[32:33], v[28:31], off offset:8 .LBB0_86: ; in Loop: Header=BB0_29 Depth=1 s_or_b32 exec_lo, exec_lo, s1 v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56 v_or_b32_e32 v28, v2, v27 v_or_b32_e32 v29, v1, v26 s_lshl_b64 s[16:17], s[12:13], 12 s_lshl_b32 s1, s8, 2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_add_i32 s1, s1, 28 v_dual_cndmask_b32 v2, v28, v2 :: v_dual_cndmask_b32 v1, v29, v1 v_lshlrev_b64 v[28:29], 6, v[24:25] s_waitcnt vmcnt(0) v_add_co_u32 v19, vcc_lo, v19, s16 v_add_co_ci_u32_e32 v20, vcc_lo, s17, v20, vcc_lo s_and_b32 s1, s1, 0x1e0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v19, vcc_lo, v19, v28 v_and_or_b32 v1, v1, 0xffffff1f, s1 v_add_co_ci_u32_e32 v20, vcc_lo, v20, v29, vcc_lo s_clause 0x3 global_store_b128 v[19:20], v[1:4], off global_store_b128 v[19:20], v[5:8], off offset:16 global_store_b128 v[19:20], v[9:12], off offset:32 global_store_b128 v[19:20], v[13:16], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_94 ; %bb.87: ; in Loop: Header=BB0_29 Depth=1 s_clause 0x1 global_load_b64 v[9:10], v25, s[2:3] offset:32 glc global_load_b64 v[1:2], v25, s[2:3] offset:40 v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11 s_waitcnt vmcnt(0) v_readfirstlane_b32 s16, v1 v_readfirstlane_b32 s17, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[16:17], s[16:17], s[10:11] s_mul_i32 s17, s17, 24 s_mul_hi_u32 s18, s16, 24 s_mul_i32 s16, s16, 24 s_add_i32 s18, s18, s17 v_add_co_u32 v5, vcc_lo, v17, s16 v_add_co_ci_u32_e32 v6, vcc_lo, s18, v18, vcc_lo s_mov_b32 s16, exec_lo global_store_b64 v[5:6], v[9:10], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[3:4], v25, v[7:10], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[3:4], v[9:10] s_cbranch_execz .LBB0_90 ; %bb.88: ; %.preheader1.i.i17.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s17, 0 .LBB0_89: ; %.preheader1.i.i17.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 v_dual_mov_b32 v1, s10 :: v_dual_mov_b32 v2, s11 s_sleep 1 global_store_b64 v[5:6], v[3:4], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[1:2], v25, v[1:4], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[3:4] v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1 s_or_b32 s17, vcc_lo, s17 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s17 s_cbranch_execnz .LBB0_89 .LBB0_90: ; %Flow224 ; in Loop: Header=BB0_29 Depth=1 s_or_b32 exec_lo, exec_lo, s16 global_load_b64 v[1:2], v25, s[2:3] offset:16 s_mov_b32 s17, exec_lo s_mov_b32 s16, exec_lo v_mbcnt_lo_u32_b32 v3, s17, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v3 s_cbranch_execz .LBB0_92 ; %bb.91: ; in Loop: Header=BB0_29 Depth=1 s_bcnt1_i32_b32 s17, s17 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, s17 s_waitcnt vmcnt(0) global_atomic_add_u64 v[1:2], v[3:4], off offset:8 .LBB0_92: ; in Loop: Header=BB0_29 Depth=1 s_or_b32 exec_lo, exec_lo, s16 s_waitcnt vmcnt(0) global_load_b64 v[3:4], v[1:2], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4] s_cbranch_vccnz .LBB0_94 ; %bb.93: ; in Loop: Header=BB0_29 Depth=1 global_load_b32 v24, v[1:2], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s16, v24 s_waitcnt_vscnt null, 0x0 global_store_b64 v[3:4], v[24:25], off s_and_b32 m0, s16, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_94: ; %Flow225 ; in Loop: Header=BB0_29 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s13, 24 s_mul_hi_u32 s13, s12, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s13, s13, s1 s_mul_i32 s1, s12, 24 v_add_co_u32 v1, vcc_lo, v17, s1 v_add_co_ci_u32_e32 v2, vcc_lo, s13, v18, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, v1, 20 v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo s_branch .LBB0_98 .p2align 6 .LBB0_95: ; in Loop: Header=BB0_98 Depth=2 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v3 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_97 ; %bb.96: ; in Loop: Header=BB0_98 Depth=2 s_sleep 1 s_cbranch_execnz .LBB0_98 s_branch .LBB0_100 .p2align 6 .LBB0_97: ; in Loop: Header=BB0_29 Depth=1 s_branch .LBB0_100 .LBB0_98: ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 v_mov_b32_e32 v3, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_95 ; %bb.99: ; in Loop: Header=BB0_98 Depth=2 global_load_b32 v3, v[1:2], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v3, 1, v3 s_branch .LBB0_95 .LBB0_100: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[1:2], v[19:20], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_28 ; %bb.101: ; in Loop: Header=BB0_29 Depth=1 s_clause 0x2 global_load_b64 v[5:6], v25, s[2:3] offset:40 global_load_b64 v[9:10], v25, s[2:3] offset:24 glc global_load_b64 v[7:8], v25, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v11, vcc_lo, v5, 1 v_add_co_ci_u32_e32 v12, vcc_lo, 0, v6, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, v11, s10 v_add_co_ci_u32_e32 v4, vcc_lo, s11, v12, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4] v_dual_cndmask_b32 v4, v4, v12 :: v_dual_cndmask_b32 v3, v3, v11 v_and_b32_e32 v6, v4, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v5, v3, v5 v_mul_hi_u32 v11, v5, 24 v_mul_lo_u32 v5, v5, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v7, vcc_lo, v7, v5 v_mov_b32_e32 v5, v9 v_mul_lo_u32 v6, v6, 24 v_add_nc_u32_e32 v6, v11, v6 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo v_mov_b32_e32 v6, v10 global_store_b64 v[7:8], v[9:10], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[5:6], v25, v[3:6], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[9:10] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_28 ; %bb.102: ; %.preheader.i.i16.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s0, 0 .LBB0_103: ; %.preheader.i.i16.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 global_store_b64 v[7:8], v[5:6], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[9:10], v25, v[3:6], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[5:6] v_dual_mov_b32 v5, v9 :: v_dual_mov_b32 v6, v10 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_103 s_branch .LBB0_28 .LBB0_104: ; implicit-def: $vgpr1_vgpr2 s_cbranch_execnz .LBB0_106 s_branch .LBB0_133 .LBB0_105: ; %Flow264 s_branch .LBB0_133 .LBB0_106: v_mov_b32_e32 v5, v21 v_mov_b32_e32 v7, 0 v_mov_b32_e32 v8, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v5 v_cmp_eq_u32_e64 s0, s0, v5 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_112 ; %bb.107: s_waitcnt vmcnt(0) v_mov_b32_e32 v1, 0 s_mov_b32 s4, exec_lo global_load_b64 v[9:10], v1, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[2:3], v1, s[2:3] offset:40 global_load_b64 v[6:7], v1, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v2, v2, v9 v_and_b32_e32 v3, v3, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v4, v2, 24 v_mul_lo_u32 v3, v3, 24 v_mul_lo_u32 v2, v2, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v3, v4, v3 s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v6, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo global_load_b64 v[7:8], v[2:3], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[7:8], v[9:10] s_cbranch_execz .LBB0_111 ; %bb.108: ; %.preheader3.i.i.i6.preheader s_mov_b32 s5, 0 .p2align 6 .LBB0_109: ; %.preheader3.i.i.i6 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[2:3], v1, s[2:3] offset:40 global_load_b64 v[11:12], v1, s[2:3] v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v2, v9 v_and_b32_e32 v8, v3, v10 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, v2, 24, v[11:12] v_mov_b32_e32 v2, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[3:4], null, v8, 24, v[2:3] v_mov_b32_e32 v7, v3 global_load_b64 v[7:8], v[6:7], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_109 ; %bb.110: ; %Flow276 s_or_b32 exec_lo, exec_lo, s5 .LBB0_111: ; %Flow278 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB0_112: ; %.loopexit4.i.i.i1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v6, 0 v_readfirstlane_b32 s4, v7 v_readfirstlane_b32 s5, v8 s_mov_b32 s8, exec_lo s_clause 0x1 global_load_b64 v[9:10], v6, s[2:3] offset:40 global_load_b128 v[1:4], v6, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v9 v_readfirstlane_b32 s7, v10 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_114 ; %bb.113: v_dual_mov_b32 v7, s8 :: v_dual_mov_b32 v8, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v9, 2 :: v_dual_mov_b32 v10, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v11, vcc_lo, v1, s8 v_add_co_ci_u32_e32 v12, vcc_lo, s9, v2, vcc_lo global_store_b128 v[11:12], v[7:10], off offset:8 .LBB0_114: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 v_and_or_b32 v22, v22, 0xffffff1f, 32 s_waitcnt vmcnt(0) v_add_co_u32 v7, vcc_lo, v3, s8 v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo v_lshlrev_b64 v[3:4], 6, v[5:6] s_mov_b32 s8, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_add_co_u32 v7, vcc_lo, v7, v3 v_mov_b32_e32 v9, 0 v_add_co_ci_u32_e32 v8, vcc_lo, v8, v4, vcc_lo v_dual_mov_b32 v3, s8 :: v_dual_mov_b32 v6, s11 v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10 s_delay_alu instid0(VALU_DEP_4) v_mov_b32_e32 v10, v9 s_clause 0x4 global_store_b64 v[7:8], v[22:23], off global_store_b128 v[7:8], v[3:6], off offset:8 global_store_b128 v[7:8], v[3:6], off offset:24 global_store_b128 v[7:8], v[3:6], off offset:40 global_store_b64 v[7:8], v[9:10], off offset:56 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_122 ; %bb.115: v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, s4 v_mov_b32_e32 v13, s5 s_clause 0x1 global_load_b64 v[14:15], v11, s[2:3] offset:32 glc global_load_b64 v[3:4], v11, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v3 v_readfirstlane_b32 s9, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v9, vcc_lo, v1, s8 v_add_co_ci_u32_e32 v10, vcc_lo, s10, v2, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[9:10], v[14:15], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[5:6], v11, v[12:15], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[5:6], v[14:15] s_cbranch_execz .LBB0_118 ; %bb.116: ; %.preheader1.i.i.i4.preheader s_mov_b32 s9, 0 .LBB0_117: ; %.preheader1.i.i.i4 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5 s_sleep 1 global_store_b64 v[9:10], v[5:6], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[3:4], v11, v[3:6], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6] v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB0_117 .LBB0_118: ; %Flow274 s_or_b32 exec_lo, exec_lo, s8 v_mov_b32_e32 v3, 0 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v5, s9, 0 global_load_b64 v[3:4], v3, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v5 s_cbranch_execz .LBB0_120 ; %bb.119: s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v5, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[3:4], v[5:6], off offset:8 .LBB0_120: s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[5:6], v[3:4], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6] s_cbranch_vccnz .LBB0_122 ; %bb.121: global_load_b32 v3, v[3:4], off offset:24 v_mov_b32_e32 v4, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v3 s_waitcnt_vscnt null, 0x0 global_store_b64 v[5:6], v[3:4], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_122: ; %Flow275 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v1, vcc_lo, v1, s1 v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, v1, 20 v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo s_branch .LBB0_126 .p2align 6 .LBB0_123: ; in Loop: Header=BB0_126 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v3 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_125 ; %bb.124: ; in Loop: Header=BB0_126 Depth=1 s_sleep 1 s_cbranch_execnz .LBB0_126 s_branch .LBB0_128 .p2align 6 .LBB0_125: s_branch .LBB0_128 .LBB0_126: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v3, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_123 ; %bb.127: ; in Loop: Header=BB0_126 Depth=1 global_load_b32 v3, v[1:2], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v3, 1, v3 s_branch .LBB0_123 .LBB0_128: global_load_b64 v[1:2], v[7:8], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_132 ; %bb.129: v_mov_b32_e32 v9, 0 s_clause 0x2 global_load_b64 v[5:6], v9, s[2:3] offset:40 global_load_b64 v[10:11], v9, s[2:3] offset:24 glc global_load_b64 v[7:8], v9, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v12, vcc_lo, v5, 1 v_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, v12, s4 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v13, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4] v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12 v_and_b32_e32 v6, v4, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v5, v3, v5 v_mul_lo_u32 v6, v6, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v12, v5, 24 v_mul_lo_u32 v5, v5, 24 v_add_nc_u32_e32 v6, v12, v6 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v7, vcc_lo, v7, v5 v_mov_b32_e32 v5, v10 v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo v_mov_b32_e32 v6, v11 global_store_b64 v[7:8], v[10:11], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[5:6], v9, v[3:6], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[10:11] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_132 ; %bb.130: ; %.preheader.i.i.i3.preheader s_mov_b32 s0, 0 .LBB0_131: ; %.preheader.i.i.i3 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[7:8], v[5:6], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[10:11], v9, v[3:6], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[5:6] v_dual_mov_b32 v5, v10 :: v_dual_mov_b32 v6, v11 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_131 .LBB0_132: ; %__ockl_hostcall_preview.exit.i s_or_b32 exec_lo, exec_lo, s1 .LBB0_133: ; %__ockl_printf_append_string_n.exit ;;#ASMSTART ;;#ASMEND v_readfirstlane_b32 s0, v21 v_mov_b32_e32 v3, 0 v_mov_b32_e32 v4, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s0, s0, v21 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_139 ; %bb.134: v_mov_b32_e32 v5, 0 s_mov_b32 s4, exec_lo global_load_b64 v[8:9], v5, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[3:4], v5, s[2:3] offset:40 global_load_b64 v[6:7], v5, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v4, v4, v9 v_and_b32_e32 v3, v3, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v4, v4, 24 v_mul_hi_u32 v10, v3, 24 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v4, v10, v4 s_waitcnt vmcnt(0) v_add_co_u32 v3, vcc_lo, v6, v3 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo global_load_b64 v[6:7], v[3:4], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[3:4], v5, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[3:4], v[8:9] s_cbranch_execz .LBB0_138 ; %bb.135: ; %.preheader3.i.i.i13.preheader s_mov_b32 s5, 0 .p2align 6 .LBB0_136: ; %.preheader3.i.i.i13 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[6:7], v5, s[2:3] offset:40 global_load_b64 v[10:11], v5, s[2:3] v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v8, v3 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v6, v6, v8 s_waitcnt vmcnt(0) v_mad_u64_u32 v[3:4], null, v6, 24, v[10:11] v_and_b32_e32 v10, v7, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, v10, 24, v[4:5] v_mov_b32_e32 v4, v6 global_load_b64 v[6:7], v[3:4], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[3:4], v5, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[8:9] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_136 ; %bb.137: ; %Flow212 s_or_b32 exec_lo, exec_lo, s5 .LBB0_138: ; %Flow214 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB0_139: ; %.loopexit4.i.i.i7 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s4, v3 v_readfirstlane_b32 s5, v4 s_mov_b32 s8, exec_lo s_clause 0x1 global_load_b64 v[9:10], v5, s[2:3] offset:40 global_load_b128 v[5:8], v5, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v9 v_readfirstlane_b32 s7, v10 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_141 ; %bb.140: v_dual_mov_b32 v9, s8 :: v_dual_mov_b32 v10, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v3, vcc_lo, v5, s8 v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo global_store_b128 v[3:4], v[9:12], off offset:8 .LBB0_141: s_or_b32 exec_lo, exec_lo, s1 s_and_b32 s1, 0xffff, s14 s_lshl_b64 s[10:11], s[6:7], 12 v_mad_u64_u32 v[3:4], null, s15, s1, v[0:1] s_mov_b32 s8, 0 s_waitcnt vmcnt(0) v_add_co_u32 v0, vcc_lo, v7, s10 v_add_co_ci_u32_e32 v7, vcc_lo, s11, v8, vcc_lo s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_mov_b32_e32 v4, 0 v_and_or_b32 v1, v1, 0xffffff1d, 34 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mov_b32_e32 v22, v4 v_lshlrev_b64 v[9:10], 6, v[21:22] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v11, vcc_lo, v0, v9 v_add_co_ci_u32_e32 v12, vcc_lo, v7, v10, vcc_lo v_mov_b32_e32 v7, s8 v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v8, s9 v_mov_b32_e32 v10, s11 s_clause 0x3 global_store_b128 v[11:12], v[1:4], off global_store_b128 v[11:12], v[7:10], off offset:16 global_store_b128 v[11:12], v[7:10], off offset:32 global_store_b128 v[11:12], v[7:10], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_149 ; %bb.142: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v9, s4 v_mov_b32_e32 v10, s5 s_clause 0x1 global_load_b64 v[11:12], v4, s[2:3] offset:32 glc global_load_b64 v[0:1], v4, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v0 v_readfirstlane_b32 s9, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v7, vcc_lo, v5, s8 v_add_co_ci_u32_e32 v8, vcc_lo, s10, v6, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[7:8], v[11:12], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v4, v[9:12], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[11:12] s_cbranch_execz .LBB0_145 ; %bb.143: ; %.preheader1.i.i.i11.preheader s_mov_b32 s9, 0 .LBB0_144: ; %.preheader1.i.i.i11 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 s_sleep 1 global_store_b64 v[7:8], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v4, v[0:3], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB0_144 .LBB0_145: ; %Flow210 s_or_b32 exec_lo, exec_lo, s8 v_mov_b32_e32 v0, 0 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v2, s9, 0 global_load_b64 v[0:1], v0, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB0_147 ; %bb.146: s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB0_147: s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB0_149 ; %bb.148: global_load_b32 v0, v[0:1], off offset:24 v_mov_b32_e32 v1, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v0 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[0:1], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_149: ; %Flow211 s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v0, vcc_lo, v5, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v6, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_153 .p2align 6 .LBB0_150: ; in Loop: Header=BB0_153 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_152 ; %bb.151: ; in Loop: Header=BB0_153 Depth=1 s_sleep 1 s_cbranch_execnz .LBB0_153 s_branch .LBB0_155 .p2align 6 .LBB0_152: s_branch .LBB0_155 .LBB0_153: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_150 ; %bb.154: ; in Loop: Header=BB0_153 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_150 .LBB0_155: s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_159 ; %bb.156: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[2:3] offset:40 global_load_b64 v[7:8], v6, s[2:3] offset:24 glc global_load_b64 v[4:5], v6, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s4 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_159 ; %bb.157: ; %.preheader.i.i.i10.preheader s_mov_b32 s0, 0 .LBB0_158: ; %.preheader.i.i.i10 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_158 .LBB0_159: ; %__ockl_printf_append_args.exit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZL8sayHellov .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 256 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 34 .amdhsa_next_free_sgpr 20 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZL8sayHellov,"axG",@progbits,_ZL8sayHellov,comdat .Lfunc_end0: .size _ZL8sayHellov, .Lfunc_end0-_ZL8sayHellov ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 6680 ; NumSgprs: 22 ; NumVgprs: 34 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 4 ; NumSGPRsForWavesPerEU: 22 ; NumVGPRsForWavesPerEU: 34 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type .str,@object ; @.str .section .rodata.str1.1,"aMS",@progbits,1 .str: .asciz "Hello from thread %d!\n" .size .str, 23 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: hidden_block_count_x - .offset: 4 .size: 4 .value_kind: hidden_block_count_y - .offset: 8 .size: 4 .value_kind: hidden_block_count_z - .offset: 12 .size: 2 .value_kind: hidden_group_size_x - .offset: 14 .size: 2 .value_kind: hidden_group_size_y - .offset: 16 .size: 2 .value_kind: hidden_group_size_z - .offset: 18 .size: 2 .value_kind: hidden_remainder_x - .offset: 20 .size: 2 .value_kind: hidden_remainder_y - .offset: 22 .size: 2 .value_kind: hidden_remainder_z - .offset: 40 .size: 8 .value_kind: hidden_global_offset_x - .offset: 48 .size: 8 .value_kind: hidden_global_offset_y - .offset: 56 .size: 8 .value_kind: hidden_global_offset_z - .offset: 64 .size: 2 .value_kind: hidden_grid_dims - .offset: 80 .size: 8 .value_kind: hidden_hostcall_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 256 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _ZL8sayHellov .private_segment_fixed_size: 0 .sgpr_count: 22 .sgpr_spill_count: 0 .symbol: _ZL8sayHellov.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 34 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "e813c08b4cb1d77e65f076469758fdaa895b7c04.hip" .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $80, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -16 movl $.L.str, %edi callq puts xorl %ebx, %ebx leaq 12(%rsp), %rsi movl $.L.str.1, %edi xorl %eax, %eax callq __isoc23_scanf movl $.L.str.2, %edi callq puts leaq 8(%rsp), %rsi movl $.L.str.1, %edi xorl %eax, %eax callq __isoc23_scanf movl $.L.str.3, %edi callq puts movl 12(%rsp), %edi movl 8(%rsp), %edx movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi orq %rax, %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB0_2 # %bb.1: leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 64(%rsp), %r9 movl $_ZL8sayHellov, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB0_2: callq hipDeviceReset testl %eax, %eax jne .LBB0_3 .LBB0_4: movl %ebx, %eax addq $80, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .LBB0_3: .cfi_def_cfa_offset 96 movq stderr(%rip), %rcx movl $.L.str.4, %edi movl $22, %esi movl $1, %edx callq fwrite@PLT movl $1, %ebx jmp .LBB0_4 .Lfunc_end0: .size main, .Lfunc_end0-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function _ZL23__device_stub__sayHellov .type _ZL23__device_stub__sayHellov,@function _ZL23__device_stub__sayHellov: # @_ZL23__device_stub__sayHellov .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_ZL8sayHellov, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end1: .size _ZL23__device_stub__sayHellov, .Lfunc_end1-_ZL23__device_stub__sayHellov .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_ZL8sayHellov, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Please enter the grid size: " .size .L.str, 29 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "%d" .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "\nPlease enter the threads per block: " .size .L.str.2, 38 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "\n" .size .L.str.3, 2 .type _ZL8sayHellov,@object # @_ZL8sayHellov .section .rodata,"a",@progbits .p2align 3, 0x0 _ZL8sayHellov: .quad _ZL23__device_stub__sayHellov .size _ZL8sayHellov, 8 .type .L.str.4,@object # @.str.4 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.4: .asciz "hipDeviceReset failed!" .size .L.str.4, 23 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_ZL8sayHellov" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _ZL23__device_stub__sayHellov .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _ZL8sayHellov .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
558
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code for sm_80 Function : _Z13coarse_reducePfS_S_S_iPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R14, SR_TID.X ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R4, R14, R3, c[0x0][0x170] ; IMAD.WIDE R6, R14.reuse, R3, c[0x0][0x178] ; LDG.E R8, [R4.64] ; LDG.E R0, [R6.64] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; SHF.R.S32.HI R15, RZ, 0x1f, R14 ; IMAD.SHL.U32 R2, R14, 0x4, RZ ; SHF.R.U32.HI R9, RZ, 0x1, R9 ; IMAD R3, R3, c[0x0][0x0], R2 ; ISETP.GE.AND P0, PT, R9, c[0x0][0x180], PT ; STS [R14.X4], R8 ; STS [R3], R0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P0 BRA 0x250 ; ISETP.GE.AND P0, PT, R14, R9, PT ; BSSY B0, 0x200 ; @P0 BRA 0x1f0 ; IMAD R10, R9.reuse, 0x4, R2 ; LDS R11, [R14.X4] ; IMAD R13, R9, 0x4, R3 ; LDS R10, [R10] ; FADD R11, R11, R10 ; STS [R14.X4], R11 ; LDS R13, [R13] ; LDS R12, [R3] ; FADD R12, R12, R13 ; STS [R3], R12 ; BSYNC B0 ; LEA.HI R9, R9, R9, RZ, 0x1 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; SHF.R.S32.HI R9, RZ, 0x1, R9 ; ISETP.GE.AND P0, PT, R9, c[0x0][0x180], PT ; @P0 BRA 0x120 ; ISETP.GE.AND P0, PT, R14, c[0x0][0x180], PT ; @P0 EXIT ; IMAD.SHL.U32 R10, R14.reuse, 0x4, RZ ; SHF.L.U64.HI R9, R14, 0x2, R15 ; IADD3 R2, P0, R10, c[0x0][0x188], RZ ; IADD3.X R3, R9, c[0x0][0x18c], RZ, P0, !PT ; LDG.E R11, [R2.64] ; BSSY B0, 0x3b0 ; IMNMX R11, R11, 0x1, !PT ; I2F R11, R11 ; MUFU.RCP R12, R11 ; FCHK P0, R8, R11 ; FFMA R13, -R11, R12, 1 ; FFMA R13, R12, R13, R12 ; FFMA R12, R8, R13, RZ ; FFMA R14, -R11, R12, R8 ; FFMA R15, R13, R14, R12 ; @!P0 BRA 0x3a0 ; IMAD.MOV.U32 R16, RZ, RZ, R8 ; MOV R8, 0x3a0 ; CALL.REL.NOINC 0x530 ; BSYNC B0 ; MUFU.RCP R8, R11 ; IADD3 R12, P0, R10, c[0x0][0x160], RZ ; BSSY B0, 0x4c0 ; IADD3.X R13, R9, c[0x0][0x164], RZ, P0, !PT ; STG.E [R12.64], R15 ; FCHK P0, R0, R11 ; FFMA R17, -R11, R8, 1 ; FFMA R19, R8, R17, R8 ; FFMA R8, R0, R19, RZ ; FFMA R17, -R11, R8, R0 ; FFMA R17, R19, R17, R8 ; @!P0 BRA 0x4b0 ; IMAD.MOV.U32 R16, RZ, RZ, R0 ; MOV R8, 0x4a0 ; CALL.REL.NOINC 0x530 ; IMAD.MOV.U32 R17, RZ, RZ, R15 ; BSYNC B0 ; IADD3 R10, P0, R10, c[0x0][0x168], RZ ; IADD3.X R11, R9, c[0x0][0x16c], RZ, P0, !PT ; STG.E [R10.64], R17 ; STG.E [R6.64], RZ ; STG.E [R4.64], RZ ; STG.E [R2.64], RZ ; EXIT ; SHF.R.U32.HI R14, RZ, 0x17, R11.reuse ; BSSY B1, 0xb90 ; SHF.R.U32.HI R12, RZ, 0x17, R16 ; IMAD.MOV.U32 R15, RZ, RZ, R11 ; LOP3.LUT R14, R14, 0xff, RZ, 0xc0, !PT ; LOP3.LUT R17, R12, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R12, RZ, RZ, R16 ; IADD3 R19, R14, -0x1, RZ ; IADD3 R18, R17, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R19, 0xfd, PT ; ISETP.GT.U32.OR P0, PT, R18, 0xfd, P0 ; @!P0 IMAD.MOV.U32 R13, RZ, RZ, RZ ; @!P0 BRA 0x770 ; FSETP.GTU.FTZ.AND P0, PT, |R16|, +INF , PT ; FSETP.GTU.FTZ.AND P1, PT, |R11|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0xb70 ; LOP3.LUT P0, RZ, R15, 0x7fffffff, R12, 0xc8, !PT ; @!P0 BRA 0xb50 ; FSETP.NEU.FTZ.AND P2, PT, |R16|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P1, PT, |R11|, +INF , PT ; FSETP.NEU.FTZ.AND P0, PT, |R16|, +INF , PT ; @!P1 BRA !P2, 0xb50 ; LOP3.LUT P2, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; @P1 BRA 0xb30 ; LOP3.LUT P1, RZ, R15, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; @P0 BRA 0xb00 ; ISETP.GE.AND P0, PT, R18, RZ, PT ; ISETP.GE.AND P1, PT, R19, RZ, PT ; @P0 IMAD.MOV.U32 R13, RZ, RZ, RZ ; @!P0 IMAD.MOV.U32 R13, RZ, RZ, -0x40 ; @!P0 FFMA R12, R16, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R15, R11, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R13, R13, 0x40, RZ ; LEA R16, R14, 0xc0800000, 0x17 ; BSSY B2, 0xaf0 ; IADD3 R17, R17, -0x7f, RZ ; IMAD.IADD R16, R15, 0x1, -R16 ; IMAD R12, R17.reuse, -0x800000, R12 ; MUFU.RCP R15, R16 ; FADD.FTZ R19, -R16, -RZ ; IADD3 R16, R17, 0x7f, -R14 ; IMAD.IADD R13, R16, 0x1, R13 ; FFMA R18, R15, R19, 1 ; FFMA R15, R15, R18, R15 ; FFMA R18, R12, R15, RZ ; FFMA R20, R19, R18, R12 ; FFMA R20, R15, R20, R18 ; FFMA R19, R19, R20, R12 ; FFMA R12, R15, R19, R20 ; SHF.R.U32.HI R14, RZ, 0x17, R12 ; LOP3.LUT R14, R14, 0xff, RZ, 0xc0, !PT ; IMAD.IADD R17, R14, 0x1, R13 ; IADD3 R14, R17, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R14, 0xfe, PT ; @!P0 BRA 0xad0 ; ISETP.GT.AND P0, PT, R17, 0xfe, PT ; @P0 BRA 0xaa0 ; ISETP.GE.AND P0, PT, R17, 0x1, PT ; @P0 BRA 0xae0 ; ISETP.GE.AND P0, PT, R17, -0x18, PT ; LOP3.LUT R12, R12, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0xae0 ; FFMA.RZ R13, R15, R19.reuse, R20.reuse ; ISETP.NE.AND P2, PT, R17, RZ, PT ; FFMA.RM R14, R15, R19.reuse, R20.reuse ; ISETP.NE.AND P1, PT, R17, RZ, PT ; LOP3.LUT R16, R13, 0x7fffff, RZ, 0xc0, !PT ; FFMA.RP R13, R15, R19, R20 ; IADD3 R15, R17, 0x20, RZ ; IMAD.MOV R17, RZ, RZ, -R17 ; LOP3.LUT R16, R16, 0x800000, RZ, 0xfc, !PT ; FSETP.NEU.FTZ.AND P0, PT, R13, R14, PT ; SHF.L.U32 R15, R16, R15, RZ ; SEL R13, R17, RZ, P2 ; ISETP.NE.AND P1, PT, R15, RZ, P1 ; SHF.R.U32.HI R13, RZ, R13, R16 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R15, RZ, 0x1, R13 ; SEL R14, RZ, 0x1, !P0 ; LOP3.LUT R14, R14, 0x1, R15, 0xf8, !PT ; LOP3.LUT R14, R14, R13, RZ, 0xc0, !PT ; IMAD.IADD R15, R15, 0x1, R14 ; LOP3.LUT R12, R15, R12, RZ, 0xfc, !PT ; BRA 0xae0 ; LOP3.LUT R12, R12, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R12, R12, 0x7f800000, RZ, 0xfc, !PT ; BRA 0xae0 ; IMAD R12, R13, 0x800000, R12 ; BSYNC B2 ; BRA 0xb80 ; LOP3.LUT R12, R15, 0x80000000, R12, 0x48, !PT ; LOP3.LUT R12, R12, 0x7f800000, RZ, 0xfc, !PT ; BRA 0xb80 ; LOP3.LUT R12, R15, 0x80000000, R12, 0x48, !PT ; BRA 0xb80 ; MUFU.RSQ R12, -QNAN ; BRA 0xb80 ; FADD.FTZ R12, R16, R11 ; BSYNC B1 ; IMAD.MOV.U32 R15, RZ, RZ, R12 ; IMAD.MOV.U32 R12, RZ, RZ, R8 ; IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; RET.REL.NODEC R12 0x0 ; BRA 0xbd0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R6, R0, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; @P0 EXIT ; ISETP.GE.AND P0, PT, R3, c[0x0][0x198], PT ; HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; @!P0 IMAD.WIDE R4, R3, R2, c[0x0][0x178] ; @!P0 IMAD.WIDE R8, R3.reuse, R2.reuse, c[0x0][0x180] ; @!P0 LDG.E.CONSTANT R4, [R4.64] ; IMAD.WIDE R10, R6.reuse, R2.reuse, c[0x0][0x160] ; @!P0 LDG.E.CONSTANT R8, [R8.64] ; IMAD.WIDE R6, R6, R2, c[0x0][0x168] ; LDG.E.CONSTANT R16, [R10.64] ; LDG.E.CONSTANT R7, [R6.64] ; IMAD.SHL.U32 R17, R3, 0x4, RZ ; IMAD.MOV.U32 R19, RZ, RZ, -0x1 ; @!P0 IMAD R13, R2, c[0x0][0x198], R17 ; MOV R2, c[0x0][0x198] ; ISETP.GE.AND P1, PT, R2, 0x1, PT ; @!P0 STS [R3.X4], R4 ; @!P0 STS [R13], R8 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P1 BRA 0x13b0 ; IADD3 R4, R2.reuse, -0x1, RZ ; IMAD.MOV.U32 R18, RZ, RZ, 0x7f7fffff ; LOP3.LUT R6, R2, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; MOV R19, 0xffffffff ; MOV R4, RZ ; @!P0 BRA 0x1270 ; IADD3 R5, -R6, c[0x0][0x198], RZ ; IMAD.MOV.U32 R18, RZ, RZ, 0x7f7fffff ; MOV R19, 0xffffffff ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; ISETP.GT.AND P0, PT, R5, RZ, PT ; @!P0 BRA 0x1000 ; ISETP.GT.AND P2, PT, R5, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0xb50 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; SHF.L.U32 R21, R4, 0x2, RZ ; IADD3 R5, R5, -0x10, RZ ; IMAD R20, R2, 0x4, R21 ; LDS.128 R12, [R21] ; LDS R8, [R20] ; LDS R26, [R20+0x4] ; LDS R22, [R20+0x8] ; LDS R24, [R20+0xc] ; FADD R13, R16, -R13 ; FADD R14, R16.reuse, -R14 ; FADD R9, R7, -R8 ; FADD R8, R16, -R12 ; FMUL R9, R9, R9 ; LDS R12, [R20+0x10] ; FADD R26, R7, -R26 ; FFMA R23, R8, R8, R9 ; LDS.128 R8, [R21+0x10] ; FMUL R26, R26, R26 ; FSETP.GEU.AND P6, PT, R23, R18.reuse, PT ; FADD R15, R16, -R15 ; FFMA R26, R13, R13, R26 ; FSEL R23, R23, R18, !P6 ; FADD R13, R7, -R22 ; LDS R18, [R20+0x14] ; SEL R19, R4, R19, !P6 ; FMUL R13, R13, R13 ; LDS R22, [R20+0x18] ; FSETP.GEU.AND P5, PT, R26, R23.reuse, PT ; FFMA R13, R14, R14, R13 ; FADD R14, R7, -R24 ; FSEL R26, R26, R23, !P5 ; LDS R24, [R20+0x1c] ; FMUL R14, R14, R14 ; FSETP.GEU.AND P4, PT, R13, R26, PT ; FFMA R14, R15, R15, R14 ; FSEL R13, R13, R26, !P4 ; @!P5 IADD3 R19, R4, 0x1, RZ ; FSETP.GEU.AND P2, PT, R14, R13, PT ; FADD R12, R7, -R12 ; FSEL R23, R14, R13, !P2 ; @!P4 IADD3 R19, R4, 0x2, RZ ; FMUL R15, R12, R12 ; FADD R8, R16.reuse, -R8 ; FADD R9, R16, -R9 ; @!P2 IADD3 R19, R4, 0x3, RZ ; FFMA R26, R8, R8, R15 ; LDS R8, [R20+0x20] ; FADD R10, R16, -R10 ; FSETP.GEU.AND P3, PT, R26.reuse, R23.reuse, PT ; LDS.128 R12, [R21+0x20] ; FADD R18, R7.reuse, -R18 ; FSEL R23, R26, R23, !P3 ; FADD R22, R7, -R22 ; FMUL R26, R18, R18 ; LDS R18, [R20+0x24] ; FADD R24, R7, -R24 ; FFMA R26, R9, R9, R26 ; @!P3 IADD3 R19, R4, 0x4, RZ ; FMUL R9, R22, R22 ; LDS R22, [R20+0x28] ; FSETP.GEU.AND P6, PT, R26, R23.reuse, PT ; FFMA R9, R10, R10, R9 ; FMUL R24, R24, R24 ; FSEL R26, R26, R23, !P6 ; FADD R11, R16, -R11 ; FSETP.GEU.AND P5, PT, R9, R26.reuse, PT ; FFMA R10, R11, R11, R24 ; LDS R24, [R20+0x2c] ; FSEL R9, R9, R26, !P5 ; @!P6 IADD3 R19, R4, 0x5, RZ ; LDS R26, [R20+0x30] ; FSETP.GEU.AND P4, PT, R10, R9, PT ; FSEL R23, R10, R9, !P4 ; FADD R27, R7, -R8 ; @!P5 IADD3 R19, R4, 0x6, RZ ; LDS.128 R8, [R21+0x30] ; FADD R25, R16.reuse, -R12 ; FMUL R28, R27, R27 ; LDS R12, [R20+0x34] ; FADD R13, R16, -R13 ; @!P4 IADD3 R19, R4, 0x7, RZ ; FFMA R28, R25, R25, R28 ; FADD R25, R7, -R18 ; LDS R18, [R20+0x38] ; FSETP.GEU.AND P2, PT, R28, R23, PT ; FMUL R25, R25, R25 ; FADD R14, R16, -R14 ; FSEL R23, R28, R23, !P2 ; FFMA R28, R13, R13, R25 ; FADD R13, R7, -R22 ; LDS R22, [R20+0x3c] ; FSETP.GEU.AND P3, PT, R28, R23, PT ; FMUL R13, R13, R13 ; FADD R15, R16, -R15 ; FSEL R23, R28, R23, !P3 ; FFMA R14, R14, R14, R13 ; @!P2 IADD3 R19, R4, 0x8, RZ ; FADD R24, R7, -R24 ; FSETP.GEU.AND P6, PT, R14, R23.reuse, PT ; FMUL R24, R24, R24 ; FADD R26, R7, -R26 ; FSEL R14, R14, R23, !P6 ; FFMA R15, R15, R15, R24 ; @!P3 IADD3 R19, R4, 0x9, RZ ; FMUL R13, R26, R26 ; FADD R8, R16.reuse, -R8 ; FSETP.GEU.AND P5, PT, R15, R14, PT ; FADD R9, R16, -R9 ; FADD R12, R7, -R12 ; FSEL R14, R15, R14, !P5 ; FFMA R13, R8, R8, R13 ; @!P6 IADD3 R19, R4, 0xa, RZ ; FMUL R12, R12, R12 ; FADD R18, R7, -R18 ; FSETP.GEU.AND P4, PT, R13, R14.reuse, PT ; FFMA R12, R9, R9, R12 ; FADD R10, R16, -R10 ; FSEL R13, R13, R14, !P4 ; FMUL R9, R18, R18 ; @!P5 IADD3 R19, R4, 0xb, RZ ; FADD R11, R16, -R11 ; FSETP.GEU.AND P2, PT, R12, R13, PT ; FFMA R9, R10, R10, R9 ; FADD R22, R7, -R22 ; FSEL R12, R12, R13, !P2 ; @!P4 IADD3 R19, R4, 0xc, RZ ; FMUL R22, R22, R22 ; FSETP.GEU.AND P3, PT, R9, R12, PT ; FFMA R22, R11, R11, R22 ; FSEL R9, R9, R12, !P3 ; @!P2 IADD3 R19, R4, 0xd, RZ ; ISETP.GT.AND P2, PT, R5, 0xc, PT ; FSETP.GEU.AND P5, PT, R22, R9, PT ; @!P3 IADD3 R19, R4, 0xe, RZ ; FSEL R18, R22, R9, !P5 ; @!P5 IADD3 R19, R4.reuse, 0xf, RZ ; IADD3 R4, R4, 0x10, RZ ; @P2 BRA 0x2b0 ; ISETP.GT.AND P2, PT, R5, 0x4, PT ; @!P2 BRA 0xfe0 ; SHF.L.U32 R23, R4, 0x2, RZ ; IADD3 R5, R5, -0x8, RZ ; IMAD R21, R2, 0x4, R23 ; LDS.128 R8, [R23] ; LDS R28, [R21] ; LDS R26, [R21+0x4] ; LDS R24, [R21+0x8] ; LDS R20, [R21+0xc] ; LDS R22, [R21+0x10] ; LDS.128 R12, [R23+0x10] ; FADD R25, R16, -R8 ; LDS R8, [R21+0x14] ; FADD R9, R16.reuse, -R9 ; FADD R28, R7.reuse, -R28 ; FADD R10, R16, -R10 ; FMUL R28, R28, R28 ; FADD R27, R7, -R26 ; FFMA R25, R25, R25, R28 ; LDS R26, [R21+0x18] ; FMUL R28, R27, R27 ; FADD R23, R7, -R24 ; FSETP.GEU.AND P5, PT, R25, R18.reuse, PT ; FFMA R9, R9, R9, R28 ; LDS R24, [R21+0x1c] ; FMUL R23, R23, R23 ; FSEL R18, R25, R18, !P5 ; FADD R20, R7, -R20 ; SEL R19, R4, R19, !P5 ; FFMA R10, R10, R10, R23 ; FSETP.GEU.AND P6, PT, R9, R18, PT ; FADD R11, R16, -R11 ; FMUL R20, R20, R20 ; FSEL R9, R9, R18, !P6 ; FADD R22, R7, -R22 ; FFMA R20, R11, R11, R20 ; FSETP.GEU.AND P4, PT, R10, R9.reuse, PT ; FADD R12, R16, -R12 ; FMUL R11, R22, R22 ; FSEL R9, R10, R9, !P4 ; FADD R13, R16, -R13 ; @!P6 IADD3 R19, R4, 0x1, RZ ; FFMA R12, R12, R12, R11 ; FSETP.GEU.AND P3, PT, R20, R9, PT ; FADD R8, R7, -R8 ; FADD R14, R16, -R14 ; FSEL R9, R20, R9, !P3 ; FMUL R8, R8, R8 ; @!P4 IADD3 R19, R4, 0x2, RZ ; FADD R15, R16, -R15 ; FSETP.GEU.AND P0, PT, R12.reuse, R9, PT ; FFMA R8, R13, R13, R8 ; FADD R26, R7.reuse, -R26 ; FSEL R9, R12, R9, !P0 ; @!P3 IADD3 R19, R4, 0x3, RZ ; FMUL R11, R26, R26 ; FSETP.GEU.AND P2, PT, R8, R9, PT ; FADD R24, R7, -R24 ; FFMA R11, R14, R14, R11 ; FSEL R8, R8, R9, !P2 ; FMUL R24, R24, R24 ; @!P0 IADD3 R19, R4.reuse, 0x4, RZ ; FSETP.GEU.AND P5, PT, R11, R8.reuse, PT ; FFMA R15, R15, R15, R24 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; FSEL R8, R11, R8, !P5 ; @!P2 IADD3 R19, R4, 0x5, RZ ; FSETP.GEU.AND P3, PT, R15, R8, PT ; FSEL R18, R15, R8, !P3 ; @!P5 IADD3 R19, R4, 0x6, RZ ; @!P3 IADD3 R19, R4.reuse, 0x7, RZ ; IADD3 R4, R4, 0x8, RZ ; ISETP.NE.OR P0, PT, R5, RZ, P0 ; @!P0 BRA 0x1270 ; SHF.L.U32 R11, R4, 0x2, RZ ; IADD3 R5, R5, -0x4, RZ ; IMAD R15, R2, 0x4, R11 ; LDS.128 R8, [R11] ; LDS R14, [R15] ; LDS R20, [R15+0x4] ; LDS R22, [R15+0x8] ; LDS R12, [R15+0xc] ; FADD R8, R16, -R8 ; FADD R9, R16.reuse, -R9 ; FADD R14, R7.reuse, -R14 ; FADD R10, R16, -R10 ; FMUL R13, R14, R14 ; FADD R20, R7, -R20 ; FFMA R13, R8, R8, R13 ; FMUL R20, R20, R20 ; FADD R22, R7, -R22 ; FSETP.GEU.AND P0, PT, R13, R18, PT ; FFMA R20, R9, R9, R20 ; FMUL R9, R22, R22 ; FSEL R13, R13, R18, !P0 ; FADD R12, R7, -R12 ; SEL R19, R4, R19, !P0 ; FFMA R10, R10, R10, R9 ; FSETP.GEU.AND P2, PT, R20, R13.reuse, PT ; FADD R11, R16, -R11 ; ISETP.NE.AND P0, PT, R5, RZ, PT ; FMUL R12, R12, R12 ; FSEL R13, R20, R13, !P2 ; FFMA R11, R11, R11, R12 ; FSETP.GEU.AND P3, PT, R10, R13, PT ; FSEL R10, R10, R13, !P3 ; @!P2 IADD3 R19, R4, 0x1, RZ ; FSETP.GEU.AND P4, PT, R11, R10, PT ; FSEL R18, R11, R10, !P4 ; @!P3 IADD3 R19, R4, 0x2, RZ ; @!P4 IADD3 R19, R4.reuse, 0x3, RZ ; IADD3 R4, R4, 0x4, RZ ; @P0 BRA 0x1000 ; ISETP.NE.AND P0, PT, R6, RZ, PT ; @!P0 BRA 0x13b0 ; IADD3 R2, R4.reuse, c[0x0][0x198], RZ ; SHF.L.U32 R5, R4, 0x2, RZ ; IMAD.SHL.U32 R2, R2, 0x4, RZ ; LDS R8, [R2] ; IADD3 R6, R6, -0x1, RZ ; LDS R9, [R5] ; ISETP.NE.AND P2, PT, R6, RZ, PT ; IADD3 R2, R2, 0x4, RZ ; IADD3 R5, R5, 0x4, RZ ; FADD R8, R7, -R8 ; FADD R9, R16, -R9 ; FMUL R8, R8, R8 ; FFMA R9, R9, R9, R8 ; FSETP.GEU.AND P0, PT, R9, R18, PT ; SEL R19, R4.reuse, R19, !P0 ; FSEL R18, R9, R18, !P0 ; IADD3 R4, R4, 0x1, RZ ; @P2 BRA 0x12c0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P1 EXIT ; MOV R6, c[0x0][0x0] ; HFMA2.MMA R4, -RZ, RZ, 0, 0 ; SHF.R.U32.HI R5, RZ, 0x1, R6 ; IMAD R2, R6, 0x4, R17 ; IMAD R6, R6, 0x4, R2 ; ISETP.NE.AND P0, PT, R19, R4, PT ; FSEL R8, R16, RZ, !P0 ; FSEL R9, R7, RZ, !P0 ; FSEL R11, RZ, 1, P0 ; STS [R3.X4], R8 ; ISETP.NE.AND P0, PT, R5, RZ, PT ; STS [R2], R9 ; STS [R6], R11 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P0 BRA 0x1650 ; MOV R8, R5 ; ISETP.GE.AND P0, PT, R3, R8, PT ; BSSY B0, 0x1610 ; @P0 BRA 0x1600 ; IMAD R9, R8, 0x4, R17 ; LDS R10, [R3.X4] ; MOV R14, c[0x0][0x0] ; LDS R11, [R9] ; FADD R10, R10, R11 ; IMAD R11, R14, 0x4, R9 ; STS [R3.X4], R10 ; LDS R12, [R2] ; LDS R13, [R11] ; FADD R13, R12, R13 ; LEA R12, R14, R11, 0x2 ; STS [R2], R13 ; LDS R12, [R12] ; LDS R9, [R6] ; FADD R9, R9, R12 ; STS [R6], R9 ; BSYNC B0 ; SHF.R.U32.HI R8, RZ, 0x1, R8 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.AND P0, PT, R8, RZ, PT ; @P0 BRA 0x14d0 ; ISETP.NE.AND P0, PT, R3, RZ, PT ; BSSY B0, 0x1750 ; @P0 BRA 0x1740 ; LDS R14, [R6] ; IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; IMAD R12, R0, c[0x0][0x198], R4 ; LDS R15, [RZ] ; IMAD.WIDE R8, R12.reuse, R13.reuse, c[0x0][0x188] ; LDS R21, [R2] ; IMAD.WIDE R10, R12, R13, c[0x0][0x190] ; IMAD.WIDE R12, R12, R13, c[0x0][0x1a0] ; F2I.TRUNC.NTZ R23, R14 ; STG.E [R8.64], R15 ; STG.E [R10.64], R21 ; STG.E [R12.64], R23 ; BSYNC B0 ; IADD3 R4, R4, 0x1, RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P0, PT, R4, c[0x0][0x198], PT ; @!P0 BRA 0x1420 ; EXIT ; BRA 0x17a0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00052ed9_00000000-6_c2f0926ca82a9e2897df7a76c67abf5de6c6ff93.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB5287: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE5287: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .text._ZN4DataC2EiRSt6vectorIfSaIfEES3_,"axG",@progbits,_ZN4DataC5EiRSt6vectorIfSaIfEES3_,comdat .align 2 .weak _ZN4DataC2EiRSt6vectorIfSaIfEES3_ .type _ZN4DataC2EiRSt6vectorIfSaIfEES3_, @function _ZN4DataC2EiRSt6vectorIfSaIfEES3_: .LFB5261: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rdx, %r12 movq %rcx, %rbp movq $0, (%rdi) movq $0, 8(%rdi) movl %esi, 16(%rdi) sall $2, %esi movl %esi, 20(%rdi) movslq %esi, %rsi call cudaMalloc@PLT movslq 20(%rbx), %rsi leaq 8(%rbx), %rdi call cudaMalloc@PLT movslq 20(%rbx), %rdx movq (%r12), %rsi movq (%rbx), %rdi movl $1, %ecx call cudaMemcpy@PLT movslq 20(%rbx), %rdx movq 0(%rbp), %rsi movq 8(%rbx), %rdi movl $1, %ecx call cudaMemcpy@PLT popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE5261: .size _ZN4DataC2EiRSt6vectorIfSaIfEES3_, .-_ZN4DataC2EiRSt6vectorIfSaIfEES3_ .weak _ZN4DataC1EiRSt6vectorIfSaIfEES3_ .set _ZN4DataC1EiRSt6vectorIfSaIfEES3_,_ZN4DataC2EiRSt6vectorIfSaIfEES3_ .section .text._ZN4DataD2Ev,"axG",@progbits,_ZN4DataD5Ev,comdat .align 2 .weak _ZN4DataD2Ev .type _ZN4DataD2Ev, @function _ZN4DataD2Ev: .LFB5264: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA5264 endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx movq (%rdi), %rdi call cudaFree@PLT movq 8(%rbx), %rdi call cudaFree@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE5264: .globl __gxx_personality_v0 .section .gcc_except_table._ZN4DataD2Ev,"aG",@progbits,_ZN4DataD5Ev,comdat .LLSDA5264: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE5264-.LLSDACSB5264 .LLSDACSB5264: .LLSDACSE5264: .section .text._ZN4DataD2Ev,"axG",@progbits,_ZN4DataD5Ev,comdat .size _ZN4DataD2Ev, .-_ZN4DataD2Ev .weak _ZN4DataD1Ev .set _ZN4DataD1Ev,_ZN4DataD2Ev .text .globl _Z19squared_l2_distanceffff .type _Z19squared_l2_distanceffff, @function _Z19squared_l2_distanceffff: .LFB5266: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE5266: .size _Z19squared_l2_distanceffff, .-_Z19squared_l2_distanceffff .globl _Z50__device_stub__Z11fine_reducePKfS0_iS0_S0_PfS1_iPiPKfS0_iS0_S0_PfS1_iPi .type _Z50__device_stub__Z11fine_reducePKfS0_iS0_S0_PfS1_iPiPKfS0_iS0_S0_PfS1_iPi, @function _Z50__device_stub__Z11fine_reducePKfS0_iS0_S0_PfS1_iPiPKfS0_iS0_S0_PfS1_iPi: .LFB5309: .cfi_startproc endbr64 subq $232, %rsp .cfi_def_cfa_offset 240 movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 216(%rsp) xorl %eax, %eax movq %rdi, 24(%rsp) leaq 24(%rsp), %rax movq %rax, 144(%rsp) movq %rsi, 32(%rsp) leaq 32(%rsp), %rax movq %rax, 152(%rsp) leaq 12(%rsp), %rax movq %rax, 160(%rsp) movq %rcx, 40(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) movq %r8, 48(%rsp) leaq 48(%rsp), %rax movq %rax, 176(%rsp) movq %r9, 56(%rsp) leaq 56(%rsp), %rax movq %rax, 184(%rsp) movq 240(%rsp), %rax movq %rax, 64(%rsp) leaq 64(%rsp), %rax movq %rax, 192(%rsp) leaq 248(%rsp), %rax movq %rax, 200(%rsp) movq 256(%rsp), %rax movq %rax, 72(%rsp) leaq 72(%rsp), %rax movq %rax, 208(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) movl $1, 104(%rsp) movl $1, 108(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) leaq 88(%rsp), %rcx leaq 80(%rsp), %rdx leaq 108(%rsp), %rsi leaq 96(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L13 .L9: movq 216(%rsp), %rax subq %fs:40, %rax jne .L14 addq $232, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L13: .cfi_restore_state pushq 88(%rsp) .cfi_def_cfa_offset 248 pushq 88(%rsp) .cfi_def_cfa_offset 256 leaq 160(%rsp), %r9 movq 124(%rsp), %rcx movl 132(%rsp), %r8d movq 112(%rsp), %rsi movl 120(%rsp), %edx leaq _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 240 jmp .L9 .L14: call __stack_chk_fail@PLT .cfi_endproc .LFE5309: .size _Z50__device_stub__Z11fine_reducePKfS0_iS0_S0_PfS1_iPiPKfS0_iS0_S0_PfS1_iPi, .-_Z50__device_stub__Z11fine_reducePKfS0_iS0_S0_PfS1_iPiPKfS0_iS0_S0_PfS1_iPi .globl _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi .type _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi, @function _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi: .LFB5310: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 pushq 40(%rsp) .cfi_def_cfa_offset 32 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 pushq 40(%rsp) .cfi_def_cfa_offset 48 call _Z50__device_stub__Z11fine_reducePKfS0_iS0_S0_PfS1_iPiPKfS0_iS0_S0_PfS1_iPi addq $40, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE5310: .size _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi, .-_Z11fine_reducePKfS0_iS0_S0_PfS1_iPi .globl _Z42__device_stub__Z13coarse_reducePfS_S_S_iPiPfS_S_S_iPi .type _Z42__device_stub__Z13coarse_reducePfS_S_S_iPiPfS_S_S_iPi, @function _Z42__device_stub__Z13coarse_reducePfS_S_S_iPiPfS_S_S_iPi: .LFB5311: .cfi_startproc endbr64 subq $200, %rsp .cfi_def_cfa_offset 208 movl %r8d, 12(%rsp) movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax movq %rdi, 24(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) movq %rsi, 32(%rsp) leaq 32(%rsp), %rax movq %rax, 136(%rsp) movq %rdx, 40(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) movq %rcx, 48(%rsp) leaq 48(%rsp), %rax movq %rax, 152(%rsp) leaq 12(%rsp), %rax movq %rax, 160(%rsp) movq %r9, 56(%rsp) leaq 56(%rsp), %rax movq %rax, 168(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L21 .L17: movq 184(%rsp), %rax subq %fs:40, %rax jne .L22 addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L21: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 216 pushq 72(%rsp) .cfi_def_cfa_offset 224 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z13coarse_reducePfS_S_S_iPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 208 jmp .L17 .L22: call __stack_chk_fail@PLT .cfi_endproc .LFE5311: .size _Z42__device_stub__Z13coarse_reducePfS_S_S_iPiPfS_S_S_iPi, .-_Z42__device_stub__Z13coarse_reducePfS_S_S_iPiPfS_S_S_iPi .globl _Z13coarse_reducePfS_S_S_iPi .type _Z13coarse_reducePfS_S_S_iPi, @function _Z13coarse_reducePfS_S_S_iPi: .LFB5312: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z42__device_stub__Z13coarse_reducePfS_S_S_iPiPfS_S_S_iPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE5312: .size _Z13coarse_reducePfS_S_S_iPi, .-_Z13coarse_reducePfS_S_S_iPi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z13coarse_reducePfS_S_S_iPi" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "_Z11fine_reducePKfS0_iS0_S0_PfS1_iPi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB5314: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z13coarse_reducePfS_S_S_iPi(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE5314: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat .align 2 .weak _ZNSt6vectorIfSaIfEED2Ev .type _ZNSt6vectorIfSaIfEED2Ev, @function _ZNSt6vectorIfSaIfEED2Ev: .LFB5688: .cfi_startproc endbr64 movq (%rdi), %rax testq %rax, %rax je .L30 subq $8, %rsp .cfi_def_cfa_offset 16 movq 16(%rdi), %rsi subq %rax, %rsi movq %rax, %rdi call _ZdlPvm@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .L30: ret .cfi_endproc .LFE5688: .size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev .weak _ZNSt6vectorIfSaIfEED1Ev .set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev .section .rodata._ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.str1.8,"aMS",@progbits,1 .align 8 .LC2: .string "cannot create std::vector larger than max_size()" .section .text._ZNSt6vectorIfSaIfEEC2EmRKfRKS0_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC5EmRKfRKS0_,comdat .align 2 .weak _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_ .type _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_, @function _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_: .LFB5735: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rsi, %rax shrq $61, %rax jne .L41 movq %rdi, %rbx movq %rdx, %rbp movq $0, (%rdi) movq $0, 8(%rdi) movq $0, 16(%rdi) testq %rsi, %rsi je .L35 leaq 0(,%rsi,4), %r12 movq %r12, %rdi call _Znwm@PLT movq %rax, (%rbx) leaq (%rax,%r12), %rdx movq %rdx, 16(%rbx) movss 0(%rbp), %xmm0 .L36: movss %xmm0, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L36 .L37: movq %rdx, 8(%rbx) popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L41: .cfi_restore_state leaq .LC2(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .L35: movq $0, (%rdi) movq $0, 16(%rdi) movl $0, %edx jmp .L37 .cfi_endproc .LFE5735: .size _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_, .-_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_ .weak _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_ .set _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_,_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_ .section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat .align 2 .weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag .type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, @function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag: .LFB5829: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $16, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbx movq %rsi, %r12 movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax subq %rsi, %rdx movq %rdx, %rbp movq %rdx, (%rsp) cmpq $15, %rdx ja .L49 movq (%rdi), %rdi cmpq $1, %rdx jne .L45 movzbl (%rsi), %eax movb %al, (%rdi) .L46: movq (%rsp), %rax movq %rax, 8(%rbx) movq (%rbx), %rdx movb $0, (%rdx,%rax) movq 8(%rsp), %rax subq %fs:40, %rax jne .L50 addq $16, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L49: .cfi_restore_state movq %rsp, %rsi movl $0, %edx call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT movq %rax, %rdi movq %rax, (%rbx) movq (%rsp), %rax movq %rax, 16(%rbx) .L44: movq %rbp, %rdx movq %r12, %rsi call memcpy@PLT jmp .L46 .L45: testq %rdx, %rdx je .L46 jmp .L44 .L50: call __stack_chk_fail@PLT .cfi_endproc .LFE5829: .size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag .section .rodata._ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_.str1.1,"aMS",@progbits,1 .LC3: .string "vector::_M_realloc_insert" .section .text._ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_,comdat .align 2 .weak _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_ .type _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_, @function _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_: .LFB5947: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $24, %rsp .cfi_def_cfa_offset 80 movq %rsi, (%rsp) movq %rdx, 8(%rsp) movq 8(%rdi), %rbp movq (%rdi), %r13 movq %rbp, %rax subq %r13, %rax sarq $2, %rax movabsq $2305843009213693951, %rdx cmpq %rdx, %rax je .L68 movq %rdi, %rbx cmpq %r13, %rbp movl $1, %edx cmovne %rax, %rdx addq %rdx, %rax jc .L54 movabsq $2305843009213693951, %r14 cmpq %r14, %rax cmovbe %rax, %r14 movq (%rsp), %r15 subq %r13, %r15 movl $0, %r12d testq %rax, %rax je .L55 jmp .L62 .L68: leaq .LC3(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .L69: movq %r15, %rdx movq %r13, %rsi movq %r12, %rdi call memmove@PLT leaq 4(%r12,%r15), %r15 movq (%rsp), %rax subq %rax, %rbp testq %rbp, %rbp jg .L57 addq %rbp, %r15 movq 16(%rbx), %rsi subq %r13, %rsi jmp .L61 .L54: movq (%rsp), %r15 subq %r13, %r15 movabsq $2305843009213693951, %r14 .L62: leaq 0(,%r14,4), %rdi call _Znwm@PLT movq %rax, %r12 .L55: movq 8(%rsp), %rax movss (%rax), %xmm0 movss %xmm0, (%r12,%r15) testq %r15, %r15 jg .L69 leaq 4(%r12,%r15), %r15 movq (%rsp), %rax subq %rax, %rbp testq %rbp, %rbp jle .L59 .L57: movq %rbp, %rdx movq (%rsp), %rsi movq %r15, %rdi call memcpy@PLT .L59: addq %rbp, %r15 testq %r13, %r13 je .L60 movq 16(%rbx), %rsi subq %r13, %rsi .L61: movq %r13, %rdi call _ZdlPvm@PLT .L60: movq %r12, (%rbx) movq %r15, 8(%rbx) leaq (%r12,%r14,4), %rax movq %rax, 16(%rbx) addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE5947: .size _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_, .-_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_ .section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,comdat .align 2 .weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv .type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, @function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv: .LFB6217: .cfi_startproc endbr64 movq %rdi, %rdx leaq 1816(%rdi), %r9 movq %rdi, %rcx movl $2567483615, %r8d .L72: movq (%rcx), %rax andq $-2147483648, %rax movq 8(%rcx), %rsi andl $2147483647, %esi orq %rsi, %rax movq %rax, %rsi shrq %rsi xorq 3176(%rcx), %rsi andl $1, %eax cmovne %r8, %rax xorq %rsi, %rax movq %rax, (%rcx) addq $8, %rcx cmpq %r9, %rcx jne .L72 leaq 3168(%rdi), %r8 movl $2567483615, %esi .L74: movq 1816(%rdx), %rax andq $-2147483648, %rax movq 1824(%rdx), %rcx andl $2147483647, %ecx orq %rcx, %rax movq %rax, %rcx shrq %rcx xorq (%rdx), %rcx andl $1, %eax cmovne %rsi, %rax xorq %rcx, %rax movq %rax, 1816(%rdx) addq $8, %rdx cmpq %r8, %rdx jne .L74 movq 4984(%rdi), %rax andq $-2147483648, %rax movq (%rdi), %rdx andl $2147483647, %edx orq %rdx, %rax movq %rax, %rdx shrq %rdx xorq 3168(%rdi), %rdx andl $1, %eax movl $2567483615, %ecx cmovne %rcx, %rax xorq %rdx, %rax movq %rax, 4984(%rdi) movq $0, 4992(%rdi) ret .cfi_endproc .LFE6217: .size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv .section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat .align 2 .weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv .type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, @function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv: .LFB6117: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx cmpq $623, 4992(%rdi) ja .L81 .L79: movq 4992(%rbx), %rax leaq 1(%rax), %rdx movq %rdx, 4992(%rbx) movq (%rbx,%rax,8), %rax movq %rax, %rdx shrq $11, %rdx movl %edx, %edx xorq %rax, %rdx movq %rdx, %rax salq $7, %rax andl $2636928640, %eax xorq %rdx, %rax movq %rax, %rdx salq $15, %rdx andl $4022730752, %edx xorq %rax, %rdx movq %rdx, %rax shrq $18, %rax xorq %rdx, %rax popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L81: .cfi_restore_state call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv jmp .L79 .cfi_endproc .LFE6117: .size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv .section .text._ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE,comdat .align 2 .weak _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE .type _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE, @function _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE: .LFB5973: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %rdi, 8(%rsp) movq %rsi, %rbp movq %rdx, %r12 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movq 8(%rdx), %rbx subq (%rdx), %rbx movl $4294967294, %eax cmpq %rbx, %rax jnb .L93 movq %rbx, %rax shrq $32, %rax je .L87 movq %rbx, %r15 shrq $32, %r15 leaq 16(%rsp), %r14 .L91: movq $0, 16(%rsp) movq %r15, 24(%rsp) movq %r14, %rdx movq %rbp, %rsi movq 8(%rsp), %rdi call _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE salq $32, %rax movq %rax, %r13 movq %rbp, %rdi call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv addq %r13, %rax cmpq %rax, %rbx jb .L91 cmpq %r13, %rax jb .L91 jmp .L86 .L93: addq $1, %rbx movq %rsi, %rdi call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv imulq %rbx, %rax movq %rax, %rcx cmpl %ebx, %eax jnb .L84 movl %ebx, %eax negl %eax movl $0, %edx divl %ebx movl %edx, %r13d cmpl %edx, %ecx jnb .L84 .L85: movq %rbp, %rdi call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv imulq %rbx, %rax movq %rax, %rcx cmpl %r13d, %eax jb .L85 .L84: movq %rcx, %rax shrq $32, %rax .L86: addq (%r12), %rax movq 40(%rsp), %rdx subq %fs:40, %rdx jne .L94 addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L87: .cfi_restore_state movq %rsi, %rdi call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv jmp .L86 .L94: call __stack_chk_fail@PLT .cfi_endproc .LFE5973: .size _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE, .-_ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE .section .text._ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_,"axG",@progbits,_ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_,comdat .weak _ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_ .type _ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_, @function _ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_: .LFB5723: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax cmpq %rsi, %rdi je .L95 movq %rdi, %rbp movq %rsi, %r12 movq %rdx, %r13 movq %rsi, %rcx subq %rdi, %rcx sarq $2, %rcx movl $4294967295, %eax movl $0, %edx divq %rcx cmpq %rcx, %rax jnb .L108 movq $0, (%rsp) movq $-1, 8(%rsp) leaq 4(%rdi), %rbx cmpq %rbx, %rsi je .L95 leaq 16(%rsp), %r14 .L102: movq $0, 16(%rsp) movq %rbx, %rax subq %rbp, %rax sarq $2, %rax movq %rax, 24(%rsp) movq %rsp, %rdi movq %r14, %rdx movq %r13, %rsi call _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE leaq 0(%rbp,%rax,4), %rax movss (%rbx), %xmm0 movss (%rax), %xmm1 movss %xmm1, (%rbx) movss %xmm0, (%rax) addq $4, %rbx cmpq %rbx, %r12 jne .L102 .L95: movq 40(%rsp), %rax subq %fs:40, %rax jne .L109 addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L108: .cfi_restore_state leaq 4(%rdi), %rbx testb $1, %cl je .L110 .L99: cmpq %rbx, %r12 je .L95 leaq 16(%rsp), %r15 .L100: movq %rbx, %rax subq %rbp, %rax sarq $2, %rax leaq 2(%rax), %r14 movq $0, 16(%rsp) addq $1, %rax imulq %r14, %rax subq $1, %rax movq %rax, 24(%rsp) movq %r15, %rdx movq %r13, %rsi movq %r15, %rdi call _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE movl $0, %edx divq %r14 leaq 0(%rbp,%rax,4), %rax movss (%rbx), %xmm0 movss (%rax), %xmm1 movss %xmm1, (%rbx) movss %xmm0, (%rax) leaq 0(%rbp,%rdx,4), %rax movss 4(%rbx), %xmm0 movss (%rax), %xmm1 movss %xmm1, 4(%rbx) movss %xmm0, (%rax) addq $8, %rbx cmpq %rbx, %r12 jne .L100 jmp .L95 .L110: movq $0, 16(%rsp) movq $1, 24(%rsp) leaq 16(%rsp), %rdi movq %rdi, %rdx movq %r13, %rsi call _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE leaq 0(%rbp,%rax,4), %rax leaq 8(%rbp), %rbx movss 4(%rbp), %xmm0 movss (%rax), %xmm1 movss %xmm1, 4(%rbp) movss %xmm0, (%rax) jmp .L99 .L109: call __stack_chk_fail@PLT .cfi_endproc .LFE5723: .size _ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_, .-_ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_ .section .rodata.str1.8 .align 8 .LC4: .string "usage: k-means <data-file> <k> [iterations]" .align 8 .LC5: .string "basic_string: construction from null is not valid" .section .rodata.str1.1 .LC6: .string "default" .section .rodata.str1.8 .align 8 .LC8: .string "Standard CUDA implementation Took: " .section .rodata.str1.1 .LC9: .string "s" .LC10: .string " for " .LC11: .string " points." .LC13: .string "a" .LC14: .string "Standardtimes.txt" .LC15: .string "%0.6f\n" .LC16: .string "basic_string::append" .LC17: .string "results/standard/" .LC18: .string "_centroids.txt" .LC19: .string "w" .LC20: .string "%0.6f %0.6f\n" .text .globl main .type main, @function main: .LFB5267: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA5267 endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsp, %rbp .cfi_def_cfa_register 6 pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $4096, %rsp orq $0, (%rsp) subq $4096, %rsp orq $0, (%rsp) subq $3000, %rsp .cfi_offset 15, -24 .cfi_offset 14, -32 .cfi_offset 13, -40 .cfi_offset 12, -48 .cfi_offset 3, -56 movq %fs:40, %rax movq %rax, -56(%rbp) xorl %eax, %eax cmpl $3, %edi jle .L218 movl %edi, %r14d movq %rsi, %rbx movq 24(%rsi), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, -11208(%rbp) movl %eax, -11196(%rbp) movl $300, -11200(%rbp) cmpl $5, %r14d je .L219 .L113: movq $0, -11168(%rbp) movq $0, -11160(%rbp) movq $0, -11152(%rbp) movq $0, -11136(%rbp) movq $0, -11128(%rbp) movq $0, -11120(%rbp) movq 16(%rbx), %rsi leaq -10816(%rbp), %rdi movl $8, %edx .LEHB0: call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT .LEHE0: jmp .L220 .L218: leaq .LC4(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi .LEHB1: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT .LEHE1: movl $1, %edi call exit@PLT .L219: movq 32(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl %eax, -11200(%rbp) jmp .L113 .L220: leaq -10928(%rbp), %rax movq %rax, -10944(%rbp) movq $0, -10936(%rbp) movb $0, -10928(%rbp) movq -10816(%rbp), %rax movq -24(%rax), %rax movq -10576(%rbp,%rax), %rbx testq %rbx, %rbx je .L114 leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %r12 leaq 24+_ZTVNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r13 leaq 40(%r13), %r14 leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %r15 jmp .L115 .L229: movq %r13, -5280(%rbp) movq %r14, -5160(%rbp) movq %r15, -5264(%rbp) movq $0, -5256(%rbp) movq $0, -5248(%rbp) movq $0, -5240(%rbp) movq $0, -5232(%rbp) movq $0, -5224(%rbp) movq $0, -5216(%rbp) leaq -5208(%rbp), %rdi call _ZNSt6localeC1Ev@PLT leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax movq %rax, -5264(%rbp) movl $0, -5200(%rbp) movq -10936(%rbp), %rdx movq -10944(%rbp), %rsi leaq -5176(%rbp), %rax movq %rax, -5192(%rbp) testq %rsi, %rsi jne .L116 testq %rdx, %rdx jne .L221 .L116: addq %rsi, %rdx leaq -5192(%rbp), %rdi .LEHB2: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag jmp .L222 .L221: movq -56(%rbp), %rax subq %fs:40, %rax jne .L223 leaq .LC5(%rip), %rdi call _ZSt19__throw_logic_errorPKc@PLT .LEHE2: .L201: endbr64 movq %rax, %r14 jmp .L120 .L223: call __stack_chk_fail@PLT .L222: movl $8, -5200(%rbp) leaq -5264(%rbp), %rdi movl $0, %ecx movl $0, %edx movq -5192(%rbp), %rsi .LEHB3: call _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcmm@PLT .LEHE3: jmp .L224 .L202: endbr64 movq %rax, %r15 leaq -5192(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq %r15, %r14 .L120: leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax movq %rax, -5264(%rbp) leaq -5208(%rbp), %rdi call _ZNSt6localeD1Ev@PLT movq %r14, %rsi .L121: movq %rbx, -5280(%rbp) movq -24(%rbx), %rax movq 16+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rbx movq %rbx, -5280(%rbp,%rax) movq $0, -5272(%rbp) movq %rsi, %rbx .L125: leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax movq %rax, -5160(%rbp) leaq -5160(%rbp), %rdi call _ZNSt8ios_baseD2Ev@PLT .L126: leaq -10944(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq -10816(%rbp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT .L180: leaq -11136(%rbp), %rdi call _ZNSt6vectorIfSaIfEED1Ev leaq -11168(%rbp), %rdi call _ZNSt6vectorIfSaIfEED1Ev movq -56(%rbp), %rax subq %fs:40, %rax je .L181 call __stack_chk_fail@PLT .L224: leaq -5264(%rbp), %rsi leaq -5160(%rbp), %rdi .LEHB4: call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT .LEHE4: jmp .L225 .L200: endbr64 movq %rax, %r15 leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax movq %rax, -5264(%rbp) movq -5192(%rbp), %rdi leaq -5176(%rbp), %rax cmpq %rax, %rdi je .L124 movq -5176(%rbp), %rax leaq 1(%rax), %rsi call _ZdlPvm@PLT .L124: leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax movq %rax, -5264(%rbp) leaq -5208(%rbp), %rdi call _ZNSt6localeD1Ev@PLT movq %r15, %rsi jmp .L121 .L199: endbr64 movq %rax, %rbx jmp .L125 .L225: leaq -11008(%rbp), %rsi leaq -5280(%rbp), %rdi .LEHB5: call _ZNSi10_M_extractIfEERSiRT_@PLT movq %rax, %rdi leaq -10976(%rbp), %rsi call _ZNSi10_M_extractIfEERSiRT_@PLT movq %rax, %rdi leaq -11040(%rbp), %rsi call _ZNSi10_M_extractItEERSiRT_@PLT .LEHE5: movq -11160(%rbp), %rsi cmpq -11152(%rbp), %rsi je .L127 movss -11008(%rbp), %xmm0 movss %xmm0, (%rsi) addq $4, %rsi movq %rsi, -11160(%rbp) .L128: movq -11128(%rbp), %rsi cmpq -11120(%rbp), %rsi je .L129 movss -10976(%rbp), %xmm0 movss %xmm0, (%rsi) addq $4, %rsi movq %rsi, -11128(%rbp) .L130: movq %r13, -5280(%rbp) movq %r14, -5160(%rbp) leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax movq %rax, -5264(%rbp) movq -5192(%rbp), %rdi leaq -5176(%rbp), %rax cmpq %rax, %rdi je .L131 movq -5176(%rbp), %rax leaq 1(%rax), %rsi call _ZdlPvm@PLT .L131: movq %r15, -5264(%rbp) leaq -5208(%rbp), %rdi call _ZNSt6localeD1Ev@PLT movq %rbx, -5280(%rbp) movq -24(%rbx), %rax movq 16+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rbx movq %rbx, -5280(%rbp,%rax) movq $0, -5272(%rbp) movq %r12, -5160(%rbp) leaq -5160(%rbp), %rdi call _ZNSt8ios_baseD2Ev@PLT movq -10816(%rbp), %rax movq -24(%rax), %rax movq -10576(%rbp,%rax), %rbx testq %rbx, %rbx je .L114 .L115: cmpb $0, 56(%rbx) je .L133 movzbl 67(%rbx), %edx .L134: movsbl %dl, %edx leaq -10944(%rbp), %rsi leaq -10816(%rbp), %rdi .LEHB6: call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT .LEHE6: jmp .L226 .L127: leaq -11008(%rbp), %rdx leaq -11168(%rbp), %rdi .LEHB7: call _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_ jmp .L128 .L129: leaq -10976(%rbp), %rdx leaq -11136(%rbp), %rdi call _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_ .LEHE7: jmp .L130 .L114: movq -56(%rbp), %rax subq %fs:40, %rax jne .L227 .LEHB8: call _ZSt16__throw_bad_castv@PLT .L191: endbr64 movq %rax, %rbx jmp .L126 .L227: call __stack_chk_fail@PLT .L133: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) .LEHE8: movl %eax, %edx jmp .L134 .L226: movq (%rax), %rdx movq -24(%rdx), %rdx testb $5, 32(%rax,%rdx) jne .L228 leaq -5280(%rbp), %rax movq %rax, -11192(%rbp) leaq -5160(%rbp), %rdi call _ZNSt8ios_baseC2Ev@PLT movq %r12, -5160(%rbp) movq $0, -4944(%rbp) movb $0, -4936(%rbp) movb $0, -4935(%rbp) movq $0, -4928(%rbp) movq $0, -4920(%rbp) movq $0, -4912(%rbp) movq $0, -4904(%rbp) movq 8+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rbx movq %rbx, -5280(%rbp) movq -24(%rbx), %rax movq 16+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi movq %rsi, -5280(%rbp,%rax) movq $0, -5272(%rbp) movq -5280(%rbp), %rax movq -11192(%rbp), %rdi addq -24(%rax), %rdi movl $0, %esi .LEHB9: call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT .LEHE9: jmp .L229 .L228: movq -11160(%rbp), %r13 movq -11168(%rbp), %r12 movq %r13, %rax subq %r12, %rax movq %rax, -11224(%rbp) sarq $2, %rax movq %rax, -11216(%rbp) movq %rax, %rbx leaq -11136(%rbp), %rcx leaq -11168(%rbp), %rdx leaq -11104(%rbp), %rdi movl %eax, %esi .LEHB10: call _ZN4DataC1EiRSt6vectorIfSaIfEES3_ .LEHE10: leaq -10288(%rbp), %rdi leaq -10272(%rbp), %rax movq %rax, -10288(%rbp) leaq 7+.LC6(%rip), %rdx leaq -7(%rdx), %rsi .LEHB11: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag .LEHE11: leaq -10288(%rbp), %rsi leaq -5280(%rbp), %rdi .LEHB12: call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT .LEHE12: movq -10288(%rbp), %rdi leaq -10272(%rbp), %rax cmpq %rax, %rdi je .L136 movq -10272(%rbp), %rax leaq 1(%rax), %rsi call _ZdlPvm@PLT .L136: leaq -5280(%rbp), %rdi .LEHB13: call _ZNSt13random_device9_M_getvalEv@PLT .LEHE13: movl %eax, %eax movq %rax, -10288(%rbp) movl $1, %ecx movabsq $945986875574848801, %rsi .L140: movq -10296(%rbp,%rcx,8), %rax movq %rax, %rdx shrq $30, %rdx xorq %rdx, %rax imulq $1812433253, %rax, %rdi movq %rcx, %rdx shrq $4, %rdx movq %rdx, %rax mulq %rsi shrq %rdx imulq $624, %rdx, %rdx movq %rcx, %rax subq %rdx, %rax addl %edi, %eax movq %rax, -10288(%rbp,%rcx,8) addq $1, %rcx cmpq $624, %rcx jne .L140 movq $624, -5296(%rbp) leaq -5280(%rbp), %rdi call _ZNSt13random_device7_M_finiEv@PLT leaq -10288(%rbp), %rax movq %rax, %r15 movq %rax, %rdx movq %r13, %rsi movq %r12, %rdi call _ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_ movq %r15, %rdx movq -11128(%rbp), %rsi movq -11136(%rbp), %rdi call _ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_ leaq -11136(%rbp), %rcx leaq -11168(%rbp), %rdx leaq -11072(%rbp), %rdi movl -11196(%rbp), %esi .LEHB14: call _ZN4DataC1EiRSt6vectorIfSaIfEES3_ .LEHE14: jmp .L230 .L203: endbr64 movq %rax, %rbx leaq -10288(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT .L139: leaq -11104(%rbp), %rdi call _ZN4DataD1Ev jmp .L126 .L230: movq -11216(%rbp), %rax leaq 1023(%rax), %r12 shrq $10, %r12 movl -11208(%rbp), %eax imull %r12d, %eax movl %eax, -11192(%rbp) leal 0(,%rax,8), %r14d movq $0, -11040(%rbp) movq $0, -11032(%rbp) movl %eax, -11024(%rbp) movslq %eax, %r13 sall $2, %eax movl %eax, -11020(%rbp) movslq %eax, %rsi leaq -11040(%rbp), %rdi .LEHB15: call cudaMalloc@PLT movslq -11020(%rbp), %rsi leaq -11032(%rbp), %rdi call cudaMalloc@PLT movslq -11020(%rbp), %rdx movl $0, %esi movq -11040(%rbp), %rdi call cudaMemset@PLT movslq -11020(%rbp), %rdx movl $0, %esi movq -11032(%rbp), %rdi call cudaMemset@PLT .LEHE15: salq $2, %r13 leaq -11176(%rbp), %rdi movq %r13, %rsi .LEHB16: call cudaMalloc@PLT movq %r13, %rdx movl $0, %esi movq -11176(%rbp), %rdi call cudaMemset@PLT call _ZNSt6chrono3_V212system_clock3nowEv@PLT movq %rax, -11232(%rbp) movl -11200(%rbp), %eax movslq %eax, %r13 testl %eax, %eax je .L141 movl $0, %r15d movslq %r14d, %r14 jmp .L144 .L231: testl %eax, %eax jne .L142 subq $8, %rsp pushq -11176(%rbp) movl -11196(%rbp), %eax pushq %rax pushq -11032(%rbp) movq -11040(%rbp), %r9 movq -11064(%rbp), %r8 movq -11072(%rbp), %rcx movl -11088(%rbp), %edx movq -11096(%rbp), %rsi movq -11104(%rbp), %rdi .cfi_escape 0x2e,0x20 call _Z50__device_stub__Z11fine_reducePKfS0_iS0_S0_PfS1_iPiPKfS0_iS0_S0_PfS1_iPi addq $32, %rsp .L142: .cfi_escape 0x2e,0 call cudaDeviceSynchronize@PLT movl -11192(%rbp), %eax movl %eax, -10976(%rbp) movl $1, -10972(%rbp) movl $1, -10968(%rbp) movl $1, -11008(%rbp) movl $1, -11004(%rbp) movl $1, -11000(%rbp) movl $0, %r9d movq %r14, %r8 movq -10976(%rbp), %rdx movl $1, %ecx movq -11008(%rbp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L143 movq -11176(%rbp), %r9 movl -11196(%rbp), %r8d movq -11032(%rbp), %rcx movq -11040(%rbp), %rdx movq -11064(%rbp), %rsi movq -11072(%rbp), %rdi call _Z42__device_stub__Z13coarse_reducePfS_S_S_iPiPfS_S_S_iPi .L143: call cudaDeviceSynchronize@PLT addq $1, %r15 cmpq %r13, %r15 je .L141 .L144: movl $1024, -10976(%rbp) movl $1, -10972(%rbp) movl $1, -10968(%rbp) movl %r12d, -11008(%rbp) movl $1, -11004(%rbp) movl $1, -11000(%rbp) movl $0, %r9d movl $12288, %r8d movq -10976(%rbp), %rdx movl $1, %ecx movq -11008(%rbp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT jmp .L231 .L141: call _ZNSt6chrono3_V212system_clock3nowEv@PLT movq -11232(%rbp), %rsi subq %rsi, %rax pxor %xmm0, %xmm0 cvtsi2ssq %rax, %xmm0 divss .LC7(%rip), %xmm0 movss %xmm0, -11192(%rbp) leaq .LC8(%rip), %rsi leaq _ZSt4cerr(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm2, %xmm2 cvtss2sd -11192(%rbp), %xmm2 movq %xmm2, %r15 movapd %xmm2, %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC9(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi leaq .LC10(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq -11216(%rbp), %rsi call _ZNSo9_M_insertImEERSoT_@PLT movq %rax, %rdi leaq .LC11(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %r15, std_time_used(%rip) movq -11176(%rbp), %rdi call cudaFree@PLT movl $0x00000000, -10976(%rbp) movslq -11208(%rbp), %r14 leaq -11180(%rbp), %rcx leaq -10976(%rbp), %rdx leaq -11008(%rbp), %rdi movq %r14, %rsi call _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_ .LEHE16: movl $0x00000000, -11180(%rbp) leaq -11181(%rbp), %rcx leaq -11180(%rbp), %rdx leaq -10976(%rbp), %rdi movq %r14, %rsi .LEHB17: call _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_ .LEHE17: movq -11008(%rbp), %r12 movslq -11052(%rbp), %rdx movl $2, %ecx movq -11072(%rbp), %rsi movq %r12, %rdi .LEHB18: call cudaMemcpy@PLT movq -10976(%rbp), %r13 movslq -11052(%rbp), %rdx movl $2, %ecx movq -11064(%rbp), %rsi movq %r13, %rdi call cudaMemcpy@PLT testq %r14, %r14 je .L145 movl $0, %eax movq %r14, %rsi .L146: addq $1, %rax cmpq %rax, %rsi jne .L146 .L145: leaq .LC13(%rip), %rsi leaq .LC14(%rip), %rdi call fopen@PLT movq %rax, %r15 movsd std_time_used(%rip), %xmm0 leaq .LC15(%rip), %rdx movl $2, %esi movq %rax, %rdi movl $1, %eax call __fprintf_chk@PLT movq %r15, %rdi call fclose@PLT movq -11224(%rbp), %rax cmpq $36, %rax jbe .L184 cmpq $396, %rax jbe .L185 cmpq $3996, %rax jbe .L186 cmpq $39996, %rax jbe .L187 movq -11216(%rbp), %rdx movl $1, %esi movabsq $3777893186295716171, %rdi .L151: movq %rdx, %rcx movq %rdx, %rax mulq %rdi shrq $11, %rdx addl $4, %esi cmpq $99999, %rcx jbe .L147 cmpq $999999, %rcx jbe .L148 cmpq $9999999, %rcx jbe .L149 cmpq $99999999, %rcx ja .L151 .L150: addl $3, %esi jmp .L147 .L185: movl $1, %esi .L148: addl $1, %esi .L147: leaq -10912(%rbp), %rdi leaq -10896(%rbp), %rax movq %rax, -10912(%rbp) movl %esi, %esi movl $0, %edx call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructEmc@PLT .LEHE18: jmp .L232 .L186: movl $1, %esi .L149: addl $2, %esi jmp .L147 .L187: movl $1, %esi jmp .L150 .L184: movl $1, %esi jmp .L147 .L232: movq -10912(%rbp), %rsi movabsq $3688503277381496880, %rax movabsq $3976738051646829616, %rdx movq %rax, -272(%rbp) movq %rdx, -264(%rbp) movabsq $3544667369688283184, %rax movabsq $3832902143785906737, %rdx movq %rax, -256(%rbp) movq %rdx, -248(%rbp) movabsq $4121136918051239473, %rax movabsq $3689066235924983858, %rdx movq %rax, -240(%rbp) movq %rdx, -232(%rbp) movabsq $3977301010190316594, %rax movabsq $3545230328231770162, %rdx movq %rax, -224(%rbp) movq %rdx, -216(%rbp) movabsq $3833465102329393715, %rax movabsq $4121699876594726451, %rdx movq %rax, -208(%rbp) movq %rdx, -200(%rbp) movabsq $3689629194468470836, %rax movabsq $3977863968733803572, %rdx movq %rax, -192(%rbp) movq %rdx, -184(%rbp) movabsq $3545793286775257140, %rax movabsq $3834028060872880693, %rdx movq %rax, -176(%rbp) movq %rdx, -168(%rbp) movabsq $4122262835138213429, %rax movabsq $3690192153011957814, %rdx movq %rax, -160(%rbp) movq %rdx, -152(%rbp) movabsq $3978426927277290550, %rax movabsq $3546356245318744118, %rdx movq %rax, -144(%rbp) movq %rdx, -136(%rbp) movabsq $3834591019416367671, %rax movabsq $4122825793681700407, %rdx movq %rax, -128(%rbp) movq %rdx, -120(%rbp) movabsq $3690755111555444792, %rax movabsq $3978989885820777528, %rdx movq %rax, -112(%rbp) movq %rdx, -104(%rbp) movabsq $3546919203862231096, %rax movabsq $3835153977959854649, %rdx movq %rax, -96(%rbp) movq %rdx, -88(%rbp) movabsq $4122263930388298034, %rax movabsq $16106987313379638, %rdx movq %rax, -87(%rbp) movq %rdx, -79(%rbp) movl -10904(%rbp), %eax leal -1(%rax), %ecx cmpq $396, -11224(%rbp) jbe .L155 movabsq $2951479051793528259, %rdi .L156: movq %rbx, %rdx shrq $2, %rdx movq %rdx, %rax mulq %rdi movq %rdx, %r8 shrq $2, %r8 andq $-4, %rdx addq %r8, %rdx leaq (%rdx,%rdx,4), %rdx salq $2, %rdx movq %rbx, %rax subq %rdx, %rax addq %rax, %rax movq %rbx, %rdx movq %r8, %rbx movl %ecx, %r8d movzbl -271(%rbp,%rax), %r9d movb %r9b, (%rsi,%r8) leal -1(%rcx), %r8d movzbl -272(%rbp,%rax), %eax movb %al, (%rsi,%r8) subl $2, %ecx cmpq $9999, %rdx ja .L156 .L155: leal 48(%rbx), %eax cmpq $9, %rbx jbe .L158 addq %rbx, %rbx movzbl -271(%rbp,%rbx), %eax movb %al, 1(%rsi) movzbl -272(%rbp,%rbx), %eax .L158: movb %al, (%rsi) leaq -10864(%rbp), %rax movq %rax, -10880(%rbp) movq $0, -10872(%rbp) movb $0, -10864(%rbp) leaq -10832(%rbp), %rax movq %rax, -10848(%rbp) movq $0, -10840(%rbp) movb $0, -10832(%rbp) movq -10904(%rbp), %rbx movq -10912(%rbp), %rax movq %rax, %r15 leaq -5280(%rbp), %rdi leaq -5264(%rbp), %rax movq %rax, -5280(%rbp) movq $0, -5272(%rbp) movb $0, -5264(%rbp) leaq 17(%rbx), %rsi .LEHB19: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm@PLT movabsq $4611686018427387903, %rax subq -5272(%rbp), %rax cmpq $16, %rax jbe .L233 leaq -5280(%rbp), %rdi movl $17, %edx leaq .LC17(%rip), %rsi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT jmp .L234 .L233: movq -56(%rbp), %rax subq %fs:40, %rax jne .L235 leaq .LC16(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .L204: endbr64 movq %rax, %rbx leaq -5280(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT .L165: leaq -10848(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq -10880(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq -10912(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT .L176: leaq -10976(%rbp), %rdi call _ZNSt6vectorIfSaIfEED1Ev .L177: leaq -11008(%rbp), %rdi call _ZNSt6vectorIfSaIfEED1Ev .L178: leaq -11040(%rbp), %rdi call _ZN4DataD1Ev .L179: leaq -11072(%rbp), %rdi call _ZN4DataD1Ev jmp .L139 .L235: call __stack_chk_fail@PLT .L234: movabsq $4611686018427387903, %rax subq -5272(%rbp), %rax cmpq %rbx, %rax jb .L236 leaq -5280(%rbp), %rdi movq %rbx, %rdx movq %r15, %rsi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT jmp .L237 .L236: movq -56(%rbp), %rax subq %fs:40, %rax jne .L238 leaq .LC16(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .LEHE19: .L238: call __stack_chk_fail@PLT .L237: leaq -5280(%rbp), %r14 leaq -10912(%rbp), %rdi movq %r14, %rsi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEOS4_@PLT movq %r14, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq -10904(%rbp), %rbx movq -10912(%rbp), %rax movq %rax, %r15 leaq -5264(%rbp), %rax movq %rax, -5280(%rbp) movq $0, -5272(%rbp) movb $0, -5264(%rbp) leaq 14(%rbx), %rsi movq %r14, %rdi .LEHB20: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm@PLT movabsq $4611686018427387903, %rax subq -5272(%rbp), %rax cmpq %rbx, %rax jb .L239 leaq -5280(%rbp), %rdi movq %rbx, %rdx movq %r15, %rsi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT jmp .L240 .L239: movq -56(%rbp), %rax subq %fs:40, %rax jne .L241 leaq .LC16(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .L205: endbr64 movq %rax, %rbx leaq -5280(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT jmp .L165 .L241: call __stack_chk_fail@PLT .L240: movabsq $4611686018427387903, %rax subq -5272(%rbp), %rax cmpq $13, %rax jbe .L242 leaq -5280(%rbp), %rdi movl $14, %edx leaq .LC18(%rip), %rsi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT jmp .L243 .L242: movq -56(%rbp), %rax subq %fs:40, %rax jne .L244 leaq .LC16(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .LEHE20: .L244: call __stack_chk_fail@PLT .L243: leaq -5280(%rbp), %rbx leaq -10848(%rbp), %rdi movq %rbx, %rsi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEOS4_@PLT movq %rbx, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq .LC19(%rip), %rsi movq -10848(%rbp), %rdi .LEHB21: call fopen@PLT movq %rax, -11192(%rbp) movq -11208(%rbp), %rax testl %eax, %eax jle .L172 leal -1(%rax), %r14d movl $0, %ebx leaq .LC20(%rip), %r15 jmp .L173 .L245: leaq 1(%rbx), %rax cmpq %r14, %rbx je .L172 movq %rax, %rbx .L173: pxor %xmm0, %xmm0 cvtss2sd (%r12,%rbx,4), %xmm0 pxor %xmm1, %xmm1 cvtss2sd 0(%r13,%rbx,4), %xmm1 movq %r15, %rdx movl $2, %esi movq -11192(%rbp), %rdi movl $2, %eax call __fprintf_chk@PLT jmp .L245 .L172: movq -11192(%rbp), %rdi call fclose@PLT .LEHE21: leaq -10848(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq -10880(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq -10912(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq -10976(%rbp), %rdi call _ZNSt6vectorIfSaIfEED1Ev leaq -11008(%rbp), %rdi call _ZNSt6vectorIfSaIfEED1Ev leaq -11040(%rbp), %rdi call _ZN4DataD1Ev leaq -11072(%rbp), %rdi call _ZN4DataD1Ev leaq -11104(%rbp), %rdi call _ZN4DataD1Ev leaq -10944(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq -10816(%rbp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT leaq -11136(%rbp), %rdi call _ZNSt6vectorIfSaIfEED1Ev leaq -11168(%rbp), %rdi call _ZNSt6vectorIfSaIfEED1Ev movq -56(%rbp), %rax subq %fs:40, %rax jne .L246 movl $0, %eax leaq -40(%rbp), %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 popq %rbp .cfi_remember_state .cfi_def_cfa 7, 8 ret .L190: .cfi_restore_state endbr64 movq %rax, %rbx leaq -5280(%rbp), %rdi call _ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT jmp .L126 .L192: endbr64 movq %rax, %rbx leaq -5280(%rbp), %rdi call _ZNSt13random_device7_M_finiEv@PLT jmp .L139 .L198: endbr64 movq %rax, %rbx jmp .L165 .L197: endbr64 movq %rax, %rbx jmp .L176 .L196: endbr64 movq %rax, %rbx jmp .L177 .L195: endbr64 movq %rax, %rbx jmp .L178 .L194: endbr64 movq %rax, %rbx jmp .L179 .L193: endbr64 movq %rax, %rbx jmp .L139 .L189: endbr64 movq %rax, %rbx jmp .L180 .L181: movq %rbx, %rdi .LEHB22: call _Unwind_Resume@PLT .LEHE22: .L246: call __stack_chk_fail@PLT .cfi_endproc .LFE5267: .section .gcc_except_table,"a",@progbits .LLSDA5267: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE5267-.LLSDACSB5267 .LLSDACSB5267: .uleb128 .LEHB0-.LFB5267 .uleb128 .LEHE0-.LEHB0 .uleb128 .L189-.LFB5267 .uleb128 0 .uleb128 .LEHB1-.LFB5267 .uleb128 .LEHE1-.LEHB1 .uleb128 0 .uleb128 0 .uleb128 .LEHB2-.LFB5267 .uleb128 .LEHE2-.LEHB2 .uleb128 .L201-.LFB5267 .uleb128 0 .uleb128 .LEHB3-.LFB5267 .uleb128 .LEHE3-.LEHB3 .uleb128 .L202-.LFB5267 .uleb128 0 .uleb128 .LEHB4-.LFB5267 .uleb128 .LEHE4-.LEHB4 .uleb128 .L200-.LFB5267 .uleb128 0 .uleb128 .LEHB5-.LFB5267 .uleb128 .LEHE5-.LEHB5 .uleb128 .L190-.LFB5267 .uleb128 0 .uleb128 .LEHB6-.LFB5267 .uleb128 .LEHE6-.LEHB6 .uleb128 .L191-.LFB5267 .uleb128 0 .uleb128 .LEHB7-.LFB5267 .uleb128 .LEHE7-.LEHB7 .uleb128 .L190-.LFB5267 .uleb128 0 .uleb128 .LEHB8-.LFB5267 .uleb128 .LEHE8-.LEHB8 .uleb128 .L191-.LFB5267 .uleb128 0 .uleb128 .LEHB9-.LFB5267 .uleb128 .LEHE9-.LEHB9 .uleb128 .L199-.LFB5267 .uleb128 0 .uleb128 .LEHB10-.LFB5267 .uleb128 .LEHE10-.LEHB10 .uleb128 .L191-.LFB5267 .uleb128 0 .uleb128 .LEHB11-.LFB5267 .uleb128 .LEHE11-.LEHB11 .uleb128 .L193-.LFB5267 .uleb128 0 .uleb128 .LEHB12-.LFB5267 .uleb128 .LEHE12-.LEHB12 .uleb128 .L203-.LFB5267 .uleb128 0 .uleb128 .LEHB13-.LFB5267 .uleb128 .LEHE13-.LEHB13 .uleb128 .L192-.LFB5267 .uleb128 0 .uleb128 .LEHB14-.LFB5267 .uleb128 .LEHE14-.LEHB14 .uleb128 .L193-.LFB5267 .uleb128 0 .uleb128 .LEHB15-.LFB5267 .uleb128 .LEHE15-.LEHB15 .uleb128 .L194-.LFB5267 .uleb128 0 .uleb128 .LEHB16-.LFB5267 .uleb128 .LEHE16-.LEHB16 .uleb128 .L195-.LFB5267 .uleb128 0 .uleb128 .LEHB17-.LFB5267 .uleb128 .LEHE17-.LEHB17 .uleb128 .L196-.LFB5267 .uleb128 0 .uleb128 .LEHB18-.LFB5267 .uleb128 .LEHE18-.LEHB18 .uleb128 .L197-.LFB5267 .uleb128 0 .uleb128 .LEHB19-.LFB5267 .uleb128 .LEHE19-.LEHB19 .uleb128 .L204-.LFB5267 .uleb128 0 .uleb128 .LEHB20-.LFB5267 .uleb128 .LEHE20-.LEHB20 .uleb128 .L205-.LFB5267 .uleb128 0 .uleb128 .LEHB21-.LFB5267 .uleb128 .LEHE21-.LEHB21 .uleb128 .L198-.LFB5267 .uleb128 0 .uleb128 .LEHB22-.LFB5267 .uleb128 .LEHE22-.LEHB22 .uleb128 0 .uleb128 0 .LLSDACSE5267: .text .size main, .-main .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .globl std_time_used .bss .align 8 .type std_time_used, @object .size std_time_used, 8 std_time_used: .zero 8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC7: .long 1315859240 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi ; -- Begin function _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi .globl _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi .p2align 8 .type _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi,@function _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi: ; @_Z11fine_reducePKfS0_iS0_S0_PfS1_iPi ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x54 s_load_b32 s3, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s8, s2, 0xffff s_mov_b32 s2, exec_lo v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1] s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_16 ; %bb.1: s_clause 0x1 s_load_b32 s9, s[0:1], 0x38 s_load_b128 s[4:7], s[0:1], 0x0 s_mov_b32 s2, exec_lo s_waitcnt lgkmcnt(0) v_cmpx_gt_i32_e64 s9, v0 s_cbranch_execz .LBB0_3 ; %bb.2: s_load_b128 s[16:19], s[0:1], 0x18 v_lshlrev_b32_e32 v2, 2, v0 v_add_nc_u32_e32 v5, s9, v0 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b32 v3, v2, s[16:17] global_load_b32 v4, v2, s[18:19] v_add_nc_u32_e32 v2, 0, v2 v_lshl_add_u32 v5, v5, 2, 0 s_waitcnt vmcnt(1) ds_store_b32 v2, v3 s_waitcnt vmcnt(0) ds_store_b32 v5, v4 .LBB0_3: s_or_b32 exec_lo, exec_lo, s2 v_ashrrev_i32_e32 v2, 31, v1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cmp_lt_i32 s9, 1 v_lshlrev_b64 v[1:2], 2, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s4, v1 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo v_add_co_u32 v5, vcc_lo, s6, v1 v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo global_load_b32 v1, v[3:4], off global_load_b32 v2, v[5:6], off s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x40 s_load_b128 s[4:7], s[0:1], 0x28 s_cbranch_scc1 .LBB0_6 ; %bb.4: ; %.lr.ph.preheader v_dual_mov_b32 v4, 0x7f7fffff :: v_dual_mov_b32 v3, -1 s_lshl_b32 s0, s9, 2 s_mov_b32 s1, 0 s_mov_b32 s10, 0 .p2align 6 .LBB0_5: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s11, s10, s0 v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v6, s11 s_add_i32 s10, s10, 4 ds_load_b32 v5, v5 ds_load_b32 v6, v6 s_waitcnt vmcnt(0) lgkmcnt(0) v_dual_sub_f32 v5, v1, v5 :: v_dual_sub_f32 v6, v2, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v6, v6, v6 v_fmac_f32_e32 v6, v5, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1) v_cmp_lt_f32_e32 vcc_lo, v6, v4 v_cndmask_b32_e64 v3, v3, s1, vcc_lo v_cndmask_b32_e32 v4, v4, v6, vcc_lo s_add_i32 s1, s1, 1 s_cmp_eq_u32 s9, s1 s_cbranch_scc0 .LBB0_5 s_branch .LBB0_7 .LBB0_6: v_mov_b32_e32 v3, -1 .LBB0_7: ; %._crit_edge s_cmp_lt_i32 s9, 1 s_waitcnt vmcnt(0) lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_16 ; %bb.8: ; %.lr.ph98 v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v4, s8, v0 v_lshl_add_u32 v5, v0, 2, 0 v_cmp_eq_u32_e64 s0, 0, v0 s_cmp_gt_u32 s8, 1 s_delay_alu instid0(VALU_DEP_3) v_add_nc_u32_e32 v6, s8, v4 v_lshl_add_u32 v7, v4, 2, 0 s_cselect_b32 s1, -1, 0 s_mov_b32 s10, 0 s_mul_i32 s15, s15, s9 v_lshl_add_u32 v8, v6, 2, 0 s_branch .LBB0_10 .LBB0_9: ; in Loop: Header=BB0_10 Depth=1 s_or_b32 exec_lo, exec_lo, s11 s_add_i32 s10, s10, 1 s_waitcnt_vscnt null, 0x0 s_cmp_lg_u32 s10, s9 s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB0_16 .LBB0_10: ; =>This Loop Header: Depth=1 ; Child Loop BB0_14 Depth 2 v_cmp_eq_u32_e32 vcc_lo, s10, v3 s_mov_b32 s11, s8 v_dual_cndmask_b32 v10, 0, v1 :: v_dual_cndmask_b32 v11, 0, v2 v_cndmask_b32_e64 v12, 0, 1.0, vcc_lo s_and_not1_b32 vcc_lo, exec_lo, s1 ds_store_b32 v5, v10 ds_store_b32 v7, v11 ds_store_b32 v8, v12 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_vccz .LBB0_14 .LBB0_11: ; %._crit_edge95 ; in Loop: Header=BB0_10 Depth=1 s_and_saveexec_b32 s11, s0 s_cbranch_execz .LBB0_9 ; %bb.12: ; in Loop: Header=BB0_10 Depth=1 ds_load_b32 v10, v8 ds_load_b32 v11, v5 ds_load_b32 v12, v7 s_add_i32 s12, s10, s15 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_ashr_i32 s13, s12, 31 s_lshl_b64 s[12:13], s[12:13], 2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s4, s12 s_addc_u32 s17, s5, s13 s_add_u32 s18, s6, s12 s_addc_u32 s19, s7, s13 s_add_u32 s12, s2, s12 s_addc_u32 s13, s3, s13 s_waitcnt lgkmcnt(2) v_cvt_i32_f32_e32 v10, v10 s_waitcnt lgkmcnt(1) global_store_b32 v9, v11, s[16:17] s_waitcnt lgkmcnt(0) s_clause 0x1 global_store_b32 v9, v12, s[18:19] global_store_b32 v9, v10, s[12:13] s_branch .LBB0_9 .p2align 6 .LBB0_13: ; in Loop: Header=BB0_14 Depth=2 s_or_b32 exec_lo, exec_lo, s13 s_cmp_lt_u32 s11, 4 s_mov_b32 s11, s12 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_11 .LBB0_14: ; %.lr.ph94 ; Parent Loop BB0_10 Depth=1 ; => This Inner Loop Header: Depth=2 s_lshr_b32 s12, s11, 1 s_mov_b32 s13, exec_lo v_cmpx_gt_u32_e64 s12, v0 s_cbranch_execz .LBB0_13 ; %bb.15: ; in Loop: Header=BB0_14 Depth=2 v_add_nc_u32_e32 v10, s12, v0 v_add_nc_u32_e32 v12, s12, v4 s_delay_alu instid0(VALU_DEP_2) v_lshl_add_u32 v10, v10, 2, 0 ds_load_b32 v10, v10 ds_load_b32 v11, v5 s_waitcnt lgkmcnt(0) v_add_f32_e32 v10, v10, v11 v_lshl_add_u32 v11, v12, 2, 0 v_add_nc_u32_e32 v12, s12, v6 ds_store_b32 v5, v10 ds_load_b32 v10, v11 ds_load_b32 v11, v7 s_waitcnt lgkmcnt(0) v_add_f32_e32 v10, v10, v11 v_lshl_add_u32 v11, v12, 2, 0 ds_store_b32 v7, v10 ds_load_b32 v10, v11 ds_load_b32 v11, v8 s_waitcnt lgkmcnt(0) v_add_f32_e32 v10, v10, v11 ds_store_b32 v8, v10 s_branch .LBB0_13 .LBB0_16: ; %.loopexit s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 328 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 13 .amdhsa_next_free_sgpr 20 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi, .Lfunc_end0-_Z11fine_reducePKfS0_iS0_S0_PfS1_iPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 920 ; NumSgprs: 22 ; NumVgprs: 13 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 22 ; NumVGPRsForWavesPerEU: 13 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z13coarse_reducePfS_S_S_iPi ; -- Begin function _Z13coarse_reducePfS_S_S_iPi .globl _Z13coarse_reducePfS_S_S_iPi .p2align 8 .type _Z13coarse_reducePfS_S_S_iPi,@function _Z13coarse_reducePfS_S_S_iPi: ; @_Z13coarse_reducePfS_S_S_iPi ; %bb.0: s_load_b128 s[4:7], s[0:1], 0x10 v_lshlrev_b32_e32 v1, 2, v0 s_clause 0x1 s_load_b32 s2, s[0:1], 0x20 s_load_b32 s3, s[0:1], 0x3c s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b32 v5, v1, s[4:5] global_load_b32 v6, v1, s[6:7] v_add_nc_u32_e32 v3, 0, v1 s_and_b32 s8, s3, 0xffff s_bfe_u32 s3, s3, 0xf0001 v_add_nc_u32_e32 v2, s8, v0 s_cmp_lt_i32 s3, s2 s_delay_alu instid0(VALU_DEP_1) v_lshl_add_u32 v4, v2, 2, 0 s_waitcnt vmcnt(1) ds_store_b32 v3, v5 s_waitcnt vmcnt(0) ds_store_b32 v4, v6 s_waitcnt lgkmcnt(0) s_set_inst_prefetch_distance 0x1 s_branch .LBB1_2 .p2align 6 .LBB1_1: ; in Loop: Header=BB1_2 Depth=1 s_or_b32 exec_lo, exec_lo, s8 s_lshr_b32 s3, s3, 1 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s3, s2 .LBB1_2: ; =>This Inner Loop Header: Depth=1 s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB1_5 ; %bb.3: ; %.lr.ph ; in Loop: Header=BB1_2 Depth=1 s_mov_b32 s8, exec_lo v_cmpx_gt_u32_e64 s3, v0 s_cbranch_execz .LBB1_1 ; %bb.4: ; in Loop: Header=BB1_2 Depth=1 v_add_nc_u32_e32 v5, s3, v0 v_add_nc_u32_e32 v7, s3, v2 s_delay_alu instid0(VALU_DEP_2) v_lshl_add_u32 v5, v5, 2, 0 ds_load_b32 v5, v5 ds_load_b32 v6, v3 s_waitcnt lgkmcnt(0) v_add_f32_e32 v5, v5, v6 v_lshl_add_u32 v6, v7, 2, 0 ds_store_b32 v3, v5 ds_load_b32 v5, v6 ds_load_b32 v6, v4 s_waitcnt lgkmcnt(0) v_add_f32_e32 v5, v5, v6 ds_store_b32 v4, v5 s_branch .LBB1_1 .LBB1_5: ; %._crit_edge s_set_inst_prefetch_distance 0x2 v_cmp_gt_i32_e32 vcc_lo, s2, v0 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB1_7 ; %bb.6: s_load_b64 s[8:9], s[0:1], 0x28 v_lshlrev_b32_e32 v4, 2, v0 v_add_co_u32 v2, s2, s4, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v3, null, s5, 0, s2 v_add_co_u32 v0, s2, s6, v1 v_add_co_ci_u32_e64 v1, null, s7, 0, s2 s_load_b128 s[4:7], s[0:1], 0x0 s_waitcnt lgkmcnt(0) global_load_b32 v5, v4, s[8:9] global_load_b32 v6, v[2:3], off global_load_b32 v7, v[0:1], off s_waitcnt vmcnt(2) v_max_i32_e32 v5, 1, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cvt_f32_i32_e32 v5, v5 s_waitcnt vmcnt(1) v_div_scale_f32 v8, null, v5, v5, v6 s_waitcnt vmcnt(0) v_div_scale_f32 v9, null, v5, v5, v7 v_div_scale_f32 v14, vcc_lo, v6, v5, v6 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_rcp_f32_e32 v10, v8 v_rcp_f32_e32 v11, v9 s_waitcnt_depctr 0xfff v_fma_f32 v12, -v8, v10, 1.0 v_fma_f32 v13, -v9, v11, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_dual_fmac_f32 v11, v13, v11 :: v_dual_fmac_f32 v10, v12, v10 v_div_scale_f32 v12, s2, v7, v5, v7 v_mul_f32_e32 v15, v12, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f32 v17, -v9, v15, v12 v_fmac_f32_e32 v15, v17, v11 v_mul_f32_e32 v13, v14, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v9, -v9, v15, v12 v_fma_f32 v16, -v8, v13, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v13, v16, v10 v_fma_f32 v8, -v8, v13, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_div_fmas_f32 v8, v8, v10, v13 v_mov_b32_e32 v10, 0 s_mov_b32 vcc_lo, s2 v_div_fmas_f32 v9, v9, v11, v15 v_div_fixup_f32 v7, v9, v5, v7 v_div_fixup_f32 v5, v8, v5, v6 global_store_b32 v[0:1], v10, off global_store_b32 v[2:3], v10, off s_clause 0x2 global_store_b32 v4, v7, s[6:7] global_store_b32 v4, v5, s[4:5] global_store_b32 v4, v10, s[8:9] .LBB1_7: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13coarse_reducePfS_S_S_iPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 304 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 18 .amdhsa_next_free_sgpr 10 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z13coarse_reducePfS_S_S_iPi, .Lfunc_end1-_Z13coarse_reducePfS_S_S_iPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 636 ; NumSgprs: 12 ; NumVgprs: 18 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 12 ; NumVGPRsForWavesPerEU: 18 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .actual_access: read_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .actual_access: read_only .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .offset: 56 .size: 4 .value_kind: by_value - .actual_access: write_only .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .offset: 72 .size: 4 .value_kind: hidden_block_count_x - .offset: 76 .size: 4 .value_kind: hidden_block_count_y - .offset: 80 .size: 4 .value_kind: hidden_block_count_z - .offset: 84 .size: 2 .value_kind: hidden_group_size_x - .offset: 86 .size: 2 .value_kind: hidden_group_size_y - .offset: 88 .size: 2 .value_kind: hidden_group_size_z - .offset: 90 .size: 2 .value_kind: hidden_remainder_x - .offset: 92 .size: 2 .value_kind: hidden_remainder_y - .offset: 94 .size: 2 .value_kind: hidden_remainder_z - .offset: 112 .size: 8 .value_kind: hidden_global_offset_x - .offset: 120 .size: 8 .value_kind: hidden_global_offset_y - .offset: 128 .size: 8 .value_kind: hidden_global_offset_z - .offset: 136 .size: 2 .value_kind: hidden_grid_dims - .offset: 192 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 328 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi .private_segment_fixed_size: 0 .sgpr_count: 22 .sgpr_spill_count: 0 .symbol: _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 13 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .actual_access: write_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: by_value - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .offset: 48 .size: 4 .value_kind: hidden_block_count_x - .offset: 52 .size: 4 .value_kind: hidden_block_count_y - .offset: 56 .size: 4 .value_kind: hidden_block_count_z - .offset: 60 .size: 2 .value_kind: hidden_group_size_x - .offset: 62 .size: 2 .value_kind: hidden_group_size_y - .offset: 64 .size: 2 .value_kind: hidden_group_size_z - .offset: 66 .size: 2 .value_kind: hidden_remainder_x - .offset: 68 .size: 2 .value_kind: hidden_remainder_y - .offset: 70 .size: 2 .value_kind: hidden_remainder_z - .offset: 88 .size: 8 .value_kind: hidden_global_offset_x - .offset: 96 .size: 8 .value_kind: hidden_global_offset_y - .offset: 104 .size: 8 .value_kind: hidden_global_offset_z - .offset: 112 .size: 2 .value_kind: hidden_grid_dims - .offset: 168 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 304 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13coarse_reducePfS_S_S_iPi .private_segment_fixed_size: 0 .sgpr_count: 12 .sgpr_spill_count: 0 .symbol: _Z13coarse_reducePfS_S_S_iPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 18 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "c2f0926ca82a9e2897df7a76c67abf5de6c6ff93.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z26__device_stub__fine_reducePKfS0_iS0_S0_PfS1_iPi # -- Begin function _Z26__device_stub__fine_reducePKfS0_iS0_S0_PfS1_iPi .p2align 4, 0x90 .type _Z26__device_stub__fine_reducePKfS0_iS0_S0_PfS1_iPi,@function _Z26__device_stub__fine_reducePKfS0_iS0_S0_PfS1_iPi: # @_Z26__device_stub__fine_reducePKfS0_iS0_S0_PfS1_iPi .cfi_startproc # %bb.0: subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movl %edx, 4(%rsp) movq %rcx, 72(%rsp) movq %r8, 64(%rsp) movq %r9, 56(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 4(%rsp), %rax movq %rax, 112(%rsp) leaq 72(%rsp), %rax movq %rax, 120(%rsp) leaq 64(%rsp), %rax movq %rax, 128(%rsp) leaq 56(%rsp), %rax movq %rax, 136(%rsp) leaq 176(%rsp), %rax movq %rax, 144(%rsp) leaq 184(%rsp), %rax movq %rax, 152(%rsp) leaq 192(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z11fine_reducePKfS0_iS0_S0_PfS1_iPi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $184, %rsp .cfi_adjust_cfa_offset -184 retq .Lfunc_end0: .size _Z26__device_stub__fine_reducePKfS0_iS0_S0_PfS1_iPi, .Lfunc_end0-_Z26__device_stub__fine_reducePKfS0_iS0_S0_PfS1_iPi .cfi_endproc # -- End function .globl _Z28__device_stub__coarse_reducePfS_S_S_iPi # -- Begin function _Z28__device_stub__coarse_reducePfS_S_S_iPi .p2align 4, 0x90 .type _Z28__device_stub__coarse_reducePfS_S_S_iPi,@function _Z28__device_stub__coarse_reducePfS_S_S_iPi: # @_Z28__device_stub__coarse_reducePfS_S_S_iPi .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movl %r8d, 4(%rsp) movq %r9, 56(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) leaq 56(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z13coarse_reducePfS_S_S_iPi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end1: .size _Z28__device_stub__coarse_reducePfS_S_S_iPi, .Lfunc_end1-_Z28__device_stub__coarse_reducePfS_S_S_iPi .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI2_0: .long 0x4e6e6b28 # float 1.0E+9 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $10888, %rsp # imm = 0x2A88 .cfi_def_cfa_offset 10944 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 cmpl $3, %edi jle .LBB2_184 # %bb.1: movq %rsi, %rbx movl %edi, %ebp movq 24(%rsi), %rdi .cfi_escape 0x2e, 0x00 xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r14 movl $300, %r15d # imm = 0x12C cmpl $5, %ebp jne .LBB2_3 # %bb.2: movq 32(%rbx), %rdi .cfi_escape 0x2e, 0x00 xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r15 .LBB2_3: movq 16(%rbx), %rsi .Ltmp0: .cfi_escape 0x2e, 0x00 leaq 360(%rsp), %rdi movl $8, %edx callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode .Ltmp1: # %bb.4: movq %r15, 192(%rsp) # 8-byte Spill leaq 320(%rsp), %rax movq %rax, 304(%rsp) movq $0, 312(%rsp) movb $0, 320(%rsp) movq 360(%rsp), %rax movq -24(%rax), %rax movq 600(%rsp,%rax), %rbx testq %rbx, %rbx je .LBB2_185 # %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i.lr.ph movq %r14, %rax movq %r14, 336(%rsp) # 8-byte Spill movq %r14, 200(%rsp) # 8-byte Spill movq %r14, 112(%rsp) # 8-byte Spill xorl %eax, %eax movq %rax, (%rsp) # 8-byte Spill leaq 304(%rsp), %r12 xorl %r13d, %r13d xorl %r15d, %r15d xorl %eax, %eax movq %rax, 8(%rsp) # 8-byte Spill xorl %ebp, %ebp xorl %r14d, %r14d jmp .LBB2_7 .p2align 4, 0x90 .LBB2_6: # %_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev.exit # in Loop: Header=BB2_7 Depth=1 addq $4, %r13 addq $4, %rbp movq $_ZTVSt15basic_streambufIcSt11char_traitsIcEE+16, 5904(%rsp) .cfi_escape 0x2e, 0x00 leaq 5960(%rsp), %rdi callq _ZNSt6localeD1Ev movq _ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE+8(%rip), %rax movq %rax, 5888(%rsp) movq -24(%rax), %rax movq _ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE+16(%rip), %rcx movq %rcx, 5888(%rsp,%rax) movq $0, 5896(%rsp) .cfi_escape 0x2e, 0x00 leaq 6008(%rsp), %rdi callq _ZNSt8ios_baseD2Ev movq 360(%rsp), %rax movq -24(%rax), %rax movq 600(%rsp,%rax), %rbx testq %rbx, %rbx je .LBB2_186 .LBB2_7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i # =>This Inner Loop Header: Depth=1 cmpb $0, 56(%rbx) je .LBB2_9 # %bb.8: # in Loop: Header=BB2_7 Depth=1 movzbl 67(%rbx), %eax jmp .LBB2_11 .p2align 4, 0x90 .LBB2_9: # in Loop: Header=BB2_7 Depth=1 .Ltmp3: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv .Ltmp4: # %bb.10: # %.noexc91 # in Loop: Header=BB2_7 Depth=1 movq (%rbx), %rax .Ltmp5: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi movl $10, %esi callq *48(%rax) .Ltmp6: .LBB2_11: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i # in Loop: Header=BB2_7 Depth=1 .Ltmp7: .cfi_escape 0x2e, 0x00 movsbl %al, %edx leaq 360(%rsp), %rdi movq %r12, %rsi callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_ .Ltmp8: # %bb.12: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit # in Loop: Header=BB2_7 Depth=1 movq (%rax), %rcx movq -24(%rcx), %rcx testb $5, 32(%rax,%rcx) jne .LBB2_42 # %bb.13: # in Loop: Header=BB2_7 Depth=1 .Ltmp138: .cfi_escape 0x2e, 0x00 leaq 5888(%rsp), %rbx movq %rbx, %rdi movq %r12, %rsi movl $8, %edx callq _ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEC1ERKNS_12basic_stringIcS2_S3_EESt13_Ios_Openmode .Ltmp139: # %bb.14: # in Loop: Header=BB2_7 Depth=1 .Ltmp141: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi leaq 880(%rsp), %rsi callq _ZNSi10_M_extractIfEERSiRT_ .Ltmp142: # %bb.15: # %_ZNSirsERf.exit # in Loop: Header=BB2_7 Depth=1 .Ltmp143: .cfi_escape 0x2e, 0x00 movq %rax, %rdi leaq 80(%rsp), %rsi callq _ZNSi10_M_extractIfEERSiRT_ .Ltmp144: # %bb.16: # %_ZNSirsERf.exit96 # in Loop: Header=BB2_7 Depth=1 .Ltmp145: .cfi_escape 0x2e, 0x00 movq %rax, %rdi leaq 208(%rsp), %rsi callq _ZNSi10_M_extractItEERSiRT_ .Ltmp146: # %bb.17: # %_ZNSirsERt.exit # in Loop: Header=BB2_7 Depth=1 cmpq %r15, %r13 je .LBB2_20 # %bb.18: # in Loop: Header=BB2_7 Depth=1 movss 880(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%r13) cmpq %r14, %rbp je .LBB2_30 .LBB2_19: # in Loop: Header=BB2_7 Depth=1 movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%rbp) jmp .LBB2_40 .p2align 4, 0x90 .LBB2_20: # in Loop: Header=BB2_7 Depth=1 subq (%rsp), %r13 # 8-byte Folded Reload movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC cmpq %rax, %r13 je .LBB2_180 # %bb.21: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i # in Loop: Header=BB2_7 Depth=1 movq %r13, %r12 sarq $2, %r12 cmpq $1, %r12 movq %r12, %rax adcq $0, %rax leaq (%rax,%r12), %r15 movabsq $2305843009213693951, %rcx # imm = 0x1FFFFFFFFFFFFFFF cmpq %rcx, %r15 cmovaeq %rcx, %r15 addq %r12, %rax cmovbq %rcx, %r15 testq %r15, %r15 je .LBB2_24 # %bb.22: # in Loop: Header=BB2_7 Depth=1 leaq (,%r15,4), %rdi .Ltmp147: .cfi_escape 0x2e, 0x00 callq _Znwm .Ltmp148: # %bb.23: # in Loop: Header=BB2_7 Depth=1 movq %rax, %rbx jmp .LBB2_25 .LBB2_24: # in Loop: Header=BB2_7 Depth=1 xorl %ebx, %ebx .LBB2_25: # %_ZNSt12_Vector_baseIfSaIfEE11_M_allocateEm.exit.i.i # in Loop: Header=BB2_7 Depth=1 movss 880(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%rbx,%r12,4) testq %r13, %r13 movq (%rsp), %r12 # 8-byte Reload jle .LBB2_27 # %bb.26: # in Loop: Header=BB2_7 Depth=1 .cfi_escape 0x2e, 0x00 movq %rbx, %rdi movq %r12, %rsi movq %r13, %rdx callq memmove@PLT .LBB2_27: # %_ZNSt6vectorIfSaIfEE11_S_relocateEPfS2_S2_RS0_.exit.i.i # in Loop: Header=BB2_7 Depth=1 testq %r12, %r12 je .LBB2_29 # %bb.28: # in Loop: Header=BB2_7 Depth=1 .cfi_escape 0x2e, 0x00 movq %r12, %rdi callq _ZdlPv .LBB2_29: # %_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_.exit.i # in Loop: Header=BB2_7 Depth=1 addq %rbx, %r13 leaq (%rbx,%r15,4), %r15 movq %rbx, (%rsp) # 8-byte Spill cmpq %r14, %rbp jne .LBB2_19 .LBB2_30: # in Loop: Header=BB2_7 Depth=1 subq 8(%rsp), %rbp # 8-byte Folded Reload movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC cmpq %rax, %rbp je .LBB2_182 # %bb.31: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i103 # in Loop: Header=BB2_7 Depth=1 movq %rbp, %r12 sarq $2, %r12 cmpq $1, %r12 movq %r12, %rax adcq $0, %rax leaq (%rax,%r12), %r14 movabsq $2305843009213693951, %rcx # imm = 0x1FFFFFFFFFFFFFFF cmpq %rcx, %r14 cmovaeq %rcx, %r14 addq %r12, %rax cmovbq %rcx, %r14 testq %r14, %r14 je .LBB2_34 # %bb.32: # in Loop: Header=BB2_7 Depth=1 leaq (,%r14,4), %rdi .Ltmp149: .cfi_escape 0x2e, 0x00 callq _Znwm .Ltmp150: # %bb.33: # in Loop: Header=BB2_7 Depth=1 movq %rax, %rbx jmp .LBB2_35 .LBB2_34: # in Loop: Header=BB2_7 Depth=1 xorl %ebx, %ebx .LBB2_35: # %_ZNSt12_Vector_baseIfSaIfEE11_M_allocateEm.exit.i.i106 # in Loop: Header=BB2_7 Depth=1 movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, (%rbx,%r12,4) testq %rbp, %rbp movq 8(%rsp), %r12 # 8-byte Reload jle .LBB2_37 # %bb.36: # in Loop: Header=BB2_7 Depth=1 .cfi_escape 0x2e, 0x00 movq %rbx, %rdi movq %r12, %rsi movq %rbp, %rdx callq memmove@PLT .LBB2_37: # %_ZNSt6vectorIfSaIfEE11_S_relocateEPfS2_S2_RS0_.exit.i.i107 # in Loop: Header=BB2_7 Depth=1 testq %r12, %r12 je .LBB2_39 # %bb.38: # in Loop: Header=BB2_7 Depth=1 .cfi_escape 0x2e, 0x00 movq %r12, %rdi callq _ZdlPv .LBB2_39: # %_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_.exit.i109 # in Loop: Header=BB2_7 Depth=1 addq %rbx, %rbp leaq (%rbx,%r14,4), %r14 movq %rbx, 8(%rsp) # 8-byte Spill .LBB2_40: # %_ZNSt6vectorIfSaIfEE9push_backERKf.exit112 # in Loop: Header=BB2_7 Depth=1 leaq 304(%rsp), %r12 movq _ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax movq %rax, 5888(%rsp) movq -24(%rax), %rax movq _ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE+24(%rip), %rcx movq %rcx, 5888(%rsp,%rax) movq $_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE+16, 5904(%rsp) movq 5976(%rsp), %rdi leaq 5992(%rsp), %rax cmpq %rax, %rdi je .LBB2_6 # %bb.41: # %.critedge.i.i.i.i.i # in Loop: Header=BB2_7 Depth=1 .cfi_escape 0x2e, 0x00 callq _ZdlPv jmp .LBB2_6 .LBB2_42: movq %r13, %r15 subq (%rsp), %r15 # 8-byte Folded Reload sarq $2, %r15 xorps %xmm0, %xmm0 movaps %xmm0, 160(%rsp) movl %r15d, 176(%rsp) leal (,%r15,4), %eax movl %eax, 180(%rsp) movslq %eax, %rsi .Ltmp10: .cfi_escape 0x2e, 0x00 leaq 160(%rsp), %rdi callq hipMalloc .Ltmp11: # %bb.43: # %.noexc113 leaq 168(%rsp), %rdi movslq 180(%rsp), %rsi .Ltmp12: .cfi_escape 0x2e, 0x00 callq hipMalloc .Ltmp13: # %bb.44: # %.noexc114 movq 160(%rsp), %rdi movslq 180(%rsp), %rdx .Ltmp14: .cfi_escape 0x2e, 0x00 movq (%rsp), %rsi # 8-byte Reload movl $1, %ecx callq hipMemcpy .Ltmp15: # %bb.45: # %.noexc115 movq 168(%rsp), %rdi movslq 180(%rsp), %rdx .Ltmp16: .cfi_escape 0x2e, 0x00 movq 8(%rsp), %rsi # 8-byte Reload movl $1, %ecx callq hipMemcpy .Ltmp17: # %bb.46: # %_ZN4DataC2EiRSt6vectorIfSaIfEES3_.exit leaq 96(%rsp), %r14 movq %r14, 80(%rsp) movl $1634100580, 96(%rsp) # imm = 0x61666564 movl $1953264993, 99(%rsp) # imm = 0x746C7561 movq $7, 88(%rsp) movb $0, 103(%rsp) .Ltmp19: .cfi_escape 0x2e, 0x00 leaq 880(%rsp), %rdi leaq 80(%rsp), %rsi callq _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .Ltmp20: # %bb.47: movq 80(%rsp), %rdi cmpq %r14, %rdi je .LBB2_49 # %bb.48: # %.critedge.i.i.i .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_49: # %_ZNSt13random_deviceC2Ev.exit .Ltmp22: .cfi_escape 0x2e, 0x00 leaq 880(%rsp), %rdi callq _ZNSt13random_device9_M_getvalEv .Ltmp23: # %bb.50: # %_ZNSt13random_deviceclEv.exit movl %eax, %eax movq %rax, 5888(%rsp) movl $1, %ecx .p2align 4, 0x90 .LBB2_51: # =>This Inner Loop Header: Depth=1 movq %rax, %rdx shrq $30, %rdx xorl %eax, %edx imull $1812433253, %edx, %eax # imm = 0x6C078965 addl %ecx, %eax movq %rax, 5888(%rsp,%rcx,8) incq %rcx cmpq $624, %rcx # imm = 0x270 jne .LBB2_51 # %bb.52: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEC2Em.exit movq $624, 10880(%rsp) # imm = 0x270 .Ltmp28: .cfi_escape 0x2e, 0x00 leaq 880(%rsp), %rdi callq _ZNSt13random_device7_M_finiEv .Ltmp29: # %bb.53: # %_ZNSt13random_deviceD2Ev.exit .Ltmp31: .cfi_escape 0x2e, 0x00 leaq 5888(%rsp), %rdx movq (%rsp), %rdi # 8-byte Reload movq %r13, %rsi callq _ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_ .Ltmp32: # %bb.54: .Ltmp33: .cfi_escape 0x2e, 0x00 leaq 5888(%rsp), %rdx movq 8(%rsp), %rdi # 8-byte Reload movq %rbp, %rsi callq _ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_ .Ltmp34: # %bb.55: xorps %xmm0, %xmm0 movaps %xmm0, 16(%rsp) movq 112(%rsp), %rax # 8-byte Reload movl %eax, 32(%rsp) leal (,%rax,4), %eax movl %eax, 36(%rsp) movslq %eax, %rsi .Ltmp36: .cfi_escape 0x2e, 0x00 leaq 16(%rsp), %rdi movq (%rsp), %r12 # 8-byte Reload callq hipMalloc .Ltmp37: # %bb.56: # %.noexc118 leaq 24(%rsp), %rdi movslq 36(%rsp), %rsi .Ltmp38: .cfi_escape 0x2e, 0x00 callq hipMalloc .Ltmp39: # %bb.57: # %.noexc119 movq 16(%rsp), %rdi movslq 36(%rsp), %rdx .Ltmp40: .cfi_escape 0x2e, 0x00 movq %r12, %rsi movl $1, %ecx callq hipMemcpy .Ltmp41: # %bb.58: # %.noexc120 movq 24(%rsp), %rdi movslq 36(%rsp), %rdx .Ltmp42: .cfi_escape 0x2e, 0x00 movq 8(%rsp), %rsi # 8-byte Reload movl $1, %ecx callq hipMemcpy .Ltmp43: # %bb.59: # %_ZN4DataC2EiRSt6vectorIfSaIfEES3_.exit122 movq %r12, (%rsp) # 8-byte Spill leaq 1023(%r15), %r14 shrq $10, %r14 movl %r14d, %ebp imull 112(%rsp), %ebp # 4-byte Folded Reload xorps %xmm0, %xmm0 movaps %xmm0, 128(%rsp) movl %ebp, 144(%rsp) leal (,%rbp,4), %eax movl %eax, 148(%rsp) movslq %eax, %rsi .Ltmp45: .cfi_escape 0x2e, 0x00 leaq 128(%rsp), %rdi callq hipMalloc .Ltmp46: # %bb.60: # %.noexc123 leaq 136(%rsp), %rdi movslq 148(%rsp), %rsi .Ltmp47: .cfi_escape 0x2e, 0x00 callq hipMalloc .Ltmp48: # %bb.61: # %.noexc124 movq 128(%rsp), %rdi movslq 148(%rsp), %rdx .Ltmp49: .cfi_escape 0x2e, 0x00 xorl %esi, %esi callq hipMemset .Ltmp50: # %bb.62: # %.noexc125 movq 136(%rsp), %rdi movslq 148(%rsp), %rdx .Ltmp51: .cfi_escape 0x2e, 0x00 xorl %esi, %esi callq hipMemset .Ltmp52: # %bb.63: # %_ZN4DataC2Ei.exit movslq %ebp, %rbx shlq $2, %rbx .Ltmp54: .cfi_escape 0x2e, 0x00 leaq 240(%rsp), %rdi movq %rbx, %rsi callq hipMalloc .Ltmp55: # %bb.64: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit movq 240(%rsp), %rdi .Ltmp56: .cfi_escape 0x2e, 0x00 xorl %esi, %esi movq %rbx, %rdx callq hipMemset .Ltmp57: # %bb.65: .cfi_escape 0x2e, 0x00 callq _ZNSt6chrono3_V212system_clock3nowEv movq %rax, 344(%rsp) # 8-byte Spill shlq $32, 192(%rsp) # 8-byte Folded Spill je .LBB2_78 # %bb.66: # %.lr.ph leal (,%rbp,8), %eax movq 192(%rsp), %r13 # 8-byte Reload sarq $32, %r13 movl %r14d, %r14d movabsq $4294967296, %rcx # imm = 0x100000000 orq %rcx, %r14 movslq %eax, %r12 movl %ebp, %ebp orq %rcx, %rbp cmpq $1, %r13 adcq $0, %r13 movabsq $4294967297, %rbx # imm = 0x100000001 .p2align 4, 0x90 .LBB2_67: # =>This Inner Loop Header: Depth=1 .Ltmp59: .cfi_escape 0x2e, 0x00 movl $12288, %r8d # imm = 0x3000 movq %r14, %rdi movl $1, %esi movabsq $4294968320, %rdx # imm = 0x100000400 movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration .Ltmp60: # %bb.68: # in Loop: Header=BB2_67 Depth=1 testl %eax, %eax jne .LBB2_71 # %bb.69: # in Loop: Header=BB2_67 Depth=1 movq 160(%rsp), %rax movq %rax, 48(%rsp) movq 168(%rsp), %rax movq %rax, 120(%rsp) movl 176(%rsp), %eax movl %eax, 300(%rsp) movq 16(%rsp), %rax movq %rax, 288(%rsp) movq 24(%rsp), %rax movq %rax, 280(%rsp) movq 128(%rsp), %rax movq %rax, 272(%rsp) movq 136(%rsp), %rax movq %rax, 264(%rsp) movq 240(%rsp), %rax movq %rax, 256(%rsp) movq 112(%rsp), %rax # 8-byte Reload movl %eax, 296(%rsp) leaq 48(%rsp), %rax movq %rax, 880(%rsp) leaq 120(%rsp), %rax movq %rax, 888(%rsp) leaq 300(%rsp), %rax movq %rax, 896(%rsp) leaq 288(%rsp), %rax movq %rax, 904(%rsp) leaq 280(%rsp), %rax movq %rax, 912(%rsp) leaq 272(%rsp), %rax movq %rax, 920(%rsp) leaq 264(%rsp), %rax movq %rax, 928(%rsp) leaq 296(%rsp), %rax movq %rax, 936(%rsp) leaq 256(%rsp), %rax movq %rax, 944(%rsp) .Ltmp61: .cfi_escape 0x2e, 0x00 leaq 80(%rsp), %rdi leaq 208(%rsp), %rsi leaq 248(%rsp), %rdx leaq 352(%rsp), %rcx callq __hipPopCallConfiguration .Ltmp62: # %bb.70: # %.noexc129 # in Loop: Header=BB2_67 Depth=1 movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 208(%rsp), %rcx movl 216(%rsp), %r8d .Ltmp63: .cfi_escape 0x2e, 0x10 movl $_Z11fine_reducePKfS0_iS0_S0_PfS1_iPi, %edi leaq 880(%rsp), %r9 pushq 352(%rsp) .cfi_adjust_cfa_offset 8 pushq 256(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .Ltmp64: .LBB2_71: # in Loop: Header=BB2_67 Depth=1 .Ltmp65: .cfi_escape 0x2e, 0x00 callq hipDeviceSynchronize .Ltmp66: # %bb.72: # in Loop: Header=BB2_67 Depth=1 .Ltmp67: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi movl $1, %esi movq %rbp, %rdx movl $1, %ecx movq %r12, %r8 xorl %r9d, %r9d callq __hipPushCallConfiguration .Ltmp68: # %bb.73: # in Loop: Header=BB2_67 Depth=1 testl %eax, %eax jne .LBB2_76 # %bb.74: # in Loop: Header=BB2_67 Depth=1 movq 16(%rsp), %rax movq 24(%rsp), %rcx movq 128(%rsp), %rdx movq 136(%rsp), %rsi movq 240(%rsp), %rdi movq %rax, 48(%rsp) movq %rcx, 120(%rsp) movq %rdx, 288(%rsp) movq %rsi, 280(%rsp) movq 112(%rsp), %rax # 8-byte Reload movl %eax, 248(%rsp) movq %rdi, 272(%rsp) leaq 48(%rsp), %rax movq %rax, 880(%rsp) leaq 120(%rsp), %rax movq %rax, 888(%rsp) leaq 288(%rsp), %rax movq %rax, 896(%rsp) leaq 280(%rsp), %rax movq %rax, 904(%rsp) leaq 248(%rsp), %rax movq %rax, 912(%rsp) leaq 272(%rsp), %rax movq %rax, 920(%rsp) .Ltmp69: .cfi_escape 0x2e, 0x00 leaq 80(%rsp), %rdi leaq 208(%rsp), %rsi leaq 264(%rsp), %rdx leaq 256(%rsp), %rcx callq __hipPopCallConfiguration .Ltmp70: # %bb.75: # %.noexc137 # in Loop: Header=BB2_67 Depth=1 movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 208(%rsp), %rcx movl 216(%rsp), %r8d .Ltmp71: .cfi_escape 0x2e, 0x10 movl $_Z13coarse_reducePfS_S_S_iPi, %edi leaq 880(%rsp), %r9 pushq 256(%rsp) .cfi_adjust_cfa_offset 8 pushq 272(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .Ltmp72: .LBB2_76: # in Loop: Header=BB2_67 Depth=1 .Ltmp73: .cfi_escape 0x2e, 0x00 callq hipDeviceSynchronize .Ltmp74: # %bb.77: # in Loop: Header=BB2_67 Depth=1 decq %r13 jne .LBB2_67 .LBB2_78: # %._crit_edge346 .cfi_escape 0x2e, 0x00 callq _ZNSt6chrono3_V212system_clock3nowEv movq %rax, %rbx .Ltmp76: .cfi_escape 0x2e, 0x00 movl $_ZSt4cerr, %edi movl $.L.str.1, %esi movl $35, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp77: # %bb.79: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit subq 344(%rsp), %rbx # 8-byte Folded Reload xorps %xmm0, %xmm0 cvtsi2ss %rbx, %xmm0 divss .LCPI2_0(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 .Ltmp78: .cfi_escape 0x2e, 0x00 movl $_ZSt4cerr, %edi movsd %xmm0, 192(%rsp) # 8-byte Spill callq _ZNSo9_M_insertIdEERSoT_ .Ltmp79: # %bb.80: # %_ZNSolsEf.exit .Ltmp80: movq %rax, %rbx .cfi_escape 0x2e, 0x00 movl $.L.str.2, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp81: # %bb.81: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit142 .Ltmp82: .cfi_escape 0x2e, 0x00 movl $.L.str.3, %esi movl $5, %edx movq %rbx, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp83: # %bb.82: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit144 .Ltmp84: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi movq %r15, %rsi callq _ZNSo9_M_insertImEERSoT_ .Ltmp85: # %bb.83: # %_ZNSolsEm.exit .Ltmp86: movq %rax, %rbx .cfi_escape 0x2e, 0x00 movl $.L.str.4, %esi movl $8, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp87: # %bb.84: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit147 movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB2_188 # %bb.85: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i219 cmpb $0, 56(%r14) je .LBB2_87 # %bb.86: movzbl 67(%r14), %eax jmp .LBB2_89 .LBB2_87: .Ltmp88: .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv .Ltmp89: # %bb.88: # %.noexc224 movq (%r14), %rax .Ltmp90: .cfi_escape 0x2e, 0x00 movq %r14, %rdi movl $10, %esi callq *48(%rax) .Ltmp91: .LBB2_89: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i221 .Ltmp92: .cfi_escape 0x2e, 0x00 movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc .Ltmp93: # %bb.90: # %.noexc226 .Ltmp94: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq _ZNSo5flushEv .Ltmp95: # %bb.91: # %_ZNSolsEPFRSoS_E.exit movsd 192(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero movsd %xmm0, std_time_used(%rip) movq 240(%rsp), %rdi .Ltmp96: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp97: # %bb.92: shlq $32, 200(%rsp) # 8-byte Folded Spill js .LBB2_190 # %bb.93: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit.i je .LBB2_96 # %bb.94: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i movq 200(%rsp), %rdi # 8-byte Reload shrq $30, %rdi .Ltmp98: .cfi_escape 0x2e, 0x00 callq _Znwm .Ltmp99: # %bb.95: movq %rax, %r13 jmp .LBB2_97 .LBB2_96: xorl %r13d, %r13d .LBB2_97: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i movq 200(%rsp), %rbx # 8-byte Reload testq %rbx, %rbx je .LBB2_100 # %bb.98: # %.lr.ph.i.i.i.i.i.i.i.i.i.preheader shrq $30, %rbx .cfi_escape 0x2e, 0x00 movq %r13, %rdi xorl %esi, %esi movq %rbx, %rdx callq memset@PLT .Ltmp100: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _Znwm .Ltmp101: # %bb.99: movq %rax, %rbp jmp .LBB2_101 .LBB2_100: xorl %ebp, %ebp .LBB2_101: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i154 movq 200(%rsp), %rdx # 8-byte Reload testq %rdx, %rdx je .LBB2_103 # %bb.102: # %.lr.ph.i.i.i.i.i.i.i.i.i155.preheader shrq $30, %rdx .cfi_escape 0x2e, 0x00 movq %rbp, %rdi xorl %esi, %esi callq memset@PLT .LBB2_103: # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit161 movq 16(%rsp), %rsi movslq 36(%rsp), %rdx .Ltmp103: .cfi_escape 0x2e, 0x00 movq %r13, %rdi movl $2, %ecx callq hipMemcpy .Ltmp104: # %bb.104: movq 24(%rsp), %rsi movslq 36(%rsp), %rdx .Ltmp105: .cfi_escape 0x2e, 0x00 movq %rbp, %rdi movl $2, %ecx callq hipMemcpy .Ltmp106: # %bb.105: # %.preheader.preheader .cfi_escape 0x2e, 0x00 movl $.L.str.5, %edi movl $.L.str.6, %esi callq fopen movq %rax, %rbx movsd std_time_used(%rip), %xmm0 # xmm0 = mem[0],zero .cfi_escape 0x2e, 0x00 movl $.L.str.7, %esi movq %rax, %rdi movb $1, %al callq fprintf .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq fclose movl $1, %esi cmpq $10, %r15 jb .LBB2_114 # %bb.106: # %.lr.ph.i.i.preheader movl $4, %esi movabsq $3777893186295716171, %rdi # imm = 0x346DC5D63886594B movq %r15, %rcx .p2align 4, 0x90 .LBB2_107: # %.lr.ph.i.i # =>This Inner Loop Header: Depth=1 cmpq $99, %rcx jbe .LBB2_112 # %bb.108: # in Loop: Header=BB2_107 Depth=1 cmpq $999, %rcx # imm = 0x3E7 jbe .LBB2_113 # %bb.109: # in Loop: Header=BB2_107 Depth=1 cmpq $10000, %rcx # imm = 0x2710 jb .LBB2_114 # %bb.110: # in Loop: Header=BB2_107 Depth=1 movq %rcx, %rax mulq %rdi shrq $11, %rdx addl $4, %esi cmpq $99999, %rcx # imm = 0x1869F movq %rdx, %rcx ja .LBB2_107 # %bb.111: # %_ZNSt8__detail14__to_chars_lenImEEjT_i.exit.i.loopexit addl $-3, %esi jmp .LBB2_114 .LBB2_112: addl $-2, %esi jmp .LBB2_114 .LBB2_113: decl %esi .LBB2_114: # %_ZNSt8__detail14__to_chars_lenImEEjT_i.exit.i movl %esi, %ebx leaq 896(%rsp), %r14 movq %r14, 880(%rsp) cmpl $16, %esi jb .LBB2_117 # %bb.115: # %.noexc.i leaq 1(%rbx), %rdi .Ltmp108: .cfi_escape 0x2e, 0x00 callq _Znwm .Ltmp109: # %bb.116: # %.noexc163 movq %rax, 880(%rsp) movq %rbx, 896(%rsp) .LBB2_117: testq %rbx, %rbx je .LBB2_121 # %bb.118: movq 880(%rsp), %rdi cmpl $1, %ebx jne .LBB2_120 # %bb.119: movb $0, (%rdi) jmp .LBB2_121 .LBB2_120: .cfi_escape 0x2e, 0x00 xorl %esi, %esi movq %rbx, %rdx callq memset@PLT .LBB2_121: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEmcRKS3_.exit.i movq %rbx, 888(%rsp) movq 880(%rsp), %rax movb $0, (%rax,%rbx) movq 880(%rsp), %rcx cmpq $100, %r15 jb .LBB2_126 # %bb.122: # %.lr.ph.preheader.i.i movl 888(%rsp), %esi addl $-2, %esi movabsq $2951479051793528259, %rdi # imm = 0x28F5C28F5C28F5C3 .p2align 4, 0x90 .LBB2_123: # %.lr.ph.i4.i # =>This Inner Loop Header: Depth=1 leal 1(%rsi), %r8d movq %r15, %rax shrq $2, %rax mulq %rdi shrq $2, %rdx imull $100, %edx, %eax movl %r15d, %r9d subl %eax, %r9d movzbl .L__const._ZNSt8__detail18__to_chars_10_implImEEvPcjT_.__digits+1(%r9,%r9), %eax movb %al, (%rcx,%r8) movzbl .L__const._ZNSt8__detail18__to_chars_10_implImEEvPcjT_.__digits(%r9,%r9), %eax movl %esi, %r8d movb %al, (%rcx,%r8) addl $-2, %esi cmpq $9999, %r15 # imm = 0x270F movq %rdx, %r15 ja .LBB2_123 # %bb.124: # %._crit_edge.i.i cmpq $10, %rdx jb .LBB2_127 .LBB2_125: movzbl .L__const._ZNSt8__detail18__to_chars_10_implImEEvPcjT_.__digits+1(%rdx,%rdx), %eax movb %al, 1(%rcx) movzbl .L__const._ZNSt8__detail18__to_chars_10_implImEEvPcjT_.__digits(%rdx,%rdx), %edx jmp .LBB2_128 .LBB2_126: movq %r15, %rdx cmpq $10, %rdx jae .LBB2_125 .LBB2_127: orb $48, %dl .LBB2_128: # %_ZNSt7__cxx119to_stringEm.exit leaq 96(%rsp), %rax movb %dl, (%rcx) movq %rax, 80(%rsp) movq $0, 88(%rsp) movb $0, 96(%rsp) leaq 224(%rsp), %r12 movq %r12, 208(%rsp) movq $0, 216(%rsp) movb $0, 224(%rsp) movq 880(%rsp), %rcx movq 888(%rsp), %r8 .Ltmp111: .cfi_escape 0x2e, 0x00 leaq 48(%rsp), %rdi leaq 120(%rsp), %r9 movl $.L.str.8, %esi movl $17, %edx callq _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE .Ltmp112: # %bb.129: # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_RKS8_.exit movq 880(%rsp), %rdi movq 48(%rsp), %rsi leaq 64(%rsp), %rbx cmpq %rbx, %rsi je .LBB2_133 # %bb.130: # %.critedge.i movq 896(%rsp), %rax movq %rsi, 880(%rsp) movups 56(%rsp), %xmm0 movups %xmm0, 888(%rsp) cmpq %r14, %rdi je .LBB2_136 # %bb.131: # %.critedge.i testq %rdi, %rdi je .LBB2_136 # %bb.132: movq %rdi, 48(%rsp) movq %rax, 64(%rsp) jmp .LBB2_139 .LBB2_133: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit23.i movq 56(%rsp), %rdx testq %rdx, %rdx je .LBB2_138 # %bb.134: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit23.i cmpq $1, %rdx jne .LBB2_137 # %bb.135: movzbl (%rsi), %eax movb %al, (%rdi) jmp .LBB2_138 .LBB2_136: movq %rbx, 48(%rsp) jmp .LBB2_139 .LBB2_137: .cfi_escape 0x2e, 0x00 callq memcpy@PLT .LBB2_138: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit.i movq 56(%rsp), %rax movq %rax, 888(%rsp) movq 880(%rsp), %rcx movb $0, (%rcx,%rax) .LBB2_139: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEOS4_.exit movq $0, 56(%rsp) movq 48(%rsp), %rax movb $0, (%rax) movq 48(%rsp), %rdi cmpq %rbx, %rdi je .LBB2_141 # %bb.140: # %.critedge.i.i .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_141: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit movq 880(%rsp), %rsi movq 888(%rsp), %rdx .Ltmp114: .cfi_escape 0x2e, 0x00 leaq 48(%rsp), %rdi leaq 120(%rsp), %r9 movl $.L.str.9, %ecx movl $14, %r8d callq _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE .Ltmp115: # %bb.142: # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_.exit movq 208(%rsp), %rdi movq 48(%rsp), %rsi cmpq %rbx, %rsi je .LBB2_146 # %bb.143: # %.critedge.i168 movq 224(%rsp), %rax movq %rsi, 208(%rsp) movups 56(%rsp), %xmm0 movups %xmm0, 216(%rsp) movq %r12, %r15 cmpq %r12, %rdi je .LBB2_149 # %bb.144: # %.critedge.i168 testq %rdi, %rdi je .LBB2_149 # %bb.145: movq %rdi, 48(%rsp) movq %rax, 64(%rsp) jmp .LBB2_152 .LBB2_146: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit23.i171 movq 56(%rsp), %rdx testq %rdx, %rdx je .LBB2_151 # %bb.147: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit23.i171 cmpq $1, %rdx jne .LBB2_150 # %bb.148: movzbl (%rsi), %eax movb %al, (%rdi) jmp .LBB2_151 .LBB2_149: movq %rbx, 48(%rsp) jmp .LBB2_152 .LBB2_150: .cfi_escape 0x2e, 0x00 callq memcpy@PLT .LBB2_151: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit.i172 movq %r12, %r15 movq 56(%rsp), %rax movq %rax, 216(%rsp) movq 208(%rsp), %rcx movb $0, (%rcx,%rax) .LBB2_152: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEOS4_.exit173 movq $0, 56(%rsp) movq 48(%rsp), %rax movb $0, (%rax) movq 48(%rsp), %rdi cmpq %rbx, %rdi je .LBB2_154 # %bb.153: # %.critedge.i.i174 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_154: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit176 movq 208(%rsp), %rdi .cfi_escape 0x2e, 0x00 movl $.L.str.10, %esi callq fopen movq %rax, %rbx cmpl $0, 112(%rsp) # 4-byte Folded Reload jle .LBB2_157 # %bb.155: # %.lr.ph348.preheader movl 336(%rsp), %r12d # 4-byte Reload xorl %r14d, %r14d .p2align 4, 0x90 .LBB2_156: # %.lr.ph348 # =>This Inner Loop Header: Depth=1 movss (%r13,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movss (%rbp,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero cvtss2sd %xmm1, %xmm1 .cfi_escape 0x2e, 0x00 movl $.L.str.11, %esi movq %rbx, %rdi movb $2, %al callq fprintf incq %r14 cmpq %r14, %r12 jne .LBB2_156 .LBB2_157: # %._crit_edge349 .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq fclose movq 208(%rsp), %rdi cmpq %r15, %rdi je .LBB2_159 # %bb.158: # %.critedge.i.i177 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_159: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit179 movq 80(%rsp), %rdi leaq 96(%rsp), %rax cmpq %rax, %rdi movq 8(%rsp), %r14 # 8-byte Reload leaq 896(%rsp), %r15 je .LBB2_161 # %bb.160: # %.critedge.i.i180 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_161: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit182 movq 880(%rsp), %rdi cmpq %r15, %rdi je .LBB2_163 # %bb.162: # %.critedge.i.i183 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_163: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit185 testq %rbp, %rbp je .LBB2_165 # %bb.164: .cfi_escape 0x2e, 0x00 movq %rbp, %rdi callq _ZdlPv .LBB2_165: # %_ZNSt6vectorIfSaIfEED2Ev.exit testq %r13, %r13 je .LBB2_167 # %bb.166: .cfi_escape 0x2e, 0x00 movq %r13, %rdi callq _ZdlPv .LBB2_167: # %_ZNSt6vectorIfSaIfEED2Ev.exit188 movq 128(%rsp), %rdi .Ltmp117: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp118: # %bb.168: movq 136(%rsp), %rdi .Ltmp119: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp120: # %bb.169: # %_ZN4DataD2Ev.exit movq 16(%rsp), %rdi .Ltmp122: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp123: movq (%rsp), %rbx # 8-byte Reload # %bb.170: movq 24(%rsp), %rdi .Ltmp124: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp125: # %bb.171: # %_ZN4DataD2Ev.exit189 movq 160(%rsp), %rdi .Ltmp127: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp128: # %bb.172: movq 168(%rsp), %rdi .Ltmp129: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp130: # %bb.173: # %_ZN4DataD2Ev.exit190 movq 304(%rsp), %rdi leaq 320(%rsp), %rax cmpq %rax, %rdi je .LBB2_175 # %bb.174: # %.critedge.i.i191 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_175: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit193 .cfi_escape 0x2e, 0x00 leaq 360(%rsp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq 616(%rsp), %rdi .cfi_escape 0x2e, 0x00 callq _ZNSt8ios_baseD2Ev testq %r14, %r14 je .LBB2_177 # %bb.176: .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _ZdlPv .LBB2_177: # %_ZNSt6vectorIfSaIfEED2Ev.exit195 testq %rbx, %rbx je .LBB2_179 # %bb.178: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _ZdlPv .LBB2_179: # %_ZNSt6vectorIfSaIfEED2Ev.exit197 xorl %eax, %eax addq $10888, %rsp # imm = 0x2A88 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_180: .cfi_def_cfa_offset 10944 .Ltmp154: .cfi_escape 0x2e, 0x00 movl $.L.str.12, %edi callq _ZSt20__throw_length_errorPKc .Ltmp155: # %bb.181: # %.noexc100 .LBB2_182: .Ltmp152: .cfi_escape 0x2e, 0x00 movl $.L.str.12, %edi callq _ZSt20__throw_length_errorPKc .Ltmp153: # %bb.183: # %.noexc110 .LBB2_184: .cfi_escape 0x2e, 0x00 movl $_ZSt4cerr, %edi movl $.L.str, %esi callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_ .cfi_escape 0x2e, 0x00 movl $1, %edi callq exit .LBB2_185: xorl %eax, %eax movq %rax, 8(%rsp) # 8-byte Spill xorl %eax, %eax movq %rax, (%rsp) # 8-byte Spill .LBB2_186: # %._crit_edge .Ltmp157: .cfi_escape 0x2e, 0x00 callq _ZSt16__throw_bad_castv .Ltmp158: # %bb.187: # %.noexc .LBB2_188: .Ltmp135: .cfi_escape 0x2e, 0x00 callq _ZSt16__throw_bad_castv .Ltmp136: # %bb.189: # %.noexc223 .LBB2_190: .Ltmp132: .cfi_escape 0x2e, 0x00 movl $.L.str.16, %edi callq _ZSt20__throw_length_errorPKc .Ltmp133: # %bb.191: # %.noexc149 .LBB2_192: .Ltmp110: jmp .LBB2_215 .LBB2_193: .Ltmp102: movq %rax, %rbx testq %r13, %r13 jne .LBB2_217 jmp .LBB2_218 .LBB2_194: .Ltmp116: jmp .LBB2_196 .LBB2_195: .Ltmp113: .LBB2_196: movq %rax, %rbx movq 208(%rsp), %rdi cmpq %r12, %rdi je .LBB2_198 # %bb.197: # %.critedge.i.i198 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_198: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit200 movq 80(%rsp), %rdi leaq 96(%rsp), %rax cmpq %rax, %rdi je .LBB2_200 # %bb.199: # %.critedge.i.i201 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_200: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit203 movq 880(%rsp), %rdi cmpq %r14, %rdi jne .LBB2_203 # %bb.201: testq %rbp, %rbp jne .LBB2_216 .LBB2_202: # %_ZNSt6vectorIfSaIfEED2Ev.exit208 testq %r13, %r13 jne .LBB2_217 jmp .LBB2_218 .LBB2_203: # %.critedge.i.i204 .cfi_escape 0x2e, 0x00 callq _ZdlPv testq %rbp, %rbp je .LBB2_202 jmp .LBB2_216 .LBB2_204: .Ltmp30: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq __clang_call_terminate .LBB2_205: .Ltmp24: movq %rax, %rbx .Ltmp25: .cfi_escape 0x2e, 0x00 leaq 880(%rsp), %rdi callq _ZNSt13random_device7_M_finiEv .Ltmp26: jmp .LBB2_221 .LBB2_206: .Ltmp27: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq __clang_call_terminate .LBB2_207: .Ltmp21: movq %rax, %rbx movq 80(%rsp), %rdi cmpq %r14, %rdi je .LBB2_221 # %bb.208: # %.critedge.i.i6.i .cfi_escape 0x2e, 0x00 callq _ZdlPv jmp .LBB2_221 .LBB2_209: .Ltmp2: movq %rax, %rbx xorl %r14d, %r14d xorl %r12d, %r12d jmp .LBB2_241 .LBB2_210: .Ltmp134: movq %rax, %rbx jmp .LBB2_218 .LBB2_211: .Ltmp131: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq __clang_call_terminate .LBB2_212: .Ltmp126: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq __clang_call_terminate .LBB2_213: .Ltmp121: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq __clang_call_terminate .LBB2_214: .Ltmp107: .LBB2_215: movq %rax, %rbx testq %rbp, %rbp je .LBB2_202 .LBB2_216: .cfi_escape 0x2e, 0x00 movq %rbp, %rdi callq _ZdlPv testq %r13, %r13 je .LBB2_218 .LBB2_217: .cfi_escape 0x2e, 0x00 movq %r13, %rdi callq _ZdlPv .LBB2_218: # %_ZNSt6vectorIfSaIfEED2Ev.exit210 movq (%rsp), %r12 # 8-byte Reload movq 8(%rsp), %r14 # 8-byte Reload jmp .LBB2_235 .LBB2_219: .Ltmp58: jmp .LBB2_234 .LBB2_220: .Ltmp35: movq %rax, %rbx .LBB2_221: # %_ZNSt13random_deviceD2Ev.exit128 movq (%rsp), %r12 # 8-byte Reload movq 8(%rsp), %r14 # 8-byte Reload jmp .LBB2_237 .LBB2_222: .Ltmp53: movq %rax, %rbx movq 8(%rsp), %r14 # 8-byte Reload movq (%rsp), %r12 # 8-byte Reload jmp .LBB2_236 .LBB2_223: .Ltmp44: movq %rax, %rbx movq 8(%rsp), %r14 # 8-byte Reload jmp .LBB2_237 .LBB2_224: .Ltmp18: jmp .LBB2_230 .LBB2_225: .Ltmp137: jmp .LBB2_234 .LBB2_226: # %.loopexit.split-lp280 .Ltmp156: jmp .LBB2_232 .LBB2_227: .Ltmp140: jmp .LBB2_230 .LBB2_228: # %.loopexit.split-lp .Ltmp159: jmp .LBB2_230 .LBB2_229: # %.loopexit .Ltmp9: .LBB2_230: movq %rax, %rbx movq (%rsp), %r12 # 8-byte Reload movq 8(%rsp), %r14 # 8-byte Reload jmp .LBB2_238 .LBB2_231: # %.loopexit279 .Ltmp151: .LBB2_232: movq %rax, %rbx movq (%rsp), %r12 # 8-byte Reload movq 8(%rsp), %r14 # 8-byte Reload .cfi_escape 0x2e, 0x00 leaq 5888(%rsp), %rdi callq _ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev jmp .LBB2_238 .LBB2_233: .Ltmp75: .LBB2_234: # %_ZNSt6vectorIfSaIfEED2Ev.exit210 movq %rax, %rbx movq 8(%rsp), %r14 # 8-byte Reload movq (%rsp), %r12 # 8-byte Reload .LBB2_235: # %_ZNSt6vectorIfSaIfEED2Ev.exit210 .cfi_escape 0x2e, 0x00 leaq 128(%rsp), %rdi callq _ZN4DataD2Ev .LBB2_236: .cfi_escape 0x2e, 0x00 leaq 16(%rsp), %rdi callq _ZN4DataD2Ev .LBB2_237: .cfi_escape 0x2e, 0x00 leaq 160(%rsp), %rdi callq _ZN4DataD2Ev .LBB2_238: movq 304(%rsp), %rdi leaq 320(%rsp), %rax cmpq %rax, %rdi je .LBB2_240 # %bb.239: # %.critedge.i.i211 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_240: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit213 .cfi_escape 0x2e, 0x00 leaq 360(%rsp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq 616(%rsp), %rdi .cfi_escape 0x2e, 0x00 callq _ZNSt8ios_baseD2Ev .LBB2_241: testq %r14, %r14 jne .LBB2_244 # %bb.242: # %_ZNSt6vectorIfSaIfEED2Ev.exit215 testq %r12, %r12 jne .LBB2_245 .LBB2_243: # %_ZNSt6vectorIfSaIfEED2Ev.exit217 .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _Unwind_Resume@PLT .LBB2_244: .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _ZdlPv testq %r12, %r12 je .LBB2_243 .LBB2_245: .cfi_escape 0x2e, 0x00 movq %r12, %rdi callq _ZdlPv .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _Unwind_Resume@PLT .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table2: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase0-.Lttbaseref0 .Lttbaseref0: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1 .uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2 .byte 0 # On action: cleanup .uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp8-.Ltmp3 # Call between .Ltmp3 and .Ltmp8 .uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9 .byte 0 # On action: cleanup .uleb128 .Ltmp138-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp139-.Ltmp138 # Call between .Ltmp138 and .Ltmp139 .uleb128 .Ltmp140-.Lfunc_begin0 # jumps to .Ltmp140 .byte 0 # On action: cleanup .uleb128 .Ltmp141-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp148-.Ltmp141 # Call between .Ltmp141 and .Ltmp148 .uleb128 .Ltmp151-.Lfunc_begin0 # jumps to .Ltmp151 .byte 0 # On action: cleanup .uleb128 .Ltmp148-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp149-.Ltmp148 # Call between .Ltmp148 and .Ltmp149 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp149-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Ltmp150-.Ltmp149 # Call between .Ltmp149 and .Ltmp150 .uleb128 .Ltmp151-.Lfunc_begin0 # jumps to .Ltmp151 .byte 0 # On action: cleanup .uleb128 .Ltmp150-.Lfunc_begin0 # >> Call Site 7 << .uleb128 .Ltmp10-.Ltmp150 # Call between .Ltmp150 and .Ltmp10 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 8 << .uleb128 .Ltmp17-.Ltmp10 # Call between .Ltmp10 and .Ltmp17 .uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18 .byte 0 # On action: cleanup .uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 9 << .uleb128 .Ltmp20-.Ltmp19 # Call between .Ltmp19 and .Ltmp20 .uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21 .byte 0 # On action: cleanup .uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 10 << .uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23 .uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24 .byte 0 # On action: cleanup .uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 11 << .uleb128 .Ltmp29-.Ltmp28 # Call between .Ltmp28 and .Ltmp29 .uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30 .byte 1 # On action: 1 .uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 12 << .uleb128 .Ltmp34-.Ltmp31 # Call between .Ltmp31 and .Ltmp34 .uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35 .byte 0 # On action: cleanup .uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 13 << .uleb128 .Ltmp43-.Ltmp36 # Call between .Ltmp36 and .Ltmp43 .uleb128 .Ltmp44-.Lfunc_begin0 # jumps to .Ltmp44 .byte 0 # On action: cleanup .uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 14 << .uleb128 .Ltmp52-.Ltmp45 # Call between .Ltmp45 and .Ltmp52 .uleb128 .Ltmp53-.Lfunc_begin0 # jumps to .Ltmp53 .byte 0 # On action: cleanup .uleb128 .Ltmp54-.Lfunc_begin0 # >> Call Site 15 << .uleb128 .Ltmp57-.Ltmp54 # Call between .Ltmp54 and .Ltmp57 .uleb128 .Ltmp58-.Lfunc_begin0 # jumps to .Ltmp58 .byte 0 # On action: cleanup .uleb128 .Ltmp59-.Lfunc_begin0 # >> Call Site 16 << .uleb128 .Ltmp74-.Ltmp59 # Call between .Ltmp59 and .Ltmp74 .uleb128 .Ltmp75-.Lfunc_begin0 # jumps to .Ltmp75 .byte 0 # On action: cleanup .uleb128 .Ltmp76-.Lfunc_begin0 # >> Call Site 17 << .uleb128 .Ltmp97-.Ltmp76 # Call between .Ltmp76 and .Ltmp97 .uleb128 .Ltmp137-.Lfunc_begin0 # jumps to .Ltmp137 .byte 0 # On action: cleanup .uleb128 .Ltmp98-.Lfunc_begin0 # >> Call Site 18 << .uleb128 .Ltmp99-.Ltmp98 # Call between .Ltmp98 and .Ltmp99 .uleb128 .Ltmp134-.Lfunc_begin0 # jumps to .Ltmp134 .byte 0 # On action: cleanup .uleb128 .Ltmp99-.Lfunc_begin0 # >> Call Site 19 << .uleb128 .Ltmp100-.Ltmp99 # Call between .Ltmp99 and .Ltmp100 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp100-.Lfunc_begin0 # >> Call Site 20 << .uleb128 .Ltmp101-.Ltmp100 # Call between .Ltmp100 and .Ltmp101 .uleb128 .Ltmp102-.Lfunc_begin0 # jumps to .Ltmp102 .byte 0 # On action: cleanup .uleb128 .Ltmp101-.Lfunc_begin0 # >> Call Site 21 << .uleb128 .Ltmp103-.Ltmp101 # Call between .Ltmp101 and .Ltmp103 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp103-.Lfunc_begin0 # >> Call Site 22 << .uleb128 .Ltmp106-.Ltmp103 # Call between .Ltmp103 and .Ltmp106 .uleb128 .Ltmp107-.Lfunc_begin0 # jumps to .Ltmp107 .byte 0 # On action: cleanup .uleb128 .Ltmp108-.Lfunc_begin0 # >> Call Site 23 << .uleb128 .Ltmp109-.Ltmp108 # Call between .Ltmp108 and .Ltmp109 .uleb128 .Ltmp110-.Lfunc_begin0 # jumps to .Ltmp110 .byte 0 # On action: cleanup .uleb128 .Ltmp109-.Lfunc_begin0 # >> Call Site 24 << .uleb128 .Ltmp111-.Ltmp109 # Call between .Ltmp109 and .Ltmp111 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp111-.Lfunc_begin0 # >> Call Site 25 << .uleb128 .Ltmp112-.Ltmp111 # Call between .Ltmp111 and .Ltmp112 .uleb128 .Ltmp113-.Lfunc_begin0 # jumps to .Ltmp113 .byte 0 # On action: cleanup .uleb128 .Ltmp112-.Lfunc_begin0 # >> Call Site 26 << .uleb128 .Ltmp114-.Ltmp112 # Call between .Ltmp112 and .Ltmp114 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp114-.Lfunc_begin0 # >> Call Site 27 << .uleb128 .Ltmp115-.Ltmp114 # Call between .Ltmp114 and .Ltmp115 .uleb128 .Ltmp116-.Lfunc_begin0 # jumps to .Ltmp116 .byte 0 # On action: cleanup .uleb128 .Ltmp115-.Lfunc_begin0 # >> Call Site 28 << .uleb128 .Ltmp117-.Ltmp115 # Call between .Ltmp115 and .Ltmp117 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp117-.Lfunc_begin0 # >> Call Site 29 << .uleb128 .Ltmp120-.Ltmp117 # Call between .Ltmp117 and .Ltmp120 .uleb128 .Ltmp121-.Lfunc_begin0 # jumps to .Ltmp121 .byte 1 # On action: 1 .uleb128 .Ltmp122-.Lfunc_begin0 # >> Call Site 30 << .uleb128 .Ltmp125-.Ltmp122 # Call between .Ltmp122 and .Ltmp125 .uleb128 .Ltmp126-.Lfunc_begin0 # jumps to .Ltmp126 .byte 1 # On action: 1 .uleb128 .Ltmp127-.Lfunc_begin0 # >> Call Site 31 << .uleb128 .Ltmp130-.Ltmp127 # Call between .Ltmp127 and .Ltmp130 .uleb128 .Ltmp131-.Lfunc_begin0 # jumps to .Ltmp131 .byte 1 # On action: 1 .uleb128 .Ltmp154-.Lfunc_begin0 # >> Call Site 32 << .uleb128 .Ltmp153-.Ltmp154 # Call between .Ltmp154 and .Ltmp153 .uleb128 .Ltmp156-.Lfunc_begin0 # jumps to .Ltmp156 .byte 0 # On action: cleanup .uleb128 .Ltmp153-.Lfunc_begin0 # >> Call Site 33 << .uleb128 .Ltmp157-.Ltmp153 # Call between .Ltmp153 and .Ltmp157 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp157-.Lfunc_begin0 # >> Call Site 34 << .uleb128 .Ltmp158-.Ltmp157 # Call between .Ltmp157 and .Ltmp158 .uleb128 .Ltmp159-.Lfunc_begin0 # jumps to .Ltmp159 .byte 0 # On action: cleanup .uleb128 .Ltmp135-.Lfunc_begin0 # >> Call Site 35 << .uleb128 .Ltmp136-.Ltmp135 # Call between .Ltmp135 and .Ltmp136 .uleb128 .Ltmp137-.Lfunc_begin0 # jumps to .Ltmp137 .byte 0 # On action: cleanup .uleb128 .Ltmp132-.Lfunc_begin0 # >> Call Site 36 << .uleb128 .Ltmp133-.Ltmp132 # Call between .Ltmp132 and .Ltmp133 .uleb128 .Ltmp134-.Lfunc_begin0 # jumps to .Ltmp134 .byte 0 # On action: cleanup .uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 37 << .uleb128 .Ltmp26-.Ltmp25 # Call between .Ltmp25 and .Ltmp26 .uleb128 .Ltmp27-.Lfunc_begin0 # jumps to .Ltmp27 .byte 1 # On action: 1 .uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 38 << .uleb128 .Lfunc_end2-.Ltmp26 # Call between .Ltmp26 and .Lfunc_end2 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase0: .p2align 2, 0x0 # -- End function .section .text._ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_,"axG",@progbits,_ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_,comdat .weak _ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_ # -- Begin function _ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_ .p2align 4, 0x90 .type _ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_,@function _ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_: # @_ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_ .cfi_startproc # %bb.0: cmpq %rsi, %rdi je .LBB3_12 # %bb.1: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $40, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %r14 movq %rdi, %r15 movq %rdx, %r12 movq %rsi, %rcx subq %rdi, %rcx movq %rcx, %rsi sarq $2, %rsi movl $4294967295, %eax # imm = 0xFFFFFFFF xorl %edx, %edx divq %rsi cmpq %rsi, %rax jae .LBB3_2 # %bb.8: movq $0, 8(%rsp) movq $-1, 16(%rsp) leaq 4(%r15), %rax cmpq %r14, %rax je .LBB3_11 # %bb.9: # %.lr.ph42 movq %r12, %rbx movl $4, %ebp leaq 8(%rsp), %r12 leaq 24(%rsp), %r13 .p2align 4, 0x90 .LBB3_10: # =>This Inner Loop Header: Depth=1 movq %rbp, %rax sarq $2, %rax movq $0, 24(%rsp) movq %rax, 32(%rsp) movq %r12, %rdi movq %rbx, %rsi movq %r13, %rdx callq _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE movss (%r15,%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero movss (%r15,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero movss %xmm1, (%r15,%rbp) movss %xmm0, (%r15,%rax,4) leaq (%r15,%rbp), %rax addq $4, %rax addq $4, %rbp cmpq %r14, %rax jne .LBB3_10 jmp .LBB3_11 .LBB3_2: testb $4, %cl jne .LBB3_3 # %bb.4: movq %r12, %rsi movq $0, 8(%rsp) movq $1, 16(%rsp) leaq 8(%r15), %r13 leaq 8(%rsp), %rdi movq %rdi, %rdx callq _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE movss 4(%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero movss (%r15,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero movss %xmm1, 4(%r15) movss %xmm0, (%r15,%rax,4) cmpq %r14, %r13 jne .LBB3_6 jmp .LBB3_11 .LBB3_3: leaq 4(%r15), %r13 cmpq %r14, %r13 je .LBB3_11 .LBB3_6: # %.lr.ph movq %r13, %rbx subq %r15, %rbx .p2align 4, 0x90 .LBB3_7: # =>This Inner Loop Header: Depth=1 movq %rbx, %rbp sarq $2, %rbp leaq 1(%rbp), %rax addq $2, %rbp imulq %rbp, %rax decq %rax movq $0, 8(%rsp) movq %rax, 16(%rsp) leaq 8(%rsp), %rdi movq %r12, %rsi movq %rdi, %rdx callq _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE xorl %edx, %edx divq %rbp movss (%r13), %xmm0 # xmm0 = mem[0],zero,zero,zero movss (%r15,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero movss %xmm1, (%r13) movss %xmm0, (%r15,%rax,4) movss 4(%r13), %xmm0 # xmm0 = mem[0],zero,zero,zero movss (%r15,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero movss %xmm1, 4(%r13) movss %xmm0, (%r15,%rdx,4) addq $8, %rbx addq $8, %r13 cmpq %r14, %r13 jne .LBB3_7 .LBB3_11: addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 .cfi_restore %rbx .cfi_restore %r12 .cfi_restore %r13 .cfi_restore %r14 .cfi_restore %r15 .cfi_restore %rbp .LBB3_12: # %.loopexit retq .Lfunc_end3: .size _ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_, .Lfunc_end3-_ZSt7shuffleIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEERSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEvT_SA_OT0_ .cfi_endproc # -- End function .section .text._ZN4DataD2Ev,"axG",@progbits,_ZN4DataD2Ev,comdat .weak _ZN4DataD2Ev # -- Begin function _ZN4DataD2Ev .p2align 4, 0x90 .type _ZN4DataD2Ev,@function _ZN4DataD2Ev: # @_ZN4DataD2Ev .Lfunc_begin1: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception1 # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq %rdi, %rbx movq (%rdi), %rdi .Ltmp160: callq hipFree .Ltmp161: # %bb.1: movq 8(%rbx), %rdi .Ltmp162: callq hipFree .Ltmp163: # %bb.2: popq %rbx .cfi_def_cfa_offset 8 retq .LBB4_3: .cfi_def_cfa_offset 16 .Ltmp164: movq %rax, %rdi callq __clang_call_terminate .Lfunc_end4: .size _ZN4DataD2Ev, .Lfunc_end4-_ZN4DataD2Ev .cfi_endproc .section .gcc_except_table._ZN4DataD2Ev,"aG",@progbits,_ZN4DataD2Ev,comdat .p2align 2, 0x0 GCC_except_table4: .Lexception1: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase1-.Lttbaseref1 .Lttbaseref1: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end1-.Lcst_begin1 .Lcst_begin1: .uleb128 .Ltmp160-.Lfunc_begin1 # >> Call Site 1 << .uleb128 .Ltmp163-.Ltmp160 # Call between .Ltmp160 and .Ltmp163 .uleb128 .Ltmp164-.Lfunc_begin1 # jumps to .Ltmp164 .byte 1 # On action: 1 .Lcst_end1: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase1: .p2align 2, 0x0 # -- End function .section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat .hidden __clang_call_terminate # -- Begin function __clang_call_terminate .weak __clang_call_terminate .p2align 4, 0x90 .type __clang_call_terminate,@function __clang_call_terminate: # @__clang_call_terminate .cfi_startproc # %bb.0: pushq %rax .cfi_def_cfa_offset 16 callq __cxa_begin_catch callq _ZSt9terminatev .Lfunc_end5: .size __clang_call_terminate, .Lfunc_end5-__clang_call_terminate .cfi_endproc # -- End function .section .text._ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,"axG",@progbits,_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,comdat .weak _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE # -- Begin function _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE .p2align 4, 0x90 .type _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,@function _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE: # @_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE .Lfunc_begin2: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception2 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r8, %r14 movq %rcx, 8(%rsp) # 8-byte Spill movq %rdx, %r12 movq %rsi, 16(%rsp) # 8-byte Spill movq %rdi, %rbx leaq 16(%rdi), %rbp movq %rbp, (%rdi) movq $0, 8(%rdi) movb $0, 16(%rdi) leaq (%r8,%rdx), %rsi .Ltmp165: callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm .Ltmp166: # %bb.1: movabsq $9223372036854775807, %r15 # imm = 0x7FFFFFFFFFFFFFFF movq 8(%rbx), %rsi movq %r15, %rax subq %rsi, %rax cmpq %r12, %rax jb .LBB6_11 # %bb.2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i leaq (%rsi,%r12), %r13 movq (%rbx), %rdi movl $15, %eax cmpq %rbp, %rdi je .LBB6_4 # %bb.3: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i movq (%rbp), %rax .LBB6_4: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i cmpq %rax, %r13 jbe .LBB6_5 # %bb.9: .Ltmp167: movq %rbx, %rdi xorl %edx, %edx movq 16(%rsp), %rcx # 8-byte Reload movq %r12, %r8 callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .Ltmp168: jmp .LBB6_10 .LBB6_5: testq %r12, %r12 je .LBB6_10 # %bb.6: addq %rsi, %rdi cmpq $1, %r12 jne .LBB6_8 # %bb.7: movq 16(%rsp), %rax # 8-byte Reload movzbl (%rax), %eax movb %al, (%rdi) jmp .LBB6_10 .LBB6_8: movq 16(%rsp), %rsi # 8-byte Reload movq %r12, %rdx callq memcpy@PLT .LBB6_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.exit movq %r13, 8(%rbx) movq (%rbx), %rax movb $0, (%rax,%r13) movq 8(%rbx), %rsi subq %rsi, %r15 cmpq %r14, %r15 jb .LBB6_11 # %bb.13: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10 leaq (%rsi,%r14), %r15 movq (%rbx), %rdi movl $15, %eax cmpq %rbp, %rdi je .LBB6_15 # %bb.14: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10 movq (%rbp), %rax .LBB6_15: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10 cmpq %rax, %r15 jbe .LBB6_16 # %bb.20: .Ltmp169: movq %rbx, %rdi xorl %edx, %edx movq 8(%rsp), %rcx # 8-byte Reload movq %r14, %r8 callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .Ltmp170: jmp .LBB6_21 .LBB6_16: testq %r14, %r14 je .LBB6_21 # %bb.17: addq %rsi, %rdi cmpq $1, %r14 jne .LBB6_19 # %bb.18: movq 8(%rsp), %rax # 8-byte Reload movzbl (%rax), %eax movb %al, (%rdi) jmp .LBB6_21 .LBB6_19: movq 8(%rsp), %rsi # 8-byte Reload movq %r14, %rdx callq memcpy@PLT .LBB6_21: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.exit17 movq %r15, 8(%rbx) movq (%rbx), %rax movb $0, (%rax,%r15) movq %rbx, %rax addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB6_11: # %.invoke .cfi_def_cfa_offset 80 .Ltmp171: movl $.L.str.17, %edi callq _ZSt20__throw_length_errorPKc .Ltmp172: # %bb.12: # %.cont .LBB6_22: .Ltmp173: movq %rax, %r14 movq (%rbx), %rdi cmpq %rbp, %rdi je .LBB6_24 # %bb.23: # %.critedge.i.i callq _ZdlPv .LBB6_24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end6: .size _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE, .Lfunc_end6-_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE .cfi_endproc .section .gcc_except_table._ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,"aG",@progbits,_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,comdat .p2align 2, 0x0 GCC_except_table6: .Lexception2: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end2-.Lcst_begin2 .Lcst_begin2: .uleb128 .Ltmp165-.Lfunc_begin2 # >> Call Site 1 << .uleb128 .Ltmp168-.Ltmp165 # Call between .Ltmp165 and .Ltmp168 .uleb128 .Ltmp173-.Lfunc_begin2 # jumps to .Ltmp173 .byte 0 # On action: cleanup .uleb128 .Ltmp168-.Lfunc_begin2 # >> Call Site 2 << .uleb128 .Ltmp169-.Ltmp168 # Call between .Ltmp168 and .Ltmp169 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp169-.Lfunc_begin2 # >> Call Site 3 << .uleb128 .Ltmp170-.Ltmp169 # Call between .Ltmp169 and .Ltmp170 .uleb128 .Ltmp173-.Lfunc_begin2 # jumps to .Ltmp173 .byte 0 # On action: cleanup .uleb128 .Ltmp170-.Lfunc_begin2 # >> Call Site 4 << .uleb128 .Ltmp171-.Ltmp170 # Call between .Ltmp170 and .Ltmp171 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp171-.Lfunc_begin2 # >> Call Site 5 << .uleb128 .Ltmp172-.Ltmp171 # Call between .Ltmp171 and .Ltmp172 .uleb128 .Ltmp173-.Lfunc_begin2 # jumps to .Ltmp173 .byte 0 # On action: cleanup .uleb128 .Ltmp172-.Lfunc_begin2 # >> Call Site 6 << .uleb128 .Lfunc_end6-.Ltmp172 # Call between .Ltmp172 and .Lfunc_end6 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end2: .p2align 2, 0x0 # -- End function .section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,comdat .weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm .p2align 4, 0x90 .type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,@function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm .cfi_startproc # %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx movq (%rdi), %r14 leaq 16(%rdi), %r12 movl $15, %eax cmpq %r12, %r14 je .LBB7_2 # %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit movq 16(%rbx), %rax .LBB7_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit cmpq %rsi, %rax jae .LBB7_12 # %bb.3: testq %rsi, %rsi js .LBB7_13 # %bb.4: addq %rax, %rax movabsq $9223372036854775807, %r13 # imm = 0x7FFFFFFFFFFFFFFF cmpq %r13, %rax cmovbq %rax, %r13 cmpq %rsi, %rax cmovbeq %rsi, %r13 movq %r13, %rdi incq %rdi js .LBB7_14 # %bb.5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit callq _Znwm movq %rax, %r15 movq 8(%rbx), %rdx cmpq $-1, %rdx je .LBB7_9 # %bb.6: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit testq %rdx, %rdx jne .LBB7_8 # %bb.7: movzbl (%r14), %eax movb %al, (%r15) .LBB7_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit cmpq %r12, %r14 je .LBB7_11 .LBB7_10: # %.critedge.i movq %r14, %rdi callq _ZdlPv .LBB7_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit movq %r15, (%rbx) movq %r13, 16(%rbx) .LBB7_12: popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB7_8: .cfi_def_cfa_offset 48 incq %rdx movq %r15, %rdi movq %r14, %rsi callq memcpy@PLT cmpq %r12, %r14 jne .LBB7_10 jmp .LBB7_11 .LBB7_14: callq _ZSt17__throw_bad_allocv .LBB7_13: movl $.L.str.15, %edi callq _ZSt20__throw_length_errorPKc .Lfunc_end7: .size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm, .Lfunc_end7-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm .cfi_endproc # -- End function .section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,comdat .weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .p2align 4, 0x90 .type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,@function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .cfi_startproc # %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $40, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r8, %rbp movq %rcx, 32(%rsp) # 8-byte Spill movq %rsi, %r15 movq %rdi, %rbx movq (%rdi), %r14 movq 8(%rdi), %r12 movq %r8, (%rsp) # 8-byte Spill movq %rdx, 16(%rsp) # 8-byte Spill subq %rdx, %rbp leaq 16(%rdi), %rcx movl $15, %eax cmpq %rcx, %r14 je .LBB8_2 # %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit movq 16(%rbx), %rax .LBB8_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit addq %r12, %rbp js .LBB8_26 # %bb.3: cmpq %rax, %rbp jbe .LBB8_6 # %bb.4: addq %rax, %rax cmpq %rax, %rbp jae .LBB8_6 # %bb.5: movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF cmpq %rbp, %rax cmovbq %rax, %rbp .LBB8_6: movq %rbp, %rdi incq %rdi js .LBB8_27 # %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit movq %rcx, 24(%rsp) # 8-byte Spill callq _Znwm movq %rax, %r13 testq %r15, %r15 je .LBB8_11 # %bb.8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit cmpq $1, %r15 jne .LBB8_10 # %bb.9: movzbl (%r14), %eax movb %al, (%r13) jmp .LBB8_11 .LBB8_10: movq %r13, %rdi movq %r14, %rsi movq %r15, %rdx callq memcpy@PLT .LBB8_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit movq %r14, 8(%rsp) # 8-byte Spill movq 16(%rsp), %rax # 8-byte Reload leaq (%rax,%r15), %r14 movq 32(%rsp), %rsi # 8-byte Reload testq %rsi, %rsi movq (%rsp), %rdx # 8-byte Reload je .LBB8_18 # %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit testq %rdx, %rdx je .LBB8_18 # %bb.13: je .LBB8_18 # %bb.14: leaq (%r15,%r13), %rdi cmpq $1, %rdx jne .LBB8_16 # %bb.15: movzbl (%rsi), %eax movb %al, (%rdi) jmp .LBB8_17 .LBB8_16: callq memcpy@PLT .LBB8_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26 movq (%rsp), %rdx # 8-byte Reload .LBB8_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26 cmpq %r14, %r12 je .LBB8_23 # %bb.19: subq %r14, %r12 je .LBB8_23 # %bb.20: movq %r13, %rdi addq %r15, %rdi addq %rdx, %rdi addq 8(%rsp), %r15 # 8-byte Folded Reload addq 16(%rsp), %r15 # 8-byte Folded Reload cmpq $1, %r12 jne .LBB8_22 # %bb.21: movzbl (%r15), %eax movb %al, (%rdi) jmp .LBB8_23 .LBB8_22: movq %r15, %rsi movq %r12, %rdx callq memcpy@PLT .LBB8_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit27 movq 8(%rsp), %rdi # 8-byte Reload cmpq 24(%rsp), %rdi # 8-byte Folded Reload je .LBB8_25 # %bb.24: # %.critedge.i callq _ZdlPv .LBB8_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit movq %r13, (%rbx) movq %rbp, 16(%rbx) addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB8_27: .cfi_def_cfa_offset 96 callq _ZSt17__throw_bad_allocv .LBB8_26: movl $.L.str.15, %edi callq _ZSt20__throw_length_errorPKc .Lfunc_end8: .size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm, .Lfunc_end8-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .cfi_endproc # -- End function .section .text._ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE,comdat .weak _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE # -- Begin function _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE .p2align 4, 0x90 .type _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE,@function _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE: # @_ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %r14 movq 8(%rdx), %r15 movq %rdx, (%rsp) # 8-byte Spill subq (%rdx), %r15 movl $4294967294, %eax # imm = 0xFFFFFFFE cmpq %rax, %r15 ja .LBB9_6 # %bb.1: leal 1(%r15), %r12d movq %r14, %rdi callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv imulq %r12, %rax cmpl %eax, %r12d jbe .LBB9_5 # %bb.2: notl %r15d movq %rax, %rcx movl %r15d, %eax xorl %edx, %edx divl %r12d movq %rcx, %rax cmpl %eax, %edx jbe .LBB9_5 # %bb.3: # %.lr.ph.i.preheader movl %edx, %ebp .p2align 4, 0x90 .LBB9_4: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 movq %r14, %rdi callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv imulq %r12, %rax cmpl %eax, %ebp ja .LBB9_4 .LBB9_5: # %_ZNSt24uniform_int_distributionImE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_.exit shrq $32, %rax jmp .LBB9_11 .LBB9_6: movl $4294967295, %eax # imm = 0xFFFFFFFF cmpq %rax, %r15 jne .LBB9_7 # %bb.10: movq %r14, %rdi callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv jmp .LBB9_11 .LBB9_7: # %.preheader movq %rdi, %r12 movq %r15, %rbx shrq $32, %rbx leaq 8(%rsp), %r13 .p2align 4, 0x90 .LBB9_8: # =>This Inner Loop Header: Depth=1 movq $0, 8(%rsp) movq %rbx, 16(%rsp) movq %r12, %rdi movq %r14, %rsi movq %r13, %rdx callq _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE movq %rax, %rbp shlq $32, %rbp movq %r14, %rdi callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv addq %rbp, %rax setb %cl cmpq %r15, %rax ja .LBB9_8 # %bb.9: # in Loop: Header=BB9_8 Depth=1 testb %cl, %cl jne .LBB9_8 .LBB9_11: # %.loopexit movq (%rsp), %rcx # 8-byte Reload addq (%rcx), %rax addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end9: .size _ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE, .Lfunc_end9-_ZNSt24uniform_int_distributionImEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEmRT_RKNS0_10param_typeE .cfi_endproc # -- End function .section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat .weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv .p2align 4, 0x90 .type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,@function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv: # @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv .cfi_startproc # %bb.0: cmpq $624, 4992(%rdi) # imm = 0x270 jb .LBB10_6 # %bb.1: # %.preheader.preheader movl $2567483615, %eax # imm = 0x9908B0DF xorl %edx, %edx movq $-2147483648, %rcx # imm = 0x80000000 .p2align 4, 0x90 .LBB10_2: # %.preheader # =>This Inner Loop Header: Depth=1 movq (%rdi,%rdx,8), %rsi andq %rcx, %rsi movq 8(%rdi,%rdx,8), %r8 movl %r8d, %r9d andl $2147483646, %r9d # imm = 0x7FFFFFFE orq %rsi, %r9 shrq %r9 xorq 3176(%rdi,%rdx,8), %r9 andl $1, %r8d negl %r8d andl %eax, %r8d xorq %r9, %r8 movq %r8, (%rdi,%rdx,8) leaq 1(%rdx), %rsi movq %rsi, %rdx cmpq $227, %rsi jne .LBB10_2 # %bb.3: # %.preheader.i.preheader movl $228, %ecx movq $-2147483648, %rdx # imm = 0x80000000 .p2align 4, 0x90 .LBB10_4: # %.preheader.i # =>This Inner Loop Header: Depth=1 movq -8(%rdi,%rcx,8), %rsi andq %rdx, %rsi movq (%rdi,%rcx,8), %r8 movl %r8d, %r9d andl $2147483646, %r9d # imm = 0x7FFFFFFE orq %rsi, %r9 shrq %r9 xorq -1824(%rdi,%rcx,8), %r9 andl $1, %r8d negl %r8d andl %eax, %r8d xorq %r9, %r8 movq %r8, -8(%rdi,%rcx,8) incq %rcx cmpq $624, %rcx # imm = 0x270 jne .LBB10_4 # %bb.5: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv.exit movq $-2147483648, %rcx # imm = 0x80000000 andq 4984(%rdi), %rcx movq (%rdi), %rdx movl %edx, %esi andl $2147483646, %esi # imm = 0x7FFFFFFE orq %rcx, %rsi shrq %rsi xorq 3168(%rdi), %rsi andl $1, %edx negl %edx andl %eax, %edx xorq %rsi, %rdx movq %rdx, 4984(%rdi) movq $0, 4992(%rdi) .LBB10_6: movq 4992(%rdi), %rax leaq 1(%rax), %rcx movq %rcx, 4992(%rdi) movq (%rdi,%rax,8), %rax movq %rax, %rcx shrq $11, %rcx movl %ecx, %ecx xorq %rax, %rcx movl %ecx, %eax shll $7, %eax andl $-1658038656, %eax # imm = 0x9D2C5680 xorq %rcx, %rax movl %eax, %ecx shll $15, %ecx andl $-272236544, %ecx # imm = 0xEFC60000 xorq %rax, %rcx movq %rcx, %rax shrq $18, %rax xorq %rcx, %rax retq .Lfunc_end10: .size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .Lfunc_end10-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv .cfi_endproc # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB11_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB11_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11fine_reducePKfS0_iS0_S0_PfS1_iPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13coarse_reducePfS_S_S_iPi, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end11: .size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB12_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB12_2: retq .Lfunc_end12: .size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor .cfi_endproc # -- End function .type std_time_used,@object # @std_time_used .bss .globl std_time_used .p2align 3, 0x0 std_time_used: .quad 0x0000000000000000 # double 0 .size std_time_used, 8 .type _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi,@object # @_Z11fine_reducePKfS0_iS0_S0_PfS1_iPi .section .rodata,"a",@progbits .globl _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi .p2align 3, 0x0 _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi: .quad _Z26__device_stub__fine_reducePKfS0_iS0_S0_PfS1_iPi .size _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi, 8 .type _Z13coarse_reducePfS_S_S_iPi,@object # @_Z13coarse_reducePfS_S_S_iPi .globl _Z13coarse_reducePfS_S_S_iPi .p2align 3, 0x0 _Z13coarse_reducePfS_S_S_iPi: .quad _Z28__device_stub__coarse_reducePfS_S_S_iPi .size _Z13coarse_reducePfS_S_S_iPi, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "usage: k-means <data-file> <k> [iterations]" .size .L.str, 44 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Standard CUDA implementation Took: " .size .L.str.1, 36 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "s" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz " for " .size .L.str.3, 6 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz " points." .size .L.str.4, 9 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Standardtimes.txt" .size .L.str.5, 18 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "a" .size .L.str.6, 2 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "%0.6f\n" .size .L.str.7, 7 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "results/standard/" .size .L.str.8, 18 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "_centroids.txt" .size .L.str.9, 15 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "w" .size .L.str.10, 2 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "%0.6f %0.6f\n" .size .L.str.11, 13 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz "vector::_M_realloc_insert" .size .L.str.12, 26 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz "default" .size .L.str.13, 8 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "basic_string::_M_create" .size .L.str.15, 24 .type .L.str.16,@object # @.str.16 .L.str.16: .asciz "cannot create std::vector larger than max_size()" .size .L.str.16, 49 .type .L__const._ZNSt8__detail18__to_chars_10_implImEEvPcjT_.__digits,@object # @__const._ZNSt8__detail18__to_chars_10_implImEEvPcjT_.__digits .section .rodata.str1.16,"aMS",@progbits,1 .p2align 4, 0x0 .L__const._ZNSt8__detail18__to_chars_10_implImEEvPcjT_.__digits: .asciz "00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899" .size .L__const._ZNSt8__detail18__to_chars_10_implImEEvPcjT_.__digits, 201 .type .L.str.17,@object # @.str.17 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.17: .asciz "basic_string::append" .size .L.str.17, 21 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z11fine_reducePKfS0_iS0_S0_PfS1_iPi" .size .L__unnamed_1, 37 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z13coarse_reducePfS_S_S_iPi" .size .L__unnamed_2, 29 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub__fine_reducePKfS0_iS0_S0_PfS1_iPi .addrsig_sym _Z28__device_stub__coarse_reducePfS_S_S_iPi .addrsig_sym __gxx_personality_v0 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Unwind_Resume .addrsig_sym _Z11fine_reducePKfS0_iS0_S0_PfS1_iPi .addrsig_sym _Z13coarse_reducePfS_S_S_iPi .addrsig_sym _ZSt4cerr .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
12,873
33,447
9,174
47,620
162
code for sm_80 Function : _Z14dynproc_kerneliPiS_S_iiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R3, SR_CTAID.X ; ULDC UR4, c[0x0][0x160] ; BSSY B0, 0x130 ; UIADD3 UR4, -UR4, URZ, URZ ; S2R R0, SR_TID.X ; ULDC.64 UR6, c[0x0][0x118] ; ULEA UR5, UR4, 0x100, 0x1 ; IMAD R3, R3, UR5, RZ ; IADD3 R7, R3, -c[0x0][0x18c], RZ ; IMAD.IADD R2, R7, 0x1, R0 ; ISETP.GE.AND P0, PT, R2, c[0x0][0x180], PT ; ISETP.LT.OR P0, PT, R2, RZ, P0 ; @P0 BRA 0x120 ; IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; IMAD.WIDE R4, R2, R5, c[0x0][0x170] ; LDG.E R5, [R4.64] ; STS [R0.X4], R5 ; BSYNC B0 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P0, PT, R4, 0x1, PT ; @!P0 BRA 0x490 ; IADD3 R4, -R7.reuse, -0xff, RZ ; IMAD.MOV R6, RZ, RZ, -R7.reuse ; IADD3 R5, R7, 0xff, RZ ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x188] ; IADD3 R4, R4, c[0x0][0x180], RZ ; ISETP.GE.AND P0, PT, R5, c[0x0][0x180], PT ; IMAD R8, R9, c[0x0][0x180], R0 ; IADD3 R4, R4, 0xfe, RZ ; SHF.R.S32.HI R7, RZ, 0x1f, R7 ; SEL R5, R4, 0xff, P0 ; LOP3.LUT R7, R7, R6, RZ, 0xc0, !PT ; ISETP.GT.AND P0, PT, R0.reuse, R5, PT ; IADD3 R4, R0.reuse, -0x1, RZ ; IADD3 R6, R0.reuse, 0x1, RZ ; ISETP.GE.AND P0, PT, R0, R7, !P0 ; IADD3 R9, R8, -c[0x0][0x18c], R3 ; IMAD.MOV.U32 R3, RZ, RZ, RZ ; IMNMX R7, R7, R4, !PT ; IMAD.U32 R8, RZ, RZ, UR4 ; IMNMX R6, R5, R6, PT ; IADD3 R5, -R3, 0xfe, RZ ; ISETP.GT.AND P1, PT, R0, R5, PT ; ISETP.GT.AND P1, PT, R0, R3, !P1 ; PLOP3.LUT P1, PT, P0, P1, PT, 0x80, 0x0 ; @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; @P1 LDS R10, [R7.X4] ; @P1 IMAD.WIDE R4, R9, R4, c[0x0][0x168] ; @P1 LDS R11, [R0.X4] ; @P1 LDS R13, [R6.X4] ; @P1 LDG.E R5, [R4.64] ; ISETP.NE.AND P2, PT, R8, -0x1, PT ; IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; @P1 IMNMX R10, R10, R11, PT ; @P1 IMNMX R10, R10, R13, PT ; @P1 IMAD.IADD R11, R10, 0x1, R5 ; PRMT R10, RZ, 0x7610, R10 ; @P1 STS [R0.X4+0x400], R11 ; @P1 PRMT R10, R4, 0x7610, R10 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P2 BRA 0x490 ; PRMT R4, R10, 0x9910, RZ ; IADD3 R3, R3, 0x1, RZ ; ISETP.NE.AND P1, PT, R4, RZ, PT ; IADD3 R8, R8, 0x1, RZ ; IADD3 R9, R9, c[0x0][0x180], RZ ; @P1 LDS R5, [R0.X4+0x400] ; @P1 STS [R0.X4], R5 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P1, PT, R3, c[0x0][0x160], PT ; @!P1 BRA 0x2b0 ; LOP3.LUT P0, RZ, R10, 0xff, RZ, 0xc0, !PT ; @!P0 EXIT ; LDS R5, [R0.X4+0x400] ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; IMAD.WIDE R2, R2, R3, c[0x0][0x178] ; STG.E [R2.64], R5 ; EXIT ; BRA 0x500; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000cc27b_00000000-6_5fa106f504e79004a9db77fd11b9a1d19a233645.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2064: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2064: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "Usage: dynproc row_len col_len pyramid_height\n" .text .globl _Z4initiPPc .type _Z4initiPPc, @function _Z4initiPPc: .LFB2057: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 cmpl $4, %edi je .L26 leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %edi call exit@PLT .L26: movq %rsi, %rbx movq 8(%rsi), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl %eax, cols(%rip) movq 16(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl %eax, rows(%rip) movq 24(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl %eax, pyramid_height(%rip) movl rows(%rip), %eax imull cols(%rip), %eax cltq movabsq $2305843009213693950, %rdx cmpq %rax, %rdx jb .L27 leaq 0(,%rax,4), %rdi call _Znam@PLT movq %rax, data(%rip) movslq rows(%rip), %rax movq %rax, %rdi shrq $60, %rdi jne .L28 leaq 0(,%rax,8), %rdi call _Znam@PLT movq %rax, wall(%rip) movl rows(%rip), %eax testl %eax, %eax jle .L10 movslq cols(%rip), %r8 salq $2, %r8 cltq leaq 0(,%rax,8), %rdi movl $0, %edx movl $0, %eax .L11: movq %rdx, %rsi addq data(%rip), %rsi movq wall(%rip), %rcx movq %rsi, (%rcx,%rax) addq $8, %rax addq %r8, %rdx cmpq %rdi, %rax jne .L11 .L10: movslq cols(%rip), %rax movabsq $2305843009213693950, %rdx cmpq %rax, %rdx jb .L12 leaq 0(,%rax,4), %rdi call _Znam@PLT movq %rax, result(%rip) movl $9, %edi call srand@PLT movl $0, %r12d cmpl $0, rows(%rip) jg .L13 .L3: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L27: .cfi_restore_state call __cxa_throw_bad_array_new_length@PLT .L28: call __cxa_throw_bad_array_new_length@PLT .L12: call __cxa_throw_bad_array_new_length@PLT .L15: call rand@PLT movq wall(%rip), %rdx movq (%rdx,%rbp), %rcx movslq %eax, %rdx imulq $1717986919, %rdx, %rdx sarq $34, %rdx movl %eax, %esi sarl $31, %esi subl %esi, %edx leal (%rdx,%rdx,4), %edx addl %edx, %edx subl %edx, %eax movl %eax, (%rcx,%rbx,4) addq $1, %rbx cmpl %ebx, cols(%rip) jg .L15 .L17: addq $1, %r12 cmpl %r12d, rows(%rip) jle .L3 .L13: leaq 0(,%r12,8), %rbp movl $0, %ebx cmpl $0, cols(%rip) jg .L15 jmp .L17 .cfi_endproc .LFE2057: .size _Z4initiPPc, .-_Z4initiPPc .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "error: %s\n" .text .globl _Z5fatalPc .type _Z5fatalPc, @function _Z5fatalPc: .LFB2058: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq %rdi, %rcx leaq .LC1(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z5fatalPc, .-_Z5fatalPc .globl _Z43__device_stub__Z14dynproc_kerneliPiS_S_iiiiiPiS_S_iiii .type _Z43__device_stub__Z14dynproc_kerneliPiS_S_iiiiiPiS_S_iiii, @function _Z43__device_stub__Z14dynproc_kerneliPiS_S_iiiiiPiS_S_iiii: .LFB2086: .cfi_startproc endbr64 subq $200, %rsp .cfi_def_cfa_offset 208 movl %edi, 44(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movl %r8d, 40(%rsp) movl %r9d, 12(%rsp) movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax leaq 44(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) leaq 12(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L35 .L31: movq 184(%rsp), %rax subq %fs:40, %rax jne .L36 addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L35: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 216 pushq 56(%rsp) .cfi_def_cfa_offset 224 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z14dynproc_kerneliPiS_S_iiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 208 jmp .L31 .L36: call __stack_chk_fail@PLT .cfi_endproc .LFE2086: .size _Z43__device_stub__Z14dynproc_kerneliPiS_S_iiiiiPiS_S_iiii, .-_Z43__device_stub__Z14dynproc_kerneliPiS_S_iiiiiPiS_S_iiii .globl _Z14dynproc_kerneliPiS_S_iiii .type _Z14dynproc_kerneliPiS_S_iiii, @function _Z14dynproc_kerneliPiS_S_iiii: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 call _Z43__device_stub__Z14dynproc_kerneliPiS_S_iiiiiPiS_S_iiii addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _Z14dynproc_kerneliPiS_S_iiii, .-_Z14dynproc_kerneliPiS_S_iiii .globl _Z9calc_pathPiPS_iiiii .type _Z9calc_pathPiPS_iiiii, @function _Z9calc_pathPiPS_iiiii: .LFB2059: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $72, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, 16(%rsp) movl %ecx, 24(%rsp) movl $256, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl %r9d, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) cmpl $1, %edx jle .L44 movl %r8d, %ebp leal -1(%rdx), %r15d movl %r15d, %r12d movl $0, %ebx movl $0, %r14d movl $1, %r13d movl %edx, 28(%rsp) jmp .L43 .L41: addl %ebp, %ebx subl %ebp, %r12d movl %r14d, %eax movl %r13d, %r14d cmpl %r15d, %ebx jge .L39 movl %eax, %r13d .L43: movl 48(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 40(%rsp), %rdx movq 52(%rsp), %rdi movl 60(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L41 movslq %r13d, %rax movq 16(%rsp), %rsi movq (%rsi,%rax,8), %rcx movslq %r14d, %rax movq (%rsi,%rax,8), %rdx leal 1(%r12), %eax cmpl %eax, %ebp movl %r12d, %edi cmovl %ebp, %edi movl 128(%rsp), %eax pushq %rax .cfi_def_cfa_offset 136 pushq %rbx .cfi_def_cfa_offset 144 movl 44(%rsp), %r9d movl 40(%rsp), %r8d movq 24(%rsp), %rsi call _Z43__device_stub__Z14dynproc_kerneliPiS_S_iiiiiPiS_S_iiii addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L41 .L44: movl $0, %r13d .L39: movl %r13d, %eax addq $72, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2059: .size _Z9calc_pathPiPS_iiiii, .-_Z9calc_pathPiPS_iiiii .section .rodata.str1.8 .align 8 .LC2: .string "pyramidHeight: %d\ngridSize: [%d]\nborder:[%d]\nblockSize: %d\nblockGrid:[%d]\ntargetBlock:[%d]\n" .text .globl _Z3runiPPc .type _Z3runiPPc, @function _Z3runiPPc: .LFB2061: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $56, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax call _Z4initiPPc movl pyramid_height(%rip), %r12d movl $128, %esi subl %r12d, %esi addl %esi, %esi movl cols(%rip), %ecx movl %ecx, %eax cltd idivl %esi cmpl $1, %edx sbbl $-1, %eax movl %eax, %ebp pushq %rsi .cfi_def_cfa_offset 104 pushq %rax .cfi_def_cfa_offset 112 movl $256, %r9d movl %r12d, %r8d movl %r12d, %edx leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl cols(%rip), %esi movl %esi, %ebx imull rows(%rip), %ebx addq $16, %rsp .cfi_def_cfa_offset 96 movslq %esi, %rsi salq $2, %rsi leaq 16(%rsp), %r13 movq %r13, %rdi call cudaMalloc@PLT movslq cols(%rip), %rsi salq $2, %rsi leaq 24(%rsp), %rdi call cudaMalloc@PLT movslq cols(%rip), %rdx salq $2, %rdx movl $1, %ecx movq data(%rip), %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl %ebx, %esi subl cols(%rip), %esi movslq %esi, %rsi salq $2, %rsi leaq 8(%rsp), %rdi call cudaMalloc@PLT movl cols(%rip), %eax subl %eax, %ebx movslq %ebx, %rdx salq $2, %rdx cltq movq data(%rip), %rcx leaq (%rcx,%rax,4), %rsi movl $1, %ecx movq 8(%rsp), %rdi call cudaMemcpy@PLT subq $8, %rsp .cfi_def_cfa_offset 104 pushq %r12 .cfi_def_cfa_offset 112 movl %ebp, %r9d movl pyramid_height(%rip), %r8d movl cols(%rip), %ecx movl rows(%rip), %edx movq %r13, %rsi movq 24(%rsp), %rdi call _Z9calc_pathPiPS_iiiii addq $16, %rsp .cfi_def_cfa_offset 96 movslq cols(%rip), %rdx salq $2, %rdx cltq movq 16(%rsp,%rax,8), %rsi movl $2, %ecx movq result(%rip), %rdi call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq data(%rip), %rdi testq %rdi, %rdi je .L49 call _ZdaPv@PLT .L49: movq wall(%rip), %rdi testq %rdi, %rdi je .L50 call _ZdaPv@PLT .L50: movq result(%rip), %rdi testq %rdi, %rdi je .L48 call _ZdaPv@PLT .L48: movq 40(%rsp), %rax subq %fs:40, %rax jne .L54 addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L54: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2061: .size _Z3runiPPc, .-_Z3runiPPc .globl main .type main, @function main: .LFB2060: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $24, %rsp .cfi_def_cfa_offset 48 movl %edi, %ebx movq %rsi, %rbp movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax leaq 4(%rsp), %rdi call cudaGetDeviceCount@PLT cmpl $1, 4(%rsp) jg .L59 .L56: movq %rbp, %rsi movl %ebx, %edi call _Z3runiPPc movq 8(%rsp), %rax subq %fs:40, %rax jne .L60 movl $0, %eax addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L59: .cfi_restore_state movl $0, %edi call cudaSetDevice@PLT jmp .L56 .L60: call __stack_chk_fail@PLT .cfi_endproc .LFE2060: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z14dynproc_kerneliPiS_S_iiii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2089: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _Z14dynproc_kerneliPiS_S_iiii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2089: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .globl pyramid_height .bss .align 4 .type pyramid_height, @object .size pyramid_height, 4 pyramid_height: .zero 4 .globl result .align 8 .type result, @object .size result, 8 result: .zero 8 .globl wall .align 8 .type wall, @object .size wall, 8 wall: .zero 8 .globl data .align 8 .type data, @object .size data, 8 data: .zero 8 .globl cols .align 4 .type cols, @object .size cols, 4 cols: .zero 4 .globl rows .align 4 .type rows, @object .size rows, 4 rows: .zero 4 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14dynproc_kerneliPiS_S_iiii ; -- Begin function _Z14dynproc_kerneliPiS_S_iiii .globl _Z14dynproc_kerneliPiS_S_iiii .p2align 8 .type _Z14dynproc_kerneliPiS_S_iiii,@function _Z14dynproc_kerneliPiS_S_iiii: ; @_Z14dynproc_kerneliPiS_S_iiii ; %bb.0: s_clause 0x2 s_load_b32 s7, s[0:1], 0x0 s_load_b32 s6, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x20 s_waitcnt lgkmcnt(0) s_lshl_b32 s2, s7, 1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_sub_i32 s8, 0x100, s2 s_mul_i32 s8, s8, s15 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_sub_i32 s9, s8, s6 v_add_nc_u32_e32 v1, s9, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_lt_i32_e32 vcc_lo, -1, v1 v_cmp_gt_i32_e64 s2, s3, v1 s_and_b32 s4, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s2, s4 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b64 s[4:5], s[0:1], 0x10 v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo global_load_b32 v2, v[2:3], off v_lshlrev_b32_e32 v3, 2, v0 s_waitcnt vmcnt(0) ds_store_b32 v3, v2 .LBB0_2: s_or_b32 exec_lo, exec_lo, s2 s_cmp_lt_i32 s7, 1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_14 ; %bb.3: ; %.lr.ph s_clause 0x1 s_load_b32 s2, s[0:1], 0x28 s_load_b64 s[4:5], s[0:1], 0x8 s_add_i32 s10, s9, 0xff s_sub_i32 s11, 0, s9 s_ashr_i32 s12, s9, 31 s_not_b32 s9, s9 s_and_b32 s11, s12, s11 s_add_i32 s9, s9, s3 v_add_nc_u32_e32 v2, -1, v0 v_add_nc_u32_e32 v3, 1, v0 s_cmp_ge_i32 s10, s3 v_lshlrev_b32_e32 v5, 2, v0 s_cselect_b32 s9, s9, 0xff v_max_i32_e32 v2, s11, v2 v_min_i32_e32 v3, s9, v3 v_cmp_gt_i32_e32 vcc_lo, s11, v0 v_sub_nc_u32_e32 v4, 0xfe, v0 v_add_nc_u32_e32 v8, 0x400, v5 v_lshlrev_b32_e32 v6, 2, v2 v_lshlrev_b32_e32 v7, 2, v3 s_waitcnt lgkmcnt(0) s_mul_i32 s2, s2, s3 s_add_i32 s7, s7, -1 v_add3_u32 v9, s8, s2, v0 v_cmp_lt_i32_e64 s2, s9, v0 s_mov_b32 s8, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v2, s6, v9 s_or_b32 s6, vcc_lo, s2 s_branch .LBB0_5 .p2align 6 .LBB0_4: ; in Loop: Header=BB0_5 Depth=1 s_or_b32 exec_lo, exec_lo, s10 v_add_nc_u32_e32 v2, s3, v2 s_add_i32 s8, s8, 1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv .LBB0_5: ; =>This Inner Loop Header: Depth=1 v_cmp_ge_u32_e32 vcc_lo, s8, v0 v_cmp_gt_i32_e64 s2, s8, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s2, vcc_lo, s2 s_or_b32 s2, s2, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_xor_b32 s9, s2, -1 s_and_saveexec_b32 s10, s9 s_cbranch_execz .LBB0_7 ; %bb.6: ; in Loop: Header=BB0_5 Depth=1 v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[9:10], 2, v[2:3] v_add_co_u32 v9, vcc_lo, s4, v9 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo global_load_b32 v3, v[9:10], off ds_load_b32 v9, v6 ds_load_b32 v10, v5 ds_load_b32 v11, v7 s_waitcnt lgkmcnt(0) v_min3_i32 v9, v9, v10, v11 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_add_nc_u32_e32 v3, v9, v3 ds_store_b32 v8, v3 .LBB0_7: ; in Loop: Header=BB0_5 Depth=1 s_or_b32 exec_lo, exec_lo, s10 s_cmp_eq_u32 s7, s8 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_10 ; %bb.8: ; in Loop: Header=BB0_5 Depth=1 s_and_saveexec_b32 s10, s9 s_cbranch_execz .LBB0_4 ; %bb.9: ; in Loop: Header=BB0_5 Depth=1 ds_load_b32 v3, v8 s_waitcnt lgkmcnt(0) ds_store_b32 v5, v3 s_branch .LBB0_4 .LBB0_10: ; in Loop: Header=BB0_5 Depth=1 ; implicit-def: $sgpr8 ; implicit-def: $vgpr2 s_cbranch_execz .LBB0_5 ; %bb.11: ; %._crit_edge s_xor_b32 s2, s2, -1 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_13 .LBB0_12: s_load_b64 s[0:1], s[0:1], 0x18 v_lshlrev_b32_e32 v0, 2, v0 v_ashrrev_i32_e32 v2, 31, v1 ds_load_b32 v3, v0 offset:1024 v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v3, off .LBB0_13: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .LBB0_14: ; implicit-def: $sgpr2 s_and_saveexec_b32 s3, s2 s_cbranch_execnz .LBB0_12 s_branch .LBB0_13 .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14dynproc_kerneliPiS_S_iiii .amdhsa_group_segment_fixed_size 2048 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 48 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14dynproc_kerneliPiS_S_iiii, .Lfunc_end0-_Z14dynproc_kerneliPiS_S_iiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 676 ; NumSgprs: 18 ; NumVgprs: 12 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 2048 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 12 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: by_value - .offset: 44 .size: 4 .value_kind: by_value .group_segment_fixed_size: 2048 .kernarg_segment_align: 8 .kernarg_segment_size: 48 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14dynproc_kerneliPiS_S_iiii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z14dynproc_kerneliPiS_S_iiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "5fa106f504e79004a9db77fd11b9a1d19a233645.hip" .globl _Z4initiPPc # -- Begin function _Z4initiPPc .p2align 4, 0x90 .type _Z4initiPPc,@function _Z4initiPPc: # @_Z4initiPPc .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 cmpl $4, %edi jne .LBB0_11 # %bb.1: movq %rsi, %rbx movq 8(%rsi), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movl %eax, cols(%rip) movq 16(%rbx), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r14 movl %r14d, rows(%rip) movq 24(%rbx), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movl %eax, pyramid_height(%rip) movslq cols(%rip), %rbx movslq %r14d, %rax imulq %rbx, %rax movq %rax, %rdi shlq $2, %rdi testl %eax, %eax movq $-1, %r14 cmovsq %r14, %rdi callq _Znam movq %rax, data(%rip) movslq rows(%rip), %r15 leaq (,%r15,8), %rdi testq %r15, %r15 cmovsq %r14, %rdi callq _Znam movq %rax, wall(%rip) testq %r15, %r15 jle .LBB0_4 # %bb.2: # %.lr.ph.preheader movl %r15d, %eax leaq (,%rbx,4), %rcx xorl %edx, %edx xorl %esi, %esi .p2align 4, 0x90 .LBB0_3: # %.lr.ph # =>This Inner Loop Header: Depth=1 movq data(%rip), %rdi addq %rdx, %rdi movq wall(%rip), %r8 movq %rdi, (%r8,%rsi,8) incq %rsi addq %rcx, %rdx cmpq %rsi, %rax jne .LBB0_3 .LBB0_4: # %._crit_edge movq %rbx, %rdi shlq $2, %rdi testl %ebx, %ebx cmovsq %r14, %rdi callq _Znam movq %rax, result(%rip) movl $9, %edi callq srand cmpl $0, rows(%rip) jle .LBB0_10 # %bb.5: # %.preheader.preheader xorl %ebx, %ebx jmp .LBB0_6 .p2align 4, 0x90 .LBB0_9: # %._crit_edge19 # in Loop: Header=BB0_6 Depth=1 incq %rbx movslq rows(%rip), %rax cmpq %rax, %rbx jge .LBB0_10 .LBB0_6: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB0_8 Depth 2 cmpl $0, cols(%rip) jle .LBB0_9 # %bb.7: # %.lr.ph18.preheader # in Loop: Header=BB0_6 Depth=1 xorl %r14d, %r14d .p2align 4, 0x90 .LBB0_8: # %.lr.ph18 # Parent Loop BB0_6 Depth=1 # => This Inner Loop Header: Depth=2 callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx subl %ecx, %eax movq wall(%rip), %rcx movq (%rcx,%rbx,8), %rcx movl %eax, (%rcx,%r14,4) incq %r14 movslq cols(%rip), %rax cmpq %rax, %r14 jl .LBB0_8 jmp .LBB0_9 .LBB0_10: # %._crit_edge21 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB0_11: .cfi_def_cfa_offset 32 movl $.Lstr, %edi callq puts@PLT xorl %edi, %edi callq exit .Lfunc_end0: .size _Z4initiPPc, .Lfunc_end0-_Z4initiPPc .cfi_endproc # -- End function .globl _Z5fatalPc # -- Begin function _Z5fatalPc .p2align 4, 0x90 .type _Z5fatalPc,@function _Z5fatalPc: # @_Z5fatalPc .cfi_startproc # %bb.0: movq %rdi, %rdx movq stderr(%rip), %rdi movl $.L.str.1, %esi xorl %eax, %eax jmp fprintf # TAILCALL .Lfunc_end1: .size _Z5fatalPc, .Lfunc_end1-_Z5fatalPc .cfi_endproc # -- End function .globl _Z29__device_stub__dynproc_kerneliPiS_S_iiii # -- Begin function _Z29__device_stub__dynproc_kerneliPiS_S_iiii .p2align 4, 0x90 .type _Z29__device_stub__dynproc_kerneliPiS_S_iiii,@function _Z29__device_stub__dynproc_kerneliPiS_S_iiii: # @_Z29__device_stub__dynproc_kerneliPiS_S_iiii .cfi_startproc # %bb.0: subq $168, %rsp .cfi_def_cfa_offset 176 movl %edi, 20(%rsp) movq %rsi, 88(%rsp) movq %rdx, 80(%rsp) movq %rcx, 72(%rsp) movl %r8d, 16(%rsp) movl %r9d, 12(%rsp) leaq 20(%rsp), %rax movq %rax, 96(%rsp) leaq 88(%rsp), %rax movq %rax, 104(%rsp) leaq 80(%rsp), %rax movq %rax, 112(%rsp) leaq 72(%rsp), %rax movq %rax, 120(%rsp) leaq 16(%rsp), %rax movq %rax, 128(%rsp) leaq 12(%rsp), %rax movq %rax, 136(%rsp) leaq 176(%rsp), %rax movq %rax, 144(%rsp) leaq 184(%rsp), %rax movq %rax, 152(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z14dynproc_kerneliPiS_S_iiii, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $184, %rsp .cfi_adjust_cfa_offset -184 retq .Lfunc_end2: .size _Z29__device_stub__dynproc_kerneliPiS_S_iiii, .Lfunc_end2-_Z29__device_stub__dynproc_kerneliPiS_S_iiii .cfi_endproc # -- End function .globl _Z9calc_pathPiPS_iiiii # -- Begin function _Z9calc_pathPiPS_iiiii .p2align 4, 0x90 .type _Z9calc_pathPiPS_iiiii,@function _Z9calc_pathPiPS_iiiii: # @_Z9calc_pathPiPS_iiiii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $216, %rsp .cfi_def_cfa_offset 272 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %ecx, 8(%rsp) # 4-byte Spill # kill: def $edx killed $edx def $rdx movq %rsi, 48(%rsp) # 8-byte Spill movq %rdi, 40(%rsp) # 8-byte Spill xorl %r12d, %r12d movq %rdx, 32(%rsp) # 8-byte Spill cmpl $2, %edx jl .LBB3_5 # %bb.1: # %.lr.ph movl %r8d, %ebx movabsq $4294967296, %rcx # imm = 0x100000000 movl %r9d, %eax orq %rcx, %rax movq %rax, 64(%rsp) # 8-byte Spill movq 32(%rsp), %rax # 8-byte Reload leal -1(%rax), %r14d xorl %r15d, %r15d movl $1, %eax addq $256, %rcx # imm = 0x100 movq %rcx, 56(%rsp) # 8-byte Spill movl %r14d, %r13d xorl %ebp, %ebp jmp .LBB3_2 .p2align 4, 0x90 .LBB3_4: # in Loop: Header=BB3_2 Depth=1 addl %ebx, %ebp subl %ebx, %r14d movl %r15d, %eax movl %r12d, %r15d cmpl %r13d, %ebp jge .LBB3_5 .LBB3_2: # =>This Inner Loop Header: Depth=1 movl %eax, %r12d movq 64(%rsp), %rdi # 8-byte Reload movl $1, %esi movq 56(%rsp), %rdx # 8-byte Reload movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_4 # %bb.3: # in Loop: Header=BB3_2 Depth=1 cmpl %ebx, %r14d movl %ebx, %eax cmovll %r14d, %eax movl %r15d, %ecx movq 48(%rsp), %rsi # 8-byte Reload movq (%rsi,%rcx,8), %rcx movl %r12d, %edx movq (%rsi,%rdx,8), %rdx movl %eax, 28(%rsp) movq %rcx, 128(%rsp) movq %rdx, 120(%rsp) movq 40(%rsp), %rax # 8-byte Reload movq %rax, 136(%rsp) movl 8(%rsp), %eax # 4-byte Reload movl %eax, 24(%rsp) movq 32(%rsp), %rax # 8-byte Reload movl %eax, 20(%rsp) movl %ebp, 16(%rsp) movl 272(%rsp), %eax movl %eax, 12(%rsp) leaq 28(%rsp), %rax movq %rax, 144(%rsp) leaq 136(%rsp), %rax movq %rax, 152(%rsp) leaq 128(%rsp), %rax movq %rax, 160(%rsp) leaq 120(%rsp), %rax movq %rax, 168(%rsp) leaq 24(%rsp), %rax movq %rax, 176(%rsp) leaq 20(%rsp), %rax movq %rax, 184(%rsp) leaq 16(%rsp), %rax movq %rax, 192(%rsp) leaq 12(%rsp), %rax movq %rax, 200(%rsp) leaq 104(%rsp), %rdi leaq 88(%rsp), %rsi leaq 80(%rsp), %rdx leaq 72(%rsp), %rcx callq __hipPopCallConfiguration movq 104(%rsp), %rsi movl 112(%rsp), %edx movq 88(%rsp), %rcx movl 96(%rsp), %r8d movl $_Z14dynproc_kerneliPiS_S_iiii, %edi leaq 144(%rsp), %r9 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 pushq 88(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 jmp .LBB3_4 .LBB3_5: # %._crit_edge movl %r12d, %eax addq $216, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size _Z9calc_pathPiPS_iiiii, .Lfunc_end3-_Z9calc_pathPiPS_iiiii .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %rbp, -16 movq %rsi, %rbx movl %edi, %ebp leaq 4(%rsp), %rdi callq hipGetDeviceCount cmpl $2, 4(%rsp) jl .LBB4_2 # %bb.1: xorl %edi, %edi callq hipSetDevice .LBB4_2: movl %ebp, %edi movq %rbx, %rsi callq _Z3runiPPc xorl %eax, %eax addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end4: .size main, .Lfunc_end4-main .cfi_endproc # -- End function .globl _Z3runiPPc # -- Begin function _Z3runiPPc .p2align 4, 0x90 .type _Z3runiPPc,@function _Z3runiPPc: # @_Z3runiPPc .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $40, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 callq _Z4initiPPc movl pyramid_height(%rip), %ebx movl $256, %esi # imm = 0x100 subl %ebx, %esi subl %ebx, %esi movl cols(%rip), %ecx movl %ecx, %eax cltd idivl %esi movl %eax, %ebp cmpl $1, %edx sbbl $-1, %ebp movl %esi, (%rsp) movl $.L.str.2, %edi movl %ebx, %esi movl %ecx, %edx movl %ebx, %ecx movl $256, %r8d # imm = 0x100 movl %ebp, %r9d xorl %eax, %eax callq printf movslq rows(%rip), %r15 movslq cols(%rip), %rsi imulq %rsi, %r15 shlq $2, %rsi leaq 16(%rsp), %r14 movq %r14, %rdi callq hipMalloc leaq 24(%rsp), %rdi movslq cols(%rip), %rsi shlq $2, %rsi callq hipMalloc movq 16(%rsp), %rdi movq data(%rip), %rsi movslq cols(%rip), %rdx shlq $2, %rdx movl $1, %ecx callq hipMemcpy movslq cols(%rip), %rax movq %r15, %rsi subq %rax, %rsi shlq $2, %rsi leaq 8(%rsp), %rdi callq hipMalloc movslq cols(%rip), %rax leaq (,%rax,4), %rsi addq data(%rip), %rsi movq 8(%rsp), %rdi movslq %r15d, %rdx subq %rax, %rdx shlq $2, %rdx movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi movl rows(%rip), %edx movl cols(%rip), %ecx movl pyramid_height(%rip), %r8d movl %ebx, (%rsp) movq %r14, %rsi movl %ebp, %r9d callq _Z9calc_pathPiPS_iiiii movq result(%rip), %rdi movl %eax, %eax movq 16(%rsp,%rax,8), %rsi movslq cols(%rip), %rdx shlq $2, %rdx movl $2, %ecx callq hipMemcpy movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq data(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: callq _ZdaPv .LBB5_2: movq wall(%rip), %rdi testq %rdi, %rdi je .LBB5_4 # %bb.3: callq _ZdaPv .LBB5_4: movq result(%rip), %rdi testq %rdi, %rdi je .LBB5_6 # %bb.5: callq _ZdaPv .LBB5_6: addq $40, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end5: .size _Z3runiPPc, .Lfunc_end5-_Z3runiPPc .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB6_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB6_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14dynproc_kerneliPiS_S_iiii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end6: .size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB7_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB7_2: retq .Lfunc_end7: .size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor .cfi_endproc # -- End function .type rows,@object # @rows .bss .globl rows .p2align 2, 0x0 rows: .long 0 # 0x0 .size rows, 4 .type cols,@object # @cols .globl cols .p2align 2, 0x0 cols: .long 0 # 0x0 .size cols, 4 .type data,@object # @data .globl data .p2align 3, 0x0 data: .quad 0 .size data, 8 .type wall,@object # @wall .globl wall .p2align 3, 0x0 wall: .quad 0 .size wall, 8 .type result,@object # @result .globl result .p2align 3, 0x0 result: .quad 0 .size result, 8 .type pyramid_height,@object # @pyramid_height .globl pyramid_height .p2align 2, 0x0 pyramid_height: .long 0 # 0x0 .size pyramid_height, 4 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "error: %s\n" .size .L.str.1, 11 .type _Z14dynproc_kerneliPiS_S_iiii,@object # @_Z14dynproc_kerneliPiS_S_iiii .section .rodata,"a",@progbits .globl _Z14dynproc_kerneliPiS_S_iiii .p2align 3, 0x0 _Z14dynproc_kerneliPiS_S_iiii: .quad _Z29__device_stub__dynproc_kerneliPiS_S_iiii .size _Z14dynproc_kerneliPiS_S_iiii, 8 .type .L.str.2,@object # @.str.2 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.2: .asciz "pyramidHeight: %d\ngridSize: [%d]\nborder:[%d]\nblockSize: %d\nblockGrid:[%d]\ntargetBlock:[%d]\n" .size .L.str.2, 92 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z14dynproc_kerneliPiS_S_iiii" .size .L__unnamed_1, 30 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Usage: dynproc row_len col_len pyramid_height" .size .Lstr, 46 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__dynproc_kerneliPiS_S_iiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14dynproc_kerneliPiS_S_iiii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z15kernel_multiplyPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R5, SR_TID.X ; S2R R3, SR_CTAID.Y ; S2R R2, SR_TID.Y ; IMAD R0, R0, c[0x0][0x0], R5 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; IMAD R3, R3, c[0x0][0x4], R2 ; ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; @P0 EXIT ; MOV R2, c[0x0][0x178] ; ULDC.64 UR4, c[0x0][0x118] ; HFMA2.MMA R24, -RZ, RZ, 0, 0 ; ISETP.GE.AND P0, PT, R2, 0x1, PT ; @!P0 BRA 0xbf0 ; IADD3 R4, R2.reuse, -0x1, RZ ; LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; MOV R4, RZ ; MOV R24, RZ ; @!P0 BRA 0xaf0 ; IADD3 R6, -R5, c[0x0][0x178], RZ ; HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR6, c[0x0][0x160] ; IMAD R7, R3, c[0x0][0x178], RZ ; ISETP.GT.AND P0, PT, R6, RZ, PT ; MOV R4, RZ ; IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; @!P0 BRA 0x960 ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x6a0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; MOV R14, UR6 ; LDG.E R11, [R8.64] ; MOV R15, UR7 ; IMAD.WIDE R14, R7, 0x4, R14 ; LDG.E R10, [R14.64] ; IMAD.WIDE R8, R2, 0x4, R8 ; LDG.E R18, [R14.64+0x4] ; IMAD.WIDE R22, R2.reuse, 0x4, R8 ; LDG.E R19, [R8.64] ; LDG.E R28, [R22.64] ; IMAD.WIDE R26, R2, 0x4, R22 ; LDG.E R29, [R14.64+0x8] ; IMAD.WIDE R12, R2.reuse, 0x4, R26 ; LDG.E R16, [R26.64] ; LDG.E R17, [R14.64+0xc] ; LDG.E R20, [R14.64+0x10] ; LDG.E R21, [R12.64] ; LDG.E R8, [R14.64+0x14] ; LDG.E R26, [R14.64+0x1c] ; IMAD.WIDE R12, R2, 0x4, R12 ; LDG.E R9, [R12.64] ; IMAD.WIDE R22, R2, 0x4, R12 ; IMAD R12, R11, R10, R24 ; LDG.E R10, [R14.64+0x18] ; IMAD.WIDE R24, R2, 0x4, R22 ; LDG.E R11, [R22.64] ; LDG.E R27, [R24.64] ; IMAD R12, R19, R18, R12 ; IMAD.WIDE R18, R2, 0x4, R24 ; LDG.E R23, [R14.64+0x20] ; IMAD R28, R28, R29, R12 ; IMAD.WIDE R12, R2, 0x4, R18 ; LDG.E R25, [R14.64+0x24] ; IMAD R28, R16, R17, R28 ; LDG.E R18, [R18.64] ; IMAD.WIDE R16, R2, 0x4, R12 ; LDG.E R12, [R12.64] ; IMAD R28, R21, R20, R28 ; LDG.E R22, [R16.64] ; IMAD.WIDE R20, R2, 0x4, R16 ; LDG.E R29, [R14.64+0x28] ; LDG.E R19, [R14.64+0x2c] ; LDG.E R24, [R14.64+0x30] ; IMAD R28, R9, R8, R28 ; IMAD.WIDE R8, R2, 0x4, R20 ; LDG.E R20, [R20.64] ; LDG.E R21, [R14.64+0x38] ; IMAD R28, R11, R10, R28 ; IMAD.WIDE R10, R2, 0x4, R8 ; LDG.E R8, [R8.64] ; IMAD R13, R27, R26, R28 ; IMAD.WIDE R26, R2.reuse, 0x4, R10 ; LDG.E R10, [R10.64] ; LDG.E R9, [R14.64+0x34] ; IMAD.WIDE R16, R2, 0x4, R26 ; LDG.E R28, [R26.64] ; LDG.E R11, [R16.64] ; LDG.E R26, [R14.64+0x3c] ; IMAD R13, R18, R23, R13 ; IMAD R12, R12, R25, R13 ; IADD3 R6, R6, -0x10, RZ ; IMAD R12, R22, R29, R12 ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; IMAD R19, R20, R19, R12 ; UIADD3 UR6, UP0, UR6, 0x40, URZ ; IADD3 R4, R4, 0x10, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD R8, R8, R24, R19 ; IMAD R8, R10, R9, R8 ; IMAD R8, R28, R21, R8 ; IMAD R24, R11, R26, R8 ; IMAD.WIDE R8, R2, 0x4, R16 ; @P1 BRA 0x210 ; ISETP.GT.AND P1, PT, R6, 0x4, PT ; @!P1 BRA 0x940 ; IMAD.WIDE R16, R2, 0x4, R8 ; MOV R10, UR6 ; LDG.E R23, [R8.64] ; MOV R11, UR7 ; IMAD.WIDE R12, R2.reuse, 0x4, R16 ; LDG.E R16, [R16.64] ; IMAD.WIDE R10, R7, 0x4, R10 ; LDG.E R26, [R12.64] ; IMAD.WIDE R14, R2.reuse, 0x4, R12 ; LDG.E R22, [R10.64] ; LDG.E R25, [R10.64+0x4] ; IMAD.WIDE R18, R2, 0x4, R14 ; LDG.E R27, [R10.64+0x8] ; IMAD.WIDE R20, R2.reuse, 0x4, R18 ; LDG.E R14, [R14.64] ; LDG.E R29, [R10.64+0xc] ; IMAD.WIDE R8, R2, 0x4, R20 ; LDG.E R18, [R18.64] ; LDG.E R28, [R10.64+0x10] ; IMAD.WIDE R12, R2, 0x4, R8 ; LDG.E R20, [R20.64] ; LDG.E R15, [R10.64+0x14] ; LDG.E R17, [R8.64] ; LDG.E R19, [R10.64+0x1c] ; LDG.E R8, [R10.64+0x18] ; LDG.E R9, [R12.64] ; UIADD3 UR6, UP0, UR6, 0x20, URZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R4, R4, 0x8, RZ ; IADD3 R6, R6, -0x8, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD R22, R23, R22, R24 ; IMAD R16, R16, R25, R22 ; IMAD R16, R26, R27, R16 ; IMAD R29, R14, R29, R16 ; IMAD R18, R18, R28, R29 ; IMAD R15, R20, R15, R18 ; IMAD R8, R17, R8, R15 ; IMAD R24, R9, R19, R8 ; IMAD.WIDE R8, R2, 0x4, R12 ; ISETP.NE.OR P0, PT, R6, RZ, P0 ; @!P0 BRA 0xaf0 ; MOV R12, UR6 ; IMAD.WIDE R10, R2, 0x4, R8 ; MOV R13, UR7 ; LDG.E R9, [R8.64] ; IMAD.WIDE R12, R7, 0x4, R12 ; IMAD.WIDE R14, R2.reuse, 0x4, R10 ; LDG.E R18, [R12.64] ; LDG.E R11, [R10.64] ; IMAD.WIDE R16, R2, 0x4, R14 ; LDG.E R19, [R12.64+0x4] ; LDG.E R21, [R14.64] ; LDG.E R20, [R12.64+0x8] ; LDG.E R22, [R12.64+0xc] ; LDG.E R23, [R16.64] ; IADD3 R6, R6, -0x4, RZ ; ISETP.NE.AND P0, PT, R6, RZ, PT ; UIADD3 UR6, UP0, UR6, 0x10, URZ ; IADD3 R4, R4, 0x4, RZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; IMAD R18, R9, R18, R24 ; IMAD R18, R11, R19, R18 ; IMAD.WIDE R8, R2, 0x4, R16 ; IMAD R18, R21, R20, R18 ; IMAD R24, R23, R22, R18 ; @P0 BRA 0x960 ; ISETP.NE.AND P0, PT, R5, RZ, PT ; @!P0 BRA 0xbf0 ; HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD R6, R3, c[0x0][0x178], R4 ; IMAD R4, R4, c[0x0][0x178], R0 ; IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; LDG.E R11, [R8.64] ; LDG.E R4, [R6.64] ; IADD3 R5, R5, -0x1, RZ ; ISETP.NE.AND P0, PT, R5, RZ, PT ; IMAD.WIDE R8, R2, 0x4, R8 ; IADD3 R6, P1, R6, 0x4, RZ ; IADD3.X R7, RZ, R7, RZ, P1, !PT ; IMAD R24, R11, R4, R24 ; @P0 BRA 0xb60 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; MOV R2, 0x4 ; IMAD R3, R3, c[0x0][0x178], R0 ; IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; STG.E [R2.64], R24 ; EXIT ; BRA 0xc50; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000d3a60_00000000-6_9c097c90d1d97d773c65f06418e6890e826fdf8d.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3673: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3673: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z40__device_stub__Z15kernel_multiplyPiS_S_iPiS_S_i .type _Z40__device_stub__Z15kernel_multiplyPiS_S_iPiS_S_i, @function _Z40__device_stub__Z15kernel_multiplyPiS_S_iPiS_S_i: .LFB3695: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z15kernel_multiplyPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3695: .size _Z40__device_stub__Z15kernel_multiplyPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15kernel_multiplyPiS_S_iPiS_S_i .globl _Z15kernel_multiplyPiS_S_i .type _Z15kernel_multiplyPiS_S_i, @function _Z15kernel_multiplyPiS_S_i: .LFB3696: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z40__device_stub__Z15kernel_multiplyPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3696: .size _Z15kernel_multiplyPiS_S_i, .-_Z15kernel_multiplyPiS_S_i .globl _Z2mmPiS_S_i .type _Z2mmPiS_S_i, @function _Z2mmPiS_S_i: .LFB3669: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $40, %rsp .cfi_def_cfa_offset 80 movq %rdi, %rbp movq %rsi, %r12 movq %rdx, %r13 movl %ecx, %ebx movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl %ecx, %eax imull %ecx, %eax cmpl $512, %eax jg .L12 movl %ecx, %eax jmp .L13 .L12: pxor %xmm0, %xmm0 cvtsi2sdl %ecx, %xmm0 mulsd .LC0(%rip), %xmm0 movapd %xmm0, %xmm3 movsd .LC4(%rip), %xmm2 movapd %xmm0, %xmm1 andpd %xmm2, %xmm1 movsd .LC1(%rip), %xmm4 ucomisd %xmm1, %xmm4 jbe .L14 cvttsd2siq %xmm0, %rax pxor %xmm1, %xmm1 cvtsi2sdq %rax, %xmm1 cmpnlesd %xmm1, %xmm3 movsd .LC3(%rip), %xmm4 andpd %xmm4, %xmm3 addsd %xmm1, %xmm3 andnpd %xmm0, %xmm2 orpd %xmm2, %xmm3 .L14: cvttsd2siq %xmm3, %rax movl %eax, 20(%rsp) movl %eax, 24(%rsp) movl $512, %eax .L13: movl %eax, 8(%rsp) movl %eax, 12(%rsp) movl 16(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 8(%rsp), %rdx movq 20(%rsp), %rdi movl 28(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L17 .L11: addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L17: .cfi_restore_state movl %ebx, %ecx movq %r13, %rdx movq %r12, %rsi movq %rbp, %rdi call _Z40__device_stub__Z15kernel_multiplyPiS_S_iPiS_S_i jmp .L11 .cfi_endproc .LFE3669: .size _Z2mmPiS_S_i, .-_Z2mmPiS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC5: .string "\nEnter n:" .LC6: .string "\nMatrix A:\n" .LC7: .string "\t" .LC8: .string "\nMatrix B:\n" .LC9: .string "\nAnswer=\n" .LC10: .string "( " .LC11: .string " )\tE = " .LC12: .string "\tA = " .text .globl main .type main, @function main: .LFB3670: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $104, %rsp .cfi_def_cfa_offset 160 movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq 60(%rsp), %rsi leaq _ZSt3cin(%rip), %rdi call _ZNSirsERi@PLT movl 60(%rsp), %ebx leal 0(,%rbx,4), %eax movl %eax, 44(%rsp) imull %ebx, %eax movslq %eax, %r13 movq %r13, %rdi call malloc@PLT movq %rax, %rbp movq %r13, %rdi call malloc@PLT movq %rax, %r12 movq %r13, %rdi call malloc@PLT movq %rax, 16(%rsp) movq %r13, %rdi call malloc@PLT movq %rax, 24(%rsp) movl $0, %r13d testl %ebx, %ebx jg .L19 .L20: leaq .LC6(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl $0, %r14d leaq _ZSt4cout(%rip), %r13 leaq .LC7(%rip), %r15 cmpl $0, 60(%rsp) jg .L27 .L28: leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC8(%rip), %rsi movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl $0, %r14d movq %rbx, %r13 leaq .LC7(%rip), %r15 cmpl $0, 60(%rsp) jg .L35 .L36: leaq _ZSt4cout(%rip), %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl 60(%rsp), %ecx testl %ecx, %ecx jle .L43 movslq %ecx, %rbx leaq 0(,%rbx,4), %r8 movl $0, %edx movl $0, %eax movq %r12, 32(%rsp) movq 24(%rsp), %rdi jmp .L44 .L23: addl $1, %r13d movl 60(%rsp), %eax cmpl %r13d, %eax jle .L22 .L19: movl $0, %ebx cmpl $0, 60(%rsp) jle .L23 .L21: call rand@PLT movl 60(%rsp), %esi movl %esi, %ecx imull %r13d, %ecx addl %ebx, %ecx movslq %ecx, %rcx cltd idivl %esi movl %edx, 0(%rbp,%rcx,4) addl $1, %ebx cmpl %ebx, %esi jg .L21 jmp .L23 .L22: testl %eax, %eax jle .L20 movl $0, %r13d jmp .L24 .L26: addl $1, %r13d cmpl %r13d, 60(%rsp) jle .L20 .L24: movl $0, %ebx cmpl $0, 60(%rsp) jle .L26 .L25: call rand@PLT movl 60(%rsp), %esi movl %esi, %ecx imull %r13d, %ecx addl %ebx, %ecx movslq %ecx, %rcx cltd idivl %esi movl %edx, (%r12,%rcx,4) addl $1, %ebx cmpl %ebx, %esi jg .L25 jmp .L26 .L84: movq 88(%rsp), %rax subq %fs:40, %rax jne .L83 call _ZSt16__throw_bad_castv@PLT .L83: call __stack_chk_fail@PLT .L32: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) .L33: movsbl %al, %esi movq %r13, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT addl $1, %r14d cmpl %r14d, 60(%rsp) jle .L28 .L27: movl 60(%rsp), %eax movl $0, %ebx testl %eax, %eax jle .L34 .L29: imull %r14d, %eax addl %ebx, %eax cltq movl 0(%rbp,%rax,4), %esi movq %r13, %rdi call _ZNSolsEi@PLT movq %rax, %rdi movl $1, %edx movq %r15, %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT addl $1, %ebx movl 60(%rsp), %eax cmpl %ebx, %eax jg .L29 .L34: movq 0(%r13), %rax movq -24(%rax), %rax movq 240(%r13,%rax), %rbx testq %rbx, %rbx je .L84 cmpb $0, 56(%rbx) je .L32 movzbl 67(%rbx), %eax jmp .L33 .L86: movq 88(%rsp), %rax subq %fs:40, %rax jne .L85 call _ZSt16__throw_bad_castv@PLT .L85: call __stack_chk_fail@PLT .L40: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) .L41: movsbl %al, %esi movq %r13, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT addl $1, %r14d cmpl %r14d, 60(%rsp) jle .L36 .L35: movl 60(%rsp), %eax movl $0, %ebx testl %eax, %eax jle .L42 .L37: imull %r14d, %eax addl %ebx, %eax cltq movl (%r12,%rax,4), %esi movq %r13, %rdi call _ZNSolsEi@PLT movq %rax, %rdi movl $1, %edx movq %r15, %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT addl $1, %ebx movl 60(%rsp), %eax cmpl %ebx, %eax jg .L37 .L42: movq 0(%r13), %rax movq -24(%rax), %rax movq 240(%r13,%rax), %rbx testq %rbx, %rbx je .L86 cmpb $0, 56(%rbx) je .L40 movzbl 67(%rbx), %eax jmp .L41 .L87: movl %ebp, (%r14,%r12,4) addq $1, %r12 addq $4, %r13 cmpq %r12, %rbx je .L46 .L47: movq %r13, %r10 movq %r15, %rsi movl $0, %ebp .L45: movl (%rsi), %r9d imull (%r10), %r9d addl %r9d, %ebp addq $4, %rsi addq %r8, %r10 cmpq %r11, %rsi jne .L45 jmp .L87 .L46: movq 8(%rsp), %rbp addl $1, %eax addl %ecx, %edx cmpl %eax, %ecx je .L81 .L44: movq 32(%rsp), %r13 movslq %edx, %r9 leaq 0(,%r9,4), %r14 leaq 0(%rbp,%r14), %r15 addq %rbx, %r9 leaq 0(%rbp,%r9,4), %r11 addq %rdi, %r14 movl $0, %r12d movq %rbp, 8(%rsp) jmp .L47 .L81: movq 32(%rsp), %r12 .L43: movl 44(%rsp), %ebx imull %ebx, %ecx movslq %ecx, %rsi leaq 64(%rsp), %rdi call cudaMalloc@PLT movl %ebx, %esi imull 60(%rsp), %esi movslq %esi, %rsi leaq 72(%rsp), %rdi call cudaMalloc@PLT movl %ebx, %esi imull 60(%rsp), %esi movslq %esi, %rsi leaq 80(%rsp), %rdi call cudaMalloc@PLT movl %ebx, %edx imull 60(%rsp), %edx movslq %edx, %rdx movl $1, %ecx movq %rbp, %rsi movq 64(%rsp), %rdi call cudaMemcpy@PLT movl %ebx, %edx imull 60(%rsp), %edx movslq %edx, %rdx movl $1, %ecx movq %r12, %rsi movq 72(%rsp), %rdi call cudaMemcpy@PLT movl 60(%rsp), %ecx movq 80(%rsp), %rdx movq 72(%rsp), %rsi movq 64(%rsp), %rdi call _Z2mmPiS_S_i movl %ebx, %edx imull 60(%rsp), %edx movslq %edx, %rdx movl $2, %ecx movq 80(%rsp), %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT leaq .LC9(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl 60(%rsp), %eax imull %eax, %eax testl %eax, %eax jle .L48 movl $0, %ebx leaq .LC10(%rip), %r15 leaq _ZSt4cout(%rip), %r13 leaq .LC11(%rip), %r14 jmp .L53 .L89: movq 88(%rsp), %rax subq %fs:40, %rax jne .L88 call _ZSt16__throw_bad_castv@PLT .L88: call __stack_chk_fail@PLT .L51: movq %r12, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%r12), %rax movl $10, %esi movq %r12, %rdi call *48(%rax) .L52: movsbl %al, %esi movq %rbp, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl 60(%rsp), %eax addq $1, %rbx imull %eax, %eax cmpl %ebx, %eax jle .L48 .L53: movl $2, %edx movq %r15, %rsi movq %r13, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl %ebx, %esi movq %r13, %rdi call _ZNSolsEi@PLT movq %rax, %rbp movl $7, %edx movq %r14, %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq 24(%rsp), %rax movl (%rax,%rbx,4), %esi movq %rbp, %rdi call _ZNSolsEi@PLT movq %rax, %rbp movl $5, %edx leaq .LC12(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq 16(%rsp), %rax movl (%rax,%rbx,4), %esi movq %rbp, %rdi call _ZNSolsEi@PLT movq %rax, %rbp movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbp,%rax), %r12 testq %r12, %r12 je .L89 cmpb $0, 56(%r12) je .L51 movzbl 67(%r12), %eax jmp .L52 .L48: movq 64(%rsp), %rdi call cudaFree@PLT movq 72(%rsp), %rdi call cudaFree@PLT movq 80(%rsp), %rdi call cudaFree@PLT call cudaDeviceSynchronize@PLT movq 88(%rsp), %rdx subq %fs:40, %rdx jne .L90 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L90: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE3670: .size main, .-main .section .rodata.str1.1 .LC13: .string "_Z15kernel_multiplyPiS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3698: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC13(%rip), %rdx movq %rdx, %rcx leaq _Z15kernel_multiplyPiS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3698: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC0: .long 0 .long 1063256064 .align 8 .LC1: .long 0 .long 1127219200 .align 8 .LC3: .long 0 .long 1072693248 .align 8 .LC4: .long -1 .long 2147483647 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15kernel_multiplyPiS_S_i ; -- Begin function _Z15kernel_multiplyPiS_S_i .globl _Z15kernel_multiplyPiS_S_i .p2align 8 .type _Z15kernel_multiplyPiS_S_i,@function _Z15kernel_multiplyPiS_S_i: ; @_Z15kernel_multiplyPiS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s3, s[0:1], 0x2c s_load_b32 s2, s[0:1], 0x18 v_bfe_u32 v2, v0, 10, 10 v_and_b32_e32 v3, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_lshr_b32 s4, s3, 16 s_and_b32 s3, s3, 0xffff s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3] v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4] s_mov_b32 s3, exec_lo v_max_i32_e32 v2, v0, v1 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s2, v2 s_cbranch_execz .LBB0_6 ; %bb.1: ; %.preheader s_cmp_lt_i32 s2, 1 s_cbranch_scc1 .LBB0_4 ; %bb.2: ; %.lr.ph s_load_b128 s[4:7], s[0:1], 0x0 v_mul_lo_u32 v2, v0, s2 s_mov_b32 s3, s2 v_mov_b32_e32 v5, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[3:4], 2, v[2:3] v_mov_b32_e32 v2, 0 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v3, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo .p2align 6 .LBB0_3: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_ashrrev_i32_e32 v6, 31, v5 s_add_i32 s3, s3, -1 s_cmp_eq_u32 s3, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 2, v[5:6] v_add_co_u32 v6, vcc_lo, s6, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo global_load_b32 v8, v[3:4], off global_load_b32 v9, v[6:7], off s_waitcnt vmcnt(0) v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3] v_add_co_u32 v3, vcc_lo, v3, 4 v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5 s_cbranch_scc0 .LBB0_3 s_branch .LBB0_5 .LBB0_4: v_mov_b32_e32 v2, 0 .LBB0_5: ; %Flow41 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2] s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[0:1], 2, v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_6: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15kernel_multiplyPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15kernel_multiplyPiS_S_i, .Lfunc_end0-_Z15kernel_multiplyPiS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 360 ; NumSgprs: 18 ; NumVgprs: 10 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 10 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15kernel_multiplyPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15kernel_multiplyPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "9c097c90d1d97d773c65f06418e6890e826fdf8d.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z30__device_stub__kernel_multiplyPiS_S_i # -- Begin function _Z30__device_stub__kernel_multiplyPiS_S_i .p2align 4, 0x90 .type _Z30__device_stub__kernel_multiplyPiS_S_i,@function _Z30__device_stub__kernel_multiplyPiS_S_i: # @_Z30__device_stub__kernel_multiplyPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z15kernel_multiplyPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z30__device_stub__kernel_multiplyPiS_S_i, .Lfunc_end0-_Z30__device_stub__kernel_multiplyPiS_S_i .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function _Z2mmPiS_S_i .LCPI1_0: .quad 0x3f60000000000000 # double 0.001953125 .text .globl _Z2mmPiS_S_i .p2align 4, 0x90 .type _Z2mmPiS_S_i,@function _Z2mmPiS_S_i: # @_Z2mmPiS_S_i .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl %ecx, %ebx movq %rdx, %r14 movq %rsi, %r15 movq %rdi, %r12 movabsq $4294967297, %r13 # imm = 0x100000001 movl %ecx, %eax imull %ecx, %eax cmpl $513, %eax # imm = 0x201 jb .LBB1_1 # %bb.2: cvtsi2sd %ebx, %xmm0 mulsd .LCPI1_0(%rip), %xmm0 callq ceil@PLT cvttsd2si %xmm0, %rax movl %eax, %eax imulq %rax, %r13 movabsq $2199023256064, %rdx # imm = 0x20000000200 jmp .LBB1_3 .LBB1_1: movl %ebx, %eax movq %rax, %rdx shlq $32, %rdx orq %rax, %rdx .LBB1_3: movq %r13, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_5 # %bb.4: movq %r12, 72(%rsp) movq %r15, 64(%rsp) movq %r14, 56(%rsp) movl %ebx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z15kernel_multiplyPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_5: addq $112, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z2mmPiS_S_i, .Lfunc_end1-_Z2mmPiS_S_i .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $56, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $_ZSt4cout, %edi movl $.L.str, %esi movl $9, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l leaq 12(%rsp), %rsi movl $_ZSt3cin, %edi callq _ZNSirsERi movl 12(%rsp), %eax leal (,%rax,4), %ecx movl %ecx, 44(%rsp) # 4-byte Spill imull %ecx, %eax movslq %eax, %r14 movq %r14, %rdi callq malloc movq %rax, %r12 movq %r14, %rdi callq malloc movq %rax, %r15 movq %r14, %rdi callq malloc movq %rax, %rbx movq %r14, %rdi callq malloc movq %rax, %r14 cmpl $0, 12(%rsp) jle .LBB2_6 # %bb.1: # %.preheader105.preheader xorl %r13d, %r13d jmp .LBB2_2 .p2align 4, 0x90 .LBB2_5: # %._crit_edge # in Loop: Header=BB2_2 Depth=1 incl %r13d cmpl 12(%rsp), %r13d jge .LBB2_6 .LBB2_2: # %.preheader105 # =>This Loop Header: Depth=1 # Child Loop BB2_4 Depth 2 cmpl $0, 12(%rsp) jle .LBB2_5 # %bb.3: # %.lr.ph.preheader # in Loop: Header=BB2_2 Depth=1 xorl %ebp, %ebp .p2align 4, 0x90 .LBB2_4: # %.lr.ph # Parent Loop BB2_2 Depth=1 # => This Inner Loop Header: Depth=2 callq rand movl 12(%rsp), %ecx cltd idivl %ecx imull %r13d, %ecx movslq %ecx, %rax addq %rbp, %rax movl %edx, (%r12,%rax,4) incq %rbp cmpl 12(%rsp), %ebp jl .LBB2_4 jmp .LBB2_5 .LBB2_6: # %.preheader104 cmpl $0, 12(%rsp) jle .LBB2_12 # %bb.7: # %.preheader103.preheader xorl %r13d, %r13d jmp .LBB2_8 .p2align 4, 0x90 .LBB2_11: # %._crit_edge110 # in Loop: Header=BB2_8 Depth=1 incl %r13d cmpl 12(%rsp), %r13d jge .LBB2_12 .LBB2_8: # %.preheader103 # =>This Loop Header: Depth=1 # Child Loop BB2_10 Depth 2 cmpl $0, 12(%rsp) jle .LBB2_11 # %bb.9: # %.lr.ph109.preheader # in Loop: Header=BB2_8 Depth=1 xorl %ebp, %ebp .p2align 4, 0x90 .LBB2_10: # %.lr.ph109 # Parent Loop BB2_8 Depth=1 # => This Inner Loop Header: Depth=2 callq rand movl 12(%rsp), %ecx cltd idivl %ecx imull %r13d, %ecx movslq %ecx, %rax addq %rbp, %rax movl %edx, (%r15,%rax,4) incq %rbp cmpl 12(%rsp), %ebp jl .LBB2_10 jmp .LBB2_11 .LBB2_12: # %._crit_edge112 movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $11, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l cmpl $0, 12(%rsp) jle .LBB2_20 # %bb.13: # %.preheader102.preheader xorl %ebp, %ebp jmp .LBB2_14 .p2align 4, 0x90 .LBB2_32: # in Loop: Header=BB2_14 Depth=1 movq %r13, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r13), %rax movq %r13, %rdi movl $10, %esi callq *48(%rax) .LBB2_33: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit84 # in Loop: Header=BB2_14 Depth=1 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv incl %ebp cmpl 12(%rsp), %ebp jge .LBB2_20 .LBB2_14: # %.preheader102 # =>This Loop Header: Depth=1 # Child Loop BB2_16 Depth 2 movl 12(%rsp), %eax testl %eax, %eax jle .LBB2_17 # %bb.15: # %.lr.ph114.preheader # in Loop: Header=BB2_14 Depth=1 xorl %r13d, %r13d .p2align 4, 0x90 .LBB2_16: # %.lr.ph114 # Parent Loop BB2_14 Depth=1 # => This Inner Loop Header: Depth=2 imull %ebp, %eax cltq addq %r13, %rax movl (%r12,%rax,4), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movl $.L.str.2, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 12(%rsp), %eax incq %r13 cmpl %eax, %r13d jl .LBB2_16 .LBB2_17: # %._crit_edge115 # in Loop: Header=BB2_14 Depth=1 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r13 testq %r13, %r13 je .LBB2_55 # %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i81 # in Loop: Header=BB2_14 Depth=1 cmpb $0, 56(%r13) je .LBB2_32 # %bb.19: # in Loop: Header=BB2_14 Depth=1 movzbl 67(%r13), %eax jmp .LBB2_33 .LBB2_20: # %._crit_edge117 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r13 testq %r13, %r13 je .LBB2_55 # %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r13) je .LBB2_23 # %bb.22: movzbl 67(%r13), %eax jmp .LBB2_24 .LBB2_23: movq %r13, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r13), %rax movq %r13, %rdi movl $10, %esi callq *48(%rax) .LBB2_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $11, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l cmpl $0, 12(%rsp) jle .LBB2_34 # %bb.25: # %.preheader101.preheader xorl %ebp, %ebp jmp .LBB2_26 .p2align 4, 0x90 .LBB2_50: # in Loop: Header=BB2_26 Depth=1 movq %r13, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r13), %rax movq %r13, %rdi movl $10, %esi callq *48(%rax) .LBB2_51: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit94 # in Loop: Header=BB2_26 Depth=1 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv incl %ebp cmpl 12(%rsp), %ebp jge .LBB2_34 .LBB2_26: # %.preheader101 # =>This Loop Header: Depth=1 # Child Loop BB2_28 Depth 2 movl 12(%rsp), %eax testl %eax, %eax jle .LBB2_29 # %bb.27: # %.lr.ph119.preheader # in Loop: Header=BB2_26 Depth=1 xorl %r13d, %r13d .p2align 4, 0x90 .LBB2_28: # %.lr.ph119 # Parent Loop BB2_26 Depth=1 # => This Inner Loop Header: Depth=2 imull %ebp, %eax cltq addq %r13, %rax movl (%r15,%rax,4), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movl $.L.str.2, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 12(%rsp), %eax incq %r13 cmpl %eax, %r13d jl .LBB2_28 .LBB2_29: # %._crit_edge120 # in Loop: Header=BB2_26 Depth=1 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r13 testq %r13, %r13 je .LBB2_55 # %bb.30: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i91 # in Loop: Header=BB2_26 Depth=1 cmpb $0, 56(%r13) je .LBB2_50 # %bb.31: # in Loop: Header=BB2_26 Depth=1 movzbl 67(%r13), %eax jmp .LBB2_51 .LBB2_34: # %._crit_edge123 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r13 testq %r13, %r13 je .LBB2_55 # %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i86 cmpb $0, 56(%r13) movq %rbx, 48(%rsp) # 8-byte Spill je .LBB2_37 # %bb.36: movzbl 67(%r13), %eax jmp .LBB2_38 .LBB2_37: movq %r13, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r13), %rax movq %r13, %rdi movl $10, %esi callq *48(%rax) .LBB2_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit89 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl 12(%rsp), %eax testl %eax, %eax jle .LBB2_45 # %bb.39: # %.preheader100.lr.ph leaq (,%rax,4), %rcx xorl %edx, %edx xorl %esi, %esi .p2align 4, 0x90 .LBB2_40: # %.preheader100 # =>This Loop Header: Depth=1 # Child Loop BB2_41 Depth 2 # Child Loop BB2_42 Depth 3 movl %edx, %edi leaq (%r12,%rdi,4), %rdi movq %rsi, %r8 imulq %rax, %r8 leaq (%r14,%r8,4), %r8 movq %r15, %r9 xorl %r10d, %r10d .p2align 4, 0x90 .LBB2_41: # %.preheader # Parent Loop BB2_40 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB2_42 Depth 3 xorl %r11d, %r11d movq %r9, %r13 xorl %ebp, %ebp .p2align 4, 0x90 .LBB2_42: # Parent Loop BB2_40 Depth=1 # Parent Loop BB2_41 Depth=2 # => This Inner Loop Header: Depth=3 movl (%r13), %ebx imull (%rdi,%r11,4), %ebx addl %ebx, %ebp incq %r11 addq %rcx, %r13 cmpq %r11, %rax jne .LBB2_42 # %bb.43: # %._crit_edge127 # in Loop: Header=BB2_41 Depth=2 movl %ebp, (%r8,%r10,4) incq %r10 addq $4, %r9 cmpq %rax, %r10 jne .LBB2_41 # %bb.44: # %._crit_edge129 # in Loop: Header=BB2_40 Depth=1 incq %rsi addl %eax, %edx cmpq %rax, %rsi jne .LBB2_40 .LBB2_45: # %._crit_edge131 movl 44(%rsp), %ebx # 4-byte Reload imull %ebx, %eax movslq %eax, %rsi leaq 32(%rsp), %rdi callq hipMalloc movslq 12(%rsp), %rsi movslq %ebx, %r13 imulq %r13, %rsi leaq 24(%rsp), %rdi callq hipMalloc movslq 12(%rsp), %rsi imulq %r13, %rsi leaq 16(%rsp), %rdi callq hipMalloc movq 32(%rsp), %rdi movslq 12(%rsp), %rdx imulq %r13, %rdx movq %r12, %rsi movl $1, %ecx callq hipMemcpy movq 24(%rsp), %rdi movslq 12(%rsp), %rdx imulq %r13, %rdx movq %r15, %rsi movl $1, %ecx callq hipMemcpy movq 32(%rsp), %rdi movq 24(%rsp), %rsi movq 16(%rsp), %rdx movl 12(%rsp), %ecx callq _Z2mmPiS_S_i movq 16(%rsp), %rsi movslq 12(%rsp), %rdx imulq %r13, %rdx movq 48(%rsp), %rbx # 8-byte Reload movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movl $_ZSt4cout, %edi movl $.L.str.4, %esi movl $9, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l cmpl $0, 12(%rsp) je .LBB2_54 # %bb.46: # %.lr.ph135.preheader xorl %r15d, %r15d jmp .LBB2_47 .p2align 4, 0x90 .LBB2_52: # in Loop: Header=BB2_47 Depth=1 movq %r12, %rdi movq %rax, %r13 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r12), %rax movq %r12, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r13, %rax .LBB2_53: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit99 # in Loop: Header=BB2_47 Depth=1 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv incq %r15 movl 12(%rsp), %eax imull %eax, %eax cmpq %rax, %r15 jae .LBB2_54 .LBB2_47: # %.lr.ph135 # =>This Inner Loop Header: Depth=1 movl $_ZSt4cout, %edi movl $.L.str.5, %esi movl $2, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %r15d, %esi callq _ZNSolsEi movq %rax, %r12 movl $.L.str.6, %esi movl $7, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl (%r14,%r15,4), %esi movq %r12, %rdi callq _ZNSolsEi movq %rax, %r12 movl $.L.str.7, %esi movl $5, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl (%rbx,%r15,4), %esi movq %r12, %rdi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %r12 testq %r12, %r12 je .LBB2_55 # %bb.48: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i96 # in Loop: Header=BB2_47 Depth=1 cmpb $0, 56(%r12) je .LBB2_52 # %bb.49: # in Loop: Header=BB2_47 Depth=1 movzbl 67(%r12), %ecx jmp .LBB2_53 .LBB2_54: # %._crit_edge136 movq 32(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree callq hipDeviceSynchronize addq $56, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_55: .cfi_def_cfa_offset 112 callq _ZSt16__throw_bad_castv .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15kernel_multiplyPiS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z15kernel_multiplyPiS_S_i,@object # @_Z15kernel_multiplyPiS_S_i .section .rodata,"a",@progbits .globl _Z15kernel_multiplyPiS_S_i .p2align 3, 0x0 _Z15kernel_multiplyPiS_S_i: .quad _Z30__device_stub__kernel_multiplyPiS_S_i .size _Z15kernel_multiplyPiS_S_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "\nEnter n:" .size .L.str, 10 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "\nMatrix A:\n" .size .L.str.1, 12 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "\t" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "\nMatrix B:\n" .size .L.str.3, 12 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "\nAnswer=\n" .size .L.str.4, 10 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "( " .size .L.str.5, 3 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz " )\tE = " .size .L.str.6, 8 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "\tA = " .size .L.str.7, 6 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z15kernel_multiplyPiS_S_i" .size .L__unnamed_1, 27 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__kernel_multiplyPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15kernel_multiplyPiS_S_i .addrsig_sym _ZSt4cout .addrsig_sym _ZSt3cin .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
4,515
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code for sm_80 Function : _Z6reducePfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R6, SR_CTAID.X ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; ULDC.64 UR6, c[0x0][0x118] ; S2R R7, SR_TID.X ; IMAD R2, R6, c[0x0][0x0], R7 ; IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; LDG.E R2, [R2.64] ; ULDC UR4, c[0x0][0x0] ; ISETP.NE.AND P0, PT, R7, RZ, PT ; USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; ISETP.NE.AND P1, PT, RZ, UR4, PT ; STS [R7.X4], R2 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P1 BRA 0x1b0 ; SHF.L.U32 R0, R7, 0x2, RZ ; IMAD.U32 R3, RZ, RZ, UR4 ; ISETP.GE.U32.AND P1, PT, R7, R3, PT ; @!P1 LEA R2, R3, R0, 0x2 ; @!P1 LDS R4, [R7.X4] ; SHF.R.U32.HI R3, RZ, 0x1, R3 ; @!P1 LDS R5, [R2] ; @!P1 FADD R4, R4, R5 ; @!P1 STS [R7.X4], R4 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.AND P1, PT, R3, RZ, PT ; @P1 BRA 0x110 ; @P0 EXIT ; LDS R5, [RZ] ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; STG.E [R2.64], R5 ; EXIT ; BRA 0x210; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z13myFirstKernelPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R5, SR_CTAID.X ; HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R0, SR_TID.X ; IMAD R5, R5, c[0x0][0x0], R0 ; IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; STG.E [R2.64], R5 ; EXIT ; BRA 0x90; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00016c5d_00000000-6_352bbfe3abf1bb66b5104c395863d6ac81383965.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2065: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2065: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .globl _ZN1A5get_aEv .type _ZN1A5get_aEv, @function _ZN1A5get_aEv: .LFB2057: .cfi_startproc endbr64 movl (%rdi), %eax ret .cfi_endproc .LFE2057: .size _ZN1A5get_aEv, .-_ZN1A5get_aEv .align 2 .globl _ZN1A5set_aEi .type _ZN1A5set_aEi, @function _ZN1A5set_aEi: .LFB2058: .cfi_startproc endbr64 movl %esi, (%rdi) ret .cfi_endproc .LFE2058: .size _ZN1A5set_aEi, .-_ZN1A5set_aEi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Cuda error: %s: %s.\n" .text .globl _Z14checkCUDAErrorPKc .type _Z14checkCUDAErrorPKc, @function _Z14checkCUDAErrorPKc: .LFB2060: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx call cudaGetLastError@PLT testl %eax, %eax jne .L8 popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L8: .cfi_restore_state movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %r8 movq %rbx, %rcx leaq .LC0(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $-1, %edi call exit@PLT .cfi_endproc .LFE2060: .size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc .section .rodata.str1.1 .LC1: .string "Alloc = 4 x %d MB = %d MB\n" .LC2: .string "cudaMalloc[0]" .LC3: .string "cudaMalloc[1]" .LC4: .string "cudaMalloc[2]" .LC5: .string "cudaMalloc[3]" .LC6: .string "cudaFree" .text .globl _Z13cuda_mem_testiPPc .type _Z13cuda_mem_testiPPc, @function _Z13cuda_mem_testiPPc: .LFB2061: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $104857600, %ebx movl $100, %ebp leaq .LC1(%rip), %r15 leaq .LC2(%rip), %r14 leaq .LC3(%rip), %r13 .L10: leal 0(,%rbp,4), %ecx movl %ebp, %edx movq %r15, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %rsp, %rdi movq %rbx, %rsi call cudaMalloc@PLT movq %r14, %rdi call _Z14checkCUDAErrorPKc leaq 8(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movq %r13, %rdi call _Z14checkCUDAErrorPKc leaq 16(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC4(%rip), %rdi call _Z14checkCUDAErrorPKc leaq 24(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC5(%rip), %rdi call _Z14checkCUDAErrorPKc movq (%rsp), %rdi call cudaFree@PLT leaq .LC6(%rip), %r12 movq %r12, %rdi call _Z14checkCUDAErrorPKc movq 8(%rsp), %rdi call cudaFree@PLT movq %r12, %rdi call _Z14checkCUDAErrorPKc movq 16(%rsp), %rdi call cudaFree@PLT movq %r12, %rdi call _Z14checkCUDAErrorPKc movq 24(%rsp), %rdi call cudaFree@PLT movq %r12, %rdi call _Z14checkCUDAErrorPKc addl $100, %ebp addq $104857600, %rbx cmpl $1200, %ebp jne .L10 movq 40(%rsp), %rax subq %fs:40, %rax jne .L14 movl $0, %eax addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L14: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2061: .size _Z13cuda_mem_testiPPc, .-_Z13cuda_mem_testiPPc .section .rodata.str1.1 .LC7: .string "C++ test: %d\n" .text .globl main .type main, @function main: .LFB2062: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movl %edi, %ebx movq %rsi, %rbp movl $32, %edx leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %rbp, %rsi movl %ebx, %edi call _Z13cuda_mem_testiPPc addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size main, .-main .globl _Z33__device_stub__Z13myFirstKernelPiPi .type _Z33__device_stub__Z13myFirstKernelPiPi, @function _Z33__device_stub__Z13myFirstKernelPiPi: .LFB2087: .cfi_startproc endbr64 subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 8(%rsp) movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L21 .L17: movq 88(%rsp), %rax subq %fs:40, %rax jne .L22 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L21: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 120 pushq 24(%rsp) .cfi_def_cfa_offset 128 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z13myFirstKernelPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 112 jmp .L17 .L22: call __stack_chk_fail@PLT .cfi_endproc .LFE2087: .size _Z33__device_stub__Z13myFirstKernelPiPi, .-_Z33__device_stub__Z13myFirstKernelPiPi .globl _Z13myFirstKernelPi .type _Z13myFirstKernelPi, @function _Z13myFirstKernelPi: .LFB2088: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z33__device_stub__Z13myFirstKernelPiPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2088: .size _Z13myFirstKernelPi, .-_Z13myFirstKernelPi .section .rodata.str1.1 .LC8: .string "cudaMalloc" .LC9: .string "kernel execution" .LC10: .string "cudaMemcpy" .LC11: .string "Correct!\n" .text .globl _Z11cuda_test_1iPPc .type _Z11cuda_test_1iPPc, @function _Z11cuda_test_1iPPc: .LFB2059: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 subq $48, %rsp .cfi_def_cfa_offset 64 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $256, %edi call malloc@PLT movq %rax, %rbx leaq 8(%rsp), %rdi movl $256, %esi call cudaMalloc@PLT leaq .LC8(%rip), %rdi call _Z14checkCUDAErrorPKc movl $8, 16(%rsp) movl $1, 20(%rsp) movl $8, 28(%rsp) movl $1, 32(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L29 .L26: call cudaThreadSynchronize@PLT leaq .LC9(%rip), %rdi call _Z14checkCUDAErrorPKc movl $2, %ecx movl $256, %edx movq 8(%rsp), %rsi movq %rbx, %rdi call cudaMemcpy@PLT leaq .LC10(%rip), %rdi call _Z14checkCUDAErrorPKc movq 8(%rsp), %rdi call cudaFree@PLT movq %rbx, %rdi call free@PLT leaq .LC11(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L30 movl $0, %eax addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 ret .L29: .cfi_restore_state movq 8(%rsp), %rdi call _Z33__device_stub__Z13myFirstKernelPiPi jmp .L26 .L30: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size _Z11cuda_test_1iPPc, .-_Z11cuda_test_1iPPc .globl _Z27__device_stub__Z6reducePfS_PfS_ .type _Z27__device_stub__Z6reducePfS_PfS_, @function _Z27__device_stub__Z6reducePfS_PfS_: .LFB2089: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L35 .L31: movq 104(%rsp), %rax subq %fs:40, %rax jne .L36 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L35: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z6reducePfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L31 .L36: call __stack_chk_fail@PLT .cfi_endproc .LFE2089: .size _Z27__device_stub__Z6reducePfS_PfS_, .-_Z27__device_stub__Z6reducePfS_PfS_ .globl _Z6reducePfS_ .type _Z6reducePfS_, @function _Z6reducePfS_: .LFB2090: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z6reducePfS_PfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2090: .size _Z6reducePfS_, .-_Z6reducePfS_ .section .rodata.str1.1 .LC12: .string "_Z6reducePfS_" .LC13: .string "_Z13myFirstKernelPi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2092: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _Z6reducePfS_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC13(%rip), %rdx movq %rdx, %rcx leaq _Z13myFirstKernelPi(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2092: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13myFirstKernelPi ; -- Begin function _Z13myFirstKernelPi .globl _Z13myFirstKernelPi .p2align 8 .type _Z13myFirstKernelPi,@function _Z13myFirstKernelPi: ; @_Z13myFirstKernelPi ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x14 s_load_b64 s[0:1], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[1:2] v_add_co_u32 v2, vcc_lo, s0, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo global_store_b32 v[2:3], v1, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13myFirstKernelPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 264 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13myFirstKernelPi, .Lfunc_end0-_Z13myFirstKernelPi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 96 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z6reducePfS_ ; -- Begin function _Z6reducePfS_ .globl _Z6reducePfS_ .p2align 8 .type _Z6reducePfS_,@function _Z6reducePfS_: ; @_Z6reducePfS_ ; %bb.0: s_clause 0x1 s_load_b32 s3, s[0:1], 0x1c s_load_b64 s[4:5], s[0:1], 0x0 s_mov_b32 s2, s15 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1] v_mov_b32_e32 v2, 0 s_cmp_lt_u32 s3, 2 v_lshlrev_b64 v[1:2], 2, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, s4, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo global_load_b32 v2, v[1:2], off v_lshl_add_u32 v1, v0, 2, 0 s_waitcnt vmcnt(0) ds_store_b32 v1, v2 s_waitcnt lgkmcnt(0) s_barrier s_branch .LBB1_2 .p2align 6 .LBB1_1: ; in Loop: Header=BB1_2 Depth=1 s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_barrier s_cmp_lt_u32 s3, 4 s_mov_b32 s3, s4 .LBB1_2: ; =>This Inner Loop Header: Depth=1 buffer_gl0_inv s_cbranch_scc1 .LBB1_5 ; %bb.3: ; %.lr.ph ; in Loop: Header=BB1_2 Depth=1 s_lshr_b32 s4, s3, 1 s_mov_b32 s5, exec_lo v_cmpx_gt_u32_e64 s4, v0 s_cbranch_execz .LBB1_1 ; %bb.4: ; in Loop: Header=BB1_2 Depth=1 v_add_nc_u32_e32 v2, s4, v0 s_delay_alu instid0(VALU_DEP_1) v_lshl_add_u32 v2, v2, 2, 0 ds_load_b32 v2, v2 ds_load_b32 v3, v1 s_waitcnt lgkmcnt(0) v_add_f32_e32 v2, v2, v3 ds_store_b32 v1, v2 s_branch .LBB1_1 .LBB1_5: ; %._crit_edge s_mov_b32 s3, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB1_7 ; %bb.6: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 s_load_b64 s[0:1], s[0:1], 0x8 s_mov_b32 s3, 0 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b64 s[2:3], s[2:3], 2 ds_load_b32 v0, v0 s_waitcnt lgkmcnt(0) s_add_u32 s0, s0, s2 s_addc_u32 s1, s1, s3 global_store_b32 v1, v0, s[0:1] .LBB1_7: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6reducePfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z6reducePfS_, .Lfunc_end1-_Z6reducePfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 304 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: hidden_block_count_x - .offset: 12 .size: 4 .value_kind: hidden_block_count_y - .offset: 16 .size: 4 .value_kind: hidden_block_count_z - .offset: 20 .size: 2 .value_kind: hidden_group_size_x - .offset: 22 .size: 2 .value_kind: hidden_group_size_y - .offset: 24 .size: 2 .value_kind: hidden_group_size_z - .offset: 26 .size: 2 .value_kind: hidden_remainder_x - .offset: 28 .size: 2 .value_kind: hidden_remainder_y - .offset: 30 .size: 2 .value_kind: hidden_remainder_z - .offset: 48 .size: 8 .value_kind: hidden_global_offset_x - .offset: 56 .size: 8 .value_kind: hidden_global_offset_y - .offset: 64 .size: 8 .value_kind: hidden_global_offset_z - .offset: 72 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 264 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13myFirstKernelPi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13myFirstKernelPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims - .offset: 136 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6reducePfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6reducePfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "352bbfe3abf1bb66b5104c395863d6ac81383965.hip" .globl _ZN1A5get_aEv # -- Begin function _ZN1A5get_aEv .p2align 4, 0x90 .type _ZN1A5get_aEv,@function _ZN1A5get_aEv: # @_ZN1A5get_aEv .cfi_startproc # %bb.0: movl (%rdi), %eax retq .Lfunc_end0: .size _ZN1A5get_aEv, .Lfunc_end0-_ZN1A5get_aEv .cfi_endproc # -- End function .globl _ZN1A5set_aEi # -- Begin function _ZN1A5set_aEi .p2align 4, 0x90 .type _ZN1A5set_aEi,@function _ZN1A5set_aEi: # @_ZN1A5set_aEi .cfi_startproc # %bb.0: movl %esi, (%rdi) retq .Lfunc_end1: .size _ZN1A5set_aEi, .Lfunc_end1-_ZN1A5set_aEi .cfi_endproc # -- End function .globl _Z28__device_stub__myFirstKernelPi # -- Begin function _Z28__device_stub__myFirstKernelPi .p2align 4, 0x90 .type _Z28__device_stub__myFirstKernelPi,@function _Z28__device_stub__myFirstKernelPi: # @_Z28__device_stub__myFirstKernelPi .cfi_startproc # %bb.0: subq $72, %rsp .cfi_def_cfa_offset 80 movq %rdi, 64(%rsp) leaq 64(%rsp), %rax movq %rax, (%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d movq %rsp, %r9 movl $_Z13myFirstKernelPi, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $88, %rsp .cfi_adjust_cfa_offset -88 retq .Lfunc_end2: .size _Z28__device_stub__myFirstKernelPi, .Lfunc_end2-_Z28__device_stub__myFirstKernelPi .cfi_endproc # -- End function .globl _Z21__device_stub__reducePfS_ # -- Begin function _Z21__device_stub__reducePfS_ .p2align 4, 0x90 .type _Z21__device_stub__reducePfS_,@function _Z21__device_stub__reducePfS_: # @_Z21__device_stub__reducePfS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z6reducePfS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end3: .size _Z21__device_stub__reducePfS_, .Lfunc_end3-_Z21__device_stub__reducePfS_ .cfi_endproc # -- End function .globl _Z11cuda_test_1iPPc # -- Begin function _Z11cuda_test_1iPPc .p2align 4, 0x90 .type _Z11cuda_test_1iPPc,@function _Z11cuda_test_1iPPc: # @_Z11cuda_test_1iPPc .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $80, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -16 movl $256, %edi # imm = 0x100 callq malloc movq %rax, %rbx leaq 8(%rsp), %rdi movl $256, %esi # imm = 0x100 callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB4_1 # %bb.3: # %_Z14checkCUDAErrorPKc.exit movabsq $4294967304, %rdi # imm = 0x100000008 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB4_5 # %bb.4: movq 8(%rsp), %rax movq %rax, 72(%rsp) leaq 72(%rsp), %rax movq %rax, 16(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 16(%rsp), %r9 movl $_Z13myFirstKernelPi, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB4_5: callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax jne .LBB4_6 # %bb.7: # %_Z14checkCUDAErrorPKc.exit22 movq 8(%rsp), %rsi movl $256, %edx # imm = 0x100 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB4_8 # %bb.9: # %.preheader.preheader movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free movl $.Lstr, %edi callq puts@PLT xorl %eax, %eax addq $80, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .LBB4_1: .cfi_def_cfa_offset 96 movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.4, %esi movl $.L.str, %edx jmp .LBB4_2 .LBB4_6: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.4, %esi movl $.L.str.1, %edx jmp .LBB4_2 .LBB4_8: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.4, %esi movl $.L.str.2, %edx .LBB4_2: movq %rbx, %rdi movq %rax, %rcx xorl %eax, %eax callq fprintf movl $-1, %edi callq exit .Lfunc_end4: .size _Z11cuda_test_1iPPc, .Lfunc_end4-_Z11cuda_test_1iPPc .cfi_endproc # -- End function .globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc .p2align 4, 0x90 .type _Z14checkCUDAErrorPKc,@function _Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rdi, %rbx callq hipGetLastError testl %eax, %eax jne .LBB5_2 # %bb.1: addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB5_2: .cfi_def_cfa_offset 32 movq stderr(%rip), %r14 movl %eax, %edi callq hipGetErrorString movl $.L.str.4, %esi movq %r14, %rdi movq %rbx, %rdx movq %rax, %rcx xorl %eax, %eax callq fprintf movl $-1, %edi callq exit .Lfunc_end5: .size _Z14checkCUDAErrorPKc, .Lfunc_end5-_Z14checkCUDAErrorPKc .cfi_endproc # -- End function .globl _Z13cuda_mem_testiPPc # -- Begin function _Z13cuda_mem_testiPPc .p2align 4, 0x90 .type _Z13cuda_mem_testiPPc,@function _Z13cuda_mem_testiPPc: # @_Z13cuda_mem_testiPPc .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $40, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 leaq 16(%rsp), %r14 movl $400, %ebp # imm = 0x190 movl $104857600, %r15d # imm = 0x6400000 leaq 24(%rsp), %r12 movq %rsp, %r13 xorl %ebx, %ebx .p2align 4, 0x90 .LBB6_2: # =>This Inner Loop Header: Depth=1 leal 100(%rbx), %esi movl $.L.str.5, %edi movl %ebp, %edx xorl %eax, %eax callq printf movq %r13, %rdi movq %r15, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB6_3 # %bb.5: # %_Z14checkCUDAErrorPKc.exit # in Loop: Header=BB6_2 Depth=1 leaq 8(%rsp), %rdi movq %r15, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB6_6 # %bb.7: # %_Z14checkCUDAErrorPKc.exit9 # in Loop: Header=BB6_2 Depth=1 movq %r14, %rdi movq %r15, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB6_8 # %bb.9: # %_Z14checkCUDAErrorPKc.exit11 # in Loop: Header=BB6_2 Depth=1 movq %r12, %rdi movq %r15, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB6_10 # %bb.11: # %_Z14checkCUDAErrorPKc.exit13 # in Loop: Header=BB6_2 Depth=1 movq (%rsp), %rdi callq hipFree callq hipGetLastError testl %eax, %eax jne .LBB6_12 # %bb.13: # %_Z14checkCUDAErrorPKc.exit15 # in Loop: Header=BB6_2 Depth=1 movq 8(%rsp), %rdi callq hipFree callq hipGetLastError testl %eax, %eax jne .LBB6_12 # %bb.14: # %_Z14checkCUDAErrorPKc.exit17 # in Loop: Header=BB6_2 Depth=1 movq 16(%rsp), %rdi callq hipFree callq hipGetLastError testl %eax, %eax jne .LBB6_12 # %bb.15: # %_Z14checkCUDAErrorPKc.exit19 # in Loop: Header=BB6_2 Depth=1 movq 24(%rsp), %rdi callq hipFree callq hipGetLastError testl %eax, %eax jne .LBB6_12 # %bb.1: # in Loop: Header=BB6_2 Depth=1 addl $400, %ebp # imm = 0x190 addq $100, %rbx addq $104857600, %r15 # imm = 0x6400000 cmpq $1000, %rbx # imm = 0x3E8 jbe .LBB6_2 # %bb.16: xorl %eax, %eax addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB6_12: .cfi_def_cfa_offset 96 movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.4, %esi movl $.L.str.10, %edx jmp .LBB6_4 .LBB6_10: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.4, %esi movl $.L.str.9, %edx jmp .LBB6_4 .LBB6_8: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.4, %esi movl $.L.str.8, %edx jmp .LBB6_4 .LBB6_6: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.4, %esi movl $.L.str.7, %edx jmp .LBB6_4 .LBB6_3: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.4, %esi movl $.L.str.6, %edx .LBB6_4: movq %rbx, %rdi movq %rax, %rcx xorl %eax, %eax callq fprintf movl $-1, %edi callq exit .Lfunc_end6: .size _Z13cuda_mem_testiPPc, .Lfunc_end6-_Z13cuda_mem_testiPPc .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rax .cfi_def_cfa_offset 16 movl $.L.str.11, %edi movl $32, %esi xorl %eax, %eax callq printf callq _Z13cuda_mem_testiPPc xorl %eax, %eax popq %rcx .cfi_def_cfa_offset 8 retq .Lfunc_end7: .size main, .Lfunc_end7-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB8_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB8_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13myFirstKernelPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6reducePfS_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end8: .size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB9_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB9_2: retq .Lfunc_end9: .size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor .cfi_endproc # -- End function .type _Z13myFirstKernelPi,@object # @_Z13myFirstKernelPi .section .rodata,"a",@progbits .globl _Z13myFirstKernelPi .p2align 3, 0x0 _Z13myFirstKernelPi: .quad _Z28__device_stub__myFirstKernelPi .size _Z13myFirstKernelPi, 8 .type _Z6reducePfS_,@object # @_Z6reducePfS_ .globl _Z6reducePfS_ .p2align 3, 0x0 _Z6reducePfS_: .quad _Z21__device_stub__reducePfS_ .size _Z6reducePfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "hipMalloc" .size .L.str, 10 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "kernel execution" .size .L.str.1, 17 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "hipMemcpy" .size .L.str.2, 10 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Cuda error: %s: %s.\n" .size .L.str.4, 21 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Alloc = 4 x %d MB = %d MB\n" .size .L.str.5, 27 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "hipMalloc[0]" .size .L.str.6, 13 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "hipMalloc[1]" .size .L.str.7, 13 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "hipMalloc[2]" .size .L.str.8, 13 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "hipMalloc[3]" .size .L.str.9, 13 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "hipFree" .size .L.str.10, 8 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "C++ test: %d\n" .size .L.str.11, 14 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z13myFirstKernelPi" .size .L__unnamed_1, 20 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z6reducePfS_" .size .L__unnamed_2, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Correct!" .size .Lstr, 9 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__myFirstKernelPi .addrsig_sym _Z21__device_stub__reducePfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13myFirstKernelPi .addrsig_sym _Z6reducePfS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80
.file "tmpxft_000fda58_00000000-6_c2111dc53393346fa956705cc1a9d58e5a469fdc.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "c2111dc53393346fa956705cc1a9d58e5a469fdc.hip" .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2UR UR5, SR_CTAID.Y ; S2R R51, SR_TID.Y ; ULDC.64 UR8, c[0x0][0x0] ; MOV R2, c[0x0][0x1e8] ; ULDC UR7, c[0x0][0x8] ; S2R R4, SR_TID.X ; IADD3 R3, R2, -0x5, RZ ; S2UR UR4, SR_CTAID.X ; S2R R34, SR_TID.Z ; S2UR UR6, SR_CTAID.Z ; UIMAD UR5, UR5, UR9, URZ ; UISETP.LT.AND UP1, UPT, URZ, UR5, UPT ; UIMAD UR4, UR4, UR8, URZ ; USEL UR5, URZ, UR5, !UP1 ; UISETP.LT.AND UP0, UPT, URZ, UR4, UPT ; UIMAD UR6, UR6, UR7, URZ ; IADD3 R51, R51, UR5, RZ ; USEL UR4, URZ, UR4, !UP0 ; UISETP.LT.AND UP1, UPT, URZ, UR6, UPT ; ISETP.GE.AND P0, PT, R51, 0x4, PT ; USEL UR6, URZ, UR6, !UP1 ; IADD3 R4, R4, UR4, RZ ; ISETP.LT.OR P0, PT, R4, 0x4, !P0 ; IADD3 R34, R34, UR6, RZ ; ISETP.LT.OR P0, PT, R34, 0x4, P0 ; ISETP.GT.OR P0, PT, R4, R3, P0 ; ISETP.GT.OR P0, PT, R51, R3, P0 ; ISETP.GT.OR P0, PT, R34, R3, P0 ; @P0 EXIT ; IADD3 R0, R34, 0x1, RZ ; IMAD R49, R2, c[0x0][0x1e4], RZ ; IADD3 R3, RZ, -c[0x0][0x1e4], RZ ; ULDC.64 UR4, c[0x0][0x118] ; IMAD R0, R0, c[0x0][0x1e4], RZ ; LEA R6, R3, R0.reuse, 0x1 ; HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; IADD3 R7, R51.reuse, R0, RZ ; IADD3 R5, R51, R6, RZ ; IMAD R48, R7, c[0x0][0x1e8], R4.reuse ; IMAD R0, R5, c[0x0][0x1e8], R4 ; IADD3 R5, -R49, RZ, RZ ; IMAD.WIDE R20, R48, R3, c[0x0][0x1b8] ; IMAD.WIDE R28, R0, R3, c[0x0][0x1b8] ; IMAD.WIDE R44, R0, R3, c[0x0][0x188] ; IMAD.WIDE R46, R48, R3, c[0x0][0x188] ; IMAD.WIDE R10, R5.reuse, 0x8, R28 ; LDG.E.64.CONSTANT R28, [R28.64] ; IMAD.WIDE R6, R5, 0x8, R44 ; LDG.E.64.CONSTANT R12, [R10.64] ; IMAD.WIDE R22, R49.reuse, 0x8, R20 ; LDG.E.64.CONSTANT R8, [R6.64] ; IMAD.WIDE R14, R49, 0x8, R46 ; LDG.E.64.CONSTANT R42, [R22.64] ; LDG.E.64.CONSTANT R18, [R14.64] ; LDG.E.64.CONSTANT R44, [R44.64] ; IMAD.WIDE R32, R5, 0x8, R10 ; LDG.E.64.CONSTANT R20, [R20.64] ; IMAD.WIDE R30, R5, 0x8, R6 ; LDG.E.64.CONSTANT R46, [R46.64] ; LDG.E.64.CONSTANT R26, [R32.64] ; LDG.E.64.CONSTANT R6, [R30.64] ; IMAD.WIDE R16, R49, 0x8, R22 ; IMAD.WIDE R10, R49, 0x8, R14 ; LDG.E.64.CONSTANT R36, [R16.64] ; LDG.E.64.CONSTANT R40, [R10.64] ; IMAD.WIDE R14, R5, 0x8, R32 ; IMAD.WIDE R22, R5, 0x8, R30 ; LDG.E.64.CONSTANT R14, [R14.64] ; IMAD.WIDE R24, R49.reuse, 0x8, R16 ; LDG.E.64.CONSTANT R22, [R22.64] ; IMAD.WIDE R52, R49, 0x8, R10 ; LDG.E.64.CONSTANT R24, [R24.64] ; IMAD.WIDE R30, R0, R3, c[0x0][0x190] ; LDG.E.64.CONSTANT R32, [R52.64] ; IMAD.WIDE R16, R48.reuse, R3.reuse, c[0x0][0x190] ; LDG.E.64.CONSTANT R38, [R30.64] ; LDG.E.64.CONSTANT R10, [R16.64] ; IMAD.WIDE R52, R48, R3, c[0x0][0x198] ; IMAD.WIDE R30, R5, 0x8, R30 ; IMAD.WIDE R16, R49, 0x8, R16 ; DMUL R8, R12, R8 ; DFMA R8, R42, R18, -R8 ; DMUL R44, R28, R44 ; DMUL R8, R8, c[0x2][0x0] ; DFMA R44, R20, R46, -R44 ; LDG.E.64.CONSTANT R46, [R30.64] ; DFMA R44, R44, c[0x2][0x8], -R8 ; IMAD.WIDE R8, R0, R3, c[0x0][0x198] ; DMUL R6, R26, R6 ; LDG.E.64.CONSTANT R18, [R8.64] ; DFMA R40, R36, R40, -R6 ; LDG.E.64.CONSTANT R6, [R52.64] ; IMAD.WIDE R8, R5, 0x8, R8 ; DMUL R22, R14, R22 ; IMAD.WIDE R52, R49, 0x8, R52 ; DFMA R40, R40, c[0x2][0x10], R44 ; LDG.E.64.CONSTANT R44, [R16.64] ; DFMA R22, R24, R32, -R22 ; LDG.E.64.CONSTANT R32, [R8.64] ; DMUL R38, R28, R38 ; DFMA R38, R20, R10, -R38 ; LDG.E.64.CONSTANT R10, [R52.64] ; IMAD R51, R34, c[0x0][0x1e4], R51 ; DFMA R22, R22, c[0x2][0x18], R40 ; IMAD.WIDE R52, R49, 0x8, R52 ; IMAD.WIDE R30, R5, 0x8, R30 ; DMUL R28, R18, R28 ; DFMA R28, R6, R20, -R28 ; IMAD.WIDE R20, R5, 0x8, R8 ; LDG.E.64.CONSTANT R34, [R20.64] ; IMAD.WIDE R40, R5, 0x8, R20 ; IMAD.WIDE R8, R49, 0x8, R52 ; LDG.E.64.CONSTANT R40, [R40.64] ; LDG.E.64.CONSTANT R20, [R52.64] ; LDG.E.64.CONSTANT R8, [R8.64] ; DADD R6, -R18, R6 ; LDG.E.64.CONSTANT R18, [R30.64] ; DMUL R46, R12, R46 ; DMUL R12, R32, R12 ; DFMA R44, R42, R44, -R46 ; IMAD R46, R51, c[0x0][0x1e8], R4 ; DFMA R42, R10, R42, -R12 ; IMAD.WIDE R12, R46, R3, c[0x0][0x160] ; DADD R32, -R32, R10 ; LDG.E.64 R10, [R12.64] ; DMUL R32, R32, c[0x2][0x0] ; DFMA R32, R6, c[0x2][0x8], -R32 ; DMUL R44, R44, c[0x2][0x0] ; IMAD.WIDE R30, R5, 0x8, R30 ; DFMA R38, R38, c[0x2][0x8], -R44 ; LDG.E.64.CONSTANT R30, [R30.64] ; DMUL R6, R34, R26 ; DADD R34, -R34, R20 ; DFMA R6, R20, R36, -R6 ; DMUL R20, R40, R14 ; DADD R40, -R40, R8 ; DFMA R32, R34, c[0x2][0x10], R32 ; IMAD.WIDE R34, R0, R3.reuse, c[0x0][0x1c0] ; DFMA R20, R8, R24, -R20 ; IMAD.WIDE R8, R48, R3, c[0x0][0x1c0] ; DFMA R32, R40, c[0x2][0x18], R32 ; IMAD.WIDE R44, R5, 0x8, R34 ; DMUL R52, R26, R18 ; LDG.E.64.CONSTANT R34, [R34.64] ; IMAD.WIDE R40, R49, 0x8, R8 ; LDG.E.64.CONSTANT R26, [R44.64] ; LDG.E.64.CONSTANT R18, [R40.64] ; DFMA R10, -R32, c[0x0][0x1d8], R10 ; IMAD.WIDE R32, R46, R3, c[0x0][0x168] ; LDG.E.64.CONSTANT R8, [R8.64] ; STG.E.64 [R12.64], R10 ; LDG.E.64 R10, [R32.64] ; IMAD.WIDE R16, R49, 0x8, R16 ; IMAD.WIDE R40, R49, 0x8, R40 ; IMAD.WIDE R44, R5, 0x8, R44 ; DMUL R14, R14, R30 ; LDG.E.64.CONSTANT R30, [R16.64] ; IMAD.WIDE R12, R49, 0x8, R16 ; LDG.E.64.CONSTANT R12, [R12.64] ; IMAD.WIDE R16, R5, 0x8, R44 ; LDG.E.64.CONSTANT R16, [R16.64] ; DADD R18, -R26, R18 ; IMAD.WIDE R26, R49, 0x8, R40 ; LDG.E.64.CONSTANT R40, [R40.64] ; LDG.E.64.CONSTANT R48, [R44.64] ; LDG.E.64.CONSTANT R26, [R26.64] ; DFMA R44, -R22, c[0x0][0x1d8], R10 ; IMAD.WIDE R10, R46, R3, c[0x0][0x170] ; STG.E.64 [R32.64], R44 ; LDG.E.64 R22, [R10.64] ; DADD R8, -R34, R8 ; DADD R18, R42, R18 ; DADD R8, R28, R8 ; DMUL R18, R18, c[0x2][0x0] ; DFMA R30, R36, R30, -R52 ; IADD3 R5, R51.reuse, -0x1, RZ ; IADD3 R51, R51, 0x1, RZ ; DFMA R12, R24, R12, -R14 ; DFMA R8, R8, c[0x2][0x8], -R18 ; IMAD R14, R5, c[0x0][0x1e8], R4 ; DFMA R38, R30, c[0x2][0x10], R38 ; IMAD R36, R51, c[0x0][0x1e8], R4 ; IADD3 R0, RZ, -c[0x0][0x1e8], RZ ; IMAD.WIDE R30, R36, R3, c[0x0][0x1b0] ; IMAD.WIDE R32, R36, R3, c[0x0][0x1a0] ; IMAD.WIDE R36, R36, R3, c[0x0][0x1c0] ; IMAD.WIDE R34, R2.reuse, 0x8, R30 ; LDG.E.64.CONSTANT R30, [R30.64] ; IMAD.WIDE R28, R2.reuse, 0x8, R32 ; LDG.E.64.CONSTANT R32, [R32.64] ; IMAD.WIDE R44, R2, 0x8, R36 ; LDG.E.64.CONSTANT R36, [R36.64] ; DADD R40, -R48, R40 ; LDG.E.64.CONSTANT R48, [R44.64] ; DADD R40, R6, R40 ; DFMA R6, R12, c[0x2][0x18], R38 ; IMAD.WIDE R12, R14.reuse, R3.reuse, c[0x0][0x1b0] ; DFMA R4, R40, c[0x2][0x10], R8 ; IMAD.WIDE R8, R14, R3, c[0x0][0x1a0] ; LDG.E.64.CONSTANT R40, [R28.64] ; DADD R50, -R16, R26 ; IMAD.WIDE R18, R0, 0x8, R12 ; LDG.E.64.CONSTANT R12, [R12.64] ; IMAD.WIDE R26, R0, 0x8, R8 ; LDG.E.64.CONSTANT R38, [R18.64] ; IMAD.WIDE R14, R14, R3, c[0x0][0x1c0] ; LDG.E.64.CONSTANT R24, [R26.64] ; IMAD.WIDE R16, R0, 0x8, R14 ; DADD R50, R20, R50 ; LDG.E.64.CONSTANT R8, [R8.64] ; LDG.E.64.CONSTANT R20, [R34.64] ; LDG.E.64.CONSTANT R42, [R16.64] ; DFMA R52, -R6, c[0x0][0x1d8], R22 ; IMAD.WIDE R6, R46, R3, c[0x0][0x178] ; LDG.E.64.CONSTANT R14, [R14.64] ; STG.E.64 [R10.64], R52 ; LDG.E.64 R22, [R6.64] ; IMAD.WIDE R18, R0, 0x8, R18 ; IMAD.WIDE R28, R2, 0x8, R28 ; IMAD.WIDE R44, R2.reuse, 0x8, R44 ; DFMA R4, R50, c[0x2][0x18], R4 ; LDG.E.64.CONSTANT R50, [R28.64] ; IMAD.WIDE R34, R2, 0x8, R34 ; IMAD.WIDE R52, R2, 0x8, R28 ; IMAD.WIDE R28, R2, 0x8, R44 ; LDG.E.64.CONSTANT R52, [R52.64] ; LDG.E.64.CONSTANT R44, [R44.64] ; IMAD.WIDE R46, R46, R3, c[0x0][0x180] ; DMUL R24, R38, R24 ; DFMA R40, R20, R40, -R24 ; IMAD.WIDE R24, R0.reuse, 0x8, R16 ; DMUL R42, R38, R42 ; IMAD.WIDE R38, R0, 0x8, R26 ; DFMA R48, R20, R48, -R42 ; IMAD.WIDE R16, R0.reuse, 0x8, R18 ; LDG.E.64.CONSTANT R20, [R18.64] ; IMAD.WIDE R26, R0.reuse, 0x8, R24 ; LDG.E.64.CONSTANT R10, [R38.64] ; LDG.E.64.CONSTANT R24, [R24.64] ; IMAD.WIDE R18, R0, 0x8, R38 ; LDG.E.64.CONSTANT R16, [R16.64] ; IMAD.WIDE R42, R2, 0x8, R34 ; LDG.E.64.CONSTANT R38, [R34.64] ; LDG.E.64.CONSTANT R18, [R18.64] ; LDG.E.64.CONSTANT R26, [R26.64] ; LDG.E.64.CONSTANT R42, [R42.64] ; LDG.E.64.CONSTANT R34, [R28.64] ; DFMA R4, -R4, c[0x0][0x1d8], R22 ; STG.E.64 [R6.64], R4 ; LDG.E.64 R2, [R46.64] ; DMUL R8, R12, R8 ; DMUL R14, R12, R14 ; DFMA R8, R30, R32, -R8 ; DFMA R14, R30, R36, -R14 ; DADD R40, R40, R48 ; DADD R8, R8, R14 ; DMUL R40, R40, c[0x2][0x0] ; DFMA R8, R8, c[0x2][0x8], -R40 ; DMUL R10, R20, R10 ; DMUL R24, R20, R24 ; DFMA R10, R38, R50, -R10 ; DMUL R18, R16, R18 ; DMUL R26, R16, R26 ; DFMA R24, R38, R44, -R24 ; DFMA R18, R42, R52, -R18 ; DFMA R26, R42, R34, -R26 ; DADD R10, R10, R24 ; DADD R18, R18, R26 ; DFMA R8, R10, c[0x2][0x10], R8 ; DFMA R8, R18, c[0x2][0x18], R8 ; DFMA R2, -R8, c[0x0][0x1d0], R2 ; STG.E.64 [R46.64], R2 ; EXIT ; BRA 0x1120; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2UR UR5, SR_CTAID.Y ; S2R R50, SR_TID.Y ; ULDC.64 UR8, c[0x0][0x0] ; MOV R51, c[0x0][0x1e8] ; ULDC UR7, c[0x0][0x8] ; S2R R5, SR_TID.X ; IADD3 R0, R51, -0x5, RZ ; S2UR UR4, SR_CTAID.X ; S2R R53, SR_TID.Z ; S2UR UR6, SR_CTAID.Z ; UIMAD UR5, UR5, UR9, URZ ; UISETP.LT.AND UP1, UPT, URZ, UR5, UPT ; UIMAD UR4, UR4, UR8, URZ ; USEL UR5, URZ, UR5, !UP1 ; UISETP.LT.AND UP0, UPT, URZ, UR4, UPT ; UIMAD UR6, UR6, UR7, URZ ; IADD3 R50, R50, UR5, RZ ; USEL UR4, URZ, UR4, !UP0 ; UISETP.LT.AND UP1, UPT, URZ, UR6, UPT ; ISETP.GE.AND P0, PT, R50, 0x4, PT ; USEL UR6, URZ, UR6, !UP1 ; IADD3 R5, R5, UR4, RZ ; ISETP.LT.OR P0, PT, R5, 0x4, !P0 ; IADD3 R53, R53, UR6, RZ ; ISETP.LT.OR P0, PT, R53, 0x4, P0 ; ISETP.GT.OR P0, PT, R5, R0, P0 ; ISETP.GT.OR P0, PT, R50, R0, P0 ; ISETP.GT.OR P0, PT, R53, R0, P0 ; @P0 EXIT ; IMAD R0, R53, c[0x0][0x1e4], R50 ; HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IADD3 R52, R0.reuse, -0x1, RZ ; IADD3 R4, R0, 0x1, RZ ; IMAD R52, R52, c[0x0][0x1e8], R5.reuse ; IADD3 R2, RZ, -c[0x0][0x1e8], RZ ; IMAD R4, R4, c[0x0][0x1e8], R5 ; IMAD.WIDE R10, R52, R3, c[0x0][0x1b0] ; IMAD.WIDE R12, R52, R3.reuse, c[0x0][0x190] ; LDG.E.64.CONSTANT R6, [R10.64] ; IMAD.WIDE R32, R4.reuse, R3.reuse, c[0x0][0x190] ; LDG.E.64.CONSTANT R22, [R12.64] ; IMAD.WIDE R34, R4, R3.reuse, c[0x0][0x1b0] ; LDG.E.64.CONSTANT R44, [R32.64] ; IMAD.WIDE R48, R2.reuse, 0x8, R10 ; LDG.E.64.CONSTANT R8, [R34.64] ; IMAD.WIDE R20, R2, 0x8, R12 ; LDG.E.64.CONSTANT R10, [R48.64] ; IMAD.WIDE R30, R4, R3.reuse, c[0x0][0x1c0] ; LDG.E.64.CONSTANT R42, [R20.64] ; IMAD.WIDE R28, R52, R3, c[0x0][0x1c0] ; LDG.E.64.CONSTANT R24, [R30.64] ; IMAD.WIDE R16, R51.reuse, 0x8, R32 ; LDG.E.64.CONSTANT R26, [R28.64] ; IMAD.WIDE R46, R51.reuse, 0x8, R34 ; LDG.E.64.CONSTANT R14, [R16.64] ; LDG.E.64.CONSTANT R12, [R46.64] ; IMAD.WIDE R30, R51, 0x8, R30 ; IMAD.WIDE R28, R2, 0x8, R28 ; LDG.E.64.CONSTANT R34, [R30.64] ; IMAD.WIDE R16, R51, 0x8, R16 ; IMAD.WIDE R20, R2, 0x8, R20 ; IMAD.WIDE R48, R2, 0x8, R48 ; LDG.E.64.CONSTANT R40, [R20.64] ; IMAD.WIDE R46, R51, 0x8, R46 ; IMAD.WIDE R36, R51, 0x8, R16 ; IMAD.WIDE R32, R2, 0x8, R20 ; LDG.E.64.CONSTANT R36, [R36.64] ; LDG.E.64.CONSTANT R32, [R32.64] ; IMAD.WIDE R20, R51, 0x8, R46 ; LDG.E.64.CONSTANT R20, [R20.64] ; DMUL R18, R22, R6 ; DFMA R18, R44, R8, -R18 ; DADD R44, -R22, R44 ; LDG.E.64.CONSTANT R22, [R28.64] ; DMUL R38, R42, R10 ; DADD R26, -R26, R24 ; LDG.E.64.CONSTANT R24, [R16.64] ; DADD R42, -R42, R14 ; DFMA R38, R14, R12, -R38 ; LDG.E.64.CONSTANT R14, [R48.64] ; LDG.E.64.CONSTANT R16, [R46.64] ; DADD R26, R18, R26 ; IMAD.WIDE R18, R2, 0x8, R48 ; LDG.E.64.CONSTANT R18, [R18.64] ; DMUL R42, R42, c[0x2][0x0] ; DFMA R42, R44, c[0x2][0x8], -R42 ; IMAD.WIDE R44, R4, R3, c[0x0][0x188] ; IMAD.WIDE R28, R2, 0x8, R28 ; IMAD.WIDE R30, R51, 0x8, R30 ; DADD R22, -R22, R34 ; DADD R22, R38, R22 ; DADD R34, -R40, R24 ; DMUL R40, R40, R14 ; DMUL R22, R22, c[0x2][0x0] ; DFMA R24, R24, R16, -R40 ; IMAD.WIDE R40, R52, R3, c[0x0][0x188] ; DFMA R22, R26, c[0x2][0x8], -R22 ; DFMA R26, R34, c[0x2][0x10], R42 ; LDG.E.64.CONSTANT R34, [R40.64] ; DADD R38, -R32.reuse, R36 ; LDG.E.64.CONSTANT R42, [R44.64] ; DMUL R32, R32, R18 ; DFMA R26, R38, c[0x2][0x18], R26 ; LDG.E.64.CONSTANT R38, [R28.64] ; DFMA R32, R36, R20, -R32 ; LDG.E.64.CONSTANT R36, [R30.64] ; IMAD.WIDE R40, R2, 0x8, R40 ; LDG.E.64.CONSTANT R48, [R40.64] ; IMAD.WIDE R40, R2, 0x8, R40 ; DMUL R34, R6, R34 ; DFMA R34, R8, R42, -R34 ; IMAD.WIDE R42, R51, 0x8, R44 ; LDG.E.64.CONSTANT R44, [R40.64] ; DADD R36, -R38, R36 ; LDG.E.64.CONSTANT R38, [R42.64] ; IMAD.WIDE R42, R51, 0x8, R42 ; LDG.E.64.CONSTANT R46, [R42.64] ; DMUL R48, R10, R48 ; IMAD R0, R0, c[0x0][0x1e8], R5 ; DMUL R44, R14, R44 ; DFMA R38, R12, R38, -R48 ; DMUL R38, R38, c[0x2][0x0] ; DFMA R46, R16, R46, -R44 ; IMAD.WIDE R44, R0, R3, c[0x0][0x160] ; DFMA R34, R34, c[0x2][0x8], -R38 ; LDG.E.64 R38, [R44.64] ; IMAD.WIDE R40, R2, 0x8, R40 ; IMAD.WIDE R42, R51, 0x8, R42 ; LDG.E.64.CONSTANT R40, [R40.64] ; LDG.E.64.CONSTANT R42, [R42.64] ; DFMA R34, R46, c[0x2][0x10], R34 ; IMAD.WIDE R46, R0, R3, c[0x0][0x168] ; IMAD.WIDE R28, R2, 0x8, R28 ; IMAD.WIDE R30, R51, 0x8, R30 ; LDG.E.64.CONSTANT R28, [R28.64] ; LDG.E.64.CONSTANT R30, [R30.64] ; DFMA R26, -R26, c[0x0][0x1d0], R38 ; STG.E.64 [R44.64], R26 ; LDG.E.64 R38, [R46.64] ; DMUL R40, R18, R40 ; DFMA R40, R20, R42, -R40 ; DFMA R34, R40, c[0x2][0x18], R34 ; IMAD.WIDE R42, R52, R3, c[0x0][0x198] ; IMAD.WIDE R26, R0, R3, c[0x0][0x170] ; DADD R44, R24, R36 ; IMAD.WIDE R40, R2, 0x8, R42 ; IMAD.WIDE R36, R4, R3, c[0x0][0x198] ; LDG.E.64.CONSTANT R24, [R40.64] ; DFMA R22, R44, c[0x2][0x10], R22 ; IMAD.WIDE R44, R51, 0x8, R36 ; LDG.E.64.CONSTANT R36, [R36.64] ; DADD R30, -R28, R30 ; LDG.E.64.CONSTANT R28, [R44.64] ; DFMA R48, -R34, c[0x0][0x1d0], R38 ; LDG.E.64.CONSTANT R34, [R42.64] ; STG.E.64 [R46.64], R48 ; LDG.E.64 R38, [R26.64] ; DADD R32, R32, R30 ; IADD3 R53, R53, 0x1, RZ ; IMAD.WIDE R42, R51, 0x8, R44 ; IMAD.WIDE R48, R2, 0x8, R40 ; DFMA R40, R32, c[0x2][0x18], R22 ; LDG.E.64.CONSTANT R32, [R42.64] ; IMAD R23, R53, c[0x0][0x1e4], RZ ; IMAD.WIDE R46, R2, 0x8, R48 ; LDG.E.64.CONSTANT R30, [R48.64] ; IADD3 R2, RZ, -c[0x0][0x1e4], RZ ; IMAD.WIDE R52, R51, 0x8, R42 ; LEA R45, R2, R23, 0x1 ; IADD3 R2, R50, R45, RZ ; IMAD R51, R51, c[0x0][0x1e4], RZ ; DMUL R44, R10, R24 ; IMAD R4, R2, c[0x0][0x1e8], R5 ; IADD3 R2, -R51, RZ, RZ ; IMAD.WIDE R42, R4, R3, c[0x0][0x1b8] ; IMAD.WIDE R10, R4, R3, c[0x0][0x1a0] ; IMAD.WIDE R24, R0, R3.reuse, c[0x0][0x178] ; DMUL R34, R6, R34 ; LDG.E.64.CONSTANT R6, [R46.64] ; DFMA R38, -R40, c[0x0][0x1d0], R38 ; LDG.E.64.CONSTANT R40, [R52.64] ; IMAD.WIDE R46, R4, R3, c[0x0][0x1c0] ; DFMA R36, R8, R36, -R34 ; IMAD.WIDE R8, R2.reuse, 0x8, R42 ; STG.E.64 [R26.64], R38 ; IMAD.WIDE R34, R2, 0x8, R10 ; LDG.E.64 R48, [R24.64] ; LDG.E.64.CONSTANT R52, [R8.64] ; DMUL R30, R14, R30 ; IADD3 R50, R50, R23, RZ ; LDG.E.64.CONSTANT R42, [R42.64] ; DFMA R26, R12, R28, -R44 ; IMAD.WIDE R12, R2, 0x8, R46 ; LDG.E.64.CONSTANT R28, [R34.64] ; LDG.E.64.CONSTANT R44, [R12.64] ; DMUL R26, R26, c[0x2][0x0] ; LDG.E.64.CONSTANT R10, [R10.64] ; DFMA R30, R16, R32, -R30 ; IMAD R50, R50, c[0x0][0x1e8], R5 ; IMAD.WIDE R8, R2, 0x8, R8 ; DFMA R26, R36, c[0x2][0x8], -R26 ; LDG.E.64.CONSTANT R46, [R46.64] ; DFMA R26, R30, c[0x2][0x10], R26 ; IMAD.WIDE R4, R50, R3, c[0x0][0x1b8] ; IMAD.WIDE R14, R50, R3, c[0x0][0x1c0] ; IMAD.WIDE R36, R2, 0x8, R12 ; IMAD.WIDE R38, R2, 0x8, R36 ; LDG.E.64.CONSTANT R36, [R36.64] ; LDG.E.64.CONSTANT R38, [R38.64] ; DMUL R6, R18, R6 ; DFMA R6, R20, R40, -R6 ; DFMA R26, R6, c[0x2][0x18], R26 ; IMAD.WIDE R6, R50, R3, c[0x0][0x1a0] ; IMAD.WIDE R20, R51.reuse, 0x8, R4 ; DFMA R48, -R26, c[0x0][0x1d0], R48 ; LDG.E.64.CONSTANT R4, [R4.64] ; IMAD.WIDE R16, R51.reuse, 0x8, R6 ; LDG.E.64.CONSTANT R22, [R20.64] ; IMAD.WIDE R18, R51, 0x8, R14 ; LDG.E.64.CONSTANT R26, [R16.64] ; DMUL R30, R52, R28 ; IMAD.WIDE R40, R2, 0x8, R34 ; LDG.E.64.CONSTANT R28, [R18.64] ; DMUL R44, R52, R44 ; IMAD.WIDE R32, R51.reuse, 0x8, R16 ; STG.E.64 [R24.64], R48 ; IMAD.WIDE R52, R51.reuse, 0x8, R20 ; LDG.E.64.CONSTANT R6, [R6.64] ; IMAD.WIDE R20, R51, 0x8, R18 ; LDG.E.64.CONSTANT R14, [R14.64] ; IMAD.WIDE R34, R2.reuse, 0x8, R8 ; LDG.E.64.CONSTANT R12, [R52.64] ; IMAD.WIDE R18, R2, 0x8, R40 ; LDG.E.64.CONSTANT R24, [R8.64] ; IMAD.WIDE R16, R51, 0x8, R52 ; LDG.E.64.CONSTANT R34, [R34.64] ; IMAD.WIDE R48, R51.reuse, 0x8, R32 ; LDG.E.64.CONSTANT R18, [R18.64] ; LDG.E.64.CONSTANT R8, [R40.64] ; IMAD.WIDE R50, R51, 0x8, R20 ; LDG.E.64.CONSTANT R20, [R20.64] ; LDG.E.64.CONSTANT R16, [R16.64] ; LDG.E.64.CONSTANT R40, [R32.64] ; LDG.E.64.CONSTANT R48, [R48.64] ; LDG.E.64.CONSTANT R50, [R50.64] ; IMAD.WIDE R2, R0, R3, c[0x0][0x180] ; LDG.E.64 R32, [R2.64] ; DMUL R10, R42, R10 ; DMUL R46, R42, R46 ; DFMA R26, R22, R26, -R30 ; DFMA R28, R22, R28, -R44 ; DADD R26, R26, R28 ; DFMA R6, R4, R6, -R10 ; DFMA R14, R4, R14, -R46 ; DMUL R36, R24, R36 ; DADD R6, R6, R14 ; DMUL R8, R24, R8 ; DMUL R26, R26, c[0x2][0x0] ; DMUL R18, R34, R18 ; DMUL R38, R34, R38 ; DFMA R8, R12, R40, -R8 ; DFMA R20, R12, R20, -R36 ; DFMA R6, R6, c[0x2][0x8], -R26 ; DFMA R18, R16, R48, -R18 ; DFMA R38, R16, R50, -R38 ; DADD R8, R8, R20 ; DADD R18, R18, R38 ; DFMA R6, R8, c[0x2][0x10], R6 ; DFMA R6, R18, c[0x2][0x18], R6 ; DFMA R6, -R6, c[0x0][0x1d8], R32 ; STG.E.64 [R2.64], R6 ; EXIT ; BRA 0x1120; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2UR UR5, SR_CTAID.Y ; S2R R2, SR_TID.Y ; ULDC.64 UR8, c[0x0][0x0] ; ULDC UR7, c[0x0][0x8] ; S2R R0, SR_TID.X ; S2UR UR4, SR_CTAID.X ; S2R R3, SR_TID.Z ; S2UR UR6, SR_CTAID.Z ; UIMAD UR5, UR5, UR9, URZ ; UISETP.LT.AND UP1, UPT, URZ, UR5, UPT ; UIMAD UR4, UR4, UR8, URZ ; USEL UR5, URZ, UR5, !UP1 ; UISETP.LT.AND UP0, UPT, URZ, UR4, UPT ; UIMAD UR6, UR6, UR7, URZ ; IADD3 R2, R2, UR5, RZ ; USEL UR4, URZ, UR4, !UP0 ; UISETP.LT.AND UP1, UPT, URZ, UR6, UPT ; ISETP.GE.AND P0, PT, R2, 0x4, PT ; USEL UR6, URZ, UR6, !UP1 ; IADD3 R0, R0, UR4, RZ ; ULDC UR4, c[0x0][0x1e8] ; UIADD3 UR4, UR4, -0x5, URZ ; ISETP.LT.OR P0, PT, R0, 0x4, !P0 ; IADD3 R3, R3, UR6, RZ ; ISETP.LT.OR P0, PT, R3, 0x4, P0 ; ISETP.GT.OR P0, PT, R0, UR4, P0 ; ISETP.GT.OR P0, PT, R2, UR4, P0 ; ISETP.GT.OR P0, PT, R3, UR4, P0 ; @P0 EXIT ; HFMA2.MMA R43, -RZ, RZ, 0, 4.76837158203125e-07 ; IMAD R3, R3, c[0x0][0x1e4], R2 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD R0, R3, c[0x0][0x1e8], R0 ; IMAD.WIDE R28, R0, R43, c[0x0][0x188] ; LDG.E.64.CONSTANT R6, [R28.64+-0x10] ; IMAD.WIDE R32, R0, R43, c[0x0][0x1a8] ; LDG.E.64.CONSTANT R10, [R28.64+0x10] ; IMAD.WIDE R12, R0, R43, c[0x0][0x1c0] ; LDG.E.64.CONSTANT R4, [R28.64+-0x8] ; IMAD.WIDE R18, R0, R43, c[0x0][0x190] ; LDG.E.64.CONSTANT R40, [R28.64+0x8] ; IMAD.WIDE R22, R0, R43, c[0x0][0x198] ; LDG.E.64.CONSTANT R8, [R32.64+-0x8] ; IMAD.WIDE R24, R0, R43, c[0x0][0x1a0] ; LDG.E.64.CONSTANT R50, [R32.64+0x8] ; LDG.E.64.CONSTANT R2, [R12.64+-0x8] ; LDG.E.64.CONSTANT R30, [R18.64+-0x8] ; LDG.E.64.CONSTANT R34, [R22.64+-0x8] ; LDG.E.64.CONSTANT R16, [R24.64+-0x8] ; LDG.E.64.CONSTANT R20, [R12.64+0x8] ; LDG.E.64.CONSTANT R46, [R18.64+0x8] ; LDG.E.64.CONSTANT R36, [R22.64+0x8] ; LDG.E.64.CONSTANT R14, [R24.64+0x8] ; LDG.E.64.CONSTANT R26, [R32.64+-0x10] ; LDG.E.64.CONSTANT R38, [R32.64+0x10] ; DADD R44, -R6, R10 ; DMUL R48, R44, c[0x2][0x0] ; DADD R44, -R4, R40 ; DMUL R4, R4, R8 ; DFMA R4, R40, R50, -R4 ; DMUL R40, R8, R2 ; DMUL R30, R8, R30 ; DMUL R34, R8, R34 ; DMUL R16, R8, R16 ; LDG.E.64.CONSTANT R8, [R22.64+-0x10] ; DADD R2, -R2, R20 ; DFMA R20, R50.reuse, R20, -R40 ; LDG.E.64.CONSTANT R40, [R18.64+-0x10] ; DFMA R46, R50.reuse, R46, -R30 ; LDG.E.64.CONSTANT R30, [R24.64+-0x10] ; DFMA R36, R50.reuse, R36, -R34 ; LDG.E.64.CONSTANT R34, [R22.64+0x10] ; DFMA R50, R50, R14, -R16 ; LDG.E.64.CONSTANT R16, [R24.64+0x10] ; DMUL R14, R6, R26 ; LDG.E.64.CONSTANT R6, [R12.64+-0x10] ; DFMA R10, R10, R38, -R14 ; LDG.E.64.CONSTANT R14, [R12.64+0x10] ; DFMA R44, R44, c[0x2][0x8], -R48 ; LDG.E.64.CONSTANT R48, [R18.64+0x10] ; DADD R4, R4, R2 ; LDG.E.64.CONSTANT R2, [R18.64+-0x18] ; DMUL R8, R26, R8 ; DMUL R40, R26, R40 ; DMUL R30, R26, R30 ; DMUL R26, R26, R6 ; DFMA R26, R38, R14, -R26 ; DADD R14, -R6, R14 ; LDG.E.64.CONSTANT R6, [R32.64+-0x18] ; DFMA R48, R38, R48, -R40 ; LDG.E.64.CONSTANT R40, [R28.64+-0x18] ; DADD R14, R10, R14 ; LDG.E.64.CONSTANT R10, [R12.64+0x18] ; DFMA R8, R38, R34, -R8 ; LDG.E.64.CONSTANT R34, [R28.64+0x18] ; DMUL R14, R14, c[0x2][0x0] ; DFMA R38, R38, R16, -R30 ; LDG.E.64.CONSTANT R30, [R32.64+0x18] ; LDG.E.64.CONSTANT R16, [R12.64+-0x18] ; DFMA R4, R4, c[0x2][0x8], -R14 ; LDG.E.64.CONSTANT R14, [R18.64+0x18] ; DMUL R48, R48, c[0x2][0x0] ; DADD R26, R38, R26 ; LDG.E.64.CONSTANT R38, [R28.64+-0x20] ; DFMA R46, R46, c[0x2][0x8], -R48 ; DMUL R8, R8, c[0x2][0x0] ; DADD R20, R50, R20 ; DMUL R26, R26, c[0x2][0x0] ; DFMA R36, R36, c[0x2][0x8], -R8 ; DMUL R50, R6, R2 ; LDG.E.64.CONSTANT R2, [R32.64+-0x20] ; DADD R48, -R40, R34 ; DMUL R40, R40, R6 ; DFMA R40, R34, R30, -R40 ; DADD R8, -R16, R10 ; DFMA R44, R48, c[0x2][0x10], R44 ; DMUL R48, R6, R16 ; LDG.E.64.CONSTANT R16, [R28.64+0x20] ; DADD R40, R40, R8 ; LDG.E.64.CONSTANT R8, [R22.64+0x18] ; DFMA R52, R30, R14, -R50 ; LDG.E.64.CONSTANT R50, [R18.64+0x20] ; DFMA R34, R20, c[0x2][0x8], -R26 ; LDG.E.64.CONSTANT R26, [R22.64+-0x18] ; LDG.E.64.CONSTANT R20, [R24.64+-0x18] ; DFMA R10, R30, R10, -R48 ; LDG.E.64.CONSTANT R48, [R18.64+-0x20] ; DFMA R4, R40, c[0x2][0x10], R4 ; LDG.E.64.CONSTANT R28, [R22.64+-0x20] ; LDG.E.64.CONSTANT R40, [R24.64+0x18] ; DFMA R18, R52, c[0x2][0x10], R46 ; LDG.E.64.CONSTANT R46, [R12.64+-0x20] ; LDG.E.64.CONSTANT R52, [R24.64+-0x20] ; LDG.E.64.CONSTANT R14, [R32.64+0x20] ; LDG.E.64.CONSTANT R12, [R12.64+0x20] ; LDG.E.64.CONSTANT R22, [R22.64+0x20] ; LDG.E.64.CONSTANT R24, [R24.64+0x20] ; DMUL R26, R6, R26 ; DMUL R20, R6, R20 ; DADD R6, -R38, R16 ; DMUL R38, R38, R2 ; DFMA R8, R30, R8, -R26 ; DFMA R44, R6, c[0x2][0x18], R44 ; DMUL R28, R2, R28 ; DFMA R20, R30, R40, -R20 ; DMUL R6, R2, R46 ; DMUL R52, R2, R52 ; DFMA R38, R16, R14, -R38 ; DADD R46, -R46, R12 ; DFMA R8, R8, c[0x2][0x10], R36 ; DMUL R48, R2, R48 ; DFMA R22, R14, R22, -R28 ; DADD R10, R20, R10 ; DFMA R6, R14, R12, -R6 ; DFMA R24, R14, R24, -R52 ; DADD R38, R38, R46 ; DFMA R48, R14, R50, -R48 ; DFMA R8, R22, c[0x2][0x18], R8 ; DFMA R34, R10, c[0x2][0x10], R34 ; DADD R6, R24, R6 ; DFMA R4, R38, c[0x2][0x18], R4 ; DFMA R18, R48, c[0x2][0x18], R18 ; DMUL R8, R8, c[0x0][0x1c8] ; DFMA R6, R6, c[0x2][0x18], R34 ; DMUL R44, R44, c[0x0][0x1c8] ; DMUL R4, R4, c[0x0][0x1c8] ; DMUL R18, R18, c[0x0][0x1c8] ; DADD R14, -RZ, -R8 ; DMUL R8, R6, c[0x0][0x1c8] ; IMAD.WIDE R2, R0, R43, c[0x0][0x160] ; DADD R44, -RZ, -R44 ; IMAD.WIDE R6, R0, R43, c[0x0][0x170] ; DADD R12, -RZ, -R4 ; IMAD.WIDE R4, R0.reuse, R43.reuse, c[0x0][0x168] ; DADD R18, -RZ, -R18 ; STG.E.64 [R2.64], R44 ; IMAD.WIDE R10, R0.reuse, R43.reuse, c[0x0][0x180] ; DADD R16, -RZ, -R8 ; IMAD.WIDE R8, R0, R43, c[0x0][0x178] ; STG.E.64 [R4.64], R12 ; STG.E.64 [R6.64], R18 ; STG.E.64 [R8.64], R14 ; STG.E.64 [R10.64], R16 ; EXIT ; BRA 0xb90; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000701c4_00000000-6_252990da4bcd9cf61d055f084f0bb3d490c0eea4.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2162: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2162: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Error : %s, %s\n" .text .globl _Z11check_errorPKc .type _Z11check_errorPKc, @function _Z11check_errorPKc: .LFB2156: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx call cudaGetLastError@PLT testl %eax, %eax jne .L6 .L3: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L6: .cfi_restore_state movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx movq %rbx, %rdx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L3 .cfi_endproc .LFE2156: .size _Z11check_errorPKc, .-_Z11check_errorPKc .globl _Z66__device_stub__Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .type _Z66__device_stub__Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, @function _Z66__device_stub__Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: .LFB2184: .cfi_startproc endbr64 subq $376, %rsp .cfi_def_cfa_offset 384 movsd %xmm0, 24(%rsp) movsd %xmm1, 16(%rsp) movsd %xmm2, 8(%rsp) movq %fs:40, %rax movq %rax, 360(%rsp) xorl %eax, %eax movq %rdi, 40(%rsp) leaq 40(%rsp), %rax movq %rax, 208(%rsp) movq %rsi, 48(%rsp) leaq 48(%rsp), %rax movq %rax, 216(%rsp) movq %rdx, 56(%rsp) leaq 56(%rsp), %rax movq %rax, 224(%rsp) movq %rcx, 64(%rsp) leaq 64(%rsp), %rax movq %rax, 232(%rsp) movq %r8, 72(%rsp) leaq 72(%rsp), %rax movq %rax, 240(%rsp) movq %r9, 80(%rsp) leaq 80(%rsp), %rax movq %rax, 248(%rsp) movq 384(%rsp), %rax movq %rax, 88(%rsp) leaq 88(%rsp), %rax movq %rax, 256(%rsp) movq 392(%rsp), %rax movq %rax, 96(%rsp) leaq 96(%rsp), %rax movq %rax, 264(%rsp) movq 400(%rsp), %rax movq %rax, 104(%rsp) leaq 104(%rsp), %rax movq %rax, 272(%rsp) movq 408(%rsp), %rax movq %rax, 112(%rsp) leaq 112(%rsp), %rax movq %rax, 280(%rsp) movq 416(%rsp), %rax movq %rax, 120(%rsp) leaq 120(%rsp), %rax movq %rax, 288(%rsp) movq 424(%rsp), %rax movq %rax, 128(%rsp) leaq 128(%rsp), %rax movq %rax, 296(%rsp) movq 432(%rsp), %rax movq %rax, 136(%rsp) leaq 136(%rsp), %rax movq %rax, 304(%rsp) leaq 24(%rsp), %rax movq %rax, 312(%rsp) leaq 16(%rsp), %rax movq %rax, 320(%rsp) leaq 8(%rsp), %rax movq %rax, 328(%rsp) leaq 440(%rsp), %rax movq %rax, 336(%rsp) leaq 448(%rsp), %rax movq %rax, 344(%rsp) leaq 456(%rsp), %rax movq %rax, 352(%rsp) movl $1, 160(%rsp) movl $1, 164(%rsp) movl $1, 168(%rsp) movl $1, 172(%rsp) movl $1, 176(%rsp) movl $1, 180(%rsp) leaq 152(%rsp), %rcx leaq 144(%rsp), %rdx leaq 172(%rsp), %rsi leaq 160(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 360(%rsp), %rax subq %fs:40, %rax jne .L12 addq $376, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 152(%rsp) .cfi_def_cfa_offset 392 pushq 152(%rsp) .cfi_def_cfa_offset 400 leaq 224(%rsp), %r9 movq 188(%rsp), %rcx movl 196(%rsp), %r8d movq 176(%rsp), %rsi movl 184(%rsp), %edx leaq _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 384 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE2184: .size _Z66__device_stub__Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, .-_Z66__device_stub__Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .globl _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .type _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, @function _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: .LFB2185: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 pushq 88(%rsp) .cfi_def_cfa_offset 48 pushq 88(%rsp) .cfi_def_cfa_offset 56 pushq 88(%rsp) .cfi_def_cfa_offset 64 pushq 88(%rsp) .cfi_def_cfa_offset 72 pushq 88(%rsp) .cfi_def_cfa_offset 80 pushq 88(%rsp) .cfi_def_cfa_offset 88 pushq 88(%rsp) .cfi_def_cfa_offset 96 call _Z66__device_stub__Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii addq $88, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2185: .size _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, .-_Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .globl _Z66__device_stub__Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .type _Z66__device_stub__Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, @function _Z66__device_stub__Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: .LFB2186: .cfi_startproc endbr64 subq $376, %rsp .cfi_def_cfa_offset 384 movsd %xmm0, 24(%rsp) movsd %xmm1, 16(%rsp) movsd %xmm2, 8(%rsp) movq %fs:40, %rax movq %rax, 360(%rsp) xorl %eax, %eax movq %rdi, 40(%rsp) leaq 40(%rsp), %rax movq %rax, 208(%rsp) movq %rsi, 48(%rsp) leaq 48(%rsp), %rax movq %rax, 216(%rsp) movq %rdx, 56(%rsp) leaq 56(%rsp), %rax movq %rax, 224(%rsp) movq %rcx, 64(%rsp) leaq 64(%rsp), %rax movq %rax, 232(%rsp) movq %r8, 72(%rsp) leaq 72(%rsp), %rax movq %rax, 240(%rsp) movq %r9, 80(%rsp) leaq 80(%rsp), %rax movq %rax, 248(%rsp) movq 384(%rsp), %rax movq %rax, 88(%rsp) leaq 88(%rsp), %rax movq %rax, 256(%rsp) movq 392(%rsp), %rax movq %rax, 96(%rsp) leaq 96(%rsp), %rax movq %rax, 264(%rsp) movq 400(%rsp), %rax movq %rax, 104(%rsp) leaq 104(%rsp), %rax movq %rax, 272(%rsp) movq 408(%rsp), %rax movq %rax, 112(%rsp) leaq 112(%rsp), %rax movq %rax, 280(%rsp) movq 416(%rsp), %rax movq %rax, 120(%rsp) leaq 120(%rsp), %rax movq %rax, 288(%rsp) movq 424(%rsp), %rax movq %rax, 128(%rsp) leaq 128(%rsp), %rax movq %rax, 296(%rsp) movq 432(%rsp), %rax movq %rax, 136(%rsp) leaq 136(%rsp), %rax movq %rax, 304(%rsp) leaq 24(%rsp), %rax movq %rax, 312(%rsp) leaq 16(%rsp), %rax movq %rax, 320(%rsp) leaq 8(%rsp), %rax movq %rax, 328(%rsp) leaq 440(%rsp), %rax movq %rax, 336(%rsp) leaq 448(%rsp), %rax movq %rax, 344(%rsp) leaq 456(%rsp), %rax movq %rax, 352(%rsp) movl $1, 160(%rsp) movl $1, 164(%rsp) movl $1, 168(%rsp) movl $1, 172(%rsp) movl $1, 176(%rsp) movl $1, 180(%rsp) leaq 152(%rsp), %rcx leaq 144(%rsp), %rdx leaq 172(%rsp), %rsi leaq 160(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L19 .L15: movq 360(%rsp), %rax subq %fs:40, %rax jne .L20 addq $376, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state pushq 152(%rsp) .cfi_def_cfa_offset 392 pushq 152(%rsp) .cfi_def_cfa_offset 400 leaq 224(%rsp), %r9 movq 188(%rsp), %rcx movl 196(%rsp), %r8d movq 176(%rsp), %rsi movl 184(%rsp), %edx leaq _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 384 jmp .L15 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE2186: .size _Z66__device_stub__Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, .-_Z66__device_stub__Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .globl _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .type _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, @function _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: .LFB2187: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 pushq 88(%rsp) .cfi_def_cfa_offset 48 pushq 88(%rsp) .cfi_def_cfa_offset 56 pushq 88(%rsp) .cfi_def_cfa_offset 64 pushq 88(%rsp) .cfi_def_cfa_offset 72 pushq 88(%rsp) .cfi_def_cfa_offset 80 pushq 88(%rsp) .cfi_def_cfa_offset 88 pushq 88(%rsp) .cfi_def_cfa_offset 96 call _Z66__device_stub__Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii addq $88, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2187: .size _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, .-_Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .globl _Z66__device_stub__Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .type _Z66__device_stub__Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, @function _Z66__device_stub__Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: .LFB2188: .cfi_startproc endbr64 subq $376, %rsp .cfi_def_cfa_offset 384 movsd %xmm0, 24(%rsp) movsd %xmm1, 16(%rsp) movsd %xmm2, 8(%rsp) movq %fs:40, %rax movq %rax, 360(%rsp) xorl %eax, %eax movq %rdi, 40(%rsp) leaq 40(%rsp), %rax movq %rax, 208(%rsp) movq %rsi, 48(%rsp) leaq 48(%rsp), %rax movq %rax, 216(%rsp) movq %rdx, 56(%rsp) leaq 56(%rsp), %rax movq %rax, 224(%rsp) movq %rcx, 64(%rsp) leaq 64(%rsp), %rax movq %rax, 232(%rsp) movq %r8, 72(%rsp) leaq 72(%rsp), %rax movq %rax, 240(%rsp) movq %r9, 80(%rsp) leaq 80(%rsp), %rax movq %rax, 248(%rsp) movq 384(%rsp), %rax movq %rax, 88(%rsp) leaq 88(%rsp), %rax movq %rax, 256(%rsp) movq 392(%rsp), %rax movq %rax, 96(%rsp) leaq 96(%rsp), %rax movq %rax, 264(%rsp) movq 400(%rsp), %rax movq %rax, 104(%rsp) leaq 104(%rsp), %rax movq %rax, 272(%rsp) movq 408(%rsp), %rax movq %rax, 112(%rsp) leaq 112(%rsp), %rax movq %rax, 280(%rsp) movq 416(%rsp), %rax movq %rax, 120(%rsp) leaq 120(%rsp), %rax movq %rax, 288(%rsp) movq 424(%rsp), %rax movq %rax, 128(%rsp) leaq 128(%rsp), %rax movq %rax, 296(%rsp) movq 432(%rsp), %rax movq %rax, 136(%rsp) leaq 136(%rsp), %rax movq %rax, 304(%rsp) leaq 24(%rsp), %rax movq %rax, 312(%rsp) leaq 16(%rsp), %rax movq %rax, 320(%rsp) leaq 8(%rsp), %rax movq %rax, 328(%rsp) leaq 440(%rsp), %rax movq %rax, 336(%rsp) leaq 448(%rsp), %rax movq %rax, 344(%rsp) leaq 456(%rsp), %rax movq %rax, 352(%rsp) movl $1, 160(%rsp) movl $1, 164(%rsp) movl $1, 168(%rsp) movl $1, 172(%rsp) movl $1, 176(%rsp) movl $1, 180(%rsp) leaq 152(%rsp), %rcx leaq 144(%rsp), %rdx leaq 172(%rsp), %rsi leaq 160(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L27 .L23: movq 360(%rsp), %rax subq %fs:40, %rax jne .L28 addq $376, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L27: .cfi_restore_state pushq 152(%rsp) .cfi_def_cfa_offset 392 pushq 152(%rsp) .cfi_def_cfa_offset 400 leaq 224(%rsp), %r9 movq 188(%rsp), %rcx movl 196(%rsp), %r8d movq 176(%rsp), %rsi movl 184(%rsp), %edx leaq _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 384 jmp .L23 .L28: call __stack_chk_fail@PLT .cfi_endproc .LFE2188: .size _Z66__device_stub__Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, .-_Z66__device_stub__Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .globl _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .type _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, @function _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: .LFB2189: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 pushq 88(%rsp) .cfi_def_cfa_offset 48 pushq 88(%rsp) .cfi_def_cfa_offset 56 pushq 88(%rsp) .cfi_def_cfa_offset 64 pushq 88(%rsp) .cfi_def_cfa_offset 72 pushq 88(%rsp) .cfi_def_cfa_offset 80 pushq 88(%rsp) .cfi_def_cfa_offset 88 pushq 88(%rsp) .cfi_def_cfa_offset 96 call _Z66__device_stub__Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii addq $88, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2189: .size _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, .-_Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "Failed to allocate device memory for flux_0\n" .align 8 .LC2: .string "Failed to allocate device memory for flux_1\n" .align 8 .LC3: .string "Failed to allocate device memory for flux_2\n" .align 8 .LC4: .string "Failed to allocate device memory for flux_3\n" .align 8 .LC5: .string "Failed to allocate device memory for flux_4\n" .align 8 .LC6: .string "Failed to allocate device memory for cons_1\n" .align 8 .LC7: .string "Failed to allocate device memory for cons_2\n" .align 8 .LC8: .string "Failed to allocate device memory for cons_3\n" .align 8 .LC9: .string "Failed to allocate device memory for cons_4\n" .align 8 .LC10: .string "Failed to allocate device memory for q_1\n" .align 8 .LC11: .string "Failed to allocate device memory for q_2\n" .align 8 .LC12: .string "Failed to allocate device memory for q_3\n" .align 8 .LC13: .string "Failed to allocate device memory for q_4\n" .align 8 .LC15: .string "Average kernel execution time (k1): %f (ms)\n" .align 8 .LC16: .string "Average kernel execution time (k2): %f (ms)\n" .align 8 .LC17: .string "Average kernel execution time (k3): %f (ms)\n" .text .globl offload .type offload, @function offload: .LFB2157: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $248, %rsp .cfi_def_cfa_offset 304 movq %rdi, 8(%rsp) movq %rsi, 16(%rsp) movq %rdx, 24(%rsp) movq %rcx, 32(%rsp) movq %r8, 40(%rsp) movq %r9, 72(%rsp) movq 304(%rsp), %rbp movq 312(%rsp), %r12 movq 320(%rsp), %r13 movq 328(%rsp), %r14 movq 336(%rsp), %r15 movq 344(%rsp), %rax movq %rax, 80(%rsp) movq 352(%rsp), %rbx movq %rbx, 88(%rsp) movsd %xmm0, 48(%rsp) movsd %xmm1, 56(%rsp) movsd %xmm2, 64(%rsp) movq %fs:40, %rax movq %rax, 232(%rsp) xorl %eax, %eax movslq 368(%rsp), %rbx movslq 376(%rsp), %rax imulq %rax, %rbx movslq 360(%rsp), %rax imulq %rax, %rbx salq $3, %rbx leaq 104(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC1(%rip), %rdi call _Z11check_errorPKc leaq 112(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC2(%rip), %rdi call _Z11check_errorPKc leaq 120(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC3(%rip), %rdi call _Z11check_errorPKc leaq 128(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC4(%rip), %rdi call _Z11check_errorPKc leaq 136(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC5(%rip), %rdi call _Z11check_errorPKc leaq 144(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC6(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq 72(%rsp), %rsi movq 144(%rsp), %rdi call cudaMemcpy@PLT leaq 152(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC7(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq %rbp, %rsi movq 152(%rsp), %rdi call cudaMemcpy@PLT leaq 160(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC8(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq %r12, %rsi movq 160(%rsp), %rdi call cudaMemcpy@PLT leaq 168(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC9(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq %r13, %rsi movq 168(%rsp), %rdi call cudaMemcpy@PLT leaq 176(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC10(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq %r14, %rsi movq 176(%rsp), %rdi call cudaMemcpy@PLT leaq 184(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC11(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq %r15, %rsi movq 184(%rsp), %rdi call cudaMemcpy@PLT leaq 192(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC12(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq 80(%rsp), %rsi movq 192(%rsp), %rdi call cudaMemcpy@PLT leaq 200(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq .LC13(%rip), %rdi call _Z11check_errorPKc movl $1, %ecx movq %rbx, %rdx movq 88(%rsp), %rsi movq 200(%rsp), %rdi call cudaMemcpy@PLT movl $16, 208(%rsp) movl $4, 212(%rsp) movl $4, 216(%rsp) testb $3, 360(%rsp) jne .L32 movl 360(%rsp), %eax addl $3, %eax cmpl $0, 360(%rsp) cmovns 360(%rsp), %eax sarl $2, %eax .L33: testb $3, 368(%rsp) jne .L34 movl 368(%rsp), %edx addl $3, %edx cmpl $0, 368(%rsp) cmovns 368(%rsp), %edx sarl $2, %edx .L35: testb $15, 376(%rsp) jne .L36 movl 376(%rsp), %esi leal 15(%rsi), %ecx testl %esi, %esi cmovns %esi, %ecx sarl $4, %ecx .L37: movl %ecx, 220(%rsp) movl %edx, 224(%rsp) movl %eax, 228(%rsp) cmpl $0, 384(%rsp) jle .L44 movl $0, %r12d movl $0, %r13d movl $0, %r14d movl $0, %r15d jmp .L42 .L32: movl 360(%rsp), %eax addl $3, %eax cmpl $0, 360(%rsp) cmovns 360(%rsp), %eax sarl $2, %eax addl $1, %eax jmp .L33 .L34: movl 368(%rsp), %edx addl $3, %edx cmpl $0, 368(%rsp) cmovns 368(%rsp), %edx sarl $2, %edx addl $1, %edx jmp .L35 .L36: movl 376(%rsp), %esi leal 15(%rsi), %ecx testl %esi, %esi cmovns %esi, %ecx sarl $4, %ecx addl $1, %ecx jmp .L37 .L47: movl 376(%rsp), %eax pushq %rax .cfi_def_cfa_offset 312 movl 376(%rsp), %eax pushq %rax .cfi_def_cfa_offset 320 movl 376(%rsp), %eax pushq %rax .cfi_def_cfa_offset 328 pushq 224(%rsp) .cfi_def_cfa_offset 336 pushq 224(%rsp) .cfi_def_cfa_offset 344 pushq 224(%rsp) .cfi_def_cfa_offset 352 pushq 224(%rsp) .cfi_def_cfa_offset 360 pushq 224(%rsp) .cfi_def_cfa_offset 368 pushq 224(%rsp) .cfi_def_cfa_offset 376 pushq 224(%rsp) .cfi_def_cfa_offset 384 movsd 144(%rsp), %xmm2 movsd 136(%rsp), %xmm1 movsd 128(%rsp), %xmm0 movq 224(%rsp), %r9 movq 216(%rsp), %r8 movq 208(%rsp), %rcx movq 200(%rsp), %rdx movq 192(%rsp), %rsi movq 184(%rsp), %rdi call _Z66__device_stub__Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii addq $80, %rsp .cfi_def_cfa_offset 304 jmp .L39 .L48: movl 376(%rsp), %eax pushq %rax .cfi_def_cfa_offset 312 movl 376(%rsp), %eax pushq %rax .cfi_def_cfa_offset 320 movl 376(%rsp), %eax pushq %rax .cfi_def_cfa_offset 328 pushq 224(%rsp) .cfi_def_cfa_offset 336 pushq 224(%rsp) .cfi_def_cfa_offset 344 pushq 224(%rsp) .cfi_def_cfa_offset 352 pushq 224(%rsp) .cfi_def_cfa_offset 360 pushq 224(%rsp) .cfi_def_cfa_offset 368 pushq 224(%rsp) .cfi_def_cfa_offset 376 pushq 224(%rsp) .cfi_def_cfa_offset 384 movsd 144(%rsp), %xmm2 movsd 136(%rsp), %xmm1 movsd 128(%rsp), %xmm0 movq 224(%rsp), %r9 movq 216(%rsp), %r8 movq 208(%rsp), %rcx movq 200(%rsp), %rdx movq 192(%rsp), %rsi movq 184(%rsp), %rdi call _Z66__device_stub__Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii addq $80, %rsp .cfi_def_cfa_offset 304 jmp .L40 .L41: call cudaDeviceSynchronize@PLT call _ZNSt6chrono3_V212steady_clock3nowEv@PLT subq %rbp, %rax addq %rax, %r13 addl $1, %r12d cmpl %r12d, 384(%rsp) je .L38 .L42: movl $1, %ecx movq %rbx, %rdx movq 8(%rsp), %rsi movq 104(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq 16(%rsp), %rsi movq 112(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq 24(%rsp), %rsi movq 120(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq 32(%rsp), %rsi movq 128(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq 40(%rsp), %rsi movq 136(%rsp), %rdi call cudaMemcpy@PLT call cudaDeviceSynchronize@PLT call _ZNSt6chrono3_V212steady_clock3nowEv@PLT movq %rax, %rbp movl 216(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 208(%rsp), %rdx movq 220(%rsp), %rdi movl 228(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L47 .L39: call cudaDeviceSynchronize@PLT call _ZNSt6chrono3_V212steady_clock3nowEv@PLT subq %rbp, %rax addq %rax, %r15 call _ZNSt6chrono3_V212steady_clock3nowEv@PLT movq %rax, %rbp movl 216(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 208(%rsp), %rdx movq 220(%rsp), %rdi movl 228(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L48 .L40: call cudaDeviceSynchronize@PLT call _ZNSt6chrono3_V212steady_clock3nowEv@PLT subq %rbp, %rax addq %rax, %r14 call _ZNSt6chrono3_V212steady_clock3nowEv@PLT movq %rax, %rbp movl 216(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 208(%rsp), %rdx movq 220(%rsp), %rdi movl 228(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L41 movl 376(%rsp), %eax pushq %rax .cfi_def_cfa_offset 312 movl 376(%rsp), %eax pushq %rax .cfi_def_cfa_offset 320 movl 376(%rsp), %eax pushq %rax .cfi_def_cfa_offset 328 pushq 224(%rsp) .cfi_def_cfa_offset 336 pushq 224(%rsp) .cfi_def_cfa_offset 344 pushq 224(%rsp) .cfi_def_cfa_offset 352 pushq 224(%rsp) .cfi_def_cfa_offset 360 pushq 224(%rsp) .cfi_def_cfa_offset 368 pushq 224(%rsp) .cfi_def_cfa_offset 376 pushq 224(%rsp) .cfi_def_cfa_offset 384 movsd 144(%rsp), %xmm2 movsd 136(%rsp), %xmm1 movsd 128(%rsp), %xmm0 movq 224(%rsp), %r9 movq 216(%rsp), %r8 movq 208(%rsp), %rcx movq 200(%rsp), %rdx movq 192(%rsp), %rsi movq 184(%rsp), %rdi call _Z66__device_stub__Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiiiPdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii addq $80, %rsp .cfi_def_cfa_offset 304 jmp .L41 .L44: movl $0, %r13d movl $0, %r14d movl $0, %r15d .L38: pxor %xmm3, %xmm3 cvtsi2sdl 384(%rsp), %xmm3 pxor %xmm0, %xmm0 cvtsi2sdq %r15, %xmm0 mulsd .LC14(%rip), %xmm0 movsd %xmm3, 48(%rsp) divsd %xmm3, %xmm0 leaq .LC15(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT pxor %xmm0, %xmm0 cvtsi2sdq %r14, %xmm0 mulsd .LC14(%rip), %xmm0 divsd 48(%rsp), %xmm0 leaq .LC16(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT pxor %xmm0, %xmm0 cvtsi2sdq %r13, %xmm0 mulsd .LC14(%rip), %xmm0 divsd 48(%rsp), %xmm0 leaq .LC17(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl $2, %ecx movq %rbx, %rdx movq 104(%rsp), %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $2, %ecx movq %rbx, %rdx movq 112(%rsp), %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $2, %ecx movq %rbx, %rdx movq 120(%rsp), %rsi movq 24(%rsp), %rdi call cudaMemcpy@PLT movl $2, %ecx movq %rbx, %rdx movq 128(%rsp), %rsi movq 32(%rsp), %rdi call cudaMemcpy@PLT movl $2, %ecx movq %rbx, %rdx movq 136(%rsp), %rsi movq 40(%rsp), %rdi call cudaMemcpy@PLT movq 144(%rsp), %rdi call cudaFree@PLT movq 152(%rsp), %rdi call cudaFree@PLT movq 160(%rsp), %rdi call cudaFree@PLT movq 168(%rsp), %rdi call cudaFree@PLT movq 176(%rsp), %rdi call cudaFree@PLT movq 184(%rsp), %rdi call cudaFree@PLT movq 192(%rsp), %rdi call cudaFree@PLT movq 200(%rsp), %rdi call cudaFree@PLT movq 104(%rsp), %rdi call cudaFree@PLT movq 112(%rsp), %rdi call cudaFree@PLT movq 120(%rsp), %rdi call cudaFree@PLT movq 128(%rsp), %rdi call cudaFree@PLT movq 136(%rsp), %rdi call cudaFree@PLT movq 232(%rsp), %rax subq %fs:40, %rax jne .L49 addq $248, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L49: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2157: .size offload, .-offload .section .rodata.str1.8 .align 8 .LC18: .string "_Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii" .align 8 .LC19: .string "_Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii" .align 8 .LC20: .string "_Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2191: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC18(%rip), %rdx movq %rdx, %rcx leaq _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC19(%rip), %rdx movq %rdx, %rcx leaq _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC20(%rip), %rdx movq %rdx, %rcx leaq _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2191: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC14: .long -1598689907 .long 1051772663 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii ; -- Begin function _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .globl _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .p2align 8 .type _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii,@function _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: ; @_Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii ; %bb.0: s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x9c s_load_b32 s3, s[0:1], 0x88 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v2, v0, 10, 10 v_bfe_u32 v3, v0, 20, 10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s4, 0xffff s_lshr_b32 s4, s4, 16 s_and_b32 s5, s5, 0xffff s_mul_i32 s13, s13, s2 s_mul_i32 s14, s14, s4 s_mul_i32 s15, s15, s5 s_max_i32 s2, s13, 0 s_max_i32 s4, s14, 0 s_max_i32 s5, s15, 0 v_add_nc_u32_e32 v0, s2, v1 v_add_nc_u32_e32 v1, s4, v2 v_add_nc_u32_e32 v2, s5, v3 s_add_i32 s2, s3, -5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_min3_u32 v3, v0, v1, v2 v_max3_i32 v4, v0, v1, v2 v_cmp_lt_u32_e32 vcc_lo, 3, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_ge_i32_e64 s2, s2, v4 s_and_b32 s2, s2, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s4, s2 s_cbranch_execz .LBB0_2 ; %bb.1: s_clause 0x3 s_load_b32 s2, s[0:1], 0x84 s_load_b128 s[16:19], s[0:1], 0x60 s_load_b256 s[4:11], s[0:1], 0x20 s_load_b128 s[12:15], s[0:1], 0x40 s_waitcnt lgkmcnt(0) v_mad_u64_u32 v[3:4], null, v2, s2, v[1:2] s_brev_b32 s2, 5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, v3, s3, v[0:1] s_mov_b32 s3, 0x3fc99999 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[1:2] v_add_co_u32 v42, vcc_lo, v0, -16 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_ci_u32_e32 v43, vcc_lo, -1, v1, vcc_lo v_add_co_u32 v2, vcc_lo, s6, v42 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s7, v43, vcc_lo v_add_co_u32 v4, vcc_lo, s14, v42 v_add_co_ci_u32_e32 v5, vcc_lo, s15, v43, vcc_lo v_add_co_u32 v6, vcc_lo, s8, v42 v_add_co_ci_u32_e32 v7, vcc_lo, s9, v43, vcc_lo v_add_co_u32 v8, vcc_lo, s10, v42 global_load_b64 v[2:3], v[2:3], off global_load_b64 v[4:5], v[4:5], off v_add_co_ci_u32_e32 v9, vcc_lo, s11, v43, vcc_lo v_add_co_u32 v10, vcc_lo, s12, v42 global_load_b64 v[6:7], v[6:7], off v_add_co_ci_u32_e32 v11, vcc_lo, s13, v43, vcc_lo global_load_b64 v[8:9], v[8:9], off global_load_b64 v[10:11], v[10:11], off v_add_co_u32 v40, vcc_lo, v0, 16 v_add_co_ci_u32_e32 v41, vcc_lo, 0, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v12, vcc_lo, s6, v40 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v41, vcc_lo v_add_co_u32 v14, vcc_lo, s14, v40 v_add_co_ci_u32_e32 v15, vcc_lo, s15, v41, vcc_lo v_add_co_u32 v16, vcc_lo, s8, v40 v_add_co_ci_u32_e32 v17, vcc_lo, s9, v41, vcc_lo v_add_co_u32 v18, vcc_lo, s10, v40 global_load_b64 v[12:13], v[12:13], off global_load_b64 v[14:15], v[14:15], off v_add_co_ci_u32_e32 v19, vcc_lo, s11, v41, vcc_lo v_add_co_u32 v20, vcc_lo, s12, v40 global_load_b64 v[16:17], v[16:17], off global_load_b64 v[18:19], v[18:19], off v_add_co_ci_u32_e32 v21, vcc_lo, s13, v41, vcc_lo v_add_co_u32 v78, vcc_lo, v0, 8 v_add_co_ci_u32_e32 v79, vcc_lo, 0, v1, vcc_lo global_load_b64 v[20:21], v[20:21], off v_add_co_u32 v80, vcc_lo, v0, -8 v_add_co_ci_u32_e32 v81, vcc_lo, -1, v1, vcc_lo v_add_co_u32 v82, vcc_lo, v0, 24 v_add_co_ci_u32_e32 v83, vcc_lo, 0, v1, vcc_lo v_add_co_u32 v84, vcc_lo, v0, 0xffffffe8 v_add_co_ci_u32_e32 v85, vcc_lo, -1, v1, vcc_lo v_add_co_u32 v86, vcc_lo, v0, 32 v_add_co_ci_u32_e32 v87, vcc_lo, 0, v1, vcc_lo v_add_co_u32 v90, vcc_lo, v0, 0xffffffe0 v_add_co_ci_u32_e32 v91, vcc_lo, -1, v1, vcc_lo v_add_co_u32 v22, vcc_lo, s6, v78 v_add_co_ci_u32_e32 v23, vcc_lo, s7, v79, vcc_lo v_add_co_u32 v24, vcc_lo, s6, v80 v_add_co_ci_u32_e32 v25, vcc_lo, s7, v81, vcc_lo v_add_co_u32 v26, vcc_lo, s6, v82 v_add_co_ci_u32_e32 v27, vcc_lo, s7, v83, vcc_lo v_add_co_u32 v28, vcc_lo, s6, v84 v_add_co_ci_u32_e32 v29, vcc_lo, s7, v85, vcc_lo v_add_co_u32 v30, vcc_lo, s6, v86 v_add_co_ci_u32_e32 v31, vcc_lo, s7, v87, vcc_lo v_add_co_u32 v32, vcc_lo, s14, v78 v_add_co_ci_u32_e32 v33, vcc_lo, s15, v79, vcc_lo v_add_co_u32 v34, vcc_lo, s14, v80 v_add_co_ci_u32_e32 v35, vcc_lo, s15, v81, vcc_lo v_add_co_u32 v36, vcc_lo, s16, v78 v_add_co_ci_u32_e32 v37, vcc_lo, s17, v79, vcc_lo v_add_co_u32 v38, vcc_lo, s16, v80 v_add_co_ci_u32_e32 v39, vcc_lo, s17, v81, vcc_lo v_add_co_u32 v40, vcc_lo, s16, v40 v_add_co_ci_u32_e32 v41, vcc_lo, s17, v41, vcc_lo v_add_co_u32 v42, vcc_lo, s16, v42 v_add_co_ci_u32_e32 v43, vcc_lo, s17, v43, vcc_lo v_add_co_u32 v44, vcc_lo, s14, v82 v_add_co_ci_u32_e32 v45, vcc_lo, s15, v83, vcc_lo v_add_co_u32 v46, vcc_lo, s14, v84 v_add_co_ci_u32_e32 v47, vcc_lo, s15, v85, vcc_lo v_add_co_u32 v48, vcc_lo, s16, v82 v_add_co_ci_u32_e32 v49, vcc_lo, s17, v83, vcc_lo v_add_co_u32 v50, vcc_lo, s16, v84 v_add_co_ci_u32_e32 v51, vcc_lo, s17, v85, vcc_lo v_add_co_u32 v52, vcc_lo, s14, v86 v_add_co_ci_u32_e32 v53, vcc_lo, s15, v87, vcc_lo v_add_co_u32 v54, vcc_lo, s16, v86 v_add_co_ci_u32_e32 v55, vcc_lo, s17, v87, vcc_lo v_add_co_u32 v56, vcc_lo, s8, v78 v_add_co_ci_u32_e32 v57, vcc_lo, s9, v79, vcc_lo v_add_co_u32 v58, vcc_lo, s8, v80 v_add_co_ci_u32_e32 v59, vcc_lo, s9, v81, vcc_lo v_add_co_u32 v60, vcc_lo, s8, v82 v_add_co_ci_u32_e32 v61, vcc_lo, s9, v83, vcc_lo v_add_co_u32 v62, vcc_lo, s8, v84 v_add_co_ci_u32_e32 v63, vcc_lo, s9, v85, vcc_lo v_add_co_u32 v64, vcc_lo, s8, v86 v_add_co_ci_u32_e32 v65, vcc_lo, s9, v87, vcc_lo v_add_co_u32 v66, vcc_lo, s10, v78 v_add_co_ci_u32_e32 v67, vcc_lo, s11, v79, vcc_lo v_add_co_u32 v68, vcc_lo, s10, v80 v_add_co_ci_u32_e32 v69, vcc_lo, s11, v81, vcc_lo v_add_co_u32 v72, vcc_lo, s10, v82 v_add_co_ci_u32_e32 v73, vcc_lo, s11, v83, vcc_lo v_add_co_u32 v74, vcc_lo, s10, v84 v_add_co_ci_u32_e32 v75, vcc_lo, s11, v85, vcc_lo v_add_co_u32 v76, vcc_lo, s10, v86 v_add_co_ci_u32_e32 v77, vcc_lo, s11, v87, vcc_lo v_add_co_u32 v78, vcc_lo, s12, v78 v_add_co_ci_u32_e32 v79, vcc_lo, s13, v79, vcc_lo v_add_co_u32 v80, vcc_lo, s12, v80 v_add_co_ci_u32_e32 v81, vcc_lo, s13, v81, vcc_lo v_add_co_u32 v82, vcc_lo, s12, v82 v_add_co_ci_u32_e32 v83, vcc_lo, s13, v83, vcc_lo v_add_co_u32 v84, vcc_lo, s12, v84 v_add_co_ci_u32_e32 v85, vcc_lo, s13, v85, vcc_lo v_add_co_u32 v86, vcc_lo, s12, v86 v_add_co_ci_u32_e32 v87, vcc_lo, s13, v87, vcc_lo v_add_co_u32 v88, vcc_lo, s6, v90 v_add_co_ci_u32_e32 v89, vcc_lo, s7, v91, vcc_lo s_waitcnt vmcnt(8) v_mul_f64 v[70:71], v[2:3], v[4:5] s_waitcnt vmcnt(7) v_mul_f64 v[6:7], v[4:5], v[6:7] s_waitcnt vmcnt(6) v_mul_f64 v[8:9], v[4:5], v[8:9] s_waitcnt vmcnt(5) v_mul_f64 v[10:11], v[4:5], v[10:11] s_waitcnt vmcnt(4) v_add_f64 v[2:3], v[12:13], -v[2:3] s_waitcnt vmcnt(3) v_fma_f64 v[12:13], v[12:13], v[14:15], -v[70:71] v_add_co_u32 v70, vcc_lo, s14, v90 v_add_co_ci_u32_e32 v71, vcc_lo, s15, v91, vcc_lo s_waitcnt vmcnt(2) v_fma_f64 v[6:7], v[14:15], v[16:17], -v[6:7] v_add_co_u32 v16, vcc_lo, s16, v90 v_add_co_ci_u32_e32 v17, vcc_lo, s17, v91, vcc_lo s_waitcnt vmcnt(1) v_fma_f64 v[8:9], v[14:15], v[18:19], -v[8:9] v_add_co_u32 v18, vcc_lo, s8, v90 v_add_co_ci_u32_e32 v19, vcc_lo, s9, v91, vcc_lo s_waitcnt vmcnt(0) v_fma_f64 v[10:11], v[14:15], v[20:21], -v[10:11] v_add_co_u32 v20, vcc_lo, s10, v90 v_add_co_ci_u32_e32 v21, vcc_lo, s11, v91, vcc_lo v_add_co_u32 v90, vcc_lo, s12, v90 v_add_co_ci_u32_e32 v91, vcc_lo, s13, v91, vcc_lo global_load_b64 v[42:43], v[42:43], off global_load_b64 v[80:81], v[80:81], off global_load_b64 v[34:35], v[34:35], off global_load_b64 v[40:41], v[40:41], off global_load_b64 v[24:25], v[24:25], off global_load_b64 v[38:39], v[38:39], off global_load_b64 v[32:33], v[32:33], off global_load_b64 v[58:59], v[58:59], off global_load_b64 v[68:69], v[68:69], off global_load_b64 v[28:29], v[28:29], off global_load_b64 v[46:47], v[46:47], off global_load_b64 v[36:37], v[36:37], off s_clause 0x1 global_load_b64 v[84:85], v[84:85], off global_load_b64 v[78:79], v[78:79], off global_load_b64 v[50:51], v[50:51], off global_load_b64 v[22:23], v[22:23], off global_load_b64 v[48:49], v[48:49], off global_load_b64 v[88:89], v[88:89], off global_load_b64 v[70:71], v[70:71], off global_load_b64 v[62:63], v[62:63], off global_load_b64 v[74:75], v[74:75], off global_load_b64 v[90:91], v[90:91], off global_load_b64 v[16:17], v[16:17], off global_load_b64 v[26:27], v[26:27], off global_load_b64 v[44:45], v[44:45], off global_load_b64 v[56:57], v[56:57], off global_load_b64 v[66:67], v[66:67], off global_load_b64 v[82:83], v[82:83], off global_load_b64 v[30:31], v[30:31], off global_load_b64 v[54:55], v[54:55], off global_load_b64 v[18:19], v[18:19], off global_load_b64 v[20:21], v[20:21], off global_load_b64 v[52:53], v[52:53], off global_load_b64 v[60:61], v[60:61], off global_load_b64 v[72:73], v[72:73], off global_load_b64 v[86:87], v[86:87], off global_load_b64 v[64:65], v[64:65], off global_load_b64 v[76:77], v[76:77], off s_load_b256 s[8:15], s[0:1], 0x0 v_mul_f64 v[2:3], v[2:3], s[2:3] v_mul_f64 v[6:7], v[6:7], s[2:3] v_mul_f64 v[8:9], v[8:9], s[2:3] s_waitcnt vmcnt(37) v_mul_f64 v[4:5], v[4:5], v[42:43] s_waitcnt vmcnt(35) v_mul_f64 v[80:81], v[34:35], v[80:81] s_waitcnt vmcnt(30) v_mul_f64 v[58:59], v[34:35], v[58:59] s_waitcnt vmcnt(25) v_mul_f64 v[84:85], v[46:47], v[84:85] s_waitcnt vmcnt(7) v_mul_f64 v[18:19], v[70:71], v[18:19] s_waitcnt vmcnt(6) v_mul_f64 v[20:21], v[70:71], v[20:21] v_fma_f64 v[4:5], v[14:15], v[40:41], -v[4:5] v_mul_f64 v[14:15], v[24:25], v[34:35] v_add_f64 v[40:41], v[40:41], -v[42:43] v_mul_f64 v[42:43], v[34:35], v[38:39] v_mul_f64 v[34:35], v[34:35], v[68:69] v_mul_f64 v[68:69], v[28:29], v[46:47] v_add_f64 v[38:39], v[36:37], -v[38:39] v_fma_f64 v[78:79], v[32:33], v[78:79], -v[80:81] v_mul_f64 v[80:81], v[46:47], v[50:51] v_fma_f64 v[56:57], v[32:33], v[56:57], -v[58:59] s_waitcnt vmcnt(1) v_fma_f64 v[18:19], v[52:53], v[64:65], -v[18:19] s_waitcnt vmcnt(0) v_fma_f64 v[20:21], v[52:53], v[76:77], -v[20:21] v_add_f64 v[4:5], v[4:5], v[10:11] v_fma_f64 v[14:15], v[22:23], v[32:33], -v[14:15] v_add_f64 v[12:13], v[12:13], v[40:41] v_fma_f64 v[36:37], v[32:33], v[36:37], -v[42:43] v_add_f64 v[10:11], v[22:23], -v[24:25] v_mul_f64 v[40:41], v[46:47], v[62:63] v_mul_f64 v[42:43], v[46:47], v[74:75] v_fma_f64 v[32:33], v[32:33], v[66:67], -v[34:35] v_add_f64 v[22:23], v[48:49], -v[50:51] v_mul_f64 v[24:25], v[88:89], v[70:71] v_fma_f64 v[62:63], v[26:27], v[44:45], -v[68:69] v_mul_f64 v[46:47], v[70:71], v[90:91] v_mul_f64 v[50:51], v[70:71], v[16:17] v_fma_f64 v[34:35], v[44:45], v[82:83], -v[84:85] v_fma_f64 v[48:49], v[44:45], v[48:49], -v[80:81] v_add_f64 v[26:27], v[26:27], -v[28:29] v_add_f64 v[16:17], v[54:55], -v[16:17] v_mul_f64 v[4:5], v[4:5], s[2:3] v_add_f64 v[14:15], v[14:15], v[38:39] v_mul_f64 v[12:13], v[12:13], s[2:3] v_add_f64 v[36:37], v[36:37], v[78:79] s_mov_b32 s3, 0x3fe99999 v_fma_f64 v[28:29], v[44:45], v[60:61], -v[40:41] v_fma_f64 v[2:3], v[10:11], s[2:3], -v[2:3] v_fma_f64 v[6:7], v[56:57], s[2:3], -v[6:7] v_fma_f64 v[38:39], v[44:45], v[72:73], -v[42:43] v_fma_f64 v[8:9], v[32:33], s[2:3], -v[8:9] v_fma_f64 v[24:25], v[30:31], v[52:53], -v[24:25] v_add_f64 v[10:11], v[62:63], v[22:23] v_fma_f64 v[40:41], v[52:53], v[86:87], -v[46:47] v_fma_f64 v[42:43], v[52:53], v[54:55], -v[50:51] v_add_f64 v[22:23], v[48:49], v[34:35] v_fma_f64 v[12:13], v[14:15], s[2:3], -v[12:13] v_fma_f64 v[4:5], v[36:37], s[2:3], -v[4:5] s_mov_b32 s3, 0x3fa374bc s_brev_b32 s2, 6 v_add_f64 v[14:15], v[30:31], -v[88:89] v_fma_f64 v[2:3], v[26:27], s[2:3], v[2:3] v_fma_f64 v[6:7], v[28:29], s[2:3], v[6:7] v_fma_f64 v[8:9], v[38:39], s[2:3], v[8:9] v_add_f64 v[16:17], v[24:25], v[16:17] v_add_f64 v[24:25], v[42:43], v[40:41] v_fma_f64 v[10:11], v[10:11], s[2:3], v[12:13] v_fma_f64 v[4:5], v[22:23], s[2:3], v[4:5] s_mov_b32 s3, 0xbf6cac08 s_mov_b32 s2, 2.0 s_waitcnt lgkmcnt(0) v_add_co_u32 v12, vcc_lo, s8, v0 v_fma_f64 v[2:3], v[14:15], s[2:3], v[2:3] v_fma_f64 v[6:7], v[18:19], s[2:3], v[6:7] v_fma_f64 v[8:9], v[20:21], s[2:3], v[8:9] v_add_co_ci_u32_e32 v13, vcc_lo, s9, v1, vcc_lo v_add_co_u32 v14, vcc_lo, s10, v0 v_add_co_ci_u32_e32 v15, vcc_lo, s11, v1, vcc_lo v_fma_f64 v[10:11], v[16:17], s[2:3], v[10:11] v_fma_f64 v[4:5], v[24:25], s[2:3], v[4:5] v_add_co_u32 v16, vcc_lo, s12, v0 v_add_co_ci_u32_e32 v17, vcc_lo, s13, v1, vcc_lo v_mul_f64 v[2:3], -v[2:3], s[18:19] v_mul_f64 v[6:7], -v[6:7], s[18:19] v_mul_f64 v[8:9], -v[8:9], s[18:19] v_add_co_u32 v18, vcc_lo, s14, v0 v_add_co_ci_u32_e32 v19, vcc_lo, s15, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo v_mul_f64 v[10:11], -v[10:11], s[18:19] v_mul_f64 v[4:5], -v[4:5], s[18:19] global_store_b64 v[12:13], v[2:3], off global_store_b64 v[16:17], v[6:7], off global_store_b64 v[18:19], v[8:9], off global_store_b64 v[14:15], v[10:11], off global_store_b64 v[0:1], v[4:5], off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 400 .amdhsa_user_sgpr_count 13 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 1 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 92 .amdhsa_next_free_sgpr 20 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, .Lfunc_end0-_Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 2200 ; NumSgprs: 22 ; NumVgprs: 92 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 11 ; NumSGPRsForWavesPerEU: 22 ; NumVGPRsForWavesPerEU: 92 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 13 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2 .text .protected _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii ; -- Begin function _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .globl _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .p2align 8 .type _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii,@function _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: ; @_Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii ; %bb.0: s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x9c s_load_b32 s33, s[0:1], 0x88 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 v_bfe_u32 v0, v0, 20, 10 s_waitcnt lgkmcnt(0) s_and_b32 s4, s2, 0xffff s_lshr_b32 s2, s2, 16 s_and_b32 s3, s3, 0xffff s_mul_i32 s13, s13, s4 s_mul_i32 s14, s14, s2 s_mul_i32 s15, s15, s3 s_max_i32 s2, s13, 0 s_max_i32 s3, s14, 0 s_max_i32 s4, s15, 0 v_add_nc_u32_e32 v2, s2, v1 v_add_nc_u32_e32 v3, s3, v3 v_add_nc_u32_e32 v12, s4, v0 s_add_i32 s2, s33, -5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_min3_u32 v0, v2, v3, v12 v_max3_i32 v1, v2, v3, v12 v_cmp_lt_u32_e32 vcc_lo, 3, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_ge_i32_e64 s2, s2, v1 s_and_b32 s2, s2, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB1_2 ; %bb.1: s_clause 0x6 s_load_b64 s[2:3], s[0:1], 0x60 s_load_b128 s[24:27], s[0:1], 0x50 s_load_b64 s[28:29], s[0:1], 0x40 s_load_b256 s[12:19], s[0:1], 0x0 s_load_b256 s[4:11], s[0:1], 0x20 s_load_b128 s[20:23], s[0:1], 0x70 s_load_b32 s38, s[0:1], 0x84 s_mov_b32 s35, 0x3fc99999 s_brev_b32 s34, 5 s_mov_b32 s37, 0x3fe99999 s_mov_b32 s36, s34 s_mov_b32 s31, 0x3fa374bc s_brev_b32 s30, 6 s_mov_b32 s1, 0xbf6cac08 s_mov_b32 s0, 2.0 s_waitcnt lgkmcnt(0) v_mad_u64_u32 v[4:5], null, v12, s38, v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[0:1], null, v4, s33, v[2:3] v_add_nc_u32_e32 v1, -1, v4 v_mad_u64_u32 v[9:10], null, v1, s33, v[2:3] v_add_nc_u32_e32 v1, 2, v4 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v5, s33, v0 v_mad_u64_u32 v[17:18], null, v1, s33, v[2:3] v_add_nc_u32_e32 v1, -2, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_ashrrev_i32_e32 v6, 31, v5 v_ashrrev_i32_e32 v10, 31, v9 v_mad_u64_u32 v[21:22], null, v1, s33, v[2:3] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_lshlrev_b64 v[5:6], 3, v[5:6] v_ashrrev_i32_e32 v18, 31, v17 v_lshlrev_b64 v[9:10], 3, v[9:10] v_add_nc_u32_e32 v1, 3, v4 v_ashrrev_i32_e32 v22, 31, v21 v_add_co_u32 v7, vcc_lo, s8, v5 v_lshlrev_b64 v[17:18], 3, v[17:18] v_add_co_ci_u32_e32 v8, vcc_lo, s9, v6, vcc_lo v_add_co_u32 v13, vcc_lo, s8, v9 v_lshlrev_b64 v[21:22], 3, v[21:22] v_add_co_ci_u32_e32 v14, vcc_lo, s9, v10, vcc_lo v_add_co_u32 v19, vcc_lo, s8, v17 v_add_co_ci_u32_e32 v20, vcc_lo, s9, v18, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v23, vcc_lo, s8, v21 v_add_co_ci_u32_e32 v24, vcc_lo, s9, v22, vcc_lo s_clause 0x3 global_load_b64 v[7:8], v[7:8], off global_load_b64 v[13:14], v[13:14], off global_load_b64 v[19:20], v[19:20], off global_load_b64 v[23:24], v[23:24], off s_waitcnt vmcnt(2) v_add_f64 v[15:16], v[7:8], -v[13:14] s_waitcnt vmcnt(0) v_add_f64 v[25:26], v[19:20], -v[23:24] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[25:26], v[25:26], s[34:35] v_fma_f64 v[15:16], v[15:16], s[36:37], -v[25:26] v_mad_u64_u32 v[25:26], null, v1, s33, v[2:3] v_add_nc_u32_e32 v1, -3, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_mad_u64_u32 v[29:30], null, v1, s33, v[2:3] v_ashrrev_i32_e32 v26, 31, v25 v_add_nc_u32_e32 v1, 4, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[25:26], 3, v[25:26] v_ashrrev_i32_e32 v30, 31, v29 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[29:30], 3, v[29:30] v_add_co_u32 v27, vcc_lo, s8, v25 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v28, vcc_lo, s9, v26, vcc_lo v_add_co_u32 v31, vcc_lo, s8, v29 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v32, vcc_lo, s9, v30, vcc_lo s_clause 0x1 global_load_b64 v[27:28], v[27:28], off global_load_b64 v[31:32], v[31:32], off s_waitcnt vmcnt(0) v_add_f64 v[33:34], v[27:28], -v[31:32] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_fma_f64 v[15:16], v[33:34], s[30:31], v[15:16] v_mad_u64_u32 v[33:34], null, v1, s33, v[2:3] v_add_nc_u32_e32 v1, -4, v4 v_mad_u64_u32 v[37:38], null, v1, s33, v[2:3] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v34, 31, v33 v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[33:34], 3, v[33:34] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_ashrrev_i32_e32 v38, 31, v37 v_lshlrev_b64 v[0:1], 3, v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[37:38], 3, v[37:38] v_add_co_u32 v35, vcc_lo, s8, v33 v_add_co_ci_u32_e32 v36, vcc_lo, s9, v34, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v39, vcc_lo, s8, v37 v_add_co_ci_u32_e32 v40, vcc_lo, s9, v38, vcc_lo s_clause 0x1 global_load_b64 v[35:36], v[35:36], off global_load_b64 v[39:40], v[39:40], off s_waitcnt vmcnt(0) v_add_f64 v[41:42], v[35:36], -v[39:40] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[15:16], v[41:42], s[0:1], v[15:16] v_add_co_u32 v41, vcc_lo, s12, v0 v_add_co_ci_u32_e32 v42, vcc_lo, s13, v1, vcc_lo global_load_b64 v[43:44], v[41:42], off s_waitcnt vmcnt(0) v_fma_f64 v[15:16], -v[15:16], s[20:21], v[43:44] global_store_b64 v[41:42], v[15:16], off v_add_co_u32 v15, vcc_lo, s6, v5 v_add_co_ci_u32_e32 v16, vcc_lo, s7, v6, vcc_lo v_add_co_u32 v41, vcc_lo, s24, v5 v_add_co_ci_u32_e32 v42, vcc_lo, s25, v6, vcc_lo v_add_co_u32 v43, vcc_lo, s6, v9 v_add_co_ci_u32_e32 v44, vcc_lo, s7, v10, vcc_lo v_add_co_u32 v45, vcc_lo, s24, v9 v_add_co_ci_u32_e32 v46, vcc_lo, s25, v10, vcc_lo s_clause 0x1 global_load_b64 v[43:44], v[43:44], off global_load_b64 v[15:16], v[15:16], off s_clause 0x1 global_load_b64 v[41:42], v[41:42], off global_load_b64 v[45:46], v[45:46], off s_waitcnt vmcnt(0) v_mul_f64 v[43:44], v[43:44], v[45:46] v_mul_f64 v[13:14], v[13:14], v[45:46] s_delay_alu instid0(VALU_DEP_2) v_fma_f64 v[15:16], v[15:16], v[41:42], -v[43:44] v_add_co_u32 v43, vcc_lo, s6, v17 v_add_co_ci_u32_e32 v44, vcc_lo, s7, v18, vcc_lo v_add_co_u32 v47, vcc_lo, s24, v17 v_add_co_ci_u32_e32 v48, vcc_lo, s25, v18, vcc_lo v_add_co_u32 v49, vcc_lo, s6, v21 v_add_co_ci_u32_e32 v50, vcc_lo, s7, v22, vcc_lo v_add_co_u32 v51, vcc_lo, s24, v21 v_add_co_ci_u32_e32 v52, vcc_lo, s25, v22, vcc_lo s_clause 0x1 global_load_b64 v[49:50], v[49:50], off global_load_b64 v[43:44], v[43:44], off s_clause 0x1 global_load_b64 v[47:48], v[47:48], off global_load_b64 v[51:52], v[51:52], off v_fma_f64 v[7:8], v[7:8], v[41:42], -v[13:14] s_waitcnt vmcnt(0) v_mul_f64 v[49:50], v[49:50], v[51:52] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[43:44], v[43:44], v[47:48], -v[49:50] v_mul_f64 v[43:44], v[43:44], s[34:35] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[15:16], v[15:16], s[36:37], -v[43:44] v_add_co_u32 v43, vcc_lo, s6, v25 v_add_co_ci_u32_e32 v44, vcc_lo, s7, v26, vcc_lo v_add_co_u32 v49, vcc_lo, s24, v25 v_add_co_ci_u32_e32 v50, vcc_lo, s25, v26, vcc_lo v_add_co_u32 v53, vcc_lo, s6, v29 v_add_co_ci_u32_e32 v54, vcc_lo, s7, v30, vcc_lo v_add_co_u32 v55, vcc_lo, s24, v29 v_add_co_ci_u32_e32 v56, vcc_lo, s25, v30, vcc_lo s_clause 0x1 global_load_b64 v[53:54], v[53:54], off global_load_b64 v[43:44], v[43:44], off s_clause 0x1 global_load_b64 v[49:50], v[49:50], off global_load_b64 v[55:56], v[55:56], off s_waitcnt vmcnt(0) v_mul_f64 v[53:54], v[53:54], v[55:56] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[43:44], v[43:44], v[49:50], -v[53:54] v_fma_f64 v[15:16], v[43:44], s[30:31], v[15:16] v_add_co_u32 v43, vcc_lo, s6, v33 v_add_co_ci_u32_e32 v44, vcc_lo, s7, v34, vcc_lo v_add_co_u32 v53, vcc_lo, s24, v33 v_add_co_ci_u32_e32 v54, vcc_lo, s25, v34, vcc_lo v_add_co_u32 v57, vcc_lo, s6, v37 v_add_co_ci_u32_e32 v58, vcc_lo, s7, v38, vcc_lo v_add_co_u32 v59, vcc_lo, s24, v37 v_add_co_ci_u32_e32 v60, vcc_lo, s25, v38, vcc_lo s_clause 0x1 global_load_b64 v[57:58], v[57:58], off global_load_b64 v[43:44], v[43:44], off s_clause 0x1 global_load_b64 v[53:54], v[53:54], off global_load_b64 v[59:60], v[59:60], off s_waitcnt vmcnt(0) v_mul_f64 v[57:58], v[57:58], v[59:60] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[43:44], v[43:44], v[53:54], -v[57:58] v_fma_f64 v[15:16], v[43:44], s[0:1], v[15:16] v_add_co_u32 v43, vcc_lo, s14, v0 v_add_co_ci_u32_e32 v44, vcc_lo, s15, v1, vcc_lo v_add_co_u32 v13, vcc_lo, s2, v5 v_add_co_ci_u32_e32 v14, vcc_lo, s3, v6, vcc_lo global_load_b64 v[57:58], v[43:44], off global_load_b64 v[13:14], v[13:14], off s_waitcnt vmcnt(1) v_fma_f64 v[15:16], -v[15:16], s[20:21], v[57:58] global_store_b64 v[43:44], v[15:16], off v_add_co_u32 v15, vcc_lo, s2, v9 v_add_co_ci_u32_e32 v16, vcc_lo, s3, v10, vcc_lo global_load_b64 v[15:16], v[15:16], off s_waitcnt vmcnt(0) v_add_f64 v[13:14], v[13:14], -v[15:16] v_add_co_u32 v15, vcc_lo, s2, v17 v_add_co_ci_u32_e32 v16, vcc_lo, s3, v18, vcc_lo global_load_b64 v[15:16], v[15:16], off v_add_f64 v[7:8], v[7:8], v[13:14] v_mul_f64 v[13:14], v[23:24], v[51:52] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[13:14], v[19:20], v[47:48], -v[13:14] v_add_co_u32 v19, vcc_lo, s2, v21 v_add_co_ci_u32_e32 v20, vcc_lo, s3, v22, vcc_lo global_load_b64 v[19:20], v[19:20], off s_waitcnt vmcnt(0) v_add_f64 v[15:16], v[15:16], -v[19:20] s_delay_alu instid0(VALU_DEP_1) v_add_f64 v[13:14], v[13:14], v[15:16] v_add_co_u32 v15, vcc_lo, s2, v25 v_add_co_ci_u32_e32 v16, vcc_lo, s3, v26, vcc_lo v_add_co_u32 v19, vcc_lo, s2, v29 v_add_co_ci_u32_e32 v20, vcc_lo, s3, v30, vcc_lo s_clause 0x1 global_load_b64 v[15:16], v[15:16], off global_load_b64 v[19:20], v[19:20], off v_mul_f64 v[13:14], v[13:14], s[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[7:8], v[7:8], s[36:37], -v[13:14] v_mul_f64 v[13:14], v[31:32], v[55:56] v_fma_f64 v[13:14], v[27:28], v[49:50], -v[13:14] s_waitcnt vmcnt(0) v_add_f64 v[15:16], v[15:16], -v[19:20] s_delay_alu instid0(VALU_DEP_1) v_add_f64 v[13:14], v[13:14], v[15:16] v_add_co_u32 v15, vcc_lo, s2, v33 v_add_co_ci_u32_e32 v16, vcc_lo, s3, v34, vcc_lo v_add_co_u32 v19, vcc_lo, s2, v37 v_add_co_ci_u32_e32 v20, vcc_lo, s3, v38, vcc_lo s_clause 0x1 global_load_b64 v[15:16], v[15:16], off global_load_b64 v[19:20], v[19:20], off v_fma_f64 v[7:8], v[13:14], s[30:31], v[7:8] v_mul_f64 v[13:14], v[39:40], v[59:60] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_fma_f64 v[13:14], v[35:36], v[53:54], -v[13:14] s_waitcnt vmcnt(0) v_add_f64 v[15:16], v[15:16], -v[19:20] v_add_f64 v[13:14], v[13:14], v[15:16] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[7:8], v[13:14], s[0:1], v[7:8] v_add_co_u32 v13, vcc_lo, s16, v0 v_add_co_ci_u32_e32 v14, vcc_lo, s17, v1, vcc_lo v_add_co_u32 v5, vcc_lo, s10, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo global_load_b64 v[15:16], v[13:14], off global_load_b64 v[5:6], v[5:6], off s_waitcnt vmcnt(1) v_fma_f64 v[7:8], -v[7:8], s[20:21], v[15:16] global_store_b64 v[13:14], v[7:8], off v_add_co_u32 v7, vcc_lo, s10, v9 v_add_co_ci_u32_e32 v8, vcc_lo, s11, v10, vcc_lo v_add_nc_u32_e32 v13, -1, v12 global_load_b64 v[7:8], v[7:8], off s_waitcnt vmcnt(0) v_mul_f64 v[7:8], v[45:46], v[7:8] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[5:6], v[41:42], v[5:6], -v[7:8] v_add_co_u32 v7, vcc_lo, s10, v17 v_add_co_ci_u32_e32 v8, vcc_lo, s11, v18, vcc_lo v_add_co_u32 v9, vcc_lo, s10, v21 v_add_co_ci_u32_e32 v10, vcc_lo, s11, v22, vcc_lo s_clause 0x1 global_load_b64 v[7:8], v[7:8], off global_load_b64 v[9:10], v[9:10], off s_waitcnt vmcnt(0) v_mul_f64 v[9:10], v[51:52], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[7:8], v[47:48], v[7:8], -v[9:10] v_mul_f64 v[7:8], v[7:8], s[34:35] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[5:6], v[5:6], s[36:37], -v[7:8] v_add_co_u32 v7, vcc_lo, s10, v25 v_add_co_ci_u32_e32 v8, vcc_lo, s11, v26, vcc_lo v_add_co_u32 v9, vcc_lo, s10, v29 v_add_co_ci_u32_e32 v10, vcc_lo, s11, v30, vcc_lo s_clause 0x1 global_load_b64 v[7:8], v[7:8], off global_load_b64 v[9:10], v[9:10], off s_waitcnt vmcnt(0) v_mul_f64 v[9:10], v[55:56], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[7:8], v[49:50], v[7:8], -v[9:10] v_fma_f64 v[5:6], v[7:8], s[30:31], v[5:6] v_add_co_u32 v7, vcc_lo, s10, v33 v_add_co_ci_u32_e32 v8, vcc_lo, s11, v34, vcc_lo v_add_co_u32 v9, vcc_lo, s10, v37 v_add_co_ci_u32_e32 v10, vcc_lo, s11, v38, vcc_lo s_clause 0x1 global_load_b64 v[7:8], v[7:8], off global_load_b64 v[9:10], v[9:10], off s_waitcnt vmcnt(0) v_mul_f64 v[9:10], v[59:60], v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[7:8], v[53:54], v[7:8], -v[9:10] v_fma_f64 v[5:6], v[7:8], s[0:1], v[5:6] v_add_co_u32 v7, vcc_lo, s18, v0 v_add_co_ci_u32_e32 v8, vcc_lo, s19, v1, vcc_lo global_load_b64 v[9:10], v[7:8], off s_waitcnt vmcnt(0) v_fma_f64 v[5:6], -v[5:6], s[20:21], v[9:10] global_store_b64 v[7:8], v[5:6], off v_add_nc_u32_e32 v6, s38, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[4:5], null, v6, s33, v[2:3] v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], 3, v[4:5] v_mad_u64_u32 v[10:11], null, v13, s38, v[3:4] v_add_co_u32 v6, vcc_lo, s28, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_co_ci_u32_e32 v7, vcc_lo, s29, v5, vcc_lo v_add_co_u32 v8, vcc_lo, s26, v4 v_mad_u64_u32 v[13:14], null, v10, s33, v[2:3] v_add_co_ci_u32_e32 v9, vcc_lo, s27, v5, vcc_lo global_load_b64 v[6:7], v[6:7], off global_load_b64 v[8:9], v[8:9], off v_ashrrev_i32_e32 v14, 31, v13 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[10:11], 3, v[13:14] v_add_co_u32 v13, vcc_lo, s28, v10 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v14, vcc_lo, s29, v11, vcc_lo v_add_co_u32 v15, vcc_lo, s26, v10 v_add_co_ci_u32_e32 v16, vcc_lo, s27, v11, vcc_lo v_add_co_u32 v4, vcc_lo, s2, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo v_add_co_u32 v10, vcc_lo, s2, v10 v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo global_load_b64 v[13:14], v[13:14], off global_load_b64 v[15:16], v[15:16], off s_clause 0x1 global_load_b64 v[4:5], v[4:5], off global_load_b64 v[10:11], v[10:11], off s_waitcnt vmcnt(2) v_mul_f64 v[13:14], v[13:14], v[15:16] s_waitcnt vmcnt(0) v_mul_f64 v[10:11], v[15:16], v[10:11] v_add_nc_u32_e32 v15, -2, v12 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[6:7], v[6:7], v[8:9], -v[13:14] v_fma_f64 v[4:5], v[8:9], v[4:5], -v[10:11] v_add_nc_u32_e32 v8, 2, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[4:5], v[6:7], v[4:5] v_mad_u64_u32 v[6:7], null, v8, s38, v[3:4] v_mad_u64_u32 v[13:14], null, v15, s38, v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[7:8], null, v6, s33, v[2:3] v_mad_u64_u32 v[14:15], null, v13, s33, v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v8, 31, v7 v_ashrrev_i32_e32 v15, 31, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[8:9], 3, v[7:8] v_lshlrev_b64 v[13:14], 3, v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, s28, v8 v_add_co_ci_u32_e32 v7, vcc_lo, s29, v9, vcc_lo global_load_b64 v[10:11], v[6:7], off v_add_co_u32 v6, vcc_lo, s26, v8 v_add_co_ci_u32_e32 v7, vcc_lo, s27, v9, vcc_lo v_add_co_u32 v15, vcc_lo, s28, v13 v_add_co_ci_u32_e32 v16, vcc_lo, s29, v14, vcc_lo v_add_co_u32 v17, vcc_lo, s26, v13 v_add_co_ci_u32_e32 v18, vcc_lo, s27, v14, vcc_lo v_add_co_u32 v8, vcc_lo, s2, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo v_add_co_u32 v13, vcc_lo, s2, v13 v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo global_load_b64 v[15:16], v[15:16], off global_load_b64 v[17:18], v[17:18], off s_clause 0x1 global_load_b64 v[8:9], v[8:9], off global_load_b64 v[13:14], v[13:14], off global_load_b64 v[6:7], v[6:7], off s_waitcnt vmcnt(3) v_mul_f64 v[15:16], v[15:16], v[17:18] s_waitcnt vmcnt(1) v_mul_f64 v[13:14], v[17:18], v[13:14] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[10:11], v[10:11], v[6:7], -v[15:16] v_add_nc_u32_e32 v15, -3, v12 v_fma_f64 v[6:7], v[6:7], v[8:9], -v[13:14] v_add_nc_u32_e32 v8, 3, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[10:11], v[6:7] v_mul_f64 v[6:7], v[6:7], s[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[4:5], v[4:5], s[36:37], -v[6:7] v_mad_u64_u32 v[6:7], null, v8, s38, v[3:4] v_mad_u64_u32 v[13:14], null, v15, s38, v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[7:8], null, v6, s33, v[2:3] v_mad_u64_u32 v[14:15], null, v13, s33, v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v8, 31, v7 v_ashrrev_i32_e32 v15, 31, v14 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[6:7], 3, v[7:8] v_lshlrev_b64 v[13:14], 3, v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v8, vcc_lo, s28, v6 v_add_co_ci_u32_e32 v9, vcc_lo, s29, v7, vcc_lo v_add_co_u32 v10, vcc_lo, s26, v6 v_add_co_ci_u32_e32 v11, vcc_lo, s27, v7, vcc_lo v_add_co_u32 v15, vcc_lo, s28, v13 v_add_co_ci_u32_e32 v16, vcc_lo, s29, v14, vcc_lo v_add_co_u32 v17, vcc_lo, s26, v13 v_add_co_ci_u32_e32 v18, vcc_lo, s27, v14, vcc_lo v_add_co_u32 v6, vcc_lo, s2, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo v_add_co_u32 v13, vcc_lo, s2, v13 v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo global_load_b64 v[15:16], v[15:16], off global_load_b64 v[17:18], v[17:18], off global_load_b64 v[8:9], v[8:9], off global_load_b64 v[13:14], v[13:14], off global_load_b64 v[10:11], v[10:11], off global_load_b64 v[6:7], v[6:7], off s_waitcnt vmcnt(4) v_mul_f64 v[15:16], v[15:16], v[17:18] s_waitcnt vmcnt(2) v_mul_f64 v[13:14], v[17:18], v[13:14] s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[8:9], v[8:9], v[10:11], -v[15:16] s_waitcnt vmcnt(0) v_fma_f64 v[6:7], v[10:11], v[6:7], -v[13:14] v_add_nc_u32_e32 v14, -4, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[6:7], v[8:9], v[6:7] v_add_nc_u32_e32 v8, 4, v12 v_fma_f64 v[4:5], v[6:7], s[30:31], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[6:7], null, v8, s38, v[3:4] v_mad_u64_u32 v[12:13], null, v14, s38, v[3:4] v_mad_u64_u32 v[7:8], null, v6, s33, v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[13:14], null, v12, s33, v[2:3] v_ashrrev_i32_e32 v8, 31, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v14, 31, v13 v_lshlrev_b64 v[6:7], 3, v[7:8] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[2:3], 3, v[13:14] v_add_co_u32 v8, vcc_lo, s28, v6 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v9, vcc_lo, s29, v7, vcc_lo v_add_co_u32 v10, vcc_lo, s26, v6 v_add_co_ci_u32_e32 v11, vcc_lo, s27, v7, vcc_lo v_add_co_u32 v12, vcc_lo, s28, v2 v_add_co_ci_u32_e32 v13, vcc_lo, s29, v3, vcc_lo v_add_co_u32 v14, vcc_lo, s26, v2 v_add_co_ci_u32_e32 v15, vcc_lo, s27, v3, vcc_lo v_add_co_u32 v6, vcc_lo, s2, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_load_b64 v[12:13], v[12:13], off global_load_b64 v[14:15], v[14:15], off s_clause 0x1 global_load_b64 v[6:7], v[6:7], off global_load_b64 v[2:3], v[2:3], off global_load_b64 v[8:9], v[8:9], off global_load_b64 v[10:11], v[10:11], off v_add_co_u32 v0, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo s_waitcnt vmcnt(4) v_mul_f64 v[12:13], v[12:13], v[14:15] s_waitcnt vmcnt(2) v_mul_f64 v[2:3], v[14:15], v[2:3] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[8:9], v[8:9], v[10:11], -v[12:13] v_fma_f64 v[2:3], v[10:11], v[6:7], -v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[2:3], v[8:9], v[2:3] v_fma_f64 v[2:3], v[2:3], s[0:1], v[4:5] global_load_b64 v[4:5], v[0:1], off s_waitcnt vmcnt(0) v_fma_f64 v[2:3], -v[2:3], s[22:23], v[4:5] global_store_b64 v[0:1], v[2:3], off .LBB1_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 400 .amdhsa_user_sgpr_count 13 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 1 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 61 .amdhsa_next_free_sgpr 39 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, .Lfunc_end1-_Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 3260 ; NumSgprs: 41 ; NumVgprs: 61 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 5 ; VGPRBlocks: 7 ; NumSGPRsForWavesPerEU: 41 ; NumVGPRsForWavesPerEU: 61 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 13 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2 .text .protected _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii ; -- Begin function _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .globl _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .p2align 8 .type _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii,@function _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: ; @_Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii ; %bb.0: s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x9c s_load_b32 s33, s[0:1], 0x88 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 v_bfe_u32 v4, v0, 20, 10 s_waitcnt lgkmcnt(0) s_and_b32 s4, s2, 0xffff s_lshr_b32 s2, s2, 16 s_and_b32 s3, s3, 0xffff s_mul_i32 s13, s13, s4 s_mul_i32 s14, s14, s2 s_mul_i32 s15, s15, s3 s_max_i32 s2, s13, 0 s_max_i32 s3, s14, 0 s_max_i32 s4, s15, 0 v_add_nc_u32_e32 v2, s2, v1 v_add_nc_u32_e32 v0, s3, v3 v_add_nc_u32_e32 v1, s4, v4 s_add_i32 s2, s33, -5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_min3_u32 v3, v2, v0, v1 v_max3_i32 v4, v2, v0, v1 v_cmp_lt_u32_e32 vcc_lo, 3, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_ge_i32_e64 s2, s2, v4 s_and_b32 s2, s2, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB2_2 ; %bb.1: s_clause 0x6 s_load_b64 s[2:3], s[0:1], 0x60 s_load_b128 s[24:27], s[0:1], 0x50 s_load_b64 s[28:29], s[0:1], 0x40 s_load_b256 s[12:19], s[0:1], 0x0 s_load_b256 s[4:11], s[0:1], 0x20 s_load_b128 s[20:23], s[0:1], 0x70 s_load_b32 s0, s[0:1], 0x84 v_add_nc_u32_e32 v10, -1, v1 v_add_nc_u32_e32 v16, 2, v1 v_add_nc_u32_e32 v20, -2, v1 s_mov_b32 s35, 0x3fc99999 s_brev_b32 s34, 5 v_add_nc_u32_e32 v24, 3, v1 s_mov_b32 s37, 0x3fe99999 s_mov_b32 s36, s34 v_add_nc_u32_e32 v28, -3, v1 v_add_nc_u32_e32 v32, 4, v1 s_mov_b32 s31, 0x3fa374bc s_brev_b32 s30, 6 s_mov_b32 s1, 0xbf6cac08 s_waitcnt lgkmcnt(0) v_mad_u64_u32 v[3:4], null, v1, s0, v[0:1] v_mad_u64_u32 v[8:9], null, v10, s0, v[0:1] v_mad_u64_u32 v[14:15], null, v16, s0, v[0:1] v_mad_u64_u32 v[18:19], null, v20, s0, v[0:1] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_nc_u32_e32 v6, s0, v3 v_mad_u64_u32 v[26:27], null, v28, s0, v[0:1] v_mad_u64_u32 v[9:10], null, v8, s33, v[2:3] v_mad_u64_u32 v[4:5], null, v6, s33, v[2:3] v_mad_u64_u32 v[15:16], null, v14, s33, v[2:3] v_mad_u64_u32 v[19:20], null, v18, s33, v[2:3] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_ashrrev_i32_e32 v10, 31, v9 v_mad_u64_u32 v[27:28], null, v26, s33, v[2:3] v_ashrrev_i32_e32 v5, 31, v4 v_ashrrev_i32_e32 v16, 31, v15 v_lshlrev_b64 v[8:9], 3, v[9:10] v_ashrrev_i32_e32 v20, 31, v19 v_mad_u64_u32 v[38:39], null, v3, s33, v[2:3] v_lshlrev_b64 v[4:5], 3, v[4:5] v_lshlrev_b64 v[14:15], 3, v[15:16] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_lshlrev_b64 v[18:19], 3, v[19:20] v_ashrrev_i32_e32 v28, 31, v27 v_add_co_u32 v6, vcc_lo, s10, v4 v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo v_add_co_u32 v10, vcc_lo, s10, v8 v_add_co_ci_u32_e32 v11, vcc_lo, s11, v9, vcc_lo v_add_co_u32 v16, vcc_lo, s10, v14 v_add_co_ci_u32_e32 v17, vcc_lo, s11, v15, vcc_lo v_add_co_u32 v20, vcc_lo, s10, v18 v_add_co_ci_u32_e32 v21, vcc_lo, s11, v19, vcc_lo s_clause 0x3 global_load_b64 v[6:7], v[6:7], off global_load_b64 v[10:11], v[10:11], off global_load_b64 v[16:17], v[16:17], off global_load_b64 v[20:21], v[20:21], off v_lshlrev_b64 v[26:27], 3, v[27:28] v_ashrrev_i32_e32 v39, 31, v38 s_waitcnt vmcnt(2) v_add_f64 v[12:13], v[6:7], -v[10:11] s_waitcnt vmcnt(0) v_add_f64 v[22:23], v[16:17], -v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[22:23], v[22:23], s[34:35] v_fma_f64 v[12:13], v[12:13], s[36:37], -v[22:23] v_mad_u64_u32 v[22:23], null, v24, s0, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[23:24], null, v22, s33, v[2:3] v_ashrrev_i32_e32 v24, 31, v23 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[22:23], 3, v[23:24] v_add_co_u32 v24, vcc_lo, s10, v22 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v25, vcc_lo, s11, v23, vcc_lo v_add_co_u32 v28, vcc_lo, s10, v26 v_add_co_ci_u32_e32 v29, vcc_lo, s11, v27, vcc_lo s_clause 0x1 global_load_b64 v[24:25], v[24:25], off global_load_b64 v[28:29], v[28:29], off s_waitcnt vmcnt(0) v_add_f64 v[30:31], v[24:25], -v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], v[30:31], s[30:31], v[12:13] v_mad_u64_u32 v[30:31], null, v32, s0, v[0:1] v_add_nc_u32_e32 v1, -4, v1 v_mad_u64_u32 v[34:35], null, v1, s0, v[0:1] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[31:32], null, v30, s33, v[2:3] s_mov_b32 s0, 2.0 v_mad_u64_u32 v[0:1], null, v34, s33, v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v32, 31, v31 v_lshlrev_b64 v[30:31], 3, v[31:32] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[34:35], 3, v[0:1] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v32, vcc_lo, s10, v30 v_add_co_ci_u32_e32 v33, vcc_lo, s11, v31, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v0, vcc_lo, s10, v34 v_add_co_ci_u32_e32 v1, vcc_lo, s11, v35, vcc_lo s_clause 0x1 global_load_b64 v[32:33], v[32:33], off global_load_b64 v[36:37], v[0:1], off s_waitcnt vmcnt(0) v_add_f64 v[0:1], v[32:33], -v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], v[0:1], s[0:1], v[12:13] v_lshlrev_b64 v[0:1], 3, v[38:39] v_add_co_u32 v39, vcc_lo, s12, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v40, vcc_lo, s13, v1, vcc_lo global_load_b64 v[41:42], v[39:40], off s_waitcnt vmcnt(0) v_fma_f64 v[12:13], -v[12:13], s[22:23], v[41:42] global_store_b64 v[39:40], v[12:13], off v_add_co_u32 v12, vcc_lo, s6, v4 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v5, vcc_lo v_add_co_u32 v39, vcc_lo, s26, v4 v_add_co_ci_u32_e32 v40, vcc_lo, s27, v5, vcc_lo v_add_co_u32 v41, vcc_lo, s6, v8 v_add_co_ci_u32_e32 v42, vcc_lo, s7, v9, vcc_lo v_add_co_u32 v43, vcc_lo, s26, v8 v_add_co_ci_u32_e32 v44, vcc_lo, s27, v9, vcc_lo s_clause 0x1 global_load_b64 v[41:42], v[41:42], off global_load_b64 v[12:13], v[12:13], off s_clause 0x1 global_load_b64 v[39:40], v[39:40], off global_load_b64 v[43:44], v[43:44], off s_waitcnt vmcnt(0) v_mul_f64 v[41:42], v[41:42], v[43:44] v_mul_f64 v[10:11], v[10:11], v[43:44] s_delay_alu instid0(VALU_DEP_2) v_fma_f64 v[12:13], v[12:13], v[39:40], -v[41:42] v_add_co_u32 v41, vcc_lo, s6, v14 v_add_co_ci_u32_e32 v42, vcc_lo, s7, v15, vcc_lo v_add_co_u32 v45, vcc_lo, s26, v14 v_add_co_ci_u32_e32 v46, vcc_lo, s27, v15, vcc_lo v_add_co_u32 v47, vcc_lo, s6, v18 v_add_co_ci_u32_e32 v48, vcc_lo, s7, v19, vcc_lo v_add_co_u32 v49, vcc_lo, s26, v18 v_add_co_ci_u32_e32 v50, vcc_lo, s27, v19, vcc_lo s_clause 0x1 global_load_b64 v[47:48], v[47:48], off global_load_b64 v[41:42], v[41:42], off s_clause 0x1 global_load_b64 v[45:46], v[45:46], off global_load_b64 v[49:50], v[49:50], off v_fma_f64 v[6:7], v[6:7], v[39:40], -v[10:11] s_waitcnt vmcnt(0) v_mul_f64 v[47:48], v[47:48], v[49:50] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[41:42], v[41:42], v[45:46], -v[47:48] v_mul_f64 v[41:42], v[41:42], s[34:35] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[12:13], v[12:13], s[36:37], -v[41:42] v_add_co_u32 v41, vcc_lo, s6, v22 v_add_co_ci_u32_e32 v42, vcc_lo, s7, v23, vcc_lo v_add_co_u32 v47, vcc_lo, s26, v22 v_add_co_ci_u32_e32 v48, vcc_lo, s27, v23, vcc_lo v_add_co_u32 v51, vcc_lo, s6, v26 v_add_co_ci_u32_e32 v52, vcc_lo, s7, v27, vcc_lo v_add_co_u32 v53, vcc_lo, s26, v26 v_add_co_ci_u32_e32 v54, vcc_lo, s27, v27, vcc_lo s_clause 0x1 global_load_b64 v[51:52], v[51:52], off global_load_b64 v[41:42], v[41:42], off s_clause 0x1 global_load_b64 v[47:48], v[47:48], off global_load_b64 v[53:54], v[53:54], off s_waitcnt vmcnt(0) v_mul_f64 v[51:52], v[51:52], v[53:54] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[41:42], v[41:42], v[47:48], -v[51:52] v_fma_f64 v[12:13], v[41:42], s[30:31], v[12:13] v_add_co_u32 v41, vcc_lo, s6, v30 v_add_co_ci_u32_e32 v42, vcc_lo, s7, v31, vcc_lo v_add_co_u32 v51, vcc_lo, s26, v30 v_add_co_ci_u32_e32 v52, vcc_lo, s27, v31, vcc_lo v_add_co_u32 v55, vcc_lo, s6, v34 v_add_co_ci_u32_e32 v56, vcc_lo, s7, v35, vcc_lo v_add_co_u32 v57, vcc_lo, s26, v34 v_add_co_ci_u32_e32 v58, vcc_lo, s27, v35, vcc_lo s_clause 0x1 global_load_b64 v[55:56], v[55:56], off global_load_b64 v[41:42], v[41:42], off s_clause 0x1 global_load_b64 v[51:52], v[51:52], off global_load_b64 v[57:58], v[57:58], off s_waitcnt vmcnt(0) v_mul_f64 v[55:56], v[55:56], v[57:58] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[41:42], v[41:42], v[51:52], -v[55:56] v_fma_f64 v[12:13], v[41:42], s[0:1], v[12:13] v_add_co_u32 v41, vcc_lo, s14, v0 v_add_co_ci_u32_e32 v42, vcc_lo, s15, v1, vcc_lo global_load_b64 v[55:56], v[41:42], off s_waitcnt vmcnt(0) v_fma_f64 v[12:13], -v[12:13], s[22:23], v[55:56] global_store_b64 v[41:42], v[12:13], off v_add_co_u32 v12, vcc_lo, s8, v4 v_add_co_ci_u32_e32 v13, vcc_lo, s9, v5, vcc_lo v_add_co_u32 v41, vcc_lo, s8, v8 v_add_co_ci_u32_e32 v42, vcc_lo, s9, v9, vcc_lo s_clause 0x1 global_load_b64 v[12:13], v[12:13], off global_load_b64 v[41:42], v[41:42], off s_waitcnt vmcnt(0) v_mul_f64 v[41:42], v[43:44], v[41:42] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[12:13], v[39:40], v[12:13], -v[41:42] v_add_co_u32 v41, vcc_lo, s8, v14 v_add_co_ci_u32_e32 v42, vcc_lo, s9, v15, vcc_lo v_add_co_u32 v55, vcc_lo, s8, v18 v_add_co_ci_u32_e32 v56, vcc_lo, s9, v19, vcc_lo s_clause 0x1 global_load_b64 v[41:42], v[41:42], off global_load_b64 v[55:56], v[55:56], off s_waitcnt vmcnt(0) v_mul_f64 v[55:56], v[49:50], v[55:56] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[41:42], v[45:46], v[41:42], -v[55:56] v_mul_f64 v[41:42], v[41:42], s[34:35] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[12:13], v[12:13], s[36:37], -v[41:42] v_add_co_u32 v41, vcc_lo, s8, v22 v_add_co_ci_u32_e32 v42, vcc_lo, s9, v23, vcc_lo v_add_co_u32 v55, vcc_lo, s8, v26 v_add_co_ci_u32_e32 v56, vcc_lo, s9, v27, vcc_lo s_clause 0x1 global_load_b64 v[41:42], v[41:42], off global_load_b64 v[55:56], v[55:56], off s_waitcnt vmcnt(0) v_mul_f64 v[55:56], v[53:54], v[55:56] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[41:42], v[47:48], v[41:42], -v[55:56] v_fma_f64 v[12:13], v[41:42], s[30:31], v[12:13] v_add_co_u32 v41, vcc_lo, s8, v30 v_add_co_ci_u32_e32 v42, vcc_lo, s9, v31, vcc_lo v_add_co_u32 v55, vcc_lo, s8, v34 v_add_co_ci_u32_e32 v56, vcc_lo, s9, v35, vcc_lo s_clause 0x1 global_load_b64 v[41:42], v[41:42], off global_load_b64 v[55:56], v[55:56], off s_waitcnt vmcnt(0) v_mul_f64 v[55:56], v[57:58], v[55:56] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[41:42], v[51:52], v[41:42], -v[55:56] v_fma_f64 v[12:13], v[41:42], s[0:1], v[12:13] v_add_co_u32 v41, vcc_lo, s16, v0 v_add_co_ci_u32_e32 v42, vcc_lo, s17, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s2, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo v_add_co_u32 v8, vcc_lo, s2, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo global_load_b64 v[4:5], v[4:5], off global_load_b64 v[55:56], v[41:42], off global_load_b64 v[8:9], v[8:9], off s_waitcnt vmcnt(1) v_fma_f64 v[12:13], -v[12:13], s[22:23], v[55:56] s_waitcnt vmcnt(0) v_add_f64 v[4:5], v[4:5], -v[8:9] v_add_co_u32 v8, vcc_lo, s2, v14 v_add_co_ci_u32_e32 v9, vcc_lo, s3, v15, vcc_lo v_add_co_u32 v10, vcc_lo, s2, v18 v_add_co_ci_u32_e32 v11, vcc_lo, s3, v19, vcc_lo s_clause 0x1 global_load_b64 v[8:9], v[8:9], off global_load_b64 v[10:11], v[10:11], off global_store_b64 v[41:42], v[12:13], off v_add_nc_u32_e32 v12, -1, v3 v_add_f64 v[4:5], v[6:7], v[4:5] v_mul_f64 v[6:7], v[20:21], v[49:50] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], v[16:17], v[45:46], -v[6:7] s_waitcnt vmcnt(0) v_add_f64 v[8:9], v[8:9], -v[10:11] v_add_f64 v[6:7], v[6:7], v[8:9] v_add_co_u32 v8, vcc_lo, s2, v22 v_add_co_ci_u32_e32 v9, vcc_lo, s3, v23, vcc_lo v_add_co_u32 v10, vcc_lo, s2, v26 v_add_co_ci_u32_e32 v11, vcc_lo, s3, v27, vcc_lo s_clause 0x1 global_load_b64 v[8:9], v[8:9], off global_load_b64 v[10:11], v[10:11], off v_mul_f64 v[6:7], v[6:7], s[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[4:5], v[4:5], s[36:37], -v[6:7] v_mul_f64 v[6:7], v[28:29], v[53:54] v_fma_f64 v[6:7], v[24:25], v[47:48], -v[6:7] s_waitcnt vmcnt(0) v_add_f64 v[8:9], v[8:9], -v[10:11] s_delay_alu instid0(VALU_DEP_1) v_add_f64 v[6:7], v[6:7], v[8:9] v_add_co_u32 v8, vcc_lo, s2, v30 v_add_co_ci_u32_e32 v9, vcc_lo, s3, v31, vcc_lo v_add_co_u32 v10, vcc_lo, s2, v34 v_add_co_ci_u32_e32 v11, vcc_lo, s3, v35, vcc_lo s_clause 0x1 global_load_b64 v[8:9], v[8:9], off global_load_b64 v[10:11], v[10:11], off v_fma_f64 v[4:5], v[6:7], s[30:31], v[4:5] v_mul_f64 v[6:7], v[36:37], v[57:58] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], v[32:33], v[51:52], -v[6:7] s_waitcnt vmcnt(0) v_add_f64 v[8:9], v[8:9], -v[10:11] v_mad_u64_u32 v[10:11], null, v12, s33, v[2:3] v_ashrrev_i32_e32 v11, 31, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[10:11], 3, v[10:11] v_add_f64 v[6:7], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[4:5], v[6:7], s[0:1], v[4:5] v_add_co_u32 v6, vcc_lo, s18, v0 v_add_co_ci_u32_e32 v7, vcc_lo, s19, v1, vcc_lo global_load_b64 v[8:9], v[6:7], off s_waitcnt vmcnt(0) v_fma_f64 v[4:5], -v[4:5], s[22:23], v[8:9] global_store_b64 v[6:7], v[4:5], off v_add_nc_u32_e32 v4, s33, v38 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v5, 31, v4 v_lshlrev_b64 v[6:7], 3, v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, s28, v6 v_add_co_ci_u32_e32 v5, vcc_lo, s29, v7, vcc_lo global_load_b64 v[8:9], v[4:5], off v_add_co_u32 v4, vcc_lo, s24, v6 v_add_co_ci_u32_e32 v5, vcc_lo, s25, v7, vcc_lo v_add_co_u32 v12, vcc_lo, s28, v10 v_add_co_ci_u32_e32 v13, vcc_lo, s29, v11, vcc_lo v_add_co_u32 v14, vcc_lo, s24, v10 v_add_co_ci_u32_e32 v15, vcc_lo, s25, v11, vcc_lo v_add_co_u32 v6, vcc_lo, s2, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo v_add_co_u32 v10, vcc_lo, s2, v10 v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo global_load_b64 v[12:13], v[12:13], off global_load_b64 v[14:15], v[14:15], off s_clause 0x1 global_load_b64 v[6:7], v[6:7], off global_load_b64 v[10:11], v[10:11], off global_load_b64 v[4:5], v[4:5], off s_waitcnt vmcnt(3) v_mul_f64 v[12:13], v[12:13], v[14:15] s_waitcnt vmcnt(1) v_mul_f64 v[10:11], v[14:15], v[10:11] v_add_nc_u32_e32 v14, -2, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[8:9], v[8:9], v[4:5], -v[12:13] v_mad_u64_u32 v[12:13], null, v14, s33, v[2:3] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[4:5], v[4:5], v[6:7], -v[10:11] v_ashrrev_i32_e32 v13, 31, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[12:13], 3, v[12:13] v_add_f64 v[4:5], v[8:9], v[4:5] v_add_nc_u32_e32 v8, 2, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, v8, s33, v[2:3] v_ashrrev_i32_e32 v7, 31, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 3, v[6:7] v_add_co_u32 v8, vcc_lo, s28, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v9, vcc_lo, s29, v7, vcc_lo v_add_co_u32 v10, vcc_lo, s24, v6 v_add_co_ci_u32_e32 v11, vcc_lo, s25, v7, vcc_lo v_add_co_u32 v14, vcc_lo, s28, v12 v_add_co_ci_u32_e32 v15, vcc_lo, s29, v13, vcc_lo v_add_co_u32 v16, vcc_lo, s24, v12 v_add_co_ci_u32_e32 v17, vcc_lo, s25, v13, vcc_lo v_add_co_u32 v6, vcc_lo, s2, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo v_add_co_u32 v12, vcc_lo, s2, v12 v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo global_load_b64 v[14:15], v[14:15], off global_load_b64 v[16:17], v[16:17], off global_load_b64 v[8:9], v[8:9], off global_load_b64 v[12:13], v[12:13], off global_load_b64 v[10:11], v[10:11], off global_load_b64 v[6:7], v[6:7], off s_waitcnt vmcnt(4) v_mul_f64 v[14:15], v[14:15], v[16:17] s_waitcnt vmcnt(2) v_mul_f64 v[12:13], v[16:17], v[12:13] s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[8:9], v[8:9], v[10:11], -v[14:15] v_add_nc_u32_e32 v14, -3, v3 s_waitcnt vmcnt(0) v_fma_f64 v[6:7], v[10:11], v[6:7], -v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[12:13], null, v14, s33, v[2:3] v_ashrrev_i32_e32 v13, 31, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[12:13], 3, v[12:13] v_add_f64 v[6:7], v[8:9], v[6:7] v_add_nc_u32_e32 v8, 3, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[6:7], v[6:7], s[34:35] v_fma_f64 v[4:5], v[4:5], s[36:37], -v[6:7] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, v8, s33, v[2:3] v_ashrrev_i32_e32 v7, 31, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 3, v[6:7] v_add_co_u32 v8, vcc_lo, s28, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v9, vcc_lo, s29, v7, vcc_lo v_add_co_u32 v10, vcc_lo, s24, v6 v_add_co_ci_u32_e32 v11, vcc_lo, s25, v7, vcc_lo v_add_co_u32 v14, vcc_lo, s28, v12 v_add_co_ci_u32_e32 v15, vcc_lo, s29, v13, vcc_lo v_add_co_u32 v16, vcc_lo, s24, v12 v_add_co_ci_u32_e32 v17, vcc_lo, s25, v13, vcc_lo v_add_co_u32 v6, vcc_lo, s2, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo v_add_co_u32 v12, vcc_lo, s2, v12 v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo global_load_b64 v[14:15], v[14:15], off global_load_b64 v[16:17], v[16:17], off global_load_b64 v[8:9], v[8:9], off global_load_b64 v[12:13], v[12:13], off global_load_b64 v[10:11], v[10:11], off global_load_b64 v[6:7], v[6:7], off s_waitcnt vmcnt(4) v_mul_f64 v[14:15], v[14:15], v[16:17] s_waitcnt vmcnt(2) v_mul_f64 v[12:13], v[16:17], v[12:13] s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[8:9], v[8:9], v[10:11], -v[14:15] s_waitcnt vmcnt(0) v_fma_f64 v[6:7], v[10:11], v[6:7], -v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[6:7], v[8:9], v[6:7] v_add_nc_u32_e32 v8, 4, v3 v_fma_f64 v[4:5], v[6:7], s[30:31], v[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[6:7], null, v8, s33, v[2:3] v_add_nc_u32_e32 v3, -4, v3 v_mad_u64_u32 v[12:13], null, v3, s33, v[2:3] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v7, 31, v6 v_lshlrev_b64 v[6:7], 3, v[6:7] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v13, 31, v12 v_add_co_u32 v8, vcc_lo, s28, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[2:3], 3, v[12:13] v_add_co_ci_u32_e32 v9, vcc_lo, s29, v7, vcc_lo v_add_co_u32 v10, vcc_lo, s24, v6 v_add_co_ci_u32_e32 v11, vcc_lo, s25, v7, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v12, vcc_lo, s28, v2 v_add_co_ci_u32_e32 v13, vcc_lo, s29, v3, vcc_lo v_add_co_u32 v14, vcc_lo, s24, v2 v_add_co_ci_u32_e32 v15, vcc_lo, s25, v3, vcc_lo v_add_co_u32 v6, vcc_lo, s2, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_load_b64 v[12:13], v[12:13], off global_load_b64 v[14:15], v[14:15], off s_clause 0x1 global_load_b64 v[6:7], v[6:7], off global_load_b64 v[2:3], v[2:3], off global_load_b64 v[8:9], v[8:9], off global_load_b64 v[10:11], v[10:11], off v_add_co_u32 v0, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo s_waitcnt vmcnt(4) v_mul_f64 v[12:13], v[12:13], v[14:15] s_waitcnt vmcnt(2) v_mul_f64 v[2:3], v[14:15], v[2:3] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[8:9], v[8:9], v[10:11], -v[12:13] v_fma_f64 v[2:3], v[10:11], v[6:7], -v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[2:3], v[8:9], v[2:3] v_fma_f64 v[2:3], v[2:3], s[0:1], v[4:5] global_load_b64 v[4:5], v[0:1], off s_waitcnt vmcnt(0) v_fma_f64 v[2:3], -v[2:3], s[20:21], v[4:5] global_store_b64 v[0:1], v[2:3], off .LBB2_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 400 .amdhsa_user_sgpr_count 13 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 1 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 59 .amdhsa_next_free_sgpr 38 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, .Lfunc_end2-_Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 3252 ; NumSgprs: 40 ; NumVgprs: 59 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 4 ; VGPRBlocks: 7 ; NumSGPRsForWavesPerEU: 40 ; NumVGPRsForWavesPerEU: 59 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 13 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .actual_access: write_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 88 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 96 .size: 8 .value_kind: global_buffer - .offset: 104 .size: 8 .value_kind: by_value - .offset: 112 .size: 8 .value_kind: by_value - .offset: 120 .size: 8 .value_kind: by_value - .offset: 128 .size: 4 .value_kind: by_value - .offset: 132 .size: 4 .value_kind: by_value - .offset: 136 .size: 4 .value_kind: by_value - .offset: 144 .size: 4 .value_kind: hidden_block_count_x - .offset: 148 .size: 4 .value_kind: hidden_block_count_y - .offset: 152 .size: 4 .value_kind: hidden_block_count_z - .offset: 156 .size: 2 .value_kind: hidden_group_size_x - .offset: 158 .size: 2 .value_kind: hidden_group_size_y - .offset: 160 .size: 2 .value_kind: hidden_group_size_z - .offset: 162 .size: 2 .value_kind: hidden_remainder_x - .offset: 164 .size: 2 .value_kind: hidden_remainder_y - .offset: 166 .size: 2 .value_kind: hidden_remainder_z - .offset: 184 .size: 8 .value_kind: hidden_global_offset_x - .offset: 192 .size: 8 .value_kind: hidden_global_offset_y - .offset: 200 .size: 8 .value_kind: hidden_global_offset_z - .offset: 208 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 400 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .private_segment_fixed_size: 0 .sgpr_count: 22 .sgpr_spill_count: 0 .symbol: _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 92 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 88 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 96 .size: 8 .value_kind: global_buffer - .offset: 104 .size: 8 .value_kind: by_value - .offset: 112 .size: 8 .value_kind: by_value - .offset: 120 .size: 8 .value_kind: by_value - .offset: 128 .size: 4 .value_kind: by_value - .offset: 132 .size: 4 .value_kind: by_value - .offset: 136 .size: 4 .value_kind: by_value - .offset: 144 .size: 4 .value_kind: hidden_block_count_x - .offset: 148 .size: 4 .value_kind: hidden_block_count_y - .offset: 152 .size: 4 .value_kind: hidden_block_count_z - .offset: 156 .size: 2 .value_kind: hidden_group_size_x - .offset: 158 .size: 2 .value_kind: hidden_group_size_y - .offset: 160 .size: 2 .value_kind: hidden_group_size_z - .offset: 162 .size: 2 .value_kind: hidden_remainder_x - .offset: 164 .size: 2 .value_kind: hidden_remainder_y - .offset: 166 .size: 2 .value_kind: hidden_remainder_z - .offset: 184 .size: 8 .value_kind: hidden_global_offset_x - .offset: 192 .size: 8 .value_kind: hidden_global_offset_y - .offset: 200 .size: 8 .value_kind: hidden_global_offset_z - .offset: 208 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 400 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .private_segment_fixed_size: 0 .sgpr_count: 41 .sgpr_spill_count: 0 .symbol: _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 61 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 88 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 96 .size: 8 .value_kind: global_buffer - .offset: 104 .size: 8 .value_kind: by_value - .offset: 112 .size: 8 .value_kind: by_value - .offset: 120 .size: 8 .value_kind: by_value - .offset: 128 .size: 4 .value_kind: by_value - .offset: 132 .size: 4 .value_kind: by_value - .offset: 136 .size: 4 .value_kind: by_value - .offset: 144 .size: 4 .value_kind: hidden_block_count_x - .offset: 148 .size: 4 .value_kind: hidden_block_count_y - .offset: 152 .size: 4 .value_kind: hidden_block_count_z - .offset: 156 .size: 2 .value_kind: hidden_group_size_x - .offset: 158 .size: 2 .value_kind: hidden_group_size_y - .offset: 160 .size: 2 .value_kind: hidden_group_size_z - .offset: 162 .size: 2 .value_kind: hidden_remainder_x - .offset: 164 .size: 2 .value_kind: hidden_remainder_y - .offset: 166 .size: 2 .value_kind: hidden_remainder_z - .offset: 184 .size: 8 .value_kind: hidden_global_offset_x - .offset: 192 .size: 8 .value_kind: hidden_global_offset_y - .offset: 200 .size: 8 .value_kind: hidden_global_offset_z - .offset: 208 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 400 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .private_segment_fixed_size: 0 .sgpr_count: 40 .sgpr_spill_count: 0 .symbol: _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 59 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "252990da4bcd9cf61d055f084f0bb3d490c0eea4.hip" .globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc .p2align 4, 0x90 .type _Z11check_errorPKc,@function _Z11check_errorPKc: # @_Z11check_errorPKc .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq %rdi, %rbx callq hipGetLastError testl %eax, %eax je .LBB0_1 # %bb.2: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movq %rbx, %rsi movq %rax, %rdx xorl %eax, %eax popq %rbx .cfi_def_cfa_offset 8 jmp printf # TAILCALL .LBB0_1: .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc .cfi_endproc # -- End function .globl _Z24__device_stub__hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii # -- Begin function _Z24__device_stub__hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .p2align 4, 0x90 .type _Z24__device_stub__hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii,@function _Z24__device_stub__hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: # @_Z24__device_stub__hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .cfi_startproc # %bb.0: subq $280, %rsp # imm = 0x118 .cfi_def_cfa_offset 288 movq %rdi, 120(%rsp) movq %rsi, 112(%rsp) movq %rdx, 104(%rsp) movq %rcx, 96(%rsp) movq %r8, 88(%rsp) movq %r9, 80(%rsp) movsd %xmm0, 72(%rsp) movsd %xmm1, 64(%rsp) movsd %xmm2, 56(%rsp) leaq 120(%rsp), %rax movq %rax, 128(%rsp) leaq 112(%rsp), %rax movq %rax, 136(%rsp) leaq 104(%rsp), %rax movq %rax, 144(%rsp) leaq 96(%rsp), %rax movq %rax, 152(%rsp) leaq 88(%rsp), %rax movq %rax, 160(%rsp) leaq 80(%rsp), %rax movq %rax, 168(%rsp) leaq 288(%rsp), %rax movq %rax, 176(%rsp) leaq 296(%rsp), %rax movq %rax, 184(%rsp) leaq 304(%rsp), %rax movq %rax, 192(%rsp) leaq 312(%rsp), %rax movq %rax, 200(%rsp) leaq 320(%rsp), %rax movq %rax, 208(%rsp) leaq 328(%rsp), %rax movq %rax, 216(%rsp) leaq 336(%rsp), %rax movq %rax, 224(%rsp) leaq 72(%rsp), %rax movq %rax, 232(%rsp) leaq 64(%rsp), %rax movq %rax, 240(%rsp) leaq 56(%rsp), %rax movq %rax, 248(%rsp) leaq 344(%rsp), %rax movq %rax, 256(%rsp) leaq 352(%rsp), %rax movq %rax, 264(%rsp) leaq 360(%rsp), %rax movq %rax, 272(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 128(%rsp), %r9 movl $_Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $296, %rsp # imm = 0x128 .cfi_adjust_cfa_offset -296 retq .Lfunc_end1: .size _Z24__device_stub__hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, .Lfunc_end1-_Z24__device_stub__hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .cfi_endproc # -- End function .globl _Z24__device_stub__hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii # -- Begin function _Z24__device_stub__hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .p2align 4, 0x90 .type _Z24__device_stub__hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii,@function _Z24__device_stub__hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: # @_Z24__device_stub__hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .cfi_startproc # %bb.0: subq $280, %rsp # imm = 0x118 .cfi_def_cfa_offset 288 movq %rdi, 120(%rsp) movq %rsi, 112(%rsp) movq %rdx, 104(%rsp) movq %rcx, 96(%rsp) movq %r8, 88(%rsp) movq %r9, 80(%rsp) movsd %xmm0, 72(%rsp) movsd %xmm1, 64(%rsp) movsd %xmm2, 56(%rsp) leaq 120(%rsp), %rax movq %rax, 128(%rsp) leaq 112(%rsp), %rax movq %rax, 136(%rsp) leaq 104(%rsp), %rax movq %rax, 144(%rsp) leaq 96(%rsp), %rax movq %rax, 152(%rsp) leaq 88(%rsp), %rax movq %rax, 160(%rsp) leaq 80(%rsp), %rax movq %rax, 168(%rsp) leaq 288(%rsp), %rax movq %rax, 176(%rsp) leaq 296(%rsp), %rax movq %rax, 184(%rsp) leaq 304(%rsp), %rax movq %rax, 192(%rsp) leaq 312(%rsp), %rax movq %rax, 200(%rsp) leaq 320(%rsp), %rax movq %rax, 208(%rsp) leaq 328(%rsp), %rax movq %rax, 216(%rsp) leaq 336(%rsp), %rax movq %rax, 224(%rsp) leaq 72(%rsp), %rax movq %rax, 232(%rsp) leaq 64(%rsp), %rax movq %rax, 240(%rsp) leaq 56(%rsp), %rax movq %rax, 248(%rsp) leaq 344(%rsp), %rax movq %rax, 256(%rsp) leaq 352(%rsp), %rax movq %rax, 264(%rsp) leaq 360(%rsp), %rax movq %rax, 272(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 128(%rsp), %r9 movl $_Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $296, %rsp # imm = 0x128 .cfi_adjust_cfa_offset -296 retq .Lfunc_end2: .size _Z24__device_stub__hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, .Lfunc_end2-_Z24__device_stub__hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .cfi_endproc # -- End function .globl _Z24__device_stub__hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii # -- Begin function _Z24__device_stub__hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .p2align 4, 0x90 .type _Z24__device_stub__hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii,@function _Z24__device_stub__hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: # @_Z24__device_stub__hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .cfi_startproc # %bb.0: subq $280, %rsp # imm = 0x118 .cfi_def_cfa_offset 288 movq %rdi, 120(%rsp) movq %rsi, 112(%rsp) movq %rdx, 104(%rsp) movq %rcx, 96(%rsp) movq %r8, 88(%rsp) movq %r9, 80(%rsp) movsd %xmm0, 72(%rsp) movsd %xmm1, 64(%rsp) movsd %xmm2, 56(%rsp) leaq 120(%rsp), %rax movq %rax, 128(%rsp) leaq 112(%rsp), %rax movq %rax, 136(%rsp) leaq 104(%rsp), %rax movq %rax, 144(%rsp) leaq 96(%rsp), %rax movq %rax, 152(%rsp) leaq 88(%rsp), %rax movq %rax, 160(%rsp) leaq 80(%rsp), %rax movq %rax, 168(%rsp) leaq 288(%rsp), %rax movq %rax, 176(%rsp) leaq 296(%rsp), %rax movq %rax, 184(%rsp) leaq 304(%rsp), %rax movq %rax, 192(%rsp) leaq 312(%rsp), %rax movq %rax, 200(%rsp) leaq 320(%rsp), %rax movq %rax, 208(%rsp) leaq 328(%rsp), %rax movq %rax, 216(%rsp) leaq 336(%rsp), %rax movq %rax, 224(%rsp) leaq 72(%rsp), %rax movq %rax, 232(%rsp) leaq 64(%rsp), %rax movq %rax, 240(%rsp) leaq 56(%rsp), %rax movq %rax, 248(%rsp) leaq 344(%rsp), %rax movq %rax, 256(%rsp) leaq 352(%rsp), %rax movq %rax, 264(%rsp) leaq 360(%rsp), %rax movq %rax, 272(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 128(%rsp), %r9 movl $_Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $296, %rsp # imm = 0x128 .cfi_adjust_cfa_offset -296 retq .Lfunc_end3: .size _Z24__device_stub__hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, .Lfunc_end3-_Z24__device_stub__hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function offload .LCPI4_0: .quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7 .text .globl offload .p2align 4, 0x90 .type offload,@function offload: # @offload .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $616, %rsp # imm = 0x268 .cfi_def_cfa_offset 672 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movsd %xmm2, 368(%rsp) # 8-byte Spill movsd %xmm1, 360(%rsp) # 8-byte Spill movsd %xmm0, 352(%rsp) # 8-byte Spill movq %r9, %rbx movq %r8, 576(%rsp) # 8-byte Spill movq %rcx, 568(%rsp) # 8-byte Spill movq %rdx, 560(%rsp) # 8-byte Spill movq %rsi, 552(%rsp) # 8-byte Spill movq %rdi, 544(%rsp) # 8-byte Spill movslq 744(%rsp), %r15 movslq 736(%rsp), %r12 movslq 728(%rsp), %r13 movq %r13, %rsi imulq %r12, %rsi imulq %r15, %rsi shlq $3, %rsi leaq 56(%rsp), %rdi movq %rsi, (%rsp) # 8-byte Spill callq hipMalloc callq hipGetLastError testl %eax, %eax je .LBB4_2 # %bb.1: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.1, %esi movq %rax, %rdx xorl %eax, %eax callq printf .LBB4_2: # %_Z11check_errorPKc.exit leaq 48(%rsp), %rdi movq (%rsp), %rsi # 8-byte Reload callq hipMalloc callq hipGetLastError testl %eax, %eax je .LBB4_4 # %bb.3: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.2, %esi movq %rax, %rdx xorl %eax, %eax callq printf .LBB4_4: # %_Z11check_errorPKc.exit123 leaq 40(%rsp), %rdi movq (%rsp), %rsi # 8-byte Reload callq hipMalloc callq hipGetLastError testl %eax, %eax je .LBB4_6 # %bb.5: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.3, %esi movq %rax, %rdx xorl %eax, %eax callq printf .LBB4_6: # %_Z11check_errorPKc.exit125 leaq 32(%rsp), %rdi movq (%rsp), %rsi # 8-byte Reload callq hipMalloc callq hipGetLastError testl %eax, %eax je .LBB4_8 # %bb.7: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.4, %esi movq %rax, %rdx xorl %eax, %eax callq printf .LBB4_8: # %_Z11check_errorPKc.exit127 leaq 24(%rsp), %rdi movq (%rsp), %rsi # 8-byte Reload callq hipMalloc callq hipGetLastError testl %eax, %eax je .LBB4_10 # %bb.9: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.5, %esi movq %rax, %rdx xorl %eax, %eax callq printf .LBB4_10: # %_Z11check_errorPKc.exit129 leaq 120(%rsp), %rdi movq (%rsp), %rsi # 8-byte Reload callq hipMalloc callq hipGetLastError testl %eax, %eax je .LBB4_12 # %bb.11: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.6, %esi movq %rax, %rdx xorl %eax, %eax callq printf .LBB4_12: # %_Z11check_errorPKc.exit131 movq 672(%rsp), %r14 movq 120(%rsp), %rdi movq %rbx, %rsi movq (%rsp), %rbx # 8-byte Reload movq %rbx, %rdx movl $1, %ecx callq hipMemcpy leaq 112(%rsp), %rdi movq %rbx, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax je .LBB4_14 # %bb.13: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.7, %esi movq %rax, %rdx xorl %eax, %eax callq printf .LBB4_14: # %_Z11check_errorPKc.exit133 movq 680(%rsp), %rbx movq 112(%rsp), %rdi movq %r14, %rsi movq (%rsp), %r14 # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 104(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax je .LBB4_16 # %bb.15: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.8, %esi movq %rax, %rdx xorl %eax, %eax callq printf .LBB4_16: # %_Z11check_errorPKc.exit135 movq 688(%rsp), %r14 movq 104(%rsp), %rdi movq %rbx, %rsi movq (%rsp), %rbx # 8-byte Reload movq %rbx, %rdx movl $1, %ecx callq hipMemcpy leaq 96(%rsp), %rdi movq %rbx, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax je .LBB4_18 # %bb.17: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.9, %esi movq %rax, %rdx xorl %eax, %eax callq printf .LBB4_18: # %_Z11check_errorPKc.exit137 movq 696(%rsp), %rbx movq 96(%rsp), %rdi movq %r14, %rsi movq (%rsp), %r14 # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 88(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax je .LBB4_20 # %bb.19: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.10, %esi movq %rax, %rdx xorl %eax, %eax callq printf .LBB4_20: # %_Z11check_errorPKc.exit139 movq 704(%rsp), %r14 movq 88(%rsp), %rdi movq %rbx, %rsi movq (%rsp), %rbx # 8-byte Reload movq %rbx, %rdx movl $1, %ecx callq hipMemcpy leaq 80(%rsp), %rdi movq %rbx, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax je .LBB4_22 # %bb.21: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.11, %esi movq %rax, %rdx xorl %eax, %eax callq printf .LBB4_22: # %_Z11check_errorPKc.exit141 movq 712(%rsp), %rbx movq 80(%rsp), %rdi movq %r14, %rsi movq (%rsp), %r14 # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq 72(%rsp), %rdi movq %r14, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax je .LBB4_24 # %bb.23: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.12, %esi movq %rax, %rdx xorl %eax, %eax callq printf .LBB4_24: # %_Z11check_errorPKc.exit143 movq 720(%rsp), %r14 movq 72(%rsp), %rdi movq %rbx, %rsi movq (%rsp), %rbx # 8-byte Reload movq %rbx, %rdx movl $1, %ecx callq hipMemcpy leaq 64(%rsp), %rdi movq %rbx, %rsi callq hipMalloc callq hipGetLastError testl %eax, %eax je .LBB4_26 # %bb.25: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movl $.L.str.13, %esi movq %rax, %rdx xorl %eax, %eax callq printf .LBB4_26: # %_Z11check_errorPKc.exit145 movq 64(%rsp), %rdi movq %r14, %rsi movq (%rsp), %rdx # 8-byte Reload movl $1, %ecx callq hipMemcpy testb $15, %r15b je .LBB4_27 # %bb.28: leal 15(%r15), %eax testl %r15d, %r15d cmovnsl %r15d, %eax sarl $4, %eax incl %eax testb $3, %r12b je .LBB4_30 .LBB4_31: leal 3(%r12), %ebp testl %r12d, %r12d cmovnsl %r12d, %ebp sarl $2, %ebp incl %ebp jmp .LBB4_32 .LBB4_27: movl %r15d, %eax sarl $4, %eax testb $3, %r12b jne .LBB4_31 .LBB4_30: movl %r12d, %ebp sarl $2, %ebp .LBB4_32: movl 752(%rsp), %r14d testb $3, %r13b je .LBB4_33 # %bb.34: leal 3(%r13), %edx testl %r13d, %r13d cmovnsl %r13d, %edx sarl $2, %edx incl %edx testl %r14d, %r14d jle .LBB4_36 .LBB4_39: # %.lr.ph movl %edx, 380(%rsp) # 4-byte Spill movq %r13, 328(%rsp) # 8-byte Spill movq %r12, 336(%rsp) # 8-byte Spill movq %r15, 344(%rsp) # 8-byte Spill movl %eax, %eax shlq $32, %rbp orq %rax, %rbp movabsq $17179869200, %r12 # imm = 0x400000010 xorl %ebx, %ebx xorl %r13d, %r13d xorl %r15d, %r15d movq %rbp, 584(%rsp) # 8-byte Spill jmp .LBB4_40 .p2align 4, 0x90 .LBB4_46: # in Loop: Header=BB4_40 Depth=1 subq 312(%rsp), %rbx # 8-byte Folded Reload addq 304(%rsp), %rbx # 8-byte Folded Reload subq 608(%rsp), %r13 # 8-byte Folded Reload addq 592(%rsp), %r13 # 8-byte Folded Reload callq hipDeviceSynchronize callq _ZNSt6chrono3_V212steady_clock3nowEv subq 600(%rsp), %r15 # 8-byte Folded Reload addq %rax, %r15 decl %r14d movq 584(%rsp), %rbp # 8-byte Reload movabsq $17179869200, %r12 # imm = 0x400000010 je .LBB4_37 .LBB4_40: # =>This Inner Loop Header: Depth=1 movl %r14d, 320(%rsp) # 4-byte Spill movq 56(%rsp), %rdi movq 544(%rsp), %rsi # 8-byte Reload movq (%rsp), %r14 # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy movq 48(%rsp), %rdi movq 552(%rsp), %rsi # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy movq 40(%rsp), %rdi movq 560(%rsp), %rsi # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy movq 32(%rsp), %rdi movq 568(%rsp), %rsi # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy movq 24(%rsp), %rdi movq 576(%rsp), %rsi # 8-byte Reload movq %r14, %rdx movl $1, %ecx callq hipMemcpy callq hipDeviceSynchronize callq _ZNSt6chrono3_V212steady_clock3nowEv movq %rax, 312(%rsp) # 8-byte Spill movq %rbp, %rdi movl 380(%rsp), %r14d # 4-byte Reload movl %r14d, %esi movq %r12, %rdx movl $4, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB4_42 # %bb.41: # in Loop: Header=BB4_40 Depth=1 movq 56(%rsp), %rax movq %rax, 296(%rsp) movq 48(%rsp), %rax movq %rax, 288(%rsp) movq 40(%rsp), %rax movq %rax, 280(%rsp) movq 32(%rsp), %rax movq %rax, 272(%rsp) movq 24(%rsp), %rax movq %rax, 264(%rsp) movq 120(%rsp), %rax movq %rax, 256(%rsp) movq 112(%rsp), %rax movq %rax, 248(%rsp) movq 104(%rsp), %rax movq %rax, 240(%rsp) movq 96(%rsp), %rax movq %rax, 232(%rsp) movq 88(%rsp), %rax movq %rax, 224(%rsp) movq 80(%rsp), %rax movq %rax, 216(%rsp) movq 72(%rsp), %rax movq %rax, 208(%rsp) movq 64(%rsp), %rax movq %rax, 200(%rsp) movsd 352(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero movsd %xmm0, 192(%rsp) movsd 360(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero movsd %xmm0, 184(%rsp) movsd 368(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero movsd %xmm0, 176(%rsp) movq 328(%rsp), %rax # 8-byte Reload movl %eax, 20(%rsp) movq 336(%rsp), %rax # 8-byte Reload movl %eax, 16(%rsp) movq 344(%rsp), %rax # 8-byte Reload movl %eax, 12(%rsp) leaq 296(%rsp), %rax movq %rax, 384(%rsp) leaq 288(%rsp), %rax movq %rax, 392(%rsp) leaq 280(%rsp), %rax movq %rax, 400(%rsp) leaq 272(%rsp), %rax movq %rax, 408(%rsp) leaq 264(%rsp), %rax movq %rax, 416(%rsp) leaq 256(%rsp), %rax movq %rax, 424(%rsp) leaq 248(%rsp), %rax movq %rax, 432(%rsp) leaq 240(%rsp), %rax movq %rax, 440(%rsp) leaq 232(%rsp), %rax movq %rax, 448(%rsp) leaq 224(%rsp), %rax movq %rax, 456(%rsp) leaq 216(%rsp), %rax movq %rax, 464(%rsp) leaq 208(%rsp), %rax movq %rax, 472(%rsp) leaq 200(%rsp), %rax movq %rax, 480(%rsp) leaq 192(%rsp), %rax movq %rax, 488(%rsp) leaq 184(%rsp), %rax movq %rax, 496(%rsp) leaq 176(%rsp), %rax movq %rax, 504(%rsp) leaq 20(%rsp), %rax movq %rax, 512(%rsp) leaq 16(%rsp), %rax movq %rax, 520(%rsp) leaq 12(%rsp), %rax movq %rax, 528(%rsp) leaq 160(%rsp), %rdi leaq 144(%rsp), %rsi leaq 136(%rsp), %rdx leaq 128(%rsp), %rcx callq __hipPopCallConfiguration movq 160(%rsp), %rsi movl 168(%rsp), %edx movq 144(%rsp), %rcx movl 152(%rsp), %r8d movl $_Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, %edi leaq 384(%rsp), %r9 pushq 128(%rsp) .cfi_adjust_cfa_offset 8 pushq 144(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB4_42: # in Loop: Header=BB4_40 Depth=1 callq hipDeviceSynchronize callq _ZNSt6chrono3_V212steady_clock3nowEv movq %rax, 304(%rsp) # 8-byte Spill callq _ZNSt6chrono3_V212steady_clock3nowEv movq %rax, 608(%rsp) # 8-byte Spill movq %rbp, %rdi movl %r14d, %esi movq %r12, %rdx movl $4, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB4_44 # %bb.43: # in Loop: Header=BB4_40 Depth=1 movq 56(%rsp), %rax movq %rax, 296(%rsp) movq 48(%rsp), %rax movq %rax, 288(%rsp) movq 40(%rsp), %rax movq %rax, 280(%rsp) movq 32(%rsp), %rax movq %rax, 272(%rsp) movq 24(%rsp), %rax movq %rax, 264(%rsp) movq 120(%rsp), %rax movq %rax, 256(%rsp) movq 112(%rsp), %rax movq %rax, 248(%rsp) movq 104(%rsp), %rax movq %rax, 240(%rsp) movq 96(%rsp), %rax movq %rax, 232(%rsp) movq 88(%rsp), %rax movq %rax, 224(%rsp) movq 80(%rsp), %rax movq %rax, 216(%rsp) movq 72(%rsp), %rax movq %rax, 208(%rsp) movq 64(%rsp), %rax movq %rax, 200(%rsp) movsd 352(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero movsd %xmm0, 192(%rsp) movsd 360(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero movsd %xmm0, 184(%rsp) movsd 368(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero movsd %xmm0, 176(%rsp) movq 328(%rsp), %rax # 8-byte Reload movl %eax, 20(%rsp) movq 336(%rsp), %rax # 8-byte Reload movl %eax, 16(%rsp) movq 344(%rsp), %rax # 8-byte Reload movl %eax, 12(%rsp) leaq 296(%rsp), %rax movq %rax, 384(%rsp) leaq 288(%rsp), %rax movq %rax, 392(%rsp) leaq 280(%rsp), %rax movq %rax, 400(%rsp) leaq 272(%rsp), %rax movq %rax, 408(%rsp) leaq 264(%rsp), %rax movq %rax, 416(%rsp) leaq 256(%rsp), %rax movq %rax, 424(%rsp) leaq 248(%rsp), %rax movq %rax, 432(%rsp) leaq 240(%rsp), %rax movq %rax, 440(%rsp) leaq 232(%rsp), %rax movq %rax, 448(%rsp) leaq 224(%rsp), %rax movq %rax, 456(%rsp) leaq 216(%rsp), %rax movq %rax, 464(%rsp) leaq 208(%rsp), %rax movq %rax, 472(%rsp) leaq 200(%rsp), %rax movq %rax, 480(%rsp) leaq 192(%rsp), %rax movq %rax, 488(%rsp) leaq 184(%rsp), %rax movq %rax, 496(%rsp) leaq 176(%rsp), %rax movq %rax, 504(%rsp) leaq 20(%rsp), %rax movq %rax, 512(%rsp) leaq 16(%rsp), %rax movq %rax, 520(%rsp) leaq 12(%rsp), %rax movq %rax, 528(%rsp) leaq 160(%rsp), %rdi leaq 144(%rsp), %rsi leaq 136(%rsp), %rdx leaq 128(%rsp), %rcx callq __hipPopCallConfiguration movq 160(%rsp), %rsi movl 168(%rsp), %edx movq 144(%rsp), %rcx movl 152(%rsp), %r8d movl $_Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, %edi leaq 384(%rsp), %r9 pushq 128(%rsp) .cfi_adjust_cfa_offset 8 pushq 144(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB4_44: # in Loop: Header=BB4_40 Depth=1 callq hipDeviceSynchronize callq _ZNSt6chrono3_V212steady_clock3nowEv movq %rax, 592(%rsp) # 8-byte Spill callq _ZNSt6chrono3_V212steady_clock3nowEv movq %rax, 600(%rsp) # 8-byte Spill movq %rbp, %rdi movl %r14d, %esi movq %r12, %rdx movl $4, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax movl 320(%rsp), %r14d # 4-byte Reload jne .LBB4_46 # %bb.45: # in Loop: Header=BB4_40 Depth=1 movq 56(%rsp), %rax movq %rax, 296(%rsp) movq 48(%rsp), %rax movq %rax, 288(%rsp) movq 40(%rsp), %rax movq %rax, 280(%rsp) movq 32(%rsp), %rax movq %rax, 272(%rsp) movq 24(%rsp), %rax movq %rax, 264(%rsp) movq 120(%rsp), %rax movq %rax, 256(%rsp) movq 112(%rsp), %rax movq %rax, 248(%rsp) movq 104(%rsp), %rax movq %rax, 240(%rsp) movq 96(%rsp), %rax movq %rax, 232(%rsp) movq 88(%rsp), %rax movq %rax, 224(%rsp) movq 80(%rsp), %rax movq %rax, 216(%rsp) movq 72(%rsp), %rax movq %rax, 208(%rsp) movq 64(%rsp), %rax movq %rax, 200(%rsp) movsd 352(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero movsd %xmm0, 192(%rsp) movsd 360(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero movsd %xmm0, 184(%rsp) movsd 368(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero movsd %xmm0, 176(%rsp) movq 328(%rsp), %rax # 8-byte Reload movl %eax, 20(%rsp) movq 336(%rsp), %rax # 8-byte Reload movl %eax, 16(%rsp) movq 344(%rsp), %rax # 8-byte Reload movl %eax, 12(%rsp) leaq 296(%rsp), %rax movq %rax, 384(%rsp) leaq 288(%rsp), %rax movq %rax, 392(%rsp) leaq 280(%rsp), %rax movq %rax, 400(%rsp) leaq 272(%rsp), %rax movq %rax, 408(%rsp) leaq 264(%rsp), %rax movq %rax, 416(%rsp) leaq 256(%rsp), %rax movq %rax, 424(%rsp) leaq 248(%rsp), %rax movq %rax, 432(%rsp) leaq 240(%rsp), %rax movq %rax, 440(%rsp) leaq 232(%rsp), %rax movq %rax, 448(%rsp) leaq 224(%rsp), %rax movq %rax, 456(%rsp) leaq 216(%rsp), %rax movq %rax, 464(%rsp) leaq 208(%rsp), %rax movq %rax, 472(%rsp) leaq 200(%rsp), %rax movq %rax, 480(%rsp) leaq 192(%rsp), %rax movq %rax, 488(%rsp) leaq 184(%rsp), %rax movq %rax, 496(%rsp) leaq 176(%rsp), %rax movq %rax, 504(%rsp) leaq 20(%rsp), %rax movq %rax, 512(%rsp) leaq 16(%rsp), %rax movq %rax, 520(%rsp) leaq 12(%rsp), %rax movq %rax, 528(%rsp) leaq 160(%rsp), %rdi leaq 144(%rsp), %rsi leaq 136(%rsp), %rdx leaq 128(%rsp), %rcx callq __hipPopCallConfiguration movq 160(%rsp), %rsi movl 168(%rsp), %edx movq 144(%rsp), %rcx movl 152(%rsp), %r8d movl $_Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, %edi leaq 384(%rsp), %r9 pushq 128(%rsp) .cfi_adjust_cfa_offset 8 pushq 144(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 jmp .LBB4_46 .LBB4_37: # %._crit_edge.loopexit cvtsi2sd %rbx, %xmm0 movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero mulsd %xmm1, %xmm0 cvtsi2sd %r13, %xmm2 mulsd %xmm1, %xmm2 movsd %xmm2, 304(%rsp) # 8-byte Spill xorps %xmm2, %xmm2 cvtsi2sd %r15, %xmm2 mulsd %xmm1, %xmm2 movsd %xmm2, 312(%rsp) # 8-byte Spill movl 752(%rsp), %r14d jmp .LBB4_38 .LBB4_33: movl %r13d, %edx sarl $2, %edx testl %r14d, %r14d jg .LBB4_39 .LBB4_36: xorpd %xmm0, %xmm0 movsd %xmm0, 312(%rsp) # 8-byte Spill movsd %xmm0, 304(%rsp) # 8-byte Spill .LBB4_38: # %._crit_edge xorps %xmm1, %xmm1 cvtsi2sd %r14d, %xmm1 movsd %xmm1, 320(%rsp) # 8-byte Spill divsd %xmm1, %xmm0 movl $.L.str.14, %edi movb $1, %al callq printf movsd 304(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero divsd 320(%rsp), %xmm0 # 8-byte Folded Reload movl $.L.str.15, %edi movb $1, %al callq printf movsd 312(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero divsd 320(%rsp), %xmm0 # 8-byte Folded Reload movl $.L.str.16, %edi movb $1, %al callq printf movq 56(%rsp), %rsi movq 544(%rsp), %rdi # 8-byte Reload movq (%rsp), %rbx # 8-byte Reload movq %rbx, %rdx movl $2, %ecx callq hipMemcpy movq 48(%rsp), %rsi movq 552(%rsp), %rdi # 8-byte Reload movq %rbx, %rdx movl $2, %ecx callq hipMemcpy movq 40(%rsp), %rsi movq 560(%rsp), %rdi # 8-byte Reload movq %rbx, %rdx movl $2, %ecx callq hipMemcpy movq 32(%rsp), %rsi movq 568(%rsp), %rdi # 8-byte Reload movq %rbx, %rdx movl $2, %ecx callq hipMemcpy movq 24(%rsp), %rsi movq 576(%rsp), %rdi # 8-byte Reload movq %rbx, %rdx movl $2, %ecx callq hipMemcpy movq 120(%rsp), %rdi callq hipFree movq 112(%rsp), %rdi callq hipFree movq 104(%rsp), %rdi callq hipFree movq 96(%rsp), %rdi callq hipFree movq 88(%rsp), %rdi callq hipFree movq 80(%rsp), %rdi callq hipFree movq 72(%rsp), %rdi callq hipFree movq 64(%rsp), %rdi callq hipFree movq 56(%rsp), %rdi callq hipFree movq 48(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree addq $616, %rsp # imm = 0x268 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end4: .size offload, .Lfunc_end4-offload .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB5_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB5_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end5: .size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB6_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB6_2: retq .Lfunc_end6: .size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Error : %s, %s\n" .size .L.str, 16 .type _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii,@object # @_Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .section .rodata,"a",@progbits .globl _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .p2align 3, 0x0 _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: .quad _Z24__device_stub__hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .size _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, 8 .type _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii,@object # @_Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .globl _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .p2align 3, 0x0 _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: .quad _Z24__device_stub__hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .size _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, 8 .type _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii,@object # @_Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .globl _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .p2align 3, 0x0 _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii: .quad _Z24__device_stub__hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .size _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "Failed to allocate device memory for flux_0\n" .size .L.str.1, 45 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to allocate device memory for flux_1\n" .size .L.str.2, 45 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to allocate device memory for flux_2\n" .size .L.str.3, 45 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to allocate device memory for flux_3\n" .size .L.str.4, 45 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to allocate device memory for flux_4\n" .size .L.str.5, 45 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Failed to allocate device memory for cons_1\n" .size .L.str.6, 45 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Failed to allocate device memory for cons_2\n" .size .L.str.7, 45 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Failed to allocate device memory for cons_3\n" .size .L.str.8, 45 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Failed to allocate device memory for cons_4\n" .size .L.str.9, 45 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Failed to allocate device memory for q_1\n" .size .L.str.10, 42 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "Failed to allocate device memory for q_2\n" .size .L.str.11, 42 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz "Failed to allocate device memory for q_3\n" .size .L.str.12, 42 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz "Failed to allocate device memory for q_4\n" .size .L.str.13, 42 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz "Average kernel execution time (k1): %f (ms)\n" .size .L.str.14, 45 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "Average kernel execution time (k2): %f (ms)\n" .size .L.str.15, 45 .type .L.str.16,@object # @.str.16 .L.str.16: .asciz "Average kernel execution time (k3): %f (ms)\n" .size .L.str.16, 45 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii" .size .L__unnamed_1, 53 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii" .size .L__unnamed_2, 53 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii" .size .L__unnamed_3, 53 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .addrsig_sym _Z24__device_stub__hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .addrsig_sym _Z24__device_stub__hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9hypterm_1PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .addrsig_sym _Z9hypterm_2PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .addrsig_sym _Z9hypterm_3PdS_S_S_S_PKdS1_S1_S1_S1_S1_S1_S1_dddiii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
18,475
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code for sm_80 Function : _Z11column_sumsPKfPfm .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; SHF.R.S32.HI R3, RZ, 0x1f, R2 ; ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ; @P0 EXIT ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; UMOV UR7, 0x3 ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x174] ; ULDC UR4, c[0x0][0x170] ; IMAD.MOV.U32 R7, RZ, RZ, RZ ; IADD3 R0, P1, -R0, c[0x0][0x170], RZ ; ULDC.64 UR10, c[0x0][0x118] ; IMAD.MOV.U32 R16, RZ, RZ, RZ ; ULOP3.LUT UR7, UR7, UR4, URZ, 0xc0, !UPT ; ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; IADD3.X R0, R6, -0x1, RZ, P1, !PT ; ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; @!P0 BRA 0x3a0 ; UMOV UR4, 0x4 ; IMAD.SHL.U32 R17, R6, 0x4, RZ ; ULDC.64 UR8, c[0x0][0x170] ; LEA R8, P0, R2.reuse, c[0x0][0x160], 0x2 ; UIMAD.WIDE.U32 UR4, UR4, UR8, URZ ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; UIADD3 UR12, UP0, UR7, -UR8, URZ ; IMAD.MOV.U32 R7, RZ, RZ, RZ ; LEA.HI.X R5, R2, c[0x0][0x164], R3, 0x2, P0 ; IMAD.MOV.U32 R16, RZ, RZ, RZ ; IADD3 R17, R17, UR5, RZ ; UIADD3.X UR6, URZ, ~UR9, URZ, UP0, !UPT ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; IADD3 R10, P0, R8, UR4, RZ ; IADD3.X R11, R5, R17, RZ, P0, !PT ; LDG.E R9, [R8.64] ; IADD3 R12, P0, R10, UR4, RZ ; LDG.E R10, [R10.64] ; IMAD.X R13, R11, 0x1, R17, P0 ; IADD3 R4, P0, R12, UR4, RZ ; LDG.E R12, [R12.64] ; IMAD.X R5, R13, 0x1, R17, P0 ; LDG.E R14, [R4.64] ; IADD3 R7, P0, R7, 0x4, RZ ; IADD3 R15, P1, R7, UR12, RZ ; IMAD.X R16, RZ, RZ, R16, P0 ; ISETP.NE.U32.AND P0, PT, R15, RZ, PT ; FADD R9, R9, R0 ; IADD3.X R0, R16, UR6, RZ, P1, !PT ; ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; FADD R9, R9, R10 ; IADD3 R8, P1, R4, UR4, RZ ; FADD R9, R9, R12 ; IMAD.X R5, R5, 0x1, R17, P1 ; FADD R0, R9, R14 ; @P0 BRA 0x220 ; ISETP.NE.U32.AND P0, PT, RZ, UR7, PT ; LEA R4, P1, R2.reuse, c[0x0][0x168], 0x2 ; ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; LEA.HI.X R5, R2, c[0x0][0x16c], R3, 0x2, P1 ; @!P0 BRA 0x540 ; IMAD R16, R16, c[0x0][0x170], RZ ; MOV R8, c[0x0][0x170] ; IMAD.WIDE.U32 R2, R7, c[0x0][0x170], R2 ; UIADD3 UR4, UP0, URZ, -UR7, URZ ; IMAD R9, R7, c[0x0][0x174], R16 ; LEA R7, P0, R2, c[0x0][0x160], 0x2 ; UIADD3.X UR5, URZ, -0x1, URZ, UP0, !UPT ; IMAD.IADD R3, R3, 0x1, R9 ; SHF.L.U64.HI R9, R8, 0x2, R6 ; LEA.HI.X R6, R2, c[0x0][0x164], R3, 0x2, P0 ; IMAD.MOV.U32 R3, RZ, RZ, R6 ; IMAD.MOV.U32 R2, RZ, RZ, R7 ; LDG.E R3, [R2.64] ; UIADD3 UR4, UP0, UR4, 0x1, URZ ; LEA R7, P1, R8, R7, 0x2 ; UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; ISETP.NE.U32.AND P0, PT, RZ, UR4, PT ; IMAD.X R6, R6, 0x1, R9, P1 ; ISETP.NE.AND.EX P0, PT, RZ, UR5, PT, P0 ; FADD R0, R3, R0 ; @P0 BRA 0x490 ; STG.E [R4.64], R0 ; EXIT ; BRA 0x560; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z8row_sumsPKfPfm .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R7, SR_CTAID.X ; ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x170], PT ; SHF.R.S32.HI R8, RZ, 0x1f, R7 ; ISETP.GE.U32.AND.EX P0, PT, R8, c[0x0][0x174], PT, P0 ; @P0 EXIT ; S2R R9, SR_TID.X ; ULDC.64 UR6, c[0x0][0x118] ; BSSY B0, 0x250 ; STS [R9.X4], RZ ; ISETP.GE.U32.AND P0, PT, R9.reuse, c[0x0][0x170], PT ; IMAD.SHL.U32 R0, R9, 0x4, RZ ; SHF.R.S32.HI R2, RZ, 0x1f, R9 ; ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; @P0 BRA 0x240 ; IMAD R4, R8, c[0x0][0x170], RZ ; BSSY B1, 0x230 ; IMAD.MOV.U32 R11, RZ, RZ, R2 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R10, RZ, RZ, R9 ; IMAD R13, R7, c[0x0][0x174], R4 ; IMAD.MOV.U32 R2, RZ, RZ, R10 ; IMAD.MOV.U32 R3, RZ, RZ, R11 ; IMAD.WIDE.U32 R2, R7, c[0x0][0x170], R2 ; IMAD.IADD R3, R3, 0x1, R13 ; LEA R4, P0, R2, c[0x0][0x160], 0x2 ; LEA.HI.X R5, R2, c[0x0][0x164], R3, 0x2, P0 ; LDG.E R5, [R4.64] ; IADD3 R10, P0, R10, c[0x0][0x0], RZ ; IMAD.X R11, RZ, RZ, R11, P0 ; ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x170], PT ; ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x174], PT, P0 ; FADD R6, R5, R6 ; @!P0 BRA 0x150 ; BSYNC B1 ; STS [R9.X4], R6 ; BSYNC B0 ; ULDC UR4, c[0x0][0x0] ; ISETP.NE.AND P0, PT, R9, RZ, PT ; USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; ISETP.NE.AND P1, PT, RZ, UR4, PT ; @!P1 BRA 0x350 ; IMAD.U32 R3, RZ, RZ, UR4 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.U32.AND P1, PT, R9, R3, PT ; @!P1 IMAD R2, R3, 0x4, R0 ; SHF.R.U32.HI R3, RZ, 0x1, R3 ; @!P1 LDS R4, [R9.X4] ; @!P1 LDS R5, [R2] ; @!P1 FADD R4, R4, R5 ; @!P1 STS [R9.X4], R4 ; ISETP.NE.AND P1, PT, R3, RZ, PT ; @P1 BRA 0x2b0 ; @P0 EXIT ; LDS R5, [RZ] ; LEA R2, P0, R7, c[0x0][0x168], 0x2 ; LEA.HI.X R3, R7, c[0x0][0x16c], R8, 0x2, P0 ; STG.E [R2.64], R5 ; EXIT ; BRA 0x3b0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00071c7b_00000000-6_444dabe1451a1aec97ee99e425c88fc20870551f.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "results mismatch at %lu, was: %f, should be: %f\n" .text .globl _Z8validatePfm .type _Z8validatePfm, @function _Z8validatePfm: .LFB2057: .cfi_startproc endbr64 testq %rsi, %rsi je .L10 movl $0, %edx movq %rsi, %rcx andl $1, %ecx jmp .L9 .L5: movq %rsi, %rax shrq %rax orq %rcx, %rax pxor %xmm1, %xmm1 cvtsi2ssq %rax, %xmm1 addss %xmm1, %xmm1 .L6: ucomiss %xmm1, %xmm0 jp .L11 jne .L11 addq $1, %rdx cmpq %rdx, %rsi je .L16 .L9: movss (%rdi,%rdx,4), %xmm0 testq %rsi, %rsi js .L5 pxor %xmm1, %xmm1 cvtsi2ssq %rsi, %xmm1 jmp .L6 .L11: subq $8, %rsp .cfi_def_cfa_offset 16 cvtss2sd %xmm0, %xmm0 cvtss2sd %xmm1, %xmm1 leaq .LC0(%rip), %rsi movl $2, %edi movl $2, %eax call __printf_chk@PLT movl $0, %eax addq $8, %rsp .cfi_def_cfa_offset 8 ret .L16: movl $1, %eax ret .L10: movl $1, %eax ret .cfi_endproc .LFE2057: .size _Z8validatePfm, .-_Z8validatePfm .globl _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm .type _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm, @function _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm: .LFB2083: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L21 .L17: movq 120(%rsp), %rax subq %fs:40, %rax jne .L22 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L21: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z8row_sumsPKfPfm(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L17 .L22: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm, .-_Z31__device_stub__Z8row_sumsPKfPfmPKfPfm .globl _Z8row_sumsPKfPfm .type _Z8row_sumsPKfPfm, @function _Z8row_sumsPKfPfm: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z8row_sumsPKfPfm, .-_Z8row_sumsPKfPfm .globl _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm .type _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm, @function _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm: .LFB2085: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L29 .L25: movq 120(%rsp), %rax subq %fs:40, %rax jne .L30 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L29: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z11column_sumsPKfPfm(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L25 .L30: call __stack_chk_fail@PLT .cfi_endproc .LFE2085: .size _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm, .-_Z35__device_stub__Z11column_sumsPKfPfmPKfPfm .globl _Z11column_sumsPKfPfm .type _Z11column_sumsPKfPfm, @function _Z11column_sumsPKfPfm: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _Z11column_sumsPKfPfm, .-_Z11column_sumsPKfPfm .section .rodata.str1.8 .align 8 .LC3: .string "/home/ubuntu/Datasets/Stack_v2_cuda-hip/train/444dabe1451a1aec97ee99e425c88fc20870551f.cu" .section .rodata.str1.1,"aMS",@progbits,1 .LC4: .string "cudaMalloc failure" .section .rodata.str1.8 .align 8 .LC5: .string "Fatal error: %s (%s at %s:%d)\n" .section .rodata.str1.1 .LC6: .string "*** FAILED - ABORTING\n" .LC7: .string "cudaMemcpy H2D failure" .LC8: .string "kernel launch failure" .section .rodata.str1.8 .align 8 .LC9: .string "kernel execution failure or cudaMemcpy H2D failure" .section .rodata.str1.1 .LC10: .string "row sums correct!\n" .LC11: .string "column sums correct!\n" .text .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $56, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $1073741824, %edi call _Znam@PLT movq %rax, %rbp movl $65536, %edi call _Znam@PLT movq %rax, %rbx leaq 65536(%rax), %rdx .L34: movl $0x00000000, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L34 movq %rbp, %rax leaq 1073741824(%rbp), %rdx movss .LC2(%rip), %xmm0 .L35: movss %xmm0, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L35 movq %rsp, %rdi movl $1073741824, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $65536, %esi call cudaMalloc@PLT call cudaGetLastError@PLT testl %eax, %eax jne .L51 movl $1, %ecx movl $1073741824, %edx movq %rbp, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT call cudaGetLastError@PLT testl %eax, %eax jne .L52 movl $256, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $16384, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L53 .L38: call cudaGetLastError@PLT testl %eax, %eax jne .L54 movl $2, %ecx movl $65536, %edx movq 8(%rsp), %rsi movq %rbx, %rdi call cudaMemcpy@PLT call cudaGetLastError@PLT testl %eax, %eax jne .L55 movl $16384, %esi movq %rbx, %rdi call _Z8validatePfm testb %al, %al je .L46 leaq .LC10(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $65536, %edx movl $0, %esi movq 8(%rsp), %rdi call cudaMemset@PLT movl $256, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $64, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L56 .L42: call cudaGetLastError@PLT testl %eax, %eax jne .L57 movl $2, %ecx movl $65536, %edx movq 8(%rsp), %rsi movq %rbx, %rdi call cudaMemcpy@PLT call cudaGetLastError@PLT testl %eax, %eax jne .L58 movl $16384, %esi movq %rbx, %rdi call _Z8validatePfm testb %al, %al je .L47 leaq .LC11(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %eax .L33: movq 40(%rsp), %rdx subq %fs:40, %rdx jne .L59 addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L51: .cfi_restore_state movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %r8 subq $8, %rsp .cfi_def_cfa_offset 88 pushq $70 .cfi_def_cfa_offset 96 leaq .LC3(%rip), %r9 leaq .LC4(%rip), %rcx leaq .LC5(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT addq $16, %rsp .cfi_def_cfa_offset 80 leaq .LC6(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L52: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %r8 subq $8, %rsp .cfi_def_cfa_offset 88 pushq $73 .cfi_def_cfa_offset 96 leaq .LC3(%rip), %r9 leaq .LC7(%rip), %rcx leaq .LC5(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT addq $16, %rsp .cfi_def_cfa_offset 80 leaq .LC6(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L53: movl $16384, %edx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm jmp .L38 .L54: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %r8 subq $8, %rsp .cfi_def_cfa_offset 88 pushq $76 .cfi_def_cfa_offset 96 leaq .LC3(%rip), %r9 leaq .LC8(%rip), %rcx leaq .LC5(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT addq $16, %rsp .cfi_def_cfa_offset 80 leaq .LC6(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L55: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %r8 subq $8, %rsp .cfi_def_cfa_offset 88 pushq $81 .cfi_def_cfa_offset 96 leaq .LC3(%rip), %r9 leaq .LC9(%rip), %rcx leaq .LC5(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT addq $16, %rsp .cfi_def_cfa_offset 80 leaq .LC6(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L56: movl $16384, %edx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm jmp .L42 .L57: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %r8 subq $8, %rsp .cfi_def_cfa_offset 88 pushq $86 .cfi_def_cfa_offset 96 leaq .LC3(%rip), %r9 leaq .LC8(%rip), %rcx leaq .LC5(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT addq $16, %rsp .cfi_def_cfa_offset 80 leaq .LC6(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L58: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %r8 subq $8, %rsp .cfi_def_cfa_offset 88 pushq $91 .cfi_def_cfa_offset 96 leaq .LC3(%rip), %r9 leaq .LC9(%rip), %rcx leaq .LC5(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT addq $16, %rsp .cfi_def_cfa_offset 80 leaq .LC6(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L46: movl $-1, %eax jmp .L33 .L47: movl $-1, %eax jmp .L33 .L59: call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.1 .LC12: .string "_Z11column_sumsPKfPfm" .LC13: .string "_Z8row_sumsPKfPfm" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2088: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _Z11column_sumsPKfPfm(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC13(%rip), %rdx movq %rdx, %rcx leaq _Z8row_sumsPKfPfm(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2088: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC2: .long 1065353216 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z8row_sumsPKfPfm ; -- Begin function _Z8row_sumsPKfPfm .globl _Z8row_sumsPKfPfm .p2align 8 .type _Z8row_sumsPKfPfm,@function _Z8row_sumsPKfPfm: ; @_Z8row_sumsPKfPfm ; %bb.0: s_load_b64 s[6:7], s[0:1], 0x10 s_mov_b32 s4, s15 s_ashr_i32 s5, s15, 31 s_waitcnt lgkmcnt(0) v_cmp_ge_u64_e64 s2, s[4:5], s[6:7] s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s2 s_cbranch_vccnz .LBB0_12 ; %bb.1: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v6, 2, v0 s_mov_b32 s3, exec_lo ds_store_b32 v6, v1 v_cmpx_gt_u64_e64 s[6:7], v[0:1] s_cbranch_execz .LBB0_5 ; %bb.2: ; %.lr.ph s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b64 s[10:11], s[0:1], 0x0 ds_load_b32 v7, v6 s_mul_i32 s9, s6, s5 s_mul_hi_u32 s12, s6, s4 s_mul_i32 s13, s7, s4 s_add_i32 s9, s12, s9 s_mul_i32 s12, s6, s4 s_add_i32 s13, s9, s13 v_dual_mov_b32 v5, v1 :: v_dual_lshlrev_b32 v2, 2, v0 s_lshl_b64 s[12:13], s[12:13], 2 v_mov_b32_e32 v4, v0 s_mov_b32 s8, 0 s_waitcnt lgkmcnt(0) s_and_b32 s9, s2, 0xffff s_add_u32 s2, s10, s12 s_addc_u32 s10, s11, s13 v_add_co_u32 v2, s2, s2, v2 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v3, null, s10, 0, s2 s_lshl_b32 s10, s9, 2 s_mov_b32 s12, s8 s_mov_b32 s11, s8 .LBB0_3: ; =>This Inner Loop Header: Depth=1 global_load_b32 v1, v[2:3], off v_add_co_u32 v4, vcc_lo, v4, s9 v_add_co_ci_u32_e32 v5, vcc_lo, s8, v5, vcc_lo v_add_co_u32 v2, s2, v2, s10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v3, s2, s12, v3, s2 v_cmp_le_u64_e32 vcc_lo, s[6:7], v[4:5] s_or_b32 s11, vcc_lo, s11 s_waitcnt vmcnt(0) v_add_f32_e32 v7, v1, v7 s_and_not1_b32 exec_lo, exec_lo, s11 s_cbranch_execnz .LBB0_3 ; %bb.4: ; %._crit_edge s_or_b32 exec_lo, exec_lo, s11 ds_store_b32 v6, v7 .LBB0_5: ; %Flow42 s_or_b32 exec_lo, exec_lo, s3 s_load_b32 s2, s[0:1], 0x24 s_waitcnt lgkmcnt(0) v_cmp_lt_u16_e64 s3, s2, 2 s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s3 s_cbranch_vccnz .LBB0_10 ; %bb.6: ; %.lr.ph32.preheader s_and_b32 s2, 0xffff, s2 s_delay_alu instid0(SALU_CYCLE_1) s_lshr_b32 s2, s2, 1 s_branch .LBB0_8 .p2align 6 .LBB0_7: ; in Loop: Header=BB0_8 Depth=1 s_or_b32 exec_lo, exec_lo, s3 s_lshr_b32 s3, s2, 1 s_cmp_lt_u32 s2, 2 s_mov_b32 s2, s3 s_cbranch_scc1 .LBB0_10 .LBB0_8: ; %.lr.ph32 ; =>This Inner Loop Header: Depth=1 s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmpx_gt_u32_e64 s2, v0 s_cbranch_execz .LBB0_7 ; %bb.9: ; in Loop: Header=BB0_8 Depth=1 v_add_lshl_u32 v1, s2, v0, 2 ds_load_b32 v1, v1 ds_load_b32 v2, v6 s_waitcnt lgkmcnt(0) v_add_f32_e32 v1, v1, v2 ds_store_b32 v6, v1 s_branch .LBB0_7 .LBB0_10: ; %._crit_edge33 s_mov_b32 s2, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_12 ; %bb.11: v_mov_b32_e32 v0, 0 s_load_b64 s[0:1], s[0:1], 0x8 s_lshl_b64 s[2:3], s[4:5], 2 ds_load_b32 v1, v0 s_waitcnt lgkmcnt(0) s_add_u32 s0, s0, s2 s_addc_u32 s1, s1, s3 global_store_b32 v0, v1, s[0:1] .LBB0_12: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z8row_sumsPKfPfm .amdhsa_group_segment_fixed_size 1024 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z8row_sumsPKfPfm, .Lfunc_end0-_Z8row_sumsPKfPfm ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 492 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 1024 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z11column_sumsPKfPfm ; -- Begin function _Z11column_sumsPKfPfm .globl _Z11column_sumsPKfPfm .p2align 8 .type _Z11column_sumsPKfPfm,@function _Z11column_sumsPKfPfm: ; @_Z11column_sumsPKfPfm ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x24 s_load_b64 s[2:3], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] s_mov_b32 s4, exec_lo v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_u64_e64 s[2:3], v[1:2] s_cbranch_execz .LBB1_4 ; %bb.1: ; %.preheader s_load_b64 s[4:5], s[0:1], 0x0 v_lshlrev_b64 v[3:4], 2, v[1:2] v_mov_b32_e32 v0, 0 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v3, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo s_lshl_b64 s[4:5], s[2:3], 2 .LBB1_2: ; =>This Inner Loop Header: Depth=1 global_load_b32 v5, v[3:4], off v_add_co_u32 v3, vcc_lo, v3, s4 s_add_u32 s2, s2, -1 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo s_addc_u32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u64 s[2:3], 0 s_waitcnt vmcnt(0) v_add_f32_e32 v0, v0, v5 s_cbranch_scc0 .LBB1_2 ; %bb.3: s_load_b64 s[0:1], s[0:1], 0x8 v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, s0, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo global_store_b32 v[1:2], v0, off .LBB1_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11column_sumsPKfPfm .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z11column_sumsPKfPfm, .Lfunc_end1-_Z11column_sumsPKfPfm ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 216 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 8 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 1024 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z8row_sumsPKfPfm .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z8row_sumsPKfPfm.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 8 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11column_sumsPKfPfm .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z11column_sumsPKfPfm.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "444dabe1451a1aec97ee99e425c88fc20870551f.hip" .globl _Z23__device_stub__row_sumsPKfPfm # -- Begin function _Z23__device_stub__row_sumsPKfPfm .p2align 4, 0x90 .type _Z23__device_stub__row_sumsPKfPfm,@function _Z23__device_stub__row_sumsPKfPfm: # @_Z23__device_stub__row_sumsPKfPfm .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z8row_sumsPKfPfm, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z23__device_stub__row_sumsPKfPfm, .Lfunc_end0-_Z23__device_stub__row_sumsPKfPfm .cfi_endproc # -- End function .globl _Z26__device_stub__column_sumsPKfPfm # -- Begin function _Z26__device_stub__column_sumsPKfPfm .p2align 4, 0x90 .type _Z26__device_stub__column_sumsPKfPfm,@function _Z26__device_stub__column_sumsPKfPfm: # @_Z26__device_stub__column_sumsPKfPfm .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z11column_sumsPKfPfm, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end1: .size _Z26__device_stub__column_sumsPKfPfm, .Lfunc_end1-_Z26__device_stub__column_sumsPKfPfm .cfi_endproc # -- End function .globl _Z8validatePfm # -- Begin function _Z8validatePfm .p2align 4, 0x90 .type _Z8validatePfm,@function _Z8validatePfm: # @_Z8validatePfm .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 testq %rsi, %rsi sete %bl je .LBB2_12 # %bb.1: # %.lr.ph js .LBB2_2 # %bb.3: # %.lr.ph cvtsi2ss %rsi, %xmm1 jmp .LBB2_4 .LBB2_2: movq %rsi, %rax shrq %rax movl %esi, %ecx andl $1, %ecx orq %rax, %rcx cvtsi2ss %rcx, %xmm1 addss %xmm1, %xmm1 .LBB2_4: # %.lr.ph movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero ucomiss %xmm1, %xmm0 jne .LBB2_5 jnp .LBB2_9 .LBB2_5: xorl %eax, %eax jmp .LBB2_8 .LBB2_9: # %.lr.ph32.preheader leaq -1(%rsi), %rcx xorl %eax, %eax .p2align 4, 0x90 .LBB2_10: # %.lr.ph32 # =>This Inner Loop Header: Depth=1 cmpq %rax, %rcx je .LBB2_11 # %bb.6: # in Loop: Header=BB2_10 Depth=1 movss 4(%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero incq %rax ucomiss %xmm1, %xmm0 jne .LBB2_7 jnp .LBB2_10 .LBB2_7: # %._crit_edge.loopexit cmpq %rsi, %rax setae %bl .LBB2_8: # %._crit_edge cvtss2sd %xmm0, %xmm0 cvtss2sd %xmm1, %xmm1 movl $.L.str, %edi movq %rax, %rsi movb $2, %al callq printf .LBB2_12: # %.loopexit movl %ebx, %eax popq %rbx .cfi_def_cfa_offset 8 retq .LBB2_11: .cfi_def_cfa_offset 16 movb $1, %bl jmp .LBB2_12 .Lfunc_end2: .size _Z8validatePfm, .Lfunc_end2-_Z8validatePfm .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI3_0: .long 0x46800000 # float 16384 .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI3_1: .quad 0x40d0000000000000 # double 16384 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $120, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $1073741824, %edi # imm = 0x40000000 callq _Znam movq %rax, %r14 movl $65536, %edi # imm = 0x10000 callq _Znam movq %rax, %rbx xorl %r15d, %r15d movl $65536, %edx # imm = 0x10000 movq %rax, %rdi xorl %esi, %esi callq memset@PLT .p2align 4, 0x90 .LBB3_1: # =>This Inner Loop Header: Depth=1 movl $1065353216, (%r14,%r15,4) # imm = 0x3F800000 incq %r15 cmpq $268435456, %r15 # imm = 0x10000000 jne .LBB3_1 # %bb.2: leaq 16(%rsp), %rdi movl $1073741824, %esi # imm = 0x40000000 callq hipMalloc leaq 8(%rsp), %rdi movl $65536, %esi # imm = 0x10000 callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB3_3 # %bb.5: movq 16(%rsp), %rdi movl $1073741824, %edx # imm = 0x40000000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB3_6 # %bb.7: movabsq $4294967552, %r14 # imm = 0x100000100 leaq 16128(%r14), %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_9 # %bb.8: movq 16(%rsp), %rax movq 8(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movq $16384, 72(%rsp) # imm = 0x4000 leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z8row_sumsPKfPfm, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_9: callq hipGetLastError testl %eax, %eax jne .LBB3_10 # %bb.11: movq 8(%rsp), %rsi movl $65536, %edx # imm = 0x10000 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB3_14 # %bb.12: # %.preheader61 movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero ucomiss .LCPI3_0(%rip), %xmm0 jne .LBB3_13 jnp .LBB3_18 .LBB3_13: xorl %r15d, %r15d xorl %esi, %esi jmp .LBB3_17 .LBB3_18: # %.lr.ph.preheader xorl %esi, %esi movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero .p2align 4, 0x90 .LBB3_19: # %.lr.ph # =>This Inner Loop Header: Depth=1 cmpq $16383, %rsi # imm = 0x3FFF je .LBB3_20 # %bb.15: # in Loop: Header=BB3_19 Depth=1 movss 4(%rbx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero incq %rsi ucomiss %xmm1, %xmm0 jne .LBB3_16 jnp .LBB3_19 .LBB3_16: # %._crit_edge.loopexit leaq -1(%rsi), %rax cmpq $16383, %rax # imm = 0x3FFF setae %r15b .LBB3_17: # %._crit_edge cvtss2sd %xmm0, %xmm0 movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero movl $.L.str, %edi movb $2, %al callq printf .LBB3_21: # %_Z8validatePfm.exit movl $-1, %ebp testb %r15b, %r15b je .LBB3_38 # %bb.22: movl $.Lstr, %edi callq puts@PLT movq 8(%rsp), %rdi movl $65536, %edx # imm = 0x10000 xorl %esi, %esi callq hipMemset leaq -192(%r14), %rdi movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_24 # %bb.23: movq 16(%rsp), %rax movq 8(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movq $16384, 72(%rsp) # imm = 0x4000 leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z11column_sumsPKfPfm, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_24: callq hipGetLastError testl %eax, %eax jne .LBB3_25 # %bb.26: movq 8(%rsp), %rsi movl $65536, %edx # imm = 0x10000 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB3_29 # %bb.27: # %.preheader movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero ucomiss .LCPI3_0(%rip), %xmm0 jne .LBB3_28 jnp .LBB3_33 .LBB3_28: xorl %ebx, %ebx xorl %esi, %esi jmp .LBB3_32 .LBB3_20: # %_Z8validatePfm.exit.loopexit setae %r15b jmp .LBB3_21 .LBB3_33: # %.lr.ph78.preheader xorl %esi, %esi movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero .p2align 4, 0x90 .LBB3_34: # %.lr.ph78 # =>This Inner Loop Header: Depth=1 cmpq $16383, %rsi # imm = 0x3FFF je .LBB3_35 # %bb.30: # in Loop: Header=BB3_34 Depth=1 movss 4(%rbx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero incq %rsi ucomiss %xmm1, %xmm0 jne .LBB3_31 jnp .LBB3_34 .LBB3_31: # %._crit_edge79.loopexit leaq -1(%rsi), %rax cmpq $16383, %rax # imm = 0x3FFF setae %bl .LBB3_32: # %._crit_edge79 cvtss2sd %xmm0, %xmm0 movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero movl $.L.str, %edi movb $2, %al callq printf testb %bl, %bl je .LBB3_38 .LBB3_37: movl $.Lstr.1, %edi callq puts@PLT xorl %ebp, %ebp .LBB3_38: movl %ebp, %eax addq $120, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB3_35: # %_Z8validatePfm.exit51.loopexit .cfi_def_cfa_offset 160 setae %bl testb %bl, %bl jne .LBB3_37 jmp .LBB3_38 .LBB3_3: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.1, %esi movl $.L.str.2, %edx movl $.L.str.3, %r8d movq %rbx, %rdi movq %rax, %rcx movl $72, %r9d jmp .LBB3_4 .LBB3_6: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.1, %esi movl $.L.str.5, %edx movl $.L.str.3, %r8d movq %rbx, %rdi movq %rax, %rcx movl $75, %r9d jmp .LBB3_4 .LBB3_10: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.1, %esi movl $.L.str.6, %edx movl $.L.str.3, %r8d movq %rbx, %rdi movq %rax, %rcx movl $78, %r9d jmp .LBB3_4 .LBB3_14: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.1, %esi movl $.L.str.7, %edx movl $.L.str.3, %r8d movq %rbx, %rdi movq %rax, %rcx movl $83, %r9d jmp .LBB3_4 .LBB3_25: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.1, %esi movl $.L.str.6, %edx movl $.L.str.3, %r8d movq %rbx, %rdi movq %rax, %rcx movl $88, %r9d jmp .LBB3_4 .LBB3_29: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.1, %esi movl $.L.str.7, %edx movl $.L.str.3, %r8d movq %rbx, %rdi movq %rax, %rcx movl $93, %r9d .LBB3_4: xorl %eax, %eax callq fprintf movq stderr(%rip), %rcx movl $.L.str.4, %edi movl $22, %esi movl $1, %edx callq fwrite@PLT movl $1, %edi callq exit .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z8row_sumsPKfPfm, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11column_sumsPKfPfm, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z8row_sumsPKfPfm,@object # @_Z8row_sumsPKfPfm .section .rodata,"a",@progbits .globl _Z8row_sumsPKfPfm .p2align 3, 0x0 _Z8row_sumsPKfPfm: .quad _Z23__device_stub__row_sumsPKfPfm .size _Z8row_sumsPKfPfm, 8 .type _Z11column_sumsPKfPfm,@object # @_Z11column_sumsPKfPfm .globl _Z11column_sumsPKfPfm .p2align 3, 0x0 _Z11column_sumsPKfPfm: .quad _Z26__device_stub__column_sumsPKfPfm .size _Z11column_sumsPKfPfm, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "results mismatch at %lu, was: %f, should be: %f\n" .size .L.str, 49 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Fatal error: %s (%s at %s:%d)\n" .size .L.str.1, 31 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "hipMalloc failure" .size .L.str.2, 18 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "/home/ubuntu/Datasets/Stack_v2_cuda-hip-as/444dabe1451a1aec97ee99e425c88fc20870551f.hip" .size .L.str.3, 88 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "*** FAILED - ABORTING\n" .size .L.str.4, 23 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "hipMemcpy H2D failure" .size .L.str.5, 22 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "kernel launch failure" .size .L.str.6, 22 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "kernel execution failure or hipMemcpy H2D failure" .size .L.str.7, 50 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z8row_sumsPKfPfm" .size .L__unnamed_1, 18 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z11column_sumsPKfPfm" .size .L__unnamed_2, 22 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "row sums correct!" .size .Lstr, 18 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "column sums correct!" .size .Lstr.1, 21 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z23__device_stub__row_sumsPKfPfm .addrsig_sym _Z26__device_stub__column_sumsPKfPfm .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z8row_sumsPKfPfm .addrsig_sym _Z11column_sumsPKfPfm .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
3,769
6,873
6,037
8,170
168
code for sm_80 Function : _Z5saxpyifPfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R4, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R4, R4, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; @P0 EXIT ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; LDG.E R2, [R2.64] ; LDG.E R7, [R4.64] ; FFMA R7, R2, c[0x0][0x164], R7 ; STG.E [R4.64], R7 ; EXIT ; BRA 0xf0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000b7025_00000000-6_a84323ec49baf3c4c6dce068e180bceaac53f934.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z28__device_stub__Z5saxpyifPfS_ifPfS_ .type _Z28__device_stub__Z5saxpyifPfS_ifPfS_, @function _Z28__device_stub__Z5saxpyifPfS_ifPfS_: .LFB2082: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 28(%rsp) movss %xmm0, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 24(%rsp), %rax movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z5saxpyifPfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z28__device_stub__Z5saxpyifPfS_ifPfS_, .-_Z28__device_stub__Z5saxpyifPfS_ifPfS_ .globl _Z5saxpyifPfS_ .type _Z5saxpyifPfS_, @function _Z5saxpyifPfS_: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z28__device_stub__Z5saxpyifPfS_ifPfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC5: .string "Max error: %f\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $56, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $4194304, %edi call malloc@PLT movq %rax, %rbp movl $4194304, %edi call malloc@PLT movq %rax, %rbx movq %rsp, %rdi movl $4194304, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $4194304, %esi call cudaMalloc@PLT movl $0, %eax movss .LC1(%rip), %xmm1 movss .LC2(%rip), %xmm0 .L12: movss %xmm1, 0(%rbp,%rax) movss %xmm0, (%rbx,%rax) addq $4, %rax cmpq $4194304, %rax jne .L12 movl $1, %ecx movl $4194304, %edx movq %rbp, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $4194304, %edx movq %rbx, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $256, 28(%rsp) movl $1, 32(%rsp) movl $4096, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L19 .L13: movl $2, %ecx movl $4194304, %edx movq 8(%rsp), %rsi movq %rbx, %rdi call cudaMemcpy@PLT movq %rbx, %r12 leaq 4194304(%rbx), %r13 pxor %xmm1, %xmm1 .L14: movss (%r12), %xmm2 subss .LC3(%rip), %xmm2 andps .LC4(%rip), %xmm2 movaps %xmm2, %xmm0 call fmaxf@PLT movaps %xmm0, %xmm1 addq $4, %r12 cmpq %r13, %r12 jne .L14 cvtss2sd %xmm0, %xmm0 leaq .LC5(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call free@PLT movq %rbx, %rdi call free@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L20 movl $0, %eax addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state movq 8(%rsp), %rdx movq (%rsp), %rsi movss .LC2(%rip), %xmm0 movl $1048576, %edi call _Z28__device_stub__Z5saxpyifPfS_ifPfS_ jmp .L13 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC6: .string "_Z5saxpyifPfS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z5saxpyifPfS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 1065353216 .align 4 .LC2: .long 1073741824 .align 4 .LC3: .long 1082130432 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC4: .long 2147483647 .long 0 .long 0 .long 0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z5saxpyifPfS_ ; -- Begin function _Z5saxpyifPfS_ .globl _Z5saxpyifPfS_ .p2align 8 .type _Z5saxpyifPfS_,@function _Z5saxpyifPfS_: ; @_Z5saxpyifPfS_ ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b32 s3, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x8 v_ashrrev_i32_e32 v2, 31, v1 s_load_b32 s0, s[0:1], 0x4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo global_load_b32 v2, v[2:3], off global_load_b32 v3, v[0:1], off s_waitcnt vmcnt(0) v_fmac_f32_e32 v3, s0, v2 global_store_b32 v[0:1], v3, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5saxpyifPfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 168 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5saxpyifPfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z5saxpyifPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "a84323ec49baf3c4c6dce068e180bceaac53f934.hip" .globl _Z20__device_stub__saxpyifPfS_ # -- Begin function _Z20__device_stub__saxpyifPfS_ .p2align 4, 0x90 .type _Z20__device_stub__saxpyifPfS_,@function _Z20__device_stub__saxpyifPfS_: # @_Z20__device_stub__saxpyifPfS_ .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 12(%rsp) movss %xmm0, 8(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) leaq 72(%rsp), %rax movq %rax, 96(%rsp) leaq 64(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z5saxpyifPfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z20__device_stub__saxpyifPfS_, .Lfunc_end0-_Z20__device_stub__saxpyifPfS_ .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI1_0: .long 0xc0800000 # float -4 .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 .LCPI1_1: .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $136, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movl $4194304, %edi # imm = 0x400000 callq malloc movq %rax, %rbx movl $4194304, %edi # imm = 0x400000 callq malloc movq %rax, %r14 leaq 16(%rsp), %rdi movl $4194304, %esi # imm = 0x400000 callq hipMalloc leaq 8(%rsp), %rdi movl $4194304, %esi # imm = 0x400000 callq hipMalloc xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000 movl $1073741824, (%r14,%rax,4) # imm = 0x40000000 incq %rax cmpq $1048576, %rax # imm = 0x100000 jne .LBB1_1 # %bb.2: movq 16(%rsp), %rdi movl $4194304, %edx # imm = 0x400000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi movl $4194304, %edx # imm = 0x400000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967552, %rdx # imm = 0x100000100 leaq 3840(%rdx), %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 16(%rsp), %rax movq 8(%rsp), %rcx movl $1048576, 28(%rsp) # imm = 0x100000 movl $1073741824, 24(%rsp) # imm = 0x40000000 movq %rax, 88(%rsp) movq %rcx, 80(%rsp) leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 24(%rsp), %rax movq %rax, 104(%rsp) leaq 88(%rsp), %rax movq %rax, 112(%rsp) leaq 80(%rsp), %rax movq %rax, 120(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z5saxpyifPfS_, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: movq 8(%rsp), %rsi movl $4194304, %edx # imm = 0x400000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy xorps %xmm2, %xmm2 xorl %eax, %eax movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN] .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 cvttss2si %xmm2, %ecx movss (%r14,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero addss %xmm0, %xmm2 andps %xmm1, %xmm2 cvttss2si %xmm2, %edx cmpl %edx, %ecx cmovgl %ecx, %edx xorps %xmm2, %xmm2 cvtsi2ss %edx, %xmm2 incq %rax cmpq $1048576, %rax # imm = 0x100000 jne .LBB1_5 # %bb.6: xorps %xmm0, %xmm0 cvtss2sd %xmm2, %xmm0 movl $.L.str, %edi movb $1, %al callq printf movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free movq %r14, %rdi callq free xorl %eax, %eax addq $136, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5saxpyifPfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z5saxpyifPfS_,@object # @_Z5saxpyifPfS_ .section .rodata,"a",@progbits .globl _Z5saxpyifPfS_ .p2align 3, 0x0 _Z5saxpyifPfS_: .quad _Z20__device_stub__saxpyifPfS_ .size _Z5saxpyifPfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Max error: %f\n" .size .L.str, 15 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z5saxpyifPfS_" .size .L__unnamed_1, 15 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z20__device_stub__saxpyifPfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z5saxpyifPfS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
464
3,369
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3,740
169
code for sm_80 Function : _Z6MatMulPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R10, SR_TID.Y ; HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R7, SR_TID.X ; IMAD R10, R10, 0xa, RZ ; IMAD.WIDE R4, R7, R0, c[0x0][0x168] ; IMAD.WIDE R2, R10.reuse, R0, c[0x0][0x160] ; LDG.E R23, [R4.64] ; LDG.E R22, [R2.64] ; LDG.E R24, [R4.64+0x28] ; LDG.E R25, [R2.64+0x4] ; LDG.E R26, [R4.64+0x50] ; LDG.E R27, [R2.64+0x8] ; LDG.E R20, [R4.64+0x78] ; LDG.E R19, [R2.64+0xc] ; LDG.E R18, [R4.64+0xa0] ; LDG.E R17, [R2.64+0x10] ; LDG.E R16, [R4.64+0xc8] ; LDG.E R15, [R2.64+0x14] ; LDG.E R14, [R4.64+0xf0] ; LDG.E R13, [R2.64+0x18] ; LDG.E R12, [R4.64+0x118] ; LDG.E R11, [R2.64+0x1c] ; LDG.E R9, [R4.64+0x140] ; LDG.E R8, [R2.64+0x20] ; LDG.E R6, [R4.64+0x168] ; LDG.E R21, [R2.64+0x24] ; IADD3 R7, R10, R7, RZ ; IMAD.WIDE R2, R7, R0, c[0x0][0x170] ; IMAD R22, R22, R23, RZ ; IMAD R22, R25, R24, R22 ; IMAD R22, R27, R26, R22 ; IMAD R19, R19, R20, R22 ; IMAD R17, R17, R18, R19 ; IMAD R15, R15, R16, R17 ; IMAD R13, R13, R14, R15 ; IMAD R11, R11, R12, R13 ; IMAD R8, R8, R9, R11 ; IMAD R21, R21, R6, R8 ; STG.E [R2.64], R21 ; EXIT ; BRA 0x2a0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0005e463_00000000-6_9af224d5791086ae00e11475d1ab36bb52f565f6.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z30__device_stub__Z6MatMulPiS_S_iPiS_S_i .type _Z30__device_stub__Z6MatMulPiS_S_iPiS_S_i, @function _Z30__device_stub__Z6MatMulPiS_S_iPiS_S_i: .LFB2082: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6MatMulPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z30__device_stub__Z6MatMulPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6MatMulPiS_S_iPiS_S_i .globl _Z6MatMulPiS_S_i .type _Z6MatMulPiS_S_i, @function _Z6MatMulPiS_S_i: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z6MatMulPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z6MatMulPiS_S_i, .-_Z6MatMulPiS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Matrix A: \n" .LC1: .string "%d " .LC2: .string "\n" .LC3: .string "Matrix B: \n" .LC4: .string "Product: \n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $88, %rsp .cfi_def_cfa_offset 144 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $400, %edi call malloc@PLT movq %rax, %r12 movl $400, %edi call malloc@PLT movq %rax, %r13 movq %rax, (%rsp) movl $400, %edi call malloc@PLT movq %rax, 8(%rsp) leaq 400(%r12), %r14 movq %r12, %rbp .L12: movl $0, %ebx .L13: call rand@PLT movslq %eax, %rdx imulq $1717986919, %rdx, %rdx sarq $34, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx leal (%rdx,%rdx,4), %edx addl %edx, %edx subl %edx, %eax movl %eax, 0(%rbp,%rbx) call rand@PLT movslq %eax, %rdx imulq $1717986919, %rdx, %rdx sarq $34, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx leal (%rdx,%rdx,4), %edx addl %edx, %edx subl %edx, %eax movl %eax, 0(%r13,%rbx) addq $4, %rbx cmpq $40, %rbx jne .L13 addq $40, %rbp addq $40, %r13 cmpq %r14, %rbp jne .L12 leaq 24(%rsp), %rdi movl $400, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $400, %esi call cudaMalloc@PLT leaq 40(%rsp), %rdi movl $400, %esi call cudaMalloc@PLT movl $1, %ecx movl $400, %edx movq %r12, %rsi movq 24(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $400, %edx movq (%rsp), %rsi movq 32(%rsp), %rdi call cudaMemcpy@PLT movl $100, 60(%rsp) movl $1, 64(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $0, %r9d movl $0, %r8d movq 60(%rsp), %rdx movl $1, %ecx movq 48(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L31 .L15: movl $2, %ecx movl $400, %edx movq 40(%rsp), %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 40(%r12), %rbp leaq 440(%r12), %r15 leaq .LC1(%rip), %r13 leaq .LC2(%rip), %r14 .L16: leaq -40(%rbp), %rbx .L17: movl (%rbx), %edx movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L17 movq %r14, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $40, %rbp cmpq %r15, %rbp jne .L16 leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq (%rsp), %rax leaq 40(%rax), %rbp leaq 440(%rax), %r15 leaq .LC1(%rip), %r13 leaq .LC2(%rip), %r14 .L19: leaq -40(%rbp), %rbx .L20: movl (%rbx), %edx movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L20 movq %r14, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $40, %rbp cmpq %r15, %rbp jne .L19 leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 8(%rsp), %rax leaq 40(%rax), %rbp leaq 440(%rax), %r15 leaq .LC1(%rip), %r13 leaq .LC2(%rip), %r14 .L22: leaq -40(%rbp), %rbx .L23: movl (%rbx), %edx movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L23 movq %r14, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $40, %rbp cmpq %r15, %rbp jne .L22 leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq %r12, %rdi call free@PLT movq (%rsp), %rdi call free@PLT movq 8(%rsp), %rdi call free@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L32 movl $0, %eax addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L31: .cfi_restore_state movl $10, %ecx movq 40(%rsp), %rdx movq 32(%rsp), %rsi movq 24(%rsp), %rdi call _Z30__device_stub__Z6MatMulPiS_S_iPiS_S_i jmp .L15 .L32: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC5: .string "_Z6MatMulPiS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _Z6MatMulPiS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6MatMulPiS_S_i ; -- Begin function _Z6MatMulPiS_S_i .globl _Z6MatMulPiS_S_i .p2align 8 .type _Z6MatMulPiS_S_i,@function _Z6MatMulPiS_S_i: ; @_Z6MatMulPiS_S_i ; %bb.0: s_load_b128 s[4:7], s[0:1], 0x0 v_bfe_u32 v5, v0, 10, 10 v_and_b32_e32 v6, 0x3ff, v0 v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_u32_u24_e32 v1, 10, v5 v_lshlrev_b32_e32 v0, 2, v1 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b32_e32 v1, 2, v6 s_waitcnt lgkmcnt(0) v_add_co_u32 v7, s2, s4, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v8, null, s5, 0, s2 v_add_co_u32 v0, s2, s6, v1 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s7, 0, s2 s_mov_b64 s[2:3], 0 .p2align 6 .LBB0_1: ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(SALU_CYCLE_1) v_add_co_u32 v3, vcc_lo, v7, s2 v_add_co_ci_u32_e32 v4, vcc_lo, s3, v8, vcc_lo s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 global_load_b32 v9, v[0:1], off global_load_b32 v10, v[3:4], off v_add_co_u32 v0, vcc_lo, v0, 40 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_cmp_eq_u32 s2, 40 s_waitcnt vmcnt(0) v_mad_u64_u32 v[3:4], null, v9, v10, v[2:3] s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v2, v3 s_cbranch_scc0 .LBB0_1 ; %bb.2: s_load_b64 s[0:1], s[0:1], 0x10 v_mul_u32_u24_e32 v0, 10, v5 s_delay_alu instid0(VALU_DEP_1) v_add_lshl_u32 v0, v0, v6, 2 s_waitcnt lgkmcnt(0) global_store_b32 v0, v3, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6MatMulPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 28 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 8 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6MatMulPiS_S_i, .Lfunc_end0-_Z6MatMulPiS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 224 ; NumSgprs: 10 ; NumVgprs: 11 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 10 ; NumVGPRsForWavesPerEU: 11 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 28 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6MatMulPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 10 .sgpr_spill_count: 0 .symbol: _Z6MatMulPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "9af224d5791086ae00e11475d1ab36bb52f565f6.hip" .globl _Z21__device_stub__MatMulPiS_S_i # -- Begin function _Z21__device_stub__MatMulPiS_S_i .p2align 4, 0x90 .type _Z21__device_stub__MatMulPiS_S_i,@function _Z21__device_stub__MatMulPiS_S_i: # @_Z21__device_stub__MatMulPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6MatMulPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z21__device_stub__MatMulPiS_S_i, .Lfunc_end0-_Z21__device_stub__MatMulPiS_S_i .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $152, %rsp .cfi_def_cfa_offset 208 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $400, %edi # imm = 0x190 callq malloc movq %rax, %rbx movl $400, %edi # imm = 0x190 callq malloc movq %rax, %r14 movl $400, %edi # imm = 0x190 callq malloc movq %rax, 32(%rsp) # 8-byte Spill xorl %r12d, %r12d movq %rbx, %r13 movq %r14, %rbp .p2align 4, 0x90 .LBB1_1: # %.preheader57 # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 xorl %r15d, %r15d .p2align 4, 0x90 .LBB1_2: # Parent Loop BB1_1 Depth=1 # => This Inner Loop Header: Depth=2 callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx subl %ecx, %eax movl %eax, (%r13,%r15,4) callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx subl %ecx, %eax movl %eax, (%rbp,%r15,4) incq %r15 cmpq $10, %r15 jne .LBB1_2 # %bb.3: # in Loop: Header=BB1_1 Depth=1 incq %r12 addq $40, %rbp addq $40, %r13 cmpq $10, %r12 jne .LBB1_1 # %bb.4: leaq 16(%rsp), %rdi movl $400, %esi # imm = 0x190 callq hipMalloc leaq 8(%rsp), %rdi movl $400, %esi # imm = 0x190 callq hipMalloc movq %rsp, %rdi movl $400, %esi # imm = 0x190 callq hipMalloc movq 16(%rsp), %rdi movl $400, %edx # imm = 0x190 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi movl $400, %edx # imm = 0x190 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 99(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_6 # %bb.5: movq 16(%rsp), %rax movq 8(%rsp), %rcx movq (%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movl $10, 28(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 28(%rsp), %rax movq %rax, 136(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z6MatMulPiS_S_i, %edi pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_6: movq (%rsp), %rsi movl $400, %edx # imm = 0x190 movq 32(%rsp), %rbp # 8-byte Reload movq %rbp, %rdi movl $2, %ecx callq hipMemcpy movl $.Lstr, %edi callq puts@PLT movq %rbx, %r15 xorl %r12d, %r12d .p2align 4, 0x90 .LBB1_7: # %.preheader56 # =>This Loop Header: Depth=1 # Child Loop BB1_8 Depth 2 xorl %r13d, %r13d .p2align 4, 0x90 .LBB1_8: # Parent Loop BB1_7 Depth=1 # => This Inner Loop Header: Depth=2 movl (%r15,%r13,4), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r13 cmpq $10, %r13 jne .LBB1_8 # %bb.9: # in Loop: Header=BB1_7 Depth=1 movl $10, %edi callq putchar@PLT incq %r12 addq $40, %r15 cmpq $10, %r12 jne .LBB1_7 # %bb.10: movl $10, %edi callq putchar@PLT movl $.Lstr.1, %edi callq puts@PLT movq %r14, %r15 xorl %r12d, %r12d .p2align 4, 0x90 .LBB1_11: # %.preheader55 # =>This Loop Header: Depth=1 # Child Loop BB1_12 Depth 2 xorl %r13d, %r13d .p2align 4, 0x90 .LBB1_12: # Parent Loop BB1_11 Depth=1 # => This Inner Loop Header: Depth=2 movl (%r15,%r13,4), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r13 cmpq $10, %r13 jne .LBB1_12 # %bb.13: # in Loop: Header=BB1_11 Depth=1 movl $10, %edi callq putchar@PLT incq %r12 addq $40, %r15 cmpq $10, %r12 jne .LBB1_11 # %bb.14: movl $.Lstr.2, %edi callq puts@PLT movq %rbp, %r15 xorl %r12d, %r12d .p2align 4, 0x90 .LBB1_15: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_16 Depth 2 xorl %r13d, %r13d .p2align 4, 0x90 .LBB1_16: # Parent Loop BB1_15 Depth=1 # => This Inner Loop Header: Depth=2 movl (%r15,%r13,4), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r13 cmpq $10, %r13 jne .LBB1_16 # %bb.17: # in Loop: Header=BB1_15 Depth=1 movl $10, %edi callq putchar@PLT incq %r12 addq $40, %r15 cmpq $10, %r12 jne .LBB1_15 # %bb.18: movl $10, %edi callq putchar@PLT movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %rbp, %rdi callq free xorl %eax, %eax addq $152, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6MatMulPiS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z6MatMulPiS_S_i,@object # @_Z6MatMulPiS_S_i .section .rodata,"a",@progbits .globl _Z6MatMulPiS_S_i .p2align 3, 0x0 _Z6MatMulPiS_S_i: .quad _Z21__device_stub__MatMulPiS_S_i .size _Z6MatMulPiS_S_i, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "%d " .size .L.str.1, 4 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z6MatMulPiS_S_i" .size .L__unnamed_1, 17 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Matrix A: " .size .Lstr, 11 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "Matrix B: " .size .Lstr.1, 11 .type .Lstr.2,@object # @str.2 .Lstr.2: .asciz "Product: " .size .Lstr.2, 10 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__MatMulPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z6MatMulPiS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z14addVectorsIntoPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R3, R3, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; @P0 EXIT ; MOV R0, c[0x0][0x0] ; ULDC.64 UR4, c[0x0][0x118] ; BSSY B0, 0x340 ; IMAD R0, R0, c[0x0][0xc], RZ ; I2F.U32.RP R6, R0 ; IADD3 R9, RZ, -R0, RZ ; IADD3 R2, R0.reuse, R3, RZ ; ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; IADD3 R7, R7, c[0x0][0x178], R0 ; MUFU.RCP R6, R6 ; IADD3 R4, R6, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; HFMA2.MMA R4, -RZ, RZ, 0, 0 ; IMAD R9, R9, R5, RZ ; IMAD.HI.U32 R2, R5, R9, R4 ; IMAD.HI.U32 R2, R2, R7, RZ ; IADD3 R4, -R2, RZ, RZ ; IMAD R7, R0, R4, R7 ; ISETP.GE.U32.AND P0, PT, R7, R0, PT ; @P0 IADD3 R7, -R0, R7, RZ ; @P0 IADD3 R2, R2, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R7, R0, PT ; @P1 IADD3 R2, R2, 0x1, RZ ; @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; IADD3 R4, R2.reuse, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0x330 ; MOV R8, 0x4 ; MOV R2, R4 ; IMAD.WIDE R4, R3, R8, c[0x0][0x160] ; IMAD.WIDE R6, R3, R8, c[0x0][0x170] ; IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; LDG.E R10, [R6.64] ; LDG.E R11, [R8.64] ; IADD3 R2, R2, -0x1, RZ ; IADD3 R3, R0, R3, RZ ; ISETP.NE.AND P0, PT, R2, RZ, PT ; IMAD.WIDE R6, R0, 0x4, R6 ; IMAD.WIDE R8, R0, 0x4, R8 ; FADD R11, R10, R11 ; STG.E [R4.64], R11 ; IMAD.WIDE R4, R0, 0x4, R4 ; @P0 BRA 0x280 ; BSYNC B0 ; @!P1 EXIT ; HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD.WIDE R6, R3, R8, c[0x0][0x170] ; IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x168] ; LDG.E R2, [R6.64] ; LDG.E R11, [R4.64] ; IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; IMAD.WIDE R12, R0, 0x4, R6 ; FADD R19, R2, R11 ; IMAD.WIDE R10, R0, 0x4, R4 ; STG.E [R8.64], R19 ; LDG.E R2, [R12.64] ; LDG.E R17, [R10.64] ; IMAD.WIDE R14, R0, 0x4, R8 ; IMAD.WIDE R6, R0, 0x4, R12 ; IMAD.WIDE R4, R0, 0x4, R10 ; FADD R21, R2, R17 ; STG.E [R14.64], R21 ; LDG.E R2, [R6.64] ; LDG.E R23, [R4.64] ; IMAD.WIDE R16, R0, 0x4, R14 ; IMAD.WIDE R12, R0, 0x4, R6 ; IMAD.WIDE R8, R0, 0x4, R4 ; FADD R23, R2, R23 ; STG.E [R16.64], R23 ; LDG.E R12, [R12.64] ; LDG.E R9, [R8.64] ; IMAD.WIDE R10, R0.reuse, 0x4, R16 ; IADD3 R3, R0, R3, R0 ; IADD3 R3, R0, R3, R0 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; FADD R15, R12, R9 ; STG.E [R10.64], R15 ; @!P0 BRA 0x350 ; EXIT ; BRA 0x570; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0002c7b2_00000000-6_7b78e7e3869a0d84216cec83d31f129337fcd004.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z8initWithfPfi .type _Z8initWithfPfi, @function _Z8initWithfPfi: .LFB2057: .cfi_startproc endbr64 testl %esi, %esi jle .L3 movq %rdi, %rax movslq %esi, %rsi leaq (%rdi,%rsi,4), %rdx .L5: movss %xmm0, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L5 .L3: ret .cfi_endproc .LFE2057: .size _Z8initWithfPfi, .-_Z8initWithfPfi .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "FAIL: vector[%d] - %0.0f does not equal %0.0f\n" .align 8 .LC1: .string "Success! All values calculated correctly.\n" .text .globl _Z16checkElementsArefPfi .type _Z16checkElementsArefPfi, @function _Z16checkElementsArefPfi: .LFB2058: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 testl %esi, %esi jle .L8 movslq %esi, %rdx movl $0, %eax .L11: movss (%rdi,%rax,4), %xmm2 ucomiss %xmm0, %xmm2 jp .L12 jne .L12 addq $1, %rax cmpq %rdx, %rax jne .L11 .L8: leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L12: .cfi_restore_state cvtss2sd %xmm2, %xmm2 pxor %xmm1, %xmm1 cvtss2sd %xmm0, %xmm1 movapd %xmm2, %xmm0 movl %eax, %edx leaq .LC0(%rip), %rsi movl $2, %edi movl $2, %eax call __printf_chk@PLT movl $1, %edi call exit@PLT .cfi_endproc .LFE2058: .size _Z16checkElementsArefPfi, .-_Z16checkElementsArefPfi .globl _Z39__device_stub__Z14addVectorsIntoPfS_S_iPfS_S_i .type _Z39__device_stub__Z14addVectorsIntoPfS_S_iPfS_S_i, @function _Z39__device_stub__Z14addVectorsIntoPfS_S_iPfS_S_i: .LFB2084: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L19 .L15: movq 136(%rsp), %rax subq %fs:40, %rax jne .L20 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z14addVectorsIntoPfS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L15 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z39__device_stub__Z14addVectorsIntoPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14addVectorsIntoPfS_S_iPfS_S_i .globl _Z14addVectorsIntoPfS_S_i .type _Z14addVectorsIntoPfS_S_i, @function _Z14addVectorsIntoPfS_S_i: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z39__device_stub__Z14addVectorsIntoPfS_S_iPfS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z14addVectorsIntoPfS_S_i, .-_Z14addVectorsIntoPfS_S_i .section .rodata.str1.8 .align 8 .LC2: .string "Device ID: %d\tNumber of SMs: %d\n" .section .rodata.str1.1,"aMS",@progbits,1 .LC6: .string "Error: %s\n" .text .globl main .type main, @function main: .LFB2059: .cfi_startproc endbr64 subq $72, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movq %rsp, %rdi call cudaGetDevice@PLT leaq 4(%rsp), %rdi movl (%rsp), %edx movl $16, %esi call cudaDeviceGetAttribute@PLT movl 4(%rsp), %ecx movl (%rsp), %edx leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 8(%rsp), %rdi movl $1, %edx movl $134217728, %esi call cudaMallocManaged@PLT leaq 16(%rsp), %rdi movl $1, %edx movl $134217728, %esi call cudaMallocManaged@PLT leaq 24(%rsp), %rdi movl $1, %edx movl $134217728, %esi call cudaMallocManaged@PLT movl $33554432, %esi movq 8(%rsp), %rdi movss .LC3(%rip), %xmm0 call _Z8initWithfPfi movl $33554432, %esi movq 16(%rsp), %rdi movss .LC4(%rip), %xmm0 call _Z8initWithfPfi movl $33554432, %esi movq 24(%rsp), %rdi pxor %xmm0, %xmm0 call _Z8initWithfPfi movl 4(%rsp), %eax sall $5, %eax movl $256, 44(%rsp) movl $1, 48(%rsp) movl %eax, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L29 .L24: call cudaGetLastError@PLT testl %eax, %eax jne .L30 .L25: call cudaDeviceSynchronize@PLT testl %eax, %eax jne .L31 .L26: movl $33554432, %esi movq 24(%rsp), %rdi movss .LC7(%rip), %xmm0 call _Z16checkElementsArefPfi movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L32 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L29: .cfi_restore_state movl $33554432, %ecx movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq 24(%rsp), %rdi call _Z39__device_stub__Z14addVectorsIntoPfS_S_iPfS_S_i jmp .L24 .L30: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L25 .L31: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L26 .L32: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size main, .-main .section .rodata.str1.1 .LC8: .string "_Z14addVectorsIntoPfS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC8(%rip), %rdx movq %rdx, %rcx leaq _Z14addVectorsIntoPfS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC3: .long 1077936128 .align 4 .LC4: .long 1082130432 .align 4 .LC7: .long 1088421888 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14addVectorsIntoPfS_S_i ; -- Begin function _Z14addVectorsIntoPfS_S_i .globl _Z14addVectorsIntoPfS_S_i .p2align 8 .type _Z14addVectorsIntoPfS_S_i,@function _Z14addVectorsIntoPfS_S_i: ; @_Z14addVectorsIntoPfS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x2c s_load_b32 s12, s[0:1], 0x18 s_add_u32 s2, s0, 32 s_addc_u32 s3, s1, 0 s_waitcnt lgkmcnt(0) s_and_b32 s8, s4, 0xffff s_mov_b32 s4, exec_lo v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1] s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s12, v1 s_cbranch_execz .LBB0_3 ; %bb.1: ; %.lr.ph.preheader s_load_b32 s9, s[2:3], 0x0 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[2:3], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_lshlrev_b64 v[2:3], 2, v[1:2] s_waitcnt lgkmcnt(0) s_mul_i32 s8, s9, s8 s_ashr_i32 s9, s8, 31 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b64 s[10:11], s[8:9], 2 .p2align 6 .LBB0_2: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_1) v_add_co_u32 v4, vcc_lo, s6, v2 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo v_add_co_u32 v6, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo global_load_b32 v0, v[4:5], off global_load_b32 v6, v[6:7], off v_add_nc_u32_e32 v1, s8, v1 v_add_co_u32 v4, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo v_add_co_u32 v2, vcc_lo, v2, s10 v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo s_waitcnt vmcnt(0) v_add_f32_e32 v0, v0, v6 v_cmp_le_i32_e64 s0, s12, v1 global_store_b32 v[4:5], v0, off s_or_b32 s1, s0, s1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB0_2 .LBB0_3: ; %Flow23 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14addVectorsIntoPfS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14addVectorsIntoPfS_S_i, .Lfunc_end0-_Z14addVectorsIntoPfS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 260 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14addVectorsIntoPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z14addVectorsIntoPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "7b78e7e3869a0d84216cec83d31f129337fcd004.hip" .globl _Z8initWithfPfi # -- Begin function _Z8initWithfPfi .p2align 4, 0x90 .type _Z8initWithfPfi,@function _Z8initWithfPfi: # @_Z8initWithfPfi .cfi_startproc # %bb.0: testl %esi, %esi jle .LBB0_3 # %bb.1: # %.lr.ph.preheader movl %esi, %eax xorl %ecx, %ecx .p2align 4, 0x90 .LBB0_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movss %xmm0, (%rdi,%rcx,4) incq %rcx cmpq %rcx, %rax jne .LBB0_2 .LBB0_3: # %._crit_edge retq .Lfunc_end0: .size _Z8initWithfPfi, .Lfunc_end0-_Z8initWithfPfi .cfi_endproc # -- End function .globl _Z29__device_stub__addVectorsIntoPfS_S_i # -- Begin function _Z29__device_stub__addVectorsIntoPfS_S_i .p2align 4, 0x90 .type _Z29__device_stub__addVectorsIntoPfS_S_i,@function _Z29__device_stub__addVectorsIntoPfS_S_i: # @_Z29__device_stub__addVectorsIntoPfS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z14addVectorsIntoPfS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end1: .size _Z29__device_stub__addVectorsIntoPfS_S_i, .Lfunc_end1-_Z29__device_stub__addVectorsIntoPfS_S_i .cfi_endproc # -- End function .globl _Z16checkElementsArefPfi # -- Begin function _Z16checkElementsArefPfi .p2align 4, 0x90 .type _Z16checkElementsArefPfi,@function _Z16checkElementsArefPfi: # @_Z16checkElementsArefPfi .cfi_startproc # %bb.0: testl %esi, %esi jle .LBB2_4 # %bb.1: # %.lr.ph.preheader movl %esi, %eax xorl %esi, %esi .p2align 4, 0x90 .LBB2_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movss (%rdi,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero ucomiss %xmm0, %xmm1 jne .LBB2_5 jp .LBB2_5 # %bb.3: # in Loop: Header=BB2_2 Depth=1 incq %rsi cmpq %rsi, %rax jne .LBB2_2 .LBB2_4: # %._crit_edge movl $.Lstr, %edi jmp puts@PLT # TAILCALL .LBB2_5: pushq %rax .cfi_def_cfa_offset 16 cvtss2sd %xmm1, %xmm2 xorps %xmm1, %xmm1 cvtss2sd %xmm0, %xmm1 movl $.L.str, %edi # kill: def $esi killed $esi killed $rsi movaps %xmm2, %xmm0 movb $2, %al callq printf movl $1, %edi callq exit .Lfunc_end2: .size _Z16checkElementsArefPfi, .Lfunc_end2-_Z16checkElementsArefPfi .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI3_0: .long 0x40e00000 # float 7 .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI3_1: .quad 0x401c000000000000 # double 7 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $144, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -16 leaq 4(%rsp), %rdi callq hipGetDevice movl 4(%rsp), %edx movq %rsp, %rdi movl $63, %esi callq hipDeviceGetAttribute movl 4(%rsp), %esi movl (%rsp), %edx xorl %ebx, %ebx movl $.L.str.2, %edi xorl %eax, %eax callq printf leaq 24(%rsp), %rdi movl $134217728, %esi # imm = 0x8000000 movl $1, %edx callq hipMallocManaged leaq 16(%rsp), %rdi movl $134217728, %esi # imm = 0x8000000 movl $1, %edx callq hipMallocManaged leaq 8(%rsp), %rdi movl $134217728, %esi # imm = 0x8000000 movl $1, %edx callq hipMallocManaged movq 24(%rsp), %rax .p2align 4, 0x90 .LBB3_1: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 movl $1077936128, (%rax,%rbx,4) # imm = 0x40400000 incq %rbx cmpq $33554432, %rbx # imm = 0x2000000 jne .LBB3_1 # %bb.2: # %_Z8initWithfPfi.exit movq 16(%rsp), %rax xorl %ecx, %ecx .p2align 4, 0x90 .LBB3_3: # %.lr.ph.i15 # =>This Inner Loop Header: Depth=1 movl $1082130432, (%rax,%rcx,4) # imm = 0x40800000 incq %rcx cmpq $33554432, %rcx # imm = 0x2000000 jne .LBB3_3 # %bb.4: # %_Z8initWithfPfi.exit19 movq 8(%rsp), %rdi movl $134217728, %edx # imm = 0x8000000 xorl %esi, %esi callq memset@PLT movl (%rsp), %edi shll $5, %edi movabsq $4294967296, %rdx # imm = 0x100000000 orq %rdx, %rdi orq $256, %rdx # imm = 0x100 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_6 # %bb.5: movq 8(%rsp), %rax movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movl $33554432, 36(%rsp) # imm = 0x2000000 leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 36(%rsp), %rax movq %rax, 136(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z14addVectorsIntoPfS_S_i, %edi pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_6: callq hipGetLastError testl %eax, %eax je .LBB3_8 # %bb.7: movl %eax, %edi callq hipGetErrorString movl $.L.str.3, %edi movq %rax, %rsi xorl %eax, %eax callq printf .LBB3_8: callq hipDeviceSynchronize testl %eax, %eax je .LBB3_10 # %bb.9: movl %eax, %edi callq hipGetErrorString movl $.L.str.3, %edi movq %rax, %rsi xorl %eax, %eax callq printf .LBB3_10: movq 8(%rsp), %rax xorl %esi, %esi movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero .p2align 4, 0x90 .LBB3_11: # %.lr.ph.i25 # =>This Inner Loop Header: Depth=1 movss (%rax,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero ucomiss %xmm0, %xmm1 jne .LBB3_14 jp .LBB3_14 # %bb.12: # in Loop: Header=BB3_11 Depth=1 incq %rsi cmpq $33554432, %rsi # imm = 0x2000000 jne .LBB3_11 # %bb.13: # %_Z16checkElementsArefPfi.exit movl $.Lstr, %edi callq puts@PLT movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax addq $144, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .LBB3_14: .cfi_def_cfa_offset 160 xorps %xmm0, %xmm0 cvtss2sd %xmm1, %xmm0 movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero movl $.L.str, %edi # kill: def $esi killed $esi killed $rsi movb $2, %al callq printf movl $1, %edi callq exit .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14addVectorsIntoPfS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z14addVectorsIntoPfS_S_i,@object # @_Z14addVectorsIntoPfS_S_i .section .rodata,"a",@progbits .globl _Z14addVectorsIntoPfS_S_i .p2align 3, 0x0 _Z14addVectorsIntoPfS_S_i: .quad _Z29__device_stub__addVectorsIntoPfS_S_i .size _Z14addVectorsIntoPfS_S_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "FAIL: vector[%d] - %0.0f does not equal %0.0f\n" .size .L.str, 47 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Device ID: %d\tNumber of SMs: %d\n" .size .L.str.2, 33 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Error: %s\n" .size .L.str.3, 11 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z14addVectorsIntoPfS_S_i" .size .L__unnamed_1, 26 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Success! All values calculated correctly." .size .Lstr, 42 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__addVectorsIntoPfS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14addVectorsIntoPfS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
2,021
3,963
2,901
5,000
171
code for sm_80 Function : _Z4ScanPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R3, SR_CTAID.X ; IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; S2R R2, SR_TID.X ; IMAD R0, R3, c[0x0][0x0], R2 ; IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; LDG.E R5, [R4.64] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; ISETP.GE.U32.AND P0, PT, R3, 0x2, PT ; STS [R2.X4], R5 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P0 BRA 0x300 ; IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; ISETP.GE.U32.AND P0, PT, R2, R7, PT ; BSSY B0, 0x2d0 ; SHF.L.U32 R4, R7, 0x1, RZ ; IMAD.MOV.U32 R11, RZ, RZ, R7 ; IMAD.MOV.U32 R7, RZ, RZ, R4 ; @!P0 BRA 0x2c0 ; I2F.U32.RP R6, R7 ; IMAD.MOV R9, RZ, RZ, -R7 ; ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; MUFU.RCP R6, R6 ; IADD3 R4, R6, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; HFMA2.MMA R4, -RZ, RZ, 0, 0 ; IMAD R9, R9, R5, RZ ; IMAD.HI.U32 R5, R5, R9, R4 ; IMAD.HI.U32 R5, R5, R2, RZ ; IMAD.MOV R5, RZ, RZ, -R5 ; IMAD R8, R7.reuse, R5, R2 ; IADD3 R5, R7, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R8, R7, PT ; @P0 IMAD.IADD R8, R8, 0x1, -R7 ; ISETP.GE.U32.AND P0, PT, R8, R7, PT ; @P0 IMAD.IADD R8, R8, 0x1, -R7 ; @!P1 LOP3.LUT R8, RZ, R7, RZ, 0x33, !PT ; ISETP.NE.AND P0, PT, R8, R5, PT ; @!P0 IADD3 R4, R2, -R11, RZ ; @!P0 LDS R5, [R2.X4] ; @!P0 LDS R4, [R4.X4] ; @!P0 IMAD.IADD R5, R5, 0x1, R4 ; @!P0 STS [R2.X4], R5 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x0], PT ; @!P0 BRA 0xe0 ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; IADD3 R5, R4, -0x1, RZ ; SHF.R.U32.HI R4, RZ, 0x1, R4 ; ISETP.NE.AND P0, PT, R2, R5, PT ; ISETP.NE.AND P1, PT, R4, RZ, PT ; @!P0 STS [R2.X4], RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P1 BRA 0x570 ; IMAD.MOV.U32 R7, RZ, RZ, R4 ; LOP3.LUT P0, R3, R3, 0xfffffffe, RZ, 0xc0, !PT ; I2F.U32.RP R6, R3 ; IADD3 R9, RZ, -R3, RZ ; MUFU.RCP R6, R6 ; IADD3 R4, R6, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; IMAD R9, R9, R5, RZ ; IMAD.HI.U32 R5, R5, R9, R4 ; IMAD.HI.U32 R5, R5, R2, RZ ; IMAD.MOV R5, RZ, RZ, -R5 ; IMAD R8, R3.reuse, R5, R2 ; IADD3 R5, R3, -0x1, RZ ; ISETP.GE.U32.AND P1, PT, R8, R3, PT ; @P1 IADD3 R8, -R3, R8, RZ ; ISETP.GE.U32.AND P1, PT, R8, R3, PT ; @P1 IMAD.IADD R8, R8, 0x1, -R3 ; @!P0 LOP3.LUT R8, RZ, R3, RZ, 0x33, !PT ; ISETP.NE.AND P0, PT, R8, R5, PT ; @!P0 LDS R5, [R2.X4] ; @!P0 IMAD.IADD R4, R2, 0x1, -R7 ; @!P0 LDS R3, [R4.X4] ; @!P0 STS [R4.X4], R5 ; @!P0 LDS R6, [R2.X4] ; @!P0 IADD3 R9, R3, R6, RZ ; IMAD.MOV.U32 R3, RZ, RZ, R7.reuse ; SHF.R.U32.HI R7, RZ, 0x1, R7 ; @!P0 STS [R2.X4], R9 ; ISETP.NE.AND P0, PT, R7, RZ, PT ; @P0 BRA 0x390 ; LDS R3, [R2.X4] ; LEA R4, P0, R0, c[0x0][0x168], 0x2 ; LEA.HI.X R5, R0, c[0x0][0x16c], RZ, 0x2, P0 ; STG.E [R4.64], R3 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; EXIT ; BRA 0x5d0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000b2171_00000000-6_a1f3c0716eed693aa34399643612a20139b4b24c.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z25__device_stub__Z4ScanPiS_PiS_ .type _Z25__device_stub__Z4ScanPiS_PiS_, @function _Z25__device_stub__Z4ScanPiS_PiS_: .LFB3694: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z4ScanPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z25__device_stub__Z4ScanPiS_PiS_, .-_Z25__device_stub__Z4ScanPiS_PiS_ .globl _Z4ScanPiS_ .type _Z4ScanPiS_, @function _Z4ScanPiS_: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z25__device_stub__Z4ScanPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z4ScanPiS_, .-_Z4ScanPiS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string " elapsed" .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $64, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movl $16777216, %edi call _Znam@PLT movq %rax, %rbx leaq 16777216(%rax), %rdx .L12: movl $1, (%rax) addq $4, %rax cmpq %rdx, %rax jne .L12 movq %rsp, %rdi movl $16777216, %esi call cudaMalloc@PLT movl $1, %ecx movl $16777216, %edx movq %rbx, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT leaq 8(%rsp), %rdi movl $16777216, %esi call cudaMalloc@PLT movl $16777216, %edi call _Znam@PLT movq %rax, %rbp leaq 16(%rsp), %rdi call cudaEventCreate@PLT leaq 24(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 16(%rsp), %rdi call cudaEventRecord@PLT movl $256, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $16384, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $1024, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L17 .L13: movl $0, %esi movq 24(%rsp), %rdi call cudaEventRecord@PLT movl $2, %ecx movl $16777216, %edx movq 8(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT movq 24(%rsp), %rdi call cudaEventSynchronize@PLT movl $0x00000000, 44(%rsp) leaq 44(%rsp), %rdi movq 24(%rsp), %rdx movq 16(%rsp), %rsi call cudaEventElapsedTime@PLT pxor %xmm0, %xmm0 cvtss2sd 44(%rsp), %xmm0 leaq _ZSt4cout(%rip), %r12 movq %r12, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC1(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl 16777212(%rbp), %esi movq %r12, %rdi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rbx, %rdi call _ZdaPv@PLT movq %rbp, %rdi call _ZdaPv@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L18 movl $0, %eax addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L17: .cfi_restore_state movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z25__device_stub__Z4ScanPiS_PiS_ jmp .L13 .L18: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1 .LC2: .string "_Z4ScanPiS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z4ScanPiS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z4ScanPiS_ ; -- Begin function _Z4ScanPiS_ .globl _Z4ScanPiS_ .p2align 8 .type _Z4ScanPiS_,@function _Z4ScanPiS_: ; @_Z4ScanPiS_ ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b64 s[4:5], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_mov_b32_e32 v2, 0 s_cmp_lt_u32 s2, 2 v_lshlrev_b64 v[3:4], 2, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo global_load_b32 v4, v[3:4], off v_lshl_add_u32 v3, v0, 2, 0 s_waitcnt vmcnt(0) ds_store_b32 v3, v4 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_6 ; %bb.1: ; %.lr.ph.preheader s_mov_b32 s3, 1 s_set_inst_prefetch_distance 0x1 s_branch .LBB0_3 .p2align 6 .LBB0_2: ; in Loop: Header=BB0_3 Depth=1 s_or_b32 exec_lo, exec_lo, s4 s_lshl_b32 s3, s3, 1 s_waitcnt lgkmcnt(0) s_cmp_ge_u32 s3, s2 s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_6 .LBB0_3: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_mov_b32 s4, exec_lo v_cmpx_le_u32_e64 s3, v0 s_cbranch_execz .LBB0_2 ; %bb.4: ; in Loop: Header=BB0_3 Depth=1 s_lshl_b32 s5, s3, 1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s5, s5, -1 v_and_b32_e32 v4, s5, v0 s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, s5, v4 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_2 ; %bb.5: ; in Loop: Header=BB0_3 Depth=1 v_subrev_nc_u32_e32 v4, s3, v0 s_delay_alu instid0(VALU_DEP_1) v_lshl_add_u32 v4, v4, 2, 0 ds_load_b32 v4, v4 ds_load_b32 v5, v3 s_waitcnt lgkmcnt(0) v_add_nc_u32_e32 v4, v5, v4 ds_store_b32 v3, v4 s_branch .LBB0_2 .LBB0_6: ; %._crit_edge s_set_inst_prefetch_distance 0x2 s_add_i32 s3, s2, -1 s_delay_alu instid0(SALU_CYCLE_1) v_cmp_eq_u32_e32 vcc_lo, s3, v0 s_and_saveexec_b32 s3, vcc_lo s_cbranch_execz .LBB0_8 ; %bb.7: v_mov_b32_e32 v4, 0 ds_store_b32 v3, v4 .LBB0_8: s_or_b32 exec_lo, exec_lo, s3 s_cmp_lt_u32 s2, 2 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_13 ; %bb.9: v_cvt_f32_u32_e32 v4, v0 s_set_inst_prefetch_distance 0x1 s_branch .LBB0_11 .p2align 6 .LBB0_10: ; in Loop: Header=BB0_11 Depth=1 s_or_b32 exec_lo, exec_lo, s4 s_cmp_lt_u32 s2, 4 s_mov_b32 s2, s3 s_cbranch_scc1 .LBB0_13 .LBB0_11: ; %.lr.ph41 ; =>This Inner Loop Header: Depth=1 s_and_b32 s3, s2, 0xfffe s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_f32_u32_e32 v5, s3 v_rcp_iflag_f32_e32 v6, v5 s_waitcnt_depctr 0xfff v_mul_f32_e32 v6, v4, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_trunc_f32_e32 v6, v6 v_fma_f32 v7, -v6, v5, v4 v_cvt_u32_f32_e32 v6, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_ge_f32_e64 vcc_lo, |v7|, |v5| v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mul_lo_u32 v5, v5, s3 s_add_i32 s3, s3, -1 v_sub_nc_u32_e32 v5, v0, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v5, 0xffff, v5 v_cmp_eq_u32_e32 vcc_lo, s3, v5 s_lshr_b32 s3, s2, 1 s_and_saveexec_b32 s4, vcc_lo s_cbranch_execz .LBB0_10 ; %bb.12: ; in Loop: Header=BB0_11 Depth=1 ds_load_b32 v5, v3 v_subrev_nc_u32_e32 v6, s3, v0 s_delay_alu instid0(VALU_DEP_1) v_lshl_add_u32 v6, v6, 2, 0 ds_load_b32 v7, v6 s_waitcnt lgkmcnt(1) ds_store_b32 v6, v5 ds_load_b32 v5, v3 s_waitcnt lgkmcnt(0) v_add_nc_u32_e32 v5, v5, v7 ds_store_b32 v3, v5 s_branch .LBB0_10 .LBB0_13: ; %._crit_edge42 s_set_inst_prefetch_distance 0x2 s_load_b64 s[0:1], s[0:1], 0x8 ds_load_b32 v3, v3 v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v3, off s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z4ScanPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z4ScanPiS_, .Lfunc_end0-_Z4ScanPiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 620 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims - .offset: 136 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z4ScanPiS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z4ScanPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "a1f3c0716eed693aa34399643612a20139b4b24c.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z19__device_stub__ScanPiS_ # -- Begin function _Z19__device_stub__ScanPiS_ .p2align 4, 0x90 .type _Z19__device_stub__ScanPiS_,@function _Z19__device_stub__ScanPiS_: # @_Z19__device_stub__ScanPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z4ScanPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z19__device_stub__ScanPiS_, .Lfunc_end0-_Z19__device_stub__ScanPiS_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $120, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $16777216, %edi # imm = 0x1000000 callq _Znam movq %rax, %rbx xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1, (%rbx,%rax,4) incq %rax cmpq $4194304, %rax # imm = 0x400000 jne .LBB1_1 # %bb.2: leaq 48(%rsp), %rdi movl $16777216, %esi # imm = 0x1000000 callq hipMalloc movq 48(%rsp), %rdi movl $16777216, %edx # imm = 0x1000000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy leaq 40(%rsp), %rdi movl $16777216, %esi # imm = 0x1000000 callq hipMalloc movl $16777216, %edi # imm = 0x1000000 callq _Znam movq %rax, %r14 leaq 32(%rsp), %rdi callq hipEventCreate leaq 8(%rsp), %rdi callq hipEventCreate movq 32(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movabsq $4294967552, %rdx # imm = 0x100000100 leaq 16128(%rdx), %rdi movl $1024, %r8d # imm = 0x400 movl $1, %esi movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 48(%rsp), %rax movq 40(%rsp), %rcx movq %rax, 112(%rsp) movq %rcx, 104(%rsp) leaq 112(%rsp), %rax movq %rax, 16(%rsp) leaq 104(%rsp), %rax movq %rax, 24(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 16(%rsp), %r9 movl $_Z4ScanPiS_, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: movq 8(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 40(%rsp), %rsi movl $16777216, %edx # imm = 0x1000000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy movq 8(%rsp), %rdi callq hipEventSynchronize movl $0, 16(%rsp) movq 32(%rsp), %rsi movq 8(%rsp), %rdx leaq 16(%rsp), %rdi callq hipEventElapsedTime movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r15 movl $.L.str, %esi movl $8, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%r15), %rax movq -24(%rax), %rax movq 240(%r15,%rax), %r12 testq %r12, %r12 je .LBB1_13 # %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r12) je .LBB1_7 # %bb.6: movzbl 67(%r12), %eax jmp .LBB1_8 .LBB1_7: movq %r12, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r12), %rax movq %r12, %rdi movl $10, %esi callq *48(%rax) .LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movq %r15, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl 16777212(%r14), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %r15 testq %r15, %r15 je .LBB1_13 # %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i13 cmpb $0, 56(%r15) je .LBB1_11 # %bb.10: movzbl 67(%r15), %ecx jmp .LBB1_12 .LBB1_11: movq %r15, %rdi movq %rax, %r12 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r12, %rax .LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit16 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv xorl %eax, %eax addq $120, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB1_13: .cfi_def_cfa_offset 160 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z4ScanPiS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z4ScanPiS_,@object # @_Z4ScanPiS_ .section .rodata,"a",@progbits .globl _Z4ScanPiS_ .p2align 3, 0x0 _Z4ScanPiS_: .quad _Z19__device_stub__ScanPiS_ .size _Z4ScanPiS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz " elapsed" .size .L.str, 9 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z4ScanPiS_" .size .L__unnamed_1, 12 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z19__device_stub__ScanPiS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z4ScanPiS_ .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
2,227
3,149
4,011
4,065
172
code for sm_80 Function : _Z9gpu_wherePfS_S_S_l .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R0, R0, c[0x0][0x0], R3 ; ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x184], PT, P0 ; @P0 EXIT ; IMAD.SHL.U32 R6, R0, 0x4, RZ ; SHF.R.U32.HI R0, RZ, 0x1e, R0 ; ULDC.64 UR4, c[0x0][0x118] ; IADD3 R4, P0, R6, c[0x0][0x160], RZ ; IADD3.X R5, R0, c[0x0][0x164], RZ, P0, !PT ; LDG.E R4, [R4.64] ; IADD3 R2, P1, R6, c[0x0][0x178], RZ ; IADD3.X R3, R0, c[0x0][0x17c], RZ, P1, !PT ; FSETP.NEU.AND P0, PT, R4, RZ, PT ; @P0 BRA 0x160 ; IADD3 R4, P0, R6, c[0x0][0x170], RZ ; IADD3.X R5, R0, c[0x0][0x174], RZ, P0, !PT ; LDG.E R5, [R4.64] ; STG.E [R2.64], R5 ; EXIT ; IADD3 R4, P0, R6, c[0x0][0x168], RZ ; IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; LDG.E R5, [R4.64] ; STG.E [R2.64], R5 ; EXIT ; BRA 0x1b0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0004bd96_00000000-6_e1e2bb9de09a256ea9ea0c4de44077aa3bf493a5.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3671: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3671: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z35__device_stub__Z9gpu_wherePfS_S_S_lPfS_S_S_l .type _Z35__device_stub__Z9gpu_wherePfS_S_S_lPfS_S_S_l, @function _Z35__device_stub__Z9gpu_wherePfS_S_S_lPfS_S_S_l: .LFB3693: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movq %r8, 8(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 152(%rsp), %rax subq %fs:40, %rax jne .L8 addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 184 pushq 56(%rsp) .cfi_def_cfa_offset 192 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z9gpu_wherePfS_S_S_l(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 176 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3693: .size _Z35__device_stub__Z9gpu_wherePfS_S_S_lPfS_S_S_l, .-_Z35__device_stub__Z9gpu_wherePfS_S_S_lPfS_S_S_l .globl _Z9gpu_wherePfS_S_S_l .type _Z9gpu_wherePfS_S_S_l, @function _Z9gpu_wherePfS_S_S_l: .LFB3694: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z9gpu_wherePfS_S_S_lPfS_S_S_l addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3694: .size _Z9gpu_wherePfS_S_S_l, .-_Z9gpu_wherePfS_S_S_l .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z9gpu_wherePfS_S_S_l" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3696: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z9gpu_wherePfS_S_S_l(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3696: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9gpu_wherePfS_S_S_l ; -- Begin function _Z9gpu_wherePfS_S_S_l .globl _Z9gpu_wherePfS_S_S_l .p2align 8 .type _Z9gpu_wherePfS_S_S_l,@function _Z9gpu_wherePfS_S_S_l: ; @_Z9gpu_wherePfS_S_S_l ; %bb.0: s_clause 0x1 s_load_b32 s4, s[0:1], 0x34 s_load_b64 s[2:3], s[0:1], 0x20 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] v_mov_b32_e32 v2, 0 v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2] s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_2 ; %bb.1: ; %.sink.split s_load_b256 s[0:7], s[0:1], 0x0 v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo v_mov_b32_e32 v4, s2 global_load_b32 v2, v[2:3], off v_mov_b32_e32 v3, s3 s_waitcnt vmcnt(0) v_cmp_neq_f32_e32 vcc_lo, 0, v2 v_cndmask_b32_e32 v2, s4, v4, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v3, s5, v3, vcc_lo v_add_co_u32 v2, vcc_lo, v2, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, v3, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo global_load_b32 v2, v[2:3], off s_waitcnt vmcnt(0) global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9gpu_wherePfS_S_S_l .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9gpu_wherePfS_S_S_l, .Lfunc_end0-_Z9gpu_wherePfS_S_S_l ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 192 ; NumSgprs: 18 ; NumVgprs: 5 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 5 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 8 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9gpu_wherePfS_S_S_l .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z9gpu_wherePfS_S_S_l.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "e1e2bb9de09a256ea9ea0c4de44077aa3bf493a5.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z24__device_stub__gpu_wherePfS_S_S_l # -- Begin function _Z24__device_stub__gpu_wherePfS_S_S_l .p2align 4, 0x90 .type _Z24__device_stub__gpu_wherePfS_S_S_l,@function _Z24__device_stub__gpu_wherePfS_S_S_l: # @_Z24__device_stub__gpu_wherePfS_S_S_l .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z9gpu_wherePfS_S_S_l, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end0: .size _Z24__device_stub__gpu_wherePfS_S_S_l, .Lfunc_end0-_Z24__device_stub__gpu_wherePfS_S_S_l .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9gpu_wherePfS_S_S_l, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z9gpu_wherePfS_S_S_l,@object # @_Z9gpu_wherePfS_S_S_l .section .rodata,"a",@progbits .globl _Z9gpu_wherePfS_S_S_l .p2align 3, 0x0 _Z9gpu_wherePfS_S_S_l: .quad _Z24__device_stub__gpu_wherePfS_S_S_l .size _Z9gpu_wherePfS_S_S_l, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z9gpu_wherePfS_S_S_l" .size .L__unnamed_1, 22 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__gpu_wherePfS_S_S_l .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9gpu_wherePfS_S_S_l .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
819
1,987
2,729
1,903
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code for sm_80 Function : _Z9scol2im_fPfPKfiiiiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R3, SR_CTAID.X ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; S2R R2, SR_TID.X ; IMAD R0, R0, c[0x0][0x170], RZ ; IMAD R3, R3, c[0x0][0x0], R2 ; IMAD R2, R0, c[0x0][0x178], RZ ; ISETP.GE.AND P0, PT, R3, R2, PT ; @P0 EXIT ; ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT ; ULDC UR5, c[0x0][0xc] ; ULDC UR4, c[0x0][0x0] ; ULDC UR7, c[0x0][0x170] ; ULDC UR6, c[0x0][0x17c] ; UIMAD UR5, UR5, UR4, URZ ; UIADD3 UR6, UR7, -UR6, URZ ; ULDC.64 UR12, c[0x0][0x118] ; @P0 BRA 0xa10 ; I2F.U32.RP R6, UR5 ; IADD3 R4, R3, UR5, RZ ; BSSY B0, 0x4d0 ; ISETP.NE.U32.AND P2, PT, RZ, UR5, PT ; LOP3.LUT R7, RZ, R4, RZ, 0x33, !PT ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; IADD3 R7, R7, UR5, R2 ; MUFU.RCP R6, R6 ; IADD3 R5, R6, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; IMAD.MOV R9, RZ, RZ, -R5 ; IMAD R9, R9, UR5, RZ ; IMAD.HI.U32 R4, R5, R9, R4 ; IMAD.HI.U32 R4, R4, R7, RZ ; IMAD.MOV R6, RZ, RZ, -R4 ; IMAD R7, R6, UR5, R7 ; ISETP.GE.U32.AND P0, PT, R7, UR5, PT ; @P0 IADD3 R7, R7, -UR5, RZ ; @P0 IADD3 R4, R4, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R7, UR5, PT ; @P1 IADD3 R4, R4, 0x1, RZ ; @!P2 LOP3.LUT R4, RZ, UR5, RZ, 0x33, !PT ; IADD3 R5, R4.reuse, 0x1, RZ ; ISETP.GE.U32.AND P3, PT, R4, 0x3, PT ; LOP3.LUT P0, R5, R5, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0x4c0 ; IABS R4, R0.reuse ; IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; IABS R10, R0.reuse ; I2F.RP R8, R4 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; IABS R12, R0 ; IMAD.MOV R10, RZ, RZ, -R10 ; MUFU.RCP R8, R8 ; IADD3 R6, R8, 0xffffffe, RZ ; LOP3.LUT R8, RZ, R0, RZ, 0x33, !PT ; F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV R9, RZ, RZ, -R7 ; IMAD R9, R9, R4, RZ ; IMAD.HI.U32 R9, R7, R9, R6 ; IABS R7, R3 ; ISETP.GE.AND P2, PT, R3, RZ, PT ; IADD3 R5, R5, -0x1, RZ ; IMAD.HI.U32 R6, R9, R7, RZ ; IMAD R7, R6, R10, R7 ; ISETP.GT.U32.AND P1, PT, R4, R7, PT ; @!P1 IMAD.IADD R7, R7, 0x1, -R12 ; ISETP.GT.U32.AND P1, PT, R4, R7, PT ; @!P1 IMAD.IADD R7, R7, 0x1, -R12 ; ISETP.NE.AND P1, PT, R5, RZ, PT ; @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; SEL R6, R8, R7, !P0 ; IADD3 R6, R3.reuse, R3, -R6 ; IADD3 R3, R3, UR5, RZ ; IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; STG.E [R6.64], RZ ; @P1 BRA 0x3b0 ; BSYNC B0 ; @!P3 EXIT ; IABS R4, R0 ; I2F.RP R8, R4 ; MUFU.RCP R8, R8 ; IADD3 R6, R8, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV R5, RZ, RZ, -R7 ; IMAD R5, R5, R4, RZ ; IMAD.HI.U32 R5, R7, R5, R6 ; IABS R9, R0.reuse ; IABS R12, R3 ; I2F.RP R6, R9 ; IABS R7, R0 ; IMAD.HI.U32 R5, R5, R12, RZ ; IMAD.MOV R15, RZ, RZ, -R7 ; IADD3 R7, R3, UR5, RZ ; IMAD R12, R5, R15, R12 ; IADD3 R8, R7.reuse, UR5, RZ ; IABS R14, R7 ; MUFU.RCP R6, R6 ; ISETP.GT.U32.AND P0, PT, R4, R12, PT ; IABS R16, R8 ; ISETP.GE.AND P6, PT, R7, RZ, PT ; ISETP.GE.AND P5, PT, R8, RZ, PT ; @!P0 IMAD.IADD R12, R12, 0x1, -R9.reuse ; IADD3 R10, R6, 0xffffffe, RZ ; IADD3 R6, R8, UR5, RZ ; F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; ISETP.GT.U32.AND P4, PT, R4, R12, PT ; IMAD.MOV.U32 R4, RZ, RZ, R9 ; IABS R18, R6 ; @!P4 IMAD.IADD R12, R12, 0x1, -R9 ; ISETP.GE.AND P4, PT, R6, RZ, PT ; IADD3 R10, RZ, -R11, RZ ; IMAD R5, R10, R9, RZ ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; IMAD.HI.U32 R5, R11, R5, R10 ; IMAD.HI.U32 R10, R5, R14, RZ ; IMAD.HI.U32 R11, R5, R16, RZ ; IMAD.HI.U32 R13, R5, R18, RZ ; IMAD R10, R10, R15.reuse, R14 ; LOP3.LUT R14, RZ, R0, RZ, 0x33, !PT ; IMAD R11, R11, R15.reuse, R16 ; IMAD R13, R13, R15, R18 ; ISETP.GT.U32.AND P0, PT, R4.reuse, R10, PT ; IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; ISETP.GT.U32.AND P1, PT, R4.reuse, R11, PT ; ISETP.GT.U32.AND P2, PT, R4, R13, PT ; @!P0 IMAD.IADD R10, R10, 0x1, -R9.reuse ; ISETP.GE.AND P0, PT, R3, RZ, PT ; @!P1 IMAD.IADD R11, R11, 0x1, -R9.reuse ; @!P2 IMAD.IADD R13, R13, 0x1, -R9 ; ISETP.GT.U32.AND P1, PT, R4.reuse, R10, PT ; ISETP.GT.U32.AND P2, PT, R4.reuse, R11, PT ; ISETP.GT.U32.AND P3, PT, R4, R13, PT ; @!P0 IMAD.MOV R12, RZ, RZ, -R12 ; @!P1 IMAD.IADD R10, R10, 0x1, -R9.reuse ; ISETP.NE.AND P1, PT, R0, RZ, PT ; @!P2 IMAD.IADD R11, R11, 0x1, -R9.reuse ; @!P3 IMAD.IADD R13, R13, 0x1, -R9 ; SEL R12, R14.reuse, R12, !P1 ; @!P6 IMAD.MOV R10, RZ, RZ, -R10 ; @!P5 IADD3 R11, -R11, RZ, RZ ; @!P4 IMAD.MOV R13, RZ, RZ, -R13 ; IADD3 R9, R3, R3, -R12 ; SEL R10, R14, R10, !P1 ; SEL R11, R14.reuse, R11, !P1 ; SEL R13, R14, R13, !P1 ; IADD3 R10, R7, R7, -R10 ; IADD3 R12, R8, R8, -R11 ; IMAD.WIDE R8, R9, R15.reuse, c[0x0][0x160] ; IADD3 R14, R6.reuse, R6, -R13 ; IADD3 R3, R6, UR5, RZ ; IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x160] ; STG.E [R8.64], RZ ; ISETP.GE.AND P0, PT, R3, R2, PT ; IMAD.WIDE R12, R12, R15.reuse, c[0x0][0x160] ; STG.E [R10.64], RZ ; IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; STG.E [R12.64], RZ ; STG.E [R14.64], RZ ; @!P0 BRA 0x570 ; EXIT ; IABS R8, c[0x0][0x178] ; ULDC.64 UR8, c[0x0][0x180] ; IABS R9, c[0x0][0x184] ; ULDC.64 UR10, c[0x0][0x178] ; I2F.RP R6, R8 ; ULOP3.LUT UR4, UR9, UR10, URZ, 0x3c, !UPT ; ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; UIADD3 UR7, UR7, 0x1, -UR11 ; ULDC UR9, c[0x0][0x174] ; ISETP.LE.AND P3, PT, RZ, UR4, PT ; UIADD3 UR4, -UR8, UR9, URZ ; UIMAD UR8, UR8, UR11, URZ ; UMOV UR9, 0xfffffffc ; UIADD3 UR10, UR6, 0x1, URZ ; MUFU.RCP R6, R6 ; UIMAD UR8, UR8, UR9, 0x4 ; IADD3 R4, R6, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; IMAD.MOV R7, RZ, RZ, -R5 ; IMAD R7, R7, R8, RZ ; IMAD.HI.U32 R5, R5, R7, R4 ; IMAD.MOV.U32 R7, RZ, RZ, R9 ; IMAD.HI.U32 R4, R5, R7, RZ ; IMAD.MOV R5, RZ, RZ, -R4 ; IMAD R5, R8, R5, R7 ; ISETP.GT.U32.AND P2, PT, R8, R5, PT ; @!P2 IMAD.IADD R5, R5, 0x1, -R8 ; @!P2 IADD3 R4, R4, 0x1, RZ ; ISETP.GE.U32.AND P0, PT, R5, R8, PT ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; IADD3 R6, R5.reuse, -0x1, RZ ; LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P2, PT, R6, 0x3, PT ; IADD3 R6, R5, -c[0x0][0x17c], RZ ; @P0 IADD3 R4, R4, 0x1, RZ ; @!P3 IMAD.MOV R4, RZ, RZ, -R4 ; @!P1 LOP3.LUT R4, RZ, c[0x0][0x178], RZ, 0x33, !PT ; IABS R10, c[0x0][0x170] ; IABS R7, R0 ; I2F.RP R11, R10 ; ISETP.NE.AND P6, PT, R0, RZ, PT ; I2F.RP R14, R7 ; MUFU.RCP R11, R11 ; MUFU.RCP R14, R14 ; IADD3 R12, R11, 0xffffffe, RZ ; IABS R11, R3 ; F2I.FTZ.U32.TRUNC.NTZ R13, R12 ; IADD3 R8, R14, 0xffffffe, RZ ; IABS R14, R0 ; F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; IMAD.MOV R14, RZ, RZ, -R14 ; IMAD.MOV R15, RZ, RZ, -R13 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; IMAD R15, R15, R10, RZ ; IMAD.MOV R16, RZ, RZ, -R9 ; IMAD.HI.U32 R13, R13, R15, R12 ; MOV R12, R16 ; IMAD.HI.U32 R13, R13, R11, RZ ; IMAD R15, R12, R7, RZ ; IMAD.MOV R12, RZ, RZ, -R13 ; IMAD.HI.U32 R8, R9, R15, R8 ; IMAD R9, R10, R12, R11 ; IMAD.MOV.U32 R12, RZ, RZ, R14 ; IMAD.HI.U32 R8, R8, R11, RZ ; ISETP.GT.U32.AND P5, PT, R10, R9, PT ; IMAD R12, R8, R12, R11 ; ISETP.GT.U32.AND P0, PT, R7, R12, PT ; @!P5 IMAD.IADD R9, R9, 0x1, -R10 ; @!P5 IADD3 R13, R13, 0x1, RZ ; ISETP.NE.AND P5, PT, RZ, c[0x0][0x170], PT ; ISETP.GE.U32.AND P4, PT, R9, R10, PT ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x17c] ; LOP3.LUT R9, R3, c[0x0][0x170], RZ, 0x3c, !PT ; @!P0 IMAD.IADD R12, R12, 0x1, -R7 ; @!P0 IADD3 R8, R8, 0x1, RZ ; ISETP.GE.AND P3, PT, R9, RZ, PT ; ISETP.GE.U32.AND P1, PT, R12, R7, PT ; LOP3.LUT R7, R3, R0, RZ, 0x3c, !PT ; ISETP.GE.AND P0, PT, R10, 0x1, PT ; @P4 IADD3 R13, R13, 0x1, RZ ; ISETP.GE.AND P4, PT, R7, RZ, PT ; IMAD.MOV.U32 R7, RZ, RZ, R13 ; @P1 IADD3 R8, R8, 0x1, RZ ; @!P3 IMAD.MOV R7, RZ, RZ, -R7 ; @!P5 LOP3.LUT R7, RZ, c[0x0][0x170], RZ, 0x33, !PT ; IMAD.MOV.U32 R9, RZ, RZ, R8 ; HFMA2.MMA R8, -RZ, RZ, 0, 0 ; IMAD.MOV R10, RZ, RZ, -R7 ; @!P4 IMAD.MOV R9, RZ, RZ, -R9 ; @!P6 LOP3.LUT R9, RZ, R0, RZ, 0x33, !PT ; IMAD R10, R10, c[0x0][0x170], R3 ; @!P0 BRA 0x1780 ; IMAD R11, R4, R9, RZ ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; IMAD.IADD R12, R10, 0x1, R11 ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; IADD3 R13, R12.reuse, -0x3, RZ ; IADD3 R15, R12.reuse, -0x2, RZ ; IADD3 R20, R12, -0x1, RZ ; ISETP.NE.AND P3, PT, R5, RZ, PT ; IMAD.IADD R22, R7, 0x1, -R14 ; IMAD.MOV.U32 R27, RZ, RZ, RZ ; @!P2 BRA 0x1420 ; IMAD R21, R22.reuse, UR7, R20 ; ISETP.GT.AND P4, PT, R22.reuse, UR4, PT ; IMAD R17, R22, UR7, R13 ; IMAD R19, R22.reuse, UR7, R15 ; IMAD R23, R22, UR7, R12 ; IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x17c] ; IMAD R21, R21, c[0x0][0x180], R14.reuse ; IMAD R17, R17, c[0x0][0x180], R14.reuse ; IMAD R19, R19, c[0x0][0x180], R14 ; IMAD R26, R23, c[0x0][0x180], R14 ; IMAD R23, R21, R16.reuse, 0x1 ; IMAD R24, R17, R16.reuse, 0x3 ; IMAD R25, R19, R16, 0x2 ; IMAD.MOV.U32 R27, RZ, RZ, RZ ; IMAD.MOV.U32 R21, RZ, RZ, R10 ; IMAD R26, R26, c[0x0][0x17c], RZ ; LOP3.LUT R16, R21.reuse, R22, RZ, 0xfc, !PT ; IADD3 R17, R21, -0x1, RZ ; ISETP.LT.OR P0, PT, R16, RZ, P4 ; ISETP.GT.OR P0, PT, R21, UR6, P0 ; LOP3.LUT R16, R17, R22, RZ, 0xfc, !PT ; ISETP.LT.OR P1, PT, R16, RZ, P4 ; ISETP.GT.OR P1, PT, R17, UR6, P1 ; @!P0 IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; @!P0 IMAD.WIDE R18, R26, R19, c[0x0][0x168] ; @!P0 LDG.E R19, [R18.64] ; @!P1 IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; @!P1 IMAD.WIDE R16, R23, R16, c[0x0][0x168] ; @!P1 LDG.E R17, [R16.64] ; IADD3 R29, R21, -0x2, RZ ; LOP3.LUT R28, R29, R22, RZ, 0xfc, !PT ; @!P0 FADD R8, R8, R19 ; ISETP.LT.OR P0, PT, R28, RZ, P4 ; ISETP.GT.OR P0, PT, R29, UR6, P0 ; IADD3 R29, R21, -0x3, RZ ; LOP3.LUT R16, R29, R22, RZ, 0xfc, !PT ; @!P1 FADD R8, R8, R17 ; ISETP.LT.OR P1, PT, R16, RZ, P4 ; @!P0 IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; ISETP.GT.OR P1, PT, R29, UR6, P1 ; @!P0 IMAD.WIDE R18, R25, R18, c[0x0][0x168] ; @!P0 LDG.E R19, [R18.64] ; @!P1 IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; @!P1 IMAD.WIDE R16, R24, R17, c[0x0][0x168] ; @!P1 LDG.E R17, [R16.64] ; IADD3 R27, R27, 0x4, RZ ; IADD3 R21, R21, -0x4, RZ ; IADD3 R28, R27, R6, RZ ; IADD3 R26, R26, UR8, RZ ; IADD3 R23, R23, UR8, RZ ; IADD3 R25, R25, UR8, RZ ; IADD3 R24, R24, UR8, RZ ; @!P0 FADD R8, R8, R19 ; ISETP.NE.AND P0, PT, R28, RZ, PT ; @!P1 FADD R8, R8, R17 ; @P0 BRA 0x11a0 ; IMAD R18, R22, UR10, R11 ; @!P3 BRA 0x1750 ; IMAD.IADD R17, R10, 0x1, -R27 ; ISETP.GT.AND P0, PT, R22, UR4, PT ; BSSY B0, 0x1540 ; ISETP.NE.AND P3, PT, R5, 0x1, PT ; LOP3.LUT R16, R17, R22, RZ, 0xfc, !PT ; ISETP.LT.OR P1, PT, R16, RZ, P0 ; ISETP.GT.OR P1, PT, R17, UR6, P1 ; @P1 BRA 0x1530 ; IMAD.IADD R17, R18, 0x1, R17 ; IMAD R16, R17, c[0x0][0x180], R14 ; IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; IMAD R16, R16, c[0x0][0x17c], R27 ; IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; LDG.E R17, [R16.64] ; FADD R8, R8, R17 ; BSYNC B0 ; BSSY B0, 0x1750 ; @!P3 BRA 0x1740 ; IADD3 R16, R27, 0x1, RZ ; BSSY B1, 0x1660 ; ISETP.NE.AND P3, PT, R5, 0x2, PT ; IMAD.IADD R17, R10, 0x1, -R16 ; LOP3.LUT R19, R17, R22, RZ, 0xfc, !PT ; ISETP.LT.OR P1, PT, R19, RZ, P0 ; ISETP.GT.OR P1, PT, R17, UR6, P1 ; @P1 BRA 0x1650 ; IMAD.IADD R17, R18, 0x1, R17 ; IMAD.MOV.U32 R24, RZ, RZ, 0x4 ; IMAD R17, R17, c[0x0][0x180], R14 ; IMAD R17, R17, c[0x0][0x17c], R16 ; IMAD.WIDE R16, R17, R24, c[0x0][0x168] ; LDG.E R17, [R16.64] ; FADD R8, R8, R17 ; BSYNC B1 ; @!P3 BRA 0x1740 ; IADD3 R27, R27, 0x2, RZ ; IMAD.IADD R17, R10, 0x1, -R27 ; LOP3.LUT R22, R17, R22, RZ, 0xfc, !PT ; ISETP.LT.OR P0, PT, R22, RZ, P0 ; ISETP.GT.OR P0, PT, R17, UR6, P0 ; @P0 BRA 0x1740 ; IMAD.IADD R17, R18, 0x1, R17 ; IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; IMAD R17, R17, c[0x0][0x180], R14 ; IMAD R17, R17, c[0x0][0x17c], R27 ; IMAD.WIDE R16, R17, R16, c[0x0][0x168] ; LDG.E R17, [R16.64] ; FADD R8, R8, R17 ; BSYNC B0 ; IADD3 R14, R14, 0x1, RZ ; ISETP.GE.AND P0, PT, R14, c[0x0][0x180], PT ; @!P0 BRA 0x1060 ; IMAD R12, R0, R9, RZ ; IADD3 R3, R3, UR5, RZ ; IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; IMAD R7, R7, c[0x0][0x170], R12 ; ISETP.GE.AND P0, PT, R3, R2, PT ; IMAD.IADD R10, R10, 0x1, R7 ; IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; STG.E [R10.64], R8 ; @!P0 BRA 0xc70 ; EXIT ; BRA 0x1820; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z8im2col_fPKfPfiiiiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R13, SR_CTAID.X ; S2R R0, SR_TID.X ; IMAD R13, R13, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R13, c[0x0][0x184], PT ; @P0 EXIT ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x180] ; ISETP.GE.AND P0, PT, R0, 0x1, PT ; @!P0 EXIT ; IABS R5, c[0x0][0x178] ; ULDC UR4, c[0x0][0x184] ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ; ULDC UR5, c[0x0][0x178] ; I2F.RP R0, R5 ; ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x170] ; LOP3.LUT R19, R11, 0x3, RZ, 0xc0, !PT ; ISETP.LE.AND P2, PT, RZ, UR4, PT ; ULDC.64 UR4, c[0x0][0x118] ; IADD3 R12, -R11.reuse, 0x1, R12 ; IADD3 R11, R11, -0x1, RZ ; IADD3 R10, -R19, c[0x0][0x17c], RZ ; MUFU.RCP R0, R0 ; IADD3 R2, R0, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.MOV R4, RZ, RZ, -R3 ; IMAD R7, R4, R5, RZ ; IABS R4, c[0x0][0x184] ; IMAD.HI.U32 R3, R3, R7, R2 ; IMAD.HI.U32 R14, R3, R4, RZ ; IMAD.MOV R0, RZ, RZ, -R14 ; IMAD R0, R5, R0, R4 ; ISETP.GT.U32.AND P1, PT, R5, R0, PT ; @!P1 IMAD.IADD R0, R0, 0x1, -R5 ; @!P1 IADD3 R14, R14, 0x1, RZ ; ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; ISETP.GE.U32.AND P0, PT, R0, R5, PT ; @P0 IADD3 R14, R14, 0x1, RZ ; @!P2 IMAD.MOV R14, RZ, RZ, -R14 ; @!P1 LOP3.LUT R14, RZ, c[0x0][0x178], RZ, 0x33, !PT ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x17c] ; ISETP.GE.AND P0, PT, R0, 0x1, PT ; @!P0 BRA 0xe80 ; IABS R0, R12 ; IABS R4, R14 ; I2F.RP R5, R0 ; I2F.RP R8, R4 ; MUFU.RCP R5, R5 ; MUFU.RCP R8, R8 ; IADD3 R6, R5, 0xffffffe, RZ ; IABS R5, R13 ; F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; IADD3 R2, R8, 0xffffffe, RZ ; IABS R8, R14 ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV R8, RZ, RZ, -R8 ; IADD3 R9, RZ, -R7, RZ ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD R9, R9, R0, RZ ; IMAD.MOV R15, RZ, RZ, -R3 ; IMAD.HI.U32 R7, R7, R9, R6 ; IABS R6, R12 ; IMAD R9, R15, R4, RZ ; IMAD.MOV R6, RZ, RZ, -R6 ; IMAD.HI.U32 R2, R3, R9, R2 ; IMAD.HI.U32 R7, R7, R5, RZ ; IMAD R3, R7, R6, R5 ; IMAD.HI.U32 R2, R2, R5, RZ ; ISETP.GT.U32.AND P0, PT, R0, R3, PT ; IMAD R5, R2, R8, R5 ; IMAD.MOV.U32 R9, RZ, RZ, RZ ; ISETP.GT.U32.AND P4, PT, R4, R5, PT ; @!P0 IMAD.IADD R3, R3, 0x1, -R0 ; @!P0 IADD3 R7, R7, 0x1, RZ ; ISETP.NE.AND P0, PT, R12, RZ, PT ; ISETP.GE.U32.AND P5, PT, R3, R0, PT ; @!P4 IMAD.IADD R5, R5, 0x1, -R4 ; LOP3.LUT R0, R13.reuse, R12, RZ, 0x3c, !PT ; LOP3.LUT R3, R13, R14, RZ, 0x3c, !PT ; ISETP.GE.U32.AND P3, PT, R5, R4, PT ; ISETP.GE.AND P2, PT, R0, RZ, PT ; ISETP.GE.AND P1, PT, R3, RZ, PT ; @!P4 IADD3 R2, R2, 0x1, RZ ; ISETP.NE.AND P4, PT, R14, RZ, PT ; @P5 IADD3 R7, R7, 0x1, RZ ; @P3 IADD3 R2, R2, 0x1, RZ ; @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; @!P0 LOP3.LUT R7, RZ, R12, RZ, 0x33, !PT ; @!P1 IADD3 R2, -R2, RZ, RZ ; @!P4 LOP3.LUT R2, RZ, R14, RZ, 0x33, !PT ; IMAD.MOV R6, RZ, RZ, -R7 ; IMAD R8, R2, c[0x0][0x174], R7 ; IMAD R6, R12, R6, R13 ; ISETP.GE.U32.AND P0, PT, R11, 0x3, PT ; IMAD.IADD R15, R8, 0x1, R9.reuse ; IMAD R7, R13, c[0x0][0x180], R9 ; IADD3 R9, R9, 0x1, RZ ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; IMAD R15, R15, c[0x0][0x170], R6 ; ISETP.GE.AND P1, PT, R9, c[0x0][0x180], PT ; IMAD R7, R7, c[0x0][0x17c], RZ ; @!P0 BRA 0xd60 ; ISETP.GT.AND P0, PT, R10, RZ, PT ; IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; MOV R18, R10 ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x168] ; IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x16c] ; IMAD.WIDE R2, R15, R2, c[0x0][0x160] ; @!P0 BRA 0xc10 ; ISETP.GT.AND P2, PT, R18, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0xa10 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E R21, [R2.64] ; IMAD.MOV.U32 R4, RZ, RZ, R17 ; IMAD.MOV.U32 R5, RZ, RZ, R16 ; IMAD.WIDE R4, R7, 0x4, R4 ; STG.E [R4.64], R21 ; LDG.E R23, [R2.64+0x4] ; STG.E [R4.64+0x4], R23 ; LDG.E R25, [R2.64+0x8] ; STG.E [R4.64+0x8], R25 ; LDG.E R27, [R2.64+0xc] ; STG.E [R4.64+0xc], R27 ; LDG.E R29, [R2.64+0x10] ; STG.E [R4.64+0x10], R29 ; LDG.E R20, [R2.64+0x14] ; STG.E [R4.64+0x14], R20 ; LDG.E R21, [R2.64+0x18] ; STG.E [R4.64+0x18], R21 ; LDG.E R23, [R2.64+0x1c] ; STG.E [R4.64+0x1c], R23 ; LDG.E R25, [R2.64+0x20] ; STG.E [R4.64+0x20], R25 ; LDG.E R27, [R2.64+0x24] ; STG.E [R4.64+0x24], R27 ; LDG.E R29, [R2.64+0x28] ; STG.E [R4.64+0x28], R29 ; LDG.E R20, [R2.64+0x2c] ; STG.E [R4.64+0x2c], R20 ; LDG.E R21, [R2.64+0x30] ; STG.E [R4.64+0x30], R21 ; LDG.E R23, [R2.64+0x34] ; STG.E [R4.64+0x34], R23 ; LDG.E R25, [R2.64+0x38] ; STG.E [R4.64+0x38], R25 ; LDG.E R27, [R2.64+0x3c] ; IADD3 R18, R18, -0x10, RZ ; IADD3 R22, P4, R2, 0x40, RZ ; ISETP.GT.AND P2, PT, R18, 0xc, PT ; IADD3 R17, P3, R17, 0x40, RZ ; IMAD.X R21, RZ, RZ, R3, P4 ; IADD3 R0, R0, 0x10, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R22 ; IMAD.X R16, RZ, RZ, R16, P3 ; IMAD.MOV.U32 R3, RZ, RZ, R21 ; STG.E [R4.64+0x3c], R27 ; @P2 BRA 0x740 ; ISETP.GT.AND P2, PT, R18, 0x4, PT ; @!P2 BRA 0xbf0 ; LDG.E R21, [R2.64] ; MOV R5, R16 ; IMAD.MOV.U32 R4, RZ, RZ, R17 ; IMAD.WIDE R4, R7, 0x4, R4 ; STG.E [R4.64], R21 ; LDG.E R23, [R2.64+0x4] ; STG.E [R4.64+0x4], R23 ; LDG.E R25, [R2.64+0x8] ; STG.E [R4.64+0x8], R25 ; LDG.E R27, [R2.64+0xc] ; STG.E [R4.64+0xc], R27 ; LDG.E R29, [R2.64+0x10] ; STG.E [R4.64+0x10], R29 ; LDG.E R20, [R2.64+0x14] ; STG.E [R4.64+0x14], R20 ; LDG.E R21, [R2.64+0x18] ; STG.E [R4.64+0x18], R21 ; LDG.E R23, [R2.64+0x1c] ; IADD3 R22, P3, R2, 0x20, RZ ; IADD3 R17, P2, R17, 0x20, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD.X R25, RZ, RZ, R3, P3 ; IADD3 R0, R0, 0x8, RZ ; IMAD.X R16, RZ, RZ, R16, P2 ; IADD3 R18, R18, -0x8, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R22 ; IMAD.MOV.U32 R3, RZ, RZ, R25 ; STG.E [R4.64+0x1c], R23 ; ISETP.NE.OR P0, PT, R18, RZ, P0 ; @!P0 BRA 0xd60 ; LDG.E R21, [R2.64] ; IMAD.MOV.U32 R4, RZ, RZ, R17 ; IMAD.MOV.U32 R5, RZ, RZ, R16 ; IMAD.WIDE R4, R7, 0x4, R4 ; STG.E [R4.64], R21 ; LDG.E R23, [R2.64+0x4] ; STG.E [R4.64+0x4], R23 ; LDG.E R25, [R2.64+0x8] ; STG.E [R4.64+0x8], R25 ; LDG.E R27, [R2.64+0xc] ; IADD3 R18, R18, -0x4, RZ ; IADD3 R20, P3, R2, 0x10, RZ ; ISETP.NE.AND P0, PT, R18, RZ, PT ; IADD3 R17, P2, R17, 0x10, RZ ; IMAD.X R21, RZ, RZ, R3, P3 ; IADD3 R0, R0, 0x4, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R20 ; IADD3.X R16, RZ, R16, RZ, P2, !PT ; IMAD.MOV.U32 R3, RZ, RZ, R21 ; STG.E [R4.64+0xc], R27 ; @P0 BRA 0xc10 ; ISETP.NE.AND P0, PT, R19, RZ, PT ; @!P0 BRA 0xe70 ; IMAD.IADD R2, R15, 0x1, R0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; LDG.E R15, [R2.64] ; IMAD.IADD R4, R7, 0x1, R0 ; ISETP.NE.AND P0, PT, R19, 0x1, PT ; IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; STG.E [R4.64], R15 ; @!P0 BRA 0xe70 ; LDG.E R7, [R2.64+0x4] ; ISETP.NE.AND P0, PT, R19, 0x2, PT ; STG.E [R4.64+0x4], R7 ; @!P0 BRA 0xe70 ; LDG.E R3, [R2.64+0x8] ; STG.E [R4.64+0x8], R3 ; @!P1 BRA 0x5f0 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0xc] ; IMAD R13, R0, c[0x0][0x0], R13 ; ISETP.GE.AND P0, PT, R13, c[0x0][0x184], PT ; @!P0 BRA 0x290 ; EXIT ; BRA 0xed0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z9scol2im_dPdPKdiiiiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R3, SR_CTAID.X ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; S2R R2, SR_TID.X ; IMAD R0, R0, c[0x0][0x170], RZ ; IMAD R3, R3, c[0x0][0x0], R2 ; IMAD R2, R0, c[0x0][0x178], RZ ; ISETP.GE.AND P0, PT, R3, R2, PT ; @P0 EXIT ; ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT ; ULDC UR5, c[0x0][0xc] ; ULDC UR4, c[0x0][0x0] ; ULDC UR7, c[0x0][0x170] ; ULDC UR6, c[0x0][0x17c] ; UIMAD UR5, UR5, UR4, URZ ; UIADD3 UR6, UR7, -UR6, URZ ; ULDC.64 UR12, c[0x0][0x118] ; @P0 BRA 0xa10 ; I2F.U32.RP R6, UR5 ; IADD3 R4, R3, UR5, RZ ; BSSY B0, 0x4d0 ; ISETP.NE.U32.AND P2, PT, RZ, UR5, PT ; LOP3.LUT R7, RZ, R4, RZ, 0x33, !PT ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; IADD3 R7, R7, UR5, R2 ; MUFU.RCP R6, R6 ; IADD3 R5, R6, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; IMAD.MOV R9, RZ, RZ, -R5 ; IMAD R9, R9, UR5, RZ ; IMAD.HI.U32 R4, R5, R9, R4 ; IMAD.HI.U32 R4, R4, R7, RZ ; IMAD.MOV R6, RZ, RZ, -R4 ; IMAD R7, R6, UR5, R7 ; ISETP.GE.U32.AND P0, PT, R7, UR5, PT ; @P0 IADD3 R7, R7, -UR5, RZ ; @P0 IADD3 R4, R4, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R7, UR5, PT ; @P1 IADD3 R4, R4, 0x1, RZ ; @!P2 LOP3.LUT R4, RZ, UR5, RZ, 0x33, !PT ; IADD3 R5, R4.reuse, 0x1, RZ ; ISETP.GE.U32.AND P3, PT, R4, 0x3, PT ; LOP3.LUT P0, R5, R5, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0x4c0 ; IABS R4, R0.reuse ; IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; IABS R10, R0.reuse ; I2F.RP R8, R4 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; IABS R12, R0 ; IMAD.MOV R10, RZ, RZ, -R10 ; MUFU.RCP R8, R8 ; IADD3 R6, R8, 0xffffffe, RZ ; LOP3.LUT R8, RZ, R0, RZ, 0x33, !PT ; F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV R9, RZ, RZ, -R7 ; IMAD R9, R9, R4, RZ ; IMAD.HI.U32 R9, R7, R9, R6 ; IABS R7, R3 ; ISETP.GE.AND P2, PT, R3, RZ, PT ; IADD3 R5, R5, -0x1, RZ ; IMAD.HI.U32 R6, R9, R7, RZ ; IMAD R7, R6, R10, R7 ; ISETP.GT.U32.AND P1, PT, R4, R7, PT ; @!P1 IMAD.IADD R7, R7, 0x1, -R12 ; ISETP.GT.U32.AND P1, PT, R4, R7, PT ; @!P1 IMAD.IADD R7, R7, 0x1, -R12 ; ISETP.NE.AND P1, PT, R5, RZ, PT ; @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; SEL R6, R8, R7, !P0 ; IADD3 R6, R3.reuse, R3, -R6 ; IADD3 R3, R3, UR5, RZ ; IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; STG.E.64 [R6.64], RZ ; @P1 BRA 0x3b0 ; BSYNC B0 ; @!P3 EXIT ; IABS R4, R0 ; I2F.RP R8, R4 ; MUFU.RCP R8, R8 ; IADD3 R6, R8, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV R5, RZ, RZ, -R7 ; IMAD R5, R5, R4, RZ ; IMAD.HI.U32 R5, R7, R5, R6 ; IABS R9, R0.reuse ; IABS R12, R3 ; I2F.RP R6, R9 ; IABS R7, R0 ; IMAD.HI.U32 R5, R5, R12, RZ ; IMAD.MOV R15, RZ, RZ, -R7 ; IADD3 R7, R3, UR5, RZ ; IMAD R12, R5, R15, R12 ; IADD3 R8, R7.reuse, UR5, RZ ; IABS R14, R7 ; MUFU.RCP R6, R6 ; ISETP.GT.U32.AND P0, PT, R4, R12, PT ; IABS R16, R8 ; ISETP.GE.AND P6, PT, R7, RZ, PT ; ISETP.GE.AND P5, PT, R8, RZ, PT ; @!P0 IMAD.IADD R12, R12, 0x1, -R9.reuse ; IADD3 R10, R6, 0xffffffe, RZ ; IADD3 R6, R8, UR5, RZ ; F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; ISETP.GT.U32.AND P4, PT, R4, R12, PT ; IMAD.MOV.U32 R4, RZ, RZ, R9 ; IABS R18, R6 ; @!P4 IMAD.IADD R12, R12, 0x1, -R9 ; ISETP.GE.AND P4, PT, R6, RZ, PT ; IMAD.MOV R10, RZ, RZ, -R11 ; IMAD R5, R10, R9, RZ ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; IMAD.HI.U32 R5, R11, R5, R10 ; IMAD.HI.U32 R10, R5, R14, RZ ; IMAD.HI.U32 R11, R5, R16, RZ ; IMAD.HI.U32 R13, R5, R18, RZ ; IMAD R10, R10, R15.reuse, R14 ; LOP3.LUT R14, RZ, R0, RZ, 0x33, !PT ; IMAD R11, R11, R15.reuse, R16 ; IMAD R13, R13, R15, R18 ; ISETP.GT.U32.AND P0, PT, R4.reuse, R10, PT ; IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; ISETP.GT.U32.AND P1, PT, R4.reuse, R11, PT ; ISETP.GT.U32.AND P2, PT, R4, R13, PT ; @!P0 IMAD.IADD R10, R10, 0x1, -R9.reuse ; ISETP.GE.AND P0, PT, R3, RZ, PT ; @!P1 IMAD.IADD R11, R11, 0x1, -R9.reuse ; @!P2 IMAD.IADD R13, R13, 0x1, -R9 ; ISETP.GT.U32.AND P1, PT, R4.reuse, R10, PT ; ISETP.GT.U32.AND P2, PT, R4.reuse, R11, PT ; ISETP.GT.U32.AND P3, PT, R4, R13, PT ; @!P0 IMAD.MOV R12, RZ, RZ, -R12 ; @!P1 IMAD.IADD R10, R10, 0x1, -R9.reuse ; ISETP.NE.AND P1, PT, R0, RZ, PT ; @!P2 IMAD.IADD R11, R11, 0x1, -R9.reuse ; @!P3 IMAD.IADD R13, R13, 0x1, -R9 ; SEL R12, R14.reuse, R12, !P1 ; @!P6 IMAD.MOV R10, RZ, RZ, -R10 ; @!P5 IMAD.MOV R11, RZ, RZ, -R11 ; IADD3 R9, R3, R3, -R12 ; @!P4 IMAD.MOV R13, RZ, RZ, -R13 ; SEL R10, R14, R10, !P1 ; SEL R11, R14.reuse, R11, !P1 ; SEL R13, R14, R13, !P1 ; IADD3 R10, R7, R7, -R10 ; IADD3 R12, R8, R8, -R11 ; IMAD.WIDE R8, R9, R15.reuse, c[0x0][0x160] ; IADD3 R14, R6.reuse, R6, -R13 ; IADD3 R3, R6, UR5, RZ ; IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x160] ; STG.E.64 [R8.64], RZ ; ISETP.GE.AND P0, PT, R3, R2, PT ; IMAD.WIDE R12, R12, R15.reuse, c[0x0][0x160] ; STG.E.64 [R10.64], RZ ; IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; STG.E.64 [R12.64], RZ ; STG.E.64 [R14.64], RZ ; @!P0 BRA 0x570 ; EXIT ; IABS R8, c[0x0][0x178] ; ULDC.64 UR8, c[0x0][0x180] ; IABS R9, c[0x0][0x184] ; ULDC.64 UR10, c[0x0][0x178] ; I2F.RP R6, R8 ; ULOP3.LUT UR4, UR9, UR10, URZ, 0x3c, !UPT ; ISETP.NE.AND P2, PT, RZ, c[0x0][0x178], PT ; UIADD3 UR7, UR7, 0x1, -UR11 ; ULDC UR9, c[0x0][0x174] ; ISETP.LE.AND P3, PT, RZ, UR4, PT ; UIADD3 UR4, -UR8, UR9, URZ ; UIMAD UR8, UR8, UR11, URZ ; UMOV UR9, 0xfffffffc ; UIADD3 UR10, UR6, 0x1, URZ ; MUFU.RCP R6, R6 ; UIMAD UR8, UR8, UR9, 0x4 ; IADD3 R4, R6, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; IMAD.MOV R7, RZ, RZ, -R5 ; IMAD R7, R7, R8, RZ ; IMAD.HI.U32 R5, R5, R7, R4 ; IMAD.MOV.U32 R7, RZ, RZ, R9 ; IMAD.HI.U32 R4, R5, R7, RZ ; IMAD.MOV R5, RZ, RZ, -R4 ; IMAD R5, R8, R5, R7 ; ISETP.GT.U32.AND P1, PT, R8, R5, PT ; @!P1 IMAD.IADD R5, R5, 0x1, -R8 ; @!P1 IADD3 R4, R4, 0x1, RZ ; ISETP.GE.U32.AND P0, PT, R5, R8, PT ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; IADD3 R6, R5.reuse, -0x1, RZ ; LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; IADD3 R6, R5, -c[0x0][0x17c], RZ ; @P0 IADD3 R4, R4, 0x1, RZ ; @!P3 IMAD.MOV R4, RZ, RZ, -R4 ; @!P2 LOP3.LUT R4, RZ, c[0x0][0x178], RZ, 0x33, !PT ; IABS R10, c[0x0][0x170] ; IABS R7, R0 ; I2F.RP R11, R10 ; ISETP.NE.AND P6, PT, R0, RZ, PT ; I2F.RP R14, R7 ; MUFU.RCP R11, R11 ; MUFU.RCP R14, R14 ; IADD3 R12, R11, 0xffffffe, RZ ; IABS R11, R3 ; F2I.FTZ.U32.TRUNC.NTZ R13, R12 ; IADD3 R8, R14, 0xffffffe, RZ ; IABS R14, R0 ; F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; IMAD.MOV R14, RZ, RZ, -R14 ; IMAD.MOV R15, RZ, RZ, -R13 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; IMAD R15, R15, R10, RZ ; IMAD.HI.U32 R13, R13, R15, R12 ; IMAD.MOV R16, RZ, RZ, -R9 ; IMAD.HI.U32 R13, R13, R11, RZ ; IMAD.MOV.U32 R12, RZ, RZ, R16 ; IMAD R15, R12, R7, RZ ; IMAD.MOV R12, RZ, RZ, -R13 ; IMAD.HI.U32 R8, R9, R15, R8 ; IMAD R9, R10, R12, R11.reuse ; IMAD.MOV.U32 R12, RZ, RZ, R14 ; IMAD.HI.U32 R8, R8, R11, RZ ; ISETP.GT.U32.AND P5, PT, R10, R9, PT ; CS2R R14, SRZ ; IMAD R12, R8, R12, R11 ; ISETP.GT.U32.AND P0, PT, R7, R12, PT ; @!P5 IMAD.IADD R9, R9, 0x1, -R10 ; @!P5 IADD3 R13, R13, 0x1, RZ ; ISETP.NE.AND P5, PT, RZ, c[0x0][0x170], PT ; ISETP.GE.U32.AND P4, PT, R9, R10, PT ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x17c] ; LOP3.LUT R9, R3, c[0x0][0x170], RZ, 0x3c, !PT ; @!P0 IMAD.IADD R12, R12, 0x1, -R7 ; @!P0 IADD3 R8, R8, 0x1, RZ ; ISETP.GE.AND P3, PT, R9, RZ, PT ; ISETP.GE.U32.AND P2, PT, R12, R7, PT ; LOP3.LUT R7, R3, R0, RZ, 0x3c, !PT ; ISETP.GE.AND P0, PT, R10, 0x1, PT ; @P4 IADD3 R13, R13, 0x1, RZ ; ISETP.GE.AND P4, PT, R7, RZ, PT ; IMAD.MOV.U32 R7, RZ, RZ, R13 ; @P2 IADD3 R8, R8, 0x1, RZ ; @!P3 IMAD.MOV R7, RZ, RZ, -R7 ; @!P5 LOP3.LUT R7, RZ, c[0x0][0x170], RZ, 0x33, !PT ; IMAD.MOV.U32 R9, RZ, RZ, R8 ; IMAD.MOV R8, RZ, RZ, -R7 ; @!P4 IMAD.MOV R9, RZ, RZ, -R9 ; @!P6 LOP3.LUT R9, RZ, R0, RZ, 0x33, !PT ; IMAD R8, R8, c[0x0][0x170], R3 ; @!P0 BRA 0x1780 ; IMAD R11, R4, R9, RZ ; CS2R R14, SRZ ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; IMAD.IADD R10, R8, 0x1, R11 ; IADD3 R13, R10.reuse, -0x3, RZ ; IADD3 R18, R10.reuse, -0x2, RZ ; IADD3 R19, R10, -0x1, RZ ; ISETP.NE.AND P2, PT, R5, RZ, PT ; IMAD.IADD R20, R7, 0x1, -R12 ; IMAD.MOV.U32 R27, RZ, RZ, RZ ; @!P1 BRA 0x1420 ; IMAD R21, R20.reuse, UR7, R18 ; ISETP.GT.AND P3, PT, R20.reuse, UR4, PT ; IMAD R17, R20, UR7, R13 ; IMAD R23, R20.reuse, UR7, R19 ; IMAD R25, R20, UR7, R10 ; IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x17c] ; IMAD R21, R21, c[0x0][0x180], R12.reuse ; IMAD R17, R17, c[0x0][0x180], R12.reuse ; IMAD R22, R23, c[0x0][0x180], R12 ; IMAD R25, R25, c[0x0][0x180], R12 ; IMAD R24, R21, R16.reuse, 0x2 ; IMAD R23, R17, R16.reuse, 0x3 ; IMAD R22, R22, R16, 0x1 ; IMAD.MOV.U32 R27, RZ, RZ, RZ ; IMAD.MOV.U32 R21, RZ, RZ, R8 ; IMAD R25, R25, c[0x0][0x17c], RZ ; LOP3.LUT R16, R21, R20, RZ, 0xfc, !PT ; ISETP.LT.OR P0, PT, R16, RZ, P3 ; ISETP.GT.OR P0, PT, R21, UR6, P0 ; @!P0 IMAD.MOV.U32 R28, RZ, RZ, 0x8 ; @!P0 IMAD.WIDE R28, R25, R28, c[0x0][0x168] ; @!P0 LDG.E.64 R16, [R28.64] ; @!P0 DADD R14, R14, R16 ; IADD3 R17, R21, -0x1, RZ ; LOP3.LUT R16, R17, R20, RZ, 0xfc, !PT ; ISETP.LT.OR P0, PT, R16, RZ, P3 ; ISETP.GT.OR P0, PT, R17, UR6, P0 ; @!P0 IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; @!P0 IMAD.WIDE R16, R22, R17, c[0x0][0x168] ; @!P0 LDG.E.64 R16, [R16.64] ; IADD3 R26, R21, -0x2, RZ ; LOP3.LUT R28, R26, R20, RZ, 0xfc, !PT ; @!P0 DADD R14, R14, R16 ; ISETP.LT.OR P0, PT, R28, RZ, P3 ; ISETP.GT.OR P0, PT, R26, UR6, P0 ; @!P0 IMAD.MOV.U32 R29, RZ, RZ, 0x8 ; @!P0 IMAD.WIDE R28, R24, R29, c[0x0][0x168] ; @!P0 LDG.E.64 R16, [R28.64] ; IADD3 R26, R21, -0x3, RZ ; @!P0 DADD R14, R14, R16 ; LOP3.LUT R16, R26, R20, RZ, 0xfc, !PT ; ISETP.LT.OR P0, PT, R16, RZ, P3 ; ISETP.GT.OR P0, PT, R26, UR6, P0 ; @!P0 IMAD.MOV.U32 R16, RZ, RZ, 0x8 ; @!P0 IMAD.WIDE R16, R23, R16, c[0x0][0x168] ; @!P0 LDG.E.64 R16, [R16.64] ; IADD3 R27, R27, 0x4, RZ ; IADD3 R21, R21, -0x4, RZ ; IADD3 R25, R25, UR8, RZ ; IMAD.IADD R26, R27, 0x1, R6 ; IADD3 R22, R22, UR8, RZ ; IADD3 R24, R24, UR8, RZ ; IADD3 R23, R23, UR8, RZ ; @!P0 DADD R14, R14, R16 ; ISETP.NE.AND P0, PT, R26, RZ, PT ; @P0 BRA 0x11a0 ; IMAD R21, R20, UR10, R11 ; @!P2 BRA 0x1750 ; IMAD.IADD R17, R8, 0x1, -R27 ; ISETP.GT.AND P0, PT, R20, UR4, PT ; BSSY B0, 0x1540 ; ISETP.NE.AND P3, PT, R5, 0x1, PT ; LOP3.LUT R16, R17, R20, RZ, 0xfc, !PT ; ISETP.LT.OR P2, PT, R16, RZ, P0 ; ISETP.GT.OR P2, PT, R17, UR6, P2 ; @P2 BRA 0x1530 ; IMAD.IADD R17, R21, 0x1, R17 ; IMAD R16, R17, c[0x0][0x180], R12 ; IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; IMAD R16, R16, c[0x0][0x17c], R27 ; IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; LDG.E.64 R16, [R16.64] ; DADD R14, R14, R16 ; BSYNC B0 ; BSSY B0, 0x1750 ; @!P3 BRA 0x1740 ; IADD3 R16, R27, 0x1, RZ ; BSSY B1, 0x1660 ; ISETP.NE.AND P3, PT, R5, 0x2, PT ; IMAD.IADD R17, R8, 0x1, -R16 ; LOP3.LUT R22, R17, R20, RZ, 0xfc, !PT ; ISETP.LT.OR P2, PT, R22, RZ, P0 ; ISETP.GT.OR P2, PT, R17, UR6, P2 ; @P2 BRA 0x1650 ; IMAD.IADD R17, R21, 0x1, R17 ; IMAD.MOV.U32 R22, RZ, RZ, 0x8 ; IMAD R17, R17, c[0x0][0x180], R12 ; IMAD R17, R17, c[0x0][0x17c], R16 ; IMAD.WIDE R16, R17, R22, c[0x0][0x168] ; LDG.E.64 R16, [R16.64] ; DADD R14, R14, R16 ; BSYNC B1 ; @!P3 BRA 0x1740 ; IADD3 R16, R27, 0x2, RZ ; IMAD.IADD R17, R8, 0x1, -R16 ; LOP3.LUT R20, R17, R20, RZ, 0xfc, !PT ; ISETP.LT.OR P0, PT, R20, RZ, P0 ; ISETP.GT.OR P0, PT, R17, UR6, P0 ; @P0 BRA 0x1740 ; IMAD.IADD R21, R21, 0x1, R17 ; IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; IMAD R21, R21, c[0x0][0x180], R12 ; IMAD R16, R21, c[0x0][0x17c], R16 ; IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; LDG.E.64 R16, [R16.64] ; DADD R14, R14, R16 ; BSYNC B0 ; IADD3 R12, R12, 0x1, RZ ; ISETP.GE.AND P0, PT, R12, c[0x0][0x180], PT ; @!P0 BRA 0x1060 ; IMAD R10, R0, R9, RZ ; IADD3 R3, R3, UR5, RZ ; IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; IMAD R7, R7, c[0x0][0x170], R10 ; ISETP.GE.AND P0, PT, R3, R2, PT ; IMAD.IADD R8, R8, 0x1, R7 ; IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; STG.E.64 [R8.64], R14 ; @!P0 BRA 0xc70 ; EXIT ; BRA 0x1820; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z8im2col_dPKdPdiiiiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R4, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R4, R4, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R4, c[0x0][0x184], PT ; @P0 EXIT ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x180] ; ISETP.GE.AND P0, PT, R0, 0x1, PT ; @!P0 EXIT ; IABS R6, c[0x0][0x178] ; ULDC UR4, c[0x0][0x184] ; IABS R7, c[0x0][0x184] ; ULDC UR5, c[0x0][0x178] ; I2F.RP R0, R6 ; ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; ISETP.LE.AND P2, PT, RZ, UR4, PT ; ULDC.64 UR4, c[0x0][0x118] ; MUFU.RCP R0, R0 ; IADD3 R2, R0, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.MOV R5, RZ, RZ, -R3 ; IMAD R5, R5, R6, RZ ; IMAD.HI.U32 R3, R3, R5, R2 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; IMAD.HI.U32 R0, R3, R5, RZ ; IMAD.MOV R3, RZ, RZ, -R0 ; IMAD R3, R6, R3, R5 ; MOV R5, c[0x0][0x17c] ; ISETP.GT.U32.AND P1, PT, R6, R3, PT ; LOP3.LUT R2, R5, 0x3, RZ, 0xc0, !PT ; @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; @!P1 IADD3 R0, R0, 0x1, RZ ; ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; ISETP.GE.U32.AND P0, PT, R3, R6, PT ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; IMAD.MOV.U32 R3, RZ, RZ, R4 ; IADD3 R4, -R5.reuse, 0x1, R6 ; IADD3 R5, R5, -0x1, RZ ; IADD3 R6, -R2, c[0x0][0x17c], RZ ; @P0 IADD3 R0, R0, 0x1, RZ ; @!P2 IMAD.MOV R0, RZ, RZ, -R0 ; @!P1 LOP3.LUT R0, RZ, c[0x0][0x178], RZ, 0x33, !PT ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x17c] ; ISETP.GE.AND P0, PT, R7, 0x1, PT ; @!P0 BRA 0xeb0 ; IABS R7, R4 ; IABS R10, R0 ; I2F.RP R11, R7 ; I2F.RP R14, R10 ; MUFU.RCP R11, R11 ; MUFU.RCP R14, R14 ; IADD3 R12, R11, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R13, R12 ; IADD3 R8, R14, 0xffffffe, RZ ; IABS R14, R4 ; F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; HFMA2.MMA R12, -RZ, RZ, 0, 0 ; IMAD.MOV R14, RZ, RZ, -R14 ; IMAD.MOV R16, RZ, RZ, -R13 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; IMAD R15, R16, R7, RZ ; IABS R16, R3 ; IMAD.MOV R11, RZ, RZ, -R9 ; IMAD.HI.U32 R13, R13, R15, R12 ; IABS R15, R0 ; IMAD R11, R11, R10, RZ ; IMAD.MOV.U32 R12, RZ, RZ, R16 ; IMAD.HI.U32 R8, R9, R11, R8 ; IMAD.MOV R15, RZ, RZ, -R15 ; IMAD.MOV.U32 R11, RZ, RZ, R14 ; IMAD.HI.U32 R13, R13, R12, RZ ; IMAD.MOV.U32 R14, RZ, RZ, R15 ; IMAD.HI.U32 R9, R8, R12, RZ ; IMAD R8, R13, R11, R12.reuse ; IMAD R11, R9, R14, R12 ; ISETP.GT.U32.AND P0, PT, R7, R8, PT ; ISETP.GT.U32.AND P4, PT, R10, R11, PT ; @!P0 IADD3 R8, R8, -R7.reuse, RZ ; @!P4 IMAD.IADD R11, R11, 0x1, -R10 ; @!P0 IADD3 R13, R13, 0x1, RZ ; ISETP.GE.U32.AND P5, PT, R8, R7, PT ; LOP3.LUT R7, R3, R4, RZ, 0x3c, !PT ; ISETP.GE.U32.AND P3, PT, R11, R10, PT ; LOP3.LUT R8, R3, R0, RZ, 0x3c, !PT ; ISETP.GE.AND P2, PT, R7, RZ, PT ; ISETP.NE.AND P0, PT, R4, RZ, PT ; ISETP.GE.AND P1, PT, R8, RZ, PT ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; @!P4 IADD3 R9, R9, 0x1, RZ ; ISETP.NE.AND P4, PT, R0, RZ, PT ; @P5 IADD3 R13, R13, 0x1, RZ ; @P3 IADD3 R9, R9, 0x1, RZ ; @!P2 IMAD.MOV R13, RZ, RZ, -R13 ; @!P0 LOP3.LUT R13, RZ, R4, RZ, 0x33, !PT ; @!P1 IMAD.MOV R9, RZ, RZ, -R9 ; @!P4 LOP3.LUT R9, RZ, R0, RZ, 0x33, !PT ; IMAD.MOV R10, RZ, RZ, -R13 ; IMAD R7, R9, c[0x0][0x174], R13 ; IMAD R9, R4, R10, R3 ; ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; IMAD.IADD R10, R7, 0x1, R8.reuse ; MOV R18, RZ ; IMAD R19, R3, c[0x0][0x180], R8 ; IADD3 R8, R8, 0x1, RZ ; IMAD R11, R10, c[0x0][0x170], R9 ; IMAD R19, R19, c[0x0][0x17c], RZ ; ISETP.GE.AND P1, PT, R8, c[0x0][0x180], PT ; @!P0 BRA 0xd90 ; ISETP.GT.AND P0, PT, R6, RZ, PT ; IMAD.MOV.U32 R12, RZ, RZ, 0x8 ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x168] ; IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x16c] ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; IMAD.WIDE R12, R11, R12, c[0x0][0x160] ; @!P0 BRA 0xc40 ; ISETP.GT.AND P2, PT, R10, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P2 BRA 0xa40 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E.64 R14, [R12.64] ; IMAD.WIDE R16, R19, 0x8, R20 ; STG.E.64 [R16.64], R14 ; LDG.E.64 R24, [R12.64+0x8] ; STG.E.64 [R16.64+0x8], R24 ; LDG.E.64 R22, [R12.64+0x10] ; STG.E.64 [R16.64+0x10], R22 ; LDG.E.64 R14, [R12.64+0x18] ; STG.E.64 [R16.64+0x18], R14 ; LDG.E.64 R22, [R12.64+0x20] ; STG.E.64 [R16.64+0x20], R22 ; LDG.E.64 R28, [R12.64+0x28] ; STG.E.64 [R16.64+0x28], R28 ; LDG.E.64 R26, [R12.64+0x30] ; STG.E.64 [R16.64+0x30], R26 ; LDG.E.64 R24, [R12.64+0x38] ; STG.E.64 [R16.64+0x38], R24 ; LDG.E.64 R22, [R12.64+0x40] ; STG.E.64 [R16.64+0x40], R22 ; LDG.E.64 R14, [R12.64+0x48] ; STG.E.64 [R16.64+0x48], R14 ; LDG.E.64 R14, [R12.64+0x50] ; STG.E.64 [R16.64+0x50], R14 ; LDG.E.64 R28, [R12.64+0x58] ; STG.E.64 [R16.64+0x58], R28 ; LDG.E.64 R26, [R12.64+0x60] ; STG.E.64 [R16.64+0x60], R26 ; LDG.E.64 R24, [R12.64+0x68] ; STG.E.64 [R16.64+0x68], R24 ; LDG.E.64 R22, [R12.64+0x70] ; IADD3 R10, R10, -0x10, RZ ; STG.E.64 [R16.64+0x70], R22 ; LDG.E.64 R14, [R12.64+0x78] ; ISETP.GT.AND P2, PT, R10, 0xc, PT ; IADD3 R20, P3, R20, 0x80, RZ ; IADD3 R18, R18, 0x10, RZ ; IADD3.X R21, RZ, R21, RZ, P3, !PT ; STG.E.64 [R16.64+0x78], R14 ; IADD3 R14, P4, R12, 0x80, RZ ; IMAD.X R27, RZ, RZ, R13, P4 ; IMAD.MOV.U32 R12, RZ, RZ, R14 ; IMAD.MOV.U32 R13, RZ, RZ, R27 ; @P2 BRA 0x790 ; ISETP.GT.AND P2, PT, R10, 0x4, PT ; @!P2 BRA 0xc20 ; LDG.E.64 R14, [R12.64] ; IMAD.MOV.U32 R16, RZ, RZ, R20 ; IMAD.MOV.U32 R17, RZ, RZ, R21 ; IMAD.WIDE R16, R19, 0x8, R16 ; STG.E.64 [R16.64], R14 ; LDG.E.64 R14, [R12.64+0x8] ; STG.E.64 [R16.64+0x8], R14 ; LDG.E.64 R22, [R12.64+0x10] ; STG.E.64 [R16.64+0x10], R22 ; LDG.E.64 R28, [R12.64+0x18] ; STG.E.64 [R16.64+0x18], R28 ; LDG.E.64 R26, [R12.64+0x20] ; STG.E.64 [R16.64+0x20], R26 ; LDG.E.64 R24, [R12.64+0x28] ; STG.E.64 [R16.64+0x28], R24 ; LDG.E.64 R22, [R12.64+0x30] ; STG.E.64 [R16.64+0x30], R22 ; LDG.E.64 R14, [R12.64+0x38] ; IADD3 R20, P2, R20, 0x40, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3 R18, R18, 0x8, RZ ; IMAD.X R21, RZ, RZ, R21, P2 ; IADD3 R10, R10, -0x8, RZ ; STG.E.64 [R16.64+0x38], R14 ; IADD3 R14, P3, R12, 0x40, RZ ; MOV R12, R14 ; IMAD.X R29, RZ, RZ, R13, P3 ; IMAD.MOV.U32 R13, RZ, RZ, R29 ; ISETP.NE.OR P0, PT, R10, RZ, P0 ; @!P0 BRA 0xd90 ; LDG.E.64 R14, [R12.64] ; IMAD.MOV.U32 R16, RZ, RZ, R20 ; IMAD.MOV.U32 R17, RZ, RZ, R21 ; IMAD.WIDE R16, R19, 0x8, R16 ; STG.E.64 [R16.64], R14 ; LDG.E.64 R26, [R12.64+0x8] ; STG.E.64 [R16.64+0x8], R26 ; LDG.E.64 R24, [R12.64+0x10] ; STG.E.64 [R16.64+0x10], R24 ; LDG.E.64 R22, [R12.64+0x18] ; IADD3 R10, R10, -0x4, RZ ; IADD3 R28, P3, R12, 0x20, RZ ; ISETP.NE.AND P0, PT, R10, RZ, PT ; IADD3 R20, P2, R20, 0x20, RZ ; IMAD.X R29, RZ, RZ, R13, P3 ; IADD3 R18, R18, 0x4, RZ ; IMAD.MOV.U32 R12, RZ, RZ, R28 ; IMAD.X R21, RZ, RZ, R21, P2 ; MOV R13, R29 ; STG.E.64 [R16.64+0x18], R22 ; @P0 BRA 0xc40 ; ISETP.NE.AND P0, PT, R2, RZ, PT ; @!P0 BRA 0xea0 ; IMAD.IADD R11, R11, 0x1, R18 ; IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; IMAD.WIDE R10, R11, R15, c[0x0][0x160] ; LDG.E.64 R12, [R10.64] ; IMAD.IADD R14, R19, 0x1, R18 ; ISETP.NE.AND P0, PT, R2, 0x1, PT ; IMAD.WIDE R14, R14, R15, c[0x0][0x168] ; STG.E.64 [R14.64], R12 ; @!P0 BRA 0xea0 ; LDG.E.64 R12, [R10.64+0x8] ; ISETP.NE.AND P0, PT, R2, 0x2, PT ; STG.E.64 [R14.64+0x8], R12 ; @!P0 BRA 0xea0 ; LDG.E.64 R10, [R10.64+0x10] ; STG.E.64 [R14.64+0x10], R10 ; @!P1 BRA 0x640 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0xc] ; IMAD R3, R8, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R3, c[0x0][0x184], PT ; @!P0 BRA 0x2b0 ; EXIT ; BRA 0xf00; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_001039d1_00000000-6_3c711df0b11277f688cbc5ae7c1e29e10fe5ce3c.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2031: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2031: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z36__device_stub__Z8im2col_dPKdPdiiiiiiPKdPdiiiiii .type _Z36__device_stub__Z8im2col_dPKdPdiiiiiiPKdPdiiiiii, @function _Z36__device_stub__Z8im2col_dPKdPdiiiiiiPKdPdiiiiii: .LFB2053: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movl %r9d, (%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movq %rsp, %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 168(%rsp), %rax subq %fs:40, %rax jne .L8 addq $184, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 200 pushq 40(%rsp) .cfi_def_cfa_offset 208 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z8im2col_dPKdPdiiiiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2053: .size _Z36__device_stub__Z8im2col_dPKdPdiiiiiiPKdPdiiiiii, .-_Z36__device_stub__Z8im2col_dPKdPdiiiiiiPKdPdiiiiii .globl _Z8im2col_dPKdPdiiiiii .type _Z8im2col_dPKdPdiiiiii, @function _Z8im2col_dPKdPdiiiiii: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 call _Z36__device_stub__Z8im2col_dPKdPdiiiiiiPKdPdiiiiii addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _Z8im2col_dPKdPdiiiiii, .-_Z8im2col_dPKdPdiiiiii .globl _Z37__device_stub__Z9scol2im_dPdPKdiiiiiiPdPKdiiiiii .type _Z37__device_stub__Z9scol2im_dPdPKdiiiiiiPdPKdiiiiii, @function _Z37__device_stub__Z9scol2im_dPdPKdiiiiiiPdPKdiiiiii: .LFB2055: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movl %r9d, (%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movq %rsp, %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 168(%rsp), %rax subq %fs:40, %rax jne .L16 addq $184, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 200 pushq 40(%rsp) .cfi_def_cfa_offset 208 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z9scol2im_dPdPKdiiiiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2055: .size _Z37__device_stub__Z9scol2im_dPdPKdiiiiiiPdPKdiiiiii, .-_Z37__device_stub__Z9scol2im_dPdPKdiiiiiiPdPKdiiiiii .globl _Z9scol2im_dPdPKdiiiiii .type _Z9scol2im_dPdPKdiiiiii, @function _Z9scol2im_dPdPKdiiiiii: .LFB2056: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 call _Z37__device_stub__Z9scol2im_dPdPKdiiiiiiPdPKdiiiiii addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2056: .size _Z9scol2im_dPdPKdiiiiii, .-_Z9scol2im_dPdPKdiiiiii .globl _Z36__device_stub__Z8im2col_fPKfPfiiiiiiPKfPfiiiiii .type _Z36__device_stub__Z8im2col_fPKfPfiiiiiiPKfPfiiiiii, @function _Z36__device_stub__Z8im2col_fPKfPfiiiiiiPKfPfiiiiii: .LFB2057: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movl %r9d, (%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movq %rsp, %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L23 .L19: movq 168(%rsp), %rax subq %fs:40, %rax jne .L24 addq $184, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 200 pushq 40(%rsp) .cfi_def_cfa_offset 208 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z8im2col_fPKfPfiiiiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L19 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z36__device_stub__Z8im2col_fPKfPfiiiiiiPKfPfiiiiii, .-_Z36__device_stub__Z8im2col_fPKfPfiiiiiiPKfPfiiiiii .globl _Z8im2col_fPKfPfiiiiii .type _Z8im2col_fPKfPfiiiiii, @function _Z8im2col_fPKfPfiiiiii: .LFB2058: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 call _Z36__device_stub__Z8im2col_fPKfPfiiiiiiPKfPfiiiiii addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z8im2col_fPKfPfiiiiii, .-_Z8im2col_fPKfPfiiiiii .globl _Z37__device_stub__Z9scol2im_fPfPKfiiiiiiPfPKfiiiiii .type _Z37__device_stub__Z9scol2im_fPfPKfiiiiiiPfPKfiiiiii, @function _Z37__device_stub__Z9scol2im_fPfPKfiiiiiiPfPKfiiiiii: .LFB2059: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movl %r9d, (%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movq %rsp, %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L31 .L27: movq 168(%rsp), %rax subq %fs:40, %rax jne .L32 addq $184, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L31: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 200 pushq 40(%rsp) .cfi_def_cfa_offset 208 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z9scol2im_fPfPKfiiiiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L27 .L32: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size _Z37__device_stub__Z9scol2im_fPfPKfiiiiiiPfPKfiiiiii, .-_Z37__device_stub__Z9scol2im_fPfPKfiiiiiiPfPKfiiiiii .globl _Z9scol2im_fPfPKfiiiiii .type _Z9scol2im_fPfPKfiiiiii, @function _Z9scol2im_fPfPKfiiiiii: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 call _Z37__device_stub__Z9scol2im_fPfPKfiiiiiiPfPKfiiiiii addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _Z9scol2im_fPfPKfiiiiii, .-_Z9scol2im_fPfPKfiiiiii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z9scol2im_fPfPKfiiiiii" .LC1: .string "_Z8im2col_fPKfPfiiiiii" .LC2: .string "_Z9scol2im_dPdPKdiiiiii" .LC3: .string "_Z8im2col_dPKdPdiiiiii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2062: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z9scol2im_fPfPKfiiiiii(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z8im2col_fPKfPfiiiiii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z9scol2im_dPdPKdiiiiii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _Z8im2col_dPKdPdiiiiii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z8im2col_dPKdPdiiiiii ; -- Begin function _Z8im2col_dPKdPdiiiiii .globl _Z8im2col_dPKdPdiiiiii .p2align 8 .type _Z8im2col_dPKdPdiiiiii,@function _Z8im2col_dPKdPdiiiiii: ; @_Z8im2col_dPKdPdiiiiii ; %bb.0: s_load_b64 s[2:3], s[0:1], 0x24 s_add_u32 s4, s0, 40 s_addc_u32 s5, s1, 0 s_mov_b32 s7, exec_lo s_waitcnt lgkmcnt(0) s_cmp_lt_u32 s15, s3 s_cselect_b32 s6, 12, 18 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) v_mov_b32_e32 v1, s6 global_load_u16 v3, v1, s[4:5] s_load_b32 s4, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_ashr_i32 s5, s4, 31 s_add_i32 s4, s4, s5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_xor_b32 s4, s4, s5 v_cvt_f32_u32_e32 v1, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_rcp_iflag_f32_e32 v1, v1 s_waitcnt_depctr 0xfff v_mul_f32_e32 v4, 0x4f7ffffe, v1 s_waitcnt vmcnt(0) v_mad_u64_u32 v[1:2], null, s15, v3, v[0:1] v_cvt_u32_f32_e32 v0, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_readfirstlane_b32 s6, v0 v_cmpx_gt_i32_e64 s2, v1 s_cbranch_execz .LBB0_8 ; %bb.1: ; %.lr.ph46.i s_sub_i32 s8, 0, s4 s_ashr_i32 s7, s2, 31 s_mul_i32 s13, s8, s6 s_add_i32 s12, s2, s7 s_clause 0x1 s_load_b64 s[8:9], s[0:1], 0x10 s_load_b64 s[10:11], s[0:1], 0x1c s_mul_hi_u32 s13, s6, s13 s_xor_b32 s12, s12, s7 s_add_i32 s6, s6, s13 s_xor_b32 s5, s7, s5 s_mul_hi_u32 s6, s12, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s13, s6, s4 s_sub_i32 s7, s12, s13 s_add_i32 s12, s6, 1 s_sub_i32 s13, s7, s4 s_cmp_ge_u32 s7, s4 s_cselect_b32 s6, s12, s6 s_cselect_b32 s7, s13, s7 s_add_i32 s12, s6, 1 s_cmp_ge_u32 s7, s4 s_cselect_b32 s4, s12, s6 s_waitcnt lgkmcnt(0) s_sub_i32 s12, s8, s10 s_xor_b32 s4, s4, s5 s_add_i32 s12, s12, 1 s_sub_i32 s4, s4, s5 s_cmp_gt_i32 s11, 0 s_cselect_b32 s13, -1, 0 s_cmp_gt_i32 s10, 0 s_cselect_b32 s14, -1, 0 s_ashr_i32 s15, s12, 31 s_ashr_i32 s17, s4, 31 s_add_i32 s5, s12, s15 s_add_i32 s4, s4, s17 s_xor_b32 s16, s5, s15 s_xor_b32 s18, s4, s17 v_cvt_f32_u32_e32 v0, s16 v_cvt_f32_u32_e32 v2, s18 s_sub_i32 s4, 0, s16 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v0, v0 v_rcp_iflag_f32_e32 v2, v2 s_waitcnt_depctr 0xfff v_mul_f32_e32 v0, 0x4f7ffffe, v0 v_mul_f32_e32 v2, 0x4f7ffffe, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cvt_u32_f32_e32 v4, v0 v_mul_lo_u32 v0, s3, v3 v_cvt_u32_f32_e32 v8, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) v_mul_lo_u32 v5, s4, v4 s_load_b128 s[4:7], s[0:1], 0x0 s_mul_i32 s0, s11, s10 s_mov_b32 s1, 0 v_mul_lo_u32 v6, s0, v1 v_mul_lo_u32 v7, v0, s0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v3, v4, v5 v_add_nc_u32_e32 v9, v4, v3 s_branch .LBB0_3 .LBB0_2: ; %._crit_edge43.i ; in Loop: Header=BB0_3 Depth=1 s_set_inst_prefetch_distance 0x2 v_add_nc_u32_e32 v1, v1, v0 v_add_nc_u32_e32 v6, v6, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_le_i32_e32 vcc_lo, s2, v1 s_or_b32 s1, vcc_lo, s1 s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execz .LBB0_8 .LBB0_3: ; =>This Loop Header: Depth=1 ; Child Loop BB0_6 Depth 2 ; Child Loop BB0_7 Depth 3 s_and_not1_b32 vcc_lo, exec_lo, s13 s_cbranch_vccnz .LBB0_2 ; %bb.4: ; %.preheader.lr.ph.i ; in Loop: Header=BB0_3 Depth=1 s_sub_i32 s0, 0, s18 v_ashrrev_i32_e32 v4, 31, v1 v_mul_lo_u32 v2, s0, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v3, v1, v4 v_mul_hi_u32 v2, v8, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v5, v3, v4 v_add_nc_u32_e32 v2, v8, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v10, v5, v2 v_mad_u64_u32 v[2:3], null, v5, v9, 0 v_mul_lo_u32 v2, v10, s18 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mul_lo_u32 v11, v3, s16 v_add_nc_u32_e32 v12, 1, v10 v_sub_nc_u32_e32 v2, v5, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v5, v5, v11 v_subrev_nc_u32_e32 v13, s18, v2 v_cmp_le_u32_e32 vcc_lo, s18, v2 v_add_nc_u32_e32 v11, 1, v3 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_cmp_le_u32_e64 s0, s16, v5 v_cndmask_b32_e32 v10, v10, v12, vcc_lo v_subrev_nc_u32_e32 v12, s16, v5 v_cndmask_b32_e32 v2, v2, v13, vcc_lo v_cndmask_b32_e64 v3, v3, v11, s0 v_xor_b32_e32 v13, s17, v4 v_add_nc_u32_e32 v11, 1, v10 v_cndmask_b32_e64 v5, v5, v12, s0 v_cmp_le_u32_e32 vcc_lo, s18, v2 v_add_nc_u32_e32 v12, 1, v3 s_mov_b32 s0, 0 v_cndmask_b32_e32 v2, v10, v11, vcc_lo v_cmp_le_u32_e32 vcc_lo, s16, v5 v_xor_b32_e32 v10, s15, v4 v_mov_b32_e32 v11, v6 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_xor_b32_e32 v4, v2, v13 v_cndmask_b32_e32 v3, v3, v12, vcc_lo v_sub_nc_u32_e32 v5, v4, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v2, v3, v10 v_mad_u64_u32 v[3:4], null, v5, s9, v[2:3] v_sub_nc_u32_e32 v2, v2, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_lo_u32 v5, v2, s12 v_sub_nc_u32_e32 v4, v3, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, s8, v4, v[1:2] v_sub_nc_u32_e32 v10, v2, v5 s_set_inst_prefetch_distance 0x1 s_branch .LBB0_6 .p2align 6 .LBB0_5: ; %._crit_edge.i ; in Loop: Header=BB0_6 Depth=2 v_add_nc_u32_e32 v11, s10, v11 v_add_nc_u32_e32 v10, s8, v10 s_add_i32 s0, s0, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s0, s11 s_cbranch_scc1 .LBB0_2 .LBB0_6: ; %.preheader.i ; Parent Loop BB0_3 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB0_7 Depth 3 s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v2, v10 v_mov_b32_e32 v4, v11 s_and_not1_b32 vcc_lo, exec_lo, s14 s_mov_b32 s3, s10 s_cbranch_vccnz .LBB0_5 .p2align 6 .LBB0_7: ; Parent Loop BB0_3 Depth=1 ; Parent Loop BB0_6 Depth=2 ; => This Inner Loop Header: Depth=3 v_ashrrev_i32_e32 v3, 31, v2 v_ashrrev_i32_e32 v5, 31, v4 s_add_i32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) s_cmp_eq_u32 s3, 0 v_lshlrev_b64 v[12:13], 3, v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_lshlrev_b64 v[14:15], 3, v[4:5] v_add_nc_u32_e32 v4, 1, v4 v_add_nc_u32_e32 v2, 1, v2 s_waitcnt lgkmcnt(0) v_add_co_u32 v12, vcc_lo, s4, v12 v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo v_add_co_u32 v14, vcc_lo, s6, v14 v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo global_load_b64 v[12:13], v[12:13], off s_waitcnt vmcnt(0) global_store_b64 v[14:15], v[12:13], off s_cbranch_scc0 .LBB0_7 s_branch .LBB0_5 .LBB0_8: ; %_Z10im2col_kerIdEvPKT_PS0_iiiiii.exit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z8im2col_dPKdPdiiiiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 16 .amdhsa_next_free_sgpr 19 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z8im2col_dPKdPdiiiiii, .Lfunc_end0-_Z8im2col_dPKdPdiiiiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 892 ; NumSgprs: 21 ; NumVgprs: 16 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 21 ; NumVGPRsForWavesPerEU: 16 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z9scol2im_dPdPKdiiiiii ; -- Begin function _Z9scol2im_dPdPKdiiiiii .globl _Z9scol2im_dPdPKdiiiiii .p2align 8 .type _Z9scol2im_dPdPKdiiiiii,@function _Z9scol2im_dPdPKdiiiiii: ; @_Z9scol2im_dPdPKdiiiiii ; %bb.0: s_clause 0x1 s_load_b32 s21, s[0:1], 0x28 s_load_b32 s6, s[0:1], 0x18 s_add_u32 s2, s0, 40 s_addc_u32 s3, s1, 0 s_mov_b32 s7, exec_lo s_waitcnt lgkmcnt(0) s_cmp_lt_u32 s15, s21 s_cselect_b32 s4, 12, 18 s_ashr_i32 s5, s6, 31 v_mov_b32_e32 v1, s4 global_load_u16 v3, v1, s[2:3] s_add_i32 s2, s6, s5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_xor_b32 s4, s2, s5 s_load_b64 s[2:3], s[0:1], 0x10 v_cvt_f32_u32_e32 v1, s4 v_rcp_iflag_f32_e32 v1, v1 s_waitcnt_depctr 0xfff v_mul_f32_e32 v4, 0x4f7ffffe, v1 s_waitcnt lgkmcnt(0) s_mul_i32 s10, s3, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_mul_i32 s11, s10, s6 s_waitcnt vmcnt(0) v_mad_u64_u32 v[1:2], null, s15, v3, v[0:1] v_cvt_u32_f32_e32 v0, v4 v_readfirstlane_b32 s6, v0 s_delay_alu instid0(VALU_DEP_3) v_cmpx_gt_i32_e64 s11, v1 s_cbranch_execz .LBB1_12 ; %bb.1: ; %.lr.ph76.i s_clause 0x1 s_load_b32 s7, s[0:1], 0x24 s_load_b64 s[8:9], s[0:1], 0x1c s_sub_i32 s12, 0, s4 s_mov_b32 s20, 0 s_mul_i32 s12, s12, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_hi_u32 s12, s6, s12 s_add_i32 s6, s6, s12 s_waitcnt lgkmcnt(0) s_ashr_i32 s13, s7, 31 s_sub_i32 s3, s3, s9 s_add_i32 s7, s7, s13 s_sub_i32 s12, s2, s8 s_xor_b32 s7, s7, s13 s_xor_b32 s5, s13, s5 s_mul_hi_u32 s6, s7, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_mul_i32 s14, s6, s4 s_add_i32 s13, s6, 1 s_sub_i32 s7, s7, s14 s_sub_i32 s14, s7, s4 s_cmp_ge_u32 s7, s4 s_cselect_b32 s6, s13, s6 s_cselect_b32 s7, s14, s7 s_add_i32 s13, s6, 1 s_cmp_ge_u32 s7, s4 s_cselect_b32 s4, s13, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_xor_b32 s4, s4, s5 s_sub_i32 s13, s4, s5 s_cmp_gt_i32 s9, 0 s_cselect_b32 s14, -1, 0 s_cmp_gt_i32 s8, 0 s_cselect_b32 s15, -1, 0 s_ashr_i32 s17, s2, 31 s_ashr_i32 s16, s10, 31 s_add_i32 s5, s2, s17 s_add_i32 s4, s10, s16 s_xor_b32 s19, s5, s17 s_xor_b32 s18, s4, s16 v_cvt_f32_u32_e32 v2, s19 v_cvt_f32_u32_e32 v0, s18 s_sub_i32 s5, 0, s19 s_sub_i32 s4, 0, s18 s_sub_i32 s22, 1, s8 v_rcp_iflag_f32_e32 v2, v2 v_rcp_iflag_f32_e32 v0, v0 s_waitcnt_depctr 0xfff v_mul_f32_e32 v2, 0x4f7ffffe, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v2, v2 v_mul_lo_u32 v5, s5, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v5, v2, v5 v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_add_nc_u32 v7, v2, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v4, v0 v_mul_lo_u32 v0, s4, v4 s_load_b128 s[4:7], s[0:1], 0x0 s_not_b32 s0, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s0, s0, s8 s_mul_i32 s0, s9, s0 s_delay_alu instid0(VALU_DEP_1) v_mul_hi_u32 v6, v4, v0 v_mul_lo_u32 v0, s21, v3 s_mul_i32 s21, s9, s8 s_add_i32 s0, s0, 1 s_sub_i32 s24, 1, s21 s_mul_i32 s23, s8, s0 s_delay_alu instid0(VALU_DEP_2) v_add_nc_u32_e32 v6, v4, v6 s_branch .LBB1_4 .LBB1_2: ; in Loop: Header=BB1_4 Depth=1 v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 .LBB1_3: ; %._crit_edge72.i ; in Loop: Header=BB1_4 Depth=1 s_set_inst_prefetch_distance 0x2 v_mul_lo_u32 v4, v9, s10 v_add_nc_u32_e32 v1, v1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_le_i32_e32 vcc_lo, s11, v1 v_add3_u32 v4, v8, v4, v10 s_or_b32 s20, vcc_lo, s20 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v5, 31, v4 v_lshlrev_b64 v[4:5], 3, v[4:5] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_u32 v4, s0, s4, v4 v_add_co_ci_u32_e64 v5, s0, s5, v5, s0 global_store_b64 v[4:5], v[2:3], off s_and_not1_b32 exec_lo, exec_lo, s20 s_cbranch_execz .LBB1_12 .LBB1_4: ; =>This Loop Header: Depth=1 ; Child Loop BB1_7 Depth 2 ; Child Loop BB1_10 Depth 3 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v3, v1, v2 v_xor_b32_e32 v3, v3, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v4, v3, v7 v_mul_hi_u32 v8, v3, v6 v_mul_lo_u32 v5, v4, s19 v_add_nc_u32_e32 v9, 1, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_lo_u32 v10, v8, s18 v_sub_nc_u32_e32 v5, v3, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_sub_nc_u32_e32 v3, v3, v10 v_xor_b32_e32 v10, s17, v2 v_xor_b32_e32 v2, s16, v2 v_cmp_le_u32_e32 vcc_lo, s19, v5 v_subrev_nc_u32_e32 v11, s19, v5 v_subrev_nc_u32_e32 v12, s18, v3 v_cndmask_b32_e32 v4, v4, v9, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_nc_u32_e32 v9, 1, v4 v_cndmask_b32_e32 v5, v5, v11, vcc_lo v_add_nc_u32_e32 v11, 1, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_le_u32_e32 vcc_lo, s19, v5 v_cndmask_b32_e32 v4, v4, v9, vcc_lo v_cmp_le_u32_e32 vcc_lo, s18, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_xor_b32_e32 v4, v4, v10 v_cndmask_b32_e32 v5, v8, v11, vcc_lo v_cndmask_b32_e32 v3, v3, v12, vcc_lo v_sub_nc_u32_e32 v11, v4, v10 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_nc_u32_e32 v8, 1, v5 v_cmp_le_u32_e32 vcc_lo, s18, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v3, v5, v8, vcc_lo v_mul_lo_u32 v8, v11, s2 s_and_not1_b32 vcc_lo, exec_lo, s14 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v3, v3, v2 v_sub_nc_u32_e32 v10, v1, v8 s_delay_alu instid0(VALU_DEP_2) v_sub_nc_u32_e32 v9, v3, v2 s_cbranch_vccnz .LBB1_2 ; %bb.5: ; %.preheader.lr.ph.i ; in Loop: Header=BB1_4 Depth=1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, v9, s13 v_mul_lo_u32 v3, s22, v11 s_mov_b32 s25, 0 v_add3_u32 v2, v1, v2, v3 s_delay_alu instid0(VALU_DEP_1) v_mul_lo_u32 v12, s21, v2 v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 s_set_inst_prefetch_distance 0x1 s_branch .LBB1_7 .p2align 6 .LBB1_6: ; %._crit_edge.i ; in Loop: Header=BB1_7 Depth=2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_add_nc_u32_e32 v12, s23, v12 s_add_i32 s25, s25, 1 s_cmp_eq_u32 s25, s9 s_cbranch_scc1 .LBB1_3 .LBB1_7: ; %.preheader.i ; Parent Loop BB1_4 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB1_10 Depth 3 s_and_not1_b32 vcc_lo, exec_lo, s15 s_cbranch_vccnz .LBB1_6 ; %bb.8: ; %.lr.ph.i ; in Loop: Header=BB1_7 Depth=2 v_subrev_nc_u32_e32 v4, s25, v11 v_mov_b32_e32 v13, v10 s_mov_b32 s26, s8 s_delay_alu instid0(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, 0, v4 v_cmp_lt_i32_e64 s0, s3, v4 v_mov_b32_e32 v4, v12 s_branch .LBB1_10 .p2align 6 .LBB1_9: ; in Loop: Header=BB1_10 Depth=3 s_or_b32 exec_lo, exec_lo, s27 v_add_nc_u32_e32 v4, s24, v4 v_add_nc_u32_e32 v13, -1, v13 s_add_i32 s26, s26, -1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s26, 0 s_cbranch_scc1 .LBB1_6 .LBB1_10: ; Parent Loop BB1_4 Depth=1 ; Parent Loop BB1_7 Depth=2 ; => This Inner Loop Header: Depth=3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i32_e64 s1, 0, v13 s_or_b32 s27, s1, vcc_lo v_cmp_ge_i32_e64 s1, s12, v13 s_or_b32 s27, s27, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s27, s27, -1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_b32 s1, s27, s1 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s27, s1 s_cbranch_execz .LBB1_9 ; %bb.11: ; in Loop: Header=BB1_10 Depth=3 v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[14:15], 3, v[4:5] s_waitcnt lgkmcnt(0) v_add_co_u32 v14, s1, s6, v14 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v15, s1, s7, v15, s1 global_load_b64 v[14:15], v[14:15], off s_waitcnt vmcnt(0) v_add_f64 v[2:3], v[2:3], v[14:15] s_branch .LBB1_9 .LBB1_12: ; %_Z11scol2im_kerIdEvPT_PKS0_iiiiii.exit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9scol2im_dPdPKdiiiiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 16 .amdhsa_next_free_sgpr 28 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z9scol2im_dPdPKdiiiiii, .Lfunc_end1-_Z9scol2im_dPdPKdiiiiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1080 ; NumSgprs: 30 ; NumVgprs: 16 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 3 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 30 ; NumVGPRsForWavesPerEU: 16 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z8im2col_fPKfPfiiiiii ; -- Begin function _Z8im2col_fPKfPfiiiiii .globl _Z8im2col_fPKfPfiiiiii .p2align 8 .type _Z8im2col_fPKfPfiiiiii,@function _Z8im2col_fPKfPfiiiiii: ; @_Z8im2col_fPKfPfiiiiii ; %bb.0: s_load_b64 s[2:3], s[0:1], 0x24 s_add_u32 s4, s0, 40 s_addc_u32 s5, s1, 0 s_mov_b32 s7, exec_lo s_waitcnt lgkmcnt(0) s_cmp_lt_u32 s15, s3 s_cselect_b32 s6, 12, 18 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) v_mov_b32_e32 v1, s6 global_load_u16 v3, v1, s[4:5] s_load_b32 s4, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_ashr_i32 s5, s4, 31 s_add_i32 s4, s4, s5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_xor_b32 s4, s4, s5 v_cvt_f32_u32_e32 v1, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_rcp_iflag_f32_e32 v1, v1 s_waitcnt_depctr 0xfff v_mul_f32_e32 v4, 0x4f7ffffe, v1 s_waitcnt vmcnt(0) v_mad_u64_u32 v[1:2], null, s15, v3, v[0:1] v_cvt_u32_f32_e32 v0, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_readfirstlane_b32 s6, v0 v_cmpx_gt_i32_e64 s2, v1 s_cbranch_execz .LBB2_8 ; %bb.1: ; %.lr.ph46.i s_sub_i32 s8, 0, s4 s_ashr_i32 s7, s2, 31 s_mul_i32 s13, s8, s6 s_add_i32 s12, s2, s7 s_clause 0x1 s_load_b64 s[8:9], s[0:1], 0x10 s_load_b64 s[10:11], s[0:1], 0x1c s_mul_hi_u32 s13, s6, s13 s_xor_b32 s12, s12, s7 s_add_i32 s6, s6, s13 s_xor_b32 s5, s7, s5 s_mul_hi_u32 s6, s12, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s13, s6, s4 s_sub_i32 s7, s12, s13 s_add_i32 s12, s6, 1 s_sub_i32 s13, s7, s4 s_cmp_ge_u32 s7, s4 s_cselect_b32 s6, s12, s6 s_cselect_b32 s7, s13, s7 s_add_i32 s12, s6, 1 s_cmp_ge_u32 s7, s4 s_cselect_b32 s4, s12, s6 s_waitcnt lgkmcnt(0) s_sub_i32 s12, s8, s10 s_xor_b32 s4, s4, s5 s_add_i32 s12, s12, 1 s_sub_i32 s4, s4, s5 s_cmp_gt_i32 s11, 0 s_cselect_b32 s13, -1, 0 s_cmp_gt_i32 s10, 0 s_cselect_b32 s14, -1, 0 s_ashr_i32 s15, s12, 31 s_ashr_i32 s17, s4, 31 s_add_i32 s5, s12, s15 s_add_i32 s4, s4, s17 s_xor_b32 s16, s5, s15 s_xor_b32 s18, s4, s17 v_cvt_f32_u32_e32 v0, s16 v_cvt_f32_u32_e32 v2, s18 s_sub_i32 s4, 0, s16 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v0, v0 v_rcp_iflag_f32_e32 v2, v2 s_waitcnt_depctr 0xfff v_mul_f32_e32 v0, 0x4f7ffffe, v0 v_mul_f32_e32 v2, 0x4f7ffffe, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cvt_u32_f32_e32 v4, v0 v_mul_lo_u32 v0, s3, v3 v_cvt_u32_f32_e32 v8, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) v_mul_lo_u32 v5, s4, v4 s_load_b128 s[4:7], s[0:1], 0x0 s_mul_i32 s0, s11, s10 s_mov_b32 s1, 0 v_mul_lo_u32 v6, s0, v1 v_mul_lo_u32 v7, v0, s0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v3, v4, v5 v_add_nc_u32_e32 v9, v4, v3 s_branch .LBB2_3 .LBB2_2: ; %._crit_edge43.i ; in Loop: Header=BB2_3 Depth=1 s_set_inst_prefetch_distance 0x2 v_add_nc_u32_e32 v1, v1, v0 v_add_nc_u32_e32 v6, v6, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_le_i32_e32 vcc_lo, s2, v1 s_or_b32 s1, vcc_lo, s1 s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execz .LBB2_8 .LBB2_3: ; =>This Loop Header: Depth=1 ; Child Loop BB2_6 Depth 2 ; Child Loop BB2_7 Depth 3 s_and_not1_b32 vcc_lo, exec_lo, s13 s_cbranch_vccnz .LBB2_2 ; %bb.4: ; %.preheader.lr.ph.i ; in Loop: Header=BB2_3 Depth=1 s_sub_i32 s0, 0, s18 v_ashrrev_i32_e32 v4, 31, v1 v_mul_lo_u32 v2, s0, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v3, v1, v4 v_mul_hi_u32 v2, v8, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v5, v3, v4 v_add_nc_u32_e32 v2, v8, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v10, v5, v2 v_mad_u64_u32 v[2:3], null, v5, v9, 0 v_mul_lo_u32 v2, v10, s18 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mul_lo_u32 v11, v3, s16 v_add_nc_u32_e32 v12, 1, v10 v_sub_nc_u32_e32 v2, v5, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v5, v5, v11 v_subrev_nc_u32_e32 v13, s18, v2 v_cmp_le_u32_e32 vcc_lo, s18, v2 v_add_nc_u32_e32 v11, 1, v3 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_cmp_le_u32_e64 s0, s16, v5 v_cndmask_b32_e32 v10, v10, v12, vcc_lo v_subrev_nc_u32_e32 v12, s16, v5 v_cndmask_b32_e32 v2, v2, v13, vcc_lo v_cndmask_b32_e64 v3, v3, v11, s0 v_xor_b32_e32 v13, s17, v4 v_add_nc_u32_e32 v11, 1, v10 v_cndmask_b32_e64 v5, v5, v12, s0 v_cmp_le_u32_e32 vcc_lo, s18, v2 v_add_nc_u32_e32 v12, 1, v3 s_mov_b32 s0, 0 v_cndmask_b32_e32 v2, v10, v11, vcc_lo v_cmp_le_u32_e32 vcc_lo, s16, v5 v_xor_b32_e32 v10, s15, v4 v_mov_b32_e32 v11, v6 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_xor_b32_e32 v4, v2, v13 v_cndmask_b32_e32 v3, v3, v12, vcc_lo v_sub_nc_u32_e32 v5, v4, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v2, v3, v10 v_mad_u64_u32 v[3:4], null, v5, s9, v[2:3] v_sub_nc_u32_e32 v2, v2, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_lo_u32 v5, v2, s12 v_sub_nc_u32_e32 v4, v3, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, s8, v4, v[1:2] v_sub_nc_u32_e32 v10, v2, v5 s_set_inst_prefetch_distance 0x1 s_branch .LBB2_6 .p2align 6 .LBB2_5: ; %._crit_edge.i ; in Loop: Header=BB2_6 Depth=2 v_add_nc_u32_e32 v11, s10, v11 v_add_nc_u32_e32 v10, s8, v10 s_add_i32 s0, s0, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s0, s11 s_cbranch_scc1 .LBB2_2 .LBB2_6: ; %.preheader.i ; Parent Loop BB2_3 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB2_7 Depth 3 s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v2, v10 v_mov_b32_e32 v4, v11 s_and_not1_b32 vcc_lo, exec_lo, s14 s_mov_b32 s3, s10 s_cbranch_vccnz .LBB2_5 .p2align 6 .LBB2_7: ; Parent Loop BB2_3 Depth=1 ; Parent Loop BB2_6 Depth=2 ; => This Inner Loop Header: Depth=3 v_ashrrev_i32_e32 v3, 31, v2 v_ashrrev_i32_e32 v5, 31, v4 s_add_i32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) s_cmp_eq_u32 s3, 0 v_lshlrev_b64 v[12:13], 2, v[2:3] v_add_nc_u32_e32 v2, 1, v2 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v12, vcc_lo, s4, v12 v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo global_load_b32 v3, v[12:13], off v_lshlrev_b64 v[12:13], 2, v[4:5] v_add_nc_u32_e32 v4, 1, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v12, vcc_lo, s6, v12 v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo s_waitcnt vmcnt(0) global_store_b32 v[12:13], v3, off s_cbranch_scc0 .LBB2_7 s_branch .LBB2_5 .LBB2_8: ; %_Z10im2col_kerIfEvPKT_PS0_iiiiii.exit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z8im2col_fPKfPfiiiiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 14 .amdhsa_next_free_sgpr 19 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z8im2col_fPKfPfiiiiii, .Lfunc_end2-_Z8im2col_fPKfPfiiiiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 896 ; NumSgprs: 21 ; NumVgprs: 14 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 21 ; NumVGPRsForWavesPerEU: 14 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z9scol2im_fPfPKfiiiiii ; -- Begin function _Z9scol2im_fPfPKfiiiiii .globl _Z9scol2im_fPfPKfiiiiii .p2align 8 .type _Z9scol2im_fPfPKfiiiiii,@function _Z9scol2im_fPfPKfiiiiii: ; @_Z9scol2im_fPfPKfiiiiii ; %bb.0: s_clause 0x1 s_load_b32 s21, s[0:1], 0x28 s_load_b32 s6, s[0:1], 0x18 s_add_u32 s2, s0, 40 s_addc_u32 s3, s1, 0 s_mov_b32 s7, exec_lo s_waitcnt lgkmcnt(0) s_cmp_lt_u32 s15, s21 s_cselect_b32 s4, 12, 18 s_ashr_i32 s5, s6, 31 v_mov_b32_e32 v1, s4 global_load_u16 v3, v1, s[2:3] s_add_i32 s2, s6, s5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_xor_b32 s4, s2, s5 s_load_b64 s[2:3], s[0:1], 0x10 v_cvt_f32_u32_e32 v1, s4 v_rcp_iflag_f32_e32 v1, v1 s_waitcnt_depctr 0xfff v_mul_f32_e32 v4, 0x4f7ffffe, v1 s_waitcnt lgkmcnt(0) s_mul_i32 s10, s3, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_mul_i32 s11, s10, s6 s_waitcnt vmcnt(0) v_mad_u64_u32 v[1:2], null, s15, v3, v[0:1] v_cvt_u32_f32_e32 v0, v4 v_readfirstlane_b32 s6, v0 s_delay_alu instid0(VALU_DEP_3) v_cmpx_gt_i32_e64 s11, v1 s_cbranch_execz .LBB3_12 ; %bb.1: ; %.lr.ph76.i s_clause 0x1 s_load_b32 s7, s[0:1], 0x24 s_load_b64 s[8:9], s[0:1], 0x1c s_sub_i32 s12, 0, s4 s_mov_b32 s20, 0 s_mul_i32 s12, s12, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_hi_u32 s12, s6, s12 s_add_i32 s6, s6, s12 s_waitcnt lgkmcnt(0) s_ashr_i32 s13, s7, 31 s_sub_i32 s3, s3, s9 s_add_i32 s7, s7, s13 s_sub_i32 s12, s2, s8 s_xor_b32 s7, s7, s13 s_xor_b32 s5, s13, s5 s_mul_hi_u32 s6, s7, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_mul_i32 s14, s6, s4 s_add_i32 s13, s6, 1 s_sub_i32 s7, s7, s14 s_sub_i32 s14, s7, s4 s_cmp_ge_u32 s7, s4 s_cselect_b32 s6, s13, s6 s_cselect_b32 s7, s14, s7 s_add_i32 s13, s6, 1 s_cmp_ge_u32 s7, s4 s_cselect_b32 s4, s13, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_xor_b32 s4, s4, s5 s_sub_i32 s13, s4, s5 s_cmp_gt_i32 s9, 0 s_cselect_b32 s14, -1, 0 s_cmp_gt_i32 s8, 0 s_cselect_b32 s15, -1, 0 s_ashr_i32 s17, s2, 31 s_ashr_i32 s16, s10, 31 s_add_i32 s5, s2, s17 s_add_i32 s4, s10, s16 s_xor_b32 s19, s5, s17 s_xor_b32 s18, s4, s16 v_cvt_f32_u32_e32 v2, s19 v_cvt_f32_u32_e32 v0, s18 s_sub_i32 s5, 0, s19 s_sub_i32 s4, 0, s18 s_sub_i32 s22, 1, s8 v_rcp_iflag_f32_e32 v2, v2 v_rcp_iflag_f32_e32 v0, v0 s_waitcnt_depctr 0xfff v_mul_f32_e32 v2, 0x4f7ffffe, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v2, v2 v_mul_lo_u32 v5, s5, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v5, v2, v5 v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_add_nc_u32 v5, v2, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v4, v0 v_mul_lo_u32 v0, s4, v4 s_load_b128 s[4:7], s[0:1], 0x0 s_not_b32 s0, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s0, s0, s8 s_mul_i32 s0, s9, s0 s_delay_alu instid0(VALU_DEP_1) v_mul_hi_u32 v6, v4, v0 v_mul_lo_u32 v0, s21, v3 s_mul_i32 s21, s9, s8 s_add_i32 s0, s0, 1 s_sub_i32 s24, 1, s21 s_mul_i32 s23, s8, s0 s_delay_alu instid0(VALU_DEP_2) v_add_nc_u32_e32 v4, v4, v6 s_branch .LBB3_4 .LBB3_2: ; in Loop: Header=BB3_4 Depth=1 v_mov_b32_e32 v6, 0 .LBB3_3: ; %._crit_edge72.i ; in Loop: Header=BB3_4 Depth=1 s_set_inst_prefetch_distance 0x2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, v8, s10 v_add_nc_u32_e32 v1, v1, v0 v_cmp_le_i32_e32 vcc_lo, s11, v1 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add3_u32 v2, v7, v2, v9 s_or_b32 s20, vcc_lo, s20 v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, s0, s4, v2 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v3, s0, s5, v3, s0 global_store_b32 v[2:3], v6, off s_and_not1_b32 exec_lo, exec_lo, s20 s_cbranch_execz .LBB3_12 .LBB3_4: ; =>This Loop Header: Depth=1 ; Child Loop BB3_7 Depth 2 ; Child Loop BB3_10 Depth 3 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v3, v1, v2 v_xor_b32_e32 v3, v3, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v6, v3, v5 v_mul_hi_u32 v8, v3, v4 v_mul_lo_u32 v7, v6, s19 v_add_nc_u32_e32 v9, 1, v6 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_lo_u32 v10, v8, s18 v_sub_nc_u32_e32 v7, v3, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_sub_nc_u32_e32 v3, v3, v10 v_xor_b32_e32 v10, s17, v2 v_xor_b32_e32 v2, s16, v2 v_cmp_le_u32_e32 vcc_lo, s19, v7 v_subrev_nc_u32_e32 v11, s19, v7 v_subrev_nc_u32_e32 v12, s18, v3 v_cndmask_b32_e32 v6, v6, v9, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_nc_u32_e32 v9, 1, v6 v_cndmask_b32_e32 v7, v7, v11, vcc_lo v_add_nc_u32_e32 v11, 1, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_le_u32_e32 vcc_lo, s19, v7 v_cndmask_b32_e32 v6, v6, v9, vcc_lo v_cmp_le_u32_e32 vcc_lo, s18, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_xor_b32_e32 v6, v6, v10 v_cndmask_b32_e32 v7, v8, v11, vcc_lo v_cndmask_b32_e32 v3, v3, v12, vcc_lo v_sub_nc_u32_e32 v10, v6, v10 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_nc_u32_e32 v8, 1, v7 v_cmp_le_u32_e32 vcc_lo, s18, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v3, v7, v8, vcc_lo v_mul_lo_u32 v7, v10, s2 s_and_not1_b32 vcc_lo, exec_lo, s14 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v3, v3, v2 v_sub_nc_u32_e32 v9, v1, v7 s_delay_alu instid0(VALU_DEP_2) v_sub_nc_u32_e32 v8, v3, v2 s_cbranch_vccnz .LBB3_2 ; %bb.5: ; %.preheader.lr.ph.i ; in Loop: Header=BB3_4 Depth=1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_mul_lo_u32 v2, v8, s13 v_mul_lo_u32 v3, s22, v10 v_mov_b32_e32 v6, 0 s_mov_b32 s25, 0 v_add3_u32 v2, v1, v2, v3 s_delay_alu instid0(VALU_DEP_1) v_mul_lo_u32 v11, s21, v2 s_set_inst_prefetch_distance 0x1 s_branch .LBB3_7 .p2align 6 .LBB3_6: ; %._crit_edge.i ; in Loop: Header=BB3_7 Depth=2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_add_nc_u32_e32 v11, s23, v11 s_add_i32 s25, s25, 1 s_cmp_eq_u32 s25, s9 s_cbranch_scc1 .LBB3_3 .LBB3_7: ; %.preheader.i ; Parent Loop BB3_4 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB3_10 Depth 3 s_and_not1_b32 vcc_lo, exec_lo, s15 s_cbranch_vccnz .LBB3_6 ; %bb.8: ; %.lr.ph.i ; in Loop: Header=BB3_7 Depth=2 v_subrev_nc_u32_e32 v2, s25, v10 v_mov_b32_e32 v12, v9 s_mov_b32 s26, s8 s_delay_alu instid0(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, 0, v2 v_cmp_lt_i32_e64 s0, s3, v2 v_mov_b32_e32 v2, v11 s_branch .LBB3_10 .p2align 6 .LBB3_9: ; in Loop: Header=BB3_10 Depth=3 s_or_b32 exec_lo, exec_lo, s27 v_add_nc_u32_e32 v2, s24, v2 v_add_nc_u32_e32 v12, -1, v12 s_add_i32 s26, s26, -1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s26, 0 s_cbranch_scc1 .LBB3_6 .LBB3_10: ; Parent Loop BB3_4 Depth=1 ; Parent Loop BB3_7 Depth=2 ; => This Inner Loop Header: Depth=3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i32_e64 s1, 0, v12 s_or_b32 s27, s1, vcc_lo v_cmp_ge_i32_e64 s1, s12, v12 s_or_b32 s27, s27, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s27, s27, -1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_b32 s1, s27, s1 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s27, s1 s_cbranch_execz .LBB3_9 ; %bb.11: ; in Loop: Header=BB3_10 Depth=3 v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[13:14], 2, v[2:3] s_waitcnt lgkmcnt(0) v_add_co_u32 v13, s1, s6, v13 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v14, s1, s7, v14, s1 global_load_b32 v3, v[13:14], off s_waitcnt vmcnt(0) v_add_f32_e32 v6, v6, v3 s_branch .LBB3_9 .LBB3_12: ; %_Z11scol2im_kerIfEvPT_PKS0_iiiiii.exit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9scol2im_fPfPKfiiiiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 15 .amdhsa_next_free_sgpr 28 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end3: .size _Z9scol2im_fPfPKfiiiiii, .Lfunc_end3-_Z9scol2im_fPfPKfiiiiii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1072 ; NumSgprs: 30 ; NumVgprs: 15 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 3 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 30 ; NumVGPRsForWavesPerEU: 15 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z8im2col_dPKdPdiiiiii .private_segment_fixed_size: 0 .sgpr_count: 21 .sgpr_spill_count: 0 .symbol: _Z8im2col_dPKdPdiiiiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 16 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9scol2im_dPdPKdiiiiii .private_segment_fixed_size: 0 .sgpr_count: 30 .sgpr_spill_count: 0 .symbol: _Z9scol2im_dPdPKdiiiiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 16 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z8im2col_fPKfPfiiiiii .private_segment_fixed_size: 0 .sgpr_count: 21 .sgpr_spill_count: 0 .symbol: _Z8im2col_fPKfPfiiiiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 14 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9scol2im_fPfPKfiiiiii .private_segment_fixed_size: 0 .sgpr_count: 30 .sgpr_spill_count: 0 .symbol: _Z9scol2im_fPfPKfiiiiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 15 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "3c711df0b11277f688cbc5ae7c1e29e10fe5ce3c.hip" .globl _Z23__device_stub__im2col_dPKdPdiiiiii # -- Begin function _Z23__device_stub__im2col_dPKdPdiiiiii .p2align 4, 0x90 .type _Z23__device_stub__im2col_dPKdPdiiiiii,@function _Z23__device_stub__im2col_dPKdPdiiiiii: # @_Z23__device_stub__im2col_dPKdPdiiiiii .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movl %r9d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 4(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) leaq 160(%rsp), %rax movq %rax, 128(%rsp) leaq 168(%rsp), %rax movq %rax, 136(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z8im2col_dPKdPdiiiiii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end0: .size _Z23__device_stub__im2col_dPKdPdiiiiii, .Lfunc_end0-_Z23__device_stub__im2col_dPKdPdiiiiii .cfi_endproc # -- End function .globl _Z24__device_stub__scol2im_dPdPKdiiiiii # -- Begin function _Z24__device_stub__scol2im_dPdPKdiiiiii .p2align 4, 0x90 .type _Z24__device_stub__scol2im_dPdPKdiiiiii,@function _Z24__device_stub__scol2im_dPdPKdiiiiii: # @_Z24__device_stub__scol2im_dPdPKdiiiiii .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movl %r9d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 4(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) leaq 160(%rsp), %rax movq %rax, 128(%rsp) leaq 168(%rsp), %rax movq %rax, 136(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9scol2im_dPdPKdiiiiii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end1: .size _Z24__device_stub__scol2im_dPdPKdiiiiii, .Lfunc_end1-_Z24__device_stub__scol2im_dPdPKdiiiiii .cfi_endproc # -- End function .globl _Z23__device_stub__im2col_fPKfPfiiiiii # -- Begin function _Z23__device_stub__im2col_fPKfPfiiiiii .p2align 4, 0x90 .type _Z23__device_stub__im2col_fPKfPfiiiiii,@function _Z23__device_stub__im2col_fPKfPfiiiiii: # @_Z23__device_stub__im2col_fPKfPfiiiiii .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movl %r9d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 4(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) leaq 160(%rsp), %rax movq %rax, 128(%rsp) leaq 168(%rsp), %rax movq %rax, 136(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z8im2col_fPKfPfiiiiii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end2: .size _Z23__device_stub__im2col_fPKfPfiiiiii, .Lfunc_end2-_Z23__device_stub__im2col_fPKfPfiiiiii .cfi_endproc # -- End function .globl _Z24__device_stub__scol2im_fPfPKfiiiiii # -- Begin function _Z24__device_stub__scol2im_fPfPKfiiiiii .p2align 4, 0x90 .type _Z24__device_stub__scol2im_fPfPKfiiiiii,@function _Z24__device_stub__scol2im_fPfPKfiiiiii: # @_Z24__device_stub__scol2im_fPfPKfiiiiii .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movl %r9d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 4(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) leaq 160(%rsp), %rax movq %rax, 128(%rsp) leaq 168(%rsp), %rax movq %rax, 136(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9scol2im_fPfPKfiiiiii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end3: .size _Z24__device_stub__scol2im_fPfPKfiiiiii, .Lfunc_end3-_Z24__device_stub__scol2im_fPfPKfiiiiii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z8im2col_dPKdPdiiiiii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9scol2im_dPdPKdiiiiii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z8im2col_fPKfPfiiiiii, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9scol2im_fPfPKfiiiiii, %esi movl $.L__unnamed_4, %edx movl $.L__unnamed_4, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z8im2col_dPKdPdiiiiii,@object # @_Z8im2col_dPKdPdiiiiii .section .rodata,"a",@progbits .globl _Z8im2col_dPKdPdiiiiii .p2align 3, 0x0 _Z8im2col_dPKdPdiiiiii: .quad _Z23__device_stub__im2col_dPKdPdiiiiii .size _Z8im2col_dPKdPdiiiiii, 8 .type _Z9scol2im_dPdPKdiiiiii,@object # @_Z9scol2im_dPdPKdiiiiii .globl _Z9scol2im_dPdPKdiiiiii .p2align 3, 0x0 _Z9scol2im_dPdPKdiiiiii: .quad _Z24__device_stub__scol2im_dPdPKdiiiiii .size _Z9scol2im_dPdPKdiiiiii, 8 .type _Z8im2col_fPKfPfiiiiii,@object # @_Z8im2col_fPKfPfiiiiii .globl _Z8im2col_fPKfPfiiiiii .p2align 3, 0x0 _Z8im2col_fPKfPfiiiiii: .quad _Z23__device_stub__im2col_fPKfPfiiiiii .size _Z8im2col_fPKfPfiiiiii, 8 .type _Z9scol2im_fPfPKfiiiiii,@object # @_Z9scol2im_fPfPKfiiiiii .globl _Z9scol2im_fPfPKfiiiiii .p2align 3, 0x0 _Z9scol2im_fPfPKfiiiiii: .quad _Z24__device_stub__scol2im_fPfPKfiiiiii .size _Z9scol2im_fPfPKfiiiiii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z8im2col_dPKdPdiiiiii" .size .L__unnamed_1, 23 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z9scol2im_dPdPKdiiiiii" .size .L__unnamed_2, 24 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z8im2col_fPKfPfiiiiii" .size .L__unnamed_3, 23 .type .L__unnamed_4,@object # @3 .L__unnamed_4: .asciz "_Z9scol2im_fPfPKfiiiiii" .size .L__unnamed_4, 24 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z23__device_stub__im2col_dPKdPdiiiiii .addrsig_sym _Z24__device_stub__scol2im_dPdPKdiiiiii .addrsig_sym _Z23__device_stub__im2col_fPKfPfiiiiii .addrsig_sym _Z24__device_stub__scol2im_fPfPKfiiiiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z8im2col_dPKdPdiiiiii .addrsig_sym _Z9scol2im_dPdPKdiiiiii .addrsig_sym _Z8im2col_fPKfPfiiiiii .addrsig_sym _Z9scol2im_fPfPKfiiiiii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80
.file "tmpxft_000dddf6_00000000-6_8848ba12778f95e2cb1cda4ce75afa67a8fffc5b.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "8848ba12778f95e2cb1cda4ce75afa67a8fffc5b.hip" .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z25encode_per_channel_kernelP6uchar4PKci .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_TID.X ; ULDC UR4, c[0x0][0x170] ; USHF.L.U32 UR4, UR4, 0x3, URZ ; S2R R3, SR_CTAID.X ; IMAD R0, R3, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R0, UR4, PT ; @P0 EXIT ; SHF.R.S32.HI R3, RZ, 0x1f, R0 ; ULDC.64 UR4, c[0x0][0x118] ; LEA.HI R2, R3.reuse, R0.reuse, RZ, 0x3 ; LEA.HI R6, R3, R0, RZ, 0x2 ; SHF.R.S32.HI R5, RZ, 0x3, R2 ; IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; SHF.R.S32.HI R7, RZ, 0x2, R6 ; IADD3 R4, P0, R5, c[0x0][0x168], RZ ; IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; LEA.HI.X.SX32 R5, R5, c[0x0][0x16c], 0x1, P0 ; LDG.E R10, [R2.64] ; LDG.E.S8 R4, [R4.64] ; LEA.HI R8, R6.reuse, R7, RZ, 0x1 ; BSSY B0, 0x3c0 ; LOP3.LUT R9, R6, 0xfffffffc, RZ, 0xc0, !PT ; LOP3.LUT R8, R8, 0x3ffffffe, RZ, 0xc0, !PT ; IMAD.IADD R9, R0, 0x1, -R9 ; IMAD.IADD R8, R7, 0x1, -R8 ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; IADD3 R7, -R9.reuse, 0x7, RZ ; ISETP.NE.AND P0, PT, R9, RZ, PT ; IMAD R7, R8, -0x4, R7 ; SHF.L.U32 R7, R0, R7, RZ ; PRMT R0, R10.reuse, 0x7770, RZ ; PRMT R5, R10.reuse, 0x7772, RZ ; LOP3.LUT R7, R7, R4, RZ, 0xc0, !PT ; PRMT R4, R10.reuse, 0x7771, RZ ; PRMT R6, R10, 0x7773, RZ ; PRMT R11, R4, 0x7610, R11 ; @!P0 BRA 0x380 ; ISETP.NE.AND P0, PT, R9, 0x1, PT ; @!P0 BRA 0x340 ; ISETP.NE.AND P0, PT, R9, 0x2, PT ; @!P0 BRA 0x300 ; ISETP.NE.AND P0, PT, R9, 0x3, PT ; @P0 BRA 0x3b0 ; ISETP.NE.AND P0, PT, R7, RZ, PT ; SEL R7, RZ, 0x1, !P0 ; LOP3.LUT R6, R7, 0xfffe, R6, 0xf8, !PT ; BRA 0x3b0 ; ISETP.NE.AND P0, PT, R7, RZ, PT ; SEL R4, RZ, 0x1, !P0 ; LOP3.LUT R5, R4, 0xfffe, R5, 0xf8, !PT ; BRA 0x3b0 ; ISETP.NE.AND P0, PT, R7, RZ, PT ; SEL R4, RZ, 0x1, !P0 ; LOP3.LUT R11, R4, 0xfffe, R11, 0xf8, !PT ; BRA 0x3b0 ; ISETP.NE.AND P0, PT, R7, RZ, PT ; SEL R7, RZ, 0x1, !P0 ; LOP3.LUT R0, R7, 0xfffe, R0, 0xf8, !PT ; BSYNC B0 ; PRMT R0, R11, 0x7604, R0 ; PRMT R5, R5, 0x7054, R0 ; PRMT R5, R6, 0x654, R5 ; STG.E [R2.64], R5 ; EXIT ; BRA 0x410; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z23encode_per_pixel_kernelP6uchar4PKci .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_TID.X ; ULDC UR4, c[0x0][0x170] ; USHF.L.U32 UR4, UR4, 0x1, URZ ; S2R R3, SR_CTAID.X ; IMAD R0, R3, c[0x0][0x0], R0 ; ISETP.GE.AND P0, PT, R0, UR4, PT ; @P0 EXIT ; LEA.HI R6, R0, R0, RZ, 0x1 ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; SHF.R.S32.HI R2, RZ, 0x1, R6 ; IADD3 R4, P0, R2, c[0x0][0x168], RZ ; LEA.HI.X.SX32 R5, R2, c[0x0][0x16c], 0x1, P0 ; IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; LDG.E.S8 R8, [R4.64] ; LDG.E R12, [R2.64] ; LOP3.LUT R7, R6, 0x3ffffffe, RZ, 0xc0, !PT ; IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; IMAD.IADD R7, R0, 0x1, -R7 ; IMAD.MOV.U32 R0, RZ, RZ, -0x4 ; IMAD R7, R7, R0, 0x7 ; IADD3 R0, R7.reuse, -0x1, RZ ; IADD3 R6, R7.reuse, -0x2, RZ ; IADD3 R10, R7, -0x3, RZ ; SHF.L.U32 R7, R11.reuse, R7, RZ ; SHF.L.U32 R5, R11.reuse, R0, RZ ; SHF.L.U32 R9, R11, R6, RZ ; SHF.L.U32 R11, R11, R10, RZ ; LOP3.LUT P0, RZ, R7, R8.reuse, RZ, 0xc0, !PT ; LOP3.LUT P1, RZ, R5, R8.reuse, RZ, 0xc0, !PT ; LOP3.LUT P2, RZ, R9, R8, RZ, 0xc0, !PT ; PRMT R0, R12.reuse, 0x7770, RZ ; PRMT R4, R12, 0x7771, RZ ; SEL R7, RZ, 0x1, !P0 ; SEL R9, RZ, 0x1, !P1 ; PRMT R5, R12, 0x7772, RZ ; SEL R6, RZ, 0x1, !P2 ; LOP3.LUT P0, RZ, R11, R8, RZ, 0xc0, !PT ; LOP3.LUT R7, R7, 0xfffe, R0, 0xf8, !PT ; LOP3.LUT R4, R9, 0xfffe, R4, 0xf8, !PT ; LOP3.LUT R6, R6, 0xfffe, R5, 0xf8, !PT ; PRMT R0, R12, 0x7773, RZ ; SEL R5, RZ, 0x1, !P0 ; PRMT R7, R4, 0x7604, R7 ; LOP3.LUT R0, R5, 0xfffe, R0, 0xf8, !PT ; PRMT R7, R6, 0x7054, R7 ; PRMT R7, R0, 0x654, R7 ; STG.E [R2.64], R7 ; EXIT ; BRA 0x320; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000837e7_00000000-6_23f802941d946b2004d35f3d535ef9899fa52486.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4042: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4042: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci .type _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci, @function _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci: .LFB4064: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z23encode_per_pixel_kernelP6uchar4PKci(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE4064: .size _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci, .-_Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci .globl _Z23encode_per_pixel_kernelP6uchar4PKci .type _Z23encode_per_pixel_kernelP6uchar4PKci, @function _Z23encode_per_pixel_kernelP6uchar4PKci: .LFB4065: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4065: .size _Z23encode_per_pixel_kernelP6uchar4PKci, .-_Z23encode_per_pixel_kernelP6uchar4PKci .globl _Z15encode_parallelPK6uchar4PS_PKcimm .type _Z15encode_parallelPK6uchar4PS_PKcimm, @function _Z15encode_parallelPK6uchar4PS_PKcimm: .LFB4039: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %rdi, %r14 movq %rsi, %r12 movq %rdx, %r13 movl %ecx, %ebp movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax imulq %r9, %r8 leaq 0(,%r8,4), %rbx movq %rsp, %rdi movq %rbx, %rsi call cudaMalloc@PLT movslq %ebp, %r15 leaq 8(%rsp), %rdi movq %r15, %rsi call cudaMalloc@PLT movl $1, %ecx movq %rbx, %rdx movq %r14, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %r15, %rdx movq %r13, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT pxor %xmm0, %xmm0 cvtsi2sdl %ebp, %xmm0 addsd %xmm0, %xmm0 cvttsd2sil %xmm0, %eax pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 mulss .LC0(%rip), %xmm0 movaps %xmm0, %xmm3 movss .LC4(%rip), %xmm2 movaps %xmm0, %xmm1 andps %xmm2, %xmm1 movss .LC1(%rip), %xmm4 ucomiss %xmm1, %xmm4 jbe .L12 cvttss2sil %xmm0, %eax pxor %xmm1, %xmm1 cvtsi2ssl %eax, %xmm1 cmpnless %xmm1, %xmm3 movss .LC3(%rip), %xmm4 andps %xmm4, %xmm3 addss %xmm1, %xmm3 andnps %xmm0, %xmm2 orps %xmm2, %xmm3 .L12: movl $1024, 28(%rsp) movl $1, 32(%rsp) cvttss2sil %xmm3, %eax movl %eax, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L16 .L13: movl $2, %ecx movq %rbx, %rdx movq (%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L17 addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L16: .cfi_restore_state movl %ebp, %edx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci jmp .L13 .L17: call __stack_chk_fail@PLT .cfi_endproc .LFE4039: .size _Z15encode_parallelPK6uchar4PS_PKcimm, .-_Z15encode_parallelPK6uchar4PS_PKcimm .globl _Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci .type _Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci, @function _Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci: .LFB4066: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L22 .L18: movq 120(%rsp), %rax subq %fs:40, %rax jne .L23 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L22: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z25encode_per_channel_kernelP6uchar4PKci(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L18 .L23: call __stack_chk_fail@PLT .cfi_endproc .LFE4066: .size _Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci, .-_Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci .globl _Z25encode_per_channel_kernelP6uchar4PKci .type _Z25encode_per_channel_kernelP6uchar4PKci, @function _Z25encode_per_channel_kernelP6uchar4PKci: .LFB4067: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4067: .size _Z25encode_per_channel_kernelP6uchar4PKci, .-_Z25encode_per_channel_kernelP6uchar4PKci .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC5: .string "_Z25encode_per_channel_kernelP6uchar4PKci" .align 8 .LC6: .string "_Z23encode_per_pixel_kernelP6uchar4PKci" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4069: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _Z25encode_per_channel_kernelP6uchar4PKci(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z23encode_per_pixel_kernelP6uchar4PKci(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4069: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 981467136 .align 4 .LC1: .long 1258291200 .align 4 .LC3: .long 1065353216 .align 4 .LC4: .long 2147483647 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci ; -- Begin function _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci .globl _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci .p2align 8 .type _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci,@function _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci: ; @_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b32 s3, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_lshl_b32 s2, s3, 1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s2, v1 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b128 s[0:3], s[0:1], 0x0 v_lshrrev_b32_e32 v0, 31, v1 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v0, v1, v0 v_lshlrev_b64 v[2:3], 2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v4, 1, v0 v_and_b32_e32 v0, 0x3ffffffe, v0 v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_2) v_sub_nc_u32_e32 v0, v1, v0 s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s0, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo v_add_co_u32 v4, vcc_lo, s2, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo v_lshlrev_b32_e32 v0, 2, v0 global_load_u8 v6, v[2:3], off global_load_i8 v4, v[4:5], off s_clause 0x2 global_load_u8 v5, v[2:3], off offset:1 global_load_u8 v7, v[2:3], off offset:2 global_load_u8 v8, v[2:3], off offset:3 v_sub_nc_u32_e32 v1, 7, v0 v_sub_nc_u32_e32 v9, 6, v0 v_sub_nc_u32_e32 v10, 5, v0 v_sub_nc_u32_e32 v0, 4, v0 s_waitcnt vmcnt(4) v_and_b32_e32 v6, 0xfe, v6 s_waitcnt vmcnt(3) v_lshrrev_b32_e32 v1, v1, v4 v_lshrrev_b32_e32 v9, v9, v4 v_lshrrev_b32_e32 v10, v10, v4 v_lshrrev_b32_e32 v0, v0, v4 s_waitcnt vmcnt(2) v_and_b32_e32 v5, 0xfe, v5 v_and_b32_e32 v1, 1, v1 s_waitcnt vmcnt(0) v_and_b32_e32 v4, 0xfe, v8 v_and_b32_e32 v8, 1, v9 v_and_b32_e32 v7, 0xfe, v7 v_and_b32_e32 v9, 1, v10 v_and_b32_e32 v0, 1, v0 v_or_b32_e32 v1, v1, v6 v_or_b32_e32 v5, v8, v5 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_or_b32_e32 v6, v9, v7 v_or_b32_e32 v0, v4, v0 s_clause 0x3 global_store_b8 v[2:3], v1, off global_store_b8 v[2:3], v5, off offset:1 global_store_b8 v[2:3], v6, off offset:2 global_store_b8 v[2:3], v0, off offset:3 .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, .Lfunc_end0-_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 364 ; NumSgprs: 18 ; NumVgprs: 11 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 11 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci ; -- Begin function _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci .globl _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci .p2align 8 .type _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci,@function _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci: ; @_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b32 s3, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1] s_lshl_b32 s2, s3, 3 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s2, v2 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB1_18 ; %bb.1: ; %NodeBlock45 v_ashrrev_i32_e32 v0, 31, v2 s_load_b128 s[0:3], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshrrev_b32_e32 v1, 29, v0 v_lshrrev_b32_e32 v0, 30, v0 v_add_nc_u32_e32 v7, v2, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v8, v2, v0 v_ashrrev_i32_e32 v1, 3, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_ashrrev_i32_e32 v0, 2, v8 v_and_b32_e32 v7, -8, v7 v_and_b32_e32 v8, -4, v8 v_ashrrev_i32_e32 v4, 31, v1 s_waitcnt lgkmcnt(0) v_add_co_u32 v3, vcc_lo, s2, v1 v_ashrrev_i32_e32 v1, 31, v0 v_sub_nc_u32_e32 v7, v7, v2 v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo v_sub_nc_u32_e32 v2, v2, v8 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[0:1], 2, v[0:1] v_add_nc_u32_e32 v7, 7, v7 global_load_i8 v9, v[3:4], off v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_clause 0x3 global_load_u8 v6, v[0:1], off global_load_u8 v4, v[0:1], off offset:1 global_load_u8 v5, v[0:1], off offset:2 global_load_u8 v3, v[0:1], off offset:3 s_mov_b32 s1, exec_lo s_waitcnt vmcnt(4) v_lshrrev_b32_e32 v7, v7, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v7, 1, v7 v_cmp_eq_u32_e64 s0, 1, v7 v_cmpx_lt_i32_e32 1, v2 s_xor_b32 s1, exec_lo, s1 s_cbranch_execz .LBB1_9 ; %bb.2: ; %NodeBlock43 s_mov_b32 s2, exec_lo v_cmpx_lt_i32_e32 2, v2 s_xor_b32 s2, exec_lo, s2 s_cbranch_execz .LBB1_6 ; %bb.3: ; %LeafBlock41 s_mov_b32 s3, exec_lo v_cmpx_eq_u32_e32 3, v2 s_cbranch_execz .LBB1_5 ; %bb.4: s_waitcnt vmcnt(0) v_and_b32_e32 v2, -2, v3 v_cndmask_b32_e64 v3, 0, 1, s0 s_delay_alu instid0(VALU_DEP_1) v_or_b32_e32 v3, v2, v3 .LBB1_5: ; %Flow s_or_b32 exec_lo, exec_lo, s3 .LBB1_6: ; %Flow47 s_and_not1_saveexec_b32 s2, s2 s_cbranch_execz .LBB1_8 ; %bb.7: s_waitcnt vmcnt(1) v_and_b32_e32 v2, -2, v5 v_cndmask_b32_e64 v5, 0, 1, s0 s_delay_alu instid0(VALU_DEP_1) v_or_b32_e32 v5, v2, v5 .LBB1_8: ; %Flow48 s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $vgpr2 .LBB1_9: ; %Flow52 s_and_not1_saveexec_b32 s1, s1 s_cbranch_execz .LBB1_17 ; %bb.10: ; %NodeBlock s_mov_b32 s2, exec_lo v_cmpx_lt_i32_e32 0, v2 s_xor_b32 s2, exec_lo, s2 s_cbranch_execz .LBB1_12 ; %bb.11: s_waitcnt vmcnt(2) v_and_b32_e32 v2, -2, v4 v_cndmask_b32_e64 v4, 0, 1, s0 s_delay_alu instid0(VALU_DEP_1) v_or_b32_e32 v4, v2, v4 ; implicit-def: $vgpr2 .LBB1_12: ; %Flow50 s_and_not1_saveexec_b32 s2, s2 s_cbranch_execz .LBB1_16 ; %bb.13: ; %LeafBlock s_mov_b32 s3, exec_lo v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB1_15 ; %bb.14: s_waitcnt vmcnt(3) v_and_b32_e32 v2, -2, v6 v_cndmask_b32_e64 v6, 0, 1, s0 s_delay_alu instid0(VALU_DEP_1) v_or_b32_e32 v6, v2, v6 .LBB1_15: ; %Flow49 s_or_b32 exec_lo, exec_lo, s3 .LBB1_16: ; %Flow51 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 .LBB1_17: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_waitcnt vmcnt(3) global_store_b8 v[0:1], v6, off s_waitcnt vmcnt(2) global_store_b8 v[0:1], v4, off offset:1 s_waitcnt vmcnt(1) global_store_b8 v[0:1], v5, off offset:2 s_waitcnt vmcnt(0) global_store_b8 v[0:1], v3, off offset:3 .LBB1_18: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, .Lfunc_end1-_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 528 ; NumSgprs: 18 ; NumVgprs: 10 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 10 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "23f802941d946b2004d35f3d535ef9899fa52486.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci # -- Begin function _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci .p2align 4, 0x90 .type _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci,@function _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci: # @_Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, .Lfunc_end0-_Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci .cfi_endproc # -- End function .globl _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci # -- Begin function _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci .p2align 4, 0x90 .type _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci,@function _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci: # @_Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end1: .size _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, .Lfunc_end1-_Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function _Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm .LCPI2_0: .long 0x3a800000 # float 9.765625E-4 .text .globl _Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm .p2align 4, 0x90 .type _Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm,@function _Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm: # @_Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $120, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r8, %rbx movl %ecx, %ebp movq %rdx, %r15 movq %rsi, %r14 movq %rdi, %r12 imulq %r9, %rbx shlq $2, %rbx leaq 8(%rsp), %rdi movq %rbx, %rsi callq hipMalloc movslq %ebp, %r13 leaq 16(%rsp), %rdi movq %r13, %rsi callq hipMalloc movq 8(%rsp), %rdi movq %r12, %rsi movq %rbx, %rdx movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi movq %r15, %rsi movq %r13, %rdx movl $1, %ecx callq hipMemcpy addl %r13d, %r13d cvtsi2ss %r13d, %xmm0 mulss .LCPI2_0(%rip), %xmm0 callq ceilf@PLT cvttss2si %xmm0, %edi movabsq $4294967296, %rdx # imm = 0x100000000 orq %rdx, %rdi orq $1024, %rdx # imm = 0x400 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: movq 8(%rsp), %rax movq 16(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movl %ebp, 28(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 28(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_2: movq 8(%rsp), %rsi movq %r14, %rdi movq %rbx, %rdx movl $2, %ecx callq hipMemcpy movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree addq $120, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm, .Lfunc_end2-_Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci,@object # @_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci .section .rodata,"a",@progbits .globl _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci .p2align 3, 0x0 _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci: .quad _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci .size _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, 8 .type _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci,@object # @_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci .globl _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci .p2align 3, 0x0 _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci: .quad _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci .size _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci" .size .L__unnamed_1, 57 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci" .size .L__unnamed_2, 59 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci .addrsig_sym _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci .addrsig_sym _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
3,040
4,623
7,148
4,660
176
code for sm_80 Function : default_function_kernel0 .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_TID.X ; HFMA2.MMA R3, -RZ, RZ, 0, 0 ; MOV R91, RZ ; HFMA2.MMA R87, -RZ, RZ, 0, 0 ; MOV R85, RZ ; HFMA2.MMA R55, -RZ, RZ, 0, 0 ; CS2R R76, SRZ ; HFMA2.MMA R93, -RZ, RZ, 0, 0 ; MOV R89, RZ ; HFMA2.MMA R81, -RZ, RZ, 0, 0 ; CS2R R52, SRZ ; HFMA2.MMA R69, -RZ, RZ, 0, 0 ; CS2R R70, SRZ ; HFMA2.MMA R63, -RZ, RZ, 0, 0 ; MOV R83, RZ ; HFMA2.MMA R57, -RZ, RZ, 0, 0 ; CS2R R6, SRZ ; HFMA2.MMA R45, -RZ, RZ, 0, 0 ; CS2R R40, SRZ ; CS2R R42, SRZ ; CS2R R58, SRZ ; CS2R R64, SRZ ; MOV R79, RZ ; ULDC.64 UR4, c[0x0][0x118] ; MOV R67, RZ ; MOV R61, RZ ; MOV R47, RZ ; S2R R5, SR_CTAID.X ; LEA R4, R3, R0, 0x5 ; MOV R2, 0x4 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; IMAD.WIDE R8, R4, R2, c[0x0][0x160] ; LDG.E.CONSTANT R13, [R8.64] ; LDG.E.CONSTANT R15, [R8.64+0x800] ; LDG.E.CONSTANT R17, [R8.64+0x1000] ; LEA R11, R5, R4, 0xf ; LDG.E.CONSTANT R19, [R8.64+0x1800] ; IMAD.WIDE R10, R11, R2, c[0x0][0x168] ; LDG.E.CONSTANT R21, [R8.64+0x2000] ; LDG.E.CONSTANT R23, [R8.64+0x2800] ; LDG.E.CONSTANT R25, [R8.64+0x3000] ; LDG.E.CONSTANT R27, [R8.64+0x3800] ; LDG.E.CONSTANT R29, [R8.64+0x4000] ; LDG.E.CONSTANT R31, [R8.64+0x4800] ; LDG.E.CONSTANT R33, [R8.64+0x5000] ; LDG.E.CONSTANT R35, [R8.64+0x5800] ; LDG.E.CONSTANT R37, [R8.64+0x6000] ; LDG.E.CONSTANT R39, [R8.64+0x6800] ; LDG.E.CONSTANT R49, [R8.64+0x7000] ; LDG.E.CONSTANT R51, [R8.64+0x7800] ; LDG.E.CONSTANT R73, [R10.64] ; LDG.E.CONSTANT R75, [R10.64+0x800] ; LDG.E.CONSTANT R4, [R10.64+0x1000] ; LDG.E.CONSTANT R12, [R10.64+0x1800] ; LDG.E.CONSTANT R14, [R10.64+0x2000] ; LDG.E.CONSTANT R16, [R10.64+0x2800] ; LDG.E.CONSTANT R18, [R10.64+0x3000] ; LDG.E.CONSTANT R20, [R10.64+0x3800] ; LDG.E.CONSTANT R22, [R10.64+0x4000] ; LDG.E.CONSTANT R24, [R10.64+0x4800] ; LDG.E.CONSTANT R9, [R10.64+0x5000] ; LDG.E.CONSTANT R8, [R10.64+0x5800] ; LDG.E.CONSTANT R26, [R10.64+0x14000] ; LDG.E.CONSTANT R28, [R10.64+0x14800] ; LDG.E.CONSTANT R30, [R10.64+0x15000] ; LDG.E.CONSTANT R32, [R10.64+0x15800] ; LDG.E.CONSTANT R34, [R10.64+0x16000] ; LDG.E.CONSTANT R36, [R10.64+0x16800] ; LDG.E.CONSTANT R38, [R10.64+0x17000] ; LDG.E.CONSTANT R44, [R10.64+0x17800] ; LDG.E.CONSTANT R46, [R10.64+0x18000] ; LDG.E.CONSTANT R48, [R10.64+0x18800] ; LDG.E.CONSTANT R50, [R10.64+0x19000] ; LDG.E.CONSTANT R54, [R10.64+0x19800] ; LDG.E.CONSTANT R56, [R10.64+0x1a000] ; LDG.E.CONSTANT R60, [R10.64+0x1a800] ; LDG.E.CONSTANT R62, [R10.64+0x1b000] ; LDG.E.CONSTANT R66, [R10.64+0x1b800] ; LDG.E.CONSTANT R68, [R10.64+0x1c000] ; LDG.E.CONSTANT R78, [R10.64+0x1c800] ; LDG.E.CONSTANT R80, [R10.64+0x1d000] ; LDG.E.CONSTANT R82, [R10.64+0x1d800] ; LDG.E.CONSTANT R84, [R10.64+0x1e000] ; LDG.E.CONSTANT R86, [R10.64+0x1e800] ; LDG.E.CONSTANT R88, [R10.64+0x1f000] ; LDG.E.CONSTANT R90, [R10.64+0x1f800] ; STS [R0.X4], R13 ; STS [R0.X4+0x80], R15 ; STS [R0.X4+0x100], R17 ; STS [R0.X4+0x180], R19 ; LDG.E.CONSTANT R13, [R10.64+0x6000] ; STS [R0.X4+0x200], R21 ; STS [R0.X4+0x280], R23 ; STS [R0.X4+0x300], R25 ; STS [R0.X4+0x380], R27 ; STS [R0.X4+0x400], R29 ; STS [R0.X4+0x480], R31 ; STS [R0.X4+0x500], R33 ; STS [R0.X4+0x580], R35 ; STS [R0.X4+0x600], R37 ; STS [R0.X4+0x680], R39 ; STS [R0.X4+0x700], R49 ; STS [R0.X4+0x780], R51 ; STS [R0.X4+0x800], R73 ; STS [R0.X4+0x880], R75 ; STS [R0.X4+0x900], R4 ; STS [R0.X4+0x980], R12 ; STS [R0.X4+0xa00], R14 ; STS [R0.X4+0xa80], R16 ; STS [R0.X4+0xb00], R18 ; STS [R0.X4+0xb80], R20 ; STS [R0.X4+0xc00], R22 ; STS [R0.X4+0xc80], R24 ; STS [R0.X4+0xd00], R9 ; STS [R0.X4+0xd80], R8 ; LDG.E.CONSTANT R15, [R10.64+0x6800] ; LDG.E.CONSTANT R17, [R10.64+0x7000] ; LDG.E.CONSTANT R19, [R10.64+0x7800] ; LDG.E.CONSTANT R21, [R10.64+0x8000] ; LDG.E.CONSTANT R23, [R10.64+0x8800] ; LDG.E.CONSTANT R25, [R10.64+0x9000] ; LDG.E.CONSTANT R27, [R10.64+0x9800] ; LDG.E.CONSTANT R29, [R10.64+0xa000] ; LDG.E.CONSTANT R9, [R10.64+0xa800] ; LDG.E.CONSTANT R31, [R10.64+0xb000] ; LDG.E.CONSTANT R33, [R10.64+0xb800] ; LDG.E.CONSTANT R35, [R10.64+0xc000] ; LDG.E.CONSTANT R37, [R10.64+0xc800] ; LDG.E.CONSTANT R39, [R10.64+0xd000] ; LDG.E.CONSTANT R49, [R10.64+0xd800] ; LDG.E.CONSTANT R51, [R10.64+0xe000] ; LDG.E.CONSTANT R73, [R10.64+0xe800] ; LDG.E.CONSTANT R75, [R10.64+0xf000] ; LDG.E.CONSTANT R4, [R10.64+0xf800] ; LDG.E.CONSTANT R8, [R10.64+0x10000] ; LDG.E.CONSTANT R12, [R10.64+0x10800] ; LDG.E.CONSTANT R14, [R10.64+0x11000] ; LDG.E.CONSTANT R16, [R10.64+0x11800] ; LDG.E.CONSTANT R18, [R10.64+0x12000] ; LDG.E.CONSTANT R20, [R10.64+0x12800] ; LDG.E.CONSTANT R22, [R10.64+0x13000] ; LDG.E.CONSTANT R24, [R10.64+0x13800] ; STS [R0.X4+0x1c00], R26 ; STS [R0.X4+0x1c80], R28 ; STS [R0.X4+0x1d00], R30 ; STS [R0.X4+0x1d80], R32 ; STS [R0.X4+0x1e00], R34 ; STS [R0.X4+0x1e80], R36 ; STS [R0.X4+0x1f00], R38 ; STS [R0.X4+0x1f80], R44 ; STS [R0.X4+0x2000], R46 ; STS [R0.X4+0x2080], R48 ; STS [R0.X4+0x2100], R50 ; STS [R0.X4+0x2180], R54 ; STS [R0.X4+0x2200], R56 ; STS [R0.X4+0x2280], R60 ; STS [R0.X4+0x2300], R62 ; STS [R0.X4+0x2380], R66 ; STS [R0.X4+0x2400], R68 ; STS [R0.X4+0x2480], R78 ; STS [R0.X4+0x2500], R80 ; STS [R0.X4+0x2580], R82 ; STS [R0.X4+0x2600], R84 ; STS [R0.X4+0x2680], R86 ; STS [R0.X4+0x2700], R88 ; STS [R0.X4+0xe00], R13 ; STS [R0.X4+0x2780], R90 ; STS [R0.X4+0xe80], R15 ; STS [R0.X4+0xf00], R17 ; STS [R0.X4+0xf80], R19 ; STS [R0.X4+0x1000], R21 ; STS [R0.X4+0x1080], R23 ; STS [R0.X4+0x1100], R25 ; STS [R0.X4+0x1180], R27 ; STS [R0.X4+0x1200], R29 ; STS [R0.X4+0x1280], R9 ; STS [R0.X4+0x1300], R31 ; STS [R0.X4+0x1380], R33 ; STS [R0.X4+0x1400], R35 ; STS [R0.X4+0x1480], R37 ; STS [R0.X4+0x1500], R39 ; STS [R0.X4+0x1580], R49 ; STS [R0.X4+0x1600], R51 ; STS [R0.X4+0x1680], R73 ; STS [R0.X4+0x1700], R75 ; STS [R0.X4+0x1780], R4 ; STS [R0.X4+0x1800], R8 ; STS [R0.X4+0x1880], R12 ; STS [R0.X4+0x1900], R14 ; STS [R0.X4+0x1980], R16 ; STS [R0.X4+0x1a00], R18 ; STS [R0.X4+0x1a80], R20 ; STS [R0.X4+0x1b00], R22 ; STS [R0.X4+0x1b80], R24 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; SHF.L.U32 R4, R0, 0x8, RZ ; LDS.128 R72, [R4+0x800] ; LDS.128 R12, [RZ] ; LDS.128 R24, [R4+0x880] ; LDS.128 R32, [0x80] ; LDS.128 R20, [0x100] ; LDS.128 R8, [0x180] ; LDS.128 R16, [0x200] ; LDS.128 R36, [0x280] ; FFMA R28, R72, R12, R7 ; FFMA R6, R12, R24, R6 ; FFMA R7, R73, R13, R28 ; LDS.128 R28, [0x300] ; FFMA R13, R13, R25, R6 ; FFMA R6, R74, R14, R7 ; FFMA R14, R14, R26, R13 ; FFMA R12, R72, R32, R81 ; FFMA R52, R72, R20, R52 ; FFMA R6, R75, R15, R6 ; FFMA R7, R15, R27, R14 ; FFMA R32, R24, R32, R83 ; FFMA R13, R73.reuse, R33, R12 ; FFMA R15, R73, R21, R52 ; FFMA R33, R25.reuse, R33, R32 ; FFMA R56, R74.reuse, R34, R13 ; FFMA R52, R74, R22, R15 ; FFMA R20, R24, R20, R70 ; LDS.128 R12, [0x380] ; FFMA R54, R26, R34, R33 ; FFMA R21, R25, R21, R20 ; FFMA R56, R75, R35.reuse, R56 ; FFMA R54, R27, R35, R54 ; LDS.128 R32, [0x400] ; FFMA R50, R26, R22, R21 ; FFMA R20, R72.reuse, R8, R53 ; FFMA R22, R72, R16.reuse, R89 ; FFMA R16, R24, R16, R76 ; FFMA R8, R24, R8, R93 ; FFMA R52, R75, R23.reuse, R52 ; FFMA R50, R27, R23, R50 ; FFMA R21, R73.reuse, R9, R20 ; FFMA R23, R73, R17.reuse, R22 ; FFMA R17, R25, R17, R16 ; FFMA R9, R25, R9, R8 ; FFMA R44, R74.reuse, R18, R23 ; FFMA R48, R74, R10, R21 ; FFMA R18, R26.reuse, R18, R17 ; LDS.128 R20, [0x480] ; FFMA R46, R26, R10, R9 ; FFMA R93, R27, R19, R18 ; FFMA R48, R75, R11.reuse, R48 ; FFMA R46, R27, R11, R46 ; FFMA R16, R72.reuse, R36, R55 ; LDS.128 R8, [0x500] ; FFMA R18, R72, R28.reuse, R87 ; FFMA R28, R24, R28, R91 ; FFMA R44, R75, R19, R44 ; FFMA R36, R24, R36, R85 ; FFMA R17, R73.reuse, R37, R16 ; FFMA R19, R73, R29.reuse, R18 ; FFMA R29, R25.reuse, R29, R28 ; FFMA R37, R25, R37, R36 ; FFMA R28, R74, R38, R17 ; FFMA R36, R74, R30.reuse, R19 ; FFMA R30, R26, R30, R29 ; LDS.128 R16, [0x580] ; FFMA R91, R75.reuse, R39, R28 ; FFMA R87, R75, R31.reuse, R36 ; FFMA R85, R27, R31, R30 ; LDS.128 R28, [0x600] ; FFMA R40, R72, R12, R40 ; FFMA R12, R24, R12, R42 ; FFMA R38, R26, R38, R37 ; FFMA R37, R73, R13.reuse, R40 ; FFMA R13, R25, R13, R12 ; FFMA R58, R72, R32, R58 ; FFMA R12, R74, R14, R37 ; FFMA R89, R27, R39, R38 ; FFMA R32, R24, R32, R64 ; FFMA R14, R26, R14, R13 ; FFMA R39, R73, R33.reuse, R58 ; FFMA R33, R25, R33, R32 ; FFMA R32, R74, R34, R39 ; FFMA R55, R75, R15.reuse, R12 ; LDS.128 R36, [0x780] ; FFMA R53, R27, R15, R14 ; LDS.128 R12, [0x680] ; FFMA R51, R75, R35.reuse, R32 ; FFMA R34, R26, R34, R33 ; FFMA R32, R72, R20.reuse, R41 ; FFMA R20, R24, R20, R43 ; LDS.128 R40, [0x700] ; FFMA R49, R27, R35, R34 ; FFMA R34, R72, R8.reuse, R77 ; FFMA R8, R24, R8, R79 ; FFMA R35, R73.reuse, R9, R34 ; FFMA R33, R73, R21, R32 ; FFMA R9, R25.reuse, R9, R8 ; FFMA R21, R25, R21, R20 ; FFMA R20, R74.reuse, R10, R35 ; FFMA R8, R74, R22, R33 ; FFMA R10, R26, R10, R9 ; FFMA R32, R72, R16, R71 ; FFMA R22, R26, R22, R21 ; FFMA R16, R24, R16, R69 ; FFMA R33, R73, R17, R32 ; LDS.128 R68, [R4+0x810] ; FFMA R83, R75.reuse, R23, R8 ; FFMA R79, R75, R11.reuse, R20 ; FFMA R77, R27, R11, R10 ; FFMA R17, R25, R17, R16 ; LDS.128 R8, [0x10] ; FFMA R81, R27, R23, R22 ; FFMA R16, R72, R28, R67 ; LDS.128 R20, [R4+0x890] ; FFMA R32, R74, R18.reuse, R33 ; FFMA R18, R26, R18, R17 ; FFMA R17, R73, R29, R16 ; FFMA R28, R24, R28, R65 ; FFMA R67, R75, R19, R32 ; FFMA R65, R27, R19, R18 ; LDS.128 R32, [0x90] ; FFMA R58, R74, R30, R17 ; LDS.128 R16, [0x110] ; FFMA R29, R25, R29, R28 ; FFMA R28, R72, R12.reuse, R63 ; FFMA R12, R24, R12, R61 ; FFMA R30, R26, R30, R29 ; FFMA R29, R73, R13.reuse, R28 ; FFMA R13, R25, R13, R12 ; FFMA R12, R72, R40, R59 ; FFMA R28, R74, R14.reuse, R29 ; FFMA R14, R26, R14, R13 ; FFMA R40, R24, R40, R57 ; FFMA R13, R73, R41, R12 ; FFMA R63, R75, R31, R58 ; FFMA R61, R27, R31, R30 ; FFMA R59, R75, R15, R28 ; FFMA R41, R25, R41, R40 ; LDS.128 R28, [0x210] ; FFMA R24, R24, R36, R45 ; FFMA R57, R27, R15, R14 ; FFMA R40, R74, R42, R13 ; FFMA R72, R72, R36, R47 ; LDS.128 R12, [0x190] ; FFMA R25, R25, R37.reuse, R24 ; FFMA R73, R73, R37, R72 ; FFMA R42, R26.reuse, R42, R41 ; FFMA R26, R26, R38.reuse, R25 ; FFMA R74, R74, R38, R73 ; FFMA R6, R68, R8, R6 ; FFMA R8, R8, R20, R7 ; FFMA R47, R75, R43.reuse, R40 ; FFMA R45, R27, R43, R42 ; FFMA R75, R75, R39.reuse, R74 ; LDS.128 R40, [0x710] ; FFMA R73, R27, R39, R26 ; FFMA R7, R69, R9, R6 ; LDS.128 R36, [0x290] ; FFMA R9, R9, R21, R8 ; LDS.128 R24, [0x310] ; FFMA R6, R70, R10, R7 ; FFMA R10, R10, R22, R9 ; FFMA R56, R68.reuse, R32, R56 ; FFMA R52, R68, R16, R52 ; FFMA R6, R71, R11, R6 ; FFMA R7, R11, R23, R10 ; FFMA R9, R69.reuse, R33, R56 ; FFMA R11, R69, R17, R52 ; FFMA R54, R20, R32, R54 ; FFMA R56, R70.reuse, R34, R9 ; FFMA R52, R70, R18, R11 ; LDS.128 R8, [0x390] ; FFMA R50, R20, R16, R50 ; FFMA R33, R21.reuse, R33, R54 ; FFMA R17, R21, R17, R50 ; FFMA R54, R22.reuse, R34, R33 ; FFMA R50, R22, R18, R17 ; FFMA R44, R68, R28, R44 ; FFMA R56, R71, R35, R56 ; FFMA R54, R23, R35, R54 ; FFMA R28, R20, R28, R93 ; LDS.128 R32, [0x410] ; FFMA R48, R68, R12.reuse, R48 ; FFMA R52, R71, R19.reuse, R52 ; FFMA R50, R23, R19, R50 ; FFMA R46, R20, R12, R46 ; FFMA R19, R69, R29.reuse, R44 ; FFMA R29, R21, R29, R28 ; FFMA R17, R69, R13.reuse, R48 ; FFMA R13, R21, R13, R46 ; FFMA R44, R70, R30.reuse, R19 ; FFMA R30, R22, R30, R29 ; FFMA R48, R70, R14.reuse, R17 ; FFMA R46, R22, R14, R13 ; LDS.128 R16, [0x490] ; FFMA R93, R23, R31, R30 ; FFMA R28, R68.reuse, R36, R91 ; FFMA R30, R68, R24, R87 ; FFMA R48, R71, R15, R48 ; FFMA R46, R23, R15, R46 ; LDS.128 R12, [0x510] ; FFMA R24, R20.reuse, R24, R85 ; FFMA R44, R71, R31, R44 ; FFMA R36, R20, R36, R89 ; FFMA R29, R69.reuse, R37, R28 ; FFMA R31, R69, R25, R30 ; FFMA R25, R21.reuse, R25, R24 ; FFMA R37, R21, R37, R36 ; FFMA R24, R70.reuse, R38, R29 ; FFMA R36, R70, R26.reuse, R31 ; FFMA R26, R22, R26, R25 ; LDS.128 R28, [0x590] ; FFMA R91, R71, R39, R24 ; FFMA R87, R71, R27.reuse, R36 ; FFMA R85, R23, R27, R26 ; FFMA R36, R68, R8.reuse, R55 ; LDS.128 R24, [0x610] ; FFMA R8, R20, R8, R53 ; FFMA R38, R22, R38, R37 ; FFMA R37, R69, R9, R36 ; FFMA R9, R21, R9, R8 ; FFMA R8, R70, R10.reuse, R37 ; FFMA R10, R22, R10, R9 ; FFMA R89, R23, R39, R38 ; FFMA R38, R68, R32.reuse, R51 ; FFMA R32, R20, R32, R49 ; FFMA R55, R71, R11.reuse, R8 ; FFMA R53, R23, R11, R10 ; LDS.128 R8, [0x690] ; FFMA R39, R69, R33.reuse, R38 ; FFMA R33, R21, R33, R32 ; FFMA R32, R70, R34.reuse, R39 ; FFMA R34, R22, R34, R33 ; LDS.128 R36, [0x790] ; FFMA R51, R71, R35, R32 ; FFMA R49, R23, R35, R34 ; FFMA R32, R68, R16.reuse, R83 ; FFMA R16, R20, R16, R81 ; FFMA R34, R68, R12.reuse, R79 ; FFMA R12, R20, R12, R77 ; FFMA R33, R69, R17, R32 ; FFMA R17, R21, R17, R16 ; FFMA R35, R69, R13.reuse, R34 ; FFMA R13, R21, R13, R12 ; FFMA R12, R70, R18.reuse, R33 ; FFMA R18, R22, R18, R17 ; FFMA R16, R70, R14, R35 ; FFMA R32, R68, R28, R67 ; FFMA R14, R22, R14, R13 ; FFMA R28, R20, R28, R65 ; FFMA R33, R69, R29, R32 ; LDS.128 R64, [R4+0x820] ; FFMA R83, R71, R19.reuse, R12 ; FFMA R81, R23, R19, R18 ; FFMA R79, R71, R15, R16 ; FFMA R29, R21, R29, R28 ; LDS.128 R16, [0x20] ; FFMA R77, R23, R15, R14 ; FFMA R28, R68, R24, R63 ; LDS.128 R12, [R4+0x8a0] ; FFMA R32, R70, R30.reuse, R33 ; FFMA R30, R22, R30, R29 ; FFMA R29, R69, R25, R28 ; FFMA R24, R20, R24, R61 ; FFMA R63, R71, R31.reuse, R32 ; FFMA R61, R23, R31, R30 ; LDS.128 R32, [0xa0] ; FFMA R58, R70, R26, R29 ; LDS.128 R28, [0x120] ; FFMA R25, R21, R25, R24 ; FFMA R24, R68, R8.reuse, R59 ; FFMA R8, R20, R8, R57 ; FFMA R26, R22, R26, R25 ; FFMA R25, R69, R9.reuse, R24 ; FFMA R9, R21, R9, R8 ; FFMA R8, R68, R40, R47 ; FFMA R24, R70, R10.reuse, R25 ; FFMA R10, R22, R10, R9 ; FFMA R40, R20, R40, R45 ; FFMA R9, R69, R41.reuse, R8 ; FFMA R41, R21, R41, R40 ; FFMA R47, R71, R11.reuse, R24 ; FFMA R45, R23, R11, R10 ; FFMA R40, R70, R42, R9 ; LDS.128 R8, [0x1a0] ; FFMA R59, R71, R27.reuse, R58 ; FFMA R57, R23, R27, R26 ; LDS.128 R24, [0x220] ; FFMA R20, R20, R36, R73 ; FFMA R68, R68, R36, R75 ; FFMA R21, R21, R37.reuse, R20 ; FFMA R69, R69, R37, R68 ; FFMA R42, R22, R42, R41 ; FFMA R6, R64, R16, R6 ; FFMA R16, R16, R12, R7 ; FFMA R22, R22, R38.reuse, R21 ; FFMA R70, R70, R38, R69 ; FFMA R7, R65, R17, R6 ; FFMA R17, R17, R13, R16 ; FFMA R75, R71, R43.reuse, R40 ; FFMA R73, R23, R43, R42 ; FFMA R69, R23, R39.reuse, R22 ; LDS.128 R40, [0x720] ; FFMA R71, R71, R39, R70 ; FFMA R6, R66, R18, R7 ; LDS.128 R20, [0x320] ; FFMA R18, R18, R14, R17 ; LDS.128 R36, [0x2a0] ; FFMA R56, R64.reuse, R32, R56 ; FFMA R52, R64, R28, R52 ; FFMA R6, R67, R19, R6 ; FFMA R7, R19, R15, R18 ; FFMA R17, R65.reuse, R33, R56 ; FFMA R19, R65, R29, R52 ; FFMA R54, R12, R32, R54 ; FFMA R56, R66.reuse, R34, R17 ; FFMA R52, R66, R30, R19 ; LDS.128 R16, [0x3a0] ; FFMA R33, R13, R33, R54 ; FFMA R50, R12, R28, R50 ; FFMA R54, R14, R34, R33 ; FFMA R29, R13, R29, R50 ; FFMA R56, R67, R35.reuse, R56 ; FFMA R54, R15, R35, R54 ; LDS.128 R32, [0x420] ; FFMA R48, R64, R8, R48 ; FFMA R50, R14, R30, R29 ; FFMA R46, R12, R8, R46 ; FFMA R44, R64, R24.reuse, R44 ; FFMA R24, R12, R24, R93 ; FFMA R29, R65, R9, R48 ; FFMA R52, R67, R31.reuse, R52 ; FFMA R50, R15, R31, R50 ; FFMA R9, R13, R9, R46 ; FFMA R31, R65, R25.reuse, R44 ; FFMA R25, R13, R25, R24 ; FFMA R48, R66, R10.reuse, R29 ; FFMA R46, R14, R10, R9 ; FFMA R44, R66, R26.reuse, R31 ; FFMA R26, R14, R26, R25 ; LDS.128 R28, [0x4a0] ; FFMA R48, R67, R11, R48 ; FFMA R46, R15.reuse, R11, R46 ; LDS.128 R8, [0x520] ; FFMA R93, R15, R27.reuse, R26 ; FFMA R26, R64.reuse, R20, R87 ; FFMA R24, R64, R36.reuse, R91 ; FFMA R44, R67, R27, R44 ; FFMA R36, R12, R36, R89 ; FFMA R20, R12, R20, R85 ; FFMA R27, R65.reuse, R21, R26 ; FFMA R25, R65, R37.reuse, R24 ; FFMA R37, R13.reuse, R37, R36 ; FFMA R21, R13, R21, R20 ; FFMA R36, R66, R22, R27 ; FFMA R20, R66, R38, R25 ; FFMA R22, R14, R22, R21 ; LDS.128 R24, [0x5a0] ; FFMA R87, R67, R23, R36 ; FFMA R36, R64, R16.reuse, R55 ; FFMA R16, R12, R16, R53 ; FFMA R38, R14, R38, R37 ; FFMA R91, R67, R39, R20 ; FFMA R85, R15, R23, R22 ; LDS.128 R20, [0x620] ; FFMA R37, R65, R17.reuse, R36 ; FFMA R17, R13, R17, R16 ; FFMA R16, R66, R18.reuse, R37 ; FFMA R18, R14, R18, R17 ; FFMA R89, R15, R39, R38 ; FFMA R38, R64, R32.reuse, R51 ; FFMA R32, R12, R32, R49 ; FFMA R55, R67, R19.reuse, R16 ; FFMA R53, R15, R19, R18 ; FFMA R39, R65, R33.reuse, R38 ; LDS.128 R16, [0x6a0] ; FFMA R33, R13, R33, R32 ; FFMA R32, R66, R34.reuse, R39 ; FFMA R34, R14, R34, R33 ; LDS.128 R36, [0x7a0] ; FFMA R51, R67, R35.reuse, R32 ; FFMA R49, R15, R35, R34 ; FFMA R34, R64.reuse, R8, R79 ; FFMA R32, R64, R28, R83 ; FFMA R28, R12.reuse, R28, R81 ; FFMA R35, R65.reuse, R9, R34 ; FFMA R8, R12, R8, R77 ; FFMA R33, R65, R29.reuse, R32 ; FFMA R29, R13, R29, R28 ; FFMA R28, R66, R10, R35 ; FFMA R9, R13, R9, R8 ; FFMA R79, R67, R11, R28 ; FFMA R8, R66, R30, R33 ; FFMA R10, R14, R10, R9 ; LDS.128 R32, [R4+0x8b0] ; FFMA R28, R64, R24.reuse, R63 ; FFMA R24, R12, R24, R61 ; FFMA R30, R14, R30, R29 ; LDS.128 R60, [R4+0x830] ; FFMA R29, R65, R25, R28 ; FFMA R83, R67, R31, R8 ; FFMA R77, R15, R11, R10 ; FFMA R25, R13, R25, R24 ; LDS.128 R8, [0x30] ; FFMA R24, R64, R20, R59 ; FFMA R28, R66, R26.reuse, R29 ; FFMA R26, R14, R26, R25 ; FFMA R25, R65, R21, R24 ; FFMA R20, R12, R20, R57 ; FFMA R81, R15, R31, R30 ; FFMA R59, R67, R27, R28 ; FFMA R57, R15, R27, R26 ; LDS.128 R28, [0xb0] ; FFMA R58, R66, R22, R25 ; FFMA R21, R13, R21, R20 ; LDS.128 R24, [0x130] ; FFMA R20, R64, R16.reuse, R47 ; FFMA R16, R12, R16, R45 ; FFMA R22, R14, R22, R21 ; FFMA R21, R65, R17.reuse, R20 ; FFMA R17, R13, R17, R16 ; FFMA R16, R64, R40, R75 ; FFMA R20, R66, R18.reuse, R21 ; FFMA R18, R14, R18, R17 ; FFMA R40, R12, R40, R73 ; FFMA R17, R65, R41.reuse, R16 ; FFMA R41, R13, R41, R40 ; FFMA R75, R67, R19.reuse, R20 ; FFMA R73, R15, R19, R18 ; FFMA R40, R66, R42, R17 ; LDS.128 R16, [0x1b0] ; FFMA R47, R67, R23, R58 ; FFMA R45, R15, R23, R22 ; LDS.128 R20, [0x230] ; FFMA R12, R12, R36.reuse, R69 ; FFMA R64, R64, R36, R71 ; FFMA R13, R13, R37.reuse, R12 ; FFMA R65, R65, R37, R64 ; FFMA R42, R14, R42, R41 ; FFMA R14, R14, R38.reuse, R13 ; FFMA R66, R66, R38, R65 ; FFMA R6, R60, R8, R6 ; FFMA R8, R8, R32, R7 ; FFMA R71, R67, R43.reuse, R40 ; FFMA R69, R15, R43, R42 ; FFMA R67, R67, R39.reuse, R66 ; LDS.128 R40, [0x730] ; FFMA R65, R15, R39, R14 ; FFMA R7, R61, R9, R6 ; LDS.128 R36, [0x2b0] ; FFMA R9, R9, R33, R8 ; LDS.128 R12, [0x330] ; FFMA R6, R62, R10, R7 ; FFMA R10, R10, R34, R9 ; FFMA R56, R60.reuse, R28, R56 ; FFMA R52, R60, R24, R52 ; FFMA R6, R63, R11, R6 ; FFMA R7, R11, R35, R10 ; FFMA R54, R32, R28, R54 ; FFMA R9, R61.reuse, R29, R56 ; FFMA R11, R61, R25, R52 ; FFMA R29, R33, R29, R54 ; FFMA R64, R62.reuse, R30, R9 ; FFMA R52, R62, R26, R11 ; LDS.128 R8, [0x3b0] ; FFMA R50, R32, R24, R50 ; FFMA R54, R34, R30, R29 ; FFMA R25, R33, R25, R50 ; FFMA R64, R63, R31.reuse, R64 ; FFMA R54, R35, R31, R54 ; LDS.128 R28, [0x430] ; FFMA R48, R60, R16, R48 ; FFMA R46, R32, R16, R46 ; FFMA R50, R34, R26, R25 ; FFMA R44, R60, R20.reuse, R44 ; FFMA R20, R32, R20, R93 ; FFMA R25, R61, R17.reuse, R48 ; FFMA R17, R33, R17, R46 ; FFMA R52, R63, R27.reuse, R52 ; FFMA R50, R35, R27, R50 ; FFMA R27, R61, R21.reuse, R44 ; FFMA R21, R33, R21, R20 ; FFMA R48, R62, R18.reuse, R25 ; FFMA R46, R34, R18, R17 ; FFMA R44, R62, R22.reuse, R27 ; FFMA R22, R34, R22, R21 ; LDS.128 R24, [0x4b0] ; FFMA R48, R63, R19.reuse, R48 ; FFMA R46, R35.reuse, R19, R46 ; LDS.128 R16, [0x530] ; FFMA R93, R35, R23, R22 ; FFMA R20, R60, R36, R91 ; FFMA R22, R60, R12.reuse, R87 ; FFMA R12, R32.reuse, R12, R85 ; FFMA R44, R63, R23, R44 ; FFMA R36, R32, R36, R89 ; FFMA R21, R61.reuse, R37, R20 ; FFMA R23, R61, R13, R22 ; FFMA R13, R33.reuse, R13, R12 ; FFMA R37, R33, R37, R36 ; FFMA R12, R62.reuse, R38, R21 ; FFMA R36, R62, R14.reuse, R23 ; FFMA R14, R34, R14, R13 ; LDS.128 R20, [0x5b0] ; FFMA R91, R63, R39, R12 ; FFMA R87, R63, R15.reuse, R36 ; FFMA R85, R35, R15, R14 ; FFMA R36, R60, R8.reuse, R55 ; LDS.128 R12, [0x630] ; FFMA R8, R32, R8, R53 ; FFMA R38, R34, R38, R37 ; FFMA R37, R61, R9, R36 ; FFMA R9, R33, R9, R8 ; FFMA R89, R35, R39, R38 ; FFMA R38, R60, R28.reuse, R51 ; FFMA R28, R32, R28, R49 ; FFMA R8, R62, R10.reuse, R37 ; FFMA R10, R34, R10, R9 ; FFMA R39, R61, R29.reuse, R38 ; FFMA R29, R33, R29, R28 ; FFMA R55, R63, R11.reuse, R8 ; FFMA R53, R35, R11, R10 ; FFMA R28, R62, R30.reuse, R39 ; LDS.128 R8, [0x6b0] ; FFMA R30, R34, R30, R29 ; FFMA R51, R63, R31.reuse, R28 ; LDS.128 R36, [0x7b0] ; FFMA R49, R35, R31, R30 ; FFMA R30, R60.reuse, R16, R79 ; FFMA R28, R60, R24.reuse, R83 ; FFMA R24, R32, R24, R81 ; FFMA R31, R61, R17, R30 ; FFMA R16, R32, R16, R77 ; FFMA R29, R61, R25.reuse, R28 ; FFMA R25, R33.reuse, R25, R24 ; FFMA R24, R62, R18, R31 ; FFMA R17, R33, R17, R16 ; FFMA R79, R63, R19, R24 ; FFMA R24, R60, R20, R59 ; FFMA R16, R62, R26, R29 ; FFMA R18, R34, R18, R17 ; LDS.128 R28, [0x40] ; FFMA R20, R32, R20, R57 ; FFMA R26, R34, R26, R25 ; LDS.128 R56, [R4+0x840] ; FFMA R25, R61, R21, R24 ; FFMA R21, R33, R21, R20 ; FFMA R83, R63, R27, R16 ; FFMA R77, R35, R19, R18 ; FFMA R20, R60, R12, R47 ; LDS.128 R16, [R4+0x8c0] ; FFMA R24, R62, R22.reuse, R25 ; FFMA R22, R34, R22, R21 ; FFMA R21, R61, R13, R20 ; FFMA R81, R35, R27, R26 ; FFMA R47, R63, R23.reuse, R24 ; FFMA R12, R32, R12, R45 ; LDS.128 R24, [0xc0] ; FFMA R45, R35, R23, R22 ; FFMA R66, R62, R14, R21 ; LDS.128 R20, [0x140] ; FFMA R13, R33, R13, R12 ; FFMA R12, R60, R8.reuse, R75 ; FFMA R8, R32, R8, R73 ; FFMA R14, R34, R14, R13 ; FFMA R13, R61, R9.reuse, R12 ; FFMA R9, R33, R9, R8 ; FFMA R8, R60, R40, R71 ; FFMA R12, R62, R10.reuse, R13 ; FFMA R10, R34, R10, R9 ; FFMA R40, R32, R40, R69 ; FFMA R9, R61, R41.reuse, R8 ; FFMA R41, R33, R41, R40 ; FFMA R71, R63, R11.reuse, R12 ; FFMA R69, R35, R11, R10 ; FFMA R40, R62, R42, R9 ; LDS.128 R8, [0x1c0] ; FFMA R75, R63, R15.reuse, R66 ; FFMA R73, R35, R15, R14 ; LDS.128 R12, [0x240] ; FFMA R32, R32, R36, R65 ; FFMA R60, R60, R36, R67 ; FFMA R33, R33, R37.reuse, R32 ; FFMA R61, R61, R37, R60 ; FFMA R42, R34, R42, R41 ; FFMA R6, R56, R28, R6 ; FFMA R28, R28, R16, R7 ; FFMA R34, R34, R38.reuse, R33 ; FFMA R62, R62, R38, R61 ; FFMA R7, R57, R29, R6 ; FFMA R29, R29, R17, R28 ; FFMA R67, R63, R43.reuse, R40 ; FFMA R65, R35, R43, R42 ; FFMA R61, R35, R39.reuse, R34 ; LDS.128 R40, [0x740] ; FFMA R63, R63, R39, R62 ; FFMA R6, R58, R30, R7 ; LDS.128 R32, [0x340] ; FFMA R64, R56, R24, R64 ; FFMA R30, R30, R18, R29 ; LDS.128 R36, [0x2c0] ; FFMA R54, R16, R24, R54 ; FFMA R52, R56, R20, R52 ; FFMA R29, R57, R25, R64 ; FFMA R6, R59, R31, R6 ; FFMA R7, R31, R19, R30 ; FFMA R25, R17, R25, R54 ; FFMA R31, R57, R21, R52 ; FFMA R64, R58, R26.reuse, R29 ; FFMA R62, R18, R26, R25 ; FFMA R60, R58, R22, R31 ; LDS.128 R28, [0x3c0] ; FFMA R64, R59, R27.reuse, R64 ; FFMA R62, R19, R27, R62 ; LDS.128 R24, [0x440] ; FFMA R50, R16, R20, R50 ; FFMA R21, R17, R21, R50 ; FFMA R48, R56, R8, R48 ; FFMA R54, R18, R22, R21 ; FFMA R46, R16, R8, R46 ; FFMA R44, R56, R12.reuse, R44 ; FFMA R12, R16, R12, R93 ; FFMA R21, R57, R9, R48 ; FFMA R60, R59, R23.reuse, R60 ; FFMA R54, R19, R23, R54 ; FFMA R9, R17, R9, R46 ; FFMA R23, R57, R13.reuse, R44 ; FFMA R13, R17, R13, R12 ; FFMA R52, R58, R10.reuse, R21 ; FFMA R50, R18, R10, R9 ; FFMA R48, R58, R14.reuse, R23 ; FFMA R14, R18, R14, R13 ; LDS.128 R20, [0x4c0] ; FFMA R52, R59, R11.reuse, R52 ; FFMA R50, R19, R11, R50 ; LDS.128 R8, [0x540] ; FFMA R93, R19, R15.reuse, R14 ; FFMA R14, R56.reuse, R32, R87 ; FFMA R12, R56, R36.reuse, R91 ; FFMA R36, R16.reuse, R36, R89 ; FFMA R48, R59, R15, R48 ; FFMA R32, R16, R32, R85 ; FFMA R15, R57.reuse, R33, R14 ; FFMA R13, R57, R37.reuse, R12 ; FFMA R37, R17.reuse, R37, R36 ; FFMA R33, R17, R33, R32 ; FFMA R36, R58.reuse, R34, R15 ; FFMA R32, R58, R38, R13 ; FFMA R38, R18, R38, R37 ; LDS.128 R12, [0x5c0] ; FFMA R87, R59, R35, R36 ; FFMA R36, R56, R28.reuse, R55 ; FFMA R89, R19, R39, R38 ; FFMA R28, R16, R28, R53 ; FFMA R38, R56, R24, R51 ; FFMA R34, R18, R34, R33 ; FFMA R24, R16, R24, R49 ; FFMA R37, R57, R29, R36 ; FFMA R91, R59, R39, R32 ; FFMA R29, R17, R29, R28 ; FFMA R39, R57, R25, R38 ; FFMA R25, R17, R25, R24 ; FFMA R85, R19, R35, R34 ; FFMA R24, R58, R30.reuse, R37 ; LDS.128 R32, [0x640] ; FFMA R30, R18, R30, R29 ; FFMA R51, R59, R31.reuse, R24 ; FFMA R49, R19, R31, R30 ; LDS.128 R28, [0x6c0] ; FFMA R36, R58, R26.reuse, R39 ; FFMA R26, R18, R26, R25 ; FFMA R24, R56.reuse, R20, R83 ; FFMA R53, R19, R27, R26 ; FFMA R26, R56, R8.reuse, R79 ; FFMA R8, R16, R8, R77 ; FFMA R55, R59, R27, R36 ; FFMA R20, R16, R20, R81 ; LDS.128 R36, [0x7c0] ; FFMA R27, R57.reuse, R9, R26 ; FFMA R25, R57, R21, R24 ; FFMA R9, R17.reuse, R9, R8 ; FFMA R21, R17, R21, R20 ; FFMA R20, R58.reuse, R10, R27 ; FFMA R8, R58, R22, R25 ; FFMA R10, R18, R10, R9 ; FFMA R24, R56, R12, R47 ; FFMA R83, R59.reuse, R23, R8 ; FFMA R79, R59, R11, R20 ; FFMA R77, R19, R11, R10 ; FFMA R12, R16, R12, R45 ; LDS.128 R8, [0x50] ; LDS.128 R44, [R4+0x850] ; FFMA R22, R18, R22, R21 ; FFMA R25, R57, R13, R24 ; FFMA R13, R17, R13, R12 ; FFMA R12, R56, R32.reuse, R75 ; FFMA R32, R16, R32, R73 ; FFMA R24, R58, R14.reuse, R25 ; FFMA R81, R19, R23, R22 ; FFMA R14, R18, R14, R13 ; LDS.128 R20, [R4+0x8d0] ; FFMA R13, R57, R33, R12 ; FFMA R33, R17, R33, R32 ; FFMA R32, R56, R28, R71 ; FFMA R66, R58, R34, R13 ; FFMA R28, R16, R28, R69 ; FFMA R75, R59, R15.reuse, R24 ; FFMA R73, R19, R15, R14 ; LDS.128 R24, [0x150] ; FFMA R34, R18, R34, R33 ; FFMA R33, R57, R29.reuse, R32 ; LDS.128 R12, [0xd0] ; FFMA R29, R17, R29, R28 ; FFMA R28, R56, R40, R67 ; FFMA R32, R58, R30.reuse, R33 ; FFMA R30, R18, R30, R29 ; FFMA R40, R16, R40, R65 ; FFMA R29, R57, R41, R28 ; FFMA R71, R59, R35.reuse, R66 ; FFMA R69, R19, R35, R34 ; FFMA R67, R59, R31, R32 ; LDS.128 R32, [0x1d0] ; FFMA R41, R17, R41, R40 ; FFMA R65, R19, R31, R30 ; FFMA R40, R58, R42, R29 ; LDS.128 R28, [0x250] ; FFMA R56, R56, R36.reuse, R63 ; FFMA R16, R16, R36, R61 ; FFMA R57, R57, R37.reuse, R56 ; FFMA R17, R17, R37, R16 ; FFMA R42, R18, R42, R41 ; FFMA R16, R44, R8, R6 ; FFMA R58, R58, R38.reuse, R57 ; FFMA R6, R18, R38, R17 ; FFMA R63, R59, R43.reuse, R40 ; FFMA R61, R19, R43, R42 ; FFMA R59, R59, R39.reuse, R58 ; LDS.128 R40, [0x350] ; FFMA R6, R19, R39, R6 ; LDS.128 R36, [0x2d0] ; FFMA R8, R8, R20, R7 ; FFMA R7, R45, R9, R16 ; FFMA R9, R9, R21, R8 ; LDS.128 R16, [0x3d0] ; FFMA R64, R44, R12, R64 ; FFMA R8, R46, R10, R7 ; FFMA R62, R20, R12, R62 ; FFMA R10, R10, R22, R9 ; FFMA R60, R44, R24.reuse, R60 ; FFMA R54, R20, R24, R54 ; FFMA R9, R45, R13, R64 ; FFMA R7, R47, R11, R8 ; FFMA R13, R21, R13, R62 ; FFMA R8, R11, R23, R10 ; FFMA R11, R45, R25.reuse, R60 ; FFMA R25, R21, R25, R54 ; FFMA R10, R46, R14.reuse, R9 ; FFMA R14, R22, R14, R13 ; FFMA R52, R44, R32, R52 ; FFMA R24, R46, R26, R11 ; FFMA R50, R20, R32, R50 ; FFMA R26, R22, R26, R25 ; FFMA R9, R47, R15.reuse, R10 ; FFMA R48, R44, R28, R48 ; FFMA R10, R23, R15, R14 ; FFMA R28, R20, R28, R93 ; LDS.128 R12, [0x450] ; FFMA R25, R45, R33.reuse, R52 ; FFMA R33, R21, R33, R50 ; FFMA R11, R47, R27.reuse, R24 ; FFMA R57, R23, R27, R26 ; FFMA R27, R45, R29, R48 ; FFMA R29, R21, R29, R28 ; FFMA R28, R46, R34.reuse, R25 ; FFMA R58, R22, R34, R33 ; FFMA R93, R47, R35.reuse, R28 ; FFMA R58, R23, R35, R58 ; FFMA R56, R46, R30.reuse, R27 ; LDS.128 R32, [0x550] ; FFMA R60, R22, R30, R29 ; LDS.128 R24, [0x4d0] ; FFMA R28, R44.reuse, R36, R91 ; FFMA R30, R44, R40, R87 ; FFMA R56, R47, R31.reuse, R56 ; FFMA R60, R23, R31, R60 ; FFMA R36, R20.reuse, R36, R89 ; FFMA R40, R20, R40, R85 ; FFMA R29, R45.reuse, R37, R28 ; FFMA R31, R45, R41, R30 ; FFMA R37, R21.reuse, R37, R36 ; FFMA R41, R21, R41, R40 ; FFMA R36, R46.reuse, R38, R29 ; FFMA R40, R46, R42, R31 ; LDS.128 R28, [0x5d0] ; FFMA R85, R47, R39, R36 ; FFMA R36, R44, R16.reuse, R51 ; FFMA R16, R20, R16, R49 ; LDS.128 R48, [0x650] ; FFMA R38, R22, R38, R37 ; FFMA R89, R23, R39, R38 ; FFMA R38, R44, R12.reuse, R55 ; FFMA R12, R20, R12, R53 ; FFMA R37, R45, R17.reuse, R36 ; LDS.128 R52, [0x6d0] ; FFMA R17, R21, R17, R16 ; FFMA R39, R45, R13, R38 ; FFMA R13, R21, R13, R12 ; FFMA R62, R46, R18.reuse, R37 ; FFMA R66, R22, R18, R17 ; FFMA R64, R46, R14.reuse, R39 ; FFMA R68, R22, R14, R13 ; LDS.128 R36, [R4+0x860] ; FFMA R18, R44, R32, R79 ; FFMA R16, R44, R24, R83 ; FFMA R62, R47, R19.reuse, R62 ; FFMA R66, R23, R19, R66 ; FFMA R32, R20, R32, R77 ; FFMA R64, R47, R15.reuse, R64 ; FFMA R68, R23, R15, R68 ; FFMA R19, R45.reuse, R33, R18 ; LDS.128 R12, [0x750] ; FFMA R24, R20, R24, R81 ; FFMA R17, R45, R25, R16 ; FFMA R33, R21.reuse, R33, R32 ; FFMA R32, R46, R34, R19 ; FFMA R25, R21, R25, R24 ; FFMA R24, R46, R26, R17 ; FFMA R42, R22, R42, R41 ; LDS.128 R16, [0x7d0] ; FFMA R79, R47.reuse, R35, R32 ; FFMA R32, R44, R28.reuse, R75 ; FFMA R28, R20, R28, R73 ; FFMA R87, R47, R43, R40 ; FFMA R91, R23, R43, R42 ; FFMA R26, R22.reuse, R26, R25 ; LDS.128 R40, [0x60] ; FFMA R34, R22, R34, R33 ; FFMA R33, R45, R29.reuse, R32 ; FFMA R29, R21, R29, R28 ; FFMA R28, R44, R48, R71 ; FFMA R77, R47, R27.reuse, R24 ; FFMA R81, R23, R27, R26 ; FFMA R32, R46, R30.reuse, R33 ; LDS.128 R24, [R4+0x8e0] ; FFMA R30, R22, R30, R29 ; FFMA R29, R45, R49, R28 ; FFMA R48, R20, R48, R69 ; FFMA R83, R23, R35, R34 ; FFMA R69, R47, R31.reuse, R32 ; LDS.128 R32, [0xe0] ; FFMA R71, R23, R31, R30 ; FFMA R70, R46, R50, R29 ; LDS.128 R28, [0x160] ; FFMA R49, R21, R49, R48 ; FFMA R48, R44, R52.reuse, R67 ; FFMA R52, R20, R52, R65 ; FFMA R50, R22, R50, R49 ; FFMA R49, R45, R53.reuse, R48 ; FFMA R53, R21, R53, R52 ; FFMA R48, R44, R12, R63 ; FFMA R67, R23, R51, R50 ; FFMA R50, R46, R54.reuse, R49 ; FFMA R54, R22, R54, R53 ; FFMA R12, R20, R12, R61 ; FFMA R49, R45, R13, R48 ; FFMA R44, R44, R16, R59 ; FFMA R6, R20, R16, R6 ; FFMA R13, R21, R13, R12 ; FFMA R61, R47, R55.reuse, R50 ; FFMA R63, R23, R55, R54 ; FFMA R65, R47, R51, R70 ; LDS.128 R52, [0x260] ; FFMA R12, R46, R14, R49 ; FFMA R45, R45, R17.reuse, R44 ; LDS.128 R48, [0x1e0] ; FFMA R17, R21, R17, R6 ; FFMA R6, R36, R40, R7 ; FFMA R14, R22, R14, R13 ; FFMA R46, R46, R18.reuse, R45 ; FFMA R18, R22, R18, R17 ; FFMA R13, R37, R41, R6 ; FFMA R8, R40, R24, R8 ; FFMA R59, R47, R15.reuse, R12 ; FFMA R73, R23, R15, R14 ; FFMA R41, R41, R25, R8 ; FFMA R7, R47, R19, R46 ; FFMA R75, R23, R19, R18 ; LDS.128 R44, [R4+0x870] ; FFMA R6, R38, R42, R13 ; FFMA R8, R36.reuse, R32, R9 ; LDS.128 R12, [0x2e0] ; FFMA R20, R36, R28, R11 ; LDS.128 R16, [0x360] ; FFMA R9, R37.reuse, R33, R8 ; FFMA R11, R37, R29, R20 ; FFMA R10, R24, R32, R10 ; FFMA R20, R38, R34, R9 ; FFMA R28, R24, R28, R57 ; FFMA R33, R25, R33, R10 ; FFMA R72, R38, R30, R11 ; FFMA R57, R39, R35, R20 ; LDS.128 R8, [0x3e0] ; LDS.128 R20, [0x460] ; FFMA R29, R25, R29, R28 ; FFMA R56, R36, R52, R56 ; FFMA R76, R26, R30, R29 ; FFMA R28, R36, R48, R93 ; FFMA R72, R39, R31.reuse, R72 ; FFMA R76, R27, R31, R76 ; FFMA R31, R37, R53, R56 ; FFMA R60, R24, R52, R60 ; FFMA R29, R37, R49, R28 ; FFMA R40, R38.reuse, R54, R31 ; FFMA R53, R25, R53, R60 ; FFMA R32, R38, R50, R29 ; FFMA R74, R26, R34, R33 ; LDS.128 R28, [0x4e0] ; FFMA R70, R42, R26, R41 ; FFMA R93, R39, R55, R40 ; FFMA R54, R26, R54, R53 ; FFMA R40, R36.reuse, R12, R85 ; FFMA R42, R36, R16, R87 ; FFMA R74, R27, R35, R74 ; FFMA R53, R39, R51, R32 ; FFMA R12, R24.reuse, R12, R89 ; LDS.128 R32, [0x560] ; FFMA R6, R39, R43, R6 ; FFMA R70, R43, R27, R70 ; FFMA R16, R24, R16, R91 ; FFMA R41, R37.reuse, R13, R40 ; FFMA R43, R37, R17, R42 ; FFMA R13, R25.reuse, R13, R12 ; FFMA R17, R25, R17, R16 ; FFMA R12, R38, R14.reuse, R41 ; FFMA R14, R26, R14, R13 ; FFMA R16, R38, R18.reuse, R43 ; LDS.128 R40, [0x5e0] ; FFMA R18, R26, R18, R17 ; FFMA R85, R39, R15.reuse, R12 ; FFMA R89, R27, R15, R14 ; FFMA R62, R36.reuse, R8, R62 ; LDS.128 R12, [0x660] ; FFMA R64, R36, R20, R64 ; FFMA R66, R24, R8, R66 ; FFMA R87, R39, R19, R16 ; FFMA R91, R27, R19, R18 ; FFMA R58, R24, R48, R58 ; FFMA R17, R37.reuse, R9, R62 ; FFMA R19, R37, R21, R64 ; FFMA R9, R25.reuse, R9, R66 ; FFMA R49, R25, R49, R58 ; FFMA R55, R27, R55, R54 ; FFMA R58, R38.reuse, R10, R17 ; FFMA R54, R38, R22, R19 ; FFMA R64, R26, R10, R9 ; LDS.128 R16, [0x6e0] ; FFMA R58, R39, R11.reuse, R58 ; FFMA R64, R27, R11, R64 ; LDS.128 R8, [0x760] ; FFMA R68, R24, R20, R68 ; FFMA R21, R25, R21, R68 ; FFMA R20, R36, R28, R77 ; FFMA R56, R26, R22, R21 ; FFMA R28, R24, R28, R81 ; FFMA R22, R36, R32, R79 ; FFMA R52, R26, R50, R49 ; FFMA R54, R39, R23.reuse, R54 ; FFMA R56, R27, R23, R56 ; FFMA R32, R24, R32, R83 ; FFMA R21, R37, R29.reuse, R20 ; FFMA R29, R25, R29, R28 ; FFMA R23, R37, R33, R22 ; FFMA R52, R27, R51, R52 ; FFMA R33, R25, R33, R32 ; LDS.128 R48, [0x7e0] ; FFMA R66, R38, R30.reuse, R21 ; FFMA R68, R26, R30, R29 ; FFMA R20, R38, R34, R23 ; FFMA R32, R36, R40, R69 ; FFMA R40, R24, R40, R71 ; FFMA R34, R26, R34, R33 ; FFMA R66, R39, R31.reuse, R66 ; FFMA R68, R27, R31, R68 ; FFMA R33, R37, R41, R32 ; LDS.128 R28, [0x70] ; FFMA R77, R39, R35, R20 ; FFMA R41, R25, R41, R40 ; LDS.128 R20, [R4+0x8f0] ; FFMA R32, R36, R12, R65 ; FFMA R40, R38, R42, R33 ; FFMA R12, R24, R12, R67 ; FFMA R42, R26, R42, R41 ; FFMA R79, R27, R35, R34 ; FFMA R41, R37, R13.reuse, R32 ; LDS.128 R32, [0xf0] ; FFMA R13, R25, R13, R12 ; FFMA R12, R36, R16.reuse, R61 ; FFMA R16, R24, R16, R63 ; FFMA R65, R39, R43.reuse, R40 ; LDS.128 R60, [0x570] ; FFMA R67, R27, R43, R42 ; FFMA R4, R38, R14.reuse, R41 ; FFMA R78, R26, R14, R13 ; LDS.128 R40, [0x170] ; FFMA R13, R37, R17.reuse, R12 ; FFMA R17, R25, R17, R16 ; FFMA R12, R36, R8, R59 ; FFMA R16, R38, R18, R13 ; FFMA R18, R26, R18, R17 ; FFMA R4, R39, R15.reuse, R4 ; FFMA R78, R27, R15, R78 ; FFMA R17, R37, R9, R12 ; LDS.128 R12, [0x1f0] ; FFMA R8, R24.reuse, R8, R73 ; FFMA R24, R24, R48, R75 ; FFMA R9, R25, R9, R8 ; FFMA R59, R39, R19.reuse, R16 ; FFMA R73, R27, R19, R18 ; FFMA R8, R38, R10.reuse, R17 ; FFMA R80, R26, R10, R9 ; LDS.128 R16, [0x270] ; FFMA R25, R25, R49, R24 ; FFMA R75, R39, R11.reuse, R8 ; FFMA R80, R27, R11, R80 ; FFMA R6, R44, R28, R6 ; LDS.128 R8, [0x2f0] ; FFMA R70, R28, R20, R70 ; FFMA R84, R26, R50, R25 ; FFMA R36, R36, R48, R7 ; FFMA R7, R45, R29, R6 ; FFMA R29, R29, R21, R70 ; FFMA R84, R27, R51, R84 ; FFMA R28, R44, R32.reuse, R57 ; LDS.128 R24, [0x370] ; FFMA R74, R20, R32, R74 ; FFMA R6, R46, R30, R7 ; FFMA R30, R30, R22, R29 ; FFMA R29, R45, R33.reuse, R28 ; FFMA R33, R21, R33, R74 ; FFMA R72, R44, R40, R72 ; FFMA R32, R46, R34.reuse, R29 ; FFMA R34, R22, R34, R33 ; FFMA R33, R45, R41, R72 ; FFMA R7, R47.reuse, R31, R6 ; FFMA R81, R47, R35.reuse, R32 ; FFMA R83, R23, R35, R34 ; FFMA R37, R37, R49, R36 ; FFMA R6, R31, R23, R30 ; FFMA R34, R46, R42, R33 ; LDS.128 R28, [0x3f0] ; FFMA R32, R44, R12, R53 ; FFMA R82, R38, R50, R37 ; FFMA R12, R20, R12, R52 ; FFMA R52, R47, R43, R34 ; FFMA R37, R45, R13, R32 ; LDS.128 R32, [0x470] ; FFMA R13, R21, R13, R12 ; FFMA R12, R44, R16, R93 ; FFMA R76, R20, R40, R76 ; FFMA R40, R46, R14.reuse, R37 ; FFMA R14, R22, R14, R13 ; FFMA R13, R45, R17, R12 ; FFMA R12, R44, R8.reuse, R85 ; FFMA R8, R20, R8, R89 ; FFMA R82, R39, R51, R82 ; FFMA R93, R23, R15, R14 ; LDS.128 R36, [0x4f0] ; FFMA R14, R46, R18, R13 ; FFMA R13, R45, R9.reuse, R12 ; LDS.128 R48, [0x5f0] ; FFMA R9, R21, R9, R8 ; FFMA R8, R44, R24.reuse, R87 ; FFMA R24, R20, R24, R91 ; FFMA R12, R46, R10.reuse, R13 ; FFMA R10, R22, R10, R9 ; FFMA R9, R45, R25.reuse, R8 ; FFMA R25, R21, R25, R24 ; FFMA R8, R46, R26.reuse, R9 ; FFMA R26, R22, R26, R25 ; FFMA R16, R20, R16, R55 ; FFMA R58, R44, R28, R58 ; FFMA R87, R47, R27.reuse, R8 ; FFMA R91, R23, R27, R26 ; LDS.128 R24, [0x670] ; FFMA R17, R21, R17, R16 ; FFMA R9, R45, R29, R58 ; FFMA R54, R44, R32, R54 ; FFMA R53, R47.reuse, R15, R40 ; FFMA R89, R47.reuse, R19, R14 ; FFMA R55, R47, R11, R12 ; FFMA R18, R22, R18, R17 ; LDS.128 R12, [0x6f0] ; FFMA R40, R46.reuse, R30, R9 ; FFMA R9, R45, R33, R54 ; FFMA R41, R21, R41, R76 ; FFMA R76, R23.reuse, R19, R18 ; FFMA R85, R23, R11, R10 ; LDS.128 R16, [0x770] ; FFMA R58, R46, R34, R9 ; LDS.128 R8, [0x7f0] ; FFMA R64, R20, R28, R64 ; FFMA R66, R44, R36, R66 ; FFMA R29, R21, R29, R64 ; FFMA R30, R22, R30, R29 ; FFMA R29, R45, R37, R66 ; FFMA R28, R46, R38, R29 ; FFMA R42, R22, R42, R41 ; FFMA R41, R47, R39, R28 ; FFMA R28, R44, R60, R77 ; FFMA R70, R23, R43, R42 ; FFMA R29, R45, R61, R28 ; FFMA R4, R44.reuse, R24, R4 ; FFMA R42, R23, R31, R30 ; FFMA R30, R44, R48, R65 ; FFMA R28, R46, R62, R29 ; FFMA R29, R45, R25, R4 ; FFMA R40, R47, R31, R40 ; FFMA R31, R45, R49, R30 ; FFMA R78, R20, R24, R78 ; IADD3 R3, R3, 0x1, RZ ; FFMA R24, R44, R12.reuse, R59 ; FFMA R12, R20, R12, R73 ; FFMA R4, R46.reuse, R26, R29 ; FFMA R30, R46, R50, R31 ; ISETP.GE.U32.AND P0, PT, R3, 0x10, PT ; FFMA R48, R20, R48, R67 ; FFMA R31, R45, R13.reuse, R24 ; FFMA R13, R21, R13, R12 ; FFMA R67, R47, R27, R4 ; FFMA R60, R20, R60, R79 ; FFMA R4, R44.reuse, R16, R75 ; FFMA R82, R44, R8, R82 ; FFMA R56, R20.reuse, R32, R56 ; FFMA R68, R20, R36, R68 ; FFMA R12, R46, R14, R31 ; FFMA R80, R20.reuse, R16, R80 ; FFMA R84, R20, R8, R84 ; FFMA R14, R22, R14, R13 ; FFMA R61, R21, R61, R60 ; FFMA R13, R45.reuse, R17, R4 ; FFMA R45, R45, R9, R82 ; FFMA R33, R21.reuse, R33, R56 ; FFMA R37, R21.reuse, R37, R68 ; FFMA R49, R21, R49, R48 ; FFMA R25, R21.reuse, R25, R78 ; FFMA R17, R21.reuse, R17, R80 ; FFMA R9, R21, R9, R84 ; FFMA R62, R22, R62, R61 ; FFMA R4, R46.reuse, R18, R13 ; FFMA R46, R46, R10, R45 ; FFMA R34, R22.reuse, R34, R33 ; FFMA R38, R22.reuse, R38, R37 ; FFMA R50, R22.reuse, R50, R49 ; FFMA R26, R22.reuse, R26, R25 ; FFMA R18, R22.reuse, R18, R17 ; FFMA R10, R22, R10, R9 ; FFMA R77, R47, R63.reuse, R28 ; FFMA R79, R23, R63, R62 ; FFMA R58, R47.reuse, R35, R58 ; FFMA R71, R47.reuse, R51, R30 ; FFMA R63, R47.reuse, R15, R12 ; FFMA R59, R47, R19, R4 ; FFMA R64, R23.reuse, R35, R34 ; FFMA R43, R23.reuse, R39, R38 ; FFMA R69, R23.reuse, R51, R50 ; FFMA R65, R23.reuse, R27, R26 ; FFMA R61, R23.reuse, R15, R14 ; FFMA R57, R23, R19, R18 ; FFMA R47, R47, R11.reuse, R46 ; FFMA R45, R23, R11, R10 ; @P0 CALL.REL.NOINC 0x5590 ; BRA 0x1c0 ; LEA R3, R5, R0, 0x5 ; SHF.L.U32 R3, R3, 0x1, RZ ; IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; STG.E [R2.64], R7 ; STG.E [R2.64+0x4], R6 ; STG.E [R2.64+0x10000], R81 ; STG.E [R2.64+0x10004], R83 ; STG.E [R2.64+0x20000], R52 ; STG.E [R2.64+0x20004], R70 ; STG.E [R2.64+0x30000], R53 ; STG.E [R2.64+0x30004], R93 ; STG.E [R2.64+0x40000], R89 ; STG.E [R2.64+0x40004], R76 ; STG.E [R2.64+0x50000], R55 ; STG.E [R2.64+0x50004], R85 ; STG.E [R2.64+0x60000], R87 ; STG.E [R2.64+0x60004], R91 ; STG.E [R2.64+0x70000], R40 ; STG.E [R2.64+0x70004], R42 ; STG.E [R2.64+0x80000], R58 ; STG.E [R2.64+0x80004], R64 ; STG.E [R2.64+0x90000], R41 ; STG.E [R2.64+0x90004], R43 ; STG.E [R2.64+0xa0000], R77 ; STG.E [R2.64+0xa0004], R79 ; STG.E [R2.64+0xb0000], R71 ; STG.E [R2.64+0xb0004], R69 ; STG.E [R2.64+0xc0000], R67 ; STG.E [R2.64+0xc0004], R65 ; STG.E [R2.64+0xd0000], R63 ; STG.E [R2.64+0xd0004], R61 ; STG.E [R2.64+0xe0000], R59 ; STG.E [R2.64+0xe0004], R57 ; STG.E [R2.64+0xf0000], R47 ; STG.E [R2.64+0xf0004], R45 ; EXIT ; BRA 0x57d0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0007616e_00000000-6_c6747d1af0928f8a2319b6168d703cd976b157b1.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z48__device_stub__Z24default_function_kernel0PvS_S_PvS_S_ .type _Z48__device_stub__Z24default_function_kernel0PvS_S_PvS_S_, @function _Z48__device_stub__Z24default_function_kernel0PvS_S_PvS_S_: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax movq %rdi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 96(%rsp) movq %rsi, 16(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) movq %rdx, 24(%rsp) leaq 24(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq default_function_kernel0(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z48__device_stub__Z24default_function_kernel0PvS_S_PvS_S_, .-_Z48__device_stub__Z24default_function_kernel0PvS_S_PvS_S_ .globl default_function_kernel0 .type default_function_kernel0, @function default_function_kernel0: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z48__device_stub__Z24default_function_kernel0PvS_S_PvS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size default_function_kernel0, .-default_function_kernel0 .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "default_function_kernel0" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq default_function_kernel0(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected default_function_kernel0 ; -- Begin function default_function_kernel0 .globl default_function_kernel0 .p2align 8 .type default_function_kernel0,@function default_function_kernel0: ; @default_function_kernel0 ; %bb.0: s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 v_dual_mov_b32 v1, 16 :: v_dual_mov_b32 v2, 0 s_mov_b32 s2, 0 .LBB0_1: ; %.preheader76 ; =>This Loop Header: Depth=1 ; Child Loop BB0_2 Depth 2 s_mov_b32 s3, 0 .LBB0_2: ; Parent Loop BB0_1 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_add_nc_u32_e32 v3, s3, v1 s_add_i32 s3, s3, 4 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u32 s3, 4 scratch_store_b32 v3, v2, off s_cbranch_scc0 .LBB0_2 ; %bb.3: ; in Loop: Header=BB0_1 Depth=1 v_add_nc_u32_e32 v1, 8, v1 s_add_i32 s2, s2, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s2, 16 s_cbranch_scc0 .LBB0_1 ; %bb.4: ; %.preheader75 s_waitcnt lgkmcnt(0) s_add_u32 s2, s4, 0x800 s_addc_u32 s3, s5, 0 s_add_u32 s8, s4, 0x1000 s_addc_u32 s9, s5, 0 s_add_u32 s10, s4, 0x1800 s_addc_u32 s11, s5, 0 s_add_u32 s12, s4, 0x2000 s_addc_u32 s13, s5, 0 s_add_u32 s14, s4, 0x2800 s_addc_u32 s16, s5, 0 s_add_u32 s17, s4, 0x3000 s_addc_u32 s18, s5, 0 s_add_u32 s19, s4, 0x3800 s_addc_u32 s20, s5, 0 s_add_u32 s21, s4, 0x4000 s_addc_u32 s22, s5, 0 s_add_u32 s23, s4, 0x4800 s_addc_u32 s24, s5, 0 s_add_u32 s25, s4, 0x5000 s_addc_u32 s26, s5, 0 s_add_u32 s27, s4, 0x5800 v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v5, 2, v0 s_addc_u32 s28, s5, 0 s_add_u32 s29, s4, 0x6000 s_addc_u32 s30, s5, 0 s_add_u32 s31, s4, 0x6800 s_addc_u32 s33, s5, 0 v_lshl_or_b32 v6, s15, 15, v0 v_or_b32_e32 v7, 0x2000, v5 v_add_nc_u32_e32 v8, 0x2080, v5 v_add_nc_u32_e32 v9, 0x80, v5 v_add_nc_u32_e32 v10, 0x2100, v5 v_add_nc_u32_e32 v11, 0x100, v5 v_add_nc_u32_e32 v12, 0x2180, v5 v_add_nc_u32_e32 v13, 0x180, v5 v_add_nc_u32_e32 v14, 0x2200, v5 v_add_nc_u32_e32 v15, 0x200, v5 v_add_nc_u32_e32 v16, 0x2280, v5 v_add_nc_u32_e32 v17, 0x280, v5 v_add_nc_u32_e32 v18, 0x2300, v5 v_add_nc_u32_e32 v19, 0x300, v5 v_add_nc_u32_e32 v20, 0x2380, v5 v_add_nc_u32_e32 v21, 0x380, v5 v_add_nc_u32_e32 v22, 0x2400, v5 v_add_nc_u32_e32 v23, 0x400, v5 v_add_nc_u32_e32 v24, 0x2480, v5 v_add_nc_u32_e32 v25, 0x480, v5 v_add_nc_u32_e32 v26, 0x2500, v5 v_add_nc_u32_e32 v27, 0x500, v5 v_add_nc_u32_e32 v28, 0x2580, v5 v_add_nc_u32_e32 v29, 0x580, v5 v_add_nc_u32_e32 v30, 0x2600, v5 v_add_nc_u32_e32 v31, 0x600, v5 v_add_nc_u32_e32 v32, 0x2680, v5 v_add_nc_u32_e32 v33, 0x680, v5 s_add_u32 s34, s4, 0x7000 v_add_nc_u32_e32 v34, 0x2700, v5 v_add_nc_u32_e32 v35, 0x700, v5 v_add_nc_u32_e32 v36, 0x2780, v5 v_add_nc_u32_e32 v37, 0x780, v5 v_add_nc_u32_e32 v38, 0x800, v5 v_add_nc_u32_e32 v39, 0x880, v5 v_add_nc_u32_e32 v40, 0x900, v5 v_add_nc_u32_e32 v41, 0x980, v5 v_add_nc_u32_e32 v42, 0xa00, v5 v_add_nc_u32_e32 v43, 0xa80, v5 v_add_nc_u32_e32 v44, 0xb00, v5 v_add_nc_u32_e32 v45, 0xb80, v5 v_add_nc_u32_e32 v46, 0xc00, v5 v_add_nc_u32_e32 v47, 0xc80, v5 v_add_nc_u32_e32 v48, 0xd00, v5 v_add_nc_u32_e32 v49, 0xd80, v5 v_add_nc_u32_e32 v50, 0xe00, v5 v_add_nc_u32_e32 v51, 0xe80, v5 v_add_nc_u32_e32 v52, 0xf00, v5 v_add_nc_u32_e32 v53, 0xf80, v5 v_or_b32_e32 v54, 0x1000, v5 v_add_nc_u32_e32 v55, 0x1080, v5 v_add_nc_u32_e32 v56, 0x1100, v5 v_add_nc_u32_e32 v57, 0x1180, v5 v_add_nc_u32_e32 v58, 0x1200, v5 v_add_nc_u32_e32 v59, 0x1280, v5 v_add_nc_u32_e32 v60, 0x1300, v5 v_add_nc_u32_e32 v61, 0x1380, v5 v_add_nc_u32_e32 v62, 0x1400, v5 v_add_nc_u32_e32 v63, 0x1480, v5 v_add_nc_u32_e32 v64, 0x1500, v5 v_add_nc_u32_e32 v65, 0x1580, v5 v_add_nc_u32_e32 v66, 0x1600, v5 v_add_nc_u32_e32 v67, 0x1680, v5 v_add_nc_u32_e32 v68, 0x1700, v5 v_add_nc_u32_e32 v69, 0x1780, v5 v_add_nc_u32_e32 v70, 0x1800, v5 v_add_nc_u32_e32 v71, 0x1880, v5 v_add_nc_u32_e32 v72, 0x1900, v5 v_add_nc_u32_e32 v73, 0x1980, v5 v_add_nc_u32_e32 v74, 0x1a00, v5 v_add_nc_u32_e32 v75, 0x1a80, v5 v_add_nc_u32_e32 v76, 0x1b00, v5 v_add_nc_u32_e32 v77, 0x1b80, v5 v_add_nc_u32_e32 v78, 0x1c00, v5 v_add_nc_u32_e32 v79, 0x1c80, v5 v_add_nc_u32_e32 v80, 0x1d00, v5 v_add_nc_u32_e32 v81, 0x1d80, v5 v_add_nc_u32_e32 v82, 0x1e00, v5 v_add_nc_u32_e32 v83, 0x1e80, v5 v_add_nc_u32_e32 v84, 0x1f00, v5 v_add_nc_u32_e32 v85, 0x1f80, v5 v_lshlrev_b32_e32 v86, 8, v0 s_addc_u32 s35, s5, 0 s_add_u32 s36, s4, 0x7800 s_addc_u32 s37, s5, 0 s_mov_b32 s38, 0 s_movk_i32 s40, 0x2000 s_movk_i32 s41, 0x2000 s_movk_i32 s42, 0x2000 s_movk_i32 s43, 0x2000 s_movk_i32 s44, 0x2400 s_movk_i32 s45, 0x2400 s_movk_i32 s46, 0x2400 s_movk_i32 s47, 0x2400 .LBB0_5: ; %.preheader74 ; =>This Loop Header: Depth=1 ; Child Loop BB0_6 Depth 2 s_lshl_b32 s39, s38, 5 s_waitcnt_vscnt null, 0x0 v_add_nc_u32_e32 v1, s39, v0 s_barrier buffer_gl0_inv v_lshlrev_b64 v[3:4], 2, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s5, v4, vcc_lo global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s2, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s3, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v7, v1 global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s8, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s9, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v8, v1 global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s10, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s11, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v10, v1 global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s12, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s13, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v12, v1 global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s14, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s16, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v14, v1 global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s17, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s18, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v16, v1 global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s19, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s20, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v18, v1 global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s21, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s22, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v20, v1 global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s23, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s24, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v22, v1 global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s25, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s26, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v24, v1 global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s27, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s28, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v26, v1 global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s29, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s30, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v28, v1 global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s31, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s33, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v30, v1 global_load_b32 v1, v[87:88], off v_add_co_u32 v87, vcc_lo, s34, v3 v_add_co_ci_u32_e32 v88, vcc_lo, s35, v4, vcc_lo v_add_co_u32 v3, vcc_lo, s36, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s37, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v32, v1 global_load_b32 v1, v[87:88], off s_waitcnt vmcnt(0) ds_store_b32 v34, v1 global_load_b32 v1, v[3:4], off v_add_nc_u32_e32 v3, s39, v6 s_mov_b32 s39, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[87:88], 2, v[3:4] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v36, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x200, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v5, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x400, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v9, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x600, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v11, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x800, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v13, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0xa00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v15, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0xc00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v17, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0xe00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v19, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x1000, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v21, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x1200, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v23, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x1400, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v25, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x1600, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v27, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x1800, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v29, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x1a00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v31, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x1c00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v33, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x1e00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v35, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x2000, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v37, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x2200, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v38, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x2400, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v39, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x2600, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v40, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x2800, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v41, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x2a00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v42, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x2c00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v43, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x2e00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v44, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x3000, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v45, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x3200, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v46, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x3400, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v47, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x3600, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v48, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x3800, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v49, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x3a00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v50, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x3c00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v51, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x3e00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v52, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x4000, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v53, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x4200, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v54, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x4400, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v55, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x4600, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v56, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x4800, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v57, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x4a00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v58, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x4c00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v59, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x4e00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v60, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x5000, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v61, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x5200, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v62, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x5400, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v63, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x5600, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v64, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x5800, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v65, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x5a00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v66, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x5c00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v67, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x5e00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v68, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x6000, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v69, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x6200, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v70, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x6400, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v71, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x6600, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v72, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x6800, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v73, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x6a00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v74, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x6c00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v75, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x6e00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v76, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x7000, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v77, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x7200, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v78, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x7400, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v79, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x7600, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v80, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x7800, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v81, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x7a00, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v88, 31, v87 v_lshlrev_b64 v[87:88], 2, v[87:88] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v82, v1 global_load_b32 v1, v[87:88], off v_add_nc_u32_e32 v87, 0x7c00, v3 v_add_nc_u32_e32 v3, 0x7e00, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v88, 31, v87 v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[87:88], 2, v[87:88] v_lshlrev_b64 v[3:4], 2, v[3:4] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v87, vcc_lo, s6, v87 v_add_co_ci_u32_e32 v88, vcc_lo, s7, v88, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v3, vcc_lo, s6, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo s_waitcnt vmcnt(0) ds_store_b32 v83, v1 global_load_b32 v1, v[87:88], off s_waitcnt vmcnt(0) ds_store_b32 v84, v1 global_load_b32 v1, v[3:4], off s_waitcnt vmcnt(0) ds_store_b32 v85, v1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_clause 0x1f scratch_load_b32 v115, off, off offset:16 scratch_load_b32 v114, off, off offset:20 scratch_load_b32 v113, off, off offset:24 scratch_load_b32 v112, off, off offset:28 scratch_load_b32 v111, off, off offset:32 scratch_load_b32 v110, off, off offset:36 scratch_load_b32 v109, off, off offset:40 scratch_load_b32 v108, off, off offset:44 scratch_load_b32 v107, off, off offset:48 scratch_load_b32 v106, off, off offset:52 scratch_load_b32 v105, off, off offset:56 scratch_load_b32 v104, off, off offset:60 scratch_load_b32 v103, off, off offset:64 scratch_load_b32 v102, off, off offset:68 scratch_load_b32 v101, off, off offset:72 scratch_load_b32 v100, off, off offset:76 scratch_load_b32 v99, off, off offset:80 scratch_load_b32 v98, off, off offset:84 scratch_load_b32 v97, off, off offset:88 scratch_load_b32 v96, off, off offset:92 scratch_load_b32 v95, off, off offset:96 scratch_load_b32 v94, off, off offset:100 scratch_load_b32 v93, off, off offset:104 scratch_load_b32 v92, off, off offset:108 scratch_load_b32 v91, off, off offset:112 scratch_load_b32 v90, off, off offset:116 scratch_load_b32 v89, off, off offset:120 scratch_load_b32 v88, off, off offset:124 scratch_load_b32 v87, off, off offset:128 scratch_load_b32 v4, off, off offset:132 scratch_load_b32 v3, off, off offset:136 scratch_load_b32 v1, off, off offset:140 .LBB0_6: ; %.preheader73 ; Parent Loop BB0_5 Depth=1 ; => This Inner Loop Header: Depth=2 v_dual_mov_b32 v116, s39 :: v_dual_add_nc_u32 v117, s39, v86 s_add_i32 s39, s39, 4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_cmpk_lg_i32 s39, 0x80 v_add_nc_u32_e32 v118, s40, v116 v_add_nc_u32_e32 v120, s41, v116 v_add_nc_u32_e32 v122, s42, v116 v_add_nc_u32_e32 v124, s43, v116 v_add_nc_u32_e32 v126, s44, v116 v_add_nc_u32_e32 v128, s45, v116 v_add_nc_u32_e32 v130, s46, v116 v_add_nc_u32_e32 v132, s47, v116 ds_load_2addr_b32 v[116:117], v117 offset1:32 ds_load_2addr_b32 v[118:119], v118 offset1:32 ds_load_2addr_b32 v[120:121], v120 offset0:64 offset1:96 ds_load_2addr_b32 v[122:123], v122 offset0:128 offset1:160 ds_load_2addr_b32 v[124:125], v124 offset0:192 offset1:224 ds_load_2addr_b32 v[126:127], v126 offset1:32 ds_load_2addr_b32 v[128:129], v128 offset0:64 offset1:96 ds_load_2addr_b32 v[130:131], v130 offset0:128 offset1:160 ds_load_2addr_b32 v[132:133], v132 offset0:192 offset1:224 s_waitcnt vmcnt(28) lgkmcnt(7) v_dual_fmac_f32 v115, v118, v116 :: v_dual_fmac_f32 v112, v119, v117 v_dual_fmac_f32 v114, v118, v117 :: v_dual_fmac_f32 v113, v119, v116 s_waitcnt vmcnt(24) lgkmcnt(6) v_dual_fmac_f32 v111, v120, v116 :: v_dual_fmac_f32 v108, v121, v117 v_dual_fmac_f32 v110, v120, v117 :: v_dual_fmac_f32 v109, v121, v116 s_waitcnt vmcnt(20) lgkmcnt(5) v_dual_fmac_f32 v107, v122, v116 :: v_dual_fmac_f32 v104, v123, v117 v_dual_fmac_f32 v106, v122, v117 :: v_dual_fmac_f32 v105, v123, v116 s_waitcnt vmcnt(16) lgkmcnt(4) v_dual_fmac_f32 v103, v124, v116 :: v_dual_fmac_f32 v100, v125, v117 v_dual_fmac_f32 v102, v124, v117 :: v_dual_fmac_f32 v101, v125, v116 s_waitcnt vmcnt(12) lgkmcnt(3) v_dual_fmac_f32 v99, v126, v116 :: v_dual_fmac_f32 v96, v127, v117 v_dual_fmac_f32 v98, v126, v117 :: v_dual_fmac_f32 v97, v127, v116 s_waitcnt vmcnt(8) lgkmcnt(2) v_dual_fmac_f32 v95, v128, v116 :: v_dual_fmac_f32 v92, v129, v117 v_dual_fmac_f32 v94, v128, v117 :: v_dual_fmac_f32 v93, v129, v116 s_waitcnt vmcnt(4) lgkmcnt(1) v_dual_fmac_f32 v91, v130, v116 :: v_dual_fmac_f32 v88, v131, v117 v_dual_fmac_f32 v90, v130, v117 :: v_dual_fmac_f32 v89, v131, v116 s_waitcnt vmcnt(3) lgkmcnt(0) v_fmac_f32_e32 v87, v132, v116 s_waitcnt vmcnt(1) v_dual_fmac_f32 v4, v132, v117 :: v_dual_fmac_f32 v3, v133, v116 s_waitcnt vmcnt(0) v_fmac_f32_e32 v1, v133, v117 s_cbranch_scc1 .LBB0_6 ; %bb.7: ; in Loop: Header=BB0_5 Depth=1 s_add_i32 s38, s38, 1 s_clause 0xf scratch_store_b32 off, v115, off offset:16 scratch_store_b32 off, v114, off offset:20 scratch_store_b32 off, v113, off offset:24 scratch_store_b32 off, v112, off offset:28 scratch_store_b32 off, v111, off offset:32 scratch_store_b32 off, v110, off offset:36 scratch_store_b32 off, v109, off offset:40 scratch_store_b32 off, v108, off offset:44 scratch_store_b32 off, v107, off offset:48 scratch_store_b32 off, v106, off offset:52 scratch_store_b32 off, v105, off offset:56 scratch_store_b32 off, v104, off offset:60 scratch_store_b32 off, v103, off offset:64 scratch_store_b32 off, v102, off offset:68 scratch_store_b32 off, v101, off offset:72 scratch_store_b32 off, v100, off offset:76 s_cmp_eq_u32 s38, 16 s_clause 0xf scratch_store_b32 off, v99, off offset:80 scratch_store_b32 off, v98, off offset:84 scratch_store_b32 off, v97, off offset:88 scratch_store_b32 off, v96, off offset:92 scratch_store_b32 off, v95, off offset:96 scratch_store_b32 off, v94, off offset:100 scratch_store_b32 off, v93, off offset:104 scratch_store_b32 off, v92, off offset:108 scratch_store_b32 off, v91, off offset:112 scratch_store_b32 off, v90, off offset:116 scratch_store_b32 off, v89, off offset:120 scratch_store_b32 off, v88, off offset:124 scratch_store_b32 off, v87, off offset:128 scratch_store_b32 off, v4, off offset:132 scratch_store_b32 off, v3, off offset:136 scratch_store_b32 off, v1, off offset:140 s_cbranch_scc0 .LBB0_5 ; %bb.8: ; %.preheader69 s_clause 0x1f scratch_load_b32 v1, off, off offset:16 scratch_load_b32 v2, off, off offset:20 scratch_load_b32 v3, off, off offset:24 scratch_load_b32 v4, off, off offset:28 scratch_load_b32 v5, off, off offset:32 scratch_load_b32 v6, off, off offset:36 scratch_load_b32 v7, off, off offset:40 scratch_load_b32 v8, off, off offset:44 scratch_load_b32 v9, off, off offset:48 scratch_load_b32 v10, off, off offset:52 scratch_load_b32 v11, off, off offset:56 scratch_load_b32 v12, off, off offset:60 scratch_load_b32 v13, off, off offset:64 scratch_load_b32 v14, off, off offset:68 scratch_load_b32 v79, off, off offset:72 scratch_load_b32 v80, off, off offset:76 scratch_load_b32 v81, off, off offset:80 scratch_load_b32 v82, off, off offset:84 scratch_load_b32 v83, off, off offset:88 scratch_load_b32 v84, off, off offset:92 scratch_load_b32 v85, off, off offset:96 scratch_load_b32 v86, off, off offset:100 scratch_load_b32 v87, off, off offset:104 scratch_load_b32 v88, off, off offset:108 scratch_load_b32 v89, off, off offset:112 scratch_load_b32 v90, off, off offset:116 scratch_load_b32 v91, off, off offset:120 scratch_load_b32 v92, off, off offset:124 scratch_load_b32 v93, off, off offset:128 scratch_load_b32 v94, off, off offset:132 scratch_load_b32 v95, off, off offset:136 scratch_load_b32 v96, off, off offset:140 s_lshl_b32 s2, s15, 6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshl_add_u32 v15, v0, 1, s2 v_or_b32_e32 v17, 1, v15 v_ashrrev_i32_e32 v16, 31, v15 v_add_nc_u32_e32 v19, 0x4000, v15 v_add_nc_u32_e32 v21, 0x4001, v15 v_add_nc_u32_e32 v23, 0x8000, v15 v_ashrrev_i32_e32 v18, 31, v17 v_add_nc_u32_e32 v25, 0x8001, v15 v_add_nc_u32_e32 v27, 0xc000, v15 v_add_nc_u32_e32 v29, 0xc001, v15 v_add_nc_u32_e32 v31, 0x10000, v15 v_add_nc_u32_e32 v33, 0x10001, v15 v_add_nc_u32_e32 v35, 0x14000, v15 v_add_nc_u32_e32 v37, 0x14001, v15 v_add_nc_u32_e32 v39, 0x18000, v15 v_add_nc_u32_e32 v41, 0x18001, v15 v_add_nc_u32_e32 v43, 0x1c000, v15 v_add_nc_u32_e32 v45, 0x1c001, v15 v_add_nc_u32_e32 v47, 0x20000, v15 v_add_nc_u32_e32 v49, 0x20001, v15 v_add_nc_u32_e32 v51, 0x24000, v15 v_add_nc_u32_e32 v53, 0x24001, v15 v_add_nc_u32_e32 v55, 0x28000, v15 v_add_nc_u32_e32 v57, 0x28001, v15 v_add_nc_u32_e32 v59, 0x2c000, v15 v_add_nc_u32_e32 v61, 0x2c001, v15 v_add_nc_u32_e32 v63, 0x30000, v15 v_add_nc_u32_e32 v65, 0x30001, v15 v_add_nc_u32_e32 v67, 0x34000, v15 v_add_nc_u32_e32 v69, 0x34001, v15 v_add_nc_u32_e32 v71, 0x38000, v15 v_add_nc_u32_e32 v73, 0x38001, v15 v_add_nc_u32_e32 v75, 0x3c000, v15 v_add_nc_u32_e32 v77, 0x3c001, v15 v_lshlrev_b64 v[15:16], 2, v[15:16] v_ashrrev_i32_e32 v20, 31, v19 v_lshlrev_b64 v[17:18], 2, v[17:18] v_ashrrev_i32_e32 v22, 31, v21 v_ashrrev_i32_e32 v24, 31, v23 v_ashrrev_i32_e32 v26, 31, v25 v_lshlrev_b64 v[19:20], 2, v[19:20] v_add_co_u32 v15, vcc_lo, s0, v15 v_add_co_ci_u32_e32 v16, vcc_lo, s1, v16, vcc_lo v_lshlrev_b64 v[21:22], 2, v[21:22] v_add_co_u32 v17, vcc_lo, s0, v17 v_add_co_ci_u32_e32 v18, vcc_lo, s1, v18, vcc_lo v_lshlrev_b64 v[23:24], 2, v[23:24] v_add_co_u32 v19, vcc_lo, s0, v19 v_ashrrev_i32_e32 v28, 31, v27 v_add_co_ci_u32_e32 v20, vcc_lo, s1, v20, vcc_lo v_lshlrev_b64 v[25:26], 2, v[25:26] v_add_co_u32 v21, vcc_lo, s0, v21 v_ashrrev_i32_e32 v30, 31, v29 v_add_co_ci_u32_e32 v22, vcc_lo, s1, v22, vcc_lo v_lshlrev_b64 v[27:28], 2, v[27:28] v_add_co_u32 v23, vcc_lo, s0, v23 v_ashrrev_i32_e32 v32, 31, v31 v_add_co_ci_u32_e32 v24, vcc_lo, s1, v24, vcc_lo v_lshlrev_b64 v[29:30], 2, v[29:30] v_add_co_u32 v25, vcc_lo, s0, v25 v_ashrrev_i32_e32 v34, 31, v33 v_add_co_ci_u32_e32 v26, vcc_lo, s1, v26, vcc_lo v_lshlrev_b64 v[31:32], 2, v[31:32] v_add_co_u32 v27, vcc_lo, s0, v27 v_ashrrev_i32_e32 v36, 31, v35 v_add_co_ci_u32_e32 v28, vcc_lo, s1, v28, vcc_lo v_lshlrev_b64 v[33:34], 2, v[33:34] v_add_co_u32 v29, vcc_lo, s0, v29 v_ashrrev_i32_e32 v38, 31, v37 v_add_co_ci_u32_e32 v30, vcc_lo, s1, v30, vcc_lo v_lshlrev_b64 v[35:36], 2, v[35:36] v_add_co_u32 v31, vcc_lo, s0, v31 v_ashrrev_i32_e32 v40, 31, v39 v_add_co_ci_u32_e32 v32, vcc_lo, s1, v32, vcc_lo v_lshlrev_b64 v[37:38], 2, v[37:38] v_add_co_u32 v33, vcc_lo, s0, v33 v_ashrrev_i32_e32 v42, 31, v41 v_add_co_ci_u32_e32 v34, vcc_lo, s1, v34, vcc_lo v_lshlrev_b64 v[39:40], 2, v[39:40] v_add_co_u32 v35, vcc_lo, s0, v35 v_ashrrev_i32_e32 v44, 31, v43 v_add_co_ci_u32_e32 v36, vcc_lo, s1, v36, vcc_lo v_lshlrev_b64 v[41:42], 2, v[41:42] v_add_co_u32 v37, vcc_lo, s0, v37 v_ashrrev_i32_e32 v46, 31, v45 v_add_co_ci_u32_e32 v38, vcc_lo, s1, v38, vcc_lo v_lshlrev_b64 v[43:44], 2, v[43:44] v_add_co_u32 v39, vcc_lo, s0, v39 v_ashrrev_i32_e32 v48, 31, v47 v_add_co_ci_u32_e32 v40, vcc_lo, s1, v40, vcc_lo v_lshlrev_b64 v[45:46], 2, v[45:46] v_add_co_u32 v41, vcc_lo, s0, v41 v_ashrrev_i32_e32 v50, 31, v49 v_add_co_ci_u32_e32 v42, vcc_lo, s1, v42, vcc_lo v_lshlrev_b64 v[47:48], 2, v[47:48] v_add_co_u32 v43, vcc_lo, s0, v43 v_ashrrev_i32_e32 v52, 31, v51 v_add_co_ci_u32_e32 v44, vcc_lo, s1, v44, vcc_lo v_lshlrev_b64 v[49:50], 2, v[49:50] v_add_co_u32 v45, vcc_lo, s0, v45 v_ashrrev_i32_e32 v54, 31, v53 v_add_co_ci_u32_e32 v46, vcc_lo, s1, v46, vcc_lo v_lshlrev_b64 v[51:52], 2, v[51:52] v_add_co_u32 v47, vcc_lo, s0, v47 v_ashrrev_i32_e32 v56, 31, v55 v_add_co_ci_u32_e32 v48, vcc_lo, s1, v48, vcc_lo v_lshlrev_b64 v[53:54], 2, v[53:54] v_add_co_u32 v49, vcc_lo, s0, v49 v_ashrrev_i32_e32 v58, 31, v57 v_add_co_ci_u32_e32 v50, vcc_lo, s1, v50, vcc_lo v_lshlrev_b64 v[55:56], 2, v[55:56] v_add_co_u32 v51, vcc_lo, s0, v51 v_ashrrev_i32_e32 v60, 31, v59 v_add_co_ci_u32_e32 v52, vcc_lo, s1, v52, vcc_lo v_lshlrev_b64 v[57:58], 2, v[57:58] v_add_co_u32 v53, vcc_lo, s0, v53 v_ashrrev_i32_e32 v62, 31, v61 v_add_co_ci_u32_e32 v54, vcc_lo, s1, v54, vcc_lo v_lshlrev_b64 v[59:60], 2, v[59:60] v_add_co_u32 v55, vcc_lo, s0, v55 v_ashrrev_i32_e32 v64, 31, v63 v_add_co_ci_u32_e32 v56, vcc_lo, s1, v56, vcc_lo v_lshlrev_b64 v[61:62], 2, v[61:62] v_add_co_u32 v57, vcc_lo, s0, v57 v_ashrrev_i32_e32 v66, 31, v65 v_add_co_ci_u32_e32 v58, vcc_lo, s1, v58, vcc_lo v_lshlrev_b64 v[63:64], 2, v[63:64] v_add_co_u32 v59, vcc_lo, s0, v59 v_ashrrev_i32_e32 v68, 31, v67 v_add_co_ci_u32_e32 v60, vcc_lo, s1, v60, vcc_lo v_lshlrev_b64 v[65:66], 2, v[65:66] v_add_co_u32 v61, vcc_lo, s0, v61 v_ashrrev_i32_e32 v70, 31, v69 v_add_co_ci_u32_e32 v62, vcc_lo, s1, v62, vcc_lo v_lshlrev_b64 v[67:68], 2, v[67:68] v_add_co_u32 v63, vcc_lo, s0, v63 v_ashrrev_i32_e32 v72, 31, v71 v_add_co_ci_u32_e32 v64, vcc_lo, s1, v64, vcc_lo v_lshlrev_b64 v[69:70], 2, v[69:70] v_add_co_u32 v65, vcc_lo, s0, v65 v_ashrrev_i32_e32 v74, 31, v73 v_add_co_ci_u32_e32 v66, vcc_lo, s1, v66, vcc_lo v_lshlrev_b64 v[71:72], 2, v[71:72] v_add_co_u32 v67, vcc_lo, s0, v67 v_ashrrev_i32_e32 v76, 31, v75 v_add_co_ci_u32_e32 v68, vcc_lo, s1, v68, vcc_lo v_lshlrev_b64 v[73:74], 2, v[73:74] v_add_co_u32 v69, vcc_lo, s0, v69 v_ashrrev_i32_e32 v78, 31, v77 v_add_co_ci_u32_e32 v70, vcc_lo, s1, v70, vcc_lo v_lshlrev_b64 v[75:76], 2, v[75:76] v_add_co_u32 v71, vcc_lo, s0, v71 v_add_co_ci_u32_e32 v72, vcc_lo, s1, v72, vcc_lo v_lshlrev_b64 v[77:78], 2, v[77:78] v_add_co_u32 v73, vcc_lo, s0, v73 v_add_co_ci_u32_e32 v74, vcc_lo, s1, v74, vcc_lo v_add_co_u32 v75, vcc_lo, s0, v75 v_add_co_ci_u32_e32 v76, vcc_lo, s1, v76, vcc_lo v_add_co_u32 v77, vcc_lo, s0, v77 v_add_co_ci_u32_e32 v78, vcc_lo, s1, v78, vcc_lo s_waitcnt vmcnt(31) global_store_b32 v[15:16], v1, off s_waitcnt vmcnt(30) global_store_b32 v[17:18], v2, off s_waitcnt vmcnt(29) global_store_b32 v[19:20], v3, off s_waitcnt vmcnt(28) global_store_b32 v[21:22], v4, off s_waitcnt vmcnt(27) global_store_b32 v[23:24], v5, off s_waitcnt vmcnt(26) global_store_b32 v[25:26], v6, off s_waitcnt vmcnt(25) global_store_b32 v[27:28], v7, off s_waitcnt vmcnt(24) global_store_b32 v[29:30], v8, off s_waitcnt vmcnt(23) global_store_b32 v[31:32], v9, off s_waitcnt vmcnt(22) global_store_b32 v[33:34], v10, off s_waitcnt vmcnt(21) global_store_b32 v[35:36], v11, off s_waitcnt vmcnt(20) global_store_b32 v[37:38], v12, off s_waitcnt vmcnt(19) global_store_b32 v[39:40], v13, off s_waitcnt vmcnt(18) global_store_b32 v[41:42], v14, off s_waitcnt vmcnt(17) global_store_b32 v[43:44], v79, off s_waitcnt vmcnt(16) global_store_b32 v[45:46], v80, off s_waitcnt vmcnt(15) global_store_b32 v[47:48], v81, off s_waitcnt vmcnt(14) global_store_b32 v[49:50], v82, off s_waitcnt vmcnt(13) global_store_b32 v[51:52], v83, off s_waitcnt vmcnt(12) global_store_b32 v[53:54], v84, off s_waitcnt vmcnt(11) global_store_b32 v[55:56], v85, off s_waitcnt vmcnt(10) global_store_b32 v[57:58], v86, off s_waitcnt vmcnt(9) global_store_b32 v[59:60], v87, off s_waitcnt vmcnt(8) global_store_b32 v[61:62], v88, off s_waitcnt vmcnt(7) global_store_b32 v[63:64], v89, off s_waitcnt vmcnt(6) global_store_b32 v[65:66], v90, off s_waitcnt vmcnt(5) global_store_b32 v[67:68], v91, off s_waitcnt vmcnt(4) global_store_b32 v[69:70], v92, off s_waitcnt vmcnt(3) global_store_b32 v[71:72], v93, off s_waitcnt vmcnt(2) global_store_b32 v[73:74], v94, off s_waitcnt vmcnt(1) global_store_b32 v[75:76], v95, off s_waitcnt vmcnt(0) global_store_b32 v[77:78], v96, off s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel default_function_kernel0 .amdhsa_group_segment_fixed_size 10240 .amdhsa_private_segment_fixed_size 144 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 1 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 134 .amdhsa_next_free_sgpr 48 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size default_function_kernel0, .Lfunc_end0-default_function_kernel0 ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 7872 ; NumSgprs: 50 ; NumVgprs: 134 ; ScratchSize: 144 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 10240 bytes/workgroup (compile time only) ; SGPRBlocks: 6 ; VGPRBlocks: 16 ; NumSGPRsForWavesPerEU: 50 ; NumVGPRsForWavesPerEU: 134 ; Occupancy: 10 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .actual_access: read_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 10240 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: default_function_kernel0 .private_segment_fixed_size: 144 .sgpr_count: 50 .sgpr_spill_count: 0 .symbol: default_function_kernel0.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 134 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "c6747d1af0928f8a2319b6168d703cd976b157b1.hip" .globl __device_stub__default_function_kernel0 # -- Begin function __device_stub__default_function_kernel0 .p2align 4, 0x90 .type __device_stub__default_function_kernel0,@function __device_stub__default_function_kernel0: # @__device_stub__default_function_kernel0 .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $default_function_kernel0, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size __device_stub__default_function_kernel0, .Lfunc_end0-__device_stub__default_function_kernel0 .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $default_function_kernel0, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type default_function_kernel0,@object # @default_function_kernel0 .section .rodata,"a",@progbits .globl default_function_kernel0 .p2align 3, 0x0 default_function_kernel0: .quad __device_stub__default_function_kernel0 .size default_function_kernel0, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "default_function_kernel0" .size .L__unnamed_1, 25 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __device_stub__default_function_kernel0 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym default_function_kernel0 .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
31,878
1,842
29,022
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code for sm_80 Function : _Z22gpu_square_matrix_multPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_CTAID.Y ; ISETP.NE.AND P0, PT, RZ, c[0x0][0xc], PT ; ULDC.64 UR6, c[0x0][0x118] ; HFMA2.MMA R9, -RZ, RZ, 0, 0 ; S2R R16, SR_TID.Y ; S2R R0, SR_CTAID.X ; S2R R17, SR_TID.X ; LEA R18, R3, R16, 0x3 ; LEA R21, R0, R17, 0x3 ; @!P0 BRA 0x860 ; IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0xc] ; ULDC UR4, c[0x0][0x178] ; SHF.L.U32 R22, R16, 0x5, RZ ; UIMAD UR4, UR4, UR4, URZ ; IMAD R20, R18, c[0x0][0x178], R17 ; ISETP.NE.AND P0, PT, R23, 0x1, PT ; MOV R19, RZ ; IMAD R24, R17, 0x4, R22 ; MOV R9, RZ ; LOP3.LUT R23, R23, 0x1, RZ, 0xc0, !PT ; @!P0 BRA 0x610 ; HFMA2.MMA R19, -RZ, RZ, 0, 0 ; IADD3 R25, -R23, c[0x0][0xc], RZ ; MOV R9, RZ ; LEA R0, R19.reuse, R16, 0x3 ; IMAD.MOV.U32 R12, RZ, RZ, 0x4 ; LEA R3, R19, R20, 0x3 ; MOV R15, RZ ; IMAD R11, R0, c[0x0][0x178], R21 ; ISETP.GE.AND P0, PT, R3.reuse, UR4, PT ; IMAD.WIDE R2, R3, R12, c[0x0][0x160] ; MOV R13, RZ ; ISETP.GE.AND P1, PT, R11, UR4, PT ; @!P0 LDG.E R13, [R2.64] ; @!P1 IMAD.WIDE R10, R11, R12, c[0x0][0x168] ; @!P1 LDG.E R15, [R10.64] ; LEA R27, R19, 0x8, 0x3 ; IADD3 R26, R27, R16, RZ ; IMAD.MOV.U32 R28, RZ, RZ, RZ ; STS [R24], R13 ; STS [R24+0x100], R15 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDS R0, [R17.X4+0x100] ; LDS.128 R4, [R22] ; LDS R8, [R17.X4+0x120] ; LDS R14, [R17.X4+0x140] ; IMAD R13, R26, c[0x0][0x178], R21 ; LDS R26, [R17.X4+0x1a0] ; ISETP.GE.AND P1, PT, R13, UR4, PT ; IMAD R0, R0, R4, R9 ; IADD3 R4, R20, R27, RZ ; LDS R27, [R17.X4+0x1c0] ; IMAD R5, R8, R5, R0 ; ISETP.GE.AND P0, PT, R4, UR4, PT ; LDS R0, [R17.X4+0x160] ; IMAD R6, R14, R6, R5 ; LDS R5, [R17.X4+0x180] ; LDS R4, [R17.X4+0x1e0] ; LDS.128 R8, [R22+0x10] ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P0 LDG.E R28, [R2.64+0x20] ; @!P1 IMAD.WIDE R2, R13, R12, c[0x0][0x168] ; MOV R13, RZ ; @!P1 LDG.E R13, [R2.64] ; IMAD R0, R0, R7, R6 ; IMAD R5, R5, R8, R0 ; IMAD R5, R26, R9, R5 ; IMAD R5, R27, R10, R5 ; IMAD R10, R4, R11, R5 ; IADD3 R25, R25, -0x2, RZ ; ISETP.NE.AND P0, PT, R25, RZ, PT ; IADD3 R19, R19, 0x2, RZ ; STS [R24], R28 ; STS [R24+0x100], R13 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDS R29, [R17.X4+0x100] ; LDS.128 R12, [R22] ; LDS R0, [R17.X4+0x120] ; LDS R9, [R17.X4+0x140] ; LDS R2, [R17.X4+0x160] ; LDS R11, [R17.X4+0x180] ; LDS.128 R4, [R22+0x10] ; LDS R8, [R17.X4+0x1a0] ; LDS R3, [R17.X4+0x1c0] ; IMAD R12, R29, R12, R10 ; LDS R10, [R17.X4+0x1e0] ; IMAD R0, R0, R13, R12 ; IMAD R0, R9, R14, R0 ; IMAD R0, R2, R15, R0 ; IMAD R0, R11, R4, R0 ; IMAD R0, R8, R5, R0 ; IMAD R0, R3, R6, R0 ; IMAD R9, R10, R7, R0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P0 BRA 0x190 ; SHF.L.U32 R19, R19, 0x3, RZ ; ISETP.NE.AND P0, PT, R23, RZ, PT ; @!P0 BRA 0x860 ; IADD3 R16, R16, R19.reuse, RZ ; HFMA2.MMA R23, -RZ, RZ, 0, 0 ; IADD3 R2, R20, R19, RZ ; MOV R19, RZ ; IMAD R16, R16, c[0x0][0x178], R21 ; ISETP.GE.AND P0, PT, R2, UR4, PT ; ISETP.GE.AND P1, PT, R16, UR4, PT ; @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; @!P1 MOV R11, 0x4 ; @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; @!P1 IMAD.WIDE R10, R16, R11, c[0x0][0x168] ; @!P0 LDG.E R23, [R2.64] ; @!P1 LDG.E R19, [R10.64] ; STS [R24], R23 ; STS [R24+0x100], R19 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDS R0, [R17.X4+0x100] ; LDS.128 R4, [R22] ; LDS R8, [R17.X4+0x120] ; LDS R16, [R17.X4+0x140] ; LDS R20, [R17.X4+0x160] ; LDS R25, [R17.X4+0x180] ; LDS.128 R12, [R22+0x10] ; LDS R2, [R17.X4+0x1a0] ; LDS R3, [R17.X4+0x1c0] ; LDS R10, [R17.X4+0x1e0] ; IMAD R0, R0, R4, R9 ; IMAD R5, R8, R5, R0 ; IMAD R6, R16, R6, R5 ; IMAD R7, R20, R7, R6 ; IMAD R12, R25, R12, R7 ; IMAD R13, R2, R13, R12 ; IMAD R14, R3, R14, R13 ; IMAD R9, R10, R15, R14 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P0, PT, R21, c[0x0][0x178], PT ; ISETP.GE.OR P0, PT, R18, c[0x0][0x178], P0 ; @P0 EXIT ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD R2, R18, c[0x0][0x178], R21 ; IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; STG.E [R2.64], R9 ; EXIT ; BRA 0x8e0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000a86d9_00000000-6_53f84f5b1c344dc08a1189273b1cc3e7fcdee1c2.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z15cpu_matrix_multPiS_S_iii .type _Z15cpu_matrix_multPiS_S_iii, @function _Z15cpu_matrix_multPiS_S_iii: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 movq %rsi, -16(%rsp) movq %rdx, -8(%rsp) movl %ecx, -20(%rsp) testl %ecx, %ecx jle .L3 movl %r8d, %r11d movl %r9d, %edx movslq %r9d, %r12 leaq 0(,%r12,4), %r8 movl $0, %r13d movl $0, %ecx movl $0, %eax movslq %r11d, %r15 movq %rdi, %rsi movq %r15, %rdi jmp .L5 .L6: movl (%rax), %ecx imull (%r9), %ecx addl %ecx, %r13d addq $4, %rax addq %r8, %r9 cmpq %r10, %rax jne .L6 .L8: movl %r13d, (%r14,%rbx,4) addq $1, %rbx addq $4, %rbp cmpq %rbx, %r12 je .L13 .L9: movq %rbp, %r9 movq %r15, %rax movl $0, %r13d testl %r11d, %r11d jg .L6 jmp .L8 .L13: movl -32(%rsp), %eax movl -28(%rsp), %ecx movl -24(%rsp), %r13d .L7: addl $1, %eax addl %edx, %ecx addl %r11d, %r13d cmpl %eax, -20(%rsp) je .L3 .L5: testl %edx, %edx jle .L7 movq -16(%rsp), %rbp movslq %r13d, %r9 leaq (%rsi,%r9,4), %r15 addq %rdi, %r9 leaq (%rsi,%r9,4), %r10 movslq %ecx, %r9 movq -8(%rsp), %rbx leaq (%rbx,%r9,4), %r14 movl $0, %ebx movl %eax, -32(%rsp) movl %ecx, -28(%rsp) movl %r13d, -24(%rsp) jmp .L9 .L3: popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z15cpu_matrix_multPiS_S_iii, .-_Z15cpu_matrix_multPiS_S_iii .globl _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i .type _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i, @function _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i: .LFB2083: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L20 .L16: movq 136(%rsp), %rax subq %fs:40, %rax jne .L21 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L20: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z22gpu_square_matrix_multPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L16 .L21: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i, .-_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i .globl _Z22gpu_square_matrix_multPiS_S_i .type _Z22gpu_square_matrix_multPiS_S_i, @function _Z22gpu_square_matrix_multPiS_S_i: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z22gpu_square_matrix_multPiS_S_i, .-_Z22gpu_square_matrix_multPiS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%d\t%d\t%f\n" .LC1: .string "incorrect results\n" .text .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $168, %rsp .cfi_def_cfa_offset 224 movq %rsi, %rbx movq %rsi, 32(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax movl $3333, %edi call srand@PLT movq 8(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %r15 movq %rax, 24(%rsp) movl %eax, %r13d cltq movq %rax, %r14 movq %rax, 40(%rsp) imulq %rax, %rax leaq 0(,%rax,4), %rbx movq %rbx, 16(%rsp) leaq 56(%rsp), %rdi movq %rbx, %rsi call cudaMallocHost@PLT leaq 64(%rsp), %rdi movq %rbx, %rsi call cudaMallocHost@PLT leaq 72(%rsp), %rdi movq %rbx, %rsi call cudaMallocHost@PLT leaq 80(%rsp), %rdi movq %rbx, %rsi call cudaMallocHost@PLT testl %r15d, %r15d jle .L25 leaq 0(,%r14,4), %r15 leal -1(%r13), %eax leaq 4(,%rax,4), %rbp movq %rbp, %r12 movl $0, %r14d notq %rax salq $2, %rax movq %rax, 8(%rsp) .L26: movq 8(%rsp), %rax leaq (%rax,%r12), %rbx .L27: call rand@PLT cltd shrl $22, %edx addl %edx, %eax andl $1023, %eax subl %edx, %eax movq 56(%rsp), %rdx movl %eax, (%rdx,%rbx) addq $4, %rbx cmpq %r12, %rbx jne .L27 addl $1, %r14d addq %r15, %r12 cmpl %r13d, %r14d jne .L26 movl $0, %r12d .L28: movq 8(%rsp), %rax leaq (%rax,%rbp), %rbx .L29: call rand@PLT cltd shrl $22, %edx addl %edx, %eax andl $1023, %eax subl %edx, %eax movq 64(%rsp), %rdx movl %eax, (%rdx,%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L29 addl $1, %r12d addq %r15, %rbp cmpl %r13d, %r12d jne .L28 .L25: leaq 88(%rsp), %rdi call cudaEventCreate@PLT leaq 96(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 88(%rsp), %rdi call cudaEventRecord@PLT leaq 104(%rsp), %rdi movq 16(%rsp), %rbx movq %rbx, %rsi call cudaMalloc@PLT leaq 112(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 120(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movl $1, %ecx movq %rbx, %rdx movq 56(%rsp), %rsi movq 104(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq 64(%rsp), %rsi movq 112(%rsp), %rdi call cudaMemcpy@PLT movq 24(%rsp), %rcx movl %ecx, %eax addl $14, %eax movl %ecx, %edx addl $7, %edx cmovns %edx, %eax sarl $3, %eax movl %eax, 128(%rsp) movl %eax, 132(%rsp) movl $1, 136(%rsp) movq 32(%rsp), %r15 movq 16(%r15), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %rbx movq 16(%r15), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT sall $3, %eax movl %eax, 140(%rsp) sall $3, %ebx movl %ebx, 144(%rsp) movl $1, 148(%rsp) movl $0, %r9d movl $0, %r8d movq 140(%rsp), %rdx movl $1, %ecx movq 128(%rsp), %rdi movl 136(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L45 .L30: movl $2, %ecx movq 16(%rsp), %rdx movq 120(%rsp), %rsi movq 72(%rsp), %rdi call cudaMemcpy@PLT call cudaThreadSynchronize@PLT movl $0, %esi movq 96(%rsp), %rdi call cudaEventRecord@PLT movq 96(%rsp), %rdi call cudaEventSynchronize@PLT leaq 48(%rsp), %rdi movq 96(%rsp), %rdx movq 88(%rsp), %rsi call cudaEventElapsedTime@PLT movl $0, %esi movq 88(%rsp), %rdi call cudaEventRecord@PLT movq 24(%rsp), %rbx movl %ebx, %r9d movl %ebx, %r8d movl %r13d, %ecx movq 80(%rsp), %rdx movq 64(%rsp), %rsi movq 56(%rsp), %rdi call _Z15cpu_matrix_multPiS_S_iii movl $0, %esi movq 96(%rsp), %rdi call cudaEventRecord@PLT movq 96(%rsp), %rdi call cudaEventSynchronize@PLT leaq 52(%rsp), %rdi movq 96(%rsp), %rdx movq 88(%rsp), %rsi call cudaEventElapsedTime@PLT testl %ebx, %ebx jle .L31 movq 80(%rsp), %r8 movq 72(%rsp), %rdi movq 40(%rsp), %r10 salq $2, %r10 leal -1(%rbx), %r11d leaq 4(,%r11,4), %rcx movl $0, %r9d movl $1, %edx notq %r11 salq $2, %r11 movl $0, %esi .L32: leaq (%r11,%rcx), %rax .L34: movl (%rdi,%rax), %ebx cmpl %ebx, (%r8,%rax) cmovne %esi, %edx addq $4, %rax cmpq %rax, %rcx jne .L34 addl $1, %r9d addq %r10, %rcx cmpl %r13d, %r9d jne .L32 testl %edx, %edx jne .L31 leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L37 .L45: movl %r13d, %ecx movq 120(%rsp), %rdx movq 112(%rsp), %rsi movq 104(%rsp), %rdi call _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i jmp .L30 .L31: movss 52(%rsp), %xmm0 divss 48(%rsp), %xmm0 pxor %xmm1, %xmm1 cvtss2sd %xmm0, %xmm1 movq %xmm1, %rbx movq 32(%rsp), %rax movq 16(%rax), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rbx, %xmm0 movl %eax, %ecx movl %r13d, %edx leaq .LC0(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT .L37: movq 104(%rsp), %rdi call cudaFree@PLT movq 112(%rsp), %rdi call cudaFree@PLT movq 120(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rdi call cudaFreeHost@PLT movq 64(%rsp), %rdi call cudaFreeHost@PLT movq 72(%rsp), %rdi call cudaFreeHost@PLT movq 80(%rsp), %rdi call cudaFreeHost@PLT movq 152(%rsp), %rax subq %fs:40, %rax jne .L46 movl $0, %eax addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L46: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC2: .string "_Z22gpu_square_matrix_multPiS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z22gpu_square_matrix_multPiS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z22gpu_square_matrix_multPiS_S_i ; -- Begin function _Z22gpu_square_matrix_multPiS_S_i .globl _Z22gpu_square_matrix_multPiS_S_i .p2align 8 .type _Z22gpu_square_matrix_multPiS_S_i,@function _Z22gpu_square_matrix_multPiS_S_i: ; @_Z22gpu_square_matrix_multPiS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s3, s[0:1], 0x20 s_load_b32 s2, s[0:1], 0x18 v_bfe_u32 v6, v0, 10, 10 v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v4, 0x3ff, v0 s_mov_b32 s8, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshl_add_u32 v5, s15, 3, v6 v_lshl_add_u32 v0, s14, 3, v4 s_waitcnt lgkmcnt(0) s_cmp_eq_u32 s3, 0 s_cbranch_scc1 .LBB0_13 ; %bb.1: ; %.lr.ph s_load_b128 s[4:7], s[0:1], 0x0 v_lshlrev_b32_e32 v1, 2, v4 v_lshlrev_b32_e32 v7, 5, v6 v_mad_u64_u32 v[2:3], null, v5, s2, v[4:5] s_mul_i32 s9, s2, s2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_nc_u32_e32 v8, 0x100, v1 v_add_nc_u32_e32 v9, v7, v1 v_mov_b32_e32 v1, 0 s_delay_alu instid0(VALU_DEP_3) v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v10, v8, v7 .LBB0_2: ; =>This Loop Header: Depth=1 ; Child Loop BB0_11 Depth 2 s_lshl_b32 s10, s8, 3 s_mov_b32 s11, exec_lo v_add_nc_u32_e32 v3, s10, v2 s_delay_alu instid0(VALU_DEP_1) v_cmpx_le_i32_e64 s9, v3 s_xor_b32 s11, exec_lo, s11 s_cbranch_execz .LBB0_4 ; %bb.3: ; in Loop: Header=BB0_2 Depth=1 ds_store_b32 v9, v11 ; implicit-def: $vgpr3 .LBB0_4: ; %Flow59 ; in Loop: Header=BB0_2 Depth=1 s_and_not1_saveexec_b32 s11, s11 s_cbranch_execz .LBB0_6 ; %bb.5: ; in Loop: Header=BB0_2 Depth=1 v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[3:4], 2, v[3:4] s_waitcnt lgkmcnt(0) v_add_co_u32 v3, vcc_lo, s4, v3 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo global_load_b32 v3, v[3:4], off s_waitcnt vmcnt(0) ds_store_b32 v9, v3 .LBB0_6: ; in Loop: Header=BB0_2 Depth=1 s_or_b32 exec_lo, exec_lo, s11 v_add_nc_u32_e32 v12, s10, v6 s_mov_b32 s10, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[3:4], null, v12, s2, v[0:1] v_cmpx_le_i32_e64 s9, v3 s_xor_b32 s10, exec_lo, s10 s_cbranch_execz .LBB0_8 ; %bb.7: ; in Loop: Header=BB0_2 Depth=1 ds_store_b32 v10, v11 ; implicit-def: $vgpr3_vgpr4 .LBB0_8: ; %Flow ; in Loop: Header=BB0_2 Depth=1 s_and_not1_saveexec_b32 s10, s10 s_cbranch_execz .LBB0_10 ; %bb.9: ; in Loop: Header=BB0_2 Depth=1 v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[3:4], 2, v[3:4] s_waitcnt lgkmcnt(0) v_add_co_u32 v3, vcc_lo, s6, v3 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo global_load_b32 v3, v[3:4], off s_waitcnt vmcnt(0) ds_store_b32 v10, v3 .LBB0_10: ; in Loop: Header=BB0_2 Depth=1 s_or_b32 exec_lo, exec_lo, s10 v_mov_b32_e32 v3, v8 s_mov_b32 s10, 0 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv .LBB0_11: ; Parent Loop BB0_2 Depth=1 ; => This Inner Loop Header: Depth=2 v_add_nc_u32_e32 v4, s10, v7 s_add_i32 s10, s10, 4 ds_load_b32 v14, v3 ds_load_b32 v4, v4 v_add_nc_u32_e32 v3, 32, v3 s_cmp_eq_u32 s10, 32 s_waitcnt lgkmcnt(0) v_mad_u64_u32 v[12:13], null, v14, v4, v[1:2] s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v1, v12 s_cbranch_scc0 .LBB0_11 ; %bb.12: ; in Loop: Header=BB0_2 Depth=1 s_add_i32 s8, s8, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s8, s3 s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB0_2 .LBB0_13: ; %Flow61 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_max_i32_e32 v2, v5, v0 s_mov_b32 s3, exec_lo v_cmpx_gt_i32_e64 s2, v2 s_cbranch_execz .LBB0_15 ; %bb.14: s_load_b64 s[0:1], s[0:1], 0x10 v_mad_u64_u32 v[2:3], null, v5, s2, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s0, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo global_store_b32 v[2:3], v1, off .LBB0_15: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z22gpu_square_matrix_multPiS_S_i .amdhsa_group_segment_fixed_size 512 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 15 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z22gpu_square_matrix_multPiS_S_i, .Lfunc_end0-_Z22gpu_square_matrix_multPiS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 560 ; NumSgprs: 18 ; NumVgprs: 15 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 512 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 15 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 512 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z22gpu_square_matrix_multPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z22gpu_square_matrix_multPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 15 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "53f84f5b1c344dc08a1189273b1cc3e7fcdee1c2.hip" .globl _Z37__device_stub__gpu_square_matrix_multPiS_S_i # -- Begin function _Z37__device_stub__gpu_square_matrix_multPiS_S_i .p2align 4, 0x90 .type _Z37__device_stub__gpu_square_matrix_multPiS_S_i,@function _Z37__device_stub__gpu_square_matrix_multPiS_S_i: # @_Z37__device_stub__gpu_square_matrix_multPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z22gpu_square_matrix_multPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z37__device_stub__gpu_square_matrix_multPiS_S_i, .Lfunc_end0-_Z37__device_stub__gpu_square_matrix_multPiS_S_i .cfi_endproc # -- End function .globl _Z15cpu_matrix_multPiS_S_iii # -- Begin function _Z15cpu_matrix_multPiS_S_iii .p2align 4, 0x90 .type _Z15cpu_matrix_multPiS_S_iii,@function _Z15cpu_matrix_multPiS_S_iii: # @_Z15cpu_matrix_multPiS_S_iii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %r9d, -36(%rsp) # 4-byte Spill movq %rdx, -8(%rsp) # 8-byte Spill movq %rsi, -16(%rsp) # 8-byte Spill movq %rdi, -24(%rsp) # 8-byte Spill testl %ecx, %ecx jle .LBB1_7 # %bb.1: # %.preheader27.lr.ph movslq -36(%rsp), %rax # 4-byte Folded Reload movl %ecx, %r9d movl %eax, %r10d movl %r8d, %r11d movq %rax, -32(%rsp) # 8-byte Spill leaq (,%rax,4), %rbx xorl %r14d, %r14d xorl %r15d, %r15d jmp .LBB1_2 .p2align 4, 0x90 .LBB1_6: # %._crit_edge31 # in Loop: Header=BB1_2 Depth=1 incq %r15 addl %r8d, %r14d cmpq %r9, %r15 je .LBB1_7 .LBB1_2: # %.preheader27 # =>This Loop Header: Depth=1 # Child Loop BB1_4 Depth 2 # Child Loop BB1_9 Depth 3 cmpl $0, -36(%rsp) # 4-byte Folded Reload jle .LBB1_6 # %bb.3: # %.preheader.lr.ph # in Loop: Header=BB1_2 Depth=1 movl %r14d, %eax movq -24(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %r12 movq %r15, %rax imulq -32(%rsp), %rax # 8-byte Folded Reload movq -8(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %r13 movq -16(%rsp), %rdi # 8-byte Reload xorl %eax, %eax jmp .LBB1_4 .p2align 4, 0x90 .LBB1_5: # in Loop: Header=BB1_4 Depth=2 xorl %edx, %edx .LBB1_10: # %._crit_edge # in Loop: Header=BB1_4 Depth=2 movl %edx, (%r13,%rax,4) incq %rax addq $4, %rdi cmpq %r10, %rax je .LBB1_6 .LBB1_4: # %.preheader # Parent Loop BB1_2 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB1_9 Depth 3 testl %r8d, %r8d jle .LBB1_5 # %bb.8: # %.lr.ph.preheader # in Loop: Header=BB1_4 Depth=2 xorl %esi, %esi movq %rdi, %rbp xorl %edx, %edx .p2align 4, 0x90 .LBB1_9: # %.lr.ph # Parent Loop BB1_2 Depth=1 # Parent Loop BB1_4 Depth=2 # => This Inner Loop Header: Depth=3 movl (%rbp), %ecx imull (%r12,%rsi,4), %ecx addl %ecx, %edx incq %rsi addq %rbx, %rbp cmpq %rsi, %r11 jne .LBB1_9 jmp .LBB1_10 .LBB1_7: # %._crit_edge33 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z15cpu_matrix_multPiS_S_iii, .Lfunc_end1-_Z15cpu_matrix_multPiS_S_iii .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $216, %rsp .cfi_def_cfa_offset 272 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %rbx movl $3333, %edi # imm = 0xD05 callq srand movq %rbx, 104(%rsp) # 8-byte Spill movq 8(%rbx), %rdi xorl %r13d, %r13d xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %rbx movslq %ebx, %r14 movq %r14, %r15 imulq %r14, %r15 shlq $2, %r15 leaq 32(%rsp), %rdi movq %r15, %rsi xorl %edx, %edx callq hipHostMalloc leaq 24(%rsp), %rdi movq %r15, %rsi xorl %edx, %edx callq hipHostMalloc leaq 72(%rsp), %rdi movq %r15, %rsi xorl %edx, %edx callq hipHostMalloc leaq 64(%rsp), %rdi movq %r15, 8(%rsp) # 8-byte Spill movq %r15, %rsi xorl %edx, %edx callq hipHostMalloc movq %r14, %rax movq %r14, 112(%rsp) # 8-byte Spill testl %r14d, %r14d jle .LBB2_5 # %bb.1: # %.preheader86.lr.ph movl %ebx, %r15d xorl %r14d, %r14d .p2align 4, 0x90 .LBB2_2: # %.preheader86 # =>This Loop Header: Depth=1 # Child Loop BB2_3 Depth 2 movl %r13d, %r13d movq %r15, %rbp movq %r13, %r12 .p2align 4, 0x90 .LBB2_3: # Parent Loop BB2_2 Depth=1 # => This Inner Loop Header: Depth=2 callq rand # kill: def $eax killed $eax def $rax leal 1023(%rax), %ecx testl %eax, %eax cmovnsl %eax, %ecx andl $-1024, %ecx # imm = 0xFC00 subl %ecx, %eax movq 32(%rsp), %rcx movl %eax, (%rcx,%r12,4) incq %r12 decq %rbp jne .LBB2_3 # %bb.4: # %._crit_edge # in Loop: Header=BB2_2 Depth=1 incq %r14 addl %ebx, %r13d cmpq %r15, %r14 jne .LBB2_2 .LBB2_5: # %.preheader85 testl %ebx, %ebx jle .LBB2_10 # %bb.6: # %.preheader84.lr.ph movl %ebx, %r12d xorl %ebp, %ebp xorl %r14d, %r14d .p2align 4, 0x90 .LBB2_7: # %.preheader84 # =>This Loop Header: Depth=1 # Child Loop BB2_8 Depth 2 movl %ebp, %ebp movq %r12, %r15 movq %rbp, %r13 .p2align 4, 0x90 .LBB2_8: # Parent Loop BB2_7 Depth=1 # => This Inner Loop Header: Depth=2 callq rand # kill: def $eax killed $eax def $rax leal 1023(%rax), %ecx testl %eax, %eax cmovnsl %eax, %ecx andl $-1024, %ecx # imm = 0xFC00 subl %ecx, %eax movq 24(%rsp), %rcx movl %eax, (%rcx,%r13,4) incq %r13 decq %r15 jne .LBB2_8 # %bb.9: # %._crit_edge91 # in Loop: Header=BB2_7 Depth=1 incq %r14 addl %ebx, %ebp cmpq %r12, %r14 jne .LBB2_7 .LBB2_10: # %._crit_edge93 leaq 16(%rsp), %rdi callq hipEventCreate movq %rsp, %rdi callq hipEventCreate movq 16(%rsp), %rdi xorl %esi, %esi callq hipEventRecord leaq 56(%rsp), %rdi movq 8(%rsp), %r14 # 8-byte Reload movq %r14, %rsi callq hipMalloc leaq 48(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 40(%rsp), %rdi movq %r14, %rsi callq hipMalloc movq 56(%rsp), %rdi movq 32(%rsp), %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movq 48(%rsp), %rdi movq 24(%rsp), %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leal 7(%rbx), %eax leal 14(%rbx), %ecx testl %eax, %eax cmovnsl %eax, %ecx sarl $3, %ecx movq %rcx, %r12 shlq $32, %r12 orq %rcx, %r12 movq 104(%rsp), %rax # 8-byte Reload movq 16(%rax), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol leal (,%rax,8), %edx shlq $35, %rax orq %rax, %rdx movq %r12, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_12 # %bb.11: movq 56(%rsp), %rax movq 48(%rsp), %rcx movq 40(%rsp), %rdx movq %rax, 168(%rsp) movq %rcx, 160(%rsp) movq %rdx, 152(%rsp) movl %ebx, 84(%rsp) leaq 168(%rsp), %rax movq %rax, 176(%rsp) leaq 160(%rsp), %rax movq %rax, 184(%rsp) leaq 152(%rsp), %rax movq %rax, 192(%rsp) leaq 84(%rsp), %rax movq %rax, 200(%rsp) leaq 88(%rsp), %rdi leaq 136(%rsp), %rsi leaq 128(%rsp), %rdx leaq 120(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 136(%rsp), %rcx movl 144(%rsp), %r8d leaq 176(%rsp), %r9 movl $_Z22gpu_square_matrix_multPiS_S_i, %edi pushq 120(%rsp) .cfi_adjust_cfa_offset 8 pushq 136(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_12: movq 72(%rsp), %rdi movq 40(%rsp), %rsi movq %r14, %rdx movl $2, %ecx callq hipMemcpy callq hipDeviceSynchronize movq (%rsp), %rdi xorl %r15d, %r15d xorl %esi, %esi callq hipEventRecord movq (%rsp), %rdi callq hipEventSynchronize movq 16(%rsp), %rsi movq (%rsp), %rdx leaq 176(%rsp), %rdi callq hipEventElapsedTime movq 16(%rsp), %rdi xorl %esi, %esi callq hipEventRecord testl %ebx, %ebx movq %rbx, 8(%rsp) # 8-byte Spill jle .LBB2_19 # %bb.13: # %.preheader27.lr.ph.i movq 32(%rsp), %rax movq 24(%rsp), %rcx movq 64(%rsp), %rdx movl %ebx, %esi movq 112(%rsp), %rdi # 8-byte Reload leaq (,%rdi,4), %rdi xorl %r8d, %r8d .p2align 4, 0x90 .LBB2_14: # %.preheader27.i # =>This Loop Header: Depth=1 # Child Loop BB2_15 Depth 2 # Child Loop BB2_16 Depth 3 movl %r15d, %r9d leaq (%rax,%r9,4), %r9 movq %r8, %r10 imulq 112(%rsp), %r10 # 8-byte Folded Reload leaq (%rdx,%r10,4), %r10 movq %rcx, %r11 xorl %r14d, %r14d .p2align 4, 0x90 .LBB2_15: # %.preheader.i # Parent Loop BB2_14 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB2_16 Depth 3 xorl %r12d, %r12d movq %r11, %r13 xorl %ebp, %ebp .p2align 4, 0x90 .LBB2_16: # %.lr.ph.i # Parent Loop BB2_14 Depth=1 # Parent Loop BB2_15 Depth=2 # => This Inner Loop Header: Depth=3 movl (%r13), %ebx imull (%r9,%r12,4), %ebx addl %ebx, %ebp incq %r12 addq %rdi, %r13 cmpq %r12, %rsi jne .LBB2_16 # %bb.17: # %._crit_edge.i # in Loop: Header=BB2_15 Depth=2 movl %ebp, (%r10,%r14,4) incq %r14 addq $4, %r11 cmpq %rsi, %r14 jne .LBB2_15 # %bb.18: # %._crit_edge31.i # in Loop: Header=BB2_14 Depth=1 incq %r8 movq 8(%rsp), %rbx # 8-byte Reload addl %ebx, %r15d cmpq %rsi, %r8 jne .LBB2_14 .LBB2_19: # %_Z15cpu_matrix_multPiS_S_iii.exit movq (%rsp), %rdi xorl %r15d, %r15d xorl %esi, %esi callq hipEventRecord movq (%rsp), %rdi callq hipEventSynchronize movq 16(%rsp), %rsi movq (%rsp), %rdx leaq 88(%rsp), %rdi callq hipEventElapsedTime testl %ebx, %ebx jle .LBB2_25 # %bb.20: # %.preheader.lr.ph movq 64(%rsp), %rax movq 72(%rsp), %rcx movl %ebx, %edx movl $1, %esi xorl %edi, %edi xorl %r8d, %r8d .p2align 4, 0x90 .LBB2_21: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB2_22 Depth 2 movl %edi, %r10d leaq (%rcx,%r10,4), %r9 leaq (%rax,%r10,4), %r10 xorl %r11d, %r11d .p2align 4, 0x90 .LBB2_22: # Parent Loop BB2_21 Depth=1 # => This Inner Loop Header: Depth=2 movl (%r10,%r11,4), %ebx cmpl (%r9,%r11,4), %ebx cmovnel %r15d, %esi incq %r11 cmpq %r11, %rdx jne .LBB2_22 # %bb.23: # %._crit_edge101 # in Loop: Header=BB2_21 Depth=1 incq %r8 movq 8(%rsp), %rbx # 8-byte Reload addl %ebx, %edi cmpq %rdx, %r8 jne .LBB2_21 # %bb.24: # %._crit_edge104.loopexit testl %esi, %esi je .LBB2_26 .LBB2_25: # %.critedge movq 104(%rsp), %rax # 8-byte Reload movq 16(%rax), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movss 88(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero divss 176(%rsp), %xmm0 cvtss2sd %xmm0, %xmm0 movl $.L.str, %edi movl %ebx, %esi movl %eax, %edx movb $1, %al callq printf jmp .LBB2_27 .LBB2_26: movl $.Lstr, %edi callq puts@PLT .LBB2_27: movq 56(%rsp), %rdi callq hipFree movq 48(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipHostFree movq 24(%rsp), %rdi callq hipHostFree movq 72(%rsp), %rdi callq hipHostFree movq 64(%rsp), %rdi callq hipHostFree xorl %eax, %eax addq $216, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z22gpu_square_matrix_multPiS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z22gpu_square_matrix_multPiS_S_i,@object # @_Z22gpu_square_matrix_multPiS_S_i .section .rodata,"a",@progbits .globl _Z22gpu_square_matrix_multPiS_S_i .p2align 3, 0x0 _Z22gpu_square_matrix_multPiS_S_i: .quad _Z37__device_stub__gpu_square_matrix_multPiS_S_i .size _Z22gpu_square_matrix_multPiS_S_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%d\t%d\t%f\n" .size .L.str, 10 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z22gpu_square_matrix_multPiS_S_i" .size .L__unnamed_1, 34 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "incorrect results" .size .Lstr, 18 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z37__device_stub__gpu_square_matrix_multPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z22gpu_square_matrix_multPiS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z3addiPfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_TID.X ; ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; @P0 EXIT ; I2F.U32.RP R5, c[0x0][0x0] ; LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; ULDC.64 UR4, c[0x0][0x118] ; ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; BSSY B0, 0x2d0 ; IADD3 R4, R4, c[0x0][0x160], RZ ; MUFU.RCP R5, R5 ; IADD3 R2, R5, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; HFMA2.MMA R2, -RZ, RZ, 0, 0 ; IMAD.MOV R7, RZ, RZ, -R3 ; IMAD R7, R7, c[0x0][0x0], RZ ; IMAD.HI.U32 R3, R3, R7, R2 ; IMAD.HI.U32 R3, R3, R4, RZ ; IMAD.MOV R5, RZ, RZ, -R3 ; IMAD R4, R5, c[0x0][0x0], R4 ; ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; @P0 IADD3 R3, R3, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; @P1 IADD3 R3, R3, 0x1, RZ ; @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; IADD3 R2, R3.reuse, 0x1, RZ ; ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; @!P0 BRA 0x2c0 ; MOV R9, 0x4 ; IMAD.MOV.U32 R6, RZ, RZ, R2 ; IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; LDG.E R7, [R2.64] ; LDG.E R8, [R4.64] ; IADD3 R6, R6, -0x1, RZ ; IADD3 R0, R0, c[0x0][0x0], RZ ; ISETP.NE.AND P0, PT, R6, RZ, PT ; IMAD.WIDE R4, R9, c[0x0][0x0], R4 ; FADD R7, R7, R8 ; STG.E [R2.64], R7 ; IMAD.WIDE R2, R9, c[0x0][0x0], R2 ; @P0 BRA 0x220 ; BSYNC B0 ; @!P1 EXIT ; HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD.WIDE R2, R0, R21, c[0x0][0x168] ; IMAD.WIDE R4, R0, R21, c[0x0][0x170] ; LDG.E R7, [R2.64] ; LDG.E R6, [R4.64] ; IMAD.WIDE R8, R21, c[0x0][0x0], R4 ; FADD R15, R6, R7 ; IMAD.WIDE R6, R21, c[0x0][0x0], R2 ; STG.E [R4.64], R15 ; LDG.E R10, [R8.64] ; LDG.E R11, [R6.64] ; IMAD.WIDE R12, R21, c[0x0][0x0], R8 ; FADD R17, R10, R11 ; IMAD.WIDE R10, R21, c[0x0][0x0], R6 ; STG.E [R8.64], R17 ; LDG.E R2, [R12.64] ; LDG.E R3, [R10.64] ; IMAD.WIDE R4, R21, c[0x0][0x0], R12 ; FADD R19, R2, R3 ; IMAD.WIDE R2, R21, c[0x0][0x0], R10 ; STG.E [R12.64], R19 ; LDG.E R3, [R2.64] ; LDG.E R6, [R4.64] ; MOV R15, c[0x0][0x0] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; LEA R0, R15, R0, 0x1 ; LEA R0, R9, R0, 0x1 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; FADD R7, R6, R3 ; STG.E [R4.64], R7 ; @!P0 BRA 0x2e0 ; EXIT ; BRA 0x4e0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00029f59_00000000-6_9ca58f890b2cc9e3d07d5d98cc166ddabdee98c4.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z25__device_stub__Z3addiPfS_iPfS_ .type _Z25__device_stub__Z3addiPfS_iPfS_, @function _Z25__device_stub__Z3addiPfS_iPfS_: .LFB3694: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movl %edi, 28(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z3addiPfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_ .globl _Z3addiPfS_ .type _Z3addiPfS_, @function _Z3addiPfS_: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z25__device_stub__Z3addiPfS_iPfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z3addiPfS_, .-_Z3addiPfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC5: .string "Max error: " .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $72, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leaq 16(%rsp), %rdi movl $1, %edx movl $4194304, %esi call cudaMallocManaged@PLT leaq 24(%rsp), %rdi movl $1, %edx movl $4194304, %esi call cudaMallocManaged@PLT movl $0, %eax movss .LC1(%rip), %xmm1 movss .LC2(%rip), %xmm0 .L12: movq 16(%rsp), %rdx movss %xmm1, (%rdx,%rax) movq 24(%rsp), %rdx movss %xmm0, (%rdx,%rax) addq $4, %rax cmpq $4194304, %rax jne .L12 movl $256, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L19 .L13: call cudaDeviceSynchronize@PLT movq 24(%rsp), %rbx leaq 4194304(%rbx), %rbp movl $0x00000000, 12(%rsp) .L14: movss (%rbx), %xmm0 subss .LC3(%rip), %xmm0 andps .LC4(%rip), %xmm0 movss 12(%rsp), %xmm1 call fmaxf@PLT movss %xmm0, 12(%rsp) addq $4, %rbx cmpq %rbp, %rbx jne .L14 leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd 12(%rsp), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L20 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state movq 24(%rsp), %rdx movq 16(%rsp), %rsi movl $1048576, %edi call _Z25__device_stub__Z3addiPfS_iPfS_ jmp .L13 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1 .LC6: .string "_Z3addiPfS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z3addiPfS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 1065353216 .align 4 .LC2: .long 1073741824 .align 4 .LC3: .long 1077936128 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC4: .long 2147483647 .long 0 .long 0 .long 0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z3addiPfS_ ; -- Begin function _Z3addiPfS_ .globl _Z3addiPfS_ .p2align 8 .type _Z3addiPfS_,@function _Z3addiPfS_: ; @_Z3addiPfS_ ; %bb.0: s_load_b32 s2, s[0:1], 0x0 s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) v_cmpx_gt_i32_e64 s2, v0 s_cbranch_execz .LBB0_3 ; %bb.1: ; %.lr.ph.preheader s_clause 0x1 s_load_b32 s3, s[0:1], 0x24 s_load_b128 s[4:7], s[0:1], 0x8 v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0 s_waitcnt lgkmcnt(0) s_and_b32 s1, s3, 0xffff s_mov_b32 s3, 0 s_lshl_b32 s8, s1, 2 s_mov_b32 s9, s3 .p2align 6 .LBB0_2: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 v_add_co_u32 v3, vcc_lo, s4, v1 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo v_add_co_u32 v5, vcc_lo, s6, v1 v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo v_add_nc_u32_e32 v0, s1, v0 global_load_b32 v3, v[3:4], off global_load_b32 v4, v[5:6], off v_add_co_u32 v1, vcc_lo, v1, s8 v_cmp_le_i32_e64 s0, s2, v0 v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo s_delay_alu instid0(VALU_DEP_2) s_or_b32 s9, s0, s9 s_waitcnt vmcnt(0) v_add_f32_e32 v3, v3, v4 global_store_b32 v[5:6], v3, off s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB0_2 .LBB0_3: ; %Flow19 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z3addiPfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 10 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 188 ; NumSgprs: 12 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 12 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z3addiPfS_ .private_segment_fixed_size: 0 .sgpr_count: 12 .sgpr_spill_count: 0 .symbol: _Z3addiPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "9ca58f890b2cc9e3d07d5d98cc166ddabdee98c4.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_ .p2align 4, 0x90 .type _Z18__device_stub__addiPfS_,@function _Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movl %edi, 12(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3addiPfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_ .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI1_0: .long 0xc0400000 # float -3 .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 .LCPI1_1: .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .long 0x7fffffff # float NaN .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $152, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 leaq 16(%rsp), %rdi movl $4194304, %esi # imm = 0x400000 movl $1, %edx callq hipMallocManaged leaq 8(%rsp), %rdi movl $4194304, %esi # imm = 0x400000 movl $1, %edx callq hipMallocManaged movq 16(%rsp), %rax xorl %ecx, %ecx movq 8(%rsp), %rdx .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000 movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000 incq %rcx cmpq $1048576, %rcx # imm = 0x100000 jne .LBB1_1 # %bb.2: movabsq $4294967297, %rdi # imm = 0x100000001 leaq 255(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 16(%rsp), %rax movq 8(%rsp), %rcx movl $1048576, 28(%rsp) # imm = 0x100000 movq %rax, 88(%rsp) movq %rcx, 80(%rsp) leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 88(%rsp), %rax movq %rax, 104(%rsp) leaq 80(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z3addiPfS_, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: callq hipDeviceSynchronize xorps %xmm2, %xmm2 xorl %eax, %eax movq 8(%rsp), %rcx movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN] movaps %xmm2, %xmm5 .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero addss %xmm0, %xmm3 andps %xmm1, %xmm3 cmpunordss %xmm5, %xmm5 movaps %xmm5, %xmm4 andps %xmm3, %xmm4 maxss %xmm2, %xmm3 andnps %xmm3, %xmm5 orps %xmm4, %xmm5 incq %rax movaps %xmm5, %xmm2 cmpq $1048576, %rax # imm = 0x100000 jne .LBB1_5 # %bb.6: movl $_ZSt4cout, %edi movl $.L.str, %esi movl $11, %edx movaps %xmm5, 128(%rsp) # 16-byte Spill callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movaps 128(%rsp), %xmm0 # 16-byte Reload cvtss2sd %xmm0, %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB1_11 # %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB1_9 # %bb.8: movzbl 67(%rbx), %ecx jmp .LBB1_10 .LBB1_9: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax addq $152, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB1_11: .cfi_def_cfa_offset 176 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3addiPfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z3addiPfS_,@object # @_Z3addiPfS_ .section .rodata,"a",@progbits .globl _Z3addiPfS_ .p2align 3, 0x0 _Z3addiPfS_: .quad _Z18__device_stub__addiPfS_ .size _Z3addiPfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Max error: " .size .L.str, 12 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z3addiPfS_" .size .L__unnamed_1, 12 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__addiPfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3addiPfS_ .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
1,929
3,136
2,545
3,891
179
code for sm_80 Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; ULDC.64 UR4, c[0x0][0x118] ; S2R R5, SR_TID.X ; IMAD.WIDE.U32 R2, R2, 0x200, RZ ; IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; IADD3 R0, P2, R2, R5, RZ ; ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; IMAD.X R3, RZ, RZ, R3, P2 ; LEA R2, P1, R0, c[0x0][0x168], 0x2 ; ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; @P0 BRA 0x1a0 ; ISETP.GT.U32.AND P0, PT, R4, R5, PT ; SHF.R.S32.HI R6, RZ, 0x1f, R4 ; IADD3 R0, R5, 0x100, RZ ; ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; @P0 STG.E [R2.64], R7 ; ISETP.GT.U32.AND P0, PT, R4, R0, PT ; ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; @!P0 EXIT ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; STG.E [R2.64+0x400], R5 ; EXIT ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; STG.E [R2.64], R5 ; STG.E [R2.64+0x400], R5 ; EXIT ; BRA 0x1e0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; EXIT ; BRA 0x20; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z7reduce0PiS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R7, SR_TID.X ; ULDC.64 UR6, c[0x0][0x118] ; S2R R6, SR_CTAID.X ; IMAD R2, R6, c[0x0][0x0], R7 ; ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x170], PT ; @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; @!P1 IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; @!P1 LDG.E R2, [R2.64] ; ULDC UR4, c[0x0][0x0] ; ISETP.NE.AND P0, PT, R7, RZ, PT ; USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; STS [R7.X4], RZ ; ISETP.NE.AND P2, PT, RZ, UR4, PT ; @!P1 STS [R7.X4], R2 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P2 BRA 0x1d0 ; SHF.L.U32 R0, R7, 0x2, RZ ; IMAD.U32 R3, RZ, RZ, UR4 ; ISETP.GE.U32.AND P1, PT, R7, R3, PT ; @!P1 LEA R2, R3, R0, 0x2 ; @!P1 LDS R4, [R7.X4] ; SHF.R.U32.HI R3, RZ, 0x1, R3 ; @!P1 LDS R5, [R2] ; @!P1 IMAD.IADD R4, R4, 0x1, R5 ; @!P1 STS [R7.X4], R4 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.NE.AND P1, PT, R3, RZ, PT ; @P1 BRA 0x130 ; @P0 EXIT ; LDS R5, [RZ] ; HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; STG.E [R2.64], R5 ; EXIT ; BRA 0x230; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000530c9_00000000-6_c8162ff249296ec514785872e181e47080f71afe.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .section .text._ZNK6thrust20THRUST_200700_800_NS6system14error_category23default_error_conditionEi,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system14error_category23default_error_conditionEi,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6system14error_category23default_error_conditionEi .type _ZNK6thrust20THRUST_200700_800_NS6system14error_category23default_error_conditionEi, @function _ZNK6thrust20THRUST_200700_800_NS6system14error_category23default_error_conditionEi: .LFB8259: .cfi_startproc endbr64 movq %rdi, %rdx movl %esi, %eax ret .cfi_endproc .LFE8259: .size _ZNK6thrust20THRUST_200700_800_NS6system14error_category23default_error_conditionEi, .-_ZNK6thrust20THRUST_200700_800_NS6system14error_category23default_error_conditionEi .section .text._ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentEiRKNS1_15error_conditionE,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentEiRKNS1_15error_conditionE,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentEiRKNS1_15error_conditionE .type _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentEiRKNS1_15error_conditionE, @function _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentEiRKNS1_15error_conditionE: .LFB8260: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdx, %rbx movq (%rdi), %rax call *24(%rax) movq %rdx, %rcx movl $0, %edx cmpq %rcx, 8(%rbx) je .L6 .L3: movl %edx, %eax popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L6: .cfi_restore_state cmpl %eax, (%rbx) sete %dl jmp .L3 .cfi_endproc .LFE8260: .size _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentEiRKNS1_15error_conditionE, .-_ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentEiRKNS1_15error_conditionE .section .text._ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentERKNS1_10error_codeEi,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentERKNS1_10error_codeEi,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentERKNS1_10error_codeEi .type _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentERKNS1_10error_codeEi, @function _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentERKNS1_10error_codeEi: .LFB8261: .cfi_startproc endbr64 movl $0, %eax cmpq %rdi, 8(%rsi) je .L10 .L7: ret .L10: cmpl %edx, (%rsi) sete %al ret .cfi_endproc .LFE8261: .size _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentERKNS1_10error_codeEi, .-_ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentERKNS1_10error_codeEi .section .rodata._ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category4nameEv.str1.1,"aMS",@progbits,1 .LC0: .string "generic" .section .text._ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category4nameEv,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category4nameEv,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category4nameEv .type _ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category4nameEv, @function _ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category4nameEv: .LFB8271: .cfi_startproc endbr64 leaq .LC0(%rip), %rax ret .cfi_endproc .LFE8271: .size _ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category4nameEv, .-_ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category4nameEv .section .rodata._ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category4nameEv.str1.1,"aMS",@progbits,1 .LC1: .string "system" .section .text._ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category4nameEv,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category4nameEv,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category4nameEv .type _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category4nameEv, @function _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category4nameEv: .LFB8276: .cfi_startproc endbr64 leaq .LC1(%rip), %rax ret .cfi_endproc .LFE8276: .size _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category4nameEv, .-_ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category4nameEv .section .text._ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD2Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD2Ev .type _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD2Ev, @function _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD2Ev: .LFB8281: .cfi_startproc endbr64 ret .cfi_endproc .LFE8281: .size _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD2Ev, .-_ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD2Ev .weak _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev .set _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev,_ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD2Ev .section .text._ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD2Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD2Ev .type _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD2Ev, @function _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD2Ev: .LFB8286: .cfi_startproc endbr64 ret .cfi_endproc .LFE8286: .size _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD2Ev, .-_ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD2Ev .weak _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD1Ev .set _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD1Ev,_ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD2Ev .section .rodata._ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category4nameEv.str1.1,"aMS",@progbits,1 .LC2: .string "cuda" .section .text._ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category4nameEv,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category4nameEv,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category4nameEv .type _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category4nameEv, @function _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category4nameEv: .LFB8336: .cfi_startproc endbr64 leaq .LC2(%rip), %rax ret .cfi_endproc .LFE8336: .size _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category4nameEv, .-_ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category4nameEv .section .text._ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD2Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD2Ev .type _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD2Ev, @function _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD2Ev: .LFB8341: .cfi_startproc endbr64 ret .cfi_endproc .LFE8341: .size _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD2Ev, .-_ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD2Ev .weak _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD1Ev .set _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD1Ev,_ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD2Ev .section .text.nvtxEtiGetModuleFunctionTable_v3,"axG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat .weak nvtxEtiGetModuleFunctionTable_v3 .hidden nvtxEtiGetModuleFunctionTable_v3 .type nvtxEtiGetModuleFunctionTable_v3, @function nvtxEtiGetModuleFunctionTable_v3: .LFB8504: .cfi_startproc endbr64 cmpl $6, %edi ja .L27 movl %edi, %edi leaq .L20(%rip), %rcx movslq (%rcx,%rdi,4), %rax addq %rcx, %rax notrack jmp *%rax .section .rodata.nvtxEtiGetModuleFunctionTable_v3,"aG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat .align 4 .align 4 .L20: .long .L27-.L20 .long .L25-.L20 .long .L28-.L20 .long .L23-.L20 .long .L22-.L20 .long .L21-.L20 .long .L19-.L20 .section .text.nvtxEtiGetModuleFunctionTable_v3,"axG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat .L25: leaq 560+nvtxGlobals_v3(%rip), %rcx movl $136, %eax .L24: testq %rdx, %rdx je .L26 shrl $3, %eax subl $1, %eax movl %eax, (%rdx) .L26: movl $1, %eax testq %rsi, %rsi je .L17 movq %rcx, (%rsi) ret .L23: leaq 776+nvtxGlobals_v3(%rip), %rcx movl $128, %eax jmp .L24 .L22: leaq 904+nvtxGlobals_v3(%rip), %rcx movl $64, %eax jmp .L24 .L21: leaq 968+nvtxGlobals_v3(%rip), %rcx movl $136, %eax jmp .L24 .L19: leaq 1104+nvtxGlobals_v3(%rip), %rcx movl $64, %eax jmp .L24 .L28: leaq 696+nvtxGlobals_v3(%rip), %rcx movl $80, %eax jmp .L24 .L27: movl $0, %eax .L17: ret .cfi_endproc .LFE8504: .size nvtxEtiGetModuleFunctionTable_v3, .-nvtxEtiGetModuleFunctionTable_v3 .section .text.nvtxGetExportTable_v3,"axG",@progbits,nvtxGetExportTable_v3,comdat .weak nvtxGetExportTable_v3 .hidden nvtxGetExportTable_v3 .type nvtxGetExportTable_v3, @function nvtxGetExportTable_v3: .LFB8505: .cfi_startproc endbr64 leaq 8+nvtxGlobals_v3(%rip), %rax cmpl $1, %edi je .L30 cmpl $3, %edi leaq 16(%rax), %rax movl $0, %edx cmovne %rdx, %rax .L30: ret .cfi_endproc .LFE8505: .size nvtxGetExportTable_v3, .-nvtxGetExportTable_v3 .section .text.nvtxEtiSetInjectionNvtxVersion_v3,"axG",@progbits,nvtxEtiSetInjectionNvtxVersion_v3,comdat .weak nvtxEtiSetInjectionNvtxVersion_v3 .hidden nvtxEtiSetInjectionNvtxVersion_v3 .type nvtxEtiSetInjectionNvtxVersion_v3, @function nvtxEtiSetInjectionNvtxVersion_v3: .LFB8506: .cfi_startproc endbr64 ret .cfi_endproc .LFE8506: .size nvtxEtiSetInjectionNvtxVersion_v3, .-nvtxEtiSetInjectionNvtxVersion_v3 .section .text._ZNK6thrust20THRUST_200700_800_NS6system6detail9bad_alloc4whatEv,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system6detail9bad_alloc4whatEv,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6system6detail9bad_alloc4whatEv .type _ZNK6thrust20THRUST_200700_800_NS6system6detail9bad_alloc4whatEv, @function _ZNK6thrust20THRUST_200700_800_NS6system6detail9bad_alloc4whatEv: .LFB9576: .cfi_startproc endbr64 movq 8(%rdi), %rax ret .cfi_endproc .LFE9576: .size _ZNK6thrust20THRUST_200700_800_NS6system6detail9bad_alloc4whatEv, .-_ZNK6thrust20THRUST_200700_800_NS6system6detail9bad_alloc4whatEv .section .text._ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED2Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED2Ev .type _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED2Ev, @function _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED2Ev: .LFB13133: .cfi_startproc endbr64 ret .cfi_endproc .LFE13133: .size _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED2Ev, .-_ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED2Ev .weak _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED1Ev .set _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED1Ev,_ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED2Ev .section .text._ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED2Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED2Ev .type _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED2Ev, @function _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED2Ev: .LFB13293: .cfi_startproc endbr64 ret .cfi_endproc .LFE13293: .size _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED2Ev, .-_ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED2Ev .weak _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED1Ev .set _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED1Ev,_ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED2Ev .section .text._ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEE11do_is_equalERKS5_,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEE11do_is_equalERKS5_,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEE11do_is_equalERKS5_ .type _ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEE11do_is_equalERKS5_, @function _ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEE11do_is_equalERKS5_: .LFB13747: .cfi_startproc endbr64 cmpq %rdi, %rsi sete %al ret .cfi_endproc .LFE13747: .size _ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEE11do_is_equalERKS5_, .-_ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEE11do_is_equalERKS5_ .section .text._ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEE11do_is_equalERKSA_,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEE11do_is_equalERKSA_,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEE11do_is_equalERKSA_ .type _ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEE11do_is_equalERKSA_, @function _ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEE11do_is_equalERKSA_: .LFB13748: .cfi_startproc endbr64 cmpq %rdi, %rsi sete %al ret .cfi_endproc .LFE13748: .size _ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEE11do_is_equalERKSA_, .-_ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEE11do_is_equalERKSA_ .section .text._ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD0Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD0Ev .type _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD0Ev, @function _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD0Ev: .LFB8343: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl $8, %esi call _ZdlPvm@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE8343: .size _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD0Ev, .-_ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD0Ev .section .text._ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD0Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD0Ev .type _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD0Ev, @function _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD0Ev: .LFB8288: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl $8, %esi call _ZdlPvm@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE8288: .size _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD0Ev, .-_ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD0Ev .section .text._ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD0Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD0Ev .type _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD0Ev, @function _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD0Ev: .LFB8283: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl $8, %esi call _ZdlPvm@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE8283: .size _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD0Ev, .-_ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD0Ev .section .text._ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED0Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED0Ev .type _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED0Ev, @function _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED0Ev: .LFB13135: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl $16, %esi call _ZdlPvm@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE13135: .size _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED0Ev, .-_ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED0Ev .section .text._ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED0Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED0Ev .type _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED0Ev, @function _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED0Ev: .LFB13295: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl $8, %esi call _ZdlPvm@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE13295: .size _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED0Ev, .-_ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED0Ev .section .text._ZN4cuda3__410cuda_errorD2Ev,"axG",@progbits,_ZN4cuda3__410cuda_errorD5Ev,comdat .align 2 .weak _ZN4cuda3__410cuda_errorD2Ev .type _ZN4cuda3__410cuda_errorD2Ev, @function _ZN4cuda3__410cuda_errorD2Ev: .LFB6787: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq 16+_ZTVN4cuda3__410cuda_errorE(%rip), %rax movq %rax, (%rdi) call _ZNSt13runtime_errorD2Ev@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6787: .size _ZN4cuda3__410cuda_errorD2Ev, .-_ZN4cuda3__410cuda_errorD2Ev .weak _ZN4cuda3__410cuda_errorD1Ev .set _ZN4cuda3__410cuda_errorD1Ev,_ZN4cuda3__410cuda_errorD2Ev .section .text._ZN4cuda3__410cuda_errorD0Ev,"axG",@progbits,_ZN4cuda3__410cuda_errorD5Ev,comdat .align 2 .weak _ZN4cuda3__410cuda_errorD0Ev .type _ZN4cuda3__410cuda_errorD0Ev, @function _ZN4cuda3__410cuda_errorD0Ev: .LFB6789: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx leaq 16+_ZTVN4cuda3__410cuda_errorE(%rip), %rax movq %rax, (%rdi) call _ZNSt13runtime_errorD2Ev@PLT movl $16, %esi movq %rbx, %rdi call _ZdlPvm@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE6789: .size _ZN4cuda3__410cuda_errorD0Ev, .-_ZN4cuda3__410cuda_errorD0Ev .section .text._ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD2Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD2Ev .type _ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD2Ev, @function _ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD2Ev: .LFB13390: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE(%rip), %rax movq %rax, (%rdi) call _ZNSt13runtime_errorD2Ev@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE13390: .size _ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD2Ev, .-_ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD2Ev .weak _ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD1Ev .set _ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD1Ev,_ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD2Ev .section .text._ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD0Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD0Ev .type _ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD0Ev, @function _ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD0Ev: .LFB13392: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE(%rip), %rax movq %rax, (%rdi) call _ZNSt13runtime_errorD2Ev@PLT movl $16, %esi movq %rbx, %rdi call _ZdlPvm@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE13392: .size _ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD0Ev, .-_ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD0Ev .section .text._ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv,"axG",@progbits,_ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv,comdat .weak _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv .hidden _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv .type _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv, @function _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv: .LFB12467: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L62 .L58: movq 72(%rsp), %rax subq %fs:40, %rax jne .L63 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L62: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L58 .L63: call __stack_chk_fail@PLT .cfi_endproc .LFE12467: .size _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv, .-_ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv .section .text._ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_,"axG",@progbits,_ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_,comdat .weak _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_ .hidden _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_ .type _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_, @function _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_: .LFB12585: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rsi, (%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax movq %rdi, 24(%rsp) leaq 24(%rsp), %rax movq %rax, 96(%rsp) movq %rsp, %rax movq %rax, 104(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L68 .L64: movq 120(%rsp), %rax subq %fs:40, %rax jne .L69 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L68: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L64 .L69: call __stack_chk_fail@PLT .cfi_endproc .LFE12585: .size _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_, .-_ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_ .text .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB12055: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE12055: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .text._ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category23default_error_conditionEi,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category23default_error_conditionEi,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category23default_error_conditionEi .type _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category23default_error_conditionEi, @function _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category23default_error_conditionEi: .LFB8338: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movl %esi, %ebx cmpl $998, %esi jg .L73 movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result(%rip), %eax testb %al, %al je .L78 .L74: movl %ebx, %eax leaq _ZZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result(%rip), %rdx .L75: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L78: .cfi_restore_state leaq _ZGVZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L74 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L74 .L73: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result(%rip), %eax testb %al, %al je .L79 .L76: movl %ebx, %esi leaq _ZZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result(%rip), %rdi movq _ZZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result(%rip), %rax call *24(%rax) jmp .L75 .L79: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L76 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L76 .cfi_endproc .LFE8338: .size _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category23default_error_conditionEi, .-_ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category23default_error_conditionEi .section .text._ZN6thrust20THRUST_200700_800_NS6system12system_errorD2Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system12system_errorD5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system12system_errorD2Ev .type _ZN6thrust20THRUST_200700_800_NS6system12system_errorD2Ev, @function _ZN6thrust20THRUST_200700_800_NS6system12system_errorD2Ev: .LFB8345: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, (%rdi) movq 32(%rdi), %rdi leaq 48(%rbx), %rax cmpq %rax, %rdi je .L81 movq 48(%rbx), %rax leaq 1(%rax), %rsi call _ZdlPvm@PLT .L81: movq %rbx, %rdi call _ZNSt13runtime_errorD2Ev@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE8345: .size _ZN6thrust20THRUST_200700_800_NS6system12system_errorD2Ev, .-_ZN6thrust20THRUST_200700_800_NS6system12system_errorD2Ev .weak _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev .set _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev,_ZN6thrust20THRUST_200700_800_NS6system12system_errorD2Ev .section .text._ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD2Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD2Ev .type _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD2Ev, @function _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD2Ev: .LFB9573: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE(%rip), %rax movq %rax, (%rdi) movq 8(%rdi), %rdi leaq 24(%rbx), %rax cmpq %rax, %rdi je .L84 movq 24(%rbx), %rax leaq 1(%rax), %rsi call _ZdlPvm@PLT .L84: movq %rbx, %rdi call _ZNSt9bad_allocD2Ev@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE9573: .size _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD2Ev, .-_ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD2Ev .weak _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD1Ev .set _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD1Ev,_ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD2Ev .section .text._ZN6thrust20THRUST_200700_800_NS6system12system_errorD0Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system12system_errorD5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system12system_errorD0Ev .type _ZN6thrust20THRUST_200700_800_NS6system12system_errorD0Ev, @function _ZN6thrust20THRUST_200700_800_NS6system12system_errorD0Ev: .LFB8347: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, (%rdi) movq 32(%rdi), %rdi leaq 48(%rbx), %rax cmpq %rax, %rdi je .L87 movq 48(%rbx), %rax leaq 1(%rax), %rsi call _ZdlPvm@PLT .L87: movq %rbx, %rdi call _ZNSt13runtime_errorD2Ev@PLT movl $64, %esi movq %rbx, %rdi call _ZdlPvm@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE8347: .size _ZN6thrust20THRUST_200700_800_NS6system12system_errorD0Ev, .-_ZN6thrust20THRUST_200700_800_NS6system12system_errorD0Ev .section .text._ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD0Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD0Ev .type _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD0Ev, @function _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD0Ev: .LFB9575: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE(%rip), %rax movq %rax, (%rdi) movq 8(%rdi), %rdi leaq 24(%rbx), %rax cmpq %rax, %rdi je .L90 movq 24(%rbx), %rax leaq 1(%rax), %rsi call _ZdlPvm@PLT .L90: movq %rbx, %rdi call _ZNSt9bad_allocD2Ev@PLT movl $40, %esi movq %rbx, %rdi call _ZdlPvm@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE9575: .size _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD0Ev, .-_ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD0Ev .section .text._ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category7messageB5cxx11Ei,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category7messageB5cxx11Ei,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category7messageB5cxx11Ei .type _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category7messageB5cxx11Ei, @function _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category7messageB5cxx11Ei: .LFB8277: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $24, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbx movl %edx, %ebp movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L96 .L93: movl %ebp, %edx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi movq %rbx, %rdi movq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rax call *48(%rax) movq 8(%rsp), %rax subq %fs:40, %rax jne .L97 movq %rbx, %rax addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L96: .cfi_restore_state leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L93 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L93 .L97: call __stack_chk_fail@PLT .cfi_endproc .LFE8277: .size _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category7messageB5cxx11Ei, .-_ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category7messageB5cxx11Ei .section .rodata._ZNK6thrust20THRUST_200700_800_NS6system12system_error4whatEv.str1.1,"aMS",@progbits,1 .LC3: .string "basic_string::append" .LC4: .string ": " .section .text._ZNK6thrust20THRUST_200700_800_NS6system12system_error4whatEv,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system12system_error4whatEv,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6system12system_error4whatEv .type _ZNK6thrust20THRUST_200700_800_NS6system12system_error4whatEv, @function _ZNK6thrust20THRUST_200700_800_NS6system12system_error4whatEv: .LFB8368: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA8368 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $48, %rsp .cfi_def_cfa_offset 80 movq %rdi, %rbx movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax cmpq $0, 40(%rdi) je .L113 .L99: movq 32(%rbx), %rbx .L98: movq 40(%rsp), %rax subq %fs:40, %rax jne .L114 movq %rbx, %rax addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L113: .cfi_restore_state call _ZNKSt13runtime_error4whatEv@PLT movq %rax, %rbp leaq 32(%rbx), %r12 movq %rax, %rdi call strlen@PLT movq %rax, %r8 movq 40(%rbx), %rdx movq %rbp, %rcx movl $0, %esi movq %r12, %rdi .LEHB0: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT cmpl $0, 16(%rbx) je .L99 movq 40(%rbx), %rax testq %rax, %rax jne .L115 .L100: movq 24(%rbx), %rsi movq %rsp, %rdi movl 16(%rbx), %edx movq (%rsi), %rax call *48(%rax) jmp .L116 .L115: movabsq $4611686018427387903, %rdx subq %rax, %rdx cmpq $1, %rdx jbe .L117 movl $2, %edx leaq .LC4(%rip), %rsi movq %r12, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT jmp .L100 .L117: movq 40(%rsp), %rax subq %fs:40, %rax jne .L118 leaq .LC3(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .LEHE0: .L110: endbr64 movq %rax, %rdi jmp .L107 .L118: call __stack_chk_fail@PLT .L116: movq 8(%rsp), %rdx movq (%rsp), %rsi movabsq $4611686018427387903, %rax subq 40(%rbx), %rax cmpq %rdx, %rax jb .L119 movq %r12, %rdi .LEHB1: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT jmp .L120 .L119: movq 40(%rsp), %rax subq %fs:40, %rax jne .L121 leaq .LC3(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .LEHE1: .L111: endbr64 movq %rax, %rbp movq %rsp, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq %rbp, %rdi .L107: call __cxa_begin_catch@PLT movq %rbx, %rdi call _ZNKSt13runtime_error4whatEv@PLT movq %rax, %rbx call __cxa_end_catch@PLT jmp .L98 .L121: call __stack_chk_fail@PLT .L120: movq (%rsp), %rdi leaq 16(%rsp), %rax cmpq %rax, %rdi je .L99 movq 16(%rsp), %rax leaq 1(%rax), %rsi call _ZdlPvm@PLT jmp .L99 .L114: call __stack_chk_fail@PLT .cfi_endproc .LFE8368: .globl __gxx_personality_v0 .section .gcc_except_table._ZNK6thrust20THRUST_200700_800_NS6system12system_error4whatEv,"aG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system12system_error4whatEv,comdat .align 4 .LLSDA8368: .byte 0xff .byte 0x9b .uleb128 .LLSDATT8368-.LLSDATTD8368 .LLSDATTD8368: .byte 0x1 .uleb128 .LLSDACSE8368-.LLSDACSB8368 .LLSDACSB8368: .uleb128 .LEHB0-.LFB8368 .uleb128 .LEHE0-.LEHB0 .uleb128 .L110-.LFB8368 .uleb128 0x1 .uleb128 .LEHB1-.LFB8368 .uleb128 .LEHE1-.LEHB1 .uleb128 .L111-.LFB8368 .uleb128 0x3 .LLSDACSE8368: .byte 0x1 .byte 0 .byte 0 .byte 0x7d .align 4 .long 0 .LLSDATT8368: .section .text._ZNK6thrust20THRUST_200700_800_NS6system12system_error4whatEv,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system12system_error4whatEv,comdat .size _ZNK6thrust20THRUST_200700_800_NS6system12system_error4whatEv, .-_ZNK6thrust20THRUST_200700_800_NS6system12system_error4whatEv .section .text._ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category23default_error_conditionEi,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category23default_error_conditionEi,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category23default_error_conditionEi .type _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category23default_error_conditionEi, @function _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category23default_error_conditionEi: .LFB8278: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movl %esi, %ebx leal -9901(%rsi), %eax cmpl $78, %eax ja .L123 movl %eax, %eax leaq .L125(%rip), %rdx movslq (%rdx,%rax,4), %rax addq %rdx, %rax notrack jmp *%rax .section .rodata._ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category23default_error_conditionEi,"aG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category23default_error_conditionEi,comdat .align 4 .align 4 .L125: .long .L202-.L125 .long .L201-.L125 .long .L200-.L125 .long .L199-.L125 .long .L198-.L125 .long .L197-.L125 .long .L196-.L125 .long .L195-.L125 .long .L194-.L125 .long .L193-.L125 .long .L192-.L125 .long .L191-.L125 .long .L190-.L125 .long .L189-.L125 .long .L188-.L125 .long .L187-.L125 .long .L186-.L125 .long .L185-.L125 .long .L184-.L125 .long .L183-.L125 .long .L182-.L125 .long .L181-.L125 .long .L180-.L125 .long .L179-.L125 .long .L178-.L125 .long .L177-.L125 .long .L176-.L125 .long .L175-.L125 .long .L174-.L125 .long .L173-.L125 .long .L172-.L125 .long .L171-.L125 .long .L170-.L125 .long .L169-.L125 .long .L168-.L125 .long .L167-.L125 .long .L123-.L125 .long .L166-.L125 .long .L165-.L125 .long .L164-.L125 .long .L163-.L125 .long .L162-.L125 .long .L161-.L125 .long .L160-.L125 .long .L159-.L125 .long .L158-.L125 .long .L157-.L125 .long .L156-.L125 .long .L155-.L125 .long .L154-.L125 .long .L153-.L125 .long .L152-.L125 .long .L151-.L125 .long .L150-.L125 .long .L149-.L125 .long .L148-.L125 .long .L147-.L125 .long .L146-.L125 .long .L145-.L125 .long .L144-.L125 .long .L143-.L125 .long .L142-.L125 .long .L141-.L125 .long .L140-.L125 .long .L139-.L125 .long .L138-.L125 .long .L137-.L125 .long .L136-.L125 .long .L135-.L125 .long .L134-.L125 .long .L133-.L125 .long .L132-.L125 .long .L131-.L125 .long .L130-.L125 .long .L129-.L125 .long .L128-.L125 .long .L127-.L125 .long .L126-.L125 .long .L124-.L125 .section .text._ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category23default_error_conditionEi,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category23default_error_conditionEi,comdat .L202: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L284 .L203: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx .L204: movl %ebx, %eax popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L284: .cfi_restore_state leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L203 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L203 .L201: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L285 .L205: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L285: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L205 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L205 .L200: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L286 .L206: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L286: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L206 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L206 .L199: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L287 .L207: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L287: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L207 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L207 .L158: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L288 .L208: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L288: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L208 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L208 .L157: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L289 .L209: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L289: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L209 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L209 .L156: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L290 .L210: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L290: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L210 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L210 .L155: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L291 .L211: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L291: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L211 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L211 .L198: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L292 .L212: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L292: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L212 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L212 .L154: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L293 .L213: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L293: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L213 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L213 .L197: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L294 .L214: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L294: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L214 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L214 .L196: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L295 .L215: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L295: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L215 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L215 .L195: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L296 .L216: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L296: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L216 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L216 .L194: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L297 .L217: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L297: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L217 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L217 .L153: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L298 .L218: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L298: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L218 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L218 .L193: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L299 .L219: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L299: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L219 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L219 .L152: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L300 .L220: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L300: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L220 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L220 .L151: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L301 .L221: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L301: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L221 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L221 .L150: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L302 .L222: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L302: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L222 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L222 .L149: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L303 .L223: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L303: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L223 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L223 .L148: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L304 .L224: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L304: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L224 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L224 .L147: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L305 .L225: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L305: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L225 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L225 .L162: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L306 .L226: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L306: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L226 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L226 .L192: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L307 .L227: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L307: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L227 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L227 .L191: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L308 .L228: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L308: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L228 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L228 .L159: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L309 .L229: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L309: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L229 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L229 .L146: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L310 .L230: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L310: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L230 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L230 .L145: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L311 .L231: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L311: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L231 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L231 .L161: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L312 .L232: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L312: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L232 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L232 .L144: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L313 .L233: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L313: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L233 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L233 .L143: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L314 .L234: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L314: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L234 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L234 .L142: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L315 .L235: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L315: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L235 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L235 .L190: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L316 .L236: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L316: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L236 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L236 .L189: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L317 .L237: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L317: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L237 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L237 .L188: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L318 .L238: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L318: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L238 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L238 .L187: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L319 .L239: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L319: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L239 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L239 .L186: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L320 .L240: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L320: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L240 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L240 .L141: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L321 .L241: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L321: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L241 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L241 .L185: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L322 .L242: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L322: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L242 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L242 .L140: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L323 .L243: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L323: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L243 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L243 .L184: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L324 .L244: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L324: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L244 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L244 .L183: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L325 .L245: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L325: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L245 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L245 .L182: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L326 .L246: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L326: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L246 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L246 .L139: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L327 .L247: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L327: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L247 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L247 .L181: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L328 .L248: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L328: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L248 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L248 .L138: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L329 .L249: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L329: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L249 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L249 .L137: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L330 .L250: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L330: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L250 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L250 .L136: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L331 .L251: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L331: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L251 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L251 .L135: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L332 .L252: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L332: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L252 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L252 .L134: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L333 .L253: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L333: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L253 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L253 .L180: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L334 .L254: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L334: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L254 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L254 .L179: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L335 .L255: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L335: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L255 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L255 .L178: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L336 .L256: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L336: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L256 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L256 .L133: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L337 .L257: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L337: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L257 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L257 .L177: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L338 .L258: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L338: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L258 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L258 .L176: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L339 .L259: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L339: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L259 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L259 .L175: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L340 .L260: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L340: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L260 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L260 .L132: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L341 .L261: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L341: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L261 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L261 .L174: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L342 .L262: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L342: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L262 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L262 .L173: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L343 .L263: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L343: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L263 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L263 .L172: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L344 .L264: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L344: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L264 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L264 .L131: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L345 .L265: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L345: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L265 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L265 .L171: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L346 .L266: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L346: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L266 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L266 .L170: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L347 .L267: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L347: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L267 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L267 .L130: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L348 .L268: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L348: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L268 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L268 .L129: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L349 .L269: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L349: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L269 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L269 .L128: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L350 .L270: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L350: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L270 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L270 .L160: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L351 .L271: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L351: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L271 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L271 .L169: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L352 .L272: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L352: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L272 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L272 .L168: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L353 .L273: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L353: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L273 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L273 .L167: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L354 .L274: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L354: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L274 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L274 .L166: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L355 .L275: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L355: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L275 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L275 .L127: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L356 .L276: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L356: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L276 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L276 .L126: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L357 .L277: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L357: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L277 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L277 .L124: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L358 .L278: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L358: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L278 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L278 .L165: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L359 .L279: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L359: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L279 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L279 .L164: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L360 .L280: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L360: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L280 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L280 .L163: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .L361 .L281: leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdx jmp .L204 .L361: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L281 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L281 .L123: movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result(%rip), %eax testb %al, %al je .L362 .L282: leaq _ZZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result(%rip), %rdx jmp .L204 .L362: leaq _ZGVZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L282 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L282 .cfi_endproc .LFE8278: .size _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category23default_error_conditionEi, .-_ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category23default_error_conditionEi .section .rodata._ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc.str1.1,"aMS",@progbits,1 .LC5: .string "cudaError %d: %s" .section .text._ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc,"axG",@progbits,_ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc,comdat .weak _ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc .hidden _ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc .type _ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc, @function _ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc: .LFB6785: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA6785 endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $280, %rsp .cfi_def_cfa_offset 320 movl %edi, %ebp movq %rsi, %r12 movq %fs:40, %rax movq %rax, 264(%rsp) xorl %eax, %eax movl $16, %edi call __cxa_allocate_exception@PLT movq %rax, %rbx leaq 8(%rsp), %rdi movl $64, %ecx movl $0, %eax rep stosl leaq 8(%rsp), %r13 subq $8, %rsp .cfi_def_cfa_offset 328 pushq %r12 .cfi_def_cfa_offset 336 movl %ebp, %r9d leaq .LC5(%rip), %r8 movl $256, %ecx movl $2, %edx movl $256, %esi movq %r13, %rdi call __snprintf_chk@PLT addq $16, %rsp .cfi_def_cfa_offset 320 movq %r13, %rsi movq %rbx, %rdi call _ZNSt13runtime_errorC2EPKc@PLT leaq 16+_ZTVN4cuda3__410cuda_errorE(%rip), %rax movq %rax, (%rbx) movq 264(%rsp), %rax subq %fs:40, %rax je .L364 call __stack_chk_fail@PLT .L364: leaq _ZN4cuda3__410cuda_errorD1Ev(%rip), %rdx leaq _ZTIN4cuda3__410cuda_errorE(%rip), %rsi movq %rbx, %rdi .LEHB2: call __cxa_throw@PLT .LEHE2: .cfi_endproc .LFE6785: .section .gcc_except_table._ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc,"aG",@progbits,_ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc,comdat .LLSDA6785: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE6785-.LLSDACSB6785 .LLSDACSB6785: .uleb128 .LEHB2-.LFB6785 .uleb128 .LEHE2-.LEHB2 .uleb128 0 .uleb128 0 .LLSDACSE6785: .section .text._ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc,"axG",@progbits,_ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc,comdat .size _ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc, .-_ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc .section .rodata._ZN3cub17CUB_200700_800_NS10PtxVersionERi.str1.8,"aMS",@progbits,1 .align 8 .LC6: .string "Failed to query current device" .section .rodata._ZN3cub17CUB_200700_800_NS10PtxVersionERi.str1.1,"aMS",@progbits,1 .LC7: .string "Failed to set device" .section .text._ZN3cub17CUB_200700_800_NS10PtxVersionERi,"axG",@progbits,_ZN3cub17CUB_200700_800_NS10PtxVersionERi,comdat .weak _ZN3cub17CUB_200700_800_NS10PtxVersionERi .type _ZN3cub17CUB_200700_800_NS10PtxVersionERi, @function _ZN3cub17CUB_200700_800_NS10PtxVersionERi: .LFB7027: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA7027 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $200, %rsp .cfi_def_cfa_offset 256 movq %rdi, %rbx movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax movl $-1, 24(%rsp) leaq 24(%rsp), %rdi .LEHB3: call cudaGetDevice@PLT movl %eax, %ebp call cudaGetLastError@PLT testl %ebp, %ebp sete %dl testl %eax, %eax setne %al testb %al, %dl jne .L400 testl %ebp, %ebp jne .L400 movl 24(%rsp), %r14d jmp .L368 .L400: movl $-1, %r14d .L368: movzbl _ZGVZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache(%rip), %eax testb %al, %al je .L409 .L369: movzbl _ZGVZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count(%rip), %eax testb %al, %al je .L410 .L370: cmpl _ZZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count(%rip), %r14d jge .L373 testl %r14d, %r14d jns .L411 .L373: call cudaGetLastError@PLT .LEHE3: movl $101, %ebp .L367: movq 184(%rsp), %rax subq %fs:40, %rax jne .L412 movl %ebp, %eax addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L409: .cfi_restore_state leaq _ZGVZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L369 leaq _ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache(%rip), %rcx movq $0, _ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache(%rip) movq $0, 1528+_ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache(%rip) leaq 8(%rcx), %rdi andq $-8, %rdi subq %rdi, %rcx addl $1536, %ecx shrl $3, %ecx movl %ecx, %ecx movl $0, %eax rep stosq leaq _ZGVZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache(%rip), %rdi call __cxa_guard_release@PLT jmp .L369 .L410: leaq _ZGVZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L370 movl $-1, 24(%rsp) leaq 24(%rsp), %rdi .LEHB4: call cudaGetDeviceCount@PLT movl %eax, %ebp call cudaGetLastError@PLT .LEHE4: testl %ebp, %ebp sete %dl testl %eax, %eax setne %al testb %al, %dl jne .L403 testl %ebp, %ebp je .L371 .L403: movl $-1, 24(%rsp) .L371: movl 24(%rsp), %eax movl %eax, _ZZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count(%rip) leaq _ZGVZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count(%rip), %rdi call __cxa_guard_release@PLT jmp .L370 .L401: endbr64 movq %rax, %rbx leaq _ZGVZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count(%rip), %rdi call __cxa_guard_abort@PLT movq 184(%rsp), %rax subq %fs:40, %rax je .L376 call __stack_chk_fail@PLT .L376: movq %rbx, %rdi .LEHB5: call _Unwind_Resume@PLT .L411: movslq %r14d, %rbp leaq 0(%rbp,%rbp,2), %r13 salq $2, %r13 leaq _ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache(%rip), %r12 addq %r13, %r12 movl (%r12), %eax cmpl $2, %eax je .L377 movl $0, %eax movl $1, %edx lock cmpxchgl %edx, (%r12) jne .L378 movl %r14d, 24(%rsp) movl $0, 28(%rsp) leaq 28(%rsp), %rdi call cudaGetDevice@PLT .LEHE5: movl %eax, %r14d testl %eax, %eax jne .L413 movl 24(%rsp), %edi cmpl %edi, 28(%rsp) jne .L414 .L381: leaq 32(%rsp), %rdi leaq _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv(%rip), %rsi .LEHB6: call cudaFuncGetAttributes@PLT .LEHE6: jmp .L415 .L413: .LEHB7: call cudaGetLastError@PLT movq 184(%rsp), %rax subq %fs:40, %rax jne .L416 leaq .LC6(%rip), %rsi movl %r14d, %edi call _ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc .L416: call __stack_chk_fail@PLT .L414: call cudaSetDevice@PLT movl %eax, %r14d testl %eax, %eax je .L381 call cudaGetLastError@PLT movq 184(%rsp), %rax subq %fs:40, %rax jne .L417 leaq .LC7(%rip), %rsi movl %r14d, %edi call _ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc .LEHE7: .L417: call __stack_chk_fail@PLT .L415: movl %eax, %r14d .LEHB8: call cudaGetLastError@PLT .LEHE8: movl %eax, %r15d testl %r14d, %r14d jne .L404 testl %eax, %eax je .L404 leaq 0(%rbp,%rbp,2), %rax movl 64(%rsp), %edx leal (%rdx,%rdx,4), %edx addl %edx, %edx leaq _ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache(%rip), %rcx movl %edx, 4(%rcx,%rax,4) movl 28(%rsp), %edi cmpl 24(%rsp), %edi jne .L418 leaq 0(%rbp,%rbp,2), %rax leaq _ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache(%rip), %rdx movl %r15d, 8(%rdx,%rax,4) .L387: .LEHB9: call cudaGetLastError@PLT jmp .L388 .L404: leaq 0(%rbp,%rbp,2), %rax movl 64(%rsp), %edx leal (%rdx,%rdx,4), %edx addl %edx, %edx leaq _ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache(%rip), %rcx movl %edx, 4(%rcx,%rax,4) movl 28(%rsp), %edi cmpl 24(%rsp), %edi jne .L419 .L385: leaq 0(%rbp,%rbp,2), %rax leaq _ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache(%rip), %rdx movl %r14d, 8(%rdx,%rax,4) testl %r14d, %r14d jne .L387 .L388: movl $2, (%r12) .L377: leaq 0(%rbp,%rbp,2), %rdx leaq _ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache(%rip), %rax movl 4(%rax,%rdx,4), %r12d leaq 4(%rax), %rax movl 4(%rax,%r13), %ebp call cudaGetLastError@PLT .LEHE9: orl %ebp, %eax jne .L367 movl %r12d, (%rbx) jmp .L367 .L419: call cudaSetDevice@PLT movl %eax, 12(%rsp) testl %eax, %eax je .L385 jmp .L398 .L421: call __stack_chk_fail@PLT .L402: endbr64 movq %rax, %rbp movl 28(%rsp), %edi cmpl 24(%rsp), %edi je .L390 call cudaSetDevice@PLT movl %eax, %ebx testl %eax, %eax je .L390 call cudaGetLastError@PLT movq 184(%rsp), %rax subq %fs:40, %rax je .L391 call __stack_chk_fail@PLT .L391: leaq .LC7(%rip), %rsi movl %ebx, %edi call _ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc .L390: movq 184(%rsp), %rax subq %fs:40, %rax je .L392 call __stack_chk_fail@PLT .L392: movq %rbp, %rdi .LEHB10: call _Unwind_Resume@PLT .LEHE10: .L378: cmpl $1, %eax jne .L377 .L393: movl (%r12), %eax cmpl $2, %eax jne .L393 jmp .L377 .L420: leaq 0(%rbp,%rbp,2), %rax leaq _ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache(%rip), %rdx movl %r15d, 8(%rdx,%rax,4) jmp .L387 .L418: call cudaSetDevice@PLT movl %eax, 12(%rsp) testl %eax, %eax je .L420 .L398: call cudaGetLastError@PLT movq 184(%rsp), %rax subq %fs:40, %rax jne .L421 leaq .LC7(%rip), %rsi movl 12(%rsp), %edi call _ZN4cuda3__418__throw_cuda_errorE9cudaErrorPKc .L412: call __stack_chk_fail@PLT .cfi_endproc .LFE7027: .section .gcc_except_table._ZN3cub17CUB_200700_800_NS10PtxVersionERi,"aG",@progbits,_ZN3cub17CUB_200700_800_NS10PtxVersionERi,comdat .LLSDA7027: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE7027-.LLSDACSB7027 .LLSDACSB7027: .uleb128 .LEHB3-.LFB7027 .uleb128 .LEHE3-.LEHB3 .uleb128 0 .uleb128 0 .uleb128 .LEHB4-.LFB7027 .uleb128 .LEHE4-.LEHB4 .uleb128 .L401-.LFB7027 .uleb128 0 .uleb128 .LEHB5-.LFB7027 .uleb128 .LEHE5-.LEHB5 .uleb128 0 .uleb128 0 .uleb128 .LEHB6-.LFB7027 .uleb128 .LEHE6-.LEHB6 .uleb128 .L402-.LFB7027 .uleb128 0 .uleb128 .LEHB7-.LFB7027 .uleb128 .LEHE7-.LEHB7 .uleb128 0 .uleb128 0 .uleb128 .LEHB8-.LFB7027 .uleb128 .LEHE8-.LEHB8 .uleb128 .L402-.LFB7027 .uleb128 0 .uleb128 .LEHB9-.LFB7027 .uleb128 .LEHE9-.LEHB9 .uleb128 0 .uleb128 0 .uleb128 .LEHB10-.LFB7027 .uleb128 .LEHE10-.LEHB10 .uleb128 0 .uleb128 0 .LLSDACSE7027: .section .text._ZN3cub17CUB_200700_800_NS10PtxVersionERi,"axG",@progbits,_ZN3cub17CUB_200700_800_NS10PtxVersionERi,comdat .size _ZN3cub17CUB_200700_800_NS10PtxVersionERi, .-_ZN3cub17CUB_200700_800_NS10PtxVersionERi .section .text._ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv,comdat .weak _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv .type _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv, @function _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv: .LFB8339: .cfi_startproc endbr64 movzbl _ZGVZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result(%rip), %eax testb %al, %al je .L428 leaq _ZZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result(%rip), %rax ret .L428: subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZGVZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax jne .L429 .L423: leaq _ZZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result(%rip), %rax addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L429: .cfi_restore_state leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result(%rip), %rdi call __cxa_guard_release@PLT jmp .L423 .cfi_endproc .LFE8339: .size _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv, .-_ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv .section .rodata._ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE13do_deallocateESB_mm.str1.1,"aMS",@progbits,1 .LC8: .string "CUDA free failed" .section .text._ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE13do_deallocateESB_mm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE13do_deallocateESB_mm,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE13do_deallocateESB_mm .type _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE13do_deallocateESB_mm, @function _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE13do_deallocateESB_mm: .LFB13364: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13364 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rsi, %rdi .LEHB11: call cudaFree@PLT testl %eax, %eax jne .L435 popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L435: .cfi_restore_state movl %eax, %ebx call cudaGetLastError@PLT .LEHE11: movl $64, %edi call __cxa_allocate_exception@PLT movq %rax, %rbp call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %r12 leaq .LC8(%rip), %rsi movq %rbp, %rdi .LEHB12: call _ZNSt13runtime_errorC2EPKc@PLT .LEHE12: leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, 0(%rbp) movl %ebx, 16(%rbp) movq %r12, 24(%rbp) leaq 48(%rbp), %rax movq %rax, 32(%rbp) movq $0, 40(%rbp) movb $0, 48(%rbp) leaq _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rsi movq %rbp, %rdi .LEHB13: call __cxa_throw@PLT .L433: endbr64 movq %rax, %rbx movq %rbp, %rdi call __cxa_free_exception@PLT movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE13: .cfi_endproc .LFE13364: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE13do_deallocateESB_mm,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE13do_deallocateESB_mm,comdat .LLSDA13364: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13364-.LLSDACSB13364 .LLSDACSB13364: .uleb128 .LEHB11-.LFB13364 .uleb128 .LEHE11-.LEHB11 .uleb128 0 .uleb128 0 .uleb128 .LEHB12-.LFB13364 .uleb128 .LEHE12-.LEHB12 .uleb128 .L433-.LFB13364 .uleb128 0 .uleb128 .LEHB13-.LFB13364 .uleb128 .LEHE13-.LEHB13 .uleb128 0 .uleb128 0 .LLSDACSE13364: .section .text._ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE13do_deallocateESB_mm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE13do_deallocateESB_mm,comdat .size _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE13do_deallocateESB_mm, .-_ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE13do_deallocateESB_mm .section .text._ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE13do_deallocateENS0_10device_ptrIvEEmm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE13do_deallocateENS0_10device_ptrIvEEmm,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE13do_deallocateENS0_10device_ptrIvEEmm .type _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE13do_deallocateENS0_10device_ptrIvEEmm, @function _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE13do_deallocateENS0_10device_ptrIvEEmm: .LFB13299: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13299 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rsi, %rdi .LEHB14: call cudaFree@PLT testl %eax, %eax jne .L441 popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L441: .cfi_restore_state movl %eax, %ebx call cudaGetLastError@PLT .LEHE14: movl $64, %edi call __cxa_allocate_exception@PLT movq %rax, %rbp call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %r12 leaq .LC8(%rip), %rsi movq %rbp, %rdi .LEHB15: call _ZNSt13runtime_errorC2EPKc@PLT .LEHE15: leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, 0(%rbp) movl %ebx, 16(%rbp) movq %r12, 24(%rbp) leaq 48(%rbp), %rax movq %rax, 32(%rbp) movq $0, 40(%rbp) movb $0, 48(%rbp) leaq _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rsi movq %rbp, %rdi .LEHB16: call __cxa_throw@PLT .L439: endbr64 movq %rax, %rbx movq %rbp, %rdi call __cxa_free_exception@PLT movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE16: .cfi_endproc .LFE13299: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE13do_deallocateENS0_10device_ptrIvEEmm,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE13do_deallocateENS0_10device_ptrIvEEmm,comdat .LLSDA13299: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13299-.LLSDACSB13299 .LLSDACSB13299: .uleb128 .LEHB14-.LFB13299 .uleb128 .LEHE14-.LEHB14 .uleb128 0 .uleb128 0 .uleb128 .LEHB15-.LFB13299 .uleb128 .LEHE15-.LEHB15 .uleb128 .L439-.LFB13299 .uleb128 0 .uleb128 .LEHB16-.LFB13299 .uleb128 .LEHE16-.LEHB16 .uleb128 0 .uleb128 0 .LLSDACSE13299: .section .text._ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE13do_deallocateENS0_10device_ptrIvEEmm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE13do_deallocateENS0_10device_ptrIvEEmm,comdat .size _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE13do_deallocateENS0_10device_ptrIvEEmm, .-_ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE13do_deallocateENS0_10device_ptrIvEEmm .section .text.nvtxSetInitFunctionsToNoops_v3,"axG",@progbits,nvtxSetInitFunctionsToNoops_v3,comdat .weak nvtxSetInitFunctionsToNoops_v3 .hidden nvtxSetInitFunctionsToNoops_v3 .type nvtxSetInitFunctionsToNoops_v3, @function nvtxSetInitFunctionsToNoops_v3: .LFB8571: .cfi_startproc endbr64 testl %edi, %edi setne %al leaq nvtxMarkEx_impl_init_v3(%rip), %rdx cmpq %rdx, 48+nvtxGlobals_v3(%rip) je .L571 testb %al, %al je .L443 .L571: movq $0, 48+nvtxGlobals_v3(%rip) .L443: leaq nvtxMarkA_impl_init_v3(%rip), %rdx cmpq %rdx, 56+nvtxGlobals_v3(%rip) je .L572 testb %al, %al je .L445 .L572: movq $0, 56+nvtxGlobals_v3(%rip) .L445: leaq nvtxMarkW_impl_init_v3(%rip), %rdx cmpq %rdx, 64+nvtxGlobals_v3(%rip) je .L573 testb %al, %al je .L447 .L573: movq $0, 64+nvtxGlobals_v3(%rip) .L447: leaq nvtxRangeStartEx_impl_init_v3(%rip), %rdx cmpq %rdx, 72+nvtxGlobals_v3(%rip) je .L574 testb %al, %al je .L449 .L574: movq $0, 72+nvtxGlobals_v3(%rip) .L449: leaq nvtxRangeStartA_impl_init_v3(%rip), %rdx cmpq %rdx, 80+nvtxGlobals_v3(%rip) je .L575 testb %al, %al je .L451 .L575: movq $0, 80+nvtxGlobals_v3(%rip) .L451: leaq nvtxRangeStartW_impl_init_v3(%rip), %rdx cmpq %rdx, 88+nvtxGlobals_v3(%rip) je .L576 testb %al, %al je .L453 .L576: movq $0, 88+nvtxGlobals_v3(%rip) .L453: leaq nvtxRangeEnd_impl_init_v3(%rip), %rdx cmpq %rdx, 96+nvtxGlobals_v3(%rip) je .L577 testb %al, %al je .L455 .L577: movq $0, 96+nvtxGlobals_v3(%rip) .L455: leaq nvtxRangePushEx_impl_init_v3(%rip), %rdx cmpq %rdx, 104+nvtxGlobals_v3(%rip) je .L578 testb %al, %al je .L457 .L578: movq $0, 104+nvtxGlobals_v3(%rip) .L457: leaq nvtxRangePushA_impl_init_v3(%rip), %rdx cmpq %rdx, 112+nvtxGlobals_v3(%rip) je .L579 testb %al, %al je .L459 .L579: movq $0, 112+nvtxGlobals_v3(%rip) .L459: leaq nvtxRangePushW_impl_init_v3(%rip), %rdx cmpq %rdx, 120+nvtxGlobals_v3(%rip) je .L580 testb %al, %al je .L461 .L580: movq $0, 120+nvtxGlobals_v3(%rip) .L461: leaq nvtxRangePop_impl_init_v3(%rip), %rdx cmpq %rdx, 128+nvtxGlobals_v3(%rip) je .L581 testb %al, %al je .L463 .L581: movq $0, 128+nvtxGlobals_v3(%rip) .L463: leaq nvtxNameCategoryA_impl_init_v3(%rip), %rdx cmpq %rdx, 136+nvtxGlobals_v3(%rip) je .L582 testb %al, %al je .L465 .L582: movq $0, 136+nvtxGlobals_v3(%rip) .L465: leaq nvtxNameCategoryW_impl_init_v3(%rip), %rdx cmpq %rdx, 144+nvtxGlobals_v3(%rip) je .L583 testb %al, %al je .L467 .L583: movq $0, 144+nvtxGlobals_v3(%rip) .L467: leaq nvtxNameOsThreadA_impl_init_v3(%rip), %rdx cmpq %rdx, 152+nvtxGlobals_v3(%rip) je .L584 testb %al, %al je .L469 .L584: movq $0, 152+nvtxGlobals_v3(%rip) .L469: leaq nvtxNameOsThreadW_impl_init_v3(%rip), %rdx cmpq %rdx, 160+nvtxGlobals_v3(%rip) je .L585 testb %al, %al je .L471 .L585: movq $0, 160+nvtxGlobals_v3(%rip) .L471: leaq nvtxNameCuDeviceA_impl_init_v3(%rip), %rdx cmpq %rdx, 168+nvtxGlobals_v3(%rip) je .L586 testb %al, %al je .L473 .L586: movq $0, 168+nvtxGlobals_v3(%rip) .L473: leaq nvtxNameCuDeviceW_impl_init_v3(%rip), %rdx cmpq %rdx, 176+nvtxGlobals_v3(%rip) je .L587 testb %al, %al je .L475 .L587: movq $0, 176+nvtxGlobals_v3(%rip) .L475: leaq nvtxNameCuContextA_impl_init_v3(%rip), %rdx cmpq %rdx, 184+nvtxGlobals_v3(%rip) je .L588 testb %al, %al je .L477 .L588: movq $0, 184+nvtxGlobals_v3(%rip) .L477: leaq nvtxNameCuContextW_impl_init_v3(%rip), %rdx cmpq %rdx, 192+nvtxGlobals_v3(%rip) je .L589 testb %al, %al je .L479 .L589: movq $0, 192+nvtxGlobals_v3(%rip) .L479: leaq nvtxNameCuStreamA_impl_init_v3(%rip), %rdx cmpq %rdx, 200+nvtxGlobals_v3(%rip) je .L590 testb %al, %al je .L481 .L590: movq $0, 200+nvtxGlobals_v3(%rip) .L481: leaq nvtxNameCuStreamW_impl_init_v3(%rip), %rdx cmpq %rdx, 208+nvtxGlobals_v3(%rip) je .L591 testb %al, %al je .L483 .L591: movq $0, 208+nvtxGlobals_v3(%rip) .L483: leaq nvtxNameCuEventA_impl_init_v3(%rip), %rdx cmpq %rdx, 216+nvtxGlobals_v3(%rip) je .L592 testb %al, %al je .L485 .L592: movq $0, 216+nvtxGlobals_v3(%rip) .L485: leaq nvtxNameCuEventW_impl_init_v3(%rip), %rdx cmpq %rdx, 224+nvtxGlobals_v3(%rip) je .L593 testb %al, %al je .L487 .L593: movq $0, 224+nvtxGlobals_v3(%rip) .L487: leaq nvtxNameClDeviceA_impl_init_v3(%rip), %rdx cmpq %rdx, 232+nvtxGlobals_v3(%rip) je .L594 testb %al, %al je .L489 .L594: movq $0, 232+nvtxGlobals_v3(%rip) .L489: leaq nvtxNameClDeviceW_impl_init_v3(%rip), %rdx cmpq %rdx, 240+nvtxGlobals_v3(%rip) je .L595 testb %al, %al je .L491 .L595: movq $0, 240+nvtxGlobals_v3(%rip) .L491: leaq nvtxNameClContextA_impl_init_v3(%rip), %rdx cmpq %rdx, 248+nvtxGlobals_v3(%rip) je .L596 testb %al, %al je .L493 .L596: movq $0, 248+nvtxGlobals_v3(%rip) .L493: leaq nvtxNameClContextW_impl_init_v3(%rip), %rdx cmpq %rdx, 256+nvtxGlobals_v3(%rip) je .L597 testb %al, %al je .L495 .L597: movq $0, 256+nvtxGlobals_v3(%rip) .L495: leaq nvtxNameClCommandQueueA_impl_init_v3(%rip), %rdx cmpq %rdx, 264+nvtxGlobals_v3(%rip) je .L598 testb %al, %al je .L497 .L598: movq $0, 264+nvtxGlobals_v3(%rip) .L497: leaq nvtxNameClCommandQueueW_impl_init_v3(%rip), %rdx cmpq %rdx, 272+nvtxGlobals_v3(%rip) je .L599 testb %al, %al je .L499 .L599: movq $0, 272+nvtxGlobals_v3(%rip) .L499: leaq nvtxNameClMemObjectA_impl_init_v3(%rip), %rdx cmpq %rdx, 280+nvtxGlobals_v3(%rip) je .L600 testb %al, %al je .L501 .L600: movq $0, 280+nvtxGlobals_v3(%rip) .L501: leaq nvtxNameClMemObjectW_impl_init_v3(%rip), %rdx cmpq %rdx, 288+nvtxGlobals_v3(%rip) je .L601 testb %al, %al je .L503 .L601: movq $0, 288+nvtxGlobals_v3(%rip) .L503: leaq nvtxNameClSamplerA_impl_init_v3(%rip), %rdx cmpq %rdx, 296+nvtxGlobals_v3(%rip) je .L602 testb %al, %al je .L505 .L602: movq $0, 296+nvtxGlobals_v3(%rip) .L505: leaq nvtxNameClSamplerW_impl_init_v3(%rip), %rdx cmpq %rdx, 304+nvtxGlobals_v3(%rip) je .L603 testb %al, %al je .L507 .L603: movq $0, 304+nvtxGlobals_v3(%rip) .L507: leaq nvtxNameClProgramA_impl_init_v3(%rip), %rdx cmpq %rdx, 312+nvtxGlobals_v3(%rip) je .L604 testb %al, %al je .L509 .L604: movq $0, 312+nvtxGlobals_v3(%rip) .L509: leaq nvtxNameClProgramW_impl_init_v3(%rip), %rdx cmpq %rdx, 320+nvtxGlobals_v3(%rip) je .L605 testb %al, %al je .L511 .L605: movq $0, 320+nvtxGlobals_v3(%rip) .L511: leaq nvtxNameClEventA_impl_init_v3(%rip), %rdx cmpq %rdx, 328+nvtxGlobals_v3(%rip) je .L606 testb %al, %al je .L513 .L606: movq $0, 328+nvtxGlobals_v3(%rip) .L513: leaq nvtxNameClEventW_impl_init_v3(%rip), %rdx cmpq %rdx, 336+nvtxGlobals_v3(%rip) je .L607 testb %al, %al je .L515 .L607: movq $0, 336+nvtxGlobals_v3(%rip) .L515: leaq nvtxNameCudaDeviceA_impl_init_v3(%rip), %rdx cmpq %rdx, 344+nvtxGlobals_v3(%rip) je .L608 testb %al, %al je .L517 .L608: movq $0, 344+nvtxGlobals_v3(%rip) .L517: leaq nvtxNameCudaDeviceW_impl_init_v3(%rip), %rdx cmpq %rdx, 352+nvtxGlobals_v3(%rip) je .L609 testb %al, %al je .L519 .L609: movq $0, 352+nvtxGlobals_v3(%rip) .L519: leaq nvtxNameCudaStreamA_impl_init_v3(%rip), %rdx cmpq %rdx, 360+nvtxGlobals_v3(%rip) je .L610 testb %al, %al je .L521 .L610: movq $0, 360+nvtxGlobals_v3(%rip) .L521: leaq nvtxNameCudaStreamW_impl_init_v3(%rip), %rdx cmpq %rdx, 368+nvtxGlobals_v3(%rip) je .L611 testb %al, %al je .L523 .L611: movq $0, 368+nvtxGlobals_v3(%rip) .L523: leaq nvtxNameCudaEventA_impl_init_v3(%rip), %rdx cmpq %rdx, 376+nvtxGlobals_v3(%rip) je .L612 testb %al, %al je .L525 .L612: movq $0, 376+nvtxGlobals_v3(%rip) .L525: leaq nvtxNameCudaEventW_impl_init_v3(%rip), %rdx cmpq %rdx, 384+nvtxGlobals_v3(%rip) je .L613 testb %al, %al je .L527 .L613: movq $0, 384+nvtxGlobals_v3(%rip) .L527: leaq nvtxDomainMarkEx_impl_init_v3(%rip), %rdx cmpq %rdx, 392+nvtxGlobals_v3(%rip) je .L614 testb %al, %al je .L529 .L614: movq $0, 392+nvtxGlobals_v3(%rip) .L529: leaq nvtxDomainRangeStartEx_impl_init_v3(%rip), %rdx cmpq %rdx, 400+nvtxGlobals_v3(%rip) je .L615 testb %al, %al je .L531 .L615: movq $0, 400+nvtxGlobals_v3(%rip) .L531: leaq nvtxDomainRangeEnd_impl_init_v3(%rip), %rdx cmpq %rdx, 408+nvtxGlobals_v3(%rip) je .L616 testb %al, %al je .L533 .L616: movq $0, 408+nvtxGlobals_v3(%rip) .L533: leaq nvtxDomainRangePushEx_impl_init_v3(%rip), %rdx cmpq %rdx, 416+nvtxGlobals_v3(%rip) je .L617 testb %al, %al je .L535 .L617: movq $0, 416+nvtxGlobals_v3(%rip) .L535: leaq nvtxDomainRangePop_impl_init_v3(%rip), %rdx cmpq %rdx, 424+nvtxGlobals_v3(%rip) je .L618 testb %al, %al je .L537 .L618: movq $0, 424+nvtxGlobals_v3(%rip) .L537: leaq nvtxDomainResourceCreate_impl_init_v3(%rip), %rdx cmpq %rdx, 432+nvtxGlobals_v3(%rip) je .L619 testb %al, %al je .L539 .L619: movq $0, 432+nvtxGlobals_v3(%rip) .L539: leaq nvtxDomainResourceDestroy_impl_init_v3(%rip), %rdx cmpq %rdx, 440+nvtxGlobals_v3(%rip) je .L620 testb %al, %al je .L541 .L620: movq $0, 440+nvtxGlobals_v3(%rip) .L541: leaq nvtxDomainNameCategoryA_impl_init_v3(%rip), %rdx cmpq %rdx, 448+nvtxGlobals_v3(%rip) je .L621 testb %al, %al je .L543 .L621: movq $0, 448+nvtxGlobals_v3(%rip) .L543: leaq nvtxDomainNameCategoryW_impl_init_v3(%rip), %rdx cmpq %rdx, 456+nvtxGlobals_v3(%rip) je .L622 testb %al, %al je .L545 .L622: movq $0, 456+nvtxGlobals_v3(%rip) .L545: leaq nvtxDomainRegisterStringA_impl_init_v3(%rip), %rdx cmpq %rdx, 464+nvtxGlobals_v3(%rip) je .L623 testb %al, %al je .L547 .L623: movq $0, 464+nvtxGlobals_v3(%rip) .L547: leaq nvtxDomainRegisterStringW_impl_init_v3(%rip), %rdx cmpq %rdx, 472+nvtxGlobals_v3(%rip) je .L624 testb %al, %al je .L549 .L624: movq $0, 472+nvtxGlobals_v3(%rip) .L549: leaq nvtxDomainCreateA_impl_init_v3(%rip), %rdx cmpq %rdx, 480+nvtxGlobals_v3(%rip) je .L625 testb %al, %al je .L551 .L625: movq $0, 480+nvtxGlobals_v3(%rip) .L551: leaq nvtxDomainCreateW_impl_init_v3(%rip), %rdx cmpq %rdx, 488+nvtxGlobals_v3(%rip) je .L626 testb %al, %al je .L553 .L626: movq $0, 488+nvtxGlobals_v3(%rip) .L553: leaq nvtxDomainDestroy_impl_init_v3(%rip), %rdx cmpq %rdx, 496+nvtxGlobals_v3(%rip) je .L627 testb %al, %al je .L555 .L627: movq $0, 496+nvtxGlobals_v3(%rip) .L555: leaq nvtxInitialize_impl_init_v3(%rip), %rdx cmpq %rdx, 504+nvtxGlobals_v3(%rip) je .L628 testb %al, %al je .L557 .L628: movq $0, 504+nvtxGlobals_v3(%rip) .L557: leaq nvtxDomainSyncUserCreate_impl_init_v3(%rip), %rdx cmpq %rdx, 512+nvtxGlobals_v3(%rip) je .L629 testb %al, %al je .L559 .L629: movq $0, 512+nvtxGlobals_v3(%rip) .L559: leaq nvtxDomainSyncUserDestroy_impl_init_v3(%rip), %rdx cmpq %rdx, 520+nvtxGlobals_v3(%rip) je .L630 testb %al, %al je .L561 .L630: movq $0, 520+nvtxGlobals_v3(%rip) .L561: leaq nvtxDomainSyncUserAcquireStart_impl_init_v3(%rip), %rdx cmpq %rdx, 528+nvtxGlobals_v3(%rip) je .L631 testb %al, %al je .L563 .L631: movq $0, 528+nvtxGlobals_v3(%rip) .L563: leaq nvtxDomainSyncUserAcquireFailed_impl_init_v3(%rip), %rdx cmpq %rdx, 536+nvtxGlobals_v3(%rip) je .L632 testb %al, %al je .L565 .L632: movq $0, 536+nvtxGlobals_v3(%rip) .L565: leaq nvtxDomainSyncUserAcquireSuccess_impl_init_v3(%rip), %rdx cmpq %rdx, 544+nvtxGlobals_v3(%rip) je .L633 testb %al, %al je .L567 .L633: movq $0, 544+nvtxGlobals_v3(%rip) .L567: leaq nvtxDomainSyncUserReleasing_impl_init_v3(%rip), %rdx cmpq %rdx, 552+nvtxGlobals_v3(%rip) je .L634 testb %al, %al je .L442 .L634: movq $0, 552+nvtxGlobals_v3(%rip) .L442: ret .cfi_endproc .LFE8571: .size nvtxSetInitFunctionsToNoops_v3, .-nvtxSetInitFunctionsToNoops_v3 .section .rodata.nvtxDomainNameCategoryW_impl_init_v3.str1.1,"aMS",@progbits,1 .LC9: .string "NVTX_INJECTION64_PATH" .LC10: .string "InitializeInjectionNvtx2" .section .text.nvtxDomainNameCategoryW_impl_init_v3,"axG",@progbits,nvtxDomainNameCategoryW_impl_init_v3,comdat .weak nvtxDomainNameCategoryW_impl_init_v3 .hidden nvtxDomainNameCategoryW_impl_init_v3 .type nvtxDomainNameCategoryW_impl_init_v3, @function nvtxDomainNameCategoryW_impl_init_v3: .LFB8530: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $8, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbx movl %esi, %ebp movq %rdx, %r12 movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L636 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L637 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L638 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r13 testq %rax, %rax je .L644 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L649 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L643 movl $0, %eax jmp .L639 .L649: movq %r13, %rdi call dlclose@PLT movl $5, %eax jmp .L639 .L638: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L645 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L639: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L636: movq 456+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L635 movq %r12, %rdx movl %ebp, %esi movq %rbx, %rdi call *%rax .L635: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L643: .cfi_restore_state movq %r13, %rdi call dlclose@PLT movl $6, %eax jmp .L639 .L644: movl $4, %eax jmp .L639 .L645: movl $7, %eax jmp .L639 .L637: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L636 .L641: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L641 jmp .L636 .cfi_endproc .LFE8530: .size nvtxDomainNameCategoryW_impl_init_v3, .-nvtxDomainNameCategoryW_impl_init_v3 .section .text.nvtxRangePop_impl_init_v3,"axG",@progbits,nvtxRangePop_impl_init_v3,comdat .weak nvtxRangePop_impl_init_v3 .hidden nvtxRangePop_impl_init_v3 .type nvtxRangePop_impl_init_v3, @function nvtxRangePop_impl_init_v3: .LFB8517: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L651 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L652 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L653 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbx testq %rax, %rax je .L659 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L665 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L658 movl $0, %eax jmp .L654 .L665: movq %rbx, %rdi call dlclose@PLT movl $5, %eax jmp .L654 .L653: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L660 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L654: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L651: movq 128+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L662 call *%rax .L650: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L658: .cfi_restore_state movq %rbx, %rdi call dlclose@PLT movl $6, %eax jmp .L654 .L659: movl $4, %eax jmp .L654 .L660: movl $7, %eax jmp .L654 .L652: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L651 .L656: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L656 jmp .L651 .L662: movl $-2, %eax jmp .L650 .cfi_endproc .LFE8517: .size nvtxRangePop_impl_init_v3, .-nvtxRangePop_impl_init_v3 .section .text.nvtxMarkW_impl_init_v3,"axG",@progbits,nvtxMarkW_impl_init_v3,comdat .weak nvtxMarkW_impl_init_v3 .hidden nvtxMarkW_impl_init_v3 .type nvtxMarkW_impl_init_v3, @function nvtxMarkW_impl_init_v3: .LFB8509: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L667 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L668 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L669 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L675 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L680 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L674 movl $0, %eax jmp .L670 .L680: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L670 .L669: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L676 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L670: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L667: movq 64+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L666 movq %rbx, %rdi call *%rax .L666: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L674: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L670 .L675: movl $4, %eax jmp .L670 .L676: movl $7, %eax jmp .L670 .L668: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L667 .L672: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L672 jmp .L667 .cfi_endproc .LFE8509: .size nvtxMarkW_impl_init_v3, .-nvtxMarkW_impl_init_v3 .section .text.nvtxMarkEx_impl_init_v3,"axG",@progbits,nvtxMarkEx_impl_init_v3,comdat .weak nvtxMarkEx_impl_init_v3 .hidden nvtxMarkEx_impl_init_v3 .type nvtxMarkEx_impl_init_v3, @function nvtxMarkEx_impl_init_v3: .LFB8507: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L682 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L683 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L684 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L690 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L695 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L689 movl $0, %eax jmp .L685 .L695: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L685 .L684: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L691 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L685: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L682: movq 48+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L681 movq %rbx, %rdi call *%rax .L681: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L689: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L685 .L690: movl $4, %eax jmp .L685 .L691: movl $7, %eax jmp .L685 .L683: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L682 .L687: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L687 jmp .L682 .cfi_endproc .LFE8507: .size nvtxMarkEx_impl_init_v3, .-nvtxMarkEx_impl_init_v3 .section .text.nvtxDomainSyncUserReleasing_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserReleasing_impl_init_v3,comdat .weak nvtxDomainSyncUserReleasing_impl_init_v3 .hidden nvtxDomainSyncUserReleasing_impl_init_v3 .type nvtxDomainSyncUserReleasing_impl_init_v3, @function nvtxDomainSyncUserReleasing_impl_init_v3: .LFB8570: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L697 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L698 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L699 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L705 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L710 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L704 movl $0, %eax jmp .L700 .L710: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L700 .L699: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L706 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L700: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L697: movq 552+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L696 movq %rbx, %rdi call *%rax .L696: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L704: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L700 .L705: movl $4, %eax jmp .L700 .L706: movl $7, %eax jmp .L700 .L698: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L697 .L702: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L702 jmp .L697 .cfi_endproc .LFE8570: .size nvtxDomainSyncUserReleasing_impl_init_v3, .-nvtxDomainSyncUserReleasing_impl_init_v3 .section .text.nvtxDomainSyncUserDestroy_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserDestroy_impl_init_v3,comdat .weak nvtxDomainSyncUserDestroy_impl_init_v3 .hidden nvtxDomainSyncUserDestroy_impl_init_v3 .type nvtxDomainSyncUserDestroy_impl_init_v3, @function nvtxDomainSyncUserDestroy_impl_init_v3: .LFB8566: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L712 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L713 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L714 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L720 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L725 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L719 movl $0, %eax jmp .L715 .L725: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L715 .L714: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L721 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L715: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L712: movq 520+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L711 movq %rbx, %rdi call *%rax .L711: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L719: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L715 .L720: movl $4, %eax jmp .L715 .L721: movl $7, %eax jmp .L715 .L713: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L712 .L717: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L717 jmp .L712 .cfi_endproc .LFE8566: .size nvtxDomainSyncUserDestroy_impl_init_v3, .-nvtxDomainSyncUserDestroy_impl_init_v3 .section .text.nvtxDomainDestroy_impl_init_v3,"axG",@progbits,nvtxDomainDestroy_impl_init_v3,comdat .weak nvtxDomainDestroy_impl_init_v3 .hidden nvtxDomainDestroy_impl_init_v3 .type nvtxDomainDestroy_impl_init_v3, @function nvtxDomainDestroy_impl_init_v3: .LFB8535: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L727 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L728 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L729 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L735 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L740 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L734 movl $0, %eax jmp .L730 .L740: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L730 .L729: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L736 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L730: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L727: movq 496+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L726 movq %rbx, %rdi call *%rax .L726: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L734: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L730 .L735: movl $4, %eax jmp .L730 .L736: movl $7, %eax jmp .L730 .L728: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L727 .L732: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L732 jmp .L727 .cfi_endproc .LFE8535: .size nvtxDomainDestroy_impl_init_v3, .-nvtxDomainDestroy_impl_init_v3 .section .text.nvtxDomainResourceDestroy_impl_init_v3,"axG",@progbits,nvtxDomainResourceDestroy_impl_init_v3,comdat .weak nvtxDomainResourceDestroy_impl_init_v3 .hidden nvtxDomainResourceDestroy_impl_init_v3 .type nvtxDomainResourceDestroy_impl_init_v3, @function nvtxDomainResourceDestroy_impl_init_v3: .LFB8528: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L742 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L743 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L744 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L750 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L755 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L749 movl $0, %eax jmp .L745 .L755: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L745 .L744: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L751 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L745: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L742: movq 440+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L741 movq %rbx, %rdi call *%rax .L741: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L749: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L745 .L750: movl $4, %eax jmp .L745 .L751: movl $7, %eax jmp .L745 .L743: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L742 .L747: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L747 jmp .L742 .cfi_endproc .LFE8528: .size nvtxDomainResourceDestroy_impl_init_v3, .-nvtxDomainResourceDestroy_impl_init_v3 .section .text.nvtxInitialize_impl_init_v3,"axG",@progbits,nvtxInitialize_impl_init_v3,comdat .weak nvtxInitialize_impl_init_v3 .hidden nvtxInitialize_impl_init_v3 .type nvtxInitialize_impl_init_v3, @function nvtxInitialize_impl_init_v3: .LFB8536: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L757 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L758 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L759 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L765 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L770 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L764 movl $0, %eax jmp .L760 .L770: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L760 .L759: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L766 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L760: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L757: movq 504+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L756 movq %rbx, %rdi call *%rax .L756: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L764: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L760 .L765: movl $4, %eax jmp .L760 .L766: movl $7, %eax jmp .L760 .L758: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L757 .L762: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L762 jmp .L757 .cfi_endproc .LFE8536: .size nvtxInitialize_impl_init_v3, .-nvtxInitialize_impl_init_v3 .section .text.nvtxMarkA_impl_init_v3,"axG",@progbits,nvtxMarkA_impl_init_v3,comdat .weak nvtxMarkA_impl_init_v3 .hidden nvtxMarkA_impl_init_v3 .type nvtxMarkA_impl_init_v3, @function nvtxMarkA_impl_init_v3: .LFB8508: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L772 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L773 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L774 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L780 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L785 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L779 movl $0, %eax jmp .L775 .L785: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L775 .L774: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L781 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L775: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L772: movq 56+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L771 movq %rbx, %rdi call *%rax .L771: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L779: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L775 .L780: movl $4, %eax jmp .L775 .L781: movl $7, %eax jmp .L775 .L773: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L772 .L777: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L777 jmp .L772 .cfi_endproc .LFE8508: .size nvtxMarkA_impl_init_v3, .-nvtxMarkA_impl_init_v3 .section .text.nvtxRangeEnd_impl_init_v3,"axG",@progbits,nvtxRangeEnd_impl_init_v3,comdat .weak nvtxRangeEnd_impl_init_v3 .hidden nvtxRangeEnd_impl_init_v3 .type nvtxRangeEnd_impl_init_v3, @function nvtxRangeEnd_impl_init_v3: .LFB8513: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L787 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L788 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L789 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L795 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L800 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L794 movl $0, %eax jmp .L790 .L800: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L790 .L789: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L796 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L790: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L787: movq 96+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L786 movq %rbx, %rdi call *%rax .L786: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L794: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L790 .L795: movl $4, %eax jmp .L790 .L796: movl $7, %eax jmp .L790 .L788: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L787 .L792: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L792 jmp .L787 .cfi_endproc .LFE8513: .size nvtxRangeEnd_impl_init_v3, .-nvtxRangeEnd_impl_init_v3 .section .text.nvtxDomainSyncUserAcquireSuccess_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireSuccess_impl_init_v3,comdat .weak nvtxDomainSyncUserAcquireSuccess_impl_init_v3 .hidden nvtxDomainSyncUserAcquireSuccess_impl_init_v3 .type nvtxDomainSyncUserAcquireSuccess_impl_init_v3, @function nvtxDomainSyncUserAcquireSuccess_impl_init_v3: .LFB8569: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L802 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L803 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L804 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L810 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L815 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L809 movl $0, %eax jmp .L805 .L815: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L805 .L804: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L811 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L805: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L802: movq 544+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L801 movq %rbx, %rdi call *%rax .L801: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L809: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L805 .L810: movl $4, %eax jmp .L805 .L811: movl $7, %eax jmp .L805 .L803: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L802 .L807: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L807 jmp .L802 .cfi_endproc .LFE8569: .size nvtxDomainSyncUserAcquireSuccess_impl_init_v3, .-nvtxDomainSyncUserAcquireSuccess_impl_init_v3 .section .text.nvtxDomainSyncUserAcquireFailed_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireFailed_impl_init_v3,comdat .weak nvtxDomainSyncUserAcquireFailed_impl_init_v3 .hidden nvtxDomainSyncUserAcquireFailed_impl_init_v3 .type nvtxDomainSyncUserAcquireFailed_impl_init_v3, @function nvtxDomainSyncUserAcquireFailed_impl_init_v3: .LFB8568: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L817 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L818 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L819 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L825 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L830 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L824 movl $0, %eax jmp .L820 .L830: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L820 .L819: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L826 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L820: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L817: movq 536+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L816 movq %rbx, %rdi call *%rax .L816: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L824: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L820 .L825: movl $4, %eax jmp .L820 .L826: movl $7, %eax jmp .L820 .L818: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L817 .L822: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L822 jmp .L817 .cfi_endproc .LFE8568: .size nvtxDomainSyncUserAcquireFailed_impl_init_v3, .-nvtxDomainSyncUserAcquireFailed_impl_init_v3 .section .text.nvtxDomainSyncUserAcquireStart_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireStart_impl_init_v3,comdat .weak nvtxDomainSyncUserAcquireStart_impl_init_v3 .hidden nvtxDomainSyncUserAcquireStart_impl_init_v3 .type nvtxDomainSyncUserAcquireStart_impl_init_v3, @function nvtxDomainSyncUserAcquireStart_impl_init_v3: .LFB8567: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L832 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L833 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L834 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L840 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L845 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L839 movl $0, %eax jmp .L835 .L845: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L835 .L834: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L841 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L835: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L832: movq 528+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L831 movq %rbx, %rdi call *%rax .L831: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L839: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L835 .L840: movl $4, %eax jmp .L835 .L841: movl $7, %eax jmp .L835 .L833: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L832 .L837: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L837 jmp .L832 .cfi_endproc .LFE8567: .size nvtxDomainSyncUserAcquireStart_impl_init_v3, .-nvtxDomainSyncUserAcquireStart_impl_init_v3 .section .text.nvtxDomainCreateA_impl_init_v3,"axG",@progbits,nvtxDomainCreateA_impl_init_v3,comdat .weak nvtxDomainCreateA_impl_init_v3 .hidden nvtxDomainCreateA_impl_init_v3 .type nvtxDomainCreateA_impl_init_v3, @function nvtxDomainCreateA_impl_init_v3: .LFB8533: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L847 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L848 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L849 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L855 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L861 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L854 movl $0, %eax jmp .L850 .L861: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L850 .L849: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L856 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L850: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L847: movq 480+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L858 movq %rbx, %rdi call *%rax .L846: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L854: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L850 .L855: movl $4, %eax jmp .L850 .L856: movl $7, %eax jmp .L850 .L848: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L847 .L852: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L852 jmp .L847 .L858: movl $0, %eax jmp .L846 .cfi_endproc .LFE8533: .size nvtxDomainCreateA_impl_init_v3, .-nvtxDomainCreateA_impl_init_v3 .section .text.nvtxNameCuEventW_impl_init_v3,"axG",@progbits,nvtxNameCuEventW_impl_init_v3,comdat .weak nvtxNameCuEventW_impl_init_v3 .hidden nvtxNameCuEventW_impl_init_v3 .type nvtxNameCuEventW_impl_init_v3, @function nvtxNameCuEventW_impl_init_v3: .LFB8544: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L863 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L864 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L865 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L871 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L876 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L870 movl $0, %eax jmp .L866 .L876: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L866 .L865: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L872 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L866: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L863: movq 224+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L862 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L862: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L870: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L866 .L871: movl $4, %eax jmp .L866 .L872: movl $7, %eax jmp .L866 .L864: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L863 .L868: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L868 jmp .L863 .cfi_endproc .LFE8544: .size nvtxNameCuEventW_impl_init_v3, .-nvtxNameCuEventW_impl_init_v3 .section .text.nvtxDomainRangePop_impl_init_v3,"axG",@progbits,nvtxDomainRangePop_impl_init_v3,comdat .weak nvtxDomainRangePop_impl_init_v3 .hidden nvtxDomainRangePop_impl_init_v3 .type nvtxDomainRangePop_impl_init_v3, @function nvtxDomainRangePop_impl_init_v3: .LFB8526: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L878 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L879 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L880 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L886 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L892 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L885 movl $0, %eax jmp .L881 .L892: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L881 .L880: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L887 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L881: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L878: movq 424+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L889 movq %rbx, %rdi call *%rax .L877: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L885: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L881 .L886: movl $4, %eax jmp .L881 .L887: movl $7, %eax jmp .L881 .L879: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L878 .L883: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L883 jmp .L878 .L889: movl $-2, %eax jmp .L877 .cfi_endproc .LFE8526: .size nvtxDomainRangePop_impl_init_v3, .-nvtxDomainRangePop_impl_init_v3 .section .text.nvtxNameCudaStreamW_impl_init_v3,"axG",@progbits,nvtxNameCudaStreamW_impl_init_v3,comdat .weak nvtxNameCudaStreamW_impl_init_v3 .hidden nvtxNameCudaStreamW_impl_init_v3 .type nvtxNameCudaStreamW_impl_init_v3, @function nvtxNameCudaStreamW_impl_init_v3: .LFB8548: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L894 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L895 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L896 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L902 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L907 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L901 movl $0, %eax jmp .L897 .L907: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L897 .L896: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L903 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L897: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L894: movq 368+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L893 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L893: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L901: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L897 .L902: movl $4, %eax jmp .L897 .L903: movl $7, %eax jmp .L897 .L895: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L894 .L899: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L899 jmp .L894 .cfi_endproc .LFE8548: .size nvtxNameCudaStreamW_impl_init_v3, .-nvtxNameCudaStreamW_impl_init_v3 .section .text.nvtxDomainCreateW_impl_init_v3,"axG",@progbits,nvtxDomainCreateW_impl_init_v3,comdat .weak nvtxDomainCreateW_impl_init_v3 .hidden nvtxDomainCreateW_impl_init_v3 .type nvtxDomainCreateW_impl_init_v3, @function nvtxDomainCreateW_impl_init_v3: .LFB8534: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L909 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L910 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L911 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L917 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L923 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L916 movl $0, %eax jmp .L912 .L923: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L912 .L911: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L918 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L912: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L909: movq 488+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L920 movq %rbx, %rdi call *%rax .L908: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L916: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L912 .L917: movl $4, %eax jmp .L912 .L918: movl $7, %eax jmp .L912 .L910: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L909 .L914: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L914 jmp .L909 .L920: movl $0, %eax jmp .L908 .cfi_endproc .LFE8534: .size nvtxDomainCreateW_impl_init_v3, .-nvtxDomainCreateW_impl_init_v3 .section .text.nvtxDomainMarkEx_impl_init_v3,"axG",@progbits,nvtxDomainMarkEx_impl_init_v3,comdat .weak nvtxDomainMarkEx_impl_init_v3 .hidden nvtxDomainMarkEx_impl_init_v3 .type nvtxDomainMarkEx_impl_init_v3, @function nvtxDomainMarkEx_impl_init_v3: .LFB8522: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L925 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L926 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L927 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L933 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L938 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L932 movl $0, %eax jmp .L928 .L938: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L928 .L927: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L934 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L928: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L925: movq 392+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L924 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L924: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L932: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L928 .L933: movl $4, %eax jmp .L928 .L934: movl $7, %eax jmp .L928 .L926: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L925 .L930: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L930 jmp .L925 .cfi_endproc .LFE8522: .size nvtxDomainMarkEx_impl_init_v3, .-nvtxDomainMarkEx_impl_init_v3 .section .text.nvtxNameCuEventA_impl_init_v3,"axG",@progbits,nvtxNameCuEventA_impl_init_v3,comdat .weak nvtxNameCuEventA_impl_init_v3 .hidden nvtxNameCuEventA_impl_init_v3 .type nvtxNameCuEventA_impl_init_v3, @function nvtxNameCuEventA_impl_init_v3: .LFB8543: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L940 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L941 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L942 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L948 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L953 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L947 movl $0, %eax jmp .L943 .L953: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L943 .L942: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L949 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L943: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L940: movq 216+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L939 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L939: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L947: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L943 .L948: movl $4, %eax jmp .L943 .L949: movl $7, %eax jmp .L943 .L941: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L940 .L945: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L945 jmp .L940 .cfi_endproc .LFE8543: .size nvtxNameCuEventA_impl_init_v3, .-nvtxNameCuEventA_impl_init_v3 .section .text.nvtxNameCudaStreamA_impl_init_v3,"axG",@progbits,nvtxNameCudaStreamA_impl_init_v3,comdat .weak nvtxNameCudaStreamA_impl_init_v3 .hidden nvtxNameCudaStreamA_impl_init_v3 .type nvtxNameCudaStreamA_impl_init_v3, @function nvtxNameCudaStreamA_impl_init_v3: .LFB8547: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L955 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L956 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L957 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L963 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L968 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L962 movl $0, %eax jmp .L958 .L968: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L958 .L957: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L964 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L958: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L955: movq 360+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L954 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L954: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L962: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L958 .L963: movl $4, %eax jmp .L958 .L964: movl $7, %eax jmp .L958 .L956: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L955 .L960: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L960 jmp .L955 .cfi_endproc .LFE8547: .size nvtxNameCudaStreamA_impl_init_v3, .-nvtxNameCudaStreamA_impl_init_v3 .section .text.nvtxNameClMemObjectW_impl_init_v3,"axG",@progbits,nvtxNameClMemObjectW_impl_init_v3,comdat .weak nvtxNameClMemObjectW_impl_init_v3 .hidden nvtxNameClMemObjectW_impl_init_v3 .type nvtxNameClMemObjectW_impl_init_v3, @function nvtxNameClMemObjectW_impl_init_v3: .LFB8558: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L970 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L971 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L972 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L978 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L983 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L977 movl $0, %eax jmp .L973 .L983: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L973 .L972: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L979 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L973: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L970: movq 288+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L969 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L969: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L977: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L973 .L978: movl $4, %eax jmp .L973 .L979: movl $7, %eax jmp .L973 .L971: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L970 .L975: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L975 jmp .L970 .cfi_endproc .LFE8558: .size nvtxNameClMemObjectW_impl_init_v3, .-nvtxNameClMemObjectW_impl_init_v3 .section .text.nvtxNameCuStreamA_impl_init_v3,"axG",@progbits,nvtxNameCuStreamA_impl_init_v3,comdat .weak nvtxNameCuStreamA_impl_init_v3 .hidden nvtxNameCuStreamA_impl_init_v3 .type nvtxNameCuStreamA_impl_init_v3, @function nvtxNameCuStreamA_impl_init_v3: .LFB8541: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L985 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L986 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L987 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L993 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L998 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L992 movl $0, %eax jmp .L988 .L998: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L988 .L987: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L994 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L988: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L985: movq 200+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L984 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L984: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L992: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L988 .L993: movl $4, %eax jmp .L988 .L994: movl $7, %eax jmp .L988 .L986: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L985 .L990: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L990 jmp .L985 .cfi_endproc .LFE8541: .size nvtxNameCuStreamA_impl_init_v3, .-nvtxNameCuStreamA_impl_init_v3 .section .text.nvtxNameCuDeviceA_impl_init_v3,"axG",@progbits,nvtxNameCuDeviceA_impl_init_v3,comdat .weak nvtxNameCuDeviceA_impl_init_v3 .hidden nvtxNameCuDeviceA_impl_init_v3 .type nvtxNameCuDeviceA_impl_init_v3, @function nvtxNameCuDeviceA_impl_init_v3: .LFB8537: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movl %edi, %ebx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1000 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1001 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1002 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1008 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1013 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1007 movl $0, %eax jmp .L1003 .L1013: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1003 .L1002: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1009 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1003: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1000: movq 168+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L999 movq %rbp, %rsi movl %ebx, %edi call *%rax .L999: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1007: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1003 .L1008: movl $4, %eax jmp .L1003 .L1009: movl $7, %eax jmp .L1003 .L1001: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1000 .L1005: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1005 jmp .L1000 .cfi_endproc .LFE8537: .size nvtxNameCuDeviceA_impl_init_v3, .-nvtxNameCuDeviceA_impl_init_v3 .section .text.nvtxNameCudaEventA_impl_init_v3,"axG",@progbits,nvtxNameCudaEventA_impl_init_v3,comdat .weak nvtxNameCudaEventA_impl_init_v3 .hidden nvtxNameCudaEventA_impl_init_v3 .type nvtxNameCudaEventA_impl_init_v3, @function nvtxNameCudaEventA_impl_init_v3: .LFB8549: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1015 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1016 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1017 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1023 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1028 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1022 movl $0, %eax jmp .L1018 .L1028: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1018 .L1017: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1024 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1018: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1015: movq 376+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1014 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1014: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1022: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1018 .L1023: movl $4, %eax jmp .L1018 .L1024: movl $7, %eax jmp .L1018 .L1016: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1015 .L1020: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1020 jmp .L1015 .cfi_endproc .LFE8549: .size nvtxNameCudaEventA_impl_init_v3, .-nvtxNameCudaEventA_impl_init_v3 .section .text.nvtxNameCuContextA_impl_init_v3,"axG",@progbits,nvtxNameCuContextA_impl_init_v3,comdat .weak nvtxNameCuContextA_impl_init_v3 .hidden nvtxNameCuContextA_impl_init_v3 .type nvtxNameCuContextA_impl_init_v3, @function nvtxNameCuContextA_impl_init_v3: .LFB8539: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1030 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1031 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1032 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1038 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1043 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1037 movl $0, %eax jmp .L1033 .L1043: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1033 .L1032: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1039 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1033: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1030: movq 184+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1029 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1029: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1037: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1033 .L1038: movl $4, %eax jmp .L1033 .L1039: movl $7, %eax jmp .L1033 .L1031: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1030 .L1035: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1035 jmp .L1030 .cfi_endproc .LFE8539: .size nvtxNameCuContextA_impl_init_v3, .-nvtxNameCuContextA_impl_init_v3 .section .text.nvtxNameCudaDeviceA_impl_init_v3,"axG",@progbits,nvtxNameCudaDeviceA_impl_init_v3,comdat .weak nvtxNameCudaDeviceA_impl_init_v3 .hidden nvtxNameCudaDeviceA_impl_init_v3 .type nvtxNameCudaDeviceA_impl_init_v3, @function nvtxNameCudaDeviceA_impl_init_v3: .LFB8545: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movl %edi, %ebx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1045 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1046 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1047 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1053 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1058 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1052 movl $0, %eax jmp .L1048 .L1058: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1048 .L1047: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1054 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1048: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1045: movq 344+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1044 movq %rbp, %rsi movl %ebx, %edi call *%rax .L1044: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1052: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1048 .L1053: movl $4, %eax jmp .L1048 .L1054: movl $7, %eax jmp .L1048 .L1046: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1045 .L1050: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1050 jmp .L1045 .cfi_endproc .LFE8545: .size nvtxNameCudaDeviceA_impl_init_v3, .-nvtxNameCudaDeviceA_impl_init_v3 .section .text.nvtxNameCategoryW_impl_init_v3,"axG",@progbits,nvtxNameCategoryW_impl_init_v3,comdat .weak nvtxNameCategoryW_impl_init_v3 .hidden nvtxNameCategoryW_impl_init_v3 .type nvtxNameCategoryW_impl_init_v3, @function nvtxNameCategoryW_impl_init_v3: .LFB8519: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movl %edi, %ebx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1060 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1061 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1062 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1068 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1073 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1067 movl $0, %eax jmp .L1063 .L1073: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1063 .L1062: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1069 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1063: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1060: movq 144+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1059 movq %rbp, %rsi movl %ebx, %edi call *%rax .L1059: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1067: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1063 .L1068: movl $4, %eax jmp .L1063 .L1069: movl $7, %eax jmp .L1063 .L1061: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1060 .L1065: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1065 jmp .L1060 .cfi_endproc .LFE8519: .size nvtxNameCategoryW_impl_init_v3, .-nvtxNameCategoryW_impl_init_v3 .section .text.nvtxNameCuDeviceW_impl_init_v3,"axG",@progbits,nvtxNameCuDeviceW_impl_init_v3,comdat .weak nvtxNameCuDeviceW_impl_init_v3 .hidden nvtxNameCuDeviceW_impl_init_v3 .type nvtxNameCuDeviceW_impl_init_v3, @function nvtxNameCuDeviceW_impl_init_v3: .LFB8538: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movl %edi, %ebx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1075 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1076 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1077 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1083 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1088 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1082 movl $0, %eax jmp .L1078 .L1088: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1078 .L1077: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1084 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1078: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1075: movq 176+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1074 movq %rbp, %rsi movl %ebx, %edi call *%rax .L1074: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1082: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1078 .L1083: movl $4, %eax jmp .L1078 .L1084: movl $7, %eax jmp .L1078 .L1076: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1075 .L1080: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1080 jmp .L1075 .cfi_endproc .LFE8538: .size nvtxNameCuDeviceW_impl_init_v3, .-nvtxNameCuDeviceW_impl_init_v3 .section .text.nvtxNameOsThreadW_impl_init_v3,"axG",@progbits,nvtxNameOsThreadW_impl_init_v3,comdat .weak nvtxNameOsThreadW_impl_init_v3 .hidden nvtxNameOsThreadW_impl_init_v3 .type nvtxNameOsThreadW_impl_init_v3, @function nvtxNameOsThreadW_impl_init_v3: .LFB8521: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movl %edi, %ebx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1090 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1091 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1092 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1098 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1103 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1097 movl $0, %eax jmp .L1093 .L1103: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1093 .L1092: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1099 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1093: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1090: movq 160+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1089 movq %rbp, %rsi movl %ebx, %edi call *%rax .L1089: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1097: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1093 .L1098: movl $4, %eax jmp .L1093 .L1099: movl $7, %eax jmp .L1093 .L1091: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1090 .L1095: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1095 jmp .L1090 .cfi_endproc .LFE8521: .size nvtxNameOsThreadW_impl_init_v3, .-nvtxNameOsThreadW_impl_init_v3 .section .text.nvtxNameCuStreamW_impl_init_v3,"axG",@progbits,nvtxNameCuStreamW_impl_init_v3,comdat .weak nvtxNameCuStreamW_impl_init_v3 .hidden nvtxNameCuStreamW_impl_init_v3 .type nvtxNameCuStreamW_impl_init_v3, @function nvtxNameCuStreamW_impl_init_v3: .LFB8542: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1105 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1106 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1107 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1113 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1118 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1112 movl $0, %eax jmp .L1108 .L1118: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1108 .L1107: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1114 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1108: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1105: movq 208+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1104 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1104: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1112: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1108 .L1113: movl $4, %eax jmp .L1108 .L1114: movl $7, %eax jmp .L1108 .L1106: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1105 .L1110: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1110 jmp .L1105 .cfi_endproc .LFE8542: .size nvtxNameCuStreamW_impl_init_v3, .-nvtxNameCuStreamW_impl_init_v3 .section .text.nvtxDomainRangeEnd_impl_init_v3,"axG",@progbits,nvtxDomainRangeEnd_impl_init_v3,comdat .weak nvtxDomainRangeEnd_impl_init_v3 .hidden nvtxDomainRangeEnd_impl_init_v3 .type nvtxDomainRangeEnd_impl_init_v3, @function nvtxDomainRangeEnd_impl_init_v3: .LFB8524: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1120 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1121 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1122 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1128 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1133 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1127 movl $0, %eax jmp .L1123 .L1133: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1123 .L1122: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1129 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1123: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1120: movq 408+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1119 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1119: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1127: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1123 .L1128: movl $4, %eax jmp .L1123 .L1129: movl $7, %eax jmp .L1123 .L1121: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1120 .L1125: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1125 jmp .L1120 .cfi_endproc .LFE8524: .size nvtxDomainRangeEnd_impl_init_v3, .-nvtxDomainRangeEnd_impl_init_v3 .section .text.nvtxNameCuContextW_impl_init_v3,"axG",@progbits,nvtxNameCuContextW_impl_init_v3,comdat .weak nvtxNameCuContextW_impl_init_v3 .hidden nvtxNameCuContextW_impl_init_v3 .type nvtxNameCuContextW_impl_init_v3, @function nvtxNameCuContextW_impl_init_v3: .LFB8540: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1135 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1136 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1137 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1143 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1148 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1142 movl $0, %eax jmp .L1138 .L1148: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1138 .L1137: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1144 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1138: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1135: movq 192+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1134 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1134: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1142: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1138 .L1143: movl $4, %eax jmp .L1138 .L1144: movl $7, %eax jmp .L1138 .L1136: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1135 .L1140: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1140 jmp .L1135 .cfi_endproc .LFE8540: .size nvtxNameCuContextW_impl_init_v3, .-nvtxNameCuContextW_impl_init_v3 .section .text.nvtxNameOsThreadA_impl_init_v3,"axG",@progbits,nvtxNameOsThreadA_impl_init_v3,comdat .weak nvtxNameOsThreadA_impl_init_v3 .hidden nvtxNameOsThreadA_impl_init_v3 .type nvtxNameOsThreadA_impl_init_v3, @function nvtxNameOsThreadA_impl_init_v3: .LFB8520: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movl %edi, %ebx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1150 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1151 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1152 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1158 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1163 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1157 movl $0, %eax jmp .L1153 .L1163: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1153 .L1152: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1159 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1153: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1150: movq 152+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1149 movq %rbp, %rsi movl %ebx, %edi call *%rax .L1149: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1157: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1153 .L1158: movl $4, %eax jmp .L1153 .L1159: movl $7, %eax jmp .L1153 .L1151: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1150 .L1155: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1155 jmp .L1150 .cfi_endproc .LFE8520: .size nvtxNameOsThreadA_impl_init_v3, .-nvtxNameOsThreadA_impl_init_v3 .section .text.nvtxNameCudaDeviceW_impl_init_v3,"axG",@progbits,nvtxNameCudaDeviceW_impl_init_v3,comdat .weak nvtxNameCudaDeviceW_impl_init_v3 .hidden nvtxNameCudaDeviceW_impl_init_v3 .type nvtxNameCudaDeviceW_impl_init_v3, @function nvtxNameCudaDeviceW_impl_init_v3: .LFB8546: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movl %edi, %ebx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1165 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1166 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1167 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1173 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1178 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1172 movl $0, %eax jmp .L1168 .L1178: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1168 .L1167: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1174 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1168: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1165: movq 352+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1164 movq %rbp, %rsi movl %ebx, %edi call *%rax .L1164: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1172: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1168 .L1173: movl $4, %eax jmp .L1168 .L1174: movl $7, %eax jmp .L1168 .L1166: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1165 .L1170: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1170 jmp .L1165 .cfi_endproc .LFE8546: .size nvtxNameCudaDeviceW_impl_init_v3, .-nvtxNameCudaDeviceW_impl_init_v3 .section .text.nvtxRangePushA_impl_init_v3,"axG",@progbits,nvtxRangePushA_impl_init_v3,comdat .weak nvtxRangePushA_impl_init_v3 .hidden nvtxRangePushA_impl_init_v3 .type nvtxRangePushA_impl_init_v3, @function nvtxRangePushA_impl_init_v3: .LFB8515: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1180 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1181 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1182 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L1188 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1194 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1187 movl $0, %eax jmp .L1183 .L1194: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L1183 .L1182: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1189 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1183: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1180: movq 112+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1191 movq %rbx, %rdi call *%rax .L1179: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L1187: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L1183 .L1188: movl $4, %eax jmp .L1183 .L1189: movl $7, %eax jmp .L1183 .L1181: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1180 .L1185: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1185 jmp .L1180 .L1191: movl $-2, %eax jmp .L1179 .cfi_endproc .LFE8515: .size nvtxRangePushA_impl_init_v3, .-nvtxRangePushA_impl_init_v3 .section .text.nvtxRangePushEx_impl_init_v3,"axG",@progbits,nvtxRangePushEx_impl_init_v3,comdat .weak nvtxRangePushEx_impl_init_v3 .hidden nvtxRangePushEx_impl_init_v3 .type nvtxRangePushEx_impl_init_v3, @function nvtxRangePushEx_impl_init_v3: .LFB8514: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1196 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1197 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1198 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L1204 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1210 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1203 movl $0, %eax jmp .L1199 .L1210: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L1199 .L1198: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1205 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1199: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1196: movq 104+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1207 movq %rbx, %rdi call *%rax .L1195: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L1203: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L1199 .L1204: movl $4, %eax jmp .L1199 .L1205: movl $7, %eax jmp .L1199 .L1197: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1196 .L1201: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1201 jmp .L1196 .L1207: movl $-2, %eax jmp .L1195 .cfi_endproc .LFE8514: .size nvtxRangePushEx_impl_init_v3, .-nvtxRangePushEx_impl_init_v3 .section .text.nvtxRangeStartA_impl_init_v3,"axG",@progbits,nvtxRangeStartA_impl_init_v3,comdat .weak nvtxRangeStartA_impl_init_v3 .hidden nvtxRangeStartA_impl_init_v3 .type nvtxRangeStartA_impl_init_v3, @function nvtxRangeStartA_impl_init_v3: .LFB8511: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1212 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1213 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1214 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L1220 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1226 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1219 movl $0, %eax jmp .L1215 .L1226: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L1215 .L1214: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1221 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1215: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1212: movq 80+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1223 movq %rbx, %rdi call *%rax .L1211: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L1219: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L1215 .L1220: movl $4, %eax jmp .L1215 .L1221: movl $7, %eax jmp .L1215 .L1213: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1212 .L1217: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1217 jmp .L1212 .L1223: movl $0, %eax jmp .L1211 .cfi_endproc .LFE8511: .size nvtxRangeStartA_impl_init_v3, .-nvtxRangeStartA_impl_init_v3 .section .text.nvtxRangeStartW_impl_init_v3,"axG",@progbits,nvtxRangeStartW_impl_init_v3,comdat .weak nvtxRangeStartW_impl_init_v3 .hidden nvtxRangeStartW_impl_init_v3 .type nvtxRangeStartW_impl_init_v3, @function nvtxRangeStartW_impl_init_v3: .LFB8512: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1228 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1229 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1230 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L1236 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1242 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1235 movl $0, %eax jmp .L1231 .L1242: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L1231 .L1230: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1237 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1231: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1228: movq 88+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1239 movq %rbx, %rdi call *%rax .L1227: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L1235: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L1231 .L1236: movl $4, %eax jmp .L1231 .L1237: movl $7, %eax jmp .L1231 .L1229: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1228 .L1233: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1233 jmp .L1228 .L1239: movl $0, %eax jmp .L1227 .cfi_endproc .LFE8512: .size nvtxRangeStartW_impl_init_v3, .-nvtxRangeStartW_impl_init_v3 .section .text.nvtxNameCudaEventW_impl_init_v3,"axG",@progbits,nvtxNameCudaEventW_impl_init_v3,comdat .weak nvtxNameCudaEventW_impl_init_v3 .hidden nvtxNameCudaEventW_impl_init_v3 .type nvtxNameCudaEventW_impl_init_v3, @function nvtxNameCudaEventW_impl_init_v3: .LFB8550: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1244 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1245 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1246 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1252 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1257 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1251 movl $0, %eax jmp .L1247 .L1257: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1247 .L1246: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1253 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1247: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1244: movq 384+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1243 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1243: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1251: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1247 .L1252: movl $4, %eax jmp .L1247 .L1253: movl $7, %eax jmp .L1247 .L1245: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1244 .L1249: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1249 jmp .L1244 .cfi_endproc .LFE8550: .size nvtxNameCudaEventW_impl_init_v3, .-nvtxNameCudaEventW_impl_init_v3 .section .text.nvtxRangeStartEx_impl_init_v3,"axG",@progbits,nvtxRangeStartEx_impl_init_v3,comdat .weak nvtxRangeStartEx_impl_init_v3 .hidden nvtxRangeStartEx_impl_init_v3 .type nvtxRangeStartEx_impl_init_v3, @function nvtxRangeStartEx_impl_init_v3: .LFB8510: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1259 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1260 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1261 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L1267 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1273 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1266 movl $0, %eax jmp .L1262 .L1273: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L1262 .L1261: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1268 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1262: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1259: movq 72+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1270 movq %rbx, %rdi call *%rax .L1258: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L1266: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L1262 .L1267: movl $4, %eax jmp .L1262 .L1268: movl $7, %eax jmp .L1262 .L1260: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1259 .L1264: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1264 jmp .L1259 .L1270: movl $0, %eax jmp .L1258 .cfi_endproc .LFE8510: .size nvtxRangeStartEx_impl_init_v3, .-nvtxRangeStartEx_impl_init_v3 .section .text.nvtxNameCategoryA_impl_init_v3,"axG",@progbits,nvtxNameCategoryA_impl_init_v3,comdat .weak nvtxNameCategoryA_impl_init_v3 .hidden nvtxNameCategoryA_impl_init_v3 .type nvtxNameCategoryA_impl_init_v3, @function nvtxNameCategoryA_impl_init_v3: .LFB8518: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movl %edi, %ebx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1275 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1276 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1277 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1283 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1288 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1282 movl $0, %eax jmp .L1278 .L1288: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1278 .L1277: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1284 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1278: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1275: movq 136+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1274 movq %rbp, %rsi movl %ebx, %edi call *%rax .L1274: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1282: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1278 .L1283: movl $4, %eax jmp .L1278 .L1284: movl $7, %eax jmp .L1278 .L1276: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1275 .L1280: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1280 jmp .L1275 .cfi_endproc .LFE8518: .size nvtxNameCategoryA_impl_init_v3, .-nvtxNameCategoryA_impl_init_v3 .section .text.nvtxNameClCommandQueueA_impl_init_v3,"axG",@progbits,nvtxNameClCommandQueueA_impl_init_v3,comdat .weak nvtxNameClCommandQueueA_impl_init_v3 .hidden nvtxNameClCommandQueueA_impl_init_v3 .type nvtxNameClCommandQueueA_impl_init_v3, @function nvtxNameClCommandQueueA_impl_init_v3: .LFB8555: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1290 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1291 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1292 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1298 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1303 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1297 movl $0, %eax jmp .L1293 .L1303: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1293 .L1292: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1299 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1293: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1290: movq 264+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1289 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1289: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1297: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1293 .L1298: movl $4, %eax jmp .L1293 .L1299: movl $7, %eax jmp .L1293 .L1291: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1290 .L1295: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1295 jmp .L1290 .cfi_endproc .LFE8555: .size nvtxNameClCommandQueueA_impl_init_v3, .-nvtxNameClCommandQueueA_impl_init_v3 .section .text.nvtxNameClMemObjectA_impl_init_v3,"axG",@progbits,nvtxNameClMemObjectA_impl_init_v3,comdat .weak nvtxNameClMemObjectA_impl_init_v3 .hidden nvtxNameClMemObjectA_impl_init_v3 .type nvtxNameClMemObjectA_impl_init_v3, @function nvtxNameClMemObjectA_impl_init_v3: .LFB8557: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1305 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1306 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1307 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1313 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1318 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1312 movl $0, %eax jmp .L1308 .L1318: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1308 .L1307: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1314 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1308: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1305: movq 280+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1304 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1304: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1312: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1308 .L1313: movl $4, %eax jmp .L1308 .L1314: movl $7, %eax jmp .L1308 .L1306: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1305 .L1310: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1310 jmp .L1305 .cfi_endproc .LFE8557: .size nvtxNameClMemObjectA_impl_init_v3, .-nvtxNameClMemObjectA_impl_init_v3 .section .text.nvtxNameClDeviceA_impl_init_v3,"axG",@progbits,nvtxNameClDeviceA_impl_init_v3,comdat .weak nvtxNameClDeviceA_impl_init_v3 .hidden nvtxNameClDeviceA_impl_init_v3 .type nvtxNameClDeviceA_impl_init_v3, @function nvtxNameClDeviceA_impl_init_v3: .LFB8551: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1320 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1321 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1322 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1328 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1333 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1327 movl $0, %eax jmp .L1323 .L1333: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1323 .L1322: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1329 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1323: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1320: movq 232+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1319 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1319: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1327: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1323 .L1328: movl $4, %eax jmp .L1323 .L1329: movl $7, %eax jmp .L1323 .L1321: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1320 .L1325: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1325 jmp .L1320 .cfi_endproc .LFE8551: .size nvtxNameClDeviceA_impl_init_v3, .-nvtxNameClDeviceA_impl_init_v3 .section .text.nvtxNameClDeviceW_impl_init_v3,"axG",@progbits,nvtxNameClDeviceW_impl_init_v3,comdat .weak nvtxNameClDeviceW_impl_init_v3 .hidden nvtxNameClDeviceW_impl_init_v3 .type nvtxNameClDeviceW_impl_init_v3, @function nvtxNameClDeviceW_impl_init_v3: .LFB8552: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1335 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1336 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1337 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1343 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1348 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1342 movl $0, %eax jmp .L1338 .L1348: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1338 .L1337: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1344 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1338: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1335: movq 240+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1334 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1334: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1342: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1338 .L1343: movl $4, %eax jmp .L1338 .L1344: movl $7, %eax jmp .L1338 .L1336: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1335 .L1340: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1340 jmp .L1335 .cfi_endproc .LFE8552: .size nvtxNameClDeviceW_impl_init_v3, .-nvtxNameClDeviceW_impl_init_v3 .section .text.nvtxNameClContextA_impl_init_v3,"axG",@progbits,nvtxNameClContextA_impl_init_v3,comdat .weak nvtxNameClContextA_impl_init_v3 .hidden nvtxNameClContextA_impl_init_v3 .type nvtxNameClContextA_impl_init_v3, @function nvtxNameClContextA_impl_init_v3: .LFB8553: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1350 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1351 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1352 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1358 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1363 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1357 movl $0, %eax jmp .L1353 .L1363: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1353 .L1352: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1359 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1353: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1350: movq 248+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1349 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1349: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1357: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1353 .L1358: movl $4, %eax jmp .L1353 .L1359: movl $7, %eax jmp .L1353 .L1351: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1350 .L1355: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1355 jmp .L1350 .cfi_endproc .LFE8553: .size nvtxNameClContextA_impl_init_v3, .-nvtxNameClContextA_impl_init_v3 .section .text.nvtxNameClCommandQueueW_impl_init_v3,"axG",@progbits,nvtxNameClCommandQueueW_impl_init_v3,comdat .weak nvtxNameClCommandQueueW_impl_init_v3 .hidden nvtxNameClCommandQueueW_impl_init_v3 .type nvtxNameClCommandQueueW_impl_init_v3, @function nvtxNameClCommandQueueW_impl_init_v3: .LFB8556: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1365 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1366 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1367 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1373 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1378 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1372 movl $0, %eax jmp .L1368 .L1378: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1368 .L1367: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1374 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1368: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1365: movq 272+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1364 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1364: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1372: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1368 .L1373: movl $4, %eax jmp .L1368 .L1374: movl $7, %eax jmp .L1368 .L1366: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1365 .L1370: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1370 jmp .L1365 .cfi_endproc .LFE8556: .size nvtxNameClCommandQueueW_impl_init_v3, .-nvtxNameClCommandQueueW_impl_init_v3 .section .text.nvtxRangePushW_impl_init_v3,"axG",@progbits,nvtxRangePushW_impl_init_v3,comdat .weak nvtxRangePushW_impl_init_v3 .hidden nvtxRangePushW_impl_init_v3 .type nvtxRangePushW_impl_init_v3, @function nvtxRangePushW_impl_init_v3: .LFB8516: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbx movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1380 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1381 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1382 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %rbp testq %rax, %rax je .L1388 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1394 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1387 movl $0, %eax jmp .L1383 .L1394: movq %rbp, %rdi call dlclose@PLT movl $5, %eax jmp .L1383 .L1382: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1389 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1383: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1380: movq 120+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1391 movq %rbx, %rdi call *%rax .L1379: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L1387: .cfi_restore_state movq %rbp, %rdi call dlclose@PLT movl $6, %eax jmp .L1383 .L1388: movl $4, %eax jmp .L1383 .L1389: movl $7, %eax jmp .L1383 .L1381: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1380 .L1385: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1385 jmp .L1380 .L1391: movl $-2, %eax jmp .L1379 .cfi_endproc .LFE8516: .size nvtxRangePushW_impl_init_v3, .-nvtxRangePushW_impl_init_v3 .section .text.nvtxNameClEventW_impl_init_v3,"axG",@progbits,nvtxNameClEventW_impl_init_v3,comdat .weak nvtxNameClEventW_impl_init_v3 .hidden nvtxNameClEventW_impl_init_v3 .type nvtxNameClEventW_impl_init_v3, @function nvtxNameClEventW_impl_init_v3: .LFB8564: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1396 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1397 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1398 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1404 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1409 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1403 movl $0, %eax jmp .L1399 .L1409: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1399 .L1398: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1405 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1399: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1396: movq 336+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1395 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1395: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1403: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1399 .L1404: movl $4, %eax jmp .L1399 .L1405: movl $7, %eax jmp .L1399 .L1397: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1396 .L1401: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1401 jmp .L1396 .cfi_endproc .LFE8564: .size nvtxNameClEventW_impl_init_v3, .-nvtxNameClEventW_impl_init_v3 .section .text.nvtxNameClEventA_impl_init_v3,"axG",@progbits,nvtxNameClEventA_impl_init_v3,comdat .weak nvtxNameClEventA_impl_init_v3 .hidden nvtxNameClEventA_impl_init_v3 .type nvtxNameClEventA_impl_init_v3, @function nvtxNameClEventA_impl_init_v3: .LFB8563: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1411 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1412 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1413 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1419 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1424 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1418 movl $0, %eax jmp .L1414 .L1424: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1414 .L1413: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1420 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1414: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1411: movq 328+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1410 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1410: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1418: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1414 .L1419: movl $4, %eax jmp .L1414 .L1420: movl $7, %eax jmp .L1414 .L1412: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1411 .L1416: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1416 jmp .L1411 .cfi_endproc .LFE8563: .size nvtxNameClEventA_impl_init_v3, .-nvtxNameClEventA_impl_init_v3 .section .text.nvtxNameClProgramW_impl_init_v3,"axG",@progbits,nvtxNameClProgramW_impl_init_v3,comdat .weak nvtxNameClProgramW_impl_init_v3 .hidden nvtxNameClProgramW_impl_init_v3 .type nvtxNameClProgramW_impl_init_v3, @function nvtxNameClProgramW_impl_init_v3: .LFB8562: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1426 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1427 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1428 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1434 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1439 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1433 movl $0, %eax jmp .L1429 .L1439: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1429 .L1428: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1435 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1429: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1426: movq 320+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1425 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1425: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1433: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1429 .L1434: movl $4, %eax jmp .L1429 .L1435: movl $7, %eax jmp .L1429 .L1427: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1426 .L1431: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1431 jmp .L1426 .cfi_endproc .LFE8562: .size nvtxNameClProgramW_impl_init_v3, .-nvtxNameClProgramW_impl_init_v3 .section .text.nvtxNameClSamplerA_impl_init_v3,"axG",@progbits,nvtxNameClSamplerA_impl_init_v3,comdat .weak nvtxNameClSamplerA_impl_init_v3 .hidden nvtxNameClSamplerA_impl_init_v3 .type nvtxNameClSamplerA_impl_init_v3, @function nvtxNameClSamplerA_impl_init_v3: .LFB8559: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1441 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1442 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1443 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1449 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1454 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1448 movl $0, %eax jmp .L1444 .L1454: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1444 .L1443: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1450 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1444: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1441: movq 296+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1440 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1440: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1448: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1444 .L1449: movl $4, %eax jmp .L1444 .L1450: movl $7, %eax jmp .L1444 .L1442: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1441 .L1446: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1446 jmp .L1441 .cfi_endproc .LFE8559: .size nvtxNameClSamplerA_impl_init_v3, .-nvtxNameClSamplerA_impl_init_v3 .section .text.nvtxNameClSamplerW_impl_init_v3,"axG",@progbits,nvtxNameClSamplerW_impl_init_v3,comdat .weak nvtxNameClSamplerW_impl_init_v3 .hidden nvtxNameClSamplerW_impl_init_v3 .type nvtxNameClSamplerW_impl_init_v3, @function nvtxNameClSamplerW_impl_init_v3: .LFB8560: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1456 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1457 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1458 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1464 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1469 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1463 movl $0, %eax jmp .L1459 .L1469: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1459 .L1458: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1465 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1459: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1456: movq 304+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1455 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1455: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1463: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1459 .L1464: movl $4, %eax jmp .L1459 .L1465: movl $7, %eax jmp .L1459 .L1457: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1456 .L1461: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1461 jmp .L1456 .cfi_endproc .LFE8560: .size nvtxNameClSamplerW_impl_init_v3, .-nvtxNameClSamplerW_impl_init_v3 .section .text.nvtxNameClProgramA_impl_init_v3,"axG",@progbits,nvtxNameClProgramA_impl_init_v3,comdat .weak nvtxNameClProgramA_impl_init_v3 .hidden nvtxNameClProgramA_impl_init_v3 .type nvtxNameClProgramA_impl_init_v3, @function nvtxNameClProgramA_impl_init_v3: .LFB8561: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1471 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1472 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1473 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1479 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1484 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1478 movl $0, %eax jmp .L1474 .L1484: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1474 .L1473: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1480 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1474: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1471: movq 312+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1470 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1470: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1478: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1474 .L1479: movl $4, %eax jmp .L1474 .L1480: movl $7, %eax jmp .L1474 .L1472: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1471 .L1476: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1476 jmp .L1471 .cfi_endproc .LFE8561: .size nvtxNameClProgramA_impl_init_v3, .-nvtxNameClProgramA_impl_init_v3 .section .text.nvtxNameClContextW_impl_init_v3,"axG",@progbits,nvtxNameClContextW_impl_init_v3,comdat .weak nvtxNameClContextW_impl_init_v3 .hidden nvtxNameClContextW_impl_init_v3 .type nvtxNameClContextW_impl_init_v3, @function nvtxNameClContextW_impl_init_v3: .LFB8554: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1486 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1487 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1488 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1494 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1499 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1493 movl $0, %eax jmp .L1489 .L1499: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1489 .L1488: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1495 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1489: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1486: movq 256+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1485 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1485: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1493: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1489 .L1494: movl $4, %eax jmp .L1489 .L1495: movl $7, %eax jmp .L1489 .L1487: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1486 .L1491: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1491 jmp .L1486 .cfi_endproc .LFE8554: .size nvtxNameClContextW_impl_init_v3, .-nvtxNameClContextW_impl_init_v3 .section .text.nvtxDomainRangePushEx_impl_init_v3,"axG",@progbits,nvtxDomainRangePushEx_impl_init_v3,comdat .weak nvtxDomainRangePushEx_impl_init_v3 .hidden nvtxDomainRangePushEx_impl_init_v3 .type nvtxDomainRangePushEx_impl_init_v3, @function nvtxDomainRangePushEx_impl_init_v3: .LFB8525: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1501 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1502 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1503 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1509 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1515 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1508 movl $0, %eax jmp .L1504 .L1515: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1504 .L1503: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1510 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1504: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1501: movq 416+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1512 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1500: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1508: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1504 .L1509: movl $4, %eax jmp .L1504 .L1510: movl $7, %eax jmp .L1504 .L1502: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1501 .L1506: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1506 jmp .L1501 .L1512: movl $-2, %eax jmp .L1500 .cfi_endproc .LFE8525: .size nvtxDomainRangePushEx_impl_init_v3, .-nvtxDomainRangePushEx_impl_init_v3 .section .text.nvtxDomainNameCategoryA_impl_init_v3,"axG",@progbits,nvtxDomainNameCategoryA_impl_init_v3,comdat .weak nvtxDomainNameCategoryA_impl_init_v3 .hidden nvtxDomainNameCategoryA_impl_init_v3 .type nvtxDomainNameCategoryA_impl_init_v3, @function nvtxDomainNameCategoryA_impl_init_v3: .LFB8529: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $8, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbx movl %esi, %ebp movq %rdx, %r12 movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1517 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1518 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1519 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r13 testq %rax, %rax je .L1525 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1530 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1524 movl $0, %eax jmp .L1520 .L1530: movq %r13, %rdi call dlclose@PLT movl $5, %eax jmp .L1520 .L1519: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1526 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1520: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1517: movq 448+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1516 movq %r12, %rdx movl %ebp, %esi movq %rbx, %rdi call *%rax .L1516: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L1524: .cfi_restore_state movq %r13, %rdi call dlclose@PLT movl $6, %eax jmp .L1520 .L1525: movl $4, %eax jmp .L1520 .L1526: movl $7, %eax jmp .L1520 .L1518: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1517 .L1522: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1522 jmp .L1517 .cfi_endproc .LFE8529: .size nvtxDomainNameCategoryA_impl_init_v3, .-nvtxDomainNameCategoryA_impl_init_v3 .section .text.nvtxDomainRegisterStringA_impl_init_v3,"axG",@progbits,nvtxDomainRegisterStringA_impl_init_v3,comdat .weak nvtxDomainRegisterStringA_impl_init_v3 .hidden nvtxDomainRegisterStringA_impl_init_v3 .type nvtxDomainRegisterStringA_impl_init_v3, @function nvtxDomainRegisterStringA_impl_init_v3: .LFB8531: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1532 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1533 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1534 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1540 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1546 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1539 movl $0, %eax jmp .L1535 .L1546: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1535 .L1534: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1541 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1535: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1532: movq 464+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1543 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1531: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1539: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1535 .L1540: movl $4, %eax jmp .L1535 .L1541: movl $7, %eax jmp .L1535 .L1533: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1532 .L1537: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1537 jmp .L1532 .L1543: movl $0, %eax jmp .L1531 .cfi_endproc .LFE8531: .size nvtxDomainRegisterStringA_impl_init_v3, .-nvtxDomainRegisterStringA_impl_init_v3 .section .text.nvtxDomainSyncUserCreate_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserCreate_impl_init_v3,comdat .weak nvtxDomainSyncUserCreate_impl_init_v3 .hidden nvtxDomainSyncUserCreate_impl_init_v3 .type nvtxDomainSyncUserCreate_impl_init_v3, @function nvtxDomainSyncUserCreate_impl_init_v3: .LFB8565: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1548 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1549 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1550 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1556 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1562 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1555 movl $0, %eax jmp .L1551 .L1562: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1551 .L1550: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1557 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1551: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1548: movq 512+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1559 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1547: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1555: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1551 .L1556: movl $4, %eax jmp .L1551 .L1557: movl $7, %eax jmp .L1551 .L1549: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1548 .L1553: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1553 jmp .L1548 .L1559: movl $0, %eax jmp .L1547 .cfi_endproc .LFE8565: .size nvtxDomainSyncUserCreate_impl_init_v3, .-nvtxDomainSyncUserCreate_impl_init_v3 .section .text.nvtxDomainRegisterStringW_impl_init_v3,"axG",@progbits,nvtxDomainRegisterStringW_impl_init_v3,comdat .weak nvtxDomainRegisterStringW_impl_init_v3 .hidden nvtxDomainRegisterStringW_impl_init_v3 .type nvtxDomainRegisterStringW_impl_init_v3, @function nvtxDomainRegisterStringW_impl_init_v3: .LFB8532: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1564 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1565 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1566 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1572 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1578 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1571 movl $0, %eax jmp .L1567 .L1578: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1567 .L1566: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1573 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1567: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1564: movq 472+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1575 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1563: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1571: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1567 .L1572: movl $4, %eax jmp .L1567 .L1573: movl $7, %eax jmp .L1567 .L1565: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1564 .L1569: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1569 jmp .L1564 .L1575: movl $0, %eax jmp .L1563 .cfi_endproc .LFE8532: .size nvtxDomainRegisterStringW_impl_init_v3, .-nvtxDomainRegisterStringW_impl_init_v3 .section .text.nvtxDomainRangeStartEx_impl_init_v3,"axG",@progbits,nvtxDomainRangeStartEx_impl_init_v3,comdat .weak nvtxDomainRangeStartEx_impl_init_v3 .hidden nvtxDomainRangeStartEx_impl_init_v3 .type nvtxDomainRangeStartEx_impl_init_v3, @function nvtxDomainRangeStartEx_impl_init_v3: .LFB8523: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1580 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1581 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1582 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1588 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1594 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1587 movl $0, %eax jmp .L1583 .L1594: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1583 .L1582: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1589 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1583: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1580: movq 400+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1591 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1579: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1587: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1583 .L1588: movl $4, %eax jmp .L1583 .L1589: movl $7, %eax jmp .L1583 .L1581: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1580 .L1585: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1585 jmp .L1580 .L1591: movl $0, %eax jmp .L1579 .cfi_endproc .LFE8523: .size nvtxDomainRangeStartEx_impl_init_v3, .-nvtxDomainRangeStartEx_impl_init_v3 .section .text.nvtxDomainResourceCreate_impl_init_v3,"axG",@progbits,nvtxDomainResourceCreate_impl_init_v3,comdat .weak nvtxDomainResourceCreate_impl_init_v3 .hidden nvtxDomainResourceCreate_impl_init_v3 .type nvtxDomainResourceCreate_impl_init_v3, @function nvtxDomainResourceCreate_impl_init_v3: .LFB8527: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1596 lock orq $0, (%rsp) movl $1, %eax movl $0, %edx lock cmpxchgl %edx, nvtxGlobals_v3(%rip) testl %eax, %eax jne .L1597 leaq .LC9(%rip), %rdi call getenv@PLT testq %rax, %rax je .L1598 movl $1, %esi movq %rax, %rdi call dlopen@PLT movq %rax, %r12 testq %rax, %rax je .L1604 leaq .LC10(%rip), %rsi movq %rax, %rdi call dlsym@PLT testq %rax, %rax je .L1610 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax testl %eax, %eax je .L1603 movl $0, %eax jmp .L1599 .L1610: movq %r12, %rdi call dlclose@PLT movl $5, %eax jmp .L1599 .L1598: movq InitializeInjectionNvtx2_fnptr(%rip), %rax testq %rax, %rax je .L1605 leaq nvtxGetExportTable_v3(%rip), %rdi call *%rax cmpl $1, %eax sbbl %eax, %eax andl $6, %eax .L1599: testl %eax, %eax setne %dil movzbl %dil, %edi call nvtxSetInitFunctionsToNoops_v3 lock orq $0, (%rsp) movl $2, %eax xchgl nvtxGlobals_v3(%rip), %eax .L1596: movq 432+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1607 movq %rbp, %rsi movq %rbx, %rdi call *%rax .L1595: popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1603: .cfi_restore_state movq %r12, %rdi call dlclose@PLT movl $6, %eax jmp .L1599 .L1604: movl $4, %eax jmp .L1599 .L1605: movl $7, %eax jmp .L1599 .L1597: lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax je .L1596 .L1601: call sched_yield@PLT lock orq $0, (%rsp) movl nvtxGlobals_v3(%rip), %eax cmpl $2, %eax jne .L1601 jmp .L1596 .L1607: movl $0, %eax jmp .L1595 .cfi_endproc .LFE8527: .size nvtxDomainResourceCreate_impl_init_v3, .-nvtxDomainResourceCreate_impl_init_v3 .section .text._ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC5ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .type _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: .LFB9570: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA9570 endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $8, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbx movq %rsi, %r12 leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE(%rip), %rax movq %rax, (%rdi) leaq 8(%rdi), %r13 leaq 24(%rdi), %rax movq %rax, 8(%rdi) movq $0, 16(%rdi) movb $0, 24(%rdi) call _ZNKSt9bad_alloc4whatEv@PLT movq %rax, %rbp movq %rax, %rdi call strlen@PLT movq %rax, %r8 movq 16(%rbx), %rdx movq %rbp, %rcx movl $0, %esi movq %r13, %rdi .LEHB17: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT movabsq $4611686018427387903, %rax subq 16(%rbx), %rax cmpq $1, %rax jbe .L1618 movl $2, %edx leaq .LC4(%rip), %rsi movq %r13, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT jmp .L1619 .L1618: leaq .LC3(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .LEHE17: .L1615: endbr64 movq %rax, %rbp movq %r13, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq %rbx, %rdi call _ZNSt9bad_allocD2Ev@PLT movq %rbp, %rdi .LEHB18: call _Unwind_Resume@PLT .LEHE18: .L1619: movq 8(%r12), %rdx movq (%r12), %rsi movabsq $4611686018427387903, %rax subq 16(%rbx), %rax cmpq %rdx, %rax jb .L1620 movq %r13, %rdi .LEHB19: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT jmp .L1621 .L1620: leaq .LC3(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .LEHE19: .L1621: addq $8, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE9570: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC5ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat .LLSDA9570: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE9570-.LLSDACSB9570 .LLSDACSB9570: .uleb128 .LEHB17-.LFB9570 .uleb128 .LEHE17-.LEHB17 .uleb128 .L1615-.LFB9570 .uleb128 0 .uleb128 .LEHB18-.LFB9570 .uleb128 .LEHE18-.LEHB18 .uleb128 0 .uleb128 0 .uleb128 .LEHB19-.LFB9570 .uleb128 .LEHE19-.LEHB19 .uleb128 .L1615-.LFB9570 .uleb128 0 .LLSDACSE9570: .section .text._ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC5ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat .size _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .weak _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .set _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,_ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .text .globl _Z29__device_stub__Z7reduce0PiS_iPiS_i .type _Z29__device_stub__Z7reduce0PiS_iPiS_i, @function _Z29__device_stub__Z7reduce0PiS_iPiS_i: .LFB12077: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L1626 .L1622: movq 120(%rsp), %rax subq %fs:40, %rax jne .L1627 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L1626: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7reduce0PiS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L1622 .L1627: call __stack_chk_fail@PLT .cfi_endproc .LFE12077: .size _Z29__device_stub__Z7reduce0PiS_iPiS_i, .-_Z29__device_stub__Z7reduce0PiS_iPiS_i .globl _Z7reduce0PiS_i .type _Z7reduce0PiS_i, @function _Z7reduce0PiS_i: .LFB12078: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z29__device_stub__Z7reduce0PiS_iPiS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE12078: .size _Z7reduce0PiS_i, .-_Z7reduce0PiS_i .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC11: .string "_ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_" .align 8 .LC12: .string "_ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv" .section .rodata.str1.1,"aMS",@progbits,1 .LC13: .string "_Z7reduce0PiS_i" .section .rodata.str1.8 .align 8 .LC14: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std3__45__cpo5beginE" .align 8 .LC15: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std3__45__cpo3endE" .align 8 .LC16: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std3__45__cpo6cbeginE" .align 8 .LC17: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std3__45__cpo4cendE" .align 8 .LC18: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std3__45__cpo6rbeginE" .align 8 .LC19: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std3__45__cpo4rendE" .align 8 .LC20: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std3__45__cpo7crbeginE" .align 8 .LC21: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std3__45__cpo5crendE" .align 8 .LC22: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std3__476_GLOBAL__N__dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36ignoreE" .align 8 .LC23: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std3__419piecewise_constructE" .align 8 .LC24: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std3__48in_placeE" .align 8 .LC25: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std3__47nulloptE" .align 8 .LC26: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std3__420unreachable_sentinelE" .align 8 .LC27: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo4swapE" .align 8 .LC28: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo9iter_moveE" .align 8 .LC29: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo7advanceE" .align 8 .LC30: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo5beginE" .align 8 .LC31: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo3endE" .align 8 .LC32: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo6cbeginE" .align 8 .LC33: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo4cendE" .align 8 .LC34: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo9iter_swapE" .align 8 .LC35: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo4nextE" .align 8 .LC36: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo4prevE" .align 8 .LC37: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo4dataE" .align 8 .LC38: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo5cdataE" .align 8 .LC39: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo4sizeE" .align 8 .LC40: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo5ssizeE" .align 8 .LC41: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c34cuda3std6ranges3__45__cpo8distanceE" .align 8 .LC42: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS8cuda_cub3parE" .align 8 .LC43: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS8cuda_cub10par_nosyncE" .align 8 .LC44: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS6system6detail10sequential3seqE" .align 8 .LC45: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS6system3cpp3parE" .align 8 .LC46: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS12placeholders2_1E" .align 8 .LC47: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS12placeholders2_2E" .align 8 .LC48: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS12placeholders2_3E" .align 8 .LC49: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS12placeholders2_4E" .align 8 .LC50: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS12placeholders2_5E" .align 8 .LC51: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS12placeholders2_6E" .align 8 .LC52: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS12placeholders2_7E" .align 8 .LC53: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS12placeholders2_8E" .align 8 .LC54: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS12placeholders2_9E" .align 8 .LC55: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS12placeholders3_10E" .align 8 .LC56: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS3seqE" .align 8 .LC57: .string "_ZN74_INTERNAL_dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36thrust20THRUST_200700_800_NS6deviceE" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB12084: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC11(%rip), %rdx movq %rdx, %rcx leaq _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC13(%rip), %rdx movq %rdx, %rcx leaq _Z7reduce0PiS_i(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC14(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__45__cpo5beginE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC15(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__45__cpo3endE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC16(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC17(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__45__cpo4cendE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC18(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__45__cpo6rbeginE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC19(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__45__cpo4rendE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC20(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__45__cpo7crbeginE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC21(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__45__cpo5crendE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC22(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__476_GLOBAL__N__dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36ignoreE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC23(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC24(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__48in_placeE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC25(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__47nulloptE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC26(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std3__420unreachable_sentinelE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC27(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC28(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC29(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC30(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo5beginE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC31(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo3endE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC32(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo6cbeginE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC33(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo4cendE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC34(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo9iter_swapE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC35(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo4nextE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC36(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo4prevE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC37(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo4dataE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC38(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo5cdataE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC39(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo4sizeE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC40(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo5ssizeE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC41(%rip), %rdx movq %rdx, %rcx leaq _ZN4cuda3std6ranges3__45__cpo8distanceE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC42(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS8cuda_cubL3parE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC43(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS8cuda_cubL10par_nosyncE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC44(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC45(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS6system3cppL3parE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC46(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_1E(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC47(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_2E(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC48(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_3E(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC49(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_4E(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC50(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_5E(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC51(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_6E(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC52(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_7E(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC53(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_8E(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC54(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_9E(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC55(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NS12placeholdersL3_10E(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC56(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NSL3seqE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $1, %r9d movl $0, %r8d leaq .LC57(%rip), %rdx movq %rdx, %rcx leaq _ZN6thrust20THRUST_200700_800_NSL6deviceE(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE12084: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE4dataEv,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE4dataEv,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE4dataEv .type _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE4dataEv, @function _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE4dataEv: .LFB12570: .cfi_startproc endbr64 movq 8(%rdi), %rax ret .cfi_endproc .LFE12570: .size _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE4dataEv, .-_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE4dataEv .section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat .align 2 .weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag .type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, @function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag: .LFB12662: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $16, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbx movq %rsi, %r12 movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax subq %rsi, %rdx movq %rdx, %rbp movq %rdx, (%rsp) cmpq $15, %rdx ja .L1640 movq (%rdi), %rdi cmpq $1, %rdx jne .L1636 movzbl (%rsi), %eax movb %al, (%rdi) .L1637: movq (%rsp), %rax movq %rax, 8(%rbx) movq (%rbx), %rdx movb $0, (%rdx,%rax) movq 8(%rsp), %rax subq %fs:40, %rax jne .L1641 addq $16, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1640: .cfi_restore_state movq %rsp, %rsi movl $0, %edx call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT movq %rax, %rdi movq %rax, (%rbx) movq (%rsp), %rax movq %rax, 16(%rbx) .L1635: movq %rbp, %rdx movq %r12, %rsi call memcpy@PLT jmp .L1637 .L1636: testq %rdx, %rdx je .L1637 jmp .L1635 .L1641: call __stack_chk_fail@PLT .cfi_endproc .LFE12662: .size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag .section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1 .align 8 .LC58: .string "basic_string: construction from null is not valid" .section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat .align 2 .weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_: .LFB12482: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 leaq 16(%rdi), %rax movq %rax, (%rdi) testq %rsi, %rsi je .L1645 movq %rdi, %rbp movq %rsi, %rbx movq %rsi, %rdi call strlen@PLT leaq (%rbx,%rax), %rdx movq %rbx, %rsi movq %rbp, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L1645: .cfi_restore_state leaq .LC58(%rip), %rdi call _ZSt19__throw_logic_errorPKc@PLT .cfi_endproc .LFE12482: .size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .section .text._ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE11do_allocateEmm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE11do_allocateEmm,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE11do_allocateEmm .type _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE11do_allocateEmm, @function _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE11do_allocateEmm: .LFB13370: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13370 endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $104, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rdi .LEHB20: call cudaMalloc@PLT testl %eax, %eax jne .L1659 movq 8(%rsp), %rax movq 88(%rsp), %rdx subq %fs:40, %rdx jne .L1660 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L1659: .cfi_restore_state movl %eax, %ebx call cudaGetLastError@PLT .LEHE20: movl $40, %edi call __cxa_allocate_exception@PLT movq %rax, %rbp call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %rsi leaq 16(%rsp), %rdi movq (%rax), %rax movl %ebx, %edx .LEHB21: call *48(%rax) .LEHE21: leaq 7(%rsp), %rdx leaq 48(%rsp), %rdi movq 16(%rsp), %rsi .LEHB22: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .LEHE22: leaq 48(%rsp), %rsi movq %rbp, %rdi .LEHB23: call _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .LEHE23: leaq 48(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq 16(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq 88(%rsp), %rax subq %fs:40, %rax jne .L1661 leaq _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE(%rip), %rsi movq %rbp, %rdi .LEHB24: call __cxa_throw@PLT .L1661: call __stack_chk_fail@PLT .L1656: endbr64 movq %rax, %rbx leaq 48(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT .L1650: leaq 16(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT .L1651: movq %rbp, %rdi call __cxa_free_exception@PLT movq 88(%rsp), %rax subq %fs:40, %rax je .L1652 call __stack_chk_fail@PLT .L1655: endbr64 movq %rax, %rbx jmp .L1650 .L1654: endbr64 movq %rax, %rbx jmp .L1651 .L1652: movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE24: .L1660: call __stack_chk_fail@PLT .cfi_endproc .LFE13370: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE11do_allocateEmm,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE11do_allocateEmm,comdat .LLSDA13370: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13370-.LLSDACSB13370 .LLSDACSB13370: .uleb128 .LEHB20-.LFB13370 .uleb128 .LEHE20-.LEHB20 .uleb128 0 .uleb128 0 .uleb128 .LEHB21-.LFB13370 .uleb128 .LEHE21-.LEHB21 .uleb128 .L1654-.LFB13370 .uleb128 0 .uleb128 .LEHB22-.LFB13370 .uleb128 .LEHE22-.LEHB22 .uleb128 .L1655-.LFB13370 .uleb128 0 .uleb128 .LEHB23-.LFB13370 .uleb128 .LEHE23-.LEHB23 .uleb128 .L1656-.LFB13370 .uleb128 0 .uleb128 .LEHB24-.LFB13370 .uleb128 .LEHE24-.LEHB24 .uleb128 0 .uleb128 0 .LLSDACSE13370: .section .text._ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE11do_allocateEmm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE11do_allocateEmm,comdat .size _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE11do_allocateEmm, .-_ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE11do_allocateEmm .section .text._ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE11do_allocateEmm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE11do_allocateEmm,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE11do_allocateEmm .type _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE11do_allocateEmm, @function _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE11do_allocateEmm: .LFB13304: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13304 endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $104, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax leaq 8(%rsp), %rdi .LEHB25: call cudaMalloc@PLT testl %eax, %eax jne .L1675 movq 8(%rsp), %rax movq 88(%rsp), %rdx subq %fs:40, %rdx jne .L1676 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L1675: .cfi_restore_state movl %eax, %ebx call cudaGetLastError@PLT .LEHE25: movl $40, %edi call __cxa_allocate_exception@PLT movq %rax, %rbp call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %rsi leaq 48(%rsp), %rdi movq (%rax), %rax movl %ebx, %edx .LEHB26: call *48(%rax) .LEHE26: leaq 7(%rsp), %rdx leaq 16(%rsp), %rdi movq 48(%rsp), %rsi .LEHB27: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .LEHE27: leaq 16(%rsp), %rsi movq %rbp, %rdi .LEHB28: call _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .LEHE28: leaq 16(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq 48(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq 88(%rsp), %rax subq %fs:40, %rax jne .L1677 leaq _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE(%rip), %rsi movq %rbp, %rdi .LEHB29: call __cxa_throw@PLT .L1677: call __stack_chk_fail@PLT .L1672: endbr64 movq %rax, %rbx leaq 16(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT .L1666: leaq 48(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT .L1667: movq %rbp, %rdi call __cxa_free_exception@PLT movq 88(%rsp), %rax subq %fs:40, %rax je .L1668 call __stack_chk_fail@PLT .L1671: endbr64 movq %rax, %rbx jmp .L1666 .L1670: endbr64 movq %rax, %rbx jmp .L1667 .L1668: movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE29: .L1676: call __stack_chk_fail@PLT .cfi_endproc .LFE13304: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE11do_allocateEmm,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE11do_allocateEmm,comdat .LLSDA13304: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13304-.LLSDACSB13304 .LLSDACSB13304: .uleb128 .LEHB25-.LFB13304 .uleb128 .LEHE25-.LEHB25 .uleb128 0 .uleb128 0 .uleb128 .LEHB26-.LFB13304 .uleb128 .LEHE26-.LEHB26 .uleb128 .L1670-.LFB13304 .uleb128 0 .uleb128 .LEHB27-.LFB13304 .uleb128 .LEHE27-.LEHB27 .uleb128 .L1671-.LFB13304 .uleb128 0 .uleb128 .LEHB28-.LFB13304 .uleb128 .LEHE28-.LEHB28 .uleb128 .L1672-.LFB13304 .uleb128 0 .uleb128 .LEHB29-.LFB13304 .uleb128 .LEHE29-.LEHB29 .uleb128 0 .uleb128 0 .LLSDACSE13304: .section .text._ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE11do_allocateEmm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE11do_allocateEmm,comdat .size _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE11do_allocateEmm, .-_ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE11do_allocateEmm .section .rodata._ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category7messageB5cxx11Ei.str1.1,"aMS",@progbits,1 .LC59: .string "unknown error" .LC60: .string "cudaErrorUnknown" .section .text._ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category7messageB5cxx11Ei,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category7messageB5cxx11Ei,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category7messageB5cxx11Ei .type _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category7messageB5cxx11Ei, @function _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category7messageB5cxx11Ei: .LFB8337: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA8337 endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $88, %rsp .cfi_def_cfa_offset 128 movq %rdi, %rbp movl %edx, %ebx movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl %edx, %edi .LEHB30: call cudaGetErrorString@PLT movq %rax, %r12 movl %ebx, %edi call cudaGetErrorName@PLT movq %rax, %rbx testq %r12, %r12 leaq .LC59(%rip), %rax cmove %rax, %r12 testq %rbx, %rbx leaq .LC60(%rip), %rax cmove %rax, %rbx movq %rsp, %r13 leaq 16(%rsp), %rax movq %rax, (%rsp) movq %rbx, %rdi call strlen@PLT leaq (%rbx,%rax), %rdx movq %rbx, %rsi movq %r13, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag .LEHE30: movabsq $4611686018427387903, %rax subq 8(%rsp), %rax cmpq $1, %rax jbe .L1714 movq %rsp, %rdi movl $2, %edx leaq .LC4(%rip), %rsi .LEHB31: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT jmp .L1715 .L1714: movq 72(%rsp), %rax subq %fs:40, %rax jne .L1716 leaq .LC3(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .LEHE31: .L1709: endbr64 movq %rax, %rbx jmp .L1704 .L1716: call __stack_chk_fail@PLT .L1715: leaq 48(%rsp), %rdx movq %rdx, 32(%rsp) movq (%rax), %rcx leaq 16(%rax), %rdx cmpq %rdx, %rcx je .L1717 movq %rcx, 32(%rsp) movq 16(%rax), %rcx movq %rcx, 48(%rsp) .L1690: movq 8(%rax), %rcx movq %rcx, 40(%rsp) movq %rdx, (%rax) movq $0, 8(%rax) movb $0, 16(%rax) movq %r12, %rdi call strlen@PLT movq %rax, %rdx movabsq $4611686018427387903, %rax subq 40(%rsp), %rax cmpq %rdx, %rax jb .L1718 leaq 32(%rsp), %rdi movq %r12, %rsi .LEHB32: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT jmp .L1719 .L1717: leaq 48(%rsp), %r8 movq 8(%rax), %rbx leaq 1(%rbx), %rsi movq %r8, %r9 movq %rdx, %rcx cmpl $8, %esi jnb .L1720 .L1684: movl $0, %edi testb $4, %sil je .L1687 movl (%rcx), %edi movl %edi, (%r9) movl $4, %edi .L1687: testb $2, %sil je .L1688 movzwl (%rcx,%rdi), %r8d movw %r8w, (%r9,%rdi) addq $2, %rdi .L1688: testb $1, %sil je .L1690 movzbl (%rcx,%rdi), %ecx movb %cl, (%r9,%rdi) jmp .L1690 .L1720: movl %esi, %r10d andl $-8, %r10d movl $0, %ecx .L1685: movl %ecx, %edi movq (%rdx,%rdi), %r9 movq %r9, (%r8,%rdi) addl $8, %ecx cmpl %r10d, %ecx jb .L1685 movl %ecx, %ecx leaq (%r8,%rcx), %r9 addq %rdx, %rcx jmp .L1684 .L1718: movq 72(%rsp), %rax subq %fs:40, %rax jne .L1721 leaq .LC3(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .LEHE32: .L1710: endbr64 movq %rax, %rbx leaq 32(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT .L1704: movq %rsp, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq 72(%rsp), %rax subq %fs:40, %rax je .L1705 call __stack_chk_fail@PLT .L1721: call __stack_chk_fail@PLT .L1719: leaq 16(%rbp), %rcx movq %rcx, 0(%rbp) movq (%rax), %rdx leaq 16(%rax), %rsi cmpq %rsi, %rdx je .L1722 movq %rdx, 0(%rbp) movq 16(%rax), %rdx movq %rdx, 16(%rbp) .L1700: movq 8(%rax), %rdx movq %rdx, 8(%rbp) movq %rsi, (%rax) movq $0, 8(%rax) movb $0, 16(%rax) movq 32(%rsp), %rdi leaq 48(%rsp), %rax cmpq %rax, %rdi je .L1701 movq 48(%rsp), %rax leaq 1(%rax), %rsi call _ZdlPvm@PLT .L1701: movq (%rsp), %rdi leaq 16(%rsp), %rax cmpq %rax, %rdi je .L1678 movq 16(%rsp), %rax leaq 1(%rax), %rsi call _ZdlPvm@PLT .L1678: movq 72(%rsp), %rax subq %fs:40, %rax jne .L1723 movq %rbp, %rax addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L1722: .cfi_restore_state movq 8(%rax), %rbx leaq 1(%rbx), %rdx cmpl $8, %edx jnb .L1694 testb $4, %dl jne .L1724 testl %edx, %edx je .L1700 movzbl 16(%rax), %edi movb %dil, 16(%rbp) testb $2, %dl je .L1700 movl %edx, %edx movzwl -2(%rsi,%rdx), %edi movw %di, -2(%rcx,%rdx) jmp .L1700 .L1724: movl 16(%rax), %edi movl %edi, 16(%rbp) movl %edx, %edx movl -4(%rsi,%rdx), %edi movl %edi, -4(%rcx,%rdx) jmp .L1700 .L1694: movq 16(%rax), %rdi movq %rdi, 16(%rbp) movl %edx, %edi movq -8(%rsi,%rdi), %r8 movq %r8, -8(%rcx,%rdi) leaq 8(%rcx), %r8 andq $-8, %r8 subq %r8, %rcx movq %rsi, %r10 subq %rcx, %r10 addl %ecx, %edx andl $-8, %edx cmpl $8, %edx jb .L1700 andl $-8, %edx movl $0, %ecx .L1698: movl %ecx, %edi movq (%r10,%rdi), %r9 movq %r9, (%r8,%rdi) addl $8, %ecx cmpl %edx, %ecx jb .L1698 jmp .L1700 .L1705: movq %rbx, %rdi .LEHB33: call _Unwind_Resume@PLT .LEHE33: .L1723: call __stack_chk_fail@PLT .cfi_endproc .LFE8337: .section .gcc_except_table._ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category7messageB5cxx11Ei,"aG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category7messageB5cxx11Ei,comdat .LLSDA8337: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE8337-.LLSDACSB8337 .LLSDACSB8337: .uleb128 .LEHB30-.LFB8337 .uleb128 .LEHE30-.LEHB30 .uleb128 0 .uleb128 0 .uleb128 .LEHB31-.LFB8337 .uleb128 .LEHE31-.LEHB31 .uleb128 .L1709-.LFB8337 .uleb128 0 .uleb128 .LEHB32-.LFB8337 .uleb128 .LEHE32-.LEHB32 .uleb128 .L1710-.LFB8337 .uleb128 0 .uleb128 .LEHB33-.LFB8337 .uleb128 .LEHE33-.LEHB33 .uleb128 0 .uleb128 0 .LLSDACSE8337: .section .text._ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category7messageB5cxx11Ei,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category7messageB5cxx11Ei,comdat .size _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category7messageB5cxx11Ei, .-_ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category7messageB5cxx11Ei .section .rodata._ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11Ei.str1.1,"aMS",@progbits,1 .LC61: .string "Unknown error" .section .text._ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11Ei,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11Ei,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11Ei .type _ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11Ei, @function _ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11Ei: .LFB8272: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA8272 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $16, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbx movl %edx, %ebp movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax movzbl _ZGVZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err(%rip), %eax testb %al, %al jne .L1726 leaq _ZGVZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax jne .L1738 .L1726: movl %ebp, %edi call strerror@PLT movq %rax, %rbp testq %rax, %rax je .L1727 leaq 16(%rbx), %rax movq %rax, (%rbx) movq %rbp, %rdi call strlen@PLT leaq 0(%rbp,%rax), %rdx movq %rbp, %rsi movq %rbx, %rdi .LEHB34: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag .LEHE34: .L1725: movq 8(%rsp), %rax subq %fs:40, %rax jne .L1739 movq %rbx, %rax addq $16, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1738: .cfi_restore_state leaq 16+_ZZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err(%rip), %rax movq %rax, _ZZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err(%rip) leaq 13+.LC61(%rip), %rdx leaq -13(%rdx), %rsi leaq -16(%rax), %rdi .LEHB35: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag .LEHE35: leaq __dso_handle(%rip), %rdx leaq _ZZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err(%rip), %rsi movq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED1Ev@GOTPCREL(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err(%rip), %rdi call __cxa_guard_release@PLT jmp .L1726 .L1727: leaq 16(%rbx), %rdi movq %rdi, (%rbx) movq _ZZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err(%rip), %r12 movq 8+_ZZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err(%rip), %rbp movq %rbp, (%rsp) cmpq $15, %rbp ja .L1740 cmpq $1, %rbp jne .L1731 movzbl (%r12), %eax movb %al, 16(%rbx) .L1732: movq (%rsp), %rax movq %rax, 8(%rbx) movq (%rbx), %rdx movb $0, (%rdx,%rax) jmp .L1725 .L1740: movq %rsp, %rsi movl $0, %edx movq %rbx, %rdi .LEHB36: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT movq %rax, %rdi movq %rax, (%rbx) movq (%rsp), %rax movq %rax, 16(%rbx) .L1730: movq %rbp, %rdx movq %r12, %rsi call memcpy@PLT jmp .L1732 .L1731: testq %rbp, %rbp je .L1732 jmp .L1730 .L1736: endbr64 movq %rax, %rbx leaq _ZGVZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err(%rip), %rdi call __cxa_guard_abort@PLT movq 8(%rsp), %rax subq %fs:40, %rax je .L1734 call __stack_chk_fail@PLT .L1734: movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE36: .L1739: call __stack_chk_fail@PLT .cfi_endproc .LFE8272: .section .gcc_except_table._ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11Ei,"aG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11Ei,comdat .LLSDA8272: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE8272-.LLSDACSB8272 .LLSDACSB8272: .uleb128 .LEHB34-.LFB8272 .uleb128 .LEHE34-.LEHB34 .uleb128 0 .uleb128 0 .uleb128 .LEHB35-.LFB8272 .uleb128 .LEHE35-.LEHB35 .uleb128 .L1736-.LFB8272 .uleb128 0 .uleb128 .LEHB36-.LFB8272 .uleb128 .LEHE36-.LEHB36 .uleb128 0 .uleb128 0 .LLSDACSE8272: .section .text._ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11Ei,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11Ei,comdat .size _ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11Ei, .-_ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11Ei .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv .type _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv, @function _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv: .LFB12801: .cfi_startproc endbr64 movq 24(%rdi), %rdx movq 8(%rdi), %rax leaq (%rax,%rdx,4), %rax ret .cfi_endproc .LFE12801: .size _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv, .-_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE3endEv,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE3endEv,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE3endEv .type _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE3endEv, @function _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE3endEv: .LFB12934: .cfi_startproc endbr64 movq 24(%rdi), %rdx movq 8(%rdi), %rax leaq (%rax,%rdx,4), %rax ret .cfi_endproc .LFE12934: .size _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE3endEv, .-_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE3endEv .section .text._ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5beginEv,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5beginEv,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5beginEv .type _ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5beginEv, @function _ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5beginEv: .LFB12956: .cfi_startproc endbr64 movq 8(%rdi), %rax ret .cfi_endproc .LFE12956: .size _ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5beginEv, .-_ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5beginEv .section .text._ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv,"axG",@progbits,_ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv,comdat .align 2 .weak _ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv .type _ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv, @function _ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv: .LFB12957: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx call _ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5beginEv movq 24(%rbx), %rdx leaq (%rax,%rdx,4), %rax popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE12957: .size _ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv, .-_ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv .section .text._ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE10deallocateEv,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE10deallocateEv,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE10deallocateEv .type _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE10deallocateEv, @function _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE10deallocateEv: .LFB13048: .cfi_startproc endbr64 movq 16(%rdi), %rsi testq %rsi, %rsi jne .L1752 ret .L1752: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx salq $2, %rsi movq 8(%rdi), %rdi call _ZdlPvm@PLT movq $0, 8(%rbx) movq $0, 16(%rbx) popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE13048: .size _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE10deallocateEv, .-_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE10deallocateEv .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED2Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED2Ev .type _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED2Ev, @function _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED2Ev: .LFB12782: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE10deallocateEv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE12782: .size _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED2Ev, .-_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED2Ev .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED1Ev .set _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED1Ev,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED2Ev .section .text._ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE8allocateEm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE8allocateEm,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE8allocateEm .type _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE8allocateEm, @function _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE8allocateEm: .LFB13049: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbp movq %rsi, %rbx movl $0, %eax testq %rsi, %rsi jne .L1761 .L1756: movq %rax, 8(%rbp) movq %rbx, 16(%rbp) addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L1761: .cfi_restore_state movq %rsi, %rax shrq $61, %rax jne .L1762 leaq 0(,%rsi,4), %rdi call _Znwm@PLT jmp .L1756 .L1762: shrq $62, %rbx je .L1758 call _ZSt28__throw_bad_array_new_lengthv@PLT .L1758: call _ZSt17__throw_bad_allocv@PLT .cfi_endproc .LFE13049: .size _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE8allocateEm, .-_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE8allocateEm .section .text._ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv .type _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv, @function _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv: .LFB13072: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13072 endbr64 cmpq $0, 16(%rdi) jne .L1772 ret .L1772: pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq 8(%rdi), %rdi call cudaFree@PLT movl %eax, %ebp testl %eax, %eax jne .L1773 movq $0, 8(%rbx) movq $0, 16(%rbx) popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1773: .cfi_restore_state call cudaGetLastError@PLT movl $64, %edi call __cxa_allocate_exception@PLT movq %rax, %rbx call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %r12 leaq .LC8(%rip), %rsi movq %rbx, %rdi .LEHB37: call _ZNSt13runtime_errorC2EPKc@PLT .LEHE37: leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, (%rbx) movl %ebp, 16(%rbx) movq %r12, 24(%rbx) leaq 48(%rbx), %rax movq %rax, 32(%rbx) movq $0, 40(%rbx) movb $0, 48(%rbx) leaq _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rsi movq %rbx, %rdi call __cxa_throw@PLT .L1767: endbr64 movq %rbx, %rdi call __cxa_free_exception@PLT call _ZSt9terminatev@PLT .cfi_endproc .LFE13072: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv,comdat .LLSDA13072: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13072-.LLSDACSB13072 .LLSDACSB13072: .uleb128 .LEHB37-.LFB13072 .uleb128 .LEHE37-.LEHB37 .uleb128 .L1767-.LFB13072 .uleb128 0 .LLSDACSE13072: .section .text._ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv,comdat .size _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv, .-_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED2Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED2Ev .type _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED2Ev, @function _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED2Ev: .LFB12788: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE12788: .size _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED2Ev, .-_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED2Ev .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED1Ev .set _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED1Ev,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED2Ev .section .text._ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm .type _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm, @function _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm: .LFB13078: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13078 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $96, %rsp .cfi_def_cfa_offset 128 movq %rdi, %r12 movq %rsi, %rbx movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax testq %rsi, %rsi je .L1785 leaq 0(,%rsi,4), %rsi leaq 8(%rsp), %rdi .LEHB38: call cudaMalloc@PLT movl %eax, %ebp testl %eax, %eax jne .L1790 movq 8(%rsp), %rax jmp .L1777 .L1790: call cudaGetLastError@PLT .LEHE38: movl $40, %edi call __cxa_allocate_exception@PLT movq %rax, %r12 call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %rsi leaq 48(%rsp), %rdi movq (%rax), %rax movl %ebp, %edx .LEHB39: call *48(%rax) .LEHE39: leaq 7(%rsp), %rdx leaq 16(%rsp), %rdi movq 48(%rsp), %rsi .LEHB40: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .LEHE40: leaq 16(%rsp), %rsi movq %r12, %rdi .LEHB41: call _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .LEHE41: leaq 16(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq 48(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq 88(%rsp), %rax subq %fs:40, %rax jne .L1791 leaq _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE(%rip), %rsi movq %r12, %rdi .LEHB42: call __cxa_throw@PLT .L1791: call __stack_chk_fail@PLT .L1788: endbr64 movq %rax, %rbx leaq 16(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT .L1781: leaq 48(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT .L1782: movq %r12, %rdi call __cxa_free_exception@PLT movq 88(%rsp), %rax subq %fs:40, %rax je .L1783 call __stack_chk_fail@PLT .L1787: endbr64 movq %rax, %rbx jmp .L1781 .L1786: endbr64 movq %rax, %rbx jmp .L1782 .L1783: movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE42: .L1785: movl $0, %eax .L1777: movq %rax, 8(%r12) movq %rbx, 16(%r12) movq 88(%rsp), %rax subq %fs:40, %rax jne .L1792 addq $96, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1792: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE13078: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm,comdat .LLSDA13078: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13078-.LLSDACSB13078 .LLSDACSB13078: .uleb128 .LEHB38-.LFB13078 .uleb128 .LEHE38-.LEHB38 .uleb128 0 .uleb128 0 .uleb128 .LEHB39-.LFB13078 .uleb128 .LEHE39-.LEHB39 .uleb128 .L1786-.LFB13078 .uleb128 0 .uleb128 .LEHB40-.LFB13078 .uleb128 .LEHE40-.LEHB40 .uleb128 .L1787-.LFB13078 .uleb128 0 .uleb128 .LEHB41-.LFB13078 .uleb128 .LEHE41-.LEHB41 .uleb128 .L1788-.LFB13078 .uleb128 0 .uleb128 .LEHB42-.LFB13078 .uleb128 .LEHE42-.LEHB42 .uleb128 0 .uleb128 0 .LLSDACSE13078: .section .text._ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm,comdat .size _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm, .-_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm .section .text._ZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_v,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_v,comdat .weak _ZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_v .type _ZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_v, @function _ZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_v: .LFB13127: .cfi_startproc endbr64 movzbl _ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource(%rip), %eax testb %al, %al je .L1800 leaq _ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource(%rip), %rax ret .L1800: subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax jne .L1801 .L1794: leaq _ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource(%rip), %rax addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L1801: .cfi_restore_state leaq 16+_ZTVN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE(%rip), %rax movq %rax, _ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource(%rip) movzbl _ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource(%rip), %eax testb %al, %al je .L1802 .L1795: leaq _ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource(%rip), %rax movq %rax, 8+_ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource(%rip) leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource(%rip), %rdi call __cxa_guard_release@PLT jmp .L1794 .L1802: leaq _ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L1795 leaq __dso_handle(%rip), %rdx leaq _ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource(%rip), %rsi leaq _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED1Ev(%rip), %rdi call __cxa_atexit@PLT leaq _ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource(%rip), %rdi call __cxa_guard_release@PLT jmp .L1795 .cfi_endproc .LFE13127: .size _ZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_v, .-_ZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_v .section .rodata._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorIPKiEEEEvmT_SB_RNS1_18contiguous_storageIiS4_EE.str1.8,"aMS",@progbits,1 .align 8 .LC62: .string "assignment exceeds max_size()." .align 8 .LC63: .string "__copy::trivial_device_copy H->D: failed" .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorIPKiEEEEvmT_SB_RNS1_18contiguous_storageIiS4_EE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorIPKiEEEEvmT_SB_RNS1_18contiguous_storageIiS4_EE,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorIPKiEEEEvmT_SB_RNS1_18contiguous_storageIiS4_EE .type _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorIPKiEEEEvmT_SB_RNS1_18contiguous_storageIiS4_EE, @function _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorIPKiEEEEvmT_SB_RNS1_18contiguous_storageIiS4_EE: .LFB13156: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13156 endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $8, %rsp .cfi_def_cfa_offset 48 movq %r8, %rbp testq %rsi, %rsi je .L1817 movq %rdx, %rbx movq %rcx, %r12 movq 16(%rdi), %rax addq %rax, %rax cmpq %rsi, %rax cmovb %rsi, %rax cmpq %rsi, %rax jb .L1818 movq %rax, %rsi movq %r8, %rdi .LEHB43: call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm .LEHE43: movq 8(%rbp), %rdi movq %rbx, %rdx subq %r12, %rdx jns .L1803 andq $-4, %rdx negq %rdx movl $1, %r8d movl $1, %ecx movq %rbx, %rsi .LEHB44: call cudaMemcpyAsync@PLT .LEHE44: jmp .L1819 .L1817: movq %r8, %rdi call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv jmp .L1803 .L1818: movl $16, %edi call __cxa_allocate_exception@PLT movq %rax, %rbx leaq .LC62(%rip), %rsi movq %rax, %rdi .LEHB45: call _ZNSt12length_errorC1EPKc@PLT .LEHE45: movq _ZNSt12length_errorD1Ev@GOTPCREL(%rip), %rdx leaq _ZTISt12length_error(%rip), %rsi movq %rbx, %rdi .LEHB46: call __cxa_throw@PLT .LEHE46: .L1819: movl %eax, %ebx movl $1, %edi .LEHB47: call cudaStreamSynchronize@PLT call cudaGetLastError@PLT .LEHE47: testl %ebx, %ebx jne .L1820 .L1803: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L1820: .cfi_restore_state movl $64, %edi call __cxa_allocate_exception@PLT movq %rax, %r12 call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %r13 leaq .LC63(%rip), %rsi movq %r12, %rdi .LEHB48: call _ZNSt13runtime_errorC2EPKc@PLT .LEHE48: leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, (%r12) movl %ebx, 16(%r12) movq %r13, 24(%r12) leaq 48(%r12), %rax movq %rax, 32(%r12) movq $0, 40(%r12) movb $0, 48(%r12) leaq _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rsi movq %r12, %rdi .LEHB49: call __cxa_throw@PLT .LEHE49: .L1813: endbr64 movq %rax, %rdi jmp .L1809 .L1815: endbr64 movq %rax, %rbx movq %r12, %rdi call __cxa_free_exception@PLT movq %rbx, %rdi .L1809: call __cxa_begin_catch@PLT movq %rbp, %rdi call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv .LEHB50: call __cxa_rethrow@PLT .LEHE50: .L1814: endbr64 movq %rax, %rbx call __cxa_end_catch@PLT movq %rbx, %rdi .LEHB51: call _Unwind_Resume@PLT .L1812: endbr64 movq %rax, %rbp movq %rbx, %rdi call __cxa_free_exception@PLT movq %rbp, %rdi call _Unwind_Resume@PLT .LEHE51: .cfi_endproc .LFE13156: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorIPKiEEEEvmT_SB_RNS1_18contiguous_storageIiS4_EE,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorIPKiEEEEvmT_SB_RNS1_18contiguous_storageIiS4_EE,comdat .align 4 .LLSDA13156: .byte 0xff .byte 0x9b .uleb128 .LLSDATT13156-.LLSDATTD13156 .LLSDATTD13156: .byte 0x1 .uleb128 .LLSDACSE13156-.LLSDACSB13156 .LLSDACSB13156: .uleb128 .LEHB43-.LFB13156 .uleb128 .LEHE43-.LEHB43 .uleb128 0 .uleb128 0 .uleb128 .LEHB44-.LFB13156 .uleb128 .LEHE44-.LEHB44 .uleb128 .L1813-.LFB13156 .uleb128 0x1 .uleb128 .LEHB45-.LFB13156 .uleb128 .LEHE45-.LEHB45 .uleb128 .L1812-.LFB13156 .uleb128 0 .uleb128 .LEHB46-.LFB13156 .uleb128 .LEHE46-.LEHB46 .uleb128 0 .uleb128 0 .uleb128 .LEHB47-.LFB13156 .uleb128 .LEHE47-.LEHB47 .uleb128 .L1813-.LFB13156 .uleb128 0x1 .uleb128 .LEHB48-.LFB13156 .uleb128 .LEHE48-.LEHB48 .uleb128 .L1815-.LFB13156 .uleb128 0x3 .uleb128 .LEHB49-.LFB13156 .uleb128 .LEHE49-.LEHB49 .uleb128 .L1813-.LFB13156 .uleb128 0x1 .uleb128 .LEHB50-.LFB13156 .uleb128 .LEHE50-.LEHB50 .uleb128 .L1814-.LFB13156 .uleb128 0 .uleb128 .LEHB51-.LFB13156 .uleb128 .LEHE51-.LEHB51 .uleb128 0 .uleb128 0 .LLSDACSE13156: .byte 0x1 .byte 0 .byte 0 .byte 0x7d .align 4 .long 0 .LLSDATT13156: .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorIPKiEEEEvmT_SB_RNS1_18contiguous_storageIiS4_EE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorIPKiEEEEvmT_SB_RNS1_18contiguous_storageIiS4_EE,comdat .size _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorIPKiEEEEvmT_SB_RNS1_18contiguous_storageIiS4_EE, .-_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorIPKiEEEEvmT_SB_RNS1_18contiguous_storageIiS4_EE .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub18synchronize_streamINS1_3tagEEE9cudaErrorRNS1_16execution_policyIT_EE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub18synchronize_streamINS1_3tagEEE9cudaErrorRNS1_16execution_policyIT_EE,comdat .weak _ZN6thrust20THRUST_200700_800_NS8cuda_cub18synchronize_streamINS1_3tagEEE9cudaErrorRNS1_16execution_policyIT_EE .type _ZN6thrust20THRUST_200700_800_NS8cuda_cub18synchronize_streamINS1_3tagEEE9cudaErrorRNS1_16execution_policyIT_EE, @function _ZN6thrust20THRUST_200700_800_NS8cuda_cub18synchronize_streamINS1_3tagEEE9cudaErrorRNS1_16execution_policyIT_EE: .LFB13605: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movl $1, %edi call cudaStreamSynchronize@PLT movl %eax, %ebx call cudaGetLastError@PLT testl %ebx, %ebx jne .L1824 testl %eax, %eax jne .L1821 .L1824: movl %ebx, %eax .L1821: popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE13605: .size _ZN6thrust20THRUST_200700_800_NS8cuda_cub18synchronize_streamINS1_3tagEEE9cudaErrorRNS1_16execution_policyIT_EE, .-_ZN6thrust20THRUST_200700_800_NS8cuda_cub18synchronize_streamINS1_3tagEEE9cudaErrorRNS1_16execution_policyIT_EE .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub29trivial_copy_device_to_deviceINS1_16execution_policyINS1_3tagEEEiEE9cudaErrorRT_PT0_PKS9_m,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub29trivial_copy_device_to_deviceINS1_16execution_policyINS1_3tagEEEiEE9cudaErrorRT_PT0_PKS9_m,comdat .weak _ZN6thrust20THRUST_200700_800_NS8cuda_cub29trivial_copy_device_to_deviceINS1_16execution_policyINS1_3tagEEEiEE9cudaErrorRT_PT0_PKS9_m .type _ZN6thrust20THRUST_200700_800_NS8cuda_cub29trivial_copy_device_to_deviceINS1_16execution_policyINS1_3tagEEEiEE9cudaErrorRT_PT0_PKS9_m, @function _ZN6thrust20THRUST_200700_800_NS8cuda_cub29trivial_copy_device_to_deviceINS1_16execution_policyINS1_3tagEEEiEE9cudaErrorRT_PT0_PKS9_m: .LFB13465: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movl $0, %ebp testq %rcx, %rcx jne .L1830 .L1826: movl %ebp, %eax addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L1830: .cfi_restore_state movq %rdi, %rbx movq %rsi, %rdi movq %rdx, %rsi leaq 0(,%rcx,4), %rdx movl $1, %r8d movl $3, %ecx call cudaMemcpyAsync@PLT movl %eax, %ebp movq %rbx, %rdi call _ZN6thrust20THRUST_200700_800_NS8cuda_cub18synchronize_streamINS1_3tagEEE9cudaErrorRNS1_16execution_policyIT_EE jmp .L1826 .cfi_endproc .LFE13465: .size _ZN6thrust20THRUST_200700_800_NS8cuda_cub29trivial_copy_device_to_deviceINS1_16execution_policyINS1_3tagEEEiEE9cudaErrorRT_PT0_PKS9_m, .-_ZN6thrust20THRUST_200700_800_NS8cuda_cub29trivial_copy_device_to_deviceINS1_16execution_policyINS1_3tagEEEiEE9cudaErrorRT_PT0_PKS9_m .section .rodata._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_7pointerIiS4_NS0_11use_defaultES8_EEEENS6_INS0_10device_ptrIiEEEEEET1_RNS1_16execution_policyIT_EET0_SJ_SE_.str1.1,"aMS",@progbits,1 .LC64: .string "__copy:: D->D: failed" .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_7pointerIiS4_NS0_11use_defaultES8_EEEENS6_INS0_10device_ptrIiEEEEEET1_RNS1_16execution_policyIT_EET0_SJ_SE_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_7pointerIiS4_NS0_11use_defaultES8_EEEENS6_INS0_10device_ptrIiEEEEEET1_RNS1_16execution_policyIT_EET0_SJ_SE_,comdat .weak _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_7pointerIiS4_NS0_11use_defaultES8_EEEENS6_INS0_10device_ptrIiEEEEEET1_RNS1_16execution_policyIT_EET0_SJ_SE_ .type _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_7pointerIiS4_NS0_11use_defaultES8_EEEENS6_INS0_10device_ptrIiEEEEEET1_RNS1_16execution_policyIT_EET0_SJ_SE_, @function _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_7pointerIiS4_NS0_11use_defaultES8_EEEENS6_INS0_10device_ptrIiEEEEEET1_RNS1_16execution_policyIT_EET0_SJ_SE_: .LFB13347: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13347 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rcx, %rbx subq %rsi, %rdx movq %rdx, %rbp testq %rdx, %rdx jg .L1836 .L1832: leaq (%rbx,%rbp), %rax popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1836: .cfi_restore_state movq %rdx, %rcx sarq $2, %rcx movq %rsi, %rdx movq %rbx, %rsi .LEHB52: call _ZN6thrust20THRUST_200700_800_NS8cuda_cub29trivial_copy_device_to_deviceINS1_16execution_policyINS1_3tagEEEiEE9cudaErrorRT_PT0_PKS9_m movl %eax, %r12d call cudaGetLastError@PLT .LEHE52: testl %r12d, %r12d je .L1832 movl $64, %edi call __cxa_allocate_exception@PLT movq %rax, %rbx call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %rbp leaq .LC64(%rip), %rsi movq %rbx, %rdi .LEHB53: call _ZNSt13runtime_errorC2EPKc@PLT .LEHE53: leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, (%rbx) movl %r12d, 16(%rbx) movq %rbp, 24(%rbx) leaq 48(%rbx), %rax movq %rax, 32(%rbx) movq $0, 40(%rbx) movb $0, 48(%rbx) leaq _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rsi movq %rbx, %rdi .LEHB54: call __cxa_throw@PLT .L1834: endbr64 movq %rax, %rbp movq %rbx, %rdi call __cxa_free_exception@PLT movq %rbp, %rdi call _Unwind_Resume@PLT .LEHE54: .cfi_endproc .LFE13347: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_7pointerIiS4_NS0_11use_defaultES8_EEEENS6_INS0_10device_ptrIiEEEEEET1_RNS1_16execution_policyIT_EET0_SJ_SE_,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_7pointerIiS4_NS0_11use_defaultES8_EEEENS6_INS0_10device_ptrIiEEEEEET1_RNS1_16execution_policyIT_EET0_SJ_SE_,comdat .LLSDA13347: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13347-.LLSDACSB13347 .LLSDACSB13347: .uleb128 .LEHB52-.LFB13347 .uleb128 .LEHE52-.LEHB52 .uleb128 0 .uleb128 0 .uleb128 .LEHB53-.LFB13347 .uleb128 .LEHE53-.LEHB53 .uleb128 .L1834-.LFB13347 .uleb128 0 .uleb128 .LEHB54-.LFB13347 .uleb128 .LEHE54-.LEHB54 .uleb128 0 .uleb128 0 .LLSDACSE13347: .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_7pointerIiS4_NS0_11use_defaultES8_EEEENS6_INS0_10device_ptrIiEEEEEET1_RNS1_16execution_policyIT_EET0_SJ_SE_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_7pointerIiS4_NS0_11use_defaultES8_EEEENS6_INS0_10device_ptrIiEEEEEET1_RNS1_16execution_policyIT_EET0_SJ_SE_,comdat .size _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_7pointerIiS4_NS0_11use_defaultES8_EEEENS6_INS0_10device_ptrIiEEEEEET1_RNS1_16execution_policyIT_EET0_SJ_SE_, .-_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_7pointerIiS4_NS0_11use_defaultES8_EEEENS6_INS0_10device_ptrIiEEEEEET1_RNS1_16execution_policyIT_EET0_SJ_SE_ .section .rodata._ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED2Ev.str1.1,"aMS",@progbits,1 .LC65: .string "CCCL" .section .text._ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED2Ev,"axG",@progbits,_ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED5Ev,comdat .align 2 .weak _ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED2Ev .type _ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED2Ev, @function _ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED2Ev: .LFB13618: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13618 endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movzbl _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %eax testb %al, %al je .L1843 .L1838: movq _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi movq 424+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1837 call *%rax .L1837: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L1843: .cfi_restore_state leaq _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L1838 movq 480+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1841 leaq .LC65(%rip), %rdi call *%rax .L1839: movq %rax, _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip) leaq _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi call __cxa_guard_release@PLT jmp .L1838 .L1841: movl $0, %eax jmp .L1839 .cfi_endproc .LFE13618: .section .gcc_except_table._ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED2Ev,"aG",@progbits,_ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED5Ev,comdat .LLSDA13618: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13618-.LLSDACSB13618 .LLSDACSB13618: .LLSDACSE13618: .section .text._ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED2Ev,"axG",@progbits,_ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED5Ev,comdat .size _ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED2Ev, .-_ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED2Ev .weak _ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED1Ev .set _ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED1Ev,_ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED2Ev .section .rodata._ZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_st.str1.1,"aMS",@progbits,1 .LC66: .string "cub::DeviceFor::Bulk" .section .text._ZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_st,"axG",@progbits,_ZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_st,comdat .weak _ZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_st .type _ZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_st, @function _ZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_st: .LFB13475: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13475 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $104, %rsp .cfi_def_cfa_offset 160 movq %rdi, %r12 movq %rsi, %r14 movq %rdx, %r13 movq %rcx, %r15 movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax movb $0, 10(%rsp) movb $0, 11(%rsp) movzbl _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name(%rip), %eax testb %al, %al je .L1884 .L1845: movzbl _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip), %eax testb %al, %al je .L1885 .L1849: cmpb $0, 11(%rsp) jne .L1886 .L1850: movzbl _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %eax testb %al, %al je .L1887 .L1854: movq _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi movq 416+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1856 leaq _ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip), %rsi call *%rax .L1856: movb $1, 11(%rsp) movl $0, 12(%rsp) leaq 12(%rsp), %rdi .LEHB55: call _ZN3cub17CUB_200700_800_NS10PtxVersionERi .LEHE55: jmp .L1888 .L1884: leaq _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L1845 movzbl _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %eax testb %al, %al je .L1889 .L1846: movq _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi movq 464+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1872 leaq .LC66(%rip), %rsi call *%rax .L1848: movq %rax, _ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name(%rip) leaq _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name(%rip), %rdi call __cxa_guard_release@PLT jmp .L1845 .L1889: leaq _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L1846 movq 480+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1871 leaq .LC65(%rip), %rdi call *%rax .L1847: movq %rax, _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip) leaq _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi call __cxa_guard_release@PLT jmp .L1846 .L1871: movl $0, %eax jmp .L1847 .L1872: movl $0, %eax jmp .L1848 .L1885: leaq _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L1849 movw $3, _ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip) movw $48, 2+_ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip) movl $0, 4+_ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip) movl $0, 8+_ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip) movl $0, 12+_ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip) movl $0, 16+_ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip) movl $0, 20+_ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip) movq $0, 24+_ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip) movq _ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name(%rip), %rax movq %rax, 40+_ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip) movl $3, 32+_ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip) leaq _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr(%rip), %rdi call __cxa_guard_release@PLT jmp .L1849 .L1886: movzbl _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %eax testb %al, %al je .L1890 .L1851: movq _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi movq 424+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1853 call *%rax .L1853: movb $0, 11(%rsp) jmp .L1850 .L1890: leaq _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L1851 movq 480+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1873 leaq .LC65(%rip), %rdi call *%rax .L1852: movq %rax, _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip) leaq _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi call __cxa_guard_release@PLT jmp .L1851 .L1873: movl $0, %eax jmp .L1852 .L1887: leaq _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L1854 movq 480+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1874 leaq .LC65(%rip), %rdi call *%rax .L1855: movq %rax, _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip) leaq _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi call __cxa_guard_release@PLT jmp .L1854 .L1874: movl $0, %eax jmp .L1855 .L1888: movl %eax, %ebp .LEHB56: call cudaGetLastError@PLT .LEHE56: movl %eax, %ebx testl %ebp, %ebp jne .L1879 testl %eax, %eax je .L1879 .L1857: movzbl _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %eax testb %al, %al je .L1891 .L1865: movq _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi movq 424+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1844 call *%rax .L1844: movq 88(%rsp), %rax subq %fs:40, %rax jne .L1892 movl %ebx, %eax addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L1879: .cfi_restore_state movl %ebp, %ebx testl %ebp, %ebp jne .L1857 movq %r14, 24(%rsp) movl %r13d, 32(%rsp) testq %r12, %r12 je .L1859 testl $511, %r12d setne %al movzbl %al, %eax movq %r12, %rdx shrq $9, %rdx addq %rdx, %rax movl %eax, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $256, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movq %r15, %r9 movl $0, %r8d movq 60(%rsp), %rdx movl $1, %ecx movq 48(%rsp), %rdi movl $1, %esi .LEHB57: call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L1860 movq 24(%rsp), %rsi movq 32(%rsp), %rdx movq %r12, %rdi call _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_ .L1860: call cudaPeekAtLastError@PLT movl %eax, %ebx call cudaGetLastError@PLT movl %eax, %ebp testl %ebx, %ebx jne .L1880 testl %eax, %eax je .L1880 .L1859: call cudaGetLastError@PLT jmp .L1893 .L1880: movl %ebx, %ebp testl %ebx, %ebx jne .L1859 call cudaGetLastError@PLT movl %eax, %ebp testl %eax, %eax je .L1859 movq %r15, %rdi call cudaStreamSynchronize@PLT movl %eax, %ebx call cudaGetLastError@PLT movl %eax, %ebp testl %ebx, %ebx jne .L1881 testl %eax, %eax jne .L1862 .L1881: movl %ebx, %ebp .L1862: call cudaGetLastError@PLT .LEHE57: jmp .L1859 .L1893: movl %eax, %ebx testl %ebp, %ebp jne .L1882 testl %eax, %eax jne .L1857 .L1882: movl %ebp, %ebx jmp .L1857 .L1891: leaq _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi call __cxa_guard_acquire@PLT testl %eax, %eax je .L1865 movq 480+nvtxGlobals_v3(%rip), %rax testq %rax, %rax je .L1877 leaq .LC65(%rip), %rdi call *%rax .L1866: movq %rax, _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip) leaq _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d(%rip), %rdi call __cxa_guard_release@PLT jmp .L1865 .L1877: movl $0, %eax jmp .L1866 .L1878: endbr64 movq %rax, %rbx leaq 10(%rsp), %rdi call _ZN5nvtx32v115scoped_range_inIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainEED1Ev movq 88(%rsp), %rax subq %fs:40, %rax je .L1869 call __stack_chk_fail@PLT .L1869: movq %rbx, %rdi .LEHB58: call _Unwind_Resume@PLT .LEHE58: .L1892: call __stack_chk_fail@PLT .cfi_endproc .LFE13475: .section .gcc_except_table._ZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_st,"aG",@progbits,_ZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_st,comdat .LLSDA13475: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13475-.LLSDACSB13475 .LLSDACSB13475: .uleb128 .LEHB55-.LFB13475 .uleb128 .LEHE55-.LEHB55 .uleb128 .L1878-.LFB13475 .uleb128 0 .uleb128 .LEHB56-.LFB13475 .uleb128 .LEHE56-.LEHB56 .uleb128 .L1878-.LFB13475 .uleb128 0 .uleb128 .LEHB57-.LFB13475 .uleb128 .LEHE57-.LEHB57 .uleb128 .L1878-.LFB13475 .uleb128 0 .uleb128 .LEHB58-.LFB13475 .uleb128 .LEHE58-.LEHB58 .uleb128 0 .uleb128 0 .LLSDACSE13475: .section .text._ZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_st,"axG",@progbits,_ZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_st,comdat .size _ZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_st, .-_ZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_st .section .rodata._ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_.str1.1,"aMS",@progbits,1 .LC67: .string "parallel_for failed" .section .rodata._ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_.str1.8,"aMS",@progbits,1 .align 8 .LC68: .string "parallel_for: failed to synchronize" .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_,comdat .weak _ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_ .type _ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_, @function _ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_: .LFB13441: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13441 endbr64 testq %rcx, %rcx jne .L1905 ret .L1905: pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rcx, %rdi movl $1, %ecx .LEHB59: call _ZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_st movl %eax, %ebp call cudaGetLastError@PLT testl %ebp, %ebp jne .L1906 movq %rbx, %rdi call _ZN6thrust20THRUST_200700_800_NS8cuda_cub18synchronize_streamINS1_3tagEEE9cudaErrorRNS1_16execution_policyIT_EE movl %eax, %ebx call cudaGetLastError@PLT .LEHE59: testl %ebx, %ebx jne .L1907 popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1906: .cfi_restore_state movl $64, %edi call __cxa_allocate_exception@PLT movq %rax, %rbx call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %r12 leaq .LC67(%rip), %rsi movq %rbx, %rdi .LEHB60: call _ZNSt13runtime_errorC2EPKc@PLT .LEHE60: leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, (%rbx) movl %ebp, 16(%rbx) movq %r12, 24(%rbx) leaq 48(%rbx), %rax movq %rax, 32(%rbx) movq $0, 40(%rbx) movb $0, 48(%rbx) leaq _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rsi movq %rbx, %rdi .LEHB61: call __cxa_throw@PLT .L1900: endbr64 movq %rax, %rbp movq %rbx, %rdi call __cxa_free_exception@PLT movq %rbp, %rdi call _Unwind_Resume@PLT .LEHE61: .L1907: movl $64, %edi call __cxa_allocate_exception@PLT movq %rax, %rbp call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %r12 leaq .LC68(%rip), %rsi movq %rbp, %rdi .LEHB62: call _ZNSt13runtime_errorC2EPKc@PLT .LEHE62: leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, 0(%rbp) movl %ebx, 16(%rbp) movq %r12, 24(%rbp) leaq 48(%rbp), %rax movq %rax, 32(%rbp) movq $0, 40(%rbp) movb $0, 48(%rbp) leaq _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rsi movq %rbp, %rdi .LEHB63: call __cxa_throw@PLT .L1899: endbr64 movq %rax, %rbx movq %rbp, %rdi call __cxa_free_exception@PLT movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE63: .cfi_endproc .LFE13441: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_,comdat .LLSDA13441: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13441-.LLSDACSB13441 .LLSDACSB13441: .uleb128 .LEHB59-.LFB13441 .uleb128 .LEHE59-.LEHB59 .uleb128 0 .uleb128 0 .uleb128 .LEHB60-.LFB13441 .uleb128 .LEHE60-.LEHB60 .uleb128 .L1900-.LFB13441 .uleb128 0 .uleb128 .LEHB61-.LFB13441 .uleb128 .LEHE61-.LEHB61 .uleb128 0 .uleb128 0 .uleb128 .LEHB62-.LFB13441 .uleb128 .LEHE62-.LEHB62 .uleb128 .L1899-.LFB13441 .uleb128 0 .uleb128 .LEHB63-.LFB13441 .uleb128 .LEHE63-.LEHB63 .uleb128 0 .uleb128 0 .LLSDACSE13441: .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_,comdat .size _ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_, .-_ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_ .section .rodata._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_.str1.8,"aMS",@progbits,1 .align 8 .LC69: .string "trivial_device_copy D->H failed" .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_,comdat .weak _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_ .type _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_, @function _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_: .LFB13634: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13634 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rcx, %rbx movq %r8, %rbp testq %rcx, %rcx jle .L1909 movq %rdx, %rsi leaq 0(,%rcx,4), %rdx movl $1, %r8d movl $2, %ecx movq %rbp, %rdi .LEHB64: call cudaMemcpyAsync@PLT movl %eax, %r12d movl $1, %edi call cudaStreamSynchronize@PLT call cudaGetLastError@PLT .LEHE64: testl %r12d, %r12d jne .L1913 .L1909: leaq 0(%rbp,%rbx,4), %rax popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1913: .cfi_restore_state movl $64, %edi call __cxa_allocate_exception@PLT movq %rax, %rbx call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %rbp leaq .LC69(%rip), %rsi movq %rbx, %rdi .LEHB65: call _ZNSt13runtime_errorC2EPKc@PLT .LEHE65: leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, (%rbx) movl %r12d, 16(%rbx) movq %rbp, 24(%rbx) leaq 48(%rbx), %rax movq %rax, 32(%rbx) movq $0, 40(%rbx) movb $0, 48(%rbx) leaq _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rsi movq %rbx, %rdi .LEHB66: call __cxa_throw@PLT .L1911: endbr64 movq %rax, %rbp movq %rbx, %rdi call __cxa_free_exception@PLT movq %rbp, %rdi call _Unwind_Resume@PLT .LEHE66: .cfi_endproc .LFE13634: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_,comdat .LLSDA13634: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13634-.LLSDACSB13634 .LLSDACSB13634: .uleb128 .LEHB64-.LFB13634 .uleb128 .LEHE64-.LEHB64 .uleb128 0 .uleb128 0 .uleb128 .LEHB65-.LFB13634 .uleb128 .LEHE65-.LEHB65 .uleb128 .L1911-.LFB13634 .uleb128 0 .uleb128 .LEHB66-.LFB13634 .uleb128 .LEHE66-.LEHB66 .uleb128 0 .uleb128 0 .LLSDACSE13634: .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_,comdat .size _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_, .-_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_ .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIiEEEENS0_7pointerIiS4_NS0_11use_defaultESB_EEEET1_RNS1_16execution_policyIT_EET0_SI_SD_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIiEEEENS0_7pointerIiS4_NS0_11use_defaultESB_EEEET1_RNS1_16execution_policyIT_EET0_SI_SD_,comdat .weak _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIiEEEENS0_7pointerIiS4_NS0_11use_defaultESB_EEEET1_RNS1_16execution_policyIT_EET0_SI_SD_ .type _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIiEEEENS0_7pointerIiS4_NS0_11use_defaultESB_EEEET1_RNS1_16execution_policyIT_EET0_SI_SD_, @function _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIiEEEENS0_7pointerIiS4_NS0_11use_defaultESB_EEEET1_RNS1_16execution_policyIT_EET0_SI_SD_: .LFB13644: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13644 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rcx, %rbx subq %rsi, %rdx movq %rdx, %rbp testq %rdx, %rdx jg .L1919 .L1915: leaq (%rbx,%rbp), %rax popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1919: .cfi_restore_state movq %rdx, %rcx sarq $2, %rcx movq %rsi, %rdx movq %rbx, %rsi .LEHB67: call _ZN6thrust20THRUST_200700_800_NS8cuda_cub29trivial_copy_device_to_deviceINS1_16execution_policyINS1_3tagEEEiEE9cudaErrorRT_PT0_PKS9_m movl %eax, %r12d call cudaGetLastError@PLT .LEHE67: testl %r12d, %r12d je .L1915 movl $64, %edi call __cxa_allocate_exception@PLT movq %rax, %rbx call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %rbp leaq .LC64(%rip), %rsi movq %rbx, %rdi .LEHB68: call _ZNSt13runtime_errorC2EPKc@PLT .LEHE68: leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, (%rbx) movl %r12d, 16(%rbx) movq %rbp, 24(%rbx) leaq 48(%rbx), %rax movq %rax, 32(%rbx) movq $0, 40(%rbx) movb $0, 48(%rbx) leaq _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rsi movq %rbx, %rdi .LEHB69: call __cxa_throw@PLT .L1917: endbr64 movq %rax, %rbp movq %rbx, %rdi call __cxa_free_exception@PLT movq %rbp, %rdi call _Unwind_Resume@PLT .LEHE69: .cfi_endproc .LFE13644: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIiEEEENS0_7pointerIiS4_NS0_11use_defaultESB_EEEET1_RNS1_16execution_policyIT_EET0_SI_SD_,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIiEEEENS0_7pointerIiS4_NS0_11use_defaultESB_EEEET1_RNS1_16execution_policyIT_EET0_SI_SD_,comdat .LLSDA13644: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13644-.LLSDACSB13644 .LLSDACSB13644: .uleb128 .LEHB67-.LFB13644 .uleb128 .LEHE67-.LEHB67 .uleb128 0 .uleb128 0 .uleb128 .LEHB68-.LFB13644 .uleb128 .LEHE68-.LEHB68 .uleb128 .L1917-.LFB13644 .uleb128 0 .uleb128 .LEHB69-.LFB13644 .uleb128 .LEHE69-.LEHB69 .uleb128 0 .uleb128 0 .LLSDACSE13644: .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIiEEEENS0_7pointerIiS4_NS0_11use_defaultESB_EEEET1_RNS1_16execution_policyIT_EET0_SI_SD_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIiEEEENS0_7pointerIiS4_NS0_11use_defaultESB_EEEET1_RNS1_16execution_policyIT_EET0_SI_SD_,comdat .size _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIiEEEENS0_7pointerIiS4_NS0_11use_defaultESB_EEEET1_RNS1_16execution_policyIT_EET0_SI_SD_, .-_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIiEEEENS0_7pointerIiS4_NS0_11use_defaultESB_EEEET1_RNS1_16execution_policyIT_EET0_SI_SD_ .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEENS7_IiEEEET1_RNS1_16execution_policyIT_EET0_SH_SC_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEENS7_IiEEEET1_RNS1_16execution_policyIT_EET0_SH_SC_,comdat .weak _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEENS7_IiEEEET1_RNS1_16execution_policyIT_EET0_SH_SC_ .type _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEENS7_IiEEEET1_RNS1_16execution_policyIT_EET0_SH_SC_, @function _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEENS7_IiEEEET1_RNS1_16execution_policyIT_EET0_SH_SC_: .LFB13651: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13651 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rcx, %rbx subq %rsi, %rdx movq %rdx, %rbp testq %rdx, %rdx jg .L1925 .L1921: leaq (%rbx,%rbp), %rax popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1925: .cfi_restore_state movq %rdx, %rcx sarq $2, %rcx movq %rsi, %rdx movq %rbx, %rsi .LEHB70: call _ZN6thrust20THRUST_200700_800_NS8cuda_cub29trivial_copy_device_to_deviceINS1_16execution_policyINS1_3tagEEEiEE9cudaErrorRT_PT0_PKS9_m movl %eax, %r12d call cudaGetLastError@PLT .LEHE70: testl %r12d, %r12d je .L1921 movl $64, %edi call __cxa_allocate_exception@PLT movq %rax, %rbx call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %rbp leaq .LC64(%rip), %rsi movq %rbx, %rdi .LEHB71: call _ZNSt13runtime_errorC2EPKc@PLT .LEHE71: leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, (%rbx) movl %r12d, 16(%rbx) movq %rbp, 24(%rbx) leaq 48(%rbx), %rax movq %rax, 32(%rbx) movq $0, 40(%rbx) movb $0, 48(%rbx) leaq _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rsi movq %rbx, %rdi .LEHB72: call __cxa_throw@PLT .L1923: endbr64 movq %rax, %rbp movq %rbx, %rdi call __cxa_free_exception@PLT movq %rbp, %rdi call _Unwind_Resume@PLT .LEHE72: .cfi_endproc .LFE13651: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEENS7_IiEEEET1_RNS1_16execution_policyIT_EET0_SH_SC_,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEENS7_IiEEEET1_RNS1_16execution_policyIT_EET0_SH_SC_,comdat .LLSDA13651: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13651-.LLSDACSB13651 .LLSDACSB13651: .uleb128 .LEHB70-.LFB13651 .uleb128 .LEHE70-.LEHB70 .uleb128 0 .uleb128 0 .uleb128 .LEHB71-.LFB13651 .uleb128 .LEHE71-.LEHB71 .uleb128 .L1923-.LFB13651 .uleb128 0 .uleb128 .LEHB72-.LFB13651 .uleb128 .LEHE72-.LEHB72 .uleb128 0 .uleb128 0 .LLSDACSE13651: .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEENS7_IiEEEET1_RNS1_16execution_policyIT_EET0_SH_SC_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEENS7_IiEEEET1_RNS1_16execution_policyIT_EET0_SH_SC_,comdat .size _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEENS7_IiEEEET1_RNS1_16execution_policyIT_EET0_SH_SC_, .-_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEENS7_IiEEEET1_RNS1_16execution_policyIT_EET0_SH_SC_ .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SC_RNS1_18contiguous_storageIiS4_EE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SC_RNS1_18contiguous_storageIiS4_EE,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SC_RNS1_18contiguous_storageIiS4_EE .type _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SC_RNS1_18contiguous_storageIiS4_EE, @function _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SC_RNS1_18contiguous_storageIiS4_EE: .LFB13185: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13185 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $16, %rsp .cfi_def_cfa_offset 48 movq %r8, %rbx movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax testq %rsi, %rsi je .L1942 movq %rdx, %rbp movq %rcx, %r12 movq 16(%rdi), %rax addq %rax, %rax cmpq %rsi, %rax cmovb %rsi, %rax cmpq %rsi, %rax jb .L1943 movq %rax, %rsi movq %r8, %rdi .LEHB73: call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm .LEHE73: movq 8(%rbx), %rcx leaq 7(%rsp), %rdi movq %r12, %rdx movq %rbp, %rsi .LEHB74: call _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEENS7_IiEEEET1_RNS1_16execution_policyIT_EET0_SH_SC_ .LEHE74: jmp .L1926 .L1942: movq %r8, %rdi call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv .L1926: movq 8(%rsp), %rax subq %fs:40, %rax jne .L1944 addq $16, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1943: .cfi_restore_state movl $16, %edi call __cxa_allocate_exception@PLT movq %rax, %rbx leaq .LC62(%rip), %rsi movq %rax, %rdi .LEHB75: call _ZNSt12length_errorC1EPKc@PLT .LEHE75: movq 8(%rsp), %rax subq %fs:40, %rax je .L1930 call __stack_chk_fail@PLT .L1930: movq _ZNSt12length_errorD1Ev@GOTPCREL(%rip), %rdx leaq _ZTISt12length_error(%rip), %rsi movq %rbx, %rdi .LEHB76: call __cxa_throw@PLT .L1938: endbr64 movq %rax, %rbp movq %rbx, %rdi call __cxa_free_exception@PLT movq 8(%rsp), %rax subq %fs:40, %rax je .L1932 call __stack_chk_fail@PLT .L1932: movq %rbp, %rdi call _Unwind_Resume@PLT .LEHE76: .L1939: endbr64 movq %rax, %rdi call __cxa_begin_catch@PLT movq %rbx, %rdi call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv movq 8(%rsp), %rax subq %fs:40, %rax je .L1934 call __stack_chk_fail@PLT .L1934: .LEHB77: call __cxa_rethrow@PLT .LEHE77: .L1940: endbr64 movq %rax, %rbx call __cxa_end_catch@PLT movq 8(%rsp), %rax subq %fs:40, %rax je .L1936 call __stack_chk_fail@PLT .L1936: movq %rbx, %rdi .LEHB78: call _Unwind_Resume@PLT .LEHE78: .L1944: call __stack_chk_fail@PLT .cfi_endproc .LFE13185: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SC_RNS1_18contiguous_storageIiS4_EE,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SC_RNS1_18contiguous_storageIiS4_EE,comdat .align 4 .LLSDA13185: .byte 0xff .byte 0x9b .uleb128 .LLSDATT13185-.LLSDATTD13185 .LLSDATTD13185: .byte 0x1 .uleb128 .LLSDACSE13185-.LLSDACSB13185 .LLSDACSB13185: .uleb128 .LEHB73-.LFB13185 .uleb128 .LEHE73-.LEHB73 .uleb128 0 .uleb128 0 .uleb128 .LEHB74-.LFB13185 .uleb128 .LEHE74-.LEHB74 .uleb128 .L1939-.LFB13185 .uleb128 0x1 .uleb128 .LEHB75-.LFB13185 .uleb128 .LEHE75-.LEHB75 .uleb128 .L1938-.LFB13185 .uleb128 0 .uleb128 .LEHB76-.LFB13185 .uleb128 .LEHE76-.LEHB76 .uleb128 0 .uleb128 0 .uleb128 .LEHB77-.LFB13185 .uleb128 .LEHE77-.LEHB77 .uleb128 .L1940-.LFB13185 .uleb128 0 .uleb128 .LEHB78-.LFB13185 .uleb128 .LEHE78-.LEHB78 .uleb128 0 .uleb128 0 .LLSDACSE13185: .byte 0x1 .byte 0 .align 4 .long 0 .LLSDATT13185: .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SC_RNS1_18contiguous_storageIiS4_EE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SC_RNS1_18contiguous_storageIiS4_EE,comdat .size _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SC_RNS1_18contiguous_storageIiS4_EE, .-_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SC_RNS1_18contiguous_storageIiS4_EE .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE13shrink_to_fitEv,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE13shrink_to_fitEv,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE13shrink_to_fitEv .type _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE13shrink_to_fitEv, @function _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE13shrink_to_fitEv: .LFB12577: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA12577 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $64, %rsp .cfi_def_cfa_offset 96 movq %rdi, %rbx movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movq (%rdi), %rax movq %rax, 16(%rsp) movq $0, 24(%rsp) movq $0, 32(%rsp) movq $0, 40(%rsp) call _ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv movq %rax, %r12 movq %rbx, %rdi call _ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5beginEv movq %rax, %rdx movq %r12, %rbp subq %rax, %rbp sarq $2, %rbp leaq 16(%rsp), %rdi movq %rdi, %r8 movq %r12, %rcx movq %rbp, %rsi .LEHB79: call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SC_RNS1_18contiguous_storageIiS4_EE .LEHE79: movq 24(%rsp), %rax movq 8(%rbx), %rdx movq %rdx, 24(%rsp) movq %rax, 8(%rbx) movq 32(%rsp), %rax movq 16(%rbx), %rdx movq %rdx, 32(%rsp) movq %rax, 16(%rbx) movq 16(%rsp), %rax movq (%rbx), %rdx movq %rdx, 16(%rsp) movq %rax, (%rbx) movq 24(%rbx), %rax movq %rax, 40(%rsp) movq %rbp, 24(%rbx) leaq 16(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED1Ev movq 56(%rsp), %rax subq %fs:40, %rax jne .L1952 addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1949: .cfi_restore_state endbr64 movq %rax, %rbx leaq 16(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv movq 56(%rsp), %rax subq %fs:40, %rax je .L1947 call __stack_chk_fail@PLT .L1947: movq %rbx, %rdi .LEHB80: call _Unwind_Resume@PLT .LEHE80: .L1952: call __stack_chk_fail@PLT .cfi_endproc .LFE12577: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE13shrink_to_fitEv,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE13shrink_to_fitEv,comdat .LLSDA12577: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE12577-.LLSDACSB12577 .LLSDACSB12577: .uleb128 .LEHB79-.LFB12577 .uleb128 .LEHE79-.LEHB79 .uleb128 .L1949-.LFB12577 .uleb128 0 .uleb128 .LEHB80-.LFB12577 .uleb128 .LEHE80-.LEHB80 .uleb128 0 .uleb128 0 .LLSDACSE12577: .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE13shrink_to_fitEv,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE13shrink_to_fitEv,comdat .size _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE13shrink_to_fitEv, .-_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE13shrink_to_fitEv .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub6mallocINS1_3tagEEEPvRNS1_16execution_policyIT_EEm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6mallocINS1_3tagEEEPvRNS1_16execution_policyIT_EEm,comdat .weak _ZN6thrust20THRUST_200700_800_NS8cuda_cub6mallocINS1_3tagEEEPvRNS1_16execution_policyIT_EEm .type _ZN6thrust20THRUST_200700_800_NS8cuda_cub6mallocINS1_3tagEEEPvRNS1_16execution_policyIT_EEm, @function _ZN6thrust20THRUST_200700_800_NS8cuda_cub6mallocINS1_3tagEEEPvRNS1_16execution_policyIT_EEm: .LFB13690: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13690 endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $104, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax movq $0, 8(%rsp) leaq 8(%rsp), %rdi .LEHB81: call cudaMalloc@PLT testl %eax, %eax jne .L1966 movq 8(%rsp), %rax movq 88(%rsp), %rdx subq %fs:40, %rdx jne .L1967 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L1966: .cfi_restore_state movl %eax, %ebx call cudaGetLastError@PLT .LEHE81: movl $40, %edi call __cxa_allocate_exception@PLT movq %rax, %rbp call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %rsi leaq 16(%rsp), %rdi movq (%rax), %rax movl %ebx, %edx .LEHB82: call *48(%rax) .LEHE82: leaq 7(%rsp), %rdx leaq 48(%rsp), %rdi movq 16(%rsp), %rsi .LEHB83: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .LEHE83: leaq 48(%rsp), %rsi movq %rbp, %rdi .LEHB84: call _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .LEHE84: leaq 48(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq 16(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq 88(%rsp), %rax subq %fs:40, %rax jne .L1968 leaq _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE(%rip), %rsi movq %rbp, %rdi .LEHB85: call __cxa_throw@PLT .L1968: call __stack_chk_fail@PLT .L1963: endbr64 movq %rax, %rbx leaq 48(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT .L1957: leaq 16(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT .L1958: movq %rbp, %rdi call __cxa_free_exception@PLT movq 88(%rsp), %rax subq %fs:40, %rax je .L1959 call __stack_chk_fail@PLT .L1962: endbr64 movq %rax, %rbx jmp .L1957 .L1961: endbr64 movq %rax, %rbx jmp .L1958 .L1959: movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE85: .L1967: call __stack_chk_fail@PLT .cfi_endproc .LFE13690: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS8cuda_cub6mallocINS1_3tagEEEPvRNS1_16execution_policyIT_EEm,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6mallocINS1_3tagEEEPvRNS1_16execution_policyIT_EEm,comdat .LLSDA13690: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13690-.LLSDACSB13690 .LLSDACSB13690: .uleb128 .LEHB81-.LFB13690 .uleb128 .LEHE81-.LEHB81 .uleb128 0 .uleb128 0 .uleb128 .LEHB82-.LFB13690 .uleb128 .LEHE82-.LEHB82 .uleb128 .L1961-.LFB13690 .uleb128 0 .uleb128 .LEHB83-.LFB13690 .uleb128 .LEHE83-.LEHB83 .uleb128 .L1962-.LFB13690 .uleb128 0 .uleb128 .LEHB84-.LFB13690 .uleb128 .LEHE84-.LEHB84 .uleb128 .L1963-.LFB13690 .uleb128 0 .uleb128 .LEHB85-.LFB13690 .uleb128 .LEHE85-.LEHB85 .uleb128 0 .uleb128 0 .LLSDACSE13690: .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub6mallocINS1_3tagEEEPvRNS1_16execution_policyIT_EEm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6mallocINS1_3tagEEEPvRNS1_16execution_policyIT_EEm,comdat .size _ZN6thrust20THRUST_200700_800_NS8cuda_cub6mallocINS1_3tagEEEPvRNS1_16execution_policyIT_EEm, .-_ZN6thrust20THRUST_200700_800_NS8cuda_cub6mallocINS1_3tagEEEPvRNS1_16execution_policyIT_EEm .section .rodata._ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_.str1.1,"aMS",@progbits,1 .LC70: .string "device free failed" .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_,comdat .weak _ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_ .type _ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_, @function _ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_: .LFB13696: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13696 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rsi, %rdi .LEHB86: call cudaFree@PLT movl %eax, %ebx call cudaGetLastError@PLT .LEHE86: testl %ebx, %ebx jne .L1974 popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L1974: .cfi_restore_state movl $64, %edi call __cxa_allocate_exception@PLT movq %rax, %rbp call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %r12 leaq .LC70(%rip), %rsi movq %rbp, %rdi .LEHB87: call _ZNSt13runtime_errorC2EPKc@PLT .LEHE87: leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, 0(%rbp) movl %ebx, 16(%rbp) movq %r12, 24(%rbp) leaq 48(%rbp), %rax movq %rax, 32(%rbp) movq $0, 40(%rbp) movb $0, 48(%rbp) leaq _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rsi movq %rbp, %rdi .LEHB88: call __cxa_throw@PLT .L1972: endbr64 movq %rax, %rbx movq %rbp, %rdi call __cxa_free_exception@PLT movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE88: .cfi_endproc .LFE13696: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_,comdat .LLSDA13696: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13696-.LLSDACSB13696 .LLSDACSB13696: .uleb128 .LEHB86-.LFB13696 .uleb128 .LEHE86-.LEHB86 .uleb128 0 .uleb128 0 .uleb128 .LEHB87-.LFB13696 .uleb128 .LEHE87-.LEHB87 .uleb128 .L1972-.LFB13696 .uleb128 0 .uleb128 .LEHB88-.LFB13696 .uleb128 .LEHE88-.LEHB88 .uleb128 0 .uleb128 0 .LLSDACSE13696: .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_,comdat .size _ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_, .-_ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_ .section .text._ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED2Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED2Ev .type _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED2Ev, @function _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED2Ev: .LFB13253: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13253 endbr64 cmpq $0, 16(%rdi) jne .L1981 ret .L1981: subq $8, %rsp .cfi_def_cfa_offset 16 movq (%rdi), %rax movq 8(%rdi), %rsi movq %rax, %rdi call _ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE13253: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED2Ev,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED5Ev,comdat .LLSDA13253: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13253-.LLSDACSB13253 .LLSDACSB13253: .LLSDACSE13253: .section .text._ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED2Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED5Ev,comdat .size _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED2Ev, .-_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED2Ev .weak _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED1Ev .set _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED1Ev,_ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED2Ev .section .text._ZN6thrust20THRUST_200700_800_NS6detail15temporary_arrayIiNS0_8cuda_cub3tagEED2Ev,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail15temporary_arrayIiNS0_8cuda_cub3tagEED5Ev,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail15temporary_arrayIiNS0_8cuda_cub3tagEED2Ev .type _ZN6thrust20THRUST_200700_800_NS6detail15temporary_arrayIiNS0_8cuda_cub3tagEED2Ev, @function _ZN6thrust20THRUST_200700_800_NS6detail15temporary_arrayIiNS0_8cuda_cub3tagEED2Ev: .LFB13178: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED2Ev addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE13178: .size _ZN6thrust20THRUST_200700_800_NS6detail15temporary_arrayIiNS0_8cuda_cub3tagEED2Ev, .-_ZN6thrust20THRUST_200700_800_NS6detail15temporary_arrayIiNS0_8cuda_cub3tagEED2Ev .weak _ZN6thrust20THRUST_200700_800_NS6detail15temporary_arrayIiNS0_8cuda_cub3tagEED1Ev .set _ZN6thrust20THRUST_200700_800_NS6detail15temporary_arrayIiNS0_8cuda_cub3tagEED1Ev,_ZN6thrust20THRUST_200700_800_NS6detail15temporary_arrayIiNS0_8cuda_cub3tagEED2Ev .section .rodata._ZN6thrust20THRUST_200700_800_NS6detail19temporary_allocatorIiNS0_8cuda_cub3tagEE8allocateEm.str1.8,"aMS",@progbits,1 .align 8 .LC71: .string "temporary_buffer::allocate: get_temporary_buffer failed" .section .text._ZN6thrust20THRUST_200700_800_NS6detail19temporary_allocatorIiNS0_8cuda_cub3tagEE8allocateEm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail19temporary_allocatorIiNS0_8cuda_cub3tagEE8allocateEm,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail19temporary_allocatorIiNS0_8cuda_cub3tagEE8allocateEm .type _ZN6thrust20THRUST_200700_800_NS6detail19temporary_allocatorIiNS0_8cuda_cub3tagEE8allocateEm, @function _ZN6thrust20THRUST_200700_800_NS6detail19temporary_allocatorIiNS0_8cuda_cub3tagEE8allocateEm: .LFB13406: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13406 endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $72, %rsp .cfi_def_cfa_offset 96 movq %rdi, %rbp movq %rsi, %rbx movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax leaq 0(,%rsi,4), %rsi movq (%rdi), %rdi .LEHB89: call _ZN6thrust20THRUST_200700_800_NS8cuda_cub6mallocINS1_3tagEEEPvRNS1_16execution_policyIT_EEm .LEHE89: testq %rax, %rax movl $0, %edx cmovne %rbx, %rdx cmpq %rbx, %rdx jb .L1997 movq 56(%rsp), %rdx subq %fs:40, %rdx jne .L1998 addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L1997: .cfi_restore_state movq 0(%rbp), %rdi movq %rax, %rsi call _ZN6thrust20THRUST_200700_800_NS8cuda_cub4freeINS1_3tagENS0_7pointerIiS3_NS0_11use_defaultES5_EEEEvRNS1_16execution_policyIT_EET0_ movl $40, %edi call __cxa_allocate_exception@PLT movq %rax, %rbp leaq 15(%rsp), %rdx leaq 16(%rsp), %rdi leaq .LC71(%rip), %rsi .LEHB90: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .LEHE90: leaq 16(%rsp), %rsi movq %rbp, %rdi .LEHB91: call _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .LEHE91: leaq 16(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L1999 leaq _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE(%rip), %rsi movq %rbp, %rdi .LEHB92: call __cxa_throw@PLT .L1999: call __stack_chk_fail@PLT .L1994: endbr64 movq %rax, %rbx leaq 16(%rsp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT .L1989: movq %rbp, %rdi call __cxa_free_exception@PLT movq 56(%rsp), %rax subq %fs:40, %rax je .L1990 call __stack_chk_fail@PLT .L1993: endbr64 movq %rax, %rbx jmp .L1989 .L1990: movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE92: .L1998: call __stack_chk_fail@PLT .cfi_endproc .LFE13406: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS6detail19temporary_allocatorIiNS0_8cuda_cub3tagEE8allocateEm,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail19temporary_allocatorIiNS0_8cuda_cub3tagEE8allocateEm,comdat .LLSDA13406: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13406-.LLSDACSB13406 .LLSDACSB13406: .uleb128 .LEHB89-.LFB13406 .uleb128 .LEHE89-.LEHB89 .uleb128 0 .uleb128 0 .uleb128 .LEHB90-.LFB13406 .uleb128 .LEHE90-.LEHB90 .uleb128 .L1993-.LFB13406 .uleb128 0 .uleb128 .LEHB91-.LFB13406 .uleb128 .LEHE91-.LEHB91 .uleb128 .L1994-.LFB13406 .uleb128 0 .uleb128 .LEHB92-.LFB13406 .uleb128 .LEHE92-.LEHB92 .uleb128 0 .uleb128 0 .LLSDACSE13406: .section .text._ZN6thrust20THRUST_200700_800_NS6detail19temporary_allocatorIiNS0_8cuda_cub3tagEE8allocateEm,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail19temporary_allocatorIiNS0_8cuda_cub3tagEE8allocateEm,comdat .size _ZN6thrust20THRUST_200700_800_NS6detail19temporary_allocatorIiNS0_8cuda_cub3tagEE8allocateEm, .-_ZN6thrust20THRUST_200700_800_NS6detail19temporary_allocatorIiNS0_8cuda_cub3tagEE8allocateEm .section .text._ZN6thrust20THRUST_200700_800_NS6detail8dispatch15overlapped_copyINS0_8cuda_cub3tagENS1_15normal_iteratorINS0_10device_ptrIiEEEES9_EET1_RNS0_16execution_policyIT_EET0_SF_SA_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail8dispatch15overlapped_copyINS0_8cuda_cub3tagENS1_15normal_iteratorINS0_10device_ptrIiEEEES9_EET1_RNS0_16execution_policyIT_EET0_SF_SA_,comdat .weak _ZN6thrust20THRUST_200700_800_NS6detail8dispatch15overlapped_copyINS0_8cuda_cub3tagENS1_15normal_iteratorINS0_10device_ptrIiEEEES9_EET1_RNS0_16execution_policyIT_EET0_SF_SA_ .type _ZN6thrust20THRUST_200700_800_NS6detail8dispatch15overlapped_copyINS0_8cuda_cub3tagENS1_15normal_iteratorINS0_10device_ptrIiEEEES9_EET1_RNS0_16execution_policyIT_EET0_SF_SA_, @function _ZN6thrust20THRUST_200700_800_NS6detail8dispatch15overlapped_copyINS0_8cuda_cub3tagENS1_15normal_iteratorINS0_10device_ptrIiEEEES9_EET1_RNS0_16execution_policyIT_EET0_SF_SA_: .LFB13087: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13087 endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $32, %rsp .cfi_def_cfa_offset 80 movq %rdi, %rbx movq %rsi, %rbp movq %rdx, %r12 movq %rcx, %r14 movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq $0, 8(%rsp) movq $0, 16(%rsp) movq %rdx, %rax subq %rsi, %rax sarq $2, %rax je .L2001 movq %rax, %r13 movq %rsp, %rdi movq %rax, %rsi .LEHB93: call _ZN6thrust20THRUST_200700_800_NS6detail19temporary_allocatorIiNS0_8cuda_cub3tagEE8allocateEm movq %rax, 8(%rsp) movq %r13, 16(%rsp) .L2002: movq 8(%rsp), %r13 movq %r13, %rcx movq %r12, %rdx movq %rbp, %rsi movq %rbx, %rdi call _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_10device_ptrIiEEEENS0_7pointerIiS4_NS0_11use_defaultESB_EEEET1_RNS1_16execution_policyIT_EET0_SI_SD_ .LEHE93: jmp .L2013 .L2001: movq $0, 8(%rsp) jmp .L2002 .L2013: movq 16(%rsp), %rax leaq 0(%r13,%rax,4), %rdx movq %r14, %rcx movq %r13, %rsi movq %rbx, %rdi .LEHB94: call _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy16device_to_deviceINS1_3tagENS0_6detail15normal_iteratorINS0_7pointerIiS4_NS0_11use_defaultES8_EEEENS6_INS0_10device_ptrIiEEEEEET1_RNS1_16execution_policyIT_EET0_SJ_SE_ .LEHE94: movq %rax, %rbx movq %rsp, %rdi call _ZN6thrust20THRUST_200700_800_NS6detail15temporary_arrayIiNS0_8cuda_cub3tagEED1Ev movq 24(%rsp), %rax subq %fs:40, %rax jne .L2014 movq %rbx, %rax addq $32, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L2010: .cfi_restore_state endbr64 movq %rax, %rbx movq %rsp, %rdi call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS1_18no_throw_allocatorINS1_19temporary_allocatorIiNS0_8cuda_cub3tagEEEEEED2Ev movq 24(%rsp), %rax subq %fs:40, %rax je .L2005 call __stack_chk_fail@PLT .L2005: movq %rbx, %rdi .LEHB95: call _Unwind_Resume@PLT .L2009: endbr64 movq %rax, %rbx movq %rsp, %rdi call _ZN6thrust20THRUST_200700_800_NS6detail15temporary_arrayIiNS0_8cuda_cub3tagEED1Ev movq 24(%rsp), %rax subq %fs:40, %rax je .L2007 call __stack_chk_fail@PLT .L2007: movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE95: .L2014: call __stack_chk_fail@PLT .cfi_endproc .LFE13087: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS6detail8dispatch15overlapped_copyINS0_8cuda_cub3tagENS1_15normal_iteratorINS0_10device_ptrIiEEEES9_EET1_RNS0_16execution_policyIT_EET0_SF_SA_,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail8dispatch15overlapped_copyINS0_8cuda_cub3tagENS1_15normal_iteratorINS0_10device_ptrIiEEEES9_EET1_RNS0_16execution_policyIT_EET0_SF_SA_,comdat .LLSDA13087: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13087-.LLSDACSB13087 .LLSDACSB13087: .uleb128 .LEHB93-.LFB13087 .uleb128 .LEHE93-.LEHB93 .uleb128 .L2010-.LFB13087 .uleb128 0 .uleb128 .LEHB94-.LFB13087 .uleb128 .LEHE94-.LEHB94 .uleb128 .L2009-.LFB13087 .uleb128 0 .uleb128 .LEHB95-.LFB13087 .uleb128 .LEHE95-.LEHB95 .uleb128 0 .uleb128 0 .LLSDACSE13087: .section .text._ZN6thrust20THRUST_200700_800_NS6detail8dispatch15overlapped_copyINS0_8cuda_cub3tagENS1_15normal_iteratorINS0_10device_ptrIiEEEES9_EET1_RNS0_16execution_policyIT_EET0_SF_SA_,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail8dispatch15overlapped_copyINS0_8cuda_cub3tagENS1_15normal_iteratorINS0_10device_ptrIiEEEES9_EET1_RNS0_16execution_policyIT_EET0_SF_SA_,comdat .size _ZN6thrust20THRUST_200700_800_NS6detail8dispatch15overlapped_copyINS0_8cuda_cub3tagENS1_15normal_iteratorINS0_10device_ptrIiEEEES9_EET1_RNS0_16execution_policyIT_EET0_SF_SA_, .-_ZN6thrust20THRUST_200700_800_NS6detail8dispatch15overlapped_copyINS0_8cuda_cub3tagENS1_15normal_iteratorINS0_10device_ptrIiEEEES9_EET1_RNS0_16execution_policyIT_EET0_SF_SA_ .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5clearEv,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5clearEv,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5clearEv .type _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5clearEv, @function _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5clearEv: .LFB12576: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $16, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbp movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv movq %rax, %rbx movq 8(%rbp), %r12 movq %rbp, %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv movq %rax, %rdx leaq 7(%rsp), %rdi movq %r12, %rcx movq %rbx, %rsi call _ZN6thrust20THRUST_200700_800_NS6detail8dispatch15overlapped_copyINS0_8cuda_cub3tagENS1_15normal_iteratorINS0_10device_ptrIiEEEES9_EET1_RNS0_16execution_policyIT_EET0_SF_SA_ subq %r12, %rbx sarq $2, %rbx subq %rbx, 24(%rbp) movq 8(%rsp), %rax subq %fs:40, %rax jne .L2018 addq $16, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L2018: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE12576: .size _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5clearEv, .-_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5clearEv .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElPiEET3_RNS0_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_N4cuda3std3__417integral_constantIbLb1EEE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElPiEET3_RNS0_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_N4cuda3std3__417integral_constantIbLb1EEE,comdat .weak _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElPiEET3_RNS0_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_N4cuda3std3__417integral_constantIbLb1EEE .type _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElPiEET3_RNS0_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_N4cuda3std3__417integral_constantIbLb1EEE, @function _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElPiEET3_RNS0_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_N4cuda3std3__417integral_constantIbLb1EEE: .LFB13714: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13714 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rcx, %rbx movq %r8, %rbp testq %rcx, %rcx jle .L2020 movq %rdx, %rsi leaq 0(,%rcx,4), %rdx movl $1, %r8d movl $2, %ecx movq %rbp, %rdi .LEHB96: call cudaMemcpyAsync@PLT movl %eax, %r12d movl $1, %edi call cudaStreamSynchronize@PLT call cudaGetLastError@PLT .LEHE96: testl %r12d, %r12d jne .L2024 .L2020: leaq 0(%rbp,%rbx,4), %rax popq %rbx .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L2024: .cfi_restore_state movl $64, %edi call __cxa_allocate_exception@PLT movq %rax, %rbx call _ZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEv movq %rax, %rbp leaq .LC69(%rip), %rsi movq %rbx, %rdi .LEHB97: call _ZNSt13runtime_errorC2EPKc@PLT .LEHE97: leaq 16+_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rax movq %rax, (%rbx) movl %r12d, 16(%rbx) movq %rbp, 24(%rbx) leaq 48(%rbx), %rax movq %rax, 32(%rbx) movq $0, 40(%rbx) movb $0, 48(%rbx) leaq _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev(%rip), %rdx leaq _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE(%rip), %rsi movq %rbx, %rdi .LEHB98: call __cxa_throw@PLT .L2022: endbr64 movq %rax, %rbp movq %rbx, %rdi call __cxa_free_exception@PLT movq %rbp, %rdi call _Unwind_Resume@PLT .LEHE98: .cfi_endproc .LFE13714: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElPiEET3_RNS0_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_N4cuda3std3__417integral_constantIbLb1EEE,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElPiEET3_RNS0_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_N4cuda3std3__417integral_constantIbLb1EEE,comdat .LLSDA13714: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13714-.LLSDACSB13714 .LLSDACSB13714: .uleb128 .LEHB96-.LFB13714 .uleb128 .LEHE96-.LEHB96 .uleb128 0 .uleb128 0 .uleb128 .LEHB97-.LFB13714 .uleb128 .LEHE97-.LEHB97 .uleb128 .L2022-.LFB13714 .uleb128 0 .uleb128 .LEHB98-.LFB13714 .uleb128 .LEHE98-.LEHB98 .uleb128 0 .uleb128 0 .LLSDACSE13714: .section .text._ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElPiEET3_RNS0_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_N4cuda3std3__417integral_constantIbLb1EEE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElPiEET3_RNS0_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_N4cuda3std3__417integral_constantIbLb1EEE,comdat .size _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElPiEET3_RNS0_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_N4cuda3std3__417integral_constantIbLb1EEE, .-_ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElPiEET3_RNS0_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_N4cuda3std3__417integral_constantIbLb1EEE .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SB_RNS1_18contiguous_storageIiS3_EE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SB_RNS1_18contiguous_storageIiS3_EE,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SB_RNS1_18contiguous_storageIiS3_EE .type _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SB_RNS1_18contiguous_storageIiS3_EE, @function _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SB_RNS1_18contiguous_storageIiS3_EE: .LFB13320: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13320 endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $16, %rsp .cfi_def_cfa_offset 48 movq %rdx, %r12 movq %r8, %rbp movq %fs:40, %rdx movq %rdx, 8(%rsp) xorl %edx, %edx testq %rsi, %rsi je .L2041 movq %rsi, %rax movq %rcx, %rbx movq 16(%rdi), %rsi addq %rsi, %rsi cmpq %rax, %rsi cmovb %rax, %rsi movabsq $2305843009213693951, %rdx cmpq %rdx, %rsi cmova %rdx, %rsi cmpq %rax, %rsi jb .L2042 movq %r8, %rdi .LEHB99: call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE8allocateEm .LEHE99: subq %r12, %rbx movq %rbx, %rcx sarq $2, %rcx leaq 7(%rsp), %rsi leaq 6(%rsp), %rdi movq 8(%rbp), %r8 movq %r12, %rdx .LEHB100: call _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElPiEET3_RNS0_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_N4cuda3std3__417integral_constantIbLb1EEE .LEHE100: jmp .L2025 .L2041: movq %r8, %rdi call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE10deallocateEv .L2025: movq 8(%rsp), %rax subq %fs:40, %rax jne .L2043 addq $16, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L2042: .cfi_restore_state movl $16, %edi call __cxa_allocate_exception@PLT movq %rax, %rbx leaq .LC62(%rip), %rsi movq %rax, %rdi .LEHB101: call _ZNSt12length_errorC1EPKc@PLT .LEHE101: movq 8(%rsp), %rax subq %fs:40, %rax je .L2029 call __stack_chk_fail@PLT .L2029: movq _ZNSt12length_errorD1Ev@GOTPCREL(%rip), %rdx leaq _ZTISt12length_error(%rip), %rsi movq %rbx, %rdi .LEHB102: call __cxa_throw@PLT .L2037: endbr64 movq %rax, %rbp movq %rbx, %rdi call __cxa_free_exception@PLT movq 8(%rsp), %rax subq %fs:40, %rax je .L2031 call __stack_chk_fail@PLT .L2031: movq %rbp, %rdi call _Unwind_Resume@PLT .LEHE102: .L2038: endbr64 movq %rax, %rdi call __cxa_begin_catch@PLT movq %rbp, %rdi call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE10deallocateEv movq 8(%rsp), %rax subq %fs:40, %rax je .L2033 call __stack_chk_fail@PLT .L2033: .LEHB103: call __cxa_rethrow@PLT .LEHE103: .L2039: endbr64 movq %rax, %rbx call __cxa_end_catch@PLT movq 8(%rsp), %rax subq %fs:40, %rax je .L2035 call __stack_chk_fail@PLT .L2035: movq %rbx, %rdi .LEHB104: call _Unwind_Resume@PLT .LEHE104: .L2043: call __stack_chk_fail@PLT .cfi_endproc .LFE13320: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SB_RNS1_18contiguous_storageIiS3_EE,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SB_RNS1_18contiguous_storageIiS3_EE,comdat .align 4 .LLSDA13320: .byte 0xff .byte 0x9b .uleb128 .LLSDATT13320-.LLSDATTD13320 .LLSDATTD13320: .byte 0x1 .uleb128 .LLSDACSE13320-.LLSDACSB13320 .LLSDACSB13320: .uleb128 .LEHB99-.LFB13320 .uleb128 .LEHE99-.LEHB99 .uleb128 0 .uleb128 0 .uleb128 .LEHB100-.LFB13320 .uleb128 .LEHE100-.LEHB100 .uleb128 .L2038-.LFB13320 .uleb128 0x1 .uleb128 .LEHB101-.LFB13320 .uleb128 .LEHE101-.LEHB101 .uleb128 .L2037-.LFB13320 .uleb128 0 .uleb128 .LEHB102-.LFB13320 .uleb128 .LEHE102-.LEHB102 .uleb128 0 .uleb128 0 .uleb128 .LEHB103-.LFB13320 .uleb128 .LEHE103-.LEHB103 .uleb128 .L2039-.LFB13320 .uleb128 0 .uleb128 .LEHB104-.LFB13320 .uleb128 .LEHE104-.LEHB104 .uleb128 0 .uleb128 0 .LLSDACSE13320: .byte 0x1 .byte 0 .align 4 .long 0 .LLSDATT13320: .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SB_RNS1_18contiguous_storageIiS3_EE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SB_RNS1_18contiguous_storageIiS3_EE,comdat .size _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SB_RNS1_18contiguous_storageIiS3_EE, .-_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SB_RNS1_18contiguous_storageIiS3_EE .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE12range_assignINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvT_SB_NS0_27random_access_traversal_tagE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE12range_assignINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvT_SB_NS0_27random_access_traversal_tagE,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE12range_assignINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvT_SB_NS0_27random_access_traversal_tagE .type _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE12range_assignINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvT_SB_NS0_27random_access_traversal_tagE, @function _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE12range_assignINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvT_SB_NS0_27random_access_traversal_tagE: .LFB13235: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA13235 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %rdi, %rbx movq %rsi, %rax movq %rdx, %r12 movq %fs:40, %rdx movq %rdx, 40(%rsp) xorl %edx, %edx movq %r12, %rbp subq %rsi, %rbp sarq $2, %rbp cmpq %rbp, 16(%rdi) jb .L2053 movq 24(%rdi), %rcx cmpq %rbp, %rcx jb .L2047 leaq 15(%rsp), %rdi leaq 16(%rsp), %rsi movq 8(%rbx), %r8 movq %rbp, %rcx movq %rax, %rdx .LEHB105: call _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_ .LEHE105: movq %rbp, 24(%rbx) .L2044: movq 40(%rsp), %rax subq %fs:40, %rax jne .L2054 addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L2053: .cfi_restore_state movq $0, 24(%rsp) movq $0, 32(%rsp) leaq 16(%rsp), %r8 movq %r12, %rcx movq %rsi, %rdx movq %rbp, %rsi .LEHB106: call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE17allocate_and_copyINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvmT_SB_RNS1_18contiguous_storageIiS3_EE .LEHE106: movq 8(%rbx), %rax movq 24(%rsp), %rdx movq %rdx, 8(%rbx) movq %rax, 24(%rsp) movq 16(%rbx), %rax movq 32(%rsp), %rdx movq %rdx, 16(%rbx) movq %rax, 32(%rsp) movq %rbp, 24(%rbx) leaq 16(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE10deallocateEv jmp .L2044 .L2047: salq $2, %rcx leaq (%rsi,%rcx), %r15 leaq 15(%rsp), %r13 leaq 16(%rsp), %r14 sarq $2, %rcx movq 8(%rdi), %r8 movq %rsi, %rdx movq %r13, %rdi movq %r14, %rsi .LEHB107: call _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElNSA_IPiEEEET3_NS1_12cross_systemIT_T0_EET1_T2_SH_ movq %rbx, %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE3endEv movq %rax, %r8 movq %r12, %rcx subq %r15, %rcx sarq $2, %rcx movq %r15, %rdx movq %r14, %rsi movq %r13, %rdi call _ZN6thrust20THRUST_200700_800_NS8cuda_cub6__copy19cross_system_copy_nINS1_3tagENS0_6system3cpp6detail3tagENS0_6detail15normal_iteratorINS0_10device_ptrIKiEEEElPiEET3_RNS0_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_N4cuda3std3__417integral_constantIbLb1EEE movq %rbp, 24(%rbx) jmp .L2044 .L2051: endbr64 movq %rax, %rbx leaq 16(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE10deallocateEv movq 40(%rsp), %rax subq %fs:40, %rax je .L2049 call __stack_chk_fail@PLT .L2049: movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE107: .L2054: call __stack_chk_fail@PLT .cfi_endproc .LFE13235: .section .gcc_except_table._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE12range_assignINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvT_SB_NS0_27random_access_traversal_tagE,"aG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE12range_assignINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvT_SB_NS0_27random_access_traversal_tagE,comdat .LLSDA13235: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE13235-.LLSDACSB13235 .LLSDACSB13235: .uleb128 .LEHB105-.LFB13235 .uleb128 .LEHE105-.LEHB105 .uleb128 0 .uleb128 0 .uleb128 .LEHB106-.LFB13235 .uleb128 .LEHE106-.LEHB106 .uleb128 .L2051-.LFB13235 .uleb128 0 .uleb128 .LEHB107-.LFB13235 .uleb128 .LEHE107-.LEHB107 .uleb128 0 .uleb128 0 .LLSDACSE13235: .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE12range_assignINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvT_SB_NS0_27random_access_traversal_tagE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE12range_assignINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvT_SB_NS0_27random_access_traversal_tagE,comdat .size _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE12range_assignINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvT_SB_NS0_27random_access_traversal_tagE, .-_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE12range_assignINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvT_SB_NS0_27random_access_traversal_tagE .section .text._ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEEaSIiNS0_16device_allocatorIiEEEERS4_RKNS2_IT_T0_EE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEEaSIiNS0_16device_allocatorIiEEEERS4_RKNS2_IT_T0_EE,comdat .align 2 .weak _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEEaSIiNS0_16device_allocatorIiEEEERS4_RKNS2_IT_T0_EE .type _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEEaSIiNS0_16device_allocatorIiEEEERS4_RKNS2_IT_T0_EE, @function _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEEaSIiNS0_16device_allocatorIiEEEERS4_RKNS2_IT_T0_EE: .LFB12799: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movq %rsi, %rbp movq %rsi, %rdi call _ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE3endEv movq %rax, %r12 movq %rbp, %rdi call _ZNK6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5beginEv movq %rax, %rsi movq %r12, %rdx movq %rbx, %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEE12range_assignINS1_15normal_iteratorINS0_10device_ptrIKiEEEEEEvT_SB_NS0_27random_access_traversal_tagE movq %rbx, %rax popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE12799: .size _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEEaSIiNS0_16device_allocatorIiEEEERS4_RKNS2_IT_T0_EE, .-_ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEEaSIiNS0_16device_allocatorIiEEEERS4_RKNS2_IT_T0_EE .section .rodata.str1.8 .align 8 .LC72: .string "Failed to create start event (error code %s)!\n" .align 8 .LC73: .string "Failed to create stop event (error code %s)!\n" .align 8 .LC74: .string "Failed to record start event (error code %s)!\n" .align 8 .LC79: .string "Failed to record stop event (error code %s)!\n" .align 8 .LC80: .string "Failed to synchronize on the stop event (error code %s)!\n" .align 8 .LC82: .string "Failed to get time elapsed between events (error code %s)!\n" .section .rodata.str1.1 .LC83: .string "Wynik: " .LC84: .string "W czasie:" .text .globl main .type main, @function main: .LFB12052: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA12052 endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $176, %rsp .cfi_def_cfa_offset 224 movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax movq $0, 40(%rsp) movq $0, 48(%rsp) movq $0, 56(%rsp) leaq 32(%rsp), %rdi movl $939289, %esi .LEHB108: call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE8allocateEm .LEHE108: movq $939289, 56(%rsp) movq 40(%rsp), %rbp leaq 3757156(%rbp), %rbx movq %rbp, %rax .L2058: movl $1, (%rax) addq $4, %rax cmpq %rbx, %rax jne .L2058 call _ZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_v movq %rax, 64(%rsp) movq $0, 72(%rsp) movq $0, 80(%rsp) movq $0, 88(%rsp) leaq 64(%rsp), %rdi movq %rdi, %r8 movq %rbx, %rcx movq %rbp, %rdx movl $939289, %esi .LEHB109: call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE17allocate_and_copyINS1_15normal_iteratorIPKiEEEEvmT_SB_RNS1_18contiguous_storageIiS4_EE .LEHE109: jmp .L2098 .L2090: endbr64 movq %rax, %rbx leaq 32(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiSaIiEE10deallocateEv movq 168(%rsp), %rax subq %fs:40, %rax je .L2061 call __stack_chk_fail@PLT .L2061: movq %rbx, %rdi .LEHB110: call _Unwind_Resume@PLT .LEHE110: .L2098: movq $939289, 88(%rsp) call _ZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_v movq %rax, 96(%rsp) movq $0, 104(%rsp) movq $0, 112(%rsp) movq $0, 120(%rsp) leaq 96(%rsp), %rdi movl $918, %esi .LEHB111: call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE8allocateEm jmp .L2099 .L2089: endbr64 movq %rax, %rbx leaq 64(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv .L2064: leaq 32(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED2Ev movq 168(%rsp), %rax subq %fs:40, %rax je .L2084 call __stack_chk_fail@PLT .L2099: movq $918, 120(%rsp) leaq 128(%rsp), %rdi movl $918, %ecx movq 104(%rsp), %rsi movl $0, %edx call _ZN6thrust20THRUST_200700_800_NS8cuda_cub12parallel_forINS1_3tagENS1_20__uninitialized_fill7functorINS0_10device_ptrIiEEiEEmEEvRNS1_16execution_policyIT_EET0_T1_ .LEHE111: leaq 96(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE4dataEv movq %rax, %r12 leaq 64(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE4dataEv movq %rax, %r13 movq %rsp, %rdi .LEHB112: call cudaEventCreate@PLT testl %eax, %eax jne .L2100 leaq 8(%rsp), %rdi call cudaEventCreate@PLT jmp .L2101 .L2091: endbr64 movq %rax, %rbx leaq 96(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail18contiguous_storageIiNS0_16device_allocatorIiEEE10deallocateEv .L2067: leaq 64(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED2Ev jmp .L2064 .L2100: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC72(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L2101: testl %eax, %eax jne .L2102 movl $0, %esi movq (%rsp), %rdi call cudaEventRecord@PLT jmp .L2103 .L2102: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC73(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L2103: testl %eax, %eax jne .L2104 movl $1, %ebp movl $918, %ebx movl $939289, %r14d jmp .L2070 .L2104: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC74(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L2106: testl %eax, %eax je .L2105 .L2072: movl $0, %ebp .L2073: cmpl $1, %ebx je .L2075 pxor %xmm0, %xmm0 cvtsi2sdl %ebx, %xmm0 mulsd .LC75(%rip), %xmm0 movapd %xmm0, %xmm3 movsd .LC77(%rip), %xmm2 movapd %xmm0, %xmm1 andpd %xmm2, %xmm1 movsd .LC76(%rip), %xmm4 ucomisd %xmm1, %xmm4 jbe .L2076 cvttsd2siq %xmm0, %rax pxor %xmm1, %xmm1 cvtsi2sdq %rax, %xmm1 cmpnlesd %xmm1, %xmm3 movsd .LC78(%rip), %xmm5 andpd %xmm5, %xmm3 addsd %xmm1, %xmm3 andnpd %xmm0, %xmm2 orpd %xmm2, %xmm3 .L2076: movl %ebx, %r14d cvttsd2sil %xmm3, %ebx .L2070: testb %bpl, %bpl je .L2071 movl $1024, 128(%rsp) movl $1, 132(%rsp) movl $1, 136(%rsp) movl %ebx, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $0, %r9d movl $4096, %r8d movq 128(%rsp), %rdx movl $1, %ecx movq 20(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT jmp .L2106 .L2105: movl %r14d, %edx movq %r12, %rsi movq %r13, %rdi call _Z29__device_stub__Z7reduce0PiS_iPiS_i jmp .L2072 .L2071: movl $1024, 128(%rsp) movl $1, 132(%rsp) movl $1, 136(%rsp) movl %ebx, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $0, %r9d movl $4096, %r8d movq 128(%rsp), %rdx movl $1, %ecx movq 20(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L2107 .L2074: movl $1, %ebp jmp .L2073 .L2107: movl %r14d, %edx movq %r13, %rsi movq %r12, %rdi call _Z29__device_stub__Z7reduce0PiS_iPiS_i jmp .L2074 .L2075: movl $0, %esi movq 8(%rsp), %rdi call cudaEventRecord@PLT testl %eax, %eax jne .L2108 movq 8(%rsp), %rdi call cudaEventSynchronize@PLT jmp .L2109 .L2108: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC79(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L2109: testl %eax, %eax jne .L2110 movl $0x00000000, 20(%rsp) leaq 20(%rsp), %rdi movq 8(%rsp), %rdx movq (%rsp), %rsi call cudaEventElapsedTime@PLT jmp .L2111 .L2110: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC80(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT .LEHE112: movl $1, %edi call exit@PLT .L2111: testl %eax, %eax jne .L2112 movq $0, 136(%rsp) movq $0, 144(%rsp) movq $0, 152(%rsp) testb %bpl, %bpl je .L2080 leaq 64(%rsp), %rsi leaq 128(%rsp), %rdi .LEHB113: call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEEaSIiNS0_16device_allocatorIiEEEERS4_RKNS2_IT_T0_EE .LEHE113: jmp .L2081 .L2112: movl %eax, %edi .LEHB114: call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC82(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT .LEHE114: movl $1, %edi call exit@PLT .L2080: leaq 96(%rsp), %rsi leaq 128(%rsp), %rdi .LEHB115: call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEEaSIiNS0_16device_allocatorIiEEEERS4_RKNS2_IT_T0_EE .L2081: leaq 64(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5clearEv leaq 64(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE13shrink_to_fitEv leaq 96(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE5clearEv leaq 96(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEE13shrink_to_fitEv leaq .LC83(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq 136(%rsp), %rax movl (%rax), %esi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rax, %rdi leaq .LC84(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd 20(%rsp), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT .LEHE115: leaq 128(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED2Ev leaq 96(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED2Ev leaq 64(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED2Ev leaq 32(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED2Ev movq 168(%rsp), %rax subq %fs:40, %rax jne .L2113 movl $0, %eax addq $176, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L2088: .cfi_restore_state endbr64 movq %rax, %rbx leaq 128(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiSaIiEED2Ev .L2083: leaq 96(%rsp), %rdi call _ZN6thrust20THRUST_200700_800_NS6detail11vector_baseIiNS0_16device_allocatorIiEEED2Ev jmp .L2067 .L2087: endbr64 movq %rax, %rbx jmp .L2083 .L2084: movq %rbx, %rdi .LEHB116: call _Unwind_Resume@PLT .LEHE116: .L2113: call __stack_chk_fail@PLT .cfi_endproc .LFE12052: .section .gcc_except_table,"a",@progbits .LLSDA12052: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE12052-.LLSDACSB12052 .LLSDACSB12052: .uleb128 .LEHB108-.LFB12052 .uleb128 .LEHE108-.LEHB108 .uleb128 .L2090-.LFB12052 .uleb128 0 .uleb128 .LEHB109-.LFB12052 .uleb128 .LEHE109-.LEHB109 .uleb128 .L2089-.LFB12052 .uleb128 0 .uleb128 .LEHB110-.LFB12052 .uleb128 .LEHE110-.LEHB110 .uleb128 0 .uleb128 0 .uleb128 .LEHB111-.LFB12052 .uleb128 .LEHE111-.LEHB111 .uleb128 .L2091-.LFB12052 .uleb128 0 .uleb128 .LEHB112-.LFB12052 .uleb128 .LEHE112-.LEHB112 .uleb128 .L2087-.LFB12052 .uleb128 0 .uleb128 .LEHB113-.LFB12052 .uleb128 .LEHE113-.LEHB113 .uleb128 .L2088-.LFB12052 .uleb128 0 .uleb128 .LEHB114-.LFB12052 .uleb128 .LEHE114-.LEHB114 .uleb128 .L2087-.LFB12052 .uleb128 0 .uleb128 .LEHB115-.LFB12052 .uleb128 .LEHE115-.LEHB115 .uleb128 .L2088-.LFB12052 .uleb128 0 .uleb128 .LEHB116-.LFB12052 .uleb128 .LEHE116-.LEHB116 .uleb128 0 .uleb128 0 .LLSDACSE12052: .text .size main, .-main .weak _ZTSN4cuda3__410cuda_errorE .section .rodata._ZTSN4cuda3__410cuda_errorE,"aG",@progbits,_ZTSN4cuda3__410cuda_errorE,comdat .align 16 .type _ZTSN4cuda3__410cuda_errorE, @object .size _ZTSN4cuda3__410cuda_errorE, 24 _ZTSN4cuda3__410cuda_errorE: .string "N4cuda3__410cuda_errorE" .weak _ZTIN4cuda3__410cuda_errorE .section .data.rel.ro._ZTIN4cuda3__410cuda_errorE,"awG",@progbits,_ZTIN4cuda3__410cuda_errorE,comdat .align 8 .type _ZTIN4cuda3__410cuda_errorE, @object .size _ZTIN4cuda3__410cuda_errorE, 24 _ZTIN4cuda3__410cuda_errorE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN4cuda3__410cuda_errorE .quad _ZTISt13runtime_error .weak _ZTSN6thrust20THRUST_200700_800_NS6system14error_categoryE .section .rodata._ZTSN6thrust20THRUST_200700_800_NS6system14error_categoryE,"aG",@progbits,_ZTSN6thrust20THRUST_200700_800_NS6system14error_categoryE,comdat .align 32 .type _ZTSN6thrust20THRUST_200700_800_NS6system14error_categoryE, @object .size _ZTSN6thrust20THRUST_200700_800_NS6system14error_categoryE, 55 _ZTSN6thrust20THRUST_200700_800_NS6system14error_categoryE: .string "N6thrust20THRUST_200700_800_NS6system14error_categoryE" .weak _ZTIN6thrust20THRUST_200700_800_NS6system14error_categoryE .section .data.rel.ro._ZTIN6thrust20THRUST_200700_800_NS6system14error_categoryE,"awG",@progbits,_ZTIN6thrust20THRUST_200700_800_NS6system14error_categoryE,comdat .align 8 .type _ZTIN6thrust20THRUST_200700_800_NS6system14error_categoryE, @object .size _ZTIN6thrust20THRUST_200700_800_NS6system14error_categoryE, 16 _ZTIN6thrust20THRUST_200700_800_NS6system14error_categoryE: .quad _ZTVN10__cxxabiv117__class_type_infoE+16 .quad _ZTSN6thrust20THRUST_200700_800_NS6system14error_categoryE .weak _ZTSN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE .section .rodata._ZTSN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE,"aG",@progbits,_ZTSN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE,comdat .align 32 .type _ZTSN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE, @object .size _ZTSN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE, 70 _ZTSN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE: .string "N6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE" .weak _ZTIN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE .section .data.rel.ro._ZTIN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE,"awG",@progbits,_ZTIN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE,comdat .align 8 .type _ZTIN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE, @object .size _ZTIN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE, 24 _ZTIN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE .quad _ZTIN6thrust20THRUST_200700_800_NS6system14error_categoryE .weak _ZTSN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE .section .rodata._ZTSN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE,"aG",@progbits,_ZTSN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE,comdat .align 32 .type _ZTSN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE, @object .size _ZTSN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE, 69 _ZTSN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE: .string "N6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE" .weak _ZTIN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE .section .data.rel.ro._ZTIN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE,"awG",@progbits,_ZTIN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE,comdat .align 8 .type _ZTIN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE, @object .size _ZTIN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE, 24 _ZTIN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE .quad _ZTIN6thrust20THRUST_200700_800_NS6system14error_categoryE .weak _ZTSN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE .section .rodata._ZTSN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE,"aG",@progbits,_ZTSN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE,comdat .align 32 .type _ZTSN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE, @object .size _ZTSN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE, 76 _ZTSN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE: .string "N6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE" .weak _ZTIN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE .section .data.rel.ro._ZTIN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE,"awG",@progbits,_ZTIN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE,comdat .align 8 .type _ZTIN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE, @object .size _ZTIN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE, 24 _ZTIN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE .quad _ZTIN6thrust20THRUST_200700_800_NS6system14error_categoryE .weak _ZTSN6thrust20THRUST_200700_800_NS6system12system_errorE .section .rodata._ZTSN6thrust20THRUST_200700_800_NS6system12system_errorE,"aG",@progbits,_ZTSN6thrust20THRUST_200700_800_NS6system12system_errorE,comdat .align 32 .type _ZTSN6thrust20THRUST_200700_800_NS6system12system_errorE, @object .size _ZTSN6thrust20THRUST_200700_800_NS6system12system_errorE, 53 _ZTSN6thrust20THRUST_200700_800_NS6system12system_errorE: .string "N6thrust20THRUST_200700_800_NS6system12system_errorE" .weak _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE .section .data.rel.ro._ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE,"awG",@progbits,_ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE,comdat .align 8 .type _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE, @object .size _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE, 24 _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust20THRUST_200700_800_NS6system12system_errorE .quad _ZTISt13runtime_error .weak _ZTSN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE .section .rodata._ZTSN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE,"aG",@progbits,_ZTSN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE,comdat .align 32 .type _ZTSN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE, @object .size _ZTSN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE, 56 _ZTSN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE: .string "N6thrust20THRUST_200700_800_NS6system6detail9bad_allocE" .weak _ZTIN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE .section .data.rel.ro._ZTIN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE,"awG",@progbits,_ZTIN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE,comdat .align 8 .type _ZTIN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE, @object .size _ZTIN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE, 24 _ZTIN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE .quad _ZTISt9bad_alloc .weak _ZTSN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE .section .rodata._ZTSN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE,"aG",@progbits,_ZTSN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE,comdat .align 32 .type _ZTSN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE, @object .size _ZTSN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE, 67 _ZTSN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE: .string "N6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE" .weak _ZTIN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE .section .data.rel.ro._ZTIN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE,"awG",@progbits,_ZTIN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE,comdat .align 8 .type _ZTIN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE, @object .size _ZTIN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE, 24 _ZTIN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE .quad _ZTISt13runtime_error .weak _ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE .section .rodata._ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE,"aG",@progbits,_ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE,comdat .align 32 .type _ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE, @object .size _ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE, 74 _ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE: .string "N6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE" .weak _ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE .section .data.rel.ro._ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE,"awG",@progbits,_ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE,comdat .align 8 .type _ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE, @object .size _ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE, 16 _ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE: .quad _ZTVN10__cxxabiv117__class_type_infoE+16 .quad _ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE .weak _ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE .section .rodata._ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE,"aG",@progbits,_ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE,comdat .align 32 .type _ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE, @object .size _ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE, 135 _ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE: .string "N6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE" .weak _ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE .section .data.rel.ro._ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE,"awG",@progbits,_ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE,comdat .align 8 .type _ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE, @object .size _ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE, 16 _ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE: .quad _ZTVN10__cxxabiv117__class_type_infoE+16 .quad _ZTSN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE .weak _ZTSN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE .section .rodata._ZTSN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE,"aG",@progbits,_ZTSN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE,comdat .align 32 .type _ZTSN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE, @object .size _ZTSN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE, 193 _ZTSN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE: .string "N6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE" .weak _ZTIN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE .section .data.rel.ro._ZTIN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE,"awG",@progbits,_ZTIN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE,comdat .align 8 .type _ZTIN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE, @object .size _ZTIN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE, 24 _ZTIN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE .quad _ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEEE .weak _ZTSN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE .section .rodata._ZTSN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE,"aG",@progbits,_ZTSN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE,comdat .align 32 .type _ZTSN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE, @object .size _ZTSN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE, 228 _ZTSN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE: .string "N6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE" .weak _ZTIN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE .section .data.rel.ro._ZTIN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE,"awG",@progbits,_ZTIN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE,comdat .align 8 .type _ZTIN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE, @object .size _ZTIN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE, 24 _ZTIN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE .quad _ZTIN6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEEE .weak _ZTVN4cuda3__410cuda_errorE .section .data.rel.ro._ZTVN4cuda3__410cuda_errorE,"awG",@progbits,_ZTVN4cuda3__410cuda_errorE,comdat .align 8 .type _ZTVN4cuda3__410cuda_errorE, @object .size _ZTVN4cuda3__410cuda_errorE, 40 _ZTVN4cuda3__410cuda_errorE: .quad 0 .quad _ZTIN4cuda3__410cuda_errorE .quad _ZN4cuda3__410cuda_errorD1Ev .quad _ZN4cuda3__410cuda_errorD0Ev .quad _ZNKSt13runtime_error4whatEv .weak _ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE .section .data.rel.ro.local._ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE,"awG",@progbits,_ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE,comdat .align 8 .type _ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE, @object .size _ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE, 72 _ZTVN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE: .quad 0 .quad _ZTIN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryE .quad _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD1Ev .quad _ZN6thrust20THRUST_200700_800_NS6system6detail22generic_error_categoryD0Ev .quad _ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category4nameEv .quad _ZNK6thrust20THRUST_200700_800_NS6system14error_category23default_error_conditionEi .quad _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentEiRKNS1_15error_conditionE .quad _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentERKNS1_10error_codeEi .quad _ZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11Ei .weak _ZTVN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE .section .data.rel.ro.local._ZTVN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE,"awG",@progbits,_ZTVN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE,comdat .align 8 .type _ZTVN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE, @object .size _ZTVN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE, 72 _ZTVN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE: .quad 0 .quad _ZTIN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryE .quad _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD1Ev .quad _ZN6thrust20THRUST_200700_800_NS6system6detail21system_error_categoryD0Ev .quad _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category4nameEv .quad _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category23default_error_conditionEi .quad _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentEiRKNS1_15error_conditionE .quad _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentERKNS1_10error_codeEi .quad _ZNK6thrust20THRUST_200700_800_NS6system6detail21system_error_category7messageB5cxx11Ei .weak _ZTVN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE .section .data.rel.ro.local._ZTVN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE,"awG",@progbits,_ZTVN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE,comdat .align 8 .type _ZTVN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE, @object .size _ZTVN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE, 72 _ZTVN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE: .quad 0 .quad _ZTIN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryE .quad _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD1Ev .quad _ZN6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_categoryD0Ev .quad _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category4nameEv .quad _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category23default_error_conditionEi .quad _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentEiRKNS1_15error_conditionE .quad _ZNK6thrust20THRUST_200700_800_NS6system14error_category10equivalentERKNS1_10error_codeEi .quad _ZNK6thrust20THRUST_200700_800_NS6system8cuda_cub6detail19cuda_error_category7messageB5cxx11Ei .weak _ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE .section .data.rel.ro.local._ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE,"awG",@progbits,_ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE,comdat .align 8 .type _ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE, @object .size _ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE, 40 _ZTVN6thrust20THRUST_200700_800_NS6system12system_errorE: .quad 0 .quad _ZTIN6thrust20THRUST_200700_800_NS6system12system_errorE .quad _ZN6thrust20THRUST_200700_800_NS6system12system_errorD1Ev .quad _ZN6thrust20THRUST_200700_800_NS6system12system_errorD0Ev .quad _ZNK6thrust20THRUST_200700_800_NS6system12system_error4whatEv .weak _ZTVN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE .section .data.rel.ro.local._ZTVN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE,"awG",@progbits,_ZTVN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE,comdat .align 8 .type _ZTVN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE, @object .size _ZTVN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE, 40 _ZTVN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE: .quad 0 .quad _ZTIN6thrust20THRUST_200700_800_NS6system6detail9bad_allocE .quad _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD1Ev .quad _ZN6thrust20THRUST_200700_800_NS6system6detail9bad_allocD0Ev .quad _ZNK6thrust20THRUST_200700_800_NS6system6detail9bad_alloc4whatEv .weak _ZTVN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE .section .data.rel.ro._ZTVN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE,"awG",@progbits,_ZTVN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE,comdat .align 8 .type _ZTVN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE, @object .size _ZTVN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE, 40 _ZTVN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE: .quad 0 .quad _ZTIN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapE .quad _ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD1Ev .quad _ZN6thrust20THRUST_200700_800_NS6detail26allocator_mismatch_on_swapD0Ev .quad _ZNKSt13runtime_error4whatEv .weak _ZTVN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE .section .data.rel.ro.local._ZTVN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE,"awG",@progbits,_ZTVN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE,comdat .align 8 .type _ZTVN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE, @object .size _ZTVN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE, 56 _ZTVN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE: .quad 0 .quad _ZTIN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEEE .quad _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED1Ev .quad _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEED0Ev .quad _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE11do_allocateEmm .quad _ZN6thrust20THRUST_200700_800_NS6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS7_EENS0_11use_defaultEEEE13do_deallocateESB_mm .quad _ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS5_EENS0_11use_defaultEEEE11do_is_equalERKSA_ .weak _ZTVN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE .section .data.rel.ro.local._ZTVN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE,"awG",@progbits,_ZTVN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE,comdat .align 8 .type _ZTVN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE, @object .size _ZTVN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE, 56 _ZTVN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE: .quad 0 .quad _ZTIN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEEE .quad _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED1Ev .quad _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEED0Ev .quad _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE11do_allocateEmm .quad _ZN6thrust20THRUST_200700_800_NS26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS8_EENS0_11use_defaultEEEEEE13do_deallocateENS0_10device_ptrIvEEmm .quad _ZNK6thrust20THRUST_200700_800_NS2mr15memory_resourceINS0_10device_ptrIvEEE11do_is_equalERKS5_ .weak _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d .section .bss._ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d,"awG",@nobits,_ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d,comdat .align 8 .type _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d, @gnu_unique_object .size _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d, 8 _ZGVZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d: .zero 8 .weak _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d .section .bss._ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d,"awG",@nobits,_ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d,comdat .align 8 .type _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d, @gnu_unique_object .size _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d, 8 _ZZN5nvtx32v16domain3getIN3cub17CUB_200700_800_NS6detail14NVTXCCCLDomainELi0EEERKS1_vE1d: .zero 8 .weak _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr .section .bss._ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr,"awG",@nobits,_ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr,comdat .align 8 .type _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr, @gnu_unique_object .size _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr, 8 _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr: .zero 8 .weak _ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr .section .bss._ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr,"awG",@nobits,_ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr,comdat .align 32 .type _ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr, @gnu_unique_object .size _ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr, 48 _ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_attr: .zero 48 .weak _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name .section .bss._ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name,"awG",@nobits,_ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name,comdat .align 8 .type _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name, @gnu_unique_object .size _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name, 8 _ZGVZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name: .zero 8 .weak _ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name .section .bss._ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name,"awG",@nobits,_ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name,comdat .align 8 .type _ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name, @gnu_unique_object .size _ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name, 8 _ZZN3cub17CUB_200700_800_NS9DeviceFor4BulkImN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS4_10device_ptrIiEEiEEEE9cudaErrorT_T0_P11CUstream_stE21__cub_nvtx3_func_name: .zero 8 .weak _ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource .section .bss._ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource,"awG",@nobits,_ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource,comdat .align 8 .type _ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource, @gnu_unique_object .size _ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource, 8 _ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource: .zero 8 .weak _ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource .section .data.rel.local._ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource,"awG",@progbits,_ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvS9_EENS0_11use_defaultEEEEEEEPT_vE8resource,comdat .align 8 .type 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_ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource, @gnu_unique_object .size _ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource, 8 _ZGVZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource: .zero 8 .weak _ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource .section .bss._ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource,"awG",@nobits,_ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource,comdat .align 16 .type _ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource, @gnu_unique_object .size _ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource, 16 _ZZN6thrust20THRUST_200700_800_NS2mr19get_global_resourceINS0_26device_ptr_memory_resourceINS0_6system4cuda6detail20cuda_memory_resourceIXadL_Z10cudaMallocEEXadL_Z8cudaFreeEENS0_7pointerIvNS0_8cuda_cub3tagENS0_16tagged_referenceIvSA_EENS0_11use_defaultEEEEEEEEEPT_vE8resource: .zero 16 .weak _ZGVZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache .section .bss._ZGVZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache,"awG",@nobits,_ZGVZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache,comdat .align 8 .type _ZGVZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache, @gnu_unique_object .size _ZGVZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache, 8 _ZGVZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache: .zero 8 .weak _ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache .section .bss._ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache,"awG",@nobits,_ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache,comdat .align 32 .type _ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache, @gnu_unique_object .size _ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache, 1536 _ZZN3cub17CUB_200700_800_NS26GetPerDeviceAttributeCacheINS0_18PtxVersionCacheTagEEERNS0_23PerDeviceAttributeCacheEvE5cache: .zero 1536 .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata .type _ZN6thrust20THRUST_200700_800_NSL6deviceE, @object .size _ZN6thrust20THRUST_200700_800_NSL6deviceE, 1 _ZN6thrust20THRUST_200700_800_NSL6deviceE: .zero 1 .type _ZN6thrust20THRUST_200700_800_NS6system3cppL3parE, @object .size _ZN6thrust20THRUST_200700_800_NS6system3cppL3parE, 1 _ZN6thrust20THRUST_200700_800_NS6system3cppL3parE: .zero 1 .weak _ZN4cuda3std3__420unreachable_sentinelE .section .rodata._ZN4cuda3std3__420unreachable_sentinelE,"aG",@progbits,_ZN4cuda3std3__420unreachable_sentinelE,comdat .type _ZN4cuda3std3__420unreachable_sentinelE, @gnu_unique_object .size _ZN4cuda3std3__420unreachable_sentinelE, 1 _ZN4cuda3std3__420unreachable_sentinelE: .zero 1 .weak _ZN4cuda3std3__45__cpo5crendE .section .rodata._ZN4cuda3std3__45__cpo5crendE,"aG",@progbits,_ZN4cuda3std3__45__cpo5crendE,comdat .type _ZN4cuda3std3__45__cpo5crendE, @gnu_unique_object .size _ZN4cuda3std3__45__cpo5crendE, 1 _ZN4cuda3std3__45__cpo5crendE: .zero 1 .weak _ZN4cuda3std3__45__cpo7crbeginE .section .rodata._ZN4cuda3std3__45__cpo7crbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo7crbeginE,comdat .type _ZN4cuda3std3__45__cpo7crbeginE, @gnu_unique_object .size _ZN4cuda3std3__45__cpo7crbeginE, 1 _ZN4cuda3std3__45__cpo7crbeginE: .zero 1 .weak _ZN4cuda3std3__45__cpo4rendE .section .rodata._ZN4cuda3std3__45__cpo4rendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4rendE,comdat .type _ZN4cuda3std3__45__cpo4rendE, @gnu_unique_object .size _ZN4cuda3std3__45__cpo4rendE, 1 _ZN4cuda3std3__45__cpo4rendE: .zero 1 .weak _ZN4cuda3std3__45__cpo6rbeginE .section .rodata._ZN4cuda3std3__45__cpo6rbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6rbeginE,comdat .type _ZN4cuda3std3__45__cpo6rbeginE, @gnu_unique_object .size _ZN4cuda3std3__45__cpo6rbeginE, 1 _ZN4cuda3std3__45__cpo6rbeginE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo8distanceE .section .rodata._ZN4cuda3std6ranges3__45__cpo8distanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo8distanceE,comdat .type _ZN4cuda3std6ranges3__45__cpo8distanceE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo8distanceE, 1 _ZN4cuda3std6ranges3__45__cpo8distanceE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo5ssizeE .section .rodata._ZN4cuda3std6ranges3__45__cpo5ssizeE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo5ssizeE,comdat .type _ZN4cuda3std6ranges3__45__cpo5ssizeE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo5ssizeE, 1 _ZN4cuda3std6ranges3__45__cpo5ssizeE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4sizeE .section .rodata._ZN4cuda3std6ranges3__45__cpo4sizeE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4sizeE,comdat .type _ZN4cuda3std6ranges3__45__cpo4sizeE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4sizeE, 1 _ZN4cuda3std6ranges3__45__cpo4sizeE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo5cdataE .section .rodata._ZN4cuda3std6ranges3__45__cpo5cdataE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo5cdataE,comdat .type _ZN4cuda3std6ranges3__45__cpo5cdataE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo5cdataE, 1 _ZN4cuda3std6ranges3__45__cpo5cdataE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4dataE .section .rodata._ZN4cuda3std6ranges3__45__cpo4dataE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4dataE,comdat .type _ZN4cuda3std6ranges3__45__cpo4dataE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4dataE, 1 _ZN4cuda3std6ranges3__45__cpo4dataE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4prevE .section .rodata._ZN4cuda3std6ranges3__45__cpo4prevE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4prevE,comdat .type _ZN4cuda3std6ranges3__45__cpo4prevE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4prevE, 1 _ZN4cuda3std6ranges3__45__cpo4prevE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4nextE .section .rodata._ZN4cuda3std6ranges3__45__cpo4nextE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4nextE,comdat .type _ZN4cuda3std6ranges3__45__cpo4nextE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4nextE, 1 _ZN4cuda3std6ranges3__45__cpo4nextE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo9iter_swapE .section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_swapE,comdat .type _ZN4cuda3std6ranges3__45__cpo9iter_swapE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo9iter_swapE, 1 _ZN4cuda3std6ranges3__45__cpo9iter_swapE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4cendE .section .rodata._ZN4cuda3std6ranges3__45__cpo4cendE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4cendE,comdat .type _ZN4cuda3std6ranges3__45__cpo4cendE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4cendE, 1 _ZN4cuda3std6ranges3__45__cpo4cendE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo6cbeginE .section .rodata._ZN4cuda3std6ranges3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo6cbeginE,comdat .type _ZN4cuda3std6ranges3__45__cpo6cbeginE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo6cbeginE, 1 _ZN4cuda3std6ranges3__45__cpo6cbeginE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo3endE .section .rodata._ZN4cuda3std6ranges3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo3endE,comdat .type _ZN4cuda3std6ranges3__45__cpo3endE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo3endE, 1 _ZN4cuda3std6ranges3__45__cpo3endE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo5beginE .section .rodata._ZN4cuda3std6ranges3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo5beginE,comdat .type _ZN4cuda3std6ranges3__45__cpo5beginE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo5beginE, 1 _ZN4cuda3std6ranges3__45__cpo5beginE: .zero 1 .weak _ZN4cuda3std3__47nulloptE .section .rodata._ZN4cuda3std3__47nulloptE,"aG",@progbits,_ZN4cuda3std3__47nulloptE,comdat .type _ZN4cuda3std3__47nulloptE, @gnu_unique_object .size _ZN4cuda3std3__47nulloptE, 1 _ZN4cuda3std3__47nulloptE: .zero 1 .hidden InitializeInjectionNvtx2_fnptr .weak InitializeInjectionNvtx2_fnptr .bss .align 8 .type InitializeInjectionNvtx2_fnptr, @object .size InitializeInjectionNvtx2_fnptr, 8 InitializeInjectionNvtx2_fnptr: .zero 8 .hidden nvtxGlobals_v3 .weak nvtxGlobals_v3 .section .data.rel.local,"aw" .align 32 .type nvtxGlobals_v3, @object .size nvtxGlobals_v3, 1168 nvtxGlobals_v3: .long 0 .zero 4 .quad 16 .quad nvtxEtiGetModuleFunctionTable_v3 .quad 24 .long 3 .long 0 .quad nvtxEtiSetInjectionNvtxVersion_v3 .quad nvtxMarkEx_impl_init_v3 .quad nvtxMarkA_impl_init_v3 .quad nvtxMarkW_impl_init_v3 .quad nvtxRangeStartEx_impl_init_v3 .quad nvtxRangeStartA_impl_init_v3 .quad nvtxRangeStartW_impl_init_v3 .quad nvtxRangeEnd_impl_init_v3 .quad nvtxRangePushEx_impl_init_v3 .quad nvtxRangePushA_impl_init_v3 .quad nvtxRangePushW_impl_init_v3 .quad nvtxRangePop_impl_init_v3 .quad nvtxNameCategoryA_impl_init_v3 .quad nvtxNameCategoryW_impl_init_v3 .quad nvtxNameOsThreadA_impl_init_v3 .quad nvtxNameOsThreadW_impl_init_v3 .quad nvtxNameCuDeviceA_impl_init_v3 .quad nvtxNameCuDeviceW_impl_init_v3 .quad nvtxNameCuContextA_impl_init_v3 .quad nvtxNameCuContextW_impl_init_v3 .quad nvtxNameCuStreamA_impl_init_v3 .quad nvtxNameCuStreamW_impl_init_v3 .quad nvtxNameCuEventA_impl_init_v3 .quad nvtxNameCuEventW_impl_init_v3 .quad nvtxNameClDeviceA_impl_init_v3 .quad nvtxNameClDeviceW_impl_init_v3 .quad nvtxNameClContextA_impl_init_v3 .quad nvtxNameClContextW_impl_init_v3 .quad nvtxNameClCommandQueueA_impl_init_v3 .quad nvtxNameClCommandQueueW_impl_init_v3 .quad nvtxNameClMemObjectA_impl_init_v3 .quad nvtxNameClMemObjectW_impl_init_v3 .quad nvtxNameClSamplerA_impl_init_v3 .quad nvtxNameClSamplerW_impl_init_v3 .quad nvtxNameClProgramA_impl_init_v3 .quad nvtxNameClProgramW_impl_init_v3 .quad nvtxNameClEventA_impl_init_v3 .quad nvtxNameClEventW_impl_init_v3 .quad nvtxNameCudaDeviceA_impl_init_v3 .quad nvtxNameCudaDeviceW_impl_init_v3 .quad nvtxNameCudaStreamA_impl_init_v3 .quad nvtxNameCudaStreamW_impl_init_v3 .quad nvtxNameCudaEventA_impl_init_v3 .quad nvtxNameCudaEventW_impl_init_v3 .quad nvtxDomainMarkEx_impl_init_v3 .quad nvtxDomainRangeStartEx_impl_init_v3 .quad nvtxDomainRangeEnd_impl_init_v3 .quad nvtxDomainRangePushEx_impl_init_v3 .quad nvtxDomainRangePop_impl_init_v3 .quad nvtxDomainResourceCreate_impl_init_v3 .quad nvtxDomainResourceDestroy_impl_init_v3 .quad nvtxDomainNameCategoryA_impl_init_v3 .quad nvtxDomainNameCategoryW_impl_init_v3 .quad nvtxDomainRegisterStringA_impl_init_v3 .quad nvtxDomainRegisterStringW_impl_init_v3 .quad nvtxDomainCreateA_impl_init_v3 .quad nvtxDomainCreateW_impl_init_v3 .quad nvtxDomainDestroy_impl_init_v3 .quad nvtxInitialize_impl_init_v3 .quad nvtxDomainSyncUserCreate_impl_init_v3 .quad nvtxDomainSyncUserDestroy_impl_init_v3 .quad nvtxDomainSyncUserAcquireStart_impl_init_v3 .quad nvtxDomainSyncUserAcquireFailed_impl_init_v3 .quad nvtxDomainSyncUserAcquireSuccess_impl_init_v3 .quad nvtxDomainSyncUserReleasing_impl_init_v3 .quad 0 .quad nvtxGlobals_v3+48 .quad nvtxGlobals_v3+56 .quad nvtxGlobals_v3+64 .quad nvtxGlobals_v3+72 .quad nvtxGlobals_v3+80 .quad nvtxGlobals_v3+88 .quad nvtxGlobals_v3+96 .quad nvtxGlobals_v3+104 .quad nvtxGlobals_v3+112 .quad nvtxGlobals_v3+120 .quad nvtxGlobals_v3+128 .quad nvtxGlobals_v3+136 .quad nvtxGlobals_v3+144 .quad nvtxGlobals_v3+152 .quad nvtxGlobals_v3+160 .quad 0 .quad 0 .quad nvtxGlobals_v3+168 .quad nvtxGlobals_v3+176 .quad nvtxGlobals_v3+184 .quad nvtxGlobals_v3+192 .quad nvtxGlobals_v3+200 .quad nvtxGlobals_v3+208 .quad nvtxGlobals_v3+216 .quad nvtxGlobals_v3+224 .quad 0 .quad 0 .quad nvtxGlobals_v3+232 .quad nvtxGlobals_v3+240 .quad nvtxGlobals_v3+248 .quad nvtxGlobals_v3+256 .quad nvtxGlobals_v3+264 .quad nvtxGlobals_v3+272 .quad nvtxGlobals_v3+280 .quad nvtxGlobals_v3+288 .quad nvtxGlobals_v3+296 .quad nvtxGlobals_v3+304 .quad nvtxGlobals_v3+312 .quad nvtxGlobals_v3+320 .quad nvtxGlobals_v3+328 .quad nvtxGlobals_v3+336 .quad 0 .quad 0 .quad nvtxGlobals_v3+344 .quad nvtxGlobals_v3+352 .quad nvtxGlobals_v3+360 .quad nvtxGlobals_v3+368 .quad nvtxGlobals_v3+376 .quad nvtxGlobals_v3+384 .quad 0 .quad 0 .quad nvtxGlobals_v3+392 .quad nvtxGlobals_v3+400 .quad nvtxGlobals_v3+408 .quad nvtxGlobals_v3+416 .quad nvtxGlobals_v3+424 .quad nvtxGlobals_v3+432 .quad nvtxGlobals_v3+440 .quad nvtxGlobals_v3+448 .quad nvtxGlobals_v3+456 .quad nvtxGlobals_v3+464 .quad nvtxGlobals_v3+472 .quad nvtxGlobals_v3+480 .quad nvtxGlobals_v3+488 .quad nvtxGlobals_v3+496 .quad nvtxGlobals_v3+504 .quad 0 .quad 0 .quad nvtxGlobals_v3+512 .quad nvtxGlobals_v3+520 .quad nvtxGlobals_v3+528 .quad nvtxGlobals_v3+536 .quad nvtxGlobals_v3+544 .quad nvtxGlobals_v3+552 .quad 0 .section .rodata .type _ZN6thrust20THRUST_200700_800_NS8cuda_cubL10par_nosyncE, @object .size _ZN6thrust20THRUST_200700_800_NS8cuda_cubL10par_nosyncE, 1 _ZN6thrust20THRUST_200700_800_NS8cuda_cubL10par_nosyncE: .zero 1 .type _ZN6thrust20THRUST_200700_800_NS8cuda_cubL3parE, @object .size _ZN6thrust20THRUST_200700_800_NS8cuda_cubL3parE, 1 _ZN6thrust20THRUST_200700_800_NS8cuda_cubL3parE: .zero 1 .weak _ZGVZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result .section .bss._ZGVZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result,"awG",@nobits,_ZGVZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result,comdat .align 8 .type _ZGVZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result, @gnu_unique_object .size _ZGVZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result, 8 _ZGVZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result: .zero 8 .weak _ZZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result .section .bss._ZZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result,"awG",@nobits,_ZZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result,comdat .align 8 .type _ZZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result, @gnu_unique_object .size _ZZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result, 8 _ZZN6thrust20THRUST_200700_800_NS6system13cuda_categoryEvE6result: .zero 8 .weak _ZGVZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result .section .bss._ZGVZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result,"awG",@nobits,_ZGVZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result,comdat .align 8 .type _ZGVZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result, @gnu_unique_object .size _ZGVZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result, 8 _ZGVZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result: .zero 8 .weak _ZZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result .section .bss._ZZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result,"awG",@nobits,_ZZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result,comdat .align 8 .type _ZZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result, @gnu_unique_object .size _ZZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result, 8 _ZZN6thrust20THRUST_200700_800_NS6system15system_categoryEvE6result: .zero 8 .weak _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result .section .bss._ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result,"awG",@nobits,_ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result,comdat .align 8 .type _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result, @gnu_unique_object .size _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result, 8 _ZGVZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result: .zero 8 .weak _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result .section .bss._ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result,"awG",@nobits,_ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result,comdat .align 8 .type _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result, @gnu_unique_object .size _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result, 8 _ZZN6thrust20THRUST_200700_800_NS6system16generic_categoryEvE6result: .zero 8 .weak _ZGVZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err .section .bss._ZGVZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err,"awG",@nobits,_ZGVZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err,comdat .align 8 .type _ZGVZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err, @gnu_unique_object .size _ZGVZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err, 8 _ZGVZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err: .zero 8 .weak _ZZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err .section .bss._ZZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err,"awG",@nobits,_ZZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err,comdat .align 32 .type _ZZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err, @gnu_unique_object .size _ZZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err, 32 _ZZNK6thrust20THRUST_200700_800_NS6system6detail22generic_error_category7messageB5cxx11EiE11unknown_err: .zero 32 .section .rodata .type _ZN6thrust20THRUST_200700_800_NS12placeholdersL3_10E, @object .size _ZN6thrust20THRUST_200700_800_NS12placeholdersL3_10E, 1 _ZN6thrust20THRUST_200700_800_NS12placeholdersL3_10E: .zero 1 .type _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_9E, @object .size _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_9E, 1 _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_9E: .zero 1 .type _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_8E, @object .size _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_8E, 1 _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_8E: .zero 1 .type _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_7E, @object .size _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_7E, 1 _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_7E: .zero 1 .type _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_6E, @object .size _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_6E, 1 _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_6E: .zero 1 .type _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_5E, @object .size _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_5E, 1 _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_5E: .zero 1 .type _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_4E, @object .size _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_4E, 1 _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_4E: .zero 1 .type _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_3E, @object .size _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_3E, 1 _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_3E: .zero 1 .type _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_2E, @object .size _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_2E, 1 _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_2E: .zero 1 .type _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_1E, @object .size _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_1E, 1 _ZN6thrust20THRUST_200700_800_NS12placeholdersL2_1E: .zero 1 .weak _ZGVZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count .section .bss._ZGVZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count,"awG",@nobits,_ZGVZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count,comdat .align 8 .type _ZGVZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count, @gnu_unique_object .size _ZGVZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count, 8 _ZGVZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count: .zero 8 .weak _ZZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count .section .bss._ZZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count,"awG",@nobits,_ZZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count,comdat .align 4 .type _ZZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count, @gnu_unique_object .size _ZZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count, 4 _ZZN3cub17CUB_200700_800_NS22DeviceCountCachedValueEvE5count: .zero 4 .section .rodata .type _ZN6thrust20THRUST_200700_800_NSL3seqE, @object .size _ZN6thrust20THRUST_200700_800_NSL3seqE, 1 _ZN6thrust20THRUST_200700_800_NSL3seqE: .zero 1 .type _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, @object .size _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, 1 _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo7advanceE .section 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_ZN4cuda3std3__476_GLOBAL__N__dd01253e_43_c8162ff249296ec514785872e181e47080f71afe_cu_932465c36ignoreE: .zero 1 .weak _ZN4cuda3std3__48in_placeE .section .rodata._ZN4cuda3std3__48in_placeE,"aG",@progbits,_ZN4cuda3std3__48in_placeE,comdat .type _ZN4cuda3std3__48in_placeE, @gnu_unique_object .size _ZN4cuda3std3__48in_placeE, 1 _ZN4cuda3std3__48in_placeE: .zero 1 .weak _ZN4cuda3std3__45__cpo4cendE .section .rodata._ZN4cuda3std3__45__cpo4cendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4cendE,comdat .type _ZN4cuda3std3__45__cpo4cendE, @gnu_unique_object .size _ZN4cuda3std3__45__cpo4cendE, 1 _ZN4cuda3std3__45__cpo4cendE: .zero 1 .weak _ZN4cuda3std3__45__cpo6cbeginE .section .rodata._ZN4cuda3std3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6cbeginE,comdat .type _ZN4cuda3std3__45__cpo6cbeginE, @gnu_unique_object .size _ZN4cuda3std3__45__cpo6cbeginE, 1 _ZN4cuda3std3__45__cpo6cbeginE: .zero 1 .weak _ZN4cuda3std3__45__cpo3endE .section .rodata._ZN4cuda3std3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std3__45__cpo3endE,comdat .type _ZN4cuda3std3__45__cpo3endE, @gnu_unique_object .size _ZN4cuda3std3__45__cpo3endE, 1 _ZN4cuda3std3__45__cpo3endE: .zero 1 .weak _ZN4cuda3std3__45__cpo5beginE .section .rodata._ZN4cuda3std3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std3__45__cpo5beginE,comdat .type _ZN4cuda3std3__45__cpo5beginE, @gnu_unique_object .size _ZN4cuda3std3__45__cpo5beginE, 1 _ZN4cuda3std3__45__cpo5beginE: .zero 1 .weak _ZN4cuda3std3__419piecewise_constructE .section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat .type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object .size _ZN4cuda3std3__419piecewise_constructE, 1 _ZN4cuda3std3__419piecewise_constructE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE .section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat .type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1 _ZN4cuda3std6ranges3__45__cpo9iter_moveE: .zero 1 .weak _ZN4cuda3std6ranges3__45__cpo4swapE .section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat .type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object .size _ZN4cuda3std6ranges3__45__cpo4swapE, 1 _ZN4cuda3std6ranges3__45__cpo4swapE: .zero 1 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC75: .long 0 .long 1062207488 .align 8 .LC76: .long 0 .long 1127219200 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC77: .long -1 .long 2147483647 .long 0 .long 0 .section .rodata.cst8 .align 8 .LC78: .long 0 .long 1072693248 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .hidden __dso_handle .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z7reduce0PiS_i ; -- Begin function _Z7reduce0PiS_i .globl _Z7reduce0PiS_i .p2align 8 .type _Z7reduce0PiS_i,@function _Z7reduce0PiS_i: ; @_Z7reduce0PiS_i ; %bb.0: s_clause 0x1 s_load_b32 s3, s[0:1], 0x24 s_load_b32 s4, s[0:1], 0x10 s_mov_b32 s2, s15 v_lshl_add_u32 v3, v0, 2, 0 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1] v_mov_b32_e32 v2, 0 ds_store_b32 v3, v2 v_cmp_gt_u32_e32 vcc_lo, s4, v1 s_and_saveexec_b32 s4, vcc_lo s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b64 s[6:7], s[0:1], 0x0 v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, s6, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo global_load_b32 v1, v[1:2], off s_waitcnt vmcnt(0) ds_store_b32 v3, v1 .LBB0_2: s_or_b32 exec_lo, exec_lo, s4 s_cmp_lt_u32 s3, 2 s_waitcnt lgkmcnt(0) s_barrier s_branch .LBB0_4 .p2align 6 .LBB0_3: ; in Loop: Header=BB0_4 Depth=1 s_or_b32 exec_lo, exec_lo, s5 s_waitcnt lgkmcnt(0) s_barrier s_cmp_lt_u32 s3, 4 s_mov_b32 s3, s4 .LBB0_4: ; =>This Inner Loop Header: Depth=1 buffer_gl0_inv s_cbranch_scc1 .LBB0_7 ; %bb.5: ; %.lr.ph ; in Loop: Header=BB0_4 Depth=1 s_lshr_b32 s4, s3, 1 s_mov_b32 s5, exec_lo v_cmpx_gt_u32_e64 s4, v0 s_cbranch_execz .LBB0_3 ; %bb.6: ; in Loop: Header=BB0_4 Depth=1 v_add_nc_u32_e32 v1, s4, v0 s_delay_alu instid0(VALU_DEP_1) v_lshl_add_u32 v1, v1, 2, 0 ds_load_b32 v1, v1 ds_load_b32 v2, v3 s_waitcnt lgkmcnt(0) v_add_nc_u32_e32 v1, v2, v1 ds_store_b32 v3, v1 s_branch .LBB0_3 .LBB0_7: ; %._crit_edge s_mov_b32 s3, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_9 ; %bb.8: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 s_load_b64 s[0:1], s[0:1], 0x8 s_mov_b32 s3, 0 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b64 s[2:3], s[2:3], 2 ds_load_b32 v0, v0 s_waitcnt lgkmcnt(0) s_add_u32 s0, s0, s2 s_addc_u32 s1, s1, s3 global_store_b32 v1, v0, s[0:1] .LBB0_9: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z7reduce0PiS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z7reduce0PiS_i, .Lfunc_end0-_Z7reduce0PiS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 340 ; NumSgprs: 18 ; NumVgprs: 4 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 4 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ ; -- Begin function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_: ; @_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ ; %bb.0: s_load_b128 s[4:7], s[0:1], 0x10 s_lshl_b32 s2, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s2, s2, s6 s_addc_u32 s3, 0, s7 s_sub_u32 s4, s4, s2 s_subb_u32 s5, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s5, 0x100, s[4:5] s_and_b32 s5, s5, exec_lo s_cselect_b32 s4, s4, 0x100 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_cmpk_eq_i32 s4, 0x100 s_cselect_b32 s4, -1, 0 s_or_b32 s4, s4, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s5, s4 s_cbranch_execz .LBB1_2 ; %bb.1: ; %.critedge24.sink.split s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x0 s_load_b32 s6, s[0:1], 0x8 v_lshlrev_b32_e32 v0, 2, v0 s_lshl_b64 s[0:1], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s0, s4, s0 s_addc_u32 s1, s5, s1 v_add_co_u32 v0, s0, s0, v0 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s1, 0, s0 v_mov_b32_e32 v2, s6 flat_store_b32 v[0:1], v2 .LBB1_2: ; %.critedge24 s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat .Lfunc_end1: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 168 ; NumSgprs: 18 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims - .offset: 144 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z7reduce0PiS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z7reduce0PiS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 16 .value_kind: by_value - .offset: 16 .size: 8 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "c8162ff249296ec514785872e181e47080f71afe.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z22__device_stub__reduce0PiS_i # -- Begin function _Z22__device_stub__reduce0PiS_i .p2align 4, 0x90 .type _Z22__device_stub__reduce0PiS_i,@function _Z22__device_stub__reduce0PiS_i: # @_Z22__device_stub__reduce0PiS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7reduce0PiS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z22__device_stub__reduce0PiS_i, .Lfunc_end0-_Z22__device_stub__reduce0PiS_i .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI1_0: .quad 0x3f50000000000000 # double 9.765625E-4 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: # %.noexc6.i.i pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $216, %rsp .cfi_def_cfa_offset 272 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 .cfi_escape 0x2e, 0x00 movl $3757156, %edi # imm = 0x395464 callq _Znwm movq %rax, %rdx xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # %.lr.ph.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i # =>This Inner Loop Header: Depth=1 movl $1, (%rdx,%rax,4) incq %rax cmpq $939289, %rax # imm = 0xE5519 jne .LBB1_1 # %bb.2: # %_ZN6thrust11host_vectorIiSaIiEEC2IiEET_S4_.exit movzbl _ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource(%rip), %eax testb %al, %al je .LBB1_65 .LBB1_3: # %_ZN6thrust16device_allocatorIiEC2Ev.exit.i.i movq $_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, 80(%rsp) xorpd %xmm0, %xmm0 movupd %xmm0, 88(%rsp) movq $0, 104(%rsp) movq %rdx, %rcx addq $3757156, %rcx # imm = 0x395464 .Ltmp0: .cfi_escape 0x2e, 0x00 leaq 80(%rsp), %rdi movl $939289, %esi # imm = 0xE5519 movq %rdx, 152(%rsp) # 8-byte Spill movq %rdi, %r8 callq _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorIPKiEEEEvmT_SA_RNS0_18contiguous_storageIiS3_EE .Ltmp1: # %bb.4: # %_ZN6thrust13device_vectorIiNS_16device_allocatorIiEEEC2IiSaIiEEERKNS_6detail11vector_baseIT_T0_EE.exit movq $939289, 104(%rsp) # imm = 0xE5519 .Ltmp3: .cfi_escape 0x2e, 0x00 leaq 184(%rsp), %rdi movl $918, %esi # imm = 0x396 callq _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em .Ltmp4: # %bb.5: # %_ZN6thrust13device_vectorIiNS_16device_allocatorIiEEEC2Em.exit movq 192(%rsp), %rax movq %rax, 168(%rsp) # 8-byte Spill movq 88(%rsp), %rax movq %rax, 160(%rsp) # 8-byte Spill .Ltmp6: .cfi_escape 0x2e, 0x00 leaq 176(%rsp), %rdi callq hipEventCreate .Ltmp7: # %bb.6: testl %eax, %eax jne .LBB1_67 # %bb.7: .Ltmp11: .cfi_escape 0x2e, 0x00 leaq 112(%rsp), %rdi callq hipEventCreate .Ltmp12: # %bb.8: testl %eax, %eax jne .LBB1_69 # %bb.9: movq 176(%rsp), %rdi .Ltmp15: .cfi_escape 0x2e, 0x00 xorl %esi, %esi callq hipEventRecord .Ltmp16: # %bb.10: testl %eax, %eax jne .LBB1_71 # %bb.11: # %.preheader movl $939289, %r12d # imm = 0xE5519 movl $918, %eax # imm = 0x396 movb $1, %bpl movabsq $4294967296, %r15 # imm = 0x100000000 movabsq $4294968320, %r14 # imm = 0x100000400 .p2align 4, 0x90 .LBB1_12: # =>This Inner Loop Header: Depth=1 movl %eax, %ebx movl %eax, %edi orq %r15, %rdi testb %bpl, %bpl je .LBB1_16 # %bb.13: # in Loop: Header=BB1_12 Depth=1 .Ltmp19: .cfi_escape 0x2e, 0x00 movl $4096, %r8d # imm = 0x1000 movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration .Ltmp20: # %bb.14: # in Loop: Header=BB1_12 Depth=1 testl %eax, %eax jne .LBB1_22 # %bb.20: # in Loop: Header=BB1_12 Depth=1 movq 160(%rsp), %rax # 8-byte Reload movq %rax, 144(%rsp) movq 168(%rsp), %rax # 8-byte Reload movq %rax, 136(%rsp) movl %r12d, 12(%rsp) leaq 144(%rsp), %rax movq %rax, 48(%rsp) leaq 136(%rsp), %rax movq %rax, 56(%rsp) leaq 12(%rsp), %rax movq %rax, 64(%rsp) .Ltmp21: .cfi_escape 0x2e, 0x00 leaq 16(%rsp), %rdi leaq 32(%rsp), %rsi leaq 128(%rsp), %rdx leaq 120(%rsp), %rcx callq __hipPopCallConfiguration .Ltmp22: # %bb.21: # %.noexc # in Loop: Header=BB1_12 Depth=1 movq 16(%rsp), %rsi movl 24(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d .Ltmp23: .cfi_escape 0x2e, 0x10 movl $_Z7reduce0PiS_i, %edi leaq 48(%rsp), %r9 pushq 120(%rsp) .cfi_adjust_cfa_offset 8 pushq 136(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .Ltmp24: .LBB1_22: # %_Z22__device_stub__reduce0PiS_i.exit # in Loop: Header=BB1_12 Depth=1 xorl %r13d, %r13d jmp .LBB1_23 .p2align 4, 0x90 .LBB1_16: # in Loop: Header=BB1_12 Depth=1 .Ltmp25: .cfi_escape 0x2e, 0x00 movl $4096, %r8d # imm = 0x1000 movl $1, %esi movq %r14, %rdx movl $1, %ecx xorl %r9d, %r9d callq __hipPushCallConfiguration .Ltmp26: # %bb.17: # in Loop: Header=BB1_12 Depth=1 movb $1, %r13b testl %eax, %eax jne .LBB1_23 # %bb.18: # in Loop: Header=BB1_12 Depth=1 movq 168(%rsp), %rax # 8-byte Reload movq %rax, 144(%rsp) movq 160(%rsp), %rax # 8-byte Reload movq %rax, 136(%rsp) movl %r12d, 12(%rsp) leaq 144(%rsp), %rax movq %rax, 48(%rsp) leaq 136(%rsp), %rax movq %rax, 56(%rsp) leaq 12(%rsp), %rax movq %rax, 64(%rsp) .Ltmp27: .cfi_escape 0x2e, 0x00 leaq 16(%rsp), %rdi leaq 32(%rsp), %rsi leaq 128(%rsp), %rdx leaq 120(%rsp), %rcx callq __hipPopCallConfiguration .Ltmp28: # %bb.19: # %.noexc91 # in Loop: Header=BB1_12 Depth=1 movq 16(%rsp), %rsi movl 24(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d .Ltmp29: .cfi_escape 0x2e, 0x10 movl $_Z7reduce0PiS_i, %edi leaq 48(%rsp), %r9 pushq 120(%rsp) .cfi_adjust_cfa_offset 8 pushq 136(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .Ltmp30: .p2align 4, 0x90 .LBB1_23: # in Loop: Header=BB1_12 Depth=1 cmpl $1, %ebx je .LBB1_25 # %bb.24: # in Loop: Header=BB1_12 Depth=1 xorps %xmm0, %xmm0 cvtsi2sd %ebx, %xmm0 mulsd .LCPI1_0(%rip), %xmm0 .cfi_escape 0x2e, 0x00 callq ceil@PLT cvttsd2si %xmm0, %eax movl %r13d, %ebp movl %ebx, %r12d jmp .LBB1_12 .LBB1_25: movq 112(%rsp), %rdi .Ltmp32: .cfi_escape 0x2e, 0x00 xorl %esi, %esi callq hipEventRecord .Ltmp33: # %bb.26: testl %eax, %eax jne .LBB1_73 # %bb.27: movq 112(%rsp), %rdi .Ltmp36: .cfi_escape 0x2e, 0x00 callq hipEventSynchronize .Ltmp37: # %bb.28: testl %eax, %eax jne .LBB1_75 # %bb.29: movl $0, 16(%rsp) movq 176(%rsp), %rsi movq 112(%rsp), %rdx .Ltmp41: .cfi_escape 0x2e, 0x00 leaq 16(%rsp), %rdi callq hipEventElapsedTime .Ltmp42: # %bb.30: testl %eax, %eax jne .LBB1_77 # %bb.31: # %.invoke164 testb %bpl, %bpl leaq 56(%rsp), %r12 xorpd %xmm0, %xmm0 movupd %xmm0, 56(%rsp) movq $0, 72(%rsp) leaq 208(%rsp), %rax leaq 192(%rsp), %rbp movq %rbp, %rcx leaq 88(%rsp), %r13 cmoveq %r13, %rcx movq (%rcx), %rsi leaq 104(%rsp), %rcx cmovneq %rax, %rcx movq (%rcx), %rax leaq (%rsi,%rax,4), %rdx .Ltmp46: .cfi_escape 0x2e, 0x00 leaq 48(%rsp), %rdi callq _ZN6thrust6detail11vector_baseIiSaIiEE12range_assignINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvT_SA_NS_27random_access_traversal_tagE .Ltmp47: # %bb.32: # %_ZN6thrust11host_vectorIiSaIiEEaSIiNS_16device_allocatorIiEEEERS2_RKNS_6detail11vector_baseIT_T0_EE.exit movq 88(%rsp), %rcx movq 104(%rsp), %rbx leaq (%rcx,%rbx,4), %rdx .Ltmp48: .cfi_escape 0x2e, 0x00 leaq 32(%rsp), %rdi movq %rdx, %rsi callq _ZN6thrust6detail8dispatch15overlapped_copyINS_11hip_rocprim3tagENS0_15normal_iteratorINS_10device_ptrIiEEEES8_EET1_RNS_16execution_policyIT_EET0_SE_S9_ .Ltmp49: # %bb.33: # %_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE5clearEv.exit subq %rbx, 104(%rsp) .Ltmp50: .cfi_escape 0x2e, 0x00 leaq 80(%rsp), %rdi callq _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE13shrink_to_fitEv .Ltmp51: # %bb.34: movq 192(%rsp), %rcx movq 208(%rsp), %rbx leaq (%rcx,%rbx,4), %rdx .Ltmp52: .cfi_escape 0x2e, 0x00 leaq 32(%rsp), %rdi movq %rdx, %rsi callq _ZN6thrust6detail8dispatch15overlapped_copyINS_11hip_rocprim3tagENS0_15normal_iteratorINS_10device_ptrIiEEEES8_EET1_RNS_16execution_policyIT_EET0_SE_S9_ .Ltmp53: # %bb.35: # %_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE5clearEv.exit101 subq %rbx, 208(%rsp) .Ltmp54: .cfi_escape 0x2e, 0x00 leaq 184(%rsp), %rdi callq _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE13shrink_to_fitEv .Ltmp55: # %bb.36: .Ltmp56: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.6, %esi movl $7, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp57: # %bb.37: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq 56(%rsp), %rax movl (%rax), %esi .Ltmp58: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi callq _ZNSolsEi .Ltmp59: # %bb.38: movq %rax, %r14 movq (%rax), %rax movq -24(%rax), %rax movq 240(%r14,%rax), %r15 testq %r15, %r15 je .LBB1_63 # %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r15) je .LBB1_41 # %bb.40: movzbl 67(%r15), %eax jmp .LBB1_43 .LBB1_41: .Ltmp60: .cfi_escape 0x2e, 0x00 movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv .Ltmp61: # %bb.42: # %.noexc122 movq (%r15), %rax .Ltmp62: .cfi_escape 0x2e, 0x00 movq %r15, %rdi movl $10, %esi callq *48(%rax) .Ltmp63: .LBB1_43: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i .Ltmp64: .cfi_escape 0x2e, 0x00 movsbl %al, %esi movq %r14, %rdi callq _ZNSo3putEc .Ltmp65: # %bb.44: # %.noexc124 .Ltmp66: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq _ZNSo5flushEv .Ltmp67: # %bb.45: # %_ZNSolsEPFRSoS_E.exit .Ltmp68: movq %rax, %r14 .cfi_escape 0x2e, 0x00 movl $.L.str.7, %esi movl $9, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp69: # %bb.46: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit105 movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp70: .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp71: # %bb.47: # %_ZNSolsEf.exit movq %rax, %r14 movq (%rax), %rax movq -24(%rax), %rax movq 240(%r14,%rax), %r15 testq %r15, %r15 je .LBB1_63 # %bb.48: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i127 cmpb $0, 56(%r15) je .LBB1_50 # %bb.49: movzbl 67(%r15), %eax jmp .LBB1_52 .LBB1_50: .Ltmp72: .cfi_escape 0x2e, 0x00 movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv .Ltmp73: # %bb.51: # %.noexc132 movq (%r15), %rax .Ltmp74: .cfi_escape 0x2e, 0x00 movq %r15, %rdi movl $10, %esi callq *48(%rax) .Ltmp75: .LBB1_52: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i129 .Ltmp76: .cfi_escape 0x2e, 0x00 movsbl %al, %esi movq %r14, %rdi callq _ZNSo3putEc .Ltmp77: # %bb.53: # %.noexc134 .Ltmp78: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq _ZNSo5flushEv .Ltmp79: # %bb.54: # %_ZNSolsEPFRSoS_E.exit108 cmpq $0, 64(%rsp) je .LBB1_56 # %bb.55: movq 56(%rsp), %rdi .cfi_escape 0x2e, 0x00 callq _ZdlPv xorps %xmm0, %xmm0 movups %xmm0, (%r12) .LBB1_56: # %_ZN6thrust6detail11vector_baseIiSaIiEED2Ev.exit110 movq 200(%rsp), %rdx testq %rdx, %rdx je .LBB1_59 # %bb.57: movq 184(%rsp), %rax movq 192(%rsp), %rsi shlq $2, %rdx movq 8(%rax), %rdi .Ltmp80: .cfi_escape 0x2e, 0x00 movl $4, %ecx callq _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm .Ltmp81: # %bb.58: # %.noexc.i.i xorps %xmm0, %xmm0 movups %xmm0, (%rbp) .LBB1_59: # %_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev.exit movq 96(%rsp), %rdx testq %rdx, %rdx je .LBB1_62 # %bb.60: movq 80(%rsp), %rax movq 88(%rsp), %rsi shlq $2, %rdx movq 8(%rax), %rdi .Ltmp83: .cfi_escape 0x2e, 0x00 movl $4, %ecx callq _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm .Ltmp84: # %bb.61: # %.noexc.i.i114 xorps %xmm0, %xmm0 movups %xmm0, (%r13) .LBB1_62: # %_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev.exit115 .cfi_escape 0x2e, 0x00 movq 152(%rsp), %rdi # 8-byte Reload callq _ZdlPv xorl %eax, %eax addq $216, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_63: # %.invoke .cfi_def_cfa_offset 272 .Ltmp86: .cfi_escape 0x2e, 0x00 callq _ZSt16__throw_bad_castv .Ltmp87: # %bb.64: # %.cont .LBB1_65: .cfi_escape 0x2e, 0x00 movl $_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi movq %rdx, %rbx callq __cxa_guard_acquire movq %rbx, %rdx testl %eax, %eax je .LBB1_3 # %bb.66: movq $_ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE+16, _ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource(%rip) movq $_ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource, _ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource+8(%rip) .cfi_escape 0x2e, 0x00 movl $_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi callq __cxa_guard_release movq %rbx, %rdx jmp .LBB1_3 .LBB1_67: movq stderr(%rip), %r14 .Ltmp8: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp9: # %bb.68: .cfi_escape 0x2e, 0x00 movl $.L.str, %esi jmp .LBB1_79 .LBB1_69: movq stderr(%rip), %r14 .Ltmp13: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp14: # %bb.70: .cfi_escape 0x2e, 0x00 movl $.L.str.1, %esi jmp .LBB1_79 .LBB1_71: movq stderr(%rip), %r14 .Ltmp17: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp18: # %bb.72: .cfi_escape 0x2e, 0x00 movl $.L.str.2, %esi jmp .LBB1_79 .LBB1_73: movq stderr(%rip), %r14 .Ltmp34: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp35: # %bb.74: .cfi_escape 0x2e, 0x00 movl $.L.str.3, %esi jmp .LBB1_79 .LBB1_75: movq stderr(%rip), %r14 .Ltmp38: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp39: # %bb.76: .cfi_escape 0x2e, 0x00 movl $.L.str.4, %esi jmp .LBB1_79 .LBB1_77: movq stderr(%rip), %r14 .Ltmp43: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp44: # %bb.78: .cfi_escape 0x2e, 0x00 movl $.L.str.5, %esi .LBB1_79: movq %r14, %rdi movq %rax, %rdx xorl %eax, %eax callq fprintf .cfi_escape 0x2e, 0x00 movl $1, %edi callq exit .LBB1_80: .Ltmp85: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq __clang_call_terminate .LBB1_81: .Ltmp82: .cfi_escape 0x2e, 0x00 movq %rax, %rdi callq __clang_call_terminate .LBB1_82: .Ltmp5: movq %rax, %r14 jmp .LBB1_92 .LBB1_83: # %.body .Ltmp2: movq %rax, %r14 .cfi_escape 0x2e, 0x00 leaq 80(%rsp), %rdi callq _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev jmp .LBB1_93 .LBB1_84: .Ltmp45: jmp .LBB1_90 .LBB1_85: .Ltmp10: jmp .LBB1_90 .LBB1_86: # %.loopexit.split-lp .Ltmp40: jmp .LBB1_90 .LBB1_87: .Ltmp88: movq %rax, %r14 cmpq $0, 64(%rsp) je .LBB1_91 # %bb.88: movq 56(%rsp), %rdi .cfi_escape 0x2e, 0x00 callq _ZdlPv xorpd %xmm0, %xmm0 movupd %xmm0, (%r12) jmp .LBB1_91 .LBB1_89: # %.loopexit .Ltmp31: .LBB1_90: movq %rax, %r14 .LBB1_91: .cfi_escape 0x2e, 0x00 leaq 184(%rsp), %rdi callq _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev .LBB1_92: .cfi_escape 0x2e, 0x00 leaq 80(%rsp), %rdi callq _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev .LBB1_93: # %_ZN6thrust6detail11vector_baseIiSaIiEED2Ev.exit119 .cfi_escape 0x2e, 0x00 movq 152(%rsp), %rdi # 8-byte Reload callq _ZdlPv .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table1: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase0-.Lttbaseref0 .Lttbaseref0: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1 .uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2 .byte 0 # On action: cleanup .uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4 .uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5 .byte 0 # On action: cleanup .uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7 .uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10 .byte 0 # On action: cleanup .uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp16-.Ltmp11 # Call between .Ltmp11 and .Ltmp16 .uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40 .byte 0 # On action: cleanup .uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Ltmp30-.Ltmp19 # Call between .Ltmp19 and .Ltmp30 .uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31 .byte 0 # On action: cleanup .uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 7 << .uleb128 .Ltmp32-.Ltmp30 # Call between .Ltmp30 and .Ltmp32 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp32-.Lfunc_begin0 # >> Call Site 8 << .uleb128 .Ltmp37-.Ltmp32 # Call between .Ltmp32 and .Ltmp37 .uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40 .byte 0 # On action: cleanup .uleb128 .Ltmp41-.Lfunc_begin0 # >> Call Site 9 << .uleb128 .Ltmp42-.Ltmp41 # Call between .Ltmp41 and .Ltmp42 .uleb128 .Ltmp45-.Lfunc_begin0 # jumps to .Ltmp45 .byte 0 # On action: cleanup .uleb128 .Ltmp46-.Lfunc_begin0 # >> Call Site 10 << .uleb128 .Ltmp79-.Ltmp46 # Call between .Ltmp46 and .Ltmp79 .uleb128 .Ltmp88-.Lfunc_begin0 # jumps to .Ltmp88 .byte 0 # On action: cleanup .uleb128 .Ltmp80-.Lfunc_begin0 # >> Call Site 11 << .uleb128 .Ltmp81-.Ltmp80 # Call between .Ltmp80 and .Ltmp81 .uleb128 .Ltmp82-.Lfunc_begin0 # jumps to .Ltmp82 .byte 1 # On action: 1 .uleb128 .Ltmp83-.Lfunc_begin0 # >> Call Site 12 << .uleb128 .Ltmp84-.Ltmp83 # Call between .Ltmp83 and .Ltmp84 .uleb128 .Ltmp85-.Lfunc_begin0 # jumps to .Ltmp85 .byte 1 # On action: 1 .uleb128 .Ltmp86-.Lfunc_begin0 # >> Call Site 13 << .uleb128 .Ltmp87-.Ltmp86 # Call between .Ltmp86 and .Ltmp87 .uleb128 .Ltmp88-.Lfunc_begin0 # jumps to .Ltmp88 .byte 0 # On action: cleanup .uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 14 << .uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9 .uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10 .byte 0 # On action: cleanup .uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 15 << .uleb128 .Ltmp39-.Ltmp13 # Call between .Ltmp13 and .Ltmp39 .uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40 .byte 0 # On action: cleanup .uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 16 << .uleb128 .Ltmp44-.Ltmp43 # Call between .Ltmp43 and .Ltmp44 .uleb128 .Ltmp45-.Lfunc_begin0 # jumps to .Ltmp45 .byte 0 # On action: cleanup .uleb128 .Ltmp44-.Lfunc_begin0 # >> Call Site 17 << .uleb128 .Lfunc_end1-.Ltmp44 # Call between .Ltmp44 and .Lfunc_end1 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase0: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE13shrink_to_fitEv,"axG",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE13shrink_to_fitEv,comdat .weak _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE13shrink_to_fitEv # -- Begin function _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE13shrink_to_fitEv .p2align 4, 0x90 .type _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE13shrink_to_fitEv,@function _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE13shrink_to_fitEv: # @_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE13shrink_to_fitEv .Lfunc_begin1: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception1 # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $40, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rdi, %rbx movq (%rdi), %rax movq %rax, 8(%rsp) xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movq $0, 32(%rsp) movq 8(%rdi), %rdx movq 24(%rdi), %r14 leaq (%rdx,%r14,4), %rcx .Ltmp89: leaq 8(%rsp), %rdi movq %r14, %rsi movq %rdi, %r8 callq _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SB_RNS0_18contiguous_storageIiS3_EE .Ltmp90: # %bb.1: # %_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2ERKS4_.exit movq %r14, 32(%rsp) movq 16(%rsp), %rax movq 8(%rbx), %rcx movq %rcx, 16(%rsp) movq %rax, 8(%rbx) movq 24(%rsp), %rax movq 16(%rbx), %rdx movq %rdx, 24(%rsp) movq %rax, 16(%rbx) movq 8(%rsp), %rax movq (%rbx), %rcx movq %rcx, 8(%rsp) movq %rax, (%rbx) movq 24(%rbx), %rax movq %rax, 32(%rsp) movq %r14, 24(%rbx) testq %rdx, %rdx je .LBB2_4 # %bb.2: movq 8(%rsp), %rax movq 16(%rsp), %rsi shlq $2, %rdx movq 8(%rax), %rdi .Ltmp92: movl $4, %ecx callq _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm .Ltmp93: # %bb.3: # %.noexc.i.i leaq 16(%rsp), %rax xorps %xmm0, %xmm0 movups %xmm0, (%rax) .LBB2_4: # %_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev.exit addq $40, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB2_6: .cfi_def_cfa_offset 64 .Ltmp94: movq %rax, %rdi callq __clang_call_terminate .LBB2_5: .Ltmp91: movq %rax, %rbx leaq 8(%rsp), %rdi callq _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev movq %rbx, %rdi callq _Unwind_Resume@PLT .Lfunc_end2: .size _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE13shrink_to_fitEv, .Lfunc_end2-_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE13shrink_to_fitEv .cfi_endproc .section .gcc_except_table._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE13shrink_to_fitEv,"aG",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE13shrink_to_fitEv,comdat .p2align 2, 0x0 GCC_except_table2: .Lexception1: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase1-.Lttbaseref1 .Lttbaseref1: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end1-.Lcst_begin1 .Lcst_begin1: .uleb128 .Ltmp89-.Lfunc_begin1 # >> Call Site 1 << .uleb128 .Ltmp90-.Ltmp89 # Call between .Ltmp89 and .Ltmp90 .uleb128 .Ltmp91-.Lfunc_begin1 # jumps to .Ltmp91 .byte 0 # On action: cleanup .uleb128 .Ltmp92-.Lfunc_begin1 # >> Call Site 2 << .uleb128 .Ltmp93-.Ltmp92 # Call between .Ltmp92 and .Ltmp93 .uleb128 .Ltmp94-.Lfunc_begin1 # jumps to .Ltmp94 .byte 1 # On action: 1 .uleb128 .Ltmp93-.Lfunc_begin1 # >> Call Site 3 << .uleb128 .Lfunc_end2-.Ltmp93 # Call between .Ltmp93 and .Lfunc_end2 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end1: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase1: .p2align 2, 0x0 # -- End function .section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat .hidden __clang_call_terminate # -- Begin function __clang_call_terminate .weak __clang_call_terminate .p2align 4, 0x90 .type __clang_call_terminate,@function __clang_call_terminate: # @__clang_call_terminate .cfi_startproc # %bb.0: pushq %rax .cfi_def_cfa_offset 16 callq __cxa_begin_catch callq _ZSt9terminatev .Lfunc_end3: .size __clang_call_terminate, .Lfunc_end3-__clang_call_terminate .cfi_endproc # -- End function .section .text._ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev,"axG",@progbits,_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev,comdat .weak _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev # -- Begin function _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev .p2align 4, 0x90 .type _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev,@function _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev: # @_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev .Lfunc_begin2: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception2 # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq 16(%rdi), %rdx testq %rdx, %rdx je .LBB4_3 # %bb.1: movq %rdi, %rbx movq (%rdi), %rax movq 8(%rdi), %rsi shlq $2, %rdx movq 8(%rax), %rdi .Ltmp95: movl $4, %ecx callq _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm .Ltmp96: # %bb.2: # %.noexc addq $8, %rbx xorps %xmm0, %xmm0 movups %xmm0, (%rbx) .LBB4_3: # %_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv.exit popq %rbx .cfi_def_cfa_offset 8 retq .LBB4_4: .cfi_def_cfa_offset 16 .Ltmp97: movq %rax, %rdi callq __clang_call_terminate .Lfunc_end4: .size _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev, .Lfunc_end4-_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev .cfi_endproc .section .gcc_except_table._ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev,"aG",@progbits,_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev,comdat .p2align 2, 0x0 GCC_except_table4: .Lexception2: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase2-.Lttbaseref2 .Lttbaseref2: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end2-.Lcst_begin2 .Lcst_begin2: .uleb128 .Ltmp95-.Lfunc_begin2 # >> Call Site 1 << .uleb128 .Ltmp96-.Ltmp95 # Call between .Ltmp95 and .Ltmp96 .uleb128 .Ltmp97-.Lfunc_begin2 # jumps to .Ltmp97 .byte 1 # On action: 1 .Lcst_end2: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase2: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev,"axG",@progbits,_ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev,comdat .weak _ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev # -- Begin function _ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev .p2align 4, 0x90 .type _ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev,@function _ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev: # @_ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev .cfi_startproc # %bb.0: retq .Lfunc_end5: .size _ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev, .Lfunc_end5-_ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev .cfi_endproc # -- End function .section .text._ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev,"axG",@progbits,_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev,comdat .weak _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev # -- Begin function _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev .p2align 4, 0x90 .type _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev,@function _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev: # @_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev .cfi_startproc # %bb.0: jmp _ZdlPv # TAILCALL .Lfunc_end6: .size _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev, .Lfunc_end6-_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev .cfi_endproc # -- End function .section .text._ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm,"axG",@progbits,_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm,comdat .weak _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm # -- Begin function _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm .p2align 4, 0x90 .type _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm,@function _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm: # @_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm .cfi_startproc # %bb.0: movq 8(%rdi), %rdi jmp _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm # TAILCALL .Lfunc_end7: .size _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm, .Lfunc_end7-_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm .cfi_endproc # -- End function .section .text._ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm,"axG",@progbits,_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm,comdat .weak _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm # -- Begin function _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm .p2align 4, 0x90 .type _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm,@function _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm: # @_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm .cfi_startproc # %bb.0: movq 8(%rdi), %rdi jmp _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm # TAILCALL .Lfunc_end8: .size _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm, .Lfunc_end8-_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm .cfi_endproc # -- End function .section .text._ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_,"axG",@progbits,_ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_,comdat .weak _ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_ # -- Begin function _ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_ .p2align 4, 0x90 .type _ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_,@function _ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_: # @_ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_ .cfi_startproc # %bb.0: cmpq %rsi, %rdi sete %al retq .Lfunc_end9: .size _ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_, .Lfunc_end9-_ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_ .cfi_endproc # -- End function .section .text._ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev,"axG",@progbits,_ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev,comdat .weak _ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev # -- Begin function _ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev .p2align 4, 0x90 .type _ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev,@function _ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev: # @_ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev .cfi_startproc # %bb.0: retq .Lfunc_end10: .size _ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev, .Lfunc_end10-_ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev .cfi_endproc # -- End function .section .text._ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev,"axG",@progbits,_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev,comdat .weak _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev # -- Begin function _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev .p2align 4, 0x90 .type _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev,@function _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev: # @_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev .cfi_startproc # %bb.0: jmp _ZdlPv # TAILCALL .Lfunc_end11: .size _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev, .Lfunc_end11-_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev .cfi_endproc # -- End function .section .text._ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm,"axG",@progbits,_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm,comdat .weak _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm # -- Begin function _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm .p2align 4, 0x90 .type _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm,@function _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm: # @_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm .Lfunc_begin3: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception3 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $80, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 leaq 8(%rsp), %rdi callq hipMalloc testl %eax, %eax jne .LBB12_1 # %bb.15: movq 8(%rsp), %rax addq $80, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB12_1: .cfi_def_cfa_offset 112 movl %eax, %ebp callq hipGetLastError movl $40, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp98: callq _ZN6thrust6system12hip_categoryEv .Ltmp99: # %bb.2: movq (%rax), %rcx .Ltmp100: leaq 16(%rsp), %rdi movq %rax, %rsi movl %ebp, %edx callq *48(%rcx) .Ltmp101: # %bb.3: movq 16(%rsp), %rsi .Ltmp103: leaq 48(%rsp), %rdi leaq 7(%rsp), %rdx callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .Ltmp104: # %bb.4: movb $1, %bpl .Ltmp106: leaq 48(%rsp), %rsi movq %rbx, %rdi callq _ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .Ltmp107: # %bb.5: xorl %ebp, %ebp .Ltmp108: movl $_ZTIN6thrust6system6detail9bad_allocE, %esi movl $_ZN6thrust6system6detail9bad_allocD2Ev, %edx movq %rbx, %rdi callq __cxa_throw .Ltmp109: # %bb.16: .LBB12_8: .Ltmp110: movq %rax, %r14 movq 48(%rsp), %rdi leaq 64(%rsp), %rax cmpq %rax, %rdi je .LBB12_10 # %bb.9: # %.critedge.i.i callq _ZdlPv jmp .LBB12_10 .LBB12_7: .Ltmp105: movq %rax, %r14 movb $1, %bpl .LBB12_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit movq 16(%rsp), %rdi leaq 32(%rsp), %rax cmpq %rax, %rdi jne .LBB12_11 # %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit15 testb %bpl, %bpl jne .LBB12_13 .LBB12_14: movq %r14, %rdi callq _Unwind_Resume@PLT .LBB12_11: # %.critedge.i.i13 callq _ZdlPv testb %bpl, %bpl je .LBB12_14 jmp .LBB12_13 .LBB12_6: .Ltmp102: movq %rax, %r14 movb $1, %bpl testb %bpl, %bpl je .LBB12_14 .LBB12_13: movq %rbx, %rdi callq __cxa_free_exception movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end12: .size _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm, .Lfunc_end12-_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm .cfi_endproc .section .gcc_except_table._ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm,"aG",@progbits,_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm,comdat .p2align 2, 0x0 GCC_except_table12: .Lexception3: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end3-.Lcst_begin3 .Lcst_begin3: .uleb128 .Lfunc_begin3-.Lfunc_begin3 # >> Call Site 1 << .uleb128 .Ltmp98-.Lfunc_begin3 # Call between .Lfunc_begin3 and .Ltmp98 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp98-.Lfunc_begin3 # >> Call Site 2 << .uleb128 .Ltmp101-.Ltmp98 # Call between .Ltmp98 and .Ltmp101 .uleb128 .Ltmp102-.Lfunc_begin3 # jumps to .Ltmp102 .byte 0 # On action: cleanup .uleb128 .Ltmp103-.Lfunc_begin3 # >> Call Site 3 << .uleb128 .Ltmp104-.Ltmp103 # Call between .Ltmp103 and .Ltmp104 .uleb128 .Ltmp105-.Lfunc_begin3 # jumps to .Ltmp105 .byte 0 # On action: cleanup .uleb128 .Ltmp106-.Lfunc_begin3 # >> Call Site 4 << .uleb128 .Ltmp109-.Ltmp106 # Call between .Ltmp106 and .Ltmp109 .uleb128 .Ltmp110-.Lfunc_begin3 # jumps to .Ltmp110 .byte 0 # On action: cleanup .uleb128 .Ltmp109-.Lfunc_begin3 # >> Call Site 5 << .uleb128 .Lfunc_end12-.Ltmp109 # Call between .Ltmp109 and .Lfunc_end12 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end3: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm,"axG",@progbits,_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm,comdat .weak _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm # -- Begin function _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm .p2align 4, 0x90 .type _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm,@function _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm: # @_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm .Lfunc_begin4: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception4 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movq %rsi, %rdi callq hipFree testl %eax, %eax jne .LBB13_1 # %bb.5: popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB13_1: .cfi_def_cfa_offset 32 movl %eax, %ebp callq hipGetLastError movl $64, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp111: callq _ZN6thrust6system12hip_categoryEv .Ltmp112: # %bb.2: .Ltmp113: movl $.L.str.18, %ecx movq %rbx, %rdi movl %ebp, %esi movq %rax, %rdx callq _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc .Ltmp114: # %bb.3: movl $_ZTIN6thrust6system12system_errorE, %esi movl $_ZN6thrust6system12system_errorD2Ev, %edx movq %rbx, %rdi callq __cxa_throw .LBB13_4: .Ltmp115: movq %rax, %r14 movq %rbx, %rdi callq __cxa_free_exception movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end13: .size _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm, .Lfunc_end13-_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm .cfi_endproc .section .gcc_except_table._ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm,"aG",@progbits,_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm,comdat .p2align 2, 0x0 GCC_except_table13: .Lexception4: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end4-.Lcst_begin4 .Lcst_begin4: .uleb128 .Lfunc_begin4-.Lfunc_begin4 # >> Call Site 1 << .uleb128 .Ltmp111-.Lfunc_begin4 # Call between .Lfunc_begin4 and .Ltmp111 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp111-.Lfunc_begin4 # >> Call Site 2 << .uleb128 .Ltmp114-.Ltmp111 # Call between .Ltmp111 and .Ltmp114 .uleb128 .Ltmp115-.Lfunc_begin4 # jumps to .Ltmp115 .byte 0 # On action: cleanup .uleb128 .Ltmp114-.Lfunc_begin4 # >> Call Site 3 << .uleb128 .Lfunc_end13-.Ltmp114 # Call between .Ltmp114 and .Lfunc_end13 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end4: .p2align 2, 0x0 # -- End function .section .text._ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_,"axG",@progbits,_ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_,comdat .weak _ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_ # -- Begin function _ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_ .p2align 4, 0x90 .type _ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_,@function _ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_: # @_ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_ .cfi_startproc # %bb.0: cmpq %rsi, %rdi sete %al retq .Lfunc_end14: .size _ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_, .Lfunc_end14-_ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_ .cfi_endproc # -- End function .section .text._ZN6thrust6system12hip_categoryEv,"axG",@progbits,_ZN6thrust6system12hip_categoryEv,comdat .weak _ZN6thrust6system12hip_categoryEv # -- Begin function _ZN6thrust6system12hip_categoryEv .p2align 4, 0x90 .type _ZN6thrust6system12hip_categoryEv,@function _ZN6thrust6system12hip_categoryEv: # @_ZN6thrust6system12hip_categoryEv .cfi_startproc # %bb.0: movzbl _ZGVZN6thrust6system12hip_categoryEvE6result(%rip), %eax testb %al, %al je .LBB15_1 # %bb.4: movl $_ZZN6thrust6system12hip_categoryEvE6result, %eax retq .LBB15_1: pushq %rax .cfi_def_cfa_offset 16 movl $_ZGVZN6thrust6system12hip_categoryEvE6result, %edi callq __cxa_guard_acquire testl %eax, %eax je .LBB15_3 # %bb.2: movq $_ZTVN6thrust6system11hip_rocprim6detail18hip_error_categoryE+16, _ZZN6thrust6system12hip_categoryEvE6result(%rip) movl $_ZN6thrust6system14error_categoryD2Ev, %edi movl $_ZZN6thrust6system12hip_categoryEvE6result, %esi movl $__dso_handle, %edx callq __cxa_atexit movl $_ZGVZN6thrust6system12hip_categoryEvE6result, %edi callq __cxa_guard_release .LBB15_3: addq $8, %rsp .cfi_def_cfa_offset 8 movl $_ZZN6thrust6system12hip_categoryEvE6result, %eax retq .Lfunc_end15: .size _ZN6thrust6system12hip_categoryEv, .Lfunc_end15-_ZN6thrust6system12hip_categoryEv .cfi_endproc # -- End function .section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,comdat .weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .p2align 4, 0x90 .type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,@function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 16(%rdi), %rax movq %rax, (%rdi) testq %rsi, %rsi je .LBB16_10 # %bb.1: movq %rsi, %r14 movq %rdi, %rbx movq %rsi, %rdi callq strlen movq %rax, %r15 cmpq $16, %rax jb .LBB16_5 # %bb.2: testq %r15, %r15 js .LBB16_11 # %bb.3: movq %r15, %rdi incq %rdi js .LBB16_12 # %bb.4: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i callq _Znwm movq %rax, (%rbx) movq %r15, 16(%rbx) .LBB16_5: testq %r15, %r15 je .LBB16_9 # %bb.6: movq (%rbx), %rdi cmpq $1, %r15 jne .LBB16_8 # %bb.7: movzbl (%r14), %eax movb %al, (%rdi) jmp .LBB16_9 .LBB16_8: movq %r14, %rsi movq %r15, %rdx callq memcpy@PLT .LBB16_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag.exit movq %r15, 8(%rbx) movq (%rbx), %rax movb $0, (%rax,%r15) popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB16_12: # %.noexc11 .cfi_def_cfa_offset 32 callq _ZSt17__throw_bad_allocv .LBB16_10: movl $.L.str.16, %edi callq _ZSt19__throw_logic_errorPKc .LBB16_11: # %.noexc movl $.L.str.11, %edi callq _ZSt20__throw_length_errorPKc .Lfunc_end16: .size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .Lfunc_end16-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .cfi_endproc # -- End function .section .text._ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat .weak _ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .p2align 4, 0x90 .type _ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function _ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .Lfunc_begin5: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception5 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 pushq %rax .cfi_def_cfa_offset 64 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %r15 movq %rdi, %rbx movq $_ZTVN6thrust6system6detail9bad_allocE+16, (%rdi) leaq 8(%rdi), %r14 leaq 24(%rdi), %rbp movq %rbp, 8(%rdi) movq $0, 16(%rdi) movb $0, 24(%rdi) callq _ZNKSt9bad_alloc4whatEv movq %rax, %r12 movq 16(%rbx), %r13 movq %rax, %rdi callq strlen .Ltmp116: movq %r14, %rdi xorl %esi, %esi movq %r13, %rdx movq %r12, %rcx movq %rax, %r8 callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm .Ltmp117: # %bb.1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEPKc.exit movq 16(%rbx), %rsi movq %rsi, %rax shrq %rax movabsq $4611686018427387903, %rcx # imm = 0x3FFFFFFFFFFFFFFF cmpq %rcx, %rax je .LBB17_8 # %bb.2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i leaq 2(%rsi), %r12 movq (%r14), %rax movl $15, %ecx cmpq %rbp, %rax je .LBB17_4 # %bb.3: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i movq (%rbp), %rcx .LBB17_4: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i cmpq %rcx, %r12 jbe .LBB17_5 # %bb.6: .Ltmp118: movl $.L.str.14, %ecx movl $2, %r8d movq %r14, %rdi xorl %edx, %edx callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .Ltmp119: jmp .LBB17_7 .LBB17_5: movw $8250, (%rax,%rsi) # imm = 0x203A .LBB17_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLEPKc.exit movabsq $9223372036854775806, %rax # imm = 0x7FFFFFFFFFFFFFFE movq %r12, 16(%rbx) movq 8(%rbx), %rcx movb $0, (%rcx,%r12) movq 8(%r15), %r8 movq 16(%rbx), %rsi subq %rsi, %rax incq %rax cmpq %r8, %rax jb .LBB17_8 # %bb.10: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i leaq (%rsi,%r8), %r12 movq (%r14), %rdi movl $15, %eax cmpq %rbp, %rdi je .LBB17_12 # %bb.11: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i movq (%rbp), %rax .LBB17_12: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i movq (%r15), %rcx cmpq %rax, %r12 jbe .LBB17_13 # %bb.17: .Ltmp120: movq %r14, %rdi xorl %edx, %edx callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .Ltmp121: jmp .LBB17_18 .LBB17_13: testq %r8, %r8 je .LBB17_18 # %bb.14: addq %rsi, %rdi cmpq $1, %r8 jne .LBB17_16 # %bb.15: movzbl (%rcx), %eax movb %al, (%rdi) jmp .LBB17_18 .LBB17_16: movq %rcx, %rsi movq %r8, %rdx callq memcpy@PLT .LBB17_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLERKS4_.exit movq %r12, 16(%rbx) movq 8(%rbx), %rax movb $0, (%rax,%r12) addq $8, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB17_8: # %.invoke .cfi_def_cfa_offset 64 .Ltmp122: movl $.L.str.15, %edi callq _ZSt20__throw_length_errorPKc .Ltmp123: # %bb.9: # %.cont .LBB17_19: .Ltmp124: movq %rax, %r15 movq (%r14), %rdi cmpq %rbp, %rdi je .LBB17_21 # %bb.20: # %.critedge.i.i callq _ZdlPv .LBB17_21: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit movq %rbx, %rdi callq _ZNSt9bad_allocD2Ev movq %r15, %rdi callq _Unwind_Resume@PLT .Lfunc_end17: .size _ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end17-_ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .cfi_endproc .section .gcc_except_table._ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"aG",@progbits,_ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat .p2align 2, 0x0 GCC_except_table17: .Lexception5: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end5-.Lcst_begin5 .Lcst_begin5: .uleb128 .Ltmp116-.Lfunc_begin5 # >> Call Site 1 << .uleb128 .Ltmp121-.Ltmp116 # Call between .Ltmp116 and .Ltmp121 .uleb128 .Ltmp124-.Lfunc_begin5 # jumps to .Ltmp124 .byte 0 # On action: cleanup .uleb128 .Ltmp121-.Lfunc_begin5 # >> Call Site 2 << .uleb128 .Ltmp122-.Ltmp121 # Call between .Ltmp121 and .Ltmp122 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp122-.Lfunc_begin5 # >> Call Site 3 << .uleb128 .Ltmp123-.Ltmp122 # Call between .Ltmp122 and .Ltmp123 .uleb128 .Ltmp124-.Lfunc_begin5 # jumps to .Ltmp124 .byte 0 # On action: cleanup .uleb128 .Ltmp123-.Lfunc_begin5 # >> Call Site 4 << .uleb128 .Lfunc_end17-.Ltmp123 # Call between .Ltmp123 and .Lfunc_end17 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end5: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6system6detail9bad_allocD2Ev,"axG",@progbits,_ZN6thrust6system6detail9bad_allocD2Ev,comdat .weak _ZN6thrust6system6detail9bad_allocD2Ev # -- Begin function _ZN6thrust6system6detail9bad_allocD2Ev .p2align 4, 0x90 .type _ZN6thrust6system6detail9bad_allocD2Ev,@function _ZN6thrust6system6detail9bad_allocD2Ev: # @_ZN6thrust6system6detail9bad_allocD2Ev .cfi_startproc # %bb.0: movq $_ZTVN6thrust6system6detail9bad_allocE+16, (%rdi) movq 8(%rdi), %rax leaq 24(%rdi), %rcx cmpq %rcx, %rax je _ZNSt9bad_allocD2Ev # TAILCALL # %bb.1: # %.critedge.i.i pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq %rdi, %rbx movq %rax, %rdi callq _ZdlPv movq %rbx, %rdi popq %rbx .cfi_def_cfa_offset 8 .cfi_restore %rbx jmp _ZNSt9bad_allocD2Ev # TAILCALL .Lfunc_end18: .size _ZN6thrust6system6detail9bad_allocD2Ev, .Lfunc_end18-_ZN6thrust6system6detail9bad_allocD2Ev .cfi_endproc # -- End function .section .text._ZN6thrust6system14error_categoryD2Ev,"axG",@progbits,_ZN6thrust6system14error_categoryD2Ev,comdat .weak _ZN6thrust6system14error_categoryD2Ev # -- Begin function _ZN6thrust6system14error_categoryD2Ev .p2align 4, 0x90 .type _ZN6thrust6system14error_categoryD2Ev,@function _ZN6thrust6system14error_categoryD2Ev: # @_ZN6thrust6system14error_categoryD2Ev .cfi_startproc # %bb.0: movq $_ZTVN6thrust6system14error_categoryE+16, (%rdi) retq .Lfunc_end19: .size _ZN6thrust6system14error_categoryD2Ev, .Lfunc_end19-_ZN6thrust6system14error_categoryD2Ev .cfi_endproc # -- End function .section .text._ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev,"axG",@progbits,_ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev,comdat .weak _ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev # -- Begin function _ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev .p2align 4, 0x90 .type _ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev,@function _ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev: # @_ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev .cfi_startproc # %bb.0: movq $_ZTVN6thrust6system14error_categoryE+16, (%rdi) jmp _ZdlPv # TAILCALL .Lfunc_end20: .size _ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev, .Lfunc_end20-_ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev .cfi_endproc # -- End function .section .text._ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv,"axG",@progbits,_ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv,comdat .weak _ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv # -- Begin function _ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv .p2align 4, 0x90 .type _ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv,@function _ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv: # @_ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv .cfi_startproc # %bb.0: movl $.L.str.8, %eax retq .Lfunc_end21: .size _ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv, .Lfunc_end21-_ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv .cfi_endproc # -- End function .section .text._ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi,"axG",@progbits,_ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi,comdat .weak _ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi # -- Begin function _ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi .p2align 4, 0x90 .type _ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi,@function _ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi: # @_ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 cmpl $50, %esi jg .LBB22_5 # %bb.1: movzbl _ZGVZN6thrust6system12hip_categoryEvE6result(%rip), %eax testb %al, %al je .LBB22_2 .LBB22_4: # %_ZN6thrust6system20make_error_conditionENS0_11hip_rocprim4errc6errc_tE.exit movl $_ZZN6thrust6system12hip_categoryEvE6result, %edx movl %esi, %eax popq %rbx .cfi_def_cfa_offset 8 retq .LBB22_5: .cfi_def_cfa_offset 16 movzbl _ZGVZN6thrust6system15system_categoryEvE6result(%rip), %eax testb %al, %al je .LBB22_6 .LBB22_8: # %_ZN6thrust6system15system_categoryEv.exit movq _ZZN6thrust6system15system_categoryEvE6result(%rip), %rax movq 24(%rax), %rax movl $_ZZN6thrust6system15system_categoryEvE6result, %edi popq %rbx .cfi_def_cfa_offset 8 jmpq *%rax # TAILCALL .LBB22_2: .cfi_def_cfa_offset 16 movl $_ZGVZN6thrust6system12hip_categoryEvE6result, %edi movl %esi, %ebx callq __cxa_guard_acquire movl %ebx, %esi testl %eax, %eax je .LBB22_4 # %bb.3: movq $_ZTVN6thrust6system11hip_rocprim6detail18hip_error_categoryE+16, _ZZN6thrust6system12hip_categoryEvE6result(%rip) movl $_ZN6thrust6system14error_categoryD2Ev, %edi movl $_ZZN6thrust6system12hip_categoryEvE6result, %esi movl $__dso_handle, %edx callq __cxa_atexit movl $_ZGVZN6thrust6system12hip_categoryEvE6result, %edi callq __cxa_guard_release movl %ebx, %esi jmp .LBB22_4 .LBB22_6: movl $_ZGVZN6thrust6system15system_categoryEvE6result, %edi movl %esi, %ebx callq __cxa_guard_acquire movl %ebx, %esi testl %eax, %eax je .LBB22_8 # %bb.7: movq $_ZTVN6thrust6system6detail21system_error_categoryE+16, _ZZN6thrust6system15system_categoryEvE6result(%rip) movl $_ZN6thrust6system14error_categoryD2Ev, %edi movl $_ZZN6thrust6system15system_categoryEvE6result, %esi movl $__dso_handle, %edx callq __cxa_atexit movl $_ZGVZN6thrust6system15system_categoryEvE6result, %edi callq __cxa_guard_release movl %ebx, %esi jmp .LBB22_8 .Lfunc_end22: .size _ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi, .Lfunc_end22-_ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi .cfi_endproc # -- End function .section .text._ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE,"axG",@progbits,_ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE,comdat .weak _ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE # -- Begin function _ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE .p2align 4, 0x90 .type _ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE,@function _ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE: # @_ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq %rdx, %rbx movq (%rdi), %rax callq *24(%rax) cmpq 8(%rbx), %rdx sete %cl cmpl (%rbx), %eax sete %al andb %cl, %al popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end23: .size _ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE, .Lfunc_end23-_ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE .cfi_endproc # -- End function .section .text._ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi,"axG",@progbits,_ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi,comdat .weak _ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi # -- Begin function _ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi .p2align 4, 0x90 .type _ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi,@function _ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi: # @_ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi .cfi_startproc # %bb.0: cmpq %rdi, 8(%rsi) sete %cl cmpl %edx, (%rsi) sete %al andb %cl, %al retq .Lfunc_end24: .size _ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi, .Lfunc_end24-_ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi .cfi_endproc # -- End function .section .text._ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei,"axG",@progbits,_ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei,comdat .weak _ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei # -- Begin function _ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei .p2align 4, 0x90 .type _ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei,@function _ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei: # @_ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei .Lfunc_begin6: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception6 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $72, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %edx, %ebx movq %rdi, %r14 movl %edx, %edi callq hipGetErrorString movq %rax, %r15 movl %ebx, %edi callq hipGetErrorName testq %rax, %rax movl $.L.str.13, %r13d cmovneq %rax, %r13 leaq 24(%rsp), %rbx movq %rbx, 8(%rsp) movq %r13, %rdi callq strlen movq %rax, %r12 cmpq $16, %rax jb .LBB25_4 # %bb.1: testq %r12, %r12 js .LBB25_42 # %bb.2: movq %r12, %rdi incq %rdi js .LBB25_43 # %bb.3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i callq _Znwm movq %rax, 8(%rsp) movq %r12, 24(%rsp) .LBB25_4: testq %r12, %r12 je .LBB25_8 # %bb.5: movq 8(%rsp), %rdi cmpq $1, %r12 jne .LBB25_7 # %bb.6: movzbl (%r13), %eax movb %al, (%rdi) jmp .LBB25_8 .LBB25_7: movq %r13, %rsi movq %r12, %rdx callq memcpy@PLT .LBB25_8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit movq %r12, 16(%rsp) movq 8(%rsp), %rax movb $0, (%rax,%r12) movq 16(%rsp), %rsi movq %rsi, %rax shrq %rax movabsq $4611686018427387903, %rcx # imm = 0x3FFFFFFFFFFFFFFF cmpq %rcx, %rax je .LBB25_9 # %bb.11: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i leaq 2(%rsi), %r12 movq 8(%rsp), %rax movl $15, %ecx cmpq %rbx, %rax je .LBB25_13 # %bb.12: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i movq 24(%rsp), %rcx .LBB25_13: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i cmpq %rcx, %r12 jbe .LBB25_14 # %bb.15: .Ltmp125: leaq 8(%rsp), %rdi movl $.L.str.14, %ecx movl $2, %r8d xorl %edx, %edx callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .Ltmp126: jmp .LBB25_16 .LBB25_14: movw $8250, (%rax,%rsi) # imm = 0x203A .LBB25_16: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKc.exit.i movabsq $9223372036854775806, %rbx # imm = 0x7FFFFFFFFFFFFFFE movq %r12, 16(%rsp) movq 8(%rsp), %rax movb $0, (%rax,%r12) leaq 56(%rsp), %r12 movq %r12, 40(%rsp) movq 8(%rsp), %rax leaq 24(%rsp), %r13 cmpq %r13, %rax je .LBB25_17 # %bb.18: # %.critedge.i.i movq %rax, 40(%rsp) movq 24(%rsp), %rax movq %rax, 56(%rsp) jmp .LBB25_19 .LBB25_17: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i movq 16(%rsp), %rdx incq %rdx movq %r12, %rdi movq %r13, %rsi callq memcpy@PLT .LBB25_19: # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEOS8_PKS5_.exit movq 16(%rsp), %rbp movq %rbp, 48(%rsp) movq %r13, 8(%rsp) movq $0, 16(%rsp) movb $0, 24(%rsp) testq %r15, %r15 movl $.L.str.12, %r13d cmovneq %r15, %r13 movq %r13, %rdi callq strlen subq %rbp, %rbx incq %rbx cmpq %rax, %rbx jb .LBB25_20 # %bb.22: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i17 leaq (%rax,%rbp), %r15 movq 40(%rsp), %rdi movl $15, %ecx cmpq %r12, %rdi je .LBB25_24 # %bb.23: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i17 movq 56(%rsp), %rcx .LBB25_24: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i17 cmpq %rcx, %r15 leaq 24(%rsp), %rbx jbe .LBB25_25 # %bb.29: .Ltmp127: leaq 40(%rsp), %rdi movq %rbp, %rsi xorl %edx, %edx movq %r13, %rcx movq %rax, %r8 callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .Ltmp128: jmp .LBB25_30 .LBB25_25: testq %rax, %rax je .LBB25_30 # %bb.26: addq %rbp, %rdi cmpq $1, %rax jne .LBB25_28 # %bb.27: movzbl (%r13), %eax movb %al, (%rdi) jmp .LBB25_30 .LBB25_28: movq %r13, %rsi movq %rax, %rdx callq memcpy@PLT .LBB25_30: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKc.exit.i22 movq %r15, 48(%rsp) movq 40(%rsp), %rax movb $0, (%rax,%r15) leaq 16(%r14), %rdi movq %rdi, (%r14) movq 40(%rsp), %rax cmpq %r12, %rax je .LBB25_31 # %bb.32: # %.critedge.i.i23 movq %rax, (%r14) movq 56(%rsp), %rax movq %rax, 16(%r14) jmp .LBB25_33 .LBB25_31: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i24 movq 48(%rsp), %rdx incq %rdx movq %r12, %rsi callq memcpy@PLT .LBB25_33: # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEOS8_PKS5_.exit27 movq 48(%rsp), %rax movq %rax, 8(%r14) movq %r12, 40(%rsp) movq $0, 48(%rsp) movb $0, 56(%rsp) movq 8(%rsp), %rdi cmpq %rbx, %rdi je .LBB25_35 # %bb.34: # %.critedge.i.i30 callq _ZdlPv .LBB25_35: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit32 movq %r14, %rax addq $72, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB25_43: # %.noexc11.i .cfi_def_cfa_offset 128 callq _ZSt17__throw_bad_allocv .LBB25_9: .Ltmp132: movl $.L.str.15, %edi callq _ZSt20__throw_length_errorPKc .Ltmp133: # %bb.10: # %.noexc15 .LBB25_20: .Ltmp129: movl $.L.str.15, %edi callq _ZSt20__throw_length_errorPKc .Ltmp130: # %bb.21: # %.noexc25 .LBB25_42: # %.noexc.i movl $.L.str.11, %edi callq _ZSt20__throw_length_errorPKc .LBB25_37: .Ltmp131: movq %rax, %r14 movq 40(%rsp), %rdi cmpq %r12, %rdi je .LBB25_39 # %bb.38: # %.critedge.i.i33 callq _ZdlPv jmp .LBB25_39 .LBB25_36: .Ltmp134: movq %rax, %r14 .LBB25_39: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit35 movq 8(%rsp), %rdi leaq 24(%rsp), %rax cmpq %rax, %rdi je .LBB25_41 # %bb.40: # %.critedge.i.i36 callq _ZdlPv .LBB25_41: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit38 movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end25: .size _ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei, .Lfunc_end25-_ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei .cfi_endproc .section .gcc_except_table._ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei,"aG",@progbits,_ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei,comdat .p2align 2, 0x0 GCC_except_table25: .Lexception6: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end6-.Lcst_begin6 .Lcst_begin6: .uleb128 .Lfunc_begin6-.Lfunc_begin6 # >> Call Site 1 << .uleb128 .Ltmp125-.Lfunc_begin6 # Call between .Lfunc_begin6 and .Ltmp125 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp125-.Lfunc_begin6 # >> Call Site 2 << .uleb128 .Ltmp126-.Ltmp125 # Call between .Ltmp125 and .Ltmp126 .uleb128 .Ltmp134-.Lfunc_begin6 # jumps to .Ltmp134 .byte 0 # On action: cleanup .uleb128 .Ltmp126-.Lfunc_begin6 # >> Call Site 3 << .uleb128 .Ltmp127-.Ltmp126 # Call between .Ltmp126 and .Ltmp127 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp127-.Lfunc_begin6 # >> Call Site 4 << .uleb128 .Ltmp128-.Ltmp127 # Call between .Ltmp127 and .Ltmp128 .uleb128 .Ltmp131-.Lfunc_begin6 # jumps to .Ltmp131 .byte 0 # On action: cleanup .uleb128 .Ltmp128-.Lfunc_begin6 # >> Call Site 5 << .uleb128 .Ltmp132-.Ltmp128 # Call between .Ltmp128 and .Ltmp132 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp132-.Lfunc_begin6 # >> Call Site 6 << .uleb128 .Ltmp133-.Ltmp132 # Call between .Ltmp132 and .Ltmp133 .uleb128 .Ltmp134-.Lfunc_begin6 # jumps to .Ltmp134 .byte 0 # On action: cleanup .uleb128 .Ltmp129-.Lfunc_begin6 # >> Call Site 7 << .uleb128 .Ltmp130-.Ltmp129 # Call between .Ltmp129 and .Ltmp130 .uleb128 .Ltmp131-.Lfunc_begin6 # jumps to .Ltmp131 .byte 0 # On action: cleanup .uleb128 .Ltmp130-.Lfunc_begin6 # >> Call Site 8 << .uleb128 .Lfunc_end25-.Ltmp130 # Call between .Ltmp130 and .Lfunc_end25 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end6: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6system14error_categoryD0Ev,"axG",@progbits,_ZN6thrust6system14error_categoryD0Ev,comdat .weak _ZN6thrust6system14error_categoryD0Ev # -- Begin function _ZN6thrust6system14error_categoryD0Ev .p2align 4, 0x90 .type _ZN6thrust6system14error_categoryD0Ev,@function _ZN6thrust6system14error_categoryD0Ev: # @_ZN6thrust6system14error_categoryD0Ev .cfi_startproc # %bb.0: ud2 .Lfunc_end26: .size _ZN6thrust6system14error_categoryD0Ev, .Lfunc_end26-_ZN6thrust6system14error_categoryD0Ev .cfi_endproc # -- End function .section .text._ZNK6thrust6system14error_category23default_error_conditionEi,"axG",@progbits,_ZNK6thrust6system14error_category23default_error_conditionEi,comdat .weak _ZNK6thrust6system14error_category23default_error_conditionEi # -- Begin function _ZNK6thrust6system14error_category23default_error_conditionEi .p2align 4, 0x90 .type _ZNK6thrust6system14error_category23default_error_conditionEi,@function _ZNK6thrust6system14error_category23default_error_conditionEi: # @_ZNK6thrust6system14error_category23default_error_conditionEi .cfi_startproc # %bb.0: movl %esi, %eax movq %rdi, %rdx retq .Lfunc_end27: .size _ZNK6thrust6system14error_category23default_error_conditionEi, .Lfunc_end27-_ZNK6thrust6system14error_category23default_error_conditionEi .cfi_endproc # -- End function .section .text._ZN6thrust6system15system_categoryEv,"axG",@progbits,_ZN6thrust6system15system_categoryEv,comdat .weak _ZN6thrust6system15system_categoryEv # -- Begin function _ZN6thrust6system15system_categoryEv .p2align 4, 0x90 .type _ZN6thrust6system15system_categoryEv,@function _ZN6thrust6system15system_categoryEv: # @_ZN6thrust6system15system_categoryEv .cfi_startproc # %bb.0: movzbl _ZGVZN6thrust6system15system_categoryEvE6result(%rip), %eax testb %al, %al je .LBB28_1 # %bb.4: movl $_ZZN6thrust6system15system_categoryEvE6result, %eax retq .LBB28_1: pushq %rax .cfi_def_cfa_offset 16 movl $_ZGVZN6thrust6system15system_categoryEvE6result, %edi callq __cxa_guard_acquire testl %eax, %eax je .LBB28_3 # %bb.2: movq $_ZTVN6thrust6system6detail21system_error_categoryE+16, _ZZN6thrust6system15system_categoryEvE6result(%rip) movl $_ZN6thrust6system14error_categoryD2Ev, %edi movl $_ZZN6thrust6system15system_categoryEvE6result, %esi movl $__dso_handle, %edx callq __cxa_atexit movl $_ZGVZN6thrust6system15system_categoryEvE6result, %edi callq __cxa_guard_release .LBB28_3: addq $8, %rsp .cfi_def_cfa_offset 8 movl $_ZZN6thrust6system15system_categoryEvE6result, %eax retq .Lfunc_end28: .size _ZN6thrust6system15system_categoryEv, .Lfunc_end28-_ZN6thrust6system15system_categoryEv .cfi_endproc # -- End function .section .text._ZN6thrust6system6detail21system_error_categoryD0Ev,"axG",@progbits,_ZN6thrust6system6detail21system_error_categoryD0Ev,comdat .weak _ZN6thrust6system6detail21system_error_categoryD0Ev # -- Begin function _ZN6thrust6system6detail21system_error_categoryD0Ev .p2align 4, 0x90 .type _ZN6thrust6system6detail21system_error_categoryD0Ev,@function _ZN6thrust6system6detail21system_error_categoryD0Ev: # @_ZN6thrust6system6detail21system_error_categoryD0Ev .cfi_startproc # %bb.0: movq $_ZTVN6thrust6system14error_categoryE+16, (%rdi) jmp _ZdlPv # TAILCALL .Lfunc_end29: .size _ZN6thrust6system6detail21system_error_categoryD0Ev, .Lfunc_end29-_ZN6thrust6system6detail21system_error_categoryD0Ev .cfi_endproc # -- End function .section .text._ZNK6thrust6system6detail21system_error_category4nameEv,"axG",@progbits,_ZNK6thrust6system6detail21system_error_category4nameEv,comdat .weak _ZNK6thrust6system6detail21system_error_category4nameEv # -- Begin function _ZNK6thrust6system6detail21system_error_category4nameEv .p2align 4, 0x90 .type _ZNK6thrust6system6detail21system_error_category4nameEv,@function _ZNK6thrust6system6detail21system_error_category4nameEv: # @_ZNK6thrust6system6detail21system_error_category4nameEv .cfi_startproc # %bb.0: movl $.L.str.9, %eax retq .Lfunc_end30: .size _ZNK6thrust6system6detail21system_error_category4nameEv, .Lfunc_end30-_ZNK6thrust6system6detail21system_error_category4nameEv .cfi_endproc # -- End function .section .text._ZNK6thrust6system6detail21system_error_category23default_error_conditionEi,"axG",@progbits,_ZNK6thrust6system6detail21system_error_category23default_error_conditionEi,comdat .weak _ZNK6thrust6system6detail21system_error_category23default_error_conditionEi # -- Begin function _ZNK6thrust6system6detail21system_error_category23default_error_conditionEi .p2align 4, 0x90 .type _ZNK6thrust6system6detail21system_error_category23default_error_conditionEi,@function _ZNK6thrust6system6detail21system_error_category23default_error_conditionEi: # @_ZNK6thrust6system6detail21system_error_category23default_error_conditionEi .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movl %esi, %ebx leal -9901(%rbx), %eax cmpl $78, %eax ja .LBB31_81 # %bb.1: jmpq *.LJTI31_0(,%rax,8) .LBB31_2: movl $9901, %edi # imm = 0x26AD jmp .LBB31_3 .LBB31_77: movl $9979, %edi # imm = 0x26FB jmp .LBB31_3 .LBB31_33: movl $9961, %edi # imm = 0x26E9 jmp .LBB31_3 .LBB31_50: movl $9968, %edi # imm = 0x26F0 jmp .LBB31_3 .LBB31_67: movl $9974, %edi # imm = 0x26F6 jmp .LBB31_3 .LBB31_75: movl $9977, %edi # imm = 0x26F9 jmp .LBB31_3 .LBB31_28: movl $9945, %edi # imm = 0x26D9 jmp .LBB31_3 .LBB31_19: movl $9952, %edi # imm = 0x26E0 jmp .LBB31_3 .LBB31_29: movl $9958, %edi # imm = 0x26E6 jmp .LBB31_3 .LBB31_22: movl $9955, %edi # imm = 0x26E3 jmp .LBB31_3 .LBB31_17: movl $9951, %edi # imm = 0x26DF jmp .LBB31_3 .LBB31_66: movl $9933, %edi # imm = 0x26CD jmp .LBB31_3 .LBB31_80: movl $9941, %edi # imm = 0x26D5 jmp .LBB31_3 .LBB31_59: movl $9928, %edi # imm = 0x26C8 jmp .LBB31_3 .LBB31_79: movl $9940, %edi # imm = 0x26D4 jmp .LBB31_3 .LBB31_74: movl $9938, %edi # imm = 0x26D2 jmp .LBB31_3 .LBB31_58: movl $9927, %edi # imm = 0x26C7 jmp .LBB31_3 .LBB31_45: movl $9921, %edi # imm = 0x26C1 jmp .LBB31_3 .LBB31_68: movl $9975, %edi # imm = 0x26F7 jmp .LBB31_3 .LBB31_7: movl $9946, %edi # imm = 0x26DA jmp .LBB31_3 .LBB31_39: movl $9917, %edi # imm = 0x26BD jmp .LBB31_3 .LBB31_48: movl $9966, %edi # imm = 0x26EE jmp .LBB31_3 .LBB31_71: movl $9934, %edi # imm = 0x26CE jmp .LBB31_3 .LBB31_13: movl $9906, %edi # imm = 0x26B2 jmp .LBB31_3 .LBB31_43: movl $9919, %edi # imm = 0x26BF jmp .LBB31_3 .LBB31_47: movl $9922, %edi # imm = 0x26C2 jmp .LBB31_3 .LBB31_25: movl $9942, %edi # imm = 0x26D6 jmp .LBB31_3 .LBB31_57: movl $9926, %edi # imm = 0x26C6 jmp .LBB31_3 .LBB31_61: movl $9929, %edi # imm = 0x26C9 jmp .LBB31_3 .LBB31_4: movl $9902, %edi # imm = 0x26AE jmp .LBB31_3 .LBB31_54: movl $9924, %edi # imm = 0x26C4 jmp .LBB31_3 .LBB31_18: movl $9910, %edi # imm = 0x26B6 jmp .LBB31_3 .LBB31_56: movl $9971, %edi # imm = 0x26F3 jmp .LBB31_3 .LBB31_5: movl $9903, %edi # imm = 0x26AF jmp .LBB31_3 .LBB31_11: movl $9905, %edi # imm = 0x26B1 jmp .LBB31_3 .LBB31_36: movl $9914, %edi # imm = 0x26BA jmp .LBB31_3 .LBB31_62: movl $9930, %edi # imm = 0x26CA jmp .LBB31_3 .LBB31_65: movl $9932, %edi # imm = 0x26CC jmp .LBB31_3 .LBB31_15: movl $9908, %edi # imm = 0x26B4 jmp .LBB31_3 .LBB31_6: movl $9904, %edi # imm = 0x26B0 jmp .LBB31_3 .LBB31_26: movl $9911, %edi # imm = 0x26B7 jmp .LBB31_3 .LBB31_31: movl $9943, %edi # imm = 0x26D7 jmp .LBB31_3 .LBB31_53: movl $9923, %edi # imm = 0x26C3 jmp .LBB31_3 .LBB31_16: movl $9909, %edi # imm = 0x26B5 jmp .LBB31_3 .LBB31_8: movl $9947, %edi # imm = 0x26DB jmp .LBB31_3 .LBB31_12: movl $9950, %edi # imm = 0x26DE jmp .LBB31_3 .LBB31_14: movl $9907, %edi # imm = 0x26B3 jmp .LBB31_3 .LBB31_44: movl $9920, %edi # imm = 0x26C0 jmp .LBB31_3 .LBB31_69: movl $9976, %edi # imm = 0x26F8 jmp .LBB31_3 .LBB31_9: movl $9948, %edi # imm = 0x26DC jmp .LBB31_3 .LBB31_78: movl $9939, %edi # imm = 0x26D3 jmp .LBB31_3 .LBB31_35: movl $9913, %edi # imm = 0x26B9 jmp .LBB31_3 .LBB31_23: movl $9956, %edi # imm = 0x26E4 jmp .LBB31_3 .LBB31_55: movl $9925, %edi # imm = 0x26C5 jmp .LBB31_3 .LBB31_63: movl $9931, %edi # imm = 0x26CB jmp .LBB31_3 .LBB31_27: movl $9912, %edi # imm = 0x26B8 jmp .LBB31_3 .LBB31_72: movl $9935, %edi # imm = 0x26CF jmp .LBB31_3 .LBB31_37: movl $9915, %edi # imm = 0x26BB jmp .LBB31_3 .LBB31_38: movl $9916, %edi # imm = 0x26BC jmp .LBB31_3 .LBB31_24: movl $9957, %edi # imm = 0x26E5 jmp .LBB31_3 .LBB31_70: movl $9944, %edi # imm = 0x26D8 jmp .LBB31_3 .LBB31_41: movl $9918, %edi # imm = 0x26BE jmp .LBB31_3 .LBB31_42: movl $9964, %edi # imm = 0x26EC jmp .LBB31_3 .LBB31_46: movl $9965, %edi # imm = 0x26ED jmp .LBB31_3 .LBB31_32: movl $9960, %edi # imm = 0x26E8 jmp .LBB31_3 .LBB31_64: movl $9973, %edi # imm = 0x26F5 jmp .LBB31_3 .LBB31_30: movl $9959, %edi # imm = 0x26E7 jmp .LBB31_3 .LBB31_49: movl $9967, %edi # imm = 0x26EF jmp .LBB31_3 .LBB31_21: movl $9954, %edi # imm = 0x26E2 jmp .LBB31_3 .LBB31_73: movl $9936, %edi # imm = 0x26D0 jmp .LBB31_3 .LBB31_51: movl $9969, %edi # imm = 0x26F1 jmp .LBB31_3 .LBB31_10: movl $9949, %edi # imm = 0x26DD jmp .LBB31_3 .LBB31_34: movl $9962, %edi # imm = 0x26EA jmp .LBB31_3 .LBB31_52: movl $9970, %edi # imm = 0x26F2 jmp .LBB31_3 .LBB31_20: movl $9953, %edi # imm = 0x26E1 jmp .LBB31_3 .LBB31_40: movl $9963, %edi # imm = 0x26EB jmp .LBB31_3 .LBB31_60: movl $9972, %edi # imm = 0x26F4 jmp .LBB31_3 .LBB31_76: movl $9978, %edi # imm = 0x26FA .LBB31_3: callq _ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE movl %eax, %ebx .LBB31_82: movl %ebx, %eax popq %rbx .cfi_def_cfa_offset 8 retq .LBB31_81: .cfi_def_cfa_offset 16 callq _ZN6thrust6system15system_categoryEv movq %rax, %rdx jmp .LBB31_82 .Lfunc_end31: .size _ZNK6thrust6system6detail21system_error_category23default_error_conditionEi, .Lfunc_end31-_ZNK6thrust6system6detail21system_error_category23default_error_conditionEi .cfi_endproc .section .rodata._ZNK6thrust6system6detail21system_error_category23default_error_conditionEi,"aG",@progbits,_ZNK6thrust6system6detail21system_error_category23default_error_conditionEi,comdat .p2align 3, 0x0 .LJTI31_0: .quad .LBB31_2 .quad .LBB31_4 .quad .LBB31_5 .quad .LBB31_6 .quad .LBB31_11 .quad .LBB31_13 .quad .LBB31_14 .quad .LBB31_15 .quad .LBB31_16 .quad .LBB31_18 .quad .LBB31_26 .quad .LBB31_27 .quad .LBB31_35 .quad .LBB31_36 .quad .LBB31_37 .quad .LBB31_38 .quad .LBB31_39 .quad .LBB31_41 .quad .LBB31_43 .quad .LBB31_44 .quad .LBB31_45 .quad .LBB31_47 .quad .LBB31_53 .quad .LBB31_54 .quad .LBB31_55 .quad .LBB31_57 .quad .LBB31_58 .quad .LBB31_59 .quad .LBB31_61 .quad .LBB31_62 .quad .LBB31_63 .quad .LBB31_65 .quad .LBB31_66 .quad .LBB31_71 .quad .LBB31_72 .quad .LBB31_73 .quad .LBB31_81 .quad .LBB31_74 .quad .LBB31_78 .quad .LBB31_79 .quad .LBB31_80 .quad .LBB31_25 .quad .LBB31_31 .quad .LBB31_70 .quad .LBB31_28 .quad .LBB31_7 .quad .LBB31_8 .quad .LBB31_9 .quad .LBB31_10 .quad .LBB31_12 .quad .LBB31_17 .quad .LBB31_19 .quad .LBB31_20 .quad .LBB31_21 .quad .LBB31_22 .quad .LBB31_23 .quad .LBB31_24 .quad .LBB31_29 .quad .LBB31_30 .quad .LBB31_32 .quad .LBB31_33 .quad .LBB31_34 .quad .LBB31_40 .quad .LBB31_42 .quad .LBB31_46 .quad .LBB31_48 .quad .LBB31_49 .quad .LBB31_50 .quad .LBB31_51 .quad .LBB31_52 .quad .LBB31_56 .quad .LBB31_60 .quad .LBB31_64 .quad .LBB31_67 .quad .LBB31_68 .quad .LBB31_69 .quad .LBB31_75 .quad .LBB31_76 .quad .LBB31_77 # -- End function .section .text._ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei,"axG",@progbits,_ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei,comdat .weak _ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei # -- Begin function _ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei .p2align 4, 0x90 .type _ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei,@function _ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei: # @_ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %rbp, -16 movq %rdi, %rbx movzbl _ZGVZN6thrust6system16generic_categoryEvE6result(%rip), %eax testb %al, %al je .LBB32_1 .LBB32_3: # %_ZN6thrust6system16generic_categoryEv.exit movq _ZZN6thrust6system16generic_categoryEvE6result(%rip), %rax movl $_ZZN6thrust6system16generic_categoryEvE6result, %esi movq %rbx, %rdi callq *48(%rax) movq %rbx, %rax addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB32_1: .cfi_def_cfa_offset 32 movl $_ZGVZN6thrust6system16generic_categoryEvE6result, %edi movl %edx, %ebp callq __cxa_guard_acquire movl %ebp, %edx testl %eax, %eax je .LBB32_3 # %bb.2: movq $_ZTVN6thrust6system6detail22generic_error_categoryE+16, _ZZN6thrust6system16generic_categoryEvE6result(%rip) movl $_ZN6thrust6system14error_categoryD2Ev, %edi movl $_ZZN6thrust6system16generic_categoryEvE6result, %esi movl $__dso_handle, %edx callq __cxa_atexit movl $_ZGVZN6thrust6system16generic_categoryEvE6result, %edi callq __cxa_guard_release movl %ebp, %edx jmp .LBB32_3 .Lfunc_end32: .size _ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei, .Lfunc_end32-_ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei .cfi_endproc # -- End function .section .text._ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE,"axG",@progbits,_ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE,comdat .weak _ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE # -- Begin function _ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE .p2align 4, 0x90 .type _ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE,@function _ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE: # @_ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE .cfi_startproc # %bb.0: movl %edi, %eax movzbl _ZGVZN6thrust6system16generic_categoryEvE6result(%rip), %ecx testb %cl, %cl je .LBB33_1 # %bb.4: # %_ZN6thrust6system16generic_categoryEv.exit movl $_ZZN6thrust6system16generic_categoryEvE6result, %edx retq .LBB33_1: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movl $_ZGVZN6thrust6system16generic_categoryEvE6result, %edi movl %eax, %ebx callq __cxa_guard_acquire movl %eax, %ecx movl %ebx, %eax testl %ecx, %ecx je .LBB33_3 # %bb.2: movq $_ZTVN6thrust6system6detail22generic_error_categoryE+16, _ZZN6thrust6system16generic_categoryEvE6result(%rip) movl $_ZN6thrust6system14error_categoryD2Ev, %edi movl $_ZZN6thrust6system16generic_categoryEvE6result, %esi movl $__dso_handle, %edx callq __cxa_atexit movl $_ZGVZN6thrust6system16generic_categoryEvE6result, %edi callq __cxa_guard_release movl %ebx, %eax .LBB33_3: popq %rbx .cfi_def_cfa_offset 8 .cfi_restore %rbx movl $_ZZN6thrust6system16generic_categoryEvE6result, %edx retq .Lfunc_end33: .size _ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE, .Lfunc_end33-_ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE .cfi_endproc # -- End function .section .text._ZN6thrust6system6detail22generic_error_categoryD0Ev,"axG",@progbits,_ZN6thrust6system6detail22generic_error_categoryD0Ev,comdat .weak _ZN6thrust6system6detail22generic_error_categoryD0Ev # -- Begin function _ZN6thrust6system6detail22generic_error_categoryD0Ev .p2align 4, 0x90 .type _ZN6thrust6system6detail22generic_error_categoryD0Ev,@function _ZN6thrust6system6detail22generic_error_categoryD0Ev: # @_ZN6thrust6system6detail22generic_error_categoryD0Ev .cfi_startproc # %bb.0: movq $_ZTVN6thrust6system14error_categoryE+16, (%rdi) jmp _ZdlPv # TAILCALL .Lfunc_end34: .size _ZN6thrust6system6detail22generic_error_categoryD0Ev, .Lfunc_end34-_ZN6thrust6system6detail22generic_error_categoryD0Ev .cfi_endproc # -- End function .section .text._ZNK6thrust6system6detail22generic_error_category4nameEv,"axG",@progbits,_ZNK6thrust6system6detail22generic_error_category4nameEv,comdat .weak _ZNK6thrust6system6detail22generic_error_category4nameEv # -- Begin function _ZNK6thrust6system6detail22generic_error_category4nameEv .p2align 4, 0x90 .type _ZNK6thrust6system6detail22generic_error_category4nameEv,@function _ZNK6thrust6system6detail22generic_error_category4nameEv: # @_ZNK6thrust6system6detail22generic_error_category4nameEv .cfi_startproc # %bb.0: movl $.L.str.10, %eax retq .Lfunc_end35: .size _ZNK6thrust6system6detail22generic_error_category4nameEv, .Lfunc_end35-_ZNK6thrust6system6detail22generic_error_category4nameEv .cfi_endproc # -- End function .section .text._ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei,"axG",@progbits,_ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei,comdat .weak _ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei # -- Begin function _ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei .p2align 4, 0x90 .type _ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei,@function _ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei: # @_ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx movl %edx, %edi callq strerror movq %rax, %r14 leaq 16(%rbx), %rax movq %rax, (%rbx) testq %r14, %r14 je .LBB36_10 # %bb.1: movq %r14, %rdi callq strlen movq %rax, %r15 cmpq $16, %rax jb .LBB36_5 # %bb.2: testq %r15, %r15 js .LBB36_12 # %bb.3: movq %r15, %rdi incq %rdi js .LBB36_13 # %bb.4: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i callq _Znwm movq %rax, (%rbx) movq %r15, 16(%rbx) .LBB36_5: testq %r15, %r15 je .LBB36_9 # %bb.6: movq (%rbx), %rdi cmpq $1, %r15 jne .LBB36_8 # %bb.7: movzbl (%r14), %eax movb %al, (%rdi) jmp .LBB36_9 .LBB36_10: movabsq $8245935278387129975, %rcx # imm = 0x726F727265206E77 movq %rcx, 5(%rax) movabsq $2336936577129475669, %rcx # imm = 0x206E776F6E6B6E55 movq %rcx, (%rax) movq $13, 8(%rbx) leaq 29(%rbx), %rax jmp .LBB36_11 .LBB36_8: movq %r14, %rsi movq %r15, %rdx callq memcpy@PLT .LBB36_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit movq %r15, 8(%rbx) movq (%rbx), %rax addq %r15, %rax .LBB36_11: # %.critedge movb $0, (%rax) movq %rbx, %rax popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB36_13: # %.noexc11.i .cfi_def_cfa_offset 32 callq _ZSt17__throw_bad_allocv .LBB36_12: # %.noexc.i movl $.L.str.11, %edi callq _ZSt20__throw_length_errorPKc .Lfunc_end36: .size _ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei, .Lfunc_end36-_ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei .cfi_endproc # -- End function .section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,comdat .weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .p2align 4, 0x90 .type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,@function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .cfi_startproc # %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $40, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %r8, %rbp movq %rcx, 32(%rsp) # 8-byte Spill movq %rsi, %r15 movq %rdi, %rbx movq (%rdi), %r14 movq 8(%rdi), %r12 movq %r8, (%rsp) # 8-byte Spill movq %rdx, 16(%rsp) # 8-byte Spill subq %rdx, %rbp leaq 16(%rdi), %rcx movl $15, %eax cmpq %rcx, %r14 je .LBB37_2 # %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit movq 16(%rbx), %rax .LBB37_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit addq %r12, %rbp js .LBB37_26 # %bb.3: cmpq %rax, %rbp jbe .LBB37_6 # %bb.4: addq %rax, %rax cmpq %rax, %rbp jae .LBB37_6 # %bb.5: movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF cmpq %rbp, %rax cmovbq %rax, %rbp .LBB37_6: movq %rbp, %rdi incq %rdi js .LBB37_27 # %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit movq %rcx, 24(%rsp) # 8-byte Spill callq _Znwm movq %rax, %r13 testq %r15, %r15 je .LBB37_11 # %bb.8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit cmpq $1, %r15 jne .LBB37_10 # %bb.9: movzbl (%r14), %eax movb %al, (%r13) jmp .LBB37_11 .LBB37_10: movq %r13, %rdi movq %r14, %rsi movq %r15, %rdx callq memcpy@PLT .LBB37_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit movq %r14, 8(%rsp) # 8-byte Spill movq 16(%rsp), %rax # 8-byte Reload leaq (%rax,%r15), %r14 movq 32(%rsp), %rsi # 8-byte Reload testq %rsi, %rsi movq (%rsp), %rdx # 8-byte Reload je .LBB37_18 # %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit testq %rdx, %rdx je .LBB37_18 # %bb.13: je .LBB37_18 # %bb.14: leaq (%r15,%r13), %rdi cmpq $1, %rdx jne .LBB37_16 # %bb.15: movzbl (%rsi), %eax movb %al, (%rdi) jmp .LBB37_17 .LBB37_16: callq memcpy@PLT .LBB37_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26 movq (%rsp), %rdx # 8-byte Reload .LBB37_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26 cmpq %r14, %r12 je .LBB37_23 # %bb.19: subq %r14, %r12 je .LBB37_23 # %bb.20: movq %r13, %rdi addq %r15, %rdi addq %rdx, %rdi addq 8(%rsp), %r15 # 8-byte Folded Reload addq 16(%rsp), %r15 # 8-byte Folded Reload cmpq $1, %r12 jne .LBB37_22 # %bb.21: movzbl (%r15), %eax movb %al, (%rdi) jmp .LBB37_23 .LBB37_22: movq %r15, %rsi movq %r12, %rdx callq memcpy@PLT .LBB37_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit27 movq 8(%rsp), %rdi # 8-byte Reload cmpq 24(%rsp), %rdi # 8-byte Folded Reload je .LBB37_25 # %bb.24: # %.critedge.i callq _ZdlPv .LBB37_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit movq %r13, (%rbx) movq %rbp, 16(%rbx) addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB37_27: .cfi_def_cfa_offset 96 callq _ZSt17__throw_bad_allocv .LBB37_26: movl $.L.str.11, %edi callq _ZSt20__throw_length_errorPKc .Lfunc_end37: .size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm, .Lfunc_end37-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .cfi_endproc # -- End function .section .text._ZN6thrust6system6detail9bad_allocD0Ev,"axG",@progbits,_ZN6thrust6system6detail9bad_allocD0Ev,comdat .weak _ZN6thrust6system6detail9bad_allocD0Ev # -- Begin function _ZN6thrust6system6detail9bad_allocD0Ev .p2align 4, 0x90 .type _ZN6thrust6system6detail9bad_allocD0Ev,@function _ZN6thrust6system6detail9bad_allocD0Ev: # @_ZN6thrust6system6detail9bad_allocD0Ev .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq %rdi, %rbx movq $_ZTVN6thrust6system6detail9bad_allocE+16, (%rdi) movq 8(%rdi), %rdi leaq 24(%rbx), %rax cmpq %rax, %rdi je .LBB38_2 # %bb.1: # %.critedge.i.i.i callq _ZdlPv .LBB38_2: # %_ZN6thrust6system6detail9bad_allocD2Ev.exit movq %rbx, %rdi callq _ZNSt9bad_allocD2Ev movq %rbx, %rdi popq %rbx .cfi_def_cfa_offset 8 jmp _ZdlPv # TAILCALL .Lfunc_end38: .size _ZN6thrust6system6detail9bad_allocD0Ev, .Lfunc_end38-_ZN6thrust6system6detail9bad_allocD0Ev .cfi_endproc # -- End function .section .text._ZNK6thrust6system6detail9bad_alloc4whatEv,"axG",@progbits,_ZNK6thrust6system6detail9bad_alloc4whatEv,comdat .weak _ZNK6thrust6system6detail9bad_alloc4whatEv # -- Begin function _ZNK6thrust6system6detail9bad_alloc4whatEv .p2align 4, 0x90 .type _ZNK6thrust6system6detail9bad_alloc4whatEv,@function _ZNK6thrust6system6detail9bad_alloc4whatEv: # @_ZNK6thrust6system6detail9bad_alloc4whatEv .cfi_startproc # %bb.0: movq 8(%rdi), %rax retq .Lfunc_end39: .size _ZNK6thrust6system6detail9bad_alloc4whatEv, .Lfunc_end39-_ZNK6thrust6system6detail9bad_alloc4whatEv .cfi_endproc # -- End function .section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,comdat .weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm .p2align 4, 0x90 .type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,@function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx movq 8(%rdi), %rax movq %rdx, %rdi subq %rax, %rdi movabsq $9223372036854775807, %r9 # imm = 0x7FFFFFFFFFFFFFFF addq %rdi, %r9 cmpq %r8, %r9 jb .LBB40_19 # %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit movq %r8, %r15 subq %rdx, %r15 addq %rax, %r15 movq (%rbx), %rdi leaq 16(%rbx), %r10 movl $15, %r9d cmpq %r10, %rdi je .LBB40_3 # %bb.2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit movq 16(%rbx), %r9 .LBB40_3: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit cmpq %r9, %r15 jbe .LBB40_4 # %bb.17: movq %rbx, %rdi callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm jmp .LBB40_18 .LBB40_4: leaq (%rdi,%rsi), %r14 addq %rdx, %rsi movq %rax, %r9 subq %rsi, %r9 cmpq %rcx, %rdi ja .LBB40_6 # %bb.5: addq %rax, %rdi cmpq %rcx, %rdi jae .LBB40_16 .LBB40_6: cmpq %rdx, %r8 je .LBB40_12 # %bb.7: cmpq %rsi, %rax je .LBB40_12 # %bb.8: testq %r9, %r9 je .LBB40_12 # %bb.9: leaq (%r14,%r8), %rdi addq %r14, %rdx cmpq $1, %r9 jne .LBB40_11 # %bb.10: movzbl (%rdx), %eax movb %al, (%rdi) .LBB40_12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_moveEPcPKcm.exit testq %r8, %r8 je .LBB40_18 .LBB40_13: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_moveEPcPKcm.exit cmpq $1, %r8 jne .LBB40_15 # %bb.14: movzbl (%rcx), %eax movb %al, (%r14) jmp .LBB40_18 .LBB40_15: movq %r14, %rdi movq %rcx, %rsi movq %r8, %rdx callq memcpy@PLT .LBB40_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit movq %r15, 8(%rbx) movq (%rbx), %rax movb $0, (%rax,%r15) movq %rbx, %rax popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB40_11: .cfi_def_cfa_offset 48 movq %rdx, %rsi movq %r9, %rdx movq %r8, %r12 movq %rcx, %r13 callq memmove@PLT movq %r13, %rcx movq %r12, %r8 testq %r8, %r8 jne .LBB40_13 jmp .LBB40_18 .LBB40_16: movq %rbx, %rdi movq %r14, %rsi callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_replace_coldEPcmPKcmm jmp .LBB40_18 .LBB40_19: movl $.L.str.17, %edi callq _ZSt20__throw_length_errorPKc .Lfunc_end40: .size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm, .Lfunc_end40-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm .cfi_endproc # -- End function .section .text._ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc,"axG",@progbits,_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc,comdat .weak _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc # -- Begin function _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc .p2align 4, 0x90 .type _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc,@function _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc: # @_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 movq %rcx, %rsi callq _ZNSt13runtime_errorC2EPKc movq $_ZTVN6thrust6system12system_errorE+16, (%r14) movl %ebp, 16(%r14) movq %rbx, 24(%r14) leaq 48(%r14), %rax movq %rax, 32(%r14) movq $0, 40(%r14) movb $0, 48(%r14) popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end41: .size _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc, .Lfunc_end41-_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc .cfi_endproc # -- End function .section .text._ZN6thrust6system12system_errorD2Ev,"axG",@progbits,_ZN6thrust6system12system_errorD2Ev,comdat .weak _ZN6thrust6system12system_errorD2Ev # -- Begin function _ZN6thrust6system12system_errorD2Ev .p2align 4, 0x90 .type _ZN6thrust6system12system_errorD2Ev,@function _ZN6thrust6system12system_errorD2Ev: # @_ZN6thrust6system12system_errorD2Ev .cfi_startproc # %bb.0: movq $_ZTVN6thrust6system12system_errorE+16, (%rdi) movq 32(%rdi), %rax leaq 48(%rdi), %rcx cmpq %rcx, %rax je _ZNSt13runtime_errorD2Ev # TAILCALL # %bb.1: # %.critedge.i.i pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq %rdi, %rbx movq %rax, %rdi callq _ZdlPv movq %rbx, %rdi popq %rbx .cfi_def_cfa_offset 8 .cfi_restore %rbx jmp _ZNSt13runtime_errorD2Ev # TAILCALL .Lfunc_end42: .size _ZN6thrust6system12system_errorD2Ev, .Lfunc_end42-_ZN6thrust6system12system_errorD2Ev .cfi_endproc # -- End function .section .text._ZN6thrust6system12system_errorD0Ev,"axG",@progbits,_ZN6thrust6system12system_errorD0Ev,comdat .weak _ZN6thrust6system12system_errorD0Ev # -- Begin function _ZN6thrust6system12system_errorD0Ev .p2align 4, 0x90 .type _ZN6thrust6system12system_errorD0Ev,@function _ZN6thrust6system12system_errorD0Ev: # @_ZN6thrust6system12system_errorD0Ev .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq %rdi, %rbx movq $_ZTVN6thrust6system12system_errorE+16, (%rdi) movq 32(%rdi), %rdi leaq 48(%rbx), %rax cmpq %rax, %rdi je .LBB43_2 # %bb.1: # %.critedge.i.i.i callq _ZdlPv .LBB43_2: # %_ZN6thrust6system12system_errorD2Ev.exit movq %rbx, %rdi callq _ZNSt13runtime_errorD2Ev movq %rbx, %rdi popq %rbx .cfi_def_cfa_offset 8 jmp _ZdlPv # TAILCALL .Lfunc_end43: .size _ZN6thrust6system12system_errorD0Ev, .Lfunc_end43-_ZN6thrust6system12system_errorD0Ev .cfi_endproc # -- End function .section .text._ZNK6thrust6system12system_error4whatEv,"axG",@progbits,_ZNK6thrust6system12system_error4whatEv,comdat .weak _ZNK6thrust6system12system_error4whatEv # -- Begin function _ZNK6thrust6system12system_error4whatEv .p2align 4, 0x90 .type _ZNK6thrust6system12system_error4whatEv,@function _ZNK6thrust6system12system_error4whatEv: # @_ZNK6thrust6system12system_error4whatEv .Lfunc_begin7: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception7 # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $40, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 32(%rdi), %r14 cmpq $0, 40(%rdi) je .LBB44_3 .LBB44_1: movq (%r14), %rax .LBB44_2: addq $40, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB44_3: .cfi_def_cfa_offset 80 movq %rdi, %rbx callq _ZNKSt13runtime_error4whatEv movq %rax, %r15 movq 40(%rbx), %r12 movq %rax, %rdi callq strlen .Ltmp135: movq %r14, %rdi xorl %esi, %esi movq %r12, %rdx movq %r15, %rcx movq %rax, %r8 callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm .Ltmp136: # %bb.4: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEPKc.exit cmpl $0, 16(%rbx) je .LBB44_1 # %bb.5: movabsq $9223372036854775806, %r15 # imm = 0x7FFFFFFFFFFFFFFE movq 40(%rbx), %rsi testq %rsi, %rsi je .LBB44_13 # %bb.6: movq %rsi, %rax andq $-2, %rax cmpq %r15, %rax je .LBB44_27 # %bb.7: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i leaq 2(%rsi), %r12 movq 32(%rbx), %rax leaq 48(%rbx), %rdx movl $15, %ecx cmpq %rdx, %rax je .LBB44_9 # %bb.8: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i movq 48(%rbx), %rcx .LBB44_9: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i cmpq %rcx, %r12 jbe .LBB44_11 # %bb.10: .Ltmp137: movl $.L.str.14, %ecx movl $2, %r8d movq %r14, %rdi xorl %edx, %edx callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .Ltmp138: jmp .LBB44_12 .LBB44_11: movw $8250, (%rax,%rsi) # imm = 0x203A .LBB44_12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLEPKc.exit movq %r12, 40(%rbx) movq 32(%rbx), %rax movb $0, (%rax,%r12) .LBB44_13: movq 24(%rbx), %rsi movl 16(%rbx), %edx movq (%rsi), %rax .Ltmp142: leaq 8(%rsp), %rdi callq *48(%rax) .Ltmp143: # %bb.14: # %_ZNK6thrust6system10error_code7messageB5cxx11Ev.exit movq 16(%rsp), %r8 movq 40(%rbx), %rsi subq %rsi, %r15 incq %r15 cmpq %r8, %r15 jb .LBB44_25 # %bb.15: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i leaq (%rsi,%r8), %r15 movq 32(%rbx), %rdi leaq 48(%rbx), %rcx movl $15, %eax cmpq %rcx, %rdi je .LBB44_17 # %bb.16: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i movq 48(%rbx), %rax .LBB44_17: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i movq 8(%rsp), %rcx cmpq %rax, %r15 jbe .LBB44_19 # %bb.18: .Ltmp145: movq %r14, %rdi xorl %edx, %edx callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm .Ltmp146: jmp .LBB44_23 .LBB44_19: testq %r8, %r8 je .LBB44_23 # %bb.20: addq %rsi, %rdi cmpq $1, %r8 jne .LBB44_22 # %bb.21: movzbl (%rcx), %eax movb %al, (%rdi) jmp .LBB44_23 .LBB44_22: movq %rcx, %rsi movq %r8, %rdx callq memcpy@PLT .LBB44_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLERKS4_.exit movq %r15, 40(%rbx) movq 32(%rbx), %rax movb $0, (%rax,%r15) movq 8(%rsp), %rdi leaq 24(%rsp), %rax cmpq %rax, %rdi je .LBB44_1 # %bb.24: # %.critedge.i.i callq _ZdlPv jmp .LBB44_1 .LBB44_25: .Ltmp147: movl $.L.str.15, %edi callq _ZSt20__throw_length_errorPKc .Ltmp148: # %bb.26: # %.noexc6 .LBB44_27: .Ltmp139: movl $.L.str.15, %edi callq _ZSt20__throw_length_errorPKc .Ltmp140: # %bb.28: # %.noexc .LBB44_29: .Ltmp144: jmp .LBB44_33 .LBB44_30: .Ltmp149: movq %rax, %r14 movq 8(%rsp), %rdi leaq 24(%rsp), %rax cmpq %rax, %rdi je .LBB44_34 # %bb.31: # %.critedge.i.i8 callq _ZdlPv jmp .LBB44_34 .LBB44_32: .Ltmp141: .LBB44_33: movq %rax, %r14 .LBB44_34: movq %r14, %rdi callq __cxa_begin_catch movq %rbx, %rdi callq _ZNKSt13runtime_error4whatEv movq %rax, %rbx .Ltmp150: callq __cxa_end_catch .Ltmp151: # %bb.35: movq %rbx, %rax jmp .LBB44_2 .LBB44_36: .Ltmp152: movq %rax, %rdi callq __clang_call_terminate .Lfunc_end44: .size _ZNK6thrust6system12system_error4whatEv, .Lfunc_end44-_ZNK6thrust6system12system_error4whatEv .cfi_endproc .section .gcc_except_table._ZNK6thrust6system12system_error4whatEv,"aG",@progbits,_ZNK6thrust6system12system_error4whatEv,comdat .p2align 2, 0x0 GCC_except_table44: .Lexception7: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase3-.Lttbaseref3 .Lttbaseref3: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end7-.Lcst_begin7 .Lcst_begin7: .uleb128 .Ltmp135-.Lfunc_begin7 # >> Call Site 1 << .uleb128 .Ltmp138-.Ltmp135 # Call between .Ltmp135 and .Ltmp138 .uleb128 .Ltmp141-.Lfunc_begin7 # jumps to .Ltmp141 .byte 1 # On action: 1 .uleb128 .Ltmp142-.Lfunc_begin7 # >> Call Site 2 << .uleb128 .Ltmp143-.Ltmp142 # Call between .Ltmp142 and .Ltmp143 .uleb128 .Ltmp144-.Lfunc_begin7 # jumps to .Ltmp144 .byte 1 # On action: 1 .uleb128 .Ltmp145-.Lfunc_begin7 # >> Call Site 3 << .uleb128 .Ltmp146-.Ltmp145 # Call between .Ltmp145 and .Ltmp146 .uleb128 .Ltmp149-.Lfunc_begin7 # jumps to .Ltmp149 .byte 1 # On action: 1 .uleb128 .Ltmp146-.Lfunc_begin7 # >> Call Site 4 << .uleb128 .Ltmp147-.Ltmp146 # Call between .Ltmp146 and .Ltmp147 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp147-.Lfunc_begin7 # >> Call Site 5 << .uleb128 .Ltmp148-.Ltmp147 # Call between .Ltmp147 and .Ltmp148 .uleb128 .Ltmp149-.Lfunc_begin7 # jumps to .Ltmp149 .byte 1 # On action: 1 .uleb128 .Ltmp139-.Lfunc_begin7 # >> Call Site 6 << .uleb128 .Ltmp140-.Ltmp139 # Call between .Ltmp139 and .Ltmp140 .uleb128 .Ltmp141-.Lfunc_begin7 # jumps to .Ltmp141 .byte 1 # On action: 1 .uleb128 .Ltmp140-.Lfunc_begin7 # >> Call Site 7 << .uleb128 .Ltmp150-.Ltmp140 # Call between .Ltmp140 and .Ltmp150 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp150-.Lfunc_begin7 # >> Call Site 8 << .uleb128 .Ltmp151-.Ltmp150 # Call between .Ltmp150 and .Ltmp151 .uleb128 .Ltmp152-.Lfunc_begin7 # jumps to .Ltmp152 .byte 1 # On action: 1 .Lcst_end7: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase3: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorIPKiEEEEvmT_SA_RNS0_18contiguous_storageIiS3_EE,"axG",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorIPKiEEEEvmT_SA_RNS0_18contiguous_storageIiS3_EE,comdat .weak _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorIPKiEEEEvmT_SA_RNS0_18contiguous_storageIiS3_EE # -- Begin function _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorIPKiEEEEvmT_SA_RNS0_18contiguous_storageIiS3_EE .p2align 4, 0x90 .type _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorIPKiEEEEvmT_SA_RNS0_18contiguous_storageIiS3_EE,@function _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorIPKiEEEEvmT_SA_RNS0_18contiguous_storageIiS3_EE: # @_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorIPKiEEEEvmT_SA_RNS0_18contiguous_storageIiS3_EE .Lfunc_begin8: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception8 # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 pushq %rax .cfi_def_cfa_offset 48 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %r8, %rbx testq %rsi, %rsi je .LBB45_1 # %bb.4: # %_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE8allocateEm.exit movq %rcx, %r15 movq %rdx, %r14 movq 16(%rdi), %r12 addq %r12, %r12 cmpq %r12, %rsi cmovaq %rsi, %r12 movq (%rbx), %rax leaq (,%r12,4), %rsi movq 8(%rax), %rdi movl $4, %edx callq _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm movq %rax, 8(%rbx) movq %r12, 16(%rbx) movq %r14, %rcx subq %r15, %rcx sarq $2, %rcx negq %rcx .Ltmp153: leaq 6(%rsp), %rdi leaq 7(%rsp), %rsi movq %r14, %rdx movq %rax, %r8 callq _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS_6system3cpp6detail3tagENS0_3tagENS_6detail15normal_iteratorIPKiEEmNS_10device_ptrIiEEEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE .Ltmp154: jmp .LBB45_3 .LBB45_1: movq 16(%rbx), %rdx testq %rdx, %rdx je .LBB45_3 # %bb.2: movq (%rbx), %rax movq 8(%rbx), %rsi shlq $2, %rdx movq 8(%rax), %rdi movl $4, %ecx callq _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm xorps %xmm0, %xmm0 movups %xmm0, 8(%rbx) .LBB45_3: # %_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv.exit addq $8, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB45_5: .cfi_def_cfa_offset 48 .Ltmp155: movq %rax, %rdi callq __cxa_begin_catch .Ltmp156: movq %rbx, %rdi callq _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv .Ltmp157: # %bb.6: .Ltmp158: callq __cxa_rethrow .Ltmp159: # %bb.10: .LBB45_7: .Ltmp160: movq %rax, %rbx .Ltmp161: callq __cxa_end_catch .Ltmp162: # %bb.8: movq %rbx, %rdi callq _Unwind_Resume@PLT .LBB45_9: .Ltmp163: movq %rax, %rdi callq __clang_call_terminate .Lfunc_end45: .size _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorIPKiEEEEvmT_SA_RNS0_18contiguous_storageIiS3_EE, .Lfunc_end45-_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorIPKiEEEEvmT_SA_RNS0_18contiguous_storageIiS3_EE .cfi_endproc .section .gcc_except_table._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorIPKiEEEEvmT_SA_RNS0_18contiguous_storageIiS3_EE,"aG",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorIPKiEEEEvmT_SA_RNS0_18contiguous_storageIiS3_EE,comdat .p2align 2, 0x0 GCC_except_table45: .Lexception8: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase4-.Lttbaseref4 .Lttbaseref4: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end8-.Lcst_begin8 .Lcst_begin8: .uleb128 .Lfunc_begin8-.Lfunc_begin8 # >> Call Site 1 << .uleb128 .Ltmp153-.Lfunc_begin8 # Call between .Lfunc_begin8 and .Ltmp153 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp153-.Lfunc_begin8 # >> Call Site 2 << .uleb128 .Ltmp154-.Ltmp153 # Call between .Ltmp153 and .Ltmp154 .uleb128 .Ltmp155-.Lfunc_begin8 # jumps to .Ltmp155 .byte 1 # On action: 1 .uleb128 .Ltmp154-.Lfunc_begin8 # >> Call Site 3 << .uleb128 .Ltmp156-.Ltmp154 # Call between .Ltmp154 and .Ltmp156 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp156-.Lfunc_begin8 # >> Call Site 4 << .uleb128 .Ltmp159-.Ltmp156 # Call between .Ltmp156 and .Ltmp159 .uleb128 .Ltmp160-.Lfunc_begin8 # jumps to .Ltmp160 .byte 0 # On action: cleanup .uleb128 .Ltmp161-.Lfunc_begin8 # >> Call Site 5 << .uleb128 .Ltmp162-.Ltmp161 # Call between .Ltmp161 and .Ltmp162 .uleb128 .Ltmp163-.Lfunc_begin8 # jumps to .Ltmp163 .byte 1 # On action: 1 .uleb128 .Ltmp162-.Lfunc_begin8 # >> Call Site 6 << .uleb128 .Lfunc_end45-.Ltmp162 # Call between .Ltmp162 and .Lfunc_end45 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end8: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase4: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv,"axG",@progbits,_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv,comdat .weak _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv # -- Begin function _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv .p2align 4, 0x90 .type _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv,@function _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv: # @_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv .cfi_startproc # %bb.0: movq 16(%rdi), %rdx testq %rdx, %rdx je .LBB46_2 # %bb.1: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq (%rdi), %rax movq 8(%rdi), %rsi shlq $2, %rdx movq 8(%rax), %rax movl $4, %ecx movq %rdi, %rbx movq %rax, %rdi callq _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm xorps %xmm0, %xmm0 movups %xmm0, 8(%rbx) popq %rbx .cfi_def_cfa_offset 8 .LBB46_2: retq .Lfunc_end46: .size _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv, .Lfunc_end46-_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv .cfi_endproc # -- End function .section .text._ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS_6system3cpp6detail3tagENS0_3tagENS_6detail15normal_iteratorIPKiEEmNS_10device_ptrIiEEEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,"axG",@progbits,_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS_6system3cpp6detail3tagENS0_3tagENS_6detail15normal_iteratorIPKiEEmNS_10device_ptrIiEEEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,comdat .weak _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS_6system3cpp6detail3tagENS0_3tagENS_6detail15normal_iteratorIPKiEEmNS_10device_ptrIiEEEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE # -- Begin function _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS_6system3cpp6detail3tagENS0_3tagENS_6detail15normal_iteratorIPKiEEmNS_10device_ptrIiEEEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE .p2align 4, 0x90 .type _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS_6system3cpp6detail3tagENS0_3tagENS_6detail15normal_iteratorIPKiEEmNS_10device_ptrIiEEEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,@function _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS_6system3cpp6detail3tagENS0_3tagENS_6detail15normal_iteratorIPKiEEmNS_10device_ptrIiEEEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE: # @_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS_6system3cpp6detail3tagENS0_3tagENS_6detail15normal_iteratorIPKiEEmNS_10device_ptrIiEEEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE .Lfunc_begin9: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception9 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movq %r8, %rbx movq %rcx, %r14 testq %rcx, %rcx je .LBB47_6 # %bb.1: # %_ZN6thrust11hip_rocprim22trivial_copy_to_deviceIiEE10hipError_tPT_PKS3_mP12ihipStream_t.exit.i leaq (,%r14,4), %rax movq %rbx, %rdi movq %rdx, %rsi movq %rax, %rdx movl $1, %ecx xorl %r8d, %r8d callq hipMemcpyWithStream movl %eax, %ebp callq hipGetLastError testl %ebp, %ebp jne .LBB47_2 .LBB47_6: # %_ZN6thrust11hip_rocprim6__copy19trivial_device_copyINS_6system3cpp6detail3tagENS0_3tagEimEEvRNS5_16execution_policyIT_EERNS0_16execution_policyIT0_EEPT1_PKSG_T2_.exit leaq (%rbx,%r14,4), %rax popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB47_2: .cfi_def_cfa_offset 32 movl $64, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp164: callq _ZN6thrust6system12hip_categoryEv .Ltmp165: # %bb.3: .Ltmp166: movl $.L.str.20, %ecx movq %rbx, %rdi movl %ebp, %esi movq %rax, %rdx callq _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc .Ltmp167: # %bb.4: movl $_ZTIN6thrust6system12system_errorE, %esi movl $_ZN6thrust6system12system_errorD2Ev, %edx movq %rbx, %rdi callq __cxa_throw .LBB47_5: .Ltmp168: movq %rax, %r14 movq %rbx, %rdi callq __cxa_free_exception movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end47: .size _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS_6system3cpp6detail3tagENS0_3tagENS_6detail15normal_iteratorIPKiEEmNS_10device_ptrIiEEEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE, .Lfunc_end47-_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS_6system3cpp6detail3tagENS0_3tagENS_6detail15normal_iteratorIPKiEEmNS_10device_ptrIiEEEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE .cfi_endproc .section .gcc_except_table._ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS_6system3cpp6detail3tagENS0_3tagENS_6detail15normal_iteratorIPKiEEmNS_10device_ptrIiEEEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,"aG",@progbits,_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS_6system3cpp6detail3tagENS0_3tagENS_6detail15normal_iteratorIPKiEEmNS_10device_ptrIiEEEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,comdat .p2align 2, 0x0 GCC_except_table47: .Lexception9: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end9-.Lcst_begin9 .Lcst_begin9: .uleb128 .Lfunc_begin9-.Lfunc_begin9 # >> Call Site 1 << .uleb128 .Ltmp164-.Lfunc_begin9 # Call between .Lfunc_begin9 and .Ltmp164 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp164-.Lfunc_begin9 # >> Call Site 2 << .uleb128 .Ltmp167-.Ltmp164 # Call between .Ltmp164 and .Ltmp167 .uleb128 .Ltmp168-.Lfunc_begin9 # jumps to .Ltmp168 .byte 0 # On action: cleanup .uleb128 .Ltmp167-.Lfunc_begin9 # >> Call Site 3 << .uleb128 .Lfunc_end47-.Ltmp167 # Call between .Ltmp167 and .Lfunc_end47 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end9: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em,"axG",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em,comdat .weak _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em # -- Begin function _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em .p2align 4, 0x90 .type _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em,@function _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em: # @_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em .Lfunc_begin10: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception10 # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsi, %r14 movq %rdi, %rbx movzbl _ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource(%rip), %eax testb %al, %al je .LBB48_1 .LBB48_3: # %_ZN6thrust16device_allocatorIiEC2Ev.exit movq $_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, (%rbx) xorps %xmm0, %xmm0 movups %xmm0, 8(%rbx) movq $0, 24(%rbx) testq %r14, %r14 je .LBB48_6 # %bb.4: # %_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE8allocateEm.exit.i movq (%rbx), %rax leaq (,%r14,4), %rsi movq 8(%rax), %rdi .Ltmp169: movl $4, %edx callq _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm .Ltmp170: # %bb.5: # %.noexc movq %rax, 8(%rbx) movq %r14, 16(%rbx) movq %r14, 24(%rbx) .Ltmp171: leaq 7(%rsp), %rdi movq %rax, %rsi xorl %edx, %edx movq %r14, %rcx callq _ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m .Ltmp172: .LBB48_6: # %_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE12default_initEm.exit addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB48_1: .cfi_def_cfa_offset 32 movl $_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi callq __cxa_guard_acquire testl %eax, %eax je .LBB48_3 # %bb.2: movq $_ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE+16, _ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource(%rip) movq $_ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource, _ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource+8(%rip) movl $_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi callq __cxa_guard_release jmp .LBB48_3 .LBB48_7: .Ltmp173: movq %rax, %r14 movq %rbx, %rdi callq _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end48: .size _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em, .Lfunc_end48-_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em .cfi_endproc .section .gcc_except_table._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em,"aG",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em,comdat .p2align 2, 0x0 GCC_except_table48: .Lexception10: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end10-.Lcst_begin10 .Lcst_begin10: .uleb128 .Ltmp169-.Lfunc_begin10 # >> Call Site 1 << .uleb128 .Ltmp172-.Ltmp169 # Call between .Ltmp169 and .Ltmp172 .uleb128 .Ltmp173-.Lfunc_begin10 # jumps to .Ltmp173 .byte 0 # On action: cleanup .uleb128 .Ltmp172-.Lfunc_begin10 # >> Call Site 2 << .uleb128 .Lfunc_end48-.Ltmp172 # Call between .Ltmp172 and .Lfunc_end48 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end10: .p2align 2, 0x0 # -- End function .section .text._ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,"axG",@progbits,_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,comdat .weak _ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m # -- Begin function _ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m .p2align 4, 0x90 .type _ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,@function _ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m: # @_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m .Lfunc_begin11: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception11 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $136, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %edx, 12(%rsp) # 4-byte Spill movq %rsi, 24(%rsp) # 8-byte Spill movl $4294967040, %r13d # imm = 0xFFFFFF00 movq %rcx, 16(%rsp) # 8-byte Spill addq %r13, %rcx decq %rcx shrq $8, %rcx movabsq $72057598332895489, %rdx # imm = 0x100000100000101 movq %rcx, %rax mulq %rdx cmpq $16777215, %rcx # imm = 0xFFFFFF jae .LBB49_1 .LBB49_5: # %_ZN6thrust11hip_rocprim14__parallel_for12parallel_forINS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEE10hipError_tT0_T_P12ihipStream_t.exit .cfi_escape 0x2e, 0x00 callq hipPeekAtLastError movl %eax, %ebp .cfi_escape 0x2e, 0x00 callq hipGetLastError testl %ebp, %ebp jne .LBB49_6 # %bb.12: # %_ZN6thrust11hip_rocprim14throw_on_errorE10hipError_tPKc.exit .cfi_escape 0x2e, 0x00 xorl %edi, %edi callq hipStreamSynchronize movl %eax, %ebp .cfi_escape 0x2e, 0x00 callq hipGetLastError testl %ebp, %ebp jne .LBB49_13 # %bb.17: # %_ZN6thrust11hip_rocprim14throw_on_errorE10hipError_tPKc.exit8 addq $136, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB49_1: # %.lr.ph.i .cfi_def_cfa_offset 192 movq %rdx, %r15 shrq $16, %r15 xorl %ebp, %ebp leaq 512(%r13), %r12 movabsq $-4294967040, %r14 # imm = 0xFFFFFFFF00000100 movq 16(%rsp), %rbx # 8-byte Reload jmp .LBB49_2 .p2align 4, 0x90 .LBB49_4: # in Loop: Header=BB49_2 Depth=1 addq %r13, %rbp addq %r14, %rbx decq %r15 je .LBB49_5 .LBB49_2: # =>This Inner Loop Header: Depth=1 cmpq %r13, %rbx movl $4294967040, %eax # imm = 0xFFFFFF00 cmovbq %rbx, %rax addq $255, %rax shrq $8, %rax leaq (%rax,%r13), %rdi addq $256, %rdi # imm = 0x100 .cfi_escape 0x2e, 0x00 movl $1, %esi movq %r12, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB49_4 # %bb.3: # in Loop: Header=BB49_2 Depth=1 movq 24(%rsp), %rax # 8-byte Reload movq %rax, 96(%rsp) movl 12(%rsp), %eax # 4-byte Reload movl %eax, 104(%rsp) movq 16(%rsp), %rax # 8-byte Reload movq %rax, 88(%rsp) movq %rbp, 80(%rsp) leaq 96(%rsp), %rax movq %rax, 112(%rsp) leaq 88(%rsp), %rax movq %rax, 120(%rsp) leaq 80(%rsp), %rax movq %rax, 128(%rsp) .cfi_escape 0x2e, 0x00 leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d .cfi_escape 0x2e, 0x10 movl $_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, %edi leaq 112(%rsp), %r9 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 jmp .LBB49_4 .LBB49_6: .cfi_escape 0x2e, 0x00 movl $64, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp174: .cfi_escape 0x2e, 0x00 callq _ZN6thrust6system12hip_categoryEv .Ltmp175: # %bb.7: .Ltmp176: .cfi_escape 0x2e, 0x00 movl $.L.str.21, %ecx movq %rbx, %rdi movl %ebp, %esi movq %rax, %rdx callq _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc .Ltmp177: # %bb.8: .cfi_escape 0x2e, 0x00 jmp .LBB49_9 .LBB49_13: .cfi_escape 0x2e, 0x00 movl $64, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp179: .cfi_escape 0x2e, 0x00 callq _ZN6thrust6system12hip_categoryEv .Ltmp180: # %bb.14: .Ltmp181: .cfi_escape 0x2e, 0x00 movl $.L.str.22, %ecx movq %rbx, %rdi movl %ebp, %esi movq %rax, %rdx callq _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc .Ltmp182: # %bb.15: .cfi_escape 0x2e, 0x00 .LBB49_9: movl $_ZTIN6thrust6system12system_errorE, %esi movl $_ZN6thrust6system12system_errorD2Ev, %edx movq %rbx, %rdi callq __cxa_throw .LBB49_16: .Ltmp183: jmp .LBB49_11 .LBB49_10: .Ltmp178: .LBB49_11: # %common.resume movq %rax, %r14 .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq __cxa_free_exception .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end49: .size _ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m, .Lfunc_end49-_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m .cfi_endproc .section .gcc_except_table._ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,"aG",@progbits,_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,comdat .p2align 2, 0x0 GCC_except_table49: .Lexception11: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end11-.Lcst_begin11 .Lcst_begin11: .uleb128 .Lfunc_begin11-.Lfunc_begin11 # >> Call Site 1 << .uleb128 .Ltmp174-.Lfunc_begin11 # Call between .Lfunc_begin11 and .Ltmp174 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp174-.Lfunc_begin11 # >> Call Site 2 << .uleb128 .Ltmp177-.Ltmp174 # Call between .Ltmp174 and .Ltmp177 .uleb128 .Ltmp178-.Lfunc_begin11 # jumps to .Ltmp178 .byte 0 # On action: cleanup .uleb128 .Ltmp177-.Lfunc_begin11 # >> Call Site 3 << .uleb128 .Ltmp179-.Ltmp177 # Call between .Ltmp177 and .Ltmp179 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp179-.Lfunc_begin11 # >> Call Site 4 << .uleb128 .Ltmp182-.Ltmp179 # Call between .Ltmp179 and .Ltmp182 .uleb128 .Ltmp183-.Lfunc_begin11 # jumps to .Ltmp183 .byte 0 # On action: cleanup .uleb128 .Ltmp182-.Lfunc_begin11 # >> Call Site 5 << .uleb128 .Lfunc_end49-.Ltmp182 # Call between .Ltmp182 and .Lfunc_end49 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end11: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat .weak _ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ # -- Begin function _ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .p2align 4, 0x90 .type _ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function _ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_: # @_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 64(%rsp) movl %esi, 72(%rsp) movq %rdx, 56(%rsp) movq %rcx, 48(%rsp) leaq 64(%rsp), %rax movq %rax, 80(%rsp) leaq 56(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rax movq %rax, 96(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 80(%rsp), %r9 movl $_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end50: .size _ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end50-_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .cfi_endproc # -- End function .section .text._ZN6thrust6detail11vector_baseIiSaIiEE12range_assignINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvT_SA_NS_27random_access_traversal_tagE,"axG",@progbits,_ZN6thrust6detail11vector_baseIiSaIiEE12range_assignINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvT_SA_NS_27random_access_traversal_tagE,comdat .weak _ZN6thrust6detail11vector_baseIiSaIiEE12range_assignINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvT_SA_NS_27random_access_traversal_tagE # -- Begin function _ZN6thrust6detail11vector_baseIiSaIiEE12range_assignINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvT_SA_NS_27random_access_traversal_tagE .p2align 4, 0x90 .type _ZN6thrust6detail11vector_baseIiSaIiEE12range_assignINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvT_SA_NS_27random_access_traversal_tagE,@function _ZN6thrust6detail11vector_baseIiSaIiEE12range_assignINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvT_SA_NS_27random_access_traversal_tagE: # @_ZN6thrust6detail11vector_baseIiSaIiEE12range_assignINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvT_SA_NS_27random_access_traversal_tagE .Lfunc_begin12: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception12 # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $40, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdx, %r15 movq %rsi, %rdx movq %rdi, %rbx movq %r15, %r14 subq %rsi, %r14 sarq $2, %r14 cmpq 16(%rdi), %r14 jbe .LBB51_7 # %bb.1: leaq 24(%rsp), %r12 xorps %xmm0, %xmm0 movups %xmm0, 24(%rsp) .Ltmp184: leaq 16(%rsp), %r8 movq %rbx, %rdi movq %r14, %rsi movq %r15, %rcx callq _ZN6thrust6detail11vector_baseIiSaIiEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SA_RNS0_18contiguous_storageIiS2_EE .Ltmp185: # %bb.2: movq 8(%rbx), %rdi movq 24(%rsp), %rax movq %rax, 8(%rbx) movq %rdi, 24(%rsp) movq 16(%rbx), %rax movq 32(%rsp), %rcx movq %rcx, 16(%rbx) movq %rax, 32(%rsp) movq %r14, 24(%rbx) testq %rax, %rax je .LBB51_11 # %bb.3: callq _ZdlPv xorps %xmm0, %xmm0 movups %xmm0, (%r12) jmp .LBB51_11 .LBB51_7: movq 24(%rbx), %rcx cmpq %r14, %rcx jae .LBB51_8 # %bb.9: leaq (%rdx,%rcx,4), %r12 movq 8(%rbx), %r8 leaq 16(%rsp), %rdi leaq 15(%rsp), %rsi callq _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmNS9_IPiEEEET3_RNS_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_NS8_17integral_constantIbLb1EEE movq 24(%rbx), %r8 shlq $2, %r8 addq 8(%rbx), %r8 subq %r12, %r15 sarq $2, %r15 leaq 15(%rsp), %rdi leaq 16(%rsp), %rsi movq %r12, %rdx movq %r15, %rcx callq _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmPiEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE jmp .LBB51_10 .LBB51_8: movq 8(%rbx), %r8 leaq 16(%rsp), %rdi leaq 15(%rsp), %rsi movq %r14, %rcx callq _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmNS9_IPiEEEET3_RNS_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_NS8_17integral_constantIbLb1EEE .LBB51_10: movq %r14, 24(%rbx) .LBB51_11: addq $40, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB51_4: .cfi_def_cfa_offset 80 .Ltmp186: movq %rax, %rbx cmpq $0, 32(%rsp) je .LBB51_6 # %bb.5: movq 24(%rsp), %rdi callq _ZdlPv xorps %xmm0, %xmm0 movups %xmm0, (%r12) .LBB51_6: # %_ZN6thrust6detail18contiguous_storageIiSaIiEED2Ev.exit31 movq %rbx, %rdi callq _Unwind_Resume@PLT .Lfunc_end51: .size _ZN6thrust6detail11vector_baseIiSaIiEE12range_assignINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvT_SA_NS_27random_access_traversal_tagE, .Lfunc_end51-_ZN6thrust6detail11vector_baseIiSaIiEE12range_assignINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvT_SA_NS_27random_access_traversal_tagE .cfi_endproc .section .gcc_except_table._ZN6thrust6detail11vector_baseIiSaIiEE12range_assignINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvT_SA_NS_27random_access_traversal_tagE,"aG",@progbits,_ZN6thrust6detail11vector_baseIiSaIiEE12range_assignINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvT_SA_NS_27random_access_traversal_tagE,comdat .p2align 2, 0x0 GCC_except_table51: .Lexception12: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end12-.Lcst_begin12 .Lcst_begin12: .uleb128 .Ltmp184-.Lfunc_begin12 # >> Call Site 1 << .uleb128 .Ltmp185-.Ltmp184 # Call between .Ltmp184 and .Ltmp185 .uleb128 .Ltmp186-.Lfunc_begin12 # jumps to .Ltmp186 .byte 0 # On action: cleanup .uleb128 .Ltmp185-.Lfunc_begin12 # >> Call Site 2 << .uleb128 .Lfunc_end51-.Ltmp185 # Call between .Ltmp185 and .Lfunc_end51 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end12: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6detail11vector_baseIiSaIiEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SA_RNS0_18contiguous_storageIiS2_EE,"axG",@progbits,_ZN6thrust6detail11vector_baseIiSaIiEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SA_RNS0_18contiguous_storageIiS2_EE,comdat .weak _ZN6thrust6detail11vector_baseIiSaIiEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SA_RNS0_18contiguous_storageIiS2_EE # -- Begin function _ZN6thrust6detail11vector_baseIiSaIiEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SA_RNS0_18contiguous_storageIiS2_EE .p2align 4, 0x90 .type _ZN6thrust6detail11vector_baseIiSaIiEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SA_RNS0_18contiguous_storageIiS2_EE,@function _ZN6thrust6detail11vector_baseIiSaIiEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SA_RNS0_18contiguous_storageIiS2_EE: # @_ZN6thrust6detail11vector_baseIiSaIiEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SA_RNS0_18contiguous_storageIiS2_EE .Lfunc_begin13: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception13 # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $16, %rsp .cfi_def_cfa_offset 64 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %r8, %rbx testq %rsi, %rsi je .LBB52_1 # %bb.4: movq 16(%rdi), %rax addq %rax, %rax cmpq %rax, %rsi cmovaq %rsi, %rax movabsq $4611686018427387903, %r13 # imm = 0x3FFFFFFFFFFFFFFF cmpq %r13, %rax cmovbq %rax, %r13 shrq $62, %rsi jne .LBB52_5 # %bb.7: shrq $61, %rax jne .LBB52_17 # %bb.8: # %_ZN6thrust6detail16allocator_traitsISaIiEE8allocateERS2_m.exit.i movq %rcx, %r14 movq %rdx, %r15 leaq (,%r13,4), %rdi callq _Znwm leaq 8(%rbx), %r12 movq %rax, 8(%rbx) movq %r13, 16(%rbx) subq %r15, %r14 sarq $2, %r14 .Ltmp187: leaq 14(%rsp), %rdi leaq 15(%rsp), %rsi movq %r15, %rdx movq %r14, %rcx movq %rax, %r8 callq _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmPiEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE .Ltmp188: jmp .LBB52_3 .LBB52_1: cmpq $0, 16(%rbx) je .LBB52_3 # %bb.2: movq 8(%rbx), %rdi callq _ZdlPv xorps %xmm0, %xmm0 movups %xmm0, 8(%rbx) .LBB52_3: # %_ZN6thrust6detail18contiguous_storageIiSaIiEE10deallocateEv.exit addq $16, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB52_17: .cfi_def_cfa_offset 64 callq _ZSt17__throw_bad_allocv .LBB52_5: movl $16, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp196: movl $.L.str.19, %esi movq %rax, %rdi callq _ZNSt12length_errorC1EPKc .Ltmp197: # %bb.6: movl $_ZTISt12length_error, %esi movl $_ZNSt12length_errorD1Ev, %edx movq %rbx, %rdi callq __cxa_throw .LBB52_13: .Ltmp198: movq %rax, %r14 movq %rbx, %rdi callq __cxa_free_exception movq %r14, %rdi callq _Unwind_Resume@PLT .LBB52_9: .Ltmp189: movq %rax, %rdi callq __cxa_begin_catch cmpq $0, 16(%rbx) je .LBB52_11 # %bb.10: movq (%r12), %rdi callq _ZdlPv xorps %xmm0, %xmm0 movups %xmm0, (%r12) .LBB52_11: # %_ZN6thrust6detail18contiguous_storageIiSaIiEE10deallocateEv.exit24 .Ltmp190: callq __cxa_rethrow .Ltmp191: # %bb.16: .LBB52_12: .Ltmp192: movq %rax, %r14 .Ltmp193: callq __cxa_end_catch .Ltmp194: # %bb.14: movq %r14, %rdi callq _Unwind_Resume@PLT .LBB52_15: .Ltmp195: movq %rax, %rdi callq __clang_call_terminate .Lfunc_end52: .size _ZN6thrust6detail11vector_baseIiSaIiEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SA_RNS0_18contiguous_storageIiS2_EE, .Lfunc_end52-_ZN6thrust6detail11vector_baseIiSaIiEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SA_RNS0_18contiguous_storageIiS2_EE .cfi_endproc .section .gcc_except_table._ZN6thrust6detail11vector_baseIiSaIiEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SA_RNS0_18contiguous_storageIiS2_EE,"aG",@progbits,_ZN6thrust6detail11vector_baseIiSaIiEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SA_RNS0_18contiguous_storageIiS2_EE,comdat .p2align 2, 0x0 GCC_except_table52: .Lexception13: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase5-.Lttbaseref5 .Lttbaseref5: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end13-.Lcst_begin13 .Lcst_begin13: .uleb128 .Lfunc_begin13-.Lfunc_begin13 # >> Call Site 1 << .uleb128 .Ltmp187-.Lfunc_begin13 # Call between .Lfunc_begin13 and .Ltmp187 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp187-.Lfunc_begin13 # >> Call Site 2 << .uleb128 .Ltmp188-.Ltmp187 # Call between .Ltmp187 and .Ltmp188 .uleb128 .Ltmp189-.Lfunc_begin13 # jumps to .Ltmp189 .byte 1 # On action: 1 .uleb128 .Ltmp188-.Lfunc_begin13 # >> Call Site 3 << .uleb128 .Ltmp196-.Ltmp188 # Call between .Ltmp188 and .Ltmp196 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp196-.Lfunc_begin13 # >> Call Site 4 << .uleb128 .Ltmp197-.Ltmp196 # Call between .Ltmp196 and .Ltmp197 .uleb128 .Ltmp198-.Lfunc_begin13 # jumps to .Ltmp198 .byte 0 # On action: cleanup .uleb128 .Ltmp197-.Lfunc_begin13 # >> Call Site 5 << .uleb128 .Ltmp190-.Ltmp197 # Call between .Ltmp197 and .Ltmp190 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp190-.Lfunc_begin13 # >> Call Site 6 << .uleb128 .Ltmp191-.Ltmp190 # Call between .Ltmp190 and .Ltmp191 .uleb128 .Ltmp192-.Lfunc_begin13 # jumps to .Ltmp192 .byte 0 # On action: cleanup .uleb128 .Ltmp193-.Lfunc_begin13 # >> Call Site 7 << .uleb128 .Ltmp194-.Ltmp193 # Call between .Ltmp193 and .Ltmp194 .uleb128 .Ltmp195-.Lfunc_begin13 # jumps to .Ltmp195 .byte 1 # On action: 1 .uleb128 .Ltmp194-.Lfunc_begin13 # >> Call Site 8 << .uleb128 .Lfunc_end52-.Ltmp194 # Call between .Ltmp194 and .Lfunc_end52 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end13: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase5: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmNS9_IPiEEEET3_RNS_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_NS8_17integral_constantIbLb1EEE,"axG",@progbits,_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmNS9_IPiEEEET3_RNS_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_NS8_17integral_constantIbLb1EEE,comdat .weak _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmNS9_IPiEEEET3_RNS_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_NS8_17integral_constantIbLb1EEE # -- Begin function _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmNS9_IPiEEEET3_RNS_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_NS8_17integral_constantIbLb1EEE .p2align 4, 0x90 .type _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmNS9_IPiEEEET3_RNS_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_NS8_17integral_constantIbLb1EEE,@function _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmNS9_IPiEEEET3_RNS_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_NS8_17integral_constantIbLb1EEE: # @_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmNS9_IPiEEEET3_RNS_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_NS8_17integral_constantIbLb1EEE .Lfunc_begin14: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception14 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movq %r8, %rbx movq %rcx, %r14 testq %rcx, %rcx je .LBB53_6 # %bb.1: # %_ZN6thrust11hip_rocprim24trivial_copy_from_deviceIiEE10hipError_tPT_PKS3_mP12ihipStream_t.exit.i leaq (,%r14,4), %rax movq %rbx, %rdi movq %rdx, %rsi movq %rax, %rdx movl $2, %ecx xorl %r8d, %r8d callq hipMemcpyWithStream movl %eax, %ebp callq hipGetLastError testl %ebp, %ebp jne .LBB53_2 .LBB53_6: # %_ZN6thrust11hip_rocprim6__copy19trivial_device_copyINS0_3tagENS_6system3cpp6detail3tagEimEEvRNS0_16execution_policyIT_EERNS6_16execution_policyIT0_EEPT1_PKSG_T2_.exit leaq (%rbx,%r14,4), %rax popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB53_2: .cfi_def_cfa_offset 32 movl $64, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp199: callq _ZN6thrust6system12hip_categoryEv .Ltmp200: # %bb.3: .Ltmp201: movl $.L.str.24, %ecx movq %rbx, %rdi movl %ebp, %esi movq %rax, %rdx callq _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc .Ltmp202: # %bb.4: movl $_ZTIN6thrust6system12system_errorE, %esi movl $_ZN6thrust6system12system_errorD2Ev, %edx movq %rbx, %rdi callq __cxa_throw .LBB53_5: .Ltmp203: movq %rax, %r14 movq %rbx, %rdi callq __cxa_free_exception movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end53: .size _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmNS9_IPiEEEET3_RNS_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_NS8_17integral_constantIbLb1EEE, .Lfunc_end53-_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmNS9_IPiEEEET3_RNS_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_NS8_17integral_constantIbLb1EEE .cfi_endproc .section .gcc_except_table._ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmNS9_IPiEEEET3_RNS_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_NS8_17integral_constantIbLb1EEE,"aG",@progbits,_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmNS9_IPiEEEET3_RNS_16execution_policyIT_EERNSH_IT0_EET1_T2_SG_NS8_17integral_constantIbLb1EEE,comdat .p2align 2, 0x0 GCC_except_table53: .Lexception14: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end14-.Lcst_begin14 .Lcst_begin14: .uleb128 .Lfunc_begin14-.Lfunc_begin14 # >> Call Site 1 << .uleb128 .Ltmp199-.Lfunc_begin14 # Call between .Lfunc_begin14 and .Ltmp199 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp199-.Lfunc_begin14 # >> Call Site 2 << .uleb128 .Ltmp202-.Ltmp199 # Call between .Ltmp199 and .Ltmp202 .uleb128 .Ltmp203-.Lfunc_begin14 # jumps to .Ltmp203 .byte 0 # On action: cleanup .uleb128 .Ltmp202-.Lfunc_begin14 # >> Call Site 3 << .uleb128 .Lfunc_end53-.Ltmp202 # Call between .Ltmp202 and .Lfunc_end53 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end14: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmPiEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,"axG",@progbits,_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmPiEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,comdat .weak _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmPiEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE # -- Begin function _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmPiEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE .p2align 4, 0x90 .type _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmPiEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,@function _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmPiEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE: # @_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmPiEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE .Lfunc_begin15: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception15 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movq %r8, %rbx movq %rcx, %r14 testq %rcx, %rcx je .LBB54_6 # %bb.1: # %_ZN6thrust11hip_rocprim24trivial_copy_from_deviceIiEE10hipError_tPT_PKS3_mP12ihipStream_t.exit.i leaq (,%r14,4), %rax movq %rbx, %rdi movq %rdx, %rsi movq %rax, %rdx movl $2, %ecx xorl %r8d, %r8d callq hipMemcpyWithStream movl %eax, %ebp callq hipGetLastError testl %ebp, %ebp jne .LBB54_2 .LBB54_6: # %_ZN6thrust11hip_rocprim6__copy19trivial_device_copyINS0_3tagENS_6system3cpp6detail3tagEimEEvRNS0_16execution_policyIT_EERNS6_16execution_policyIT0_EEPT1_PKSG_T2_.exit leaq (%rbx,%r14,4), %rax popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB54_2: .cfi_def_cfa_offset 32 movl $64, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp204: callq _ZN6thrust6system12hip_categoryEv .Ltmp205: # %bb.3: .Ltmp206: movl $.L.str.24, %ecx movq %rbx, %rdi movl %ebp, %esi movq %rax, %rdx callq _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc .Ltmp207: # %bb.4: movl $_ZTIN6thrust6system12system_errorE, %esi movl $_ZN6thrust6system12system_errorD2Ev, %edx movq %rbx, %rdi callq __cxa_throw .LBB54_5: .Ltmp208: movq %rax, %r14 movq %rbx, %rdi callq __cxa_free_exception movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end54: .size _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmPiEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE, .Lfunc_end54-_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmPiEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE .cfi_endproc .section .gcc_except_table._ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmPiEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,"aG",@progbits,_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEEmPiEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,comdat .p2align 2, 0x0 GCC_except_table54: .Lexception15: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end15-.Lcst_begin15 .Lcst_begin15: .uleb128 .Lfunc_begin15-.Lfunc_begin15 # >> Call Site 1 << .uleb128 .Ltmp204-.Lfunc_begin15 # Call between .Lfunc_begin15 and .Ltmp204 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp204-.Lfunc_begin15 # >> Call Site 2 << .uleb128 .Ltmp207-.Ltmp204 # Call between .Ltmp204 and .Ltmp207 .uleb128 .Ltmp208-.Lfunc_begin15 # jumps to .Ltmp208 .byte 0 # On action: cleanup .uleb128 .Ltmp207-.Lfunc_begin15 # >> Call Site 3 << .uleb128 .Lfunc_end54-.Ltmp207 # Call between .Ltmp207 and .Lfunc_end54 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end15: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6detail8dispatch15overlapped_copyINS_11hip_rocprim3tagENS0_15normal_iteratorINS_10device_ptrIiEEEES8_EET1_RNS_16execution_policyIT_EET0_SE_S9_,"axG",@progbits,_ZN6thrust6detail8dispatch15overlapped_copyINS_11hip_rocprim3tagENS0_15normal_iteratorINS_10device_ptrIiEEEES8_EET1_RNS_16execution_policyIT_EET0_SE_S9_,comdat .weak _ZN6thrust6detail8dispatch15overlapped_copyINS_11hip_rocprim3tagENS0_15normal_iteratorINS_10device_ptrIiEEEES8_EET1_RNS_16execution_policyIT_EET0_SE_S9_ # -- Begin function _ZN6thrust6detail8dispatch15overlapped_copyINS_11hip_rocprim3tagENS0_15normal_iteratorINS_10device_ptrIiEEEES8_EET1_RNS_16execution_policyIT_EET0_SE_S9_ .p2align 4, 0x90 .type _ZN6thrust6detail8dispatch15overlapped_copyINS_11hip_rocprim3tagENS0_15normal_iteratorINS_10device_ptrIiEEEES8_EET1_RNS_16execution_policyIT_EET0_SE_S9_,@function _ZN6thrust6detail8dispatch15overlapped_copyINS_11hip_rocprim3tagENS0_15normal_iteratorINS_10device_ptrIiEEEES8_EET1_RNS_16execution_policyIT_EET0_SE_S9_: # @_ZN6thrust6detail8dispatch15overlapped_copyINS_11hip_rocprim3tagENS0_15normal_iteratorINS_10device_ptrIiEEEES8_EET1_RNS_16execution_policyIT_EET0_SE_S9_ .Lfunc_begin16: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception16 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rcx, %rbx movq %rdx, %r15 movq %rsi, %r12 movq %rdi, %r14 movq %rdx, %r13 movq %rdi, (%rsp) leaq 8(%rsp), %rbp xorps %xmm0, %xmm0 movups %xmm0, 8(%rsp) subq %rsi, %r13 je .LBB55_3 # %bb.1: .Ltmp209: sarq $2, %r13 movq %rsp, %rdi movq %r13, %rsi callq _ZN6thrust6detail19temporary_allocatorIiNS_11hip_rocprim3tagEE8allocateEm .Ltmp210: # %bb.2: # %.noexc.i movq %rax, 8(%rsp) movq %r13, 16(%rsp) jmp .LBB55_4 .LBB55_3: movups %xmm0, (%rbp) .LBB55_4: # %_ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEE8allocateEm.exit.i movq 8(%rsp), %rcx .Ltmp211: movq %r14, %rdi movq %r12, %rsi movq %r15, %rdx callq _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiS2_NS_11use_defaultES9_EEEET1_RNS0_16execution_policyIT_EET0_SG_SB_EN10workaround3parERNSC_IS2_EES7_S7_SA_ .Ltmp212: # %bb.5: # %_ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEEC2INS0_15normal_iteratorINS_10device_ptrIiEEEEEERNS_16execution_policyIS3_EET_SD_.exit movq 8(%rsp), %rsi movq 16(%rsp), %rax leaq (%rsi,%rax,4), %rdx .Ltmp214: movq %r14, %rdi movq %rbx, %rcx callq _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_7pointerIiS2_NS_11use_defaultES6_EEEENS4_INS_10device_ptrIiEEEEEET1_RNS0_16execution_policyIT_EET0_SH_SC_EN10workaround3parERNSD_IS2_EES8_S8_SB_ .Ltmp215: # %bb.6: # %_ZN6thrust4copyINS_11hip_rocprim3tagENS_6detail15normal_iteratorINS_7pointerIiS2_NS_11use_defaultES6_EEEENS4_INS_10device_ptrIiEEEEEET1_RKNS3_21execution_policy_baseIT_EET0_SI_SC_.exit cmpq $0, 16(%rsp) je .LBB55_12 # %bb.7: movq %rax, %rbx movq (%rsp), %rdi movq 8(%rsp), %rsi .Ltmp217: callq _ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_ .Ltmp218: .LBB55_11: # %_ZN6thrust6detail16allocator_traitsINS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEE10deallocateERS7_NS_7pointerIiS5_NS_11use_defaultESB_EEm.exit.i.i.i xorps %xmm0, %xmm0 movups %xmm0, (%rbp) movq %rbx, %rax .LBB55_12: # %_ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEED2Ev.exit addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB55_10: .cfi_def_cfa_offset 80 .Ltmp219: movq %rax, %rdi callq __cxa_begin_catch .Ltmp220: callq __cxa_end_catch .Ltmp221: jmp .LBB55_11 .LBB55_14: .Ltmp222: movq %rax, %rdi callq __clang_call_terminate .LBB55_13: .Ltmp216: movq %rax, %rbx movq %rsp, %rdi callq _ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEED2Ev movq %rbx, %rdi callq _Unwind_Resume@PLT .LBB55_8: .Ltmp213: movq %rax, %rbx movq %rsp, %rdi callq _ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEED2Ev movq %rbx, %rdi callq _Unwind_Resume@PLT .Lfunc_end55: .size _ZN6thrust6detail8dispatch15overlapped_copyINS_11hip_rocprim3tagENS0_15normal_iteratorINS_10device_ptrIiEEEES8_EET1_RNS_16execution_policyIT_EET0_SE_S9_, .Lfunc_end55-_ZN6thrust6detail8dispatch15overlapped_copyINS_11hip_rocprim3tagENS0_15normal_iteratorINS_10device_ptrIiEEEES8_EET1_RNS_16execution_policyIT_EET0_SE_S9_ .cfi_endproc .section .gcc_except_table._ZN6thrust6detail8dispatch15overlapped_copyINS_11hip_rocprim3tagENS0_15normal_iteratorINS_10device_ptrIiEEEES8_EET1_RNS_16execution_policyIT_EET0_SE_S9_,"aG",@progbits,_ZN6thrust6detail8dispatch15overlapped_copyINS_11hip_rocprim3tagENS0_15normal_iteratorINS_10device_ptrIiEEEES8_EET1_RNS_16execution_policyIT_EET0_SE_S9_,comdat .p2align 2, 0x0 GCC_except_table55: .Lexception16: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase6-.Lttbaseref6 .Lttbaseref6: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end16-.Lcst_begin16 .Lcst_begin16: .uleb128 .Ltmp209-.Lfunc_begin16 # >> Call Site 1 << .uleb128 .Ltmp212-.Ltmp209 # Call between .Ltmp209 and .Ltmp212 .uleb128 .Ltmp213-.Lfunc_begin16 # jumps to .Ltmp213 .byte 0 # On action: cleanup .uleb128 .Ltmp214-.Lfunc_begin16 # >> Call Site 2 << .uleb128 .Ltmp215-.Ltmp214 # Call between .Ltmp214 and .Ltmp215 .uleb128 .Ltmp216-.Lfunc_begin16 # jumps to .Ltmp216 .byte 0 # On action: cleanup .uleb128 .Ltmp217-.Lfunc_begin16 # >> Call Site 3 << .uleb128 .Ltmp218-.Ltmp217 # Call between .Ltmp217 and .Ltmp218 .uleb128 .Ltmp219-.Lfunc_begin16 # jumps to .Ltmp219 .byte 1 # On action: 1 .uleb128 .Ltmp218-.Lfunc_begin16 # >> Call Site 4 << .uleb128 .Ltmp220-.Ltmp218 # Call between .Ltmp218 and .Ltmp220 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp220-.Lfunc_begin16 # >> Call Site 5 << .uleb128 .Ltmp221-.Ltmp220 # Call between .Ltmp220 and .Ltmp221 .uleb128 .Ltmp222-.Lfunc_begin16 # jumps to .Ltmp222 .byte 1 # On action: 1 .uleb128 .Ltmp221-.Lfunc_begin16 # >> Call Site 6 << .uleb128 .Lfunc_end55-.Ltmp221 # Call between .Ltmp221 and .Lfunc_end55 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end16: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase6: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEED2Ev,"axG",@progbits,_ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEED2Ev,comdat .weak _ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEED2Ev # -- Begin function _ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEED2Ev .p2align 4, 0x90 .type _ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEED2Ev,@function _ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEED2Ev: # @_ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEED2Ev .Lfunc_begin17: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception17 # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 cmpq $0, 16(%rdi) je .LBB56_3 # %bb.1: movq %rdi, %rbx movq (%rdi), %rdi movq 8(%rbx), %rsi .Ltmp223: callq _ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_ .Ltmp224: .LBB56_2: # %_ZN6thrust6detail16allocator_traitsINS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEE10deallocateERS7_NS_7pointerIiS5_NS_11use_defaultESB_EEm.exit.i.i addq $8, %rbx xorps %xmm0, %xmm0 movups %xmm0, (%rbx) .LBB56_3: # %_ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEED2Ev.exit popq %rbx .cfi_def_cfa_offset 8 retq .LBB56_4: .cfi_def_cfa_offset 16 .Ltmp225: movq %rax, %rdi callq __cxa_begin_catch .Ltmp226: callq __cxa_end_catch .Ltmp227: jmp .LBB56_2 .LBB56_5: .Ltmp228: movq %rax, %rdi callq __clang_call_terminate .Lfunc_end56: .size _ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEED2Ev, .Lfunc_end56-_ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEED2Ev .cfi_endproc .section .gcc_except_table._ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEED2Ev,"aG",@progbits,_ZN6thrust6detail15temporary_arrayIiNS_11hip_rocprim3tagEED2Ev,comdat .p2align 2, 0x0 GCC_except_table56: .Lexception17: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase7-.Lttbaseref7 .Lttbaseref7: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end17-.Lcst_begin17 .Lcst_begin17: .uleb128 .Ltmp223-.Lfunc_begin17 # >> Call Site 1 << .uleb128 .Ltmp224-.Ltmp223 # Call between .Ltmp223 and .Ltmp224 .uleb128 .Ltmp225-.Lfunc_begin17 # jumps to .Ltmp225 .byte 1 # On action: 1 .uleb128 .Ltmp224-.Lfunc_begin17 # >> Call Site 2 << .uleb128 .Ltmp226-.Ltmp224 # Call between .Ltmp224 and .Ltmp226 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp226-.Lfunc_begin17 # >> Call Site 3 << .uleb128 .Ltmp227-.Ltmp226 # Call between .Ltmp226 and .Ltmp227 .uleb128 .Ltmp228-.Lfunc_begin17 # jumps to .Ltmp228 .byte 1 # On action: 1 .Lcst_end17: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase7: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEED2Ev,"axG",@progbits,_ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEED2Ev,comdat .weak _ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEED2Ev # -- Begin function _ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEED2Ev .p2align 4, 0x90 .type _ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEED2Ev,@function _ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEED2Ev: # @_ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEED2Ev .Lfunc_begin18: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception18 # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 cmpq $0, 16(%rdi) je .LBB57_4 # %bb.1: movq %rdi, %rbx movq (%rdi), %rdi movq 8(%rbx), %rsi .Ltmp229: callq _ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_ .Ltmp230: .LBB57_3: # %_ZN6thrust6detail16allocator_traitsINS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEE10deallocateERS7_NS_7pointerIiS5_NS_11use_defaultESB_EEm.exit.i addq $8, %rbx xorps %xmm0, %xmm0 movups %xmm0, (%rbx) .LBB57_4: # %_ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEE10deallocateEv.exit popq %rbx .cfi_def_cfa_offset 8 retq .LBB57_2: .cfi_def_cfa_offset 16 .Ltmp231: movq %rax, %rdi callq __cxa_begin_catch .Ltmp232: callq __cxa_end_catch .Ltmp233: jmp .LBB57_3 .LBB57_5: .Ltmp234: movq %rax, %rdi callq __clang_call_terminate .Lfunc_end57: .size _ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEED2Ev, .Lfunc_end57-_ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEED2Ev .cfi_endproc .section .gcc_except_table._ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEED2Ev,"aG",@progbits,_ZN6thrust6detail18contiguous_storageIiNS0_18no_throw_allocatorINS0_19temporary_allocatorIiNS_11hip_rocprim3tagEEEEEED2Ev,comdat .p2align 2, 0x0 GCC_except_table57: .Lexception18: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase8-.Lttbaseref8 .Lttbaseref8: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end18-.Lcst_begin18 .Lcst_begin18: .uleb128 .Ltmp229-.Lfunc_begin18 # >> Call Site 1 << .uleb128 .Ltmp230-.Ltmp229 # Call between .Ltmp229 and .Ltmp230 .uleb128 .Ltmp231-.Lfunc_begin18 # jumps to .Ltmp231 .byte 1 # On action: 1 .uleb128 .Ltmp230-.Lfunc_begin18 # >> Call Site 2 << .uleb128 .Ltmp232-.Ltmp230 # Call between .Ltmp230 and .Ltmp232 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp232-.Lfunc_begin18 # >> Call Site 3 << .uleb128 .Ltmp233-.Ltmp232 # Call between .Ltmp232 and .Ltmp233 .uleb128 .Ltmp234-.Lfunc_begin18 # jumps to .Ltmp234 .byte 1 # On action: 1 .Lcst_end18: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase8: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6detail19temporary_allocatorIiNS_11hip_rocprim3tagEE8allocateEm,"axG",@progbits,_ZN6thrust6detail19temporary_allocatorIiNS_11hip_rocprim3tagEE8allocateEm,comdat .weak _ZN6thrust6detail19temporary_allocatorIiNS_11hip_rocprim3tagEE8allocateEm # -- Begin function _ZN6thrust6detail19temporary_allocatorIiNS_11hip_rocprim3tagEE8allocateEm .p2align 4, 0x90 .type _ZN6thrust6detail19temporary_allocatorIiNS_11hip_rocprim3tagEE8allocateEm,@function _ZN6thrust6detail19temporary_allocatorIiNS_11hip_rocprim3tagEE8allocateEm: # @_ZN6thrust6detail19temporary_allocatorIiNS_11hip_rocprim3tagEE8allocateEm .Lfunc_begin19: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception19 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $48, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movq %rsi, %r14 movq %rdi, %rbx movq (%rdi), %rdi leaq (,%rsi,4), %rsi callq _ZN6thrust11hip_rocprim6mallocINS0_3tagEEEPvRNS0_16execution_policyIT_EEm testq %r14, %r14 je .LBB58_11 # %bb.1: testq %rax, %rax je .LBB58_2 .LBB58_11: addq $48, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB58_2: .cfi_def_cfa_offset 80 movq (%rbx), %rdi movq %rax, %rsi callq _ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_ movl $40, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp235: leaq 16(%rsp), %rdi leaq 15(%rsp), %rdx movl $.L.str.25, %esi callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .Ltmp236: # %bb.3: movb $1, %bpl .Ltmp238: leaq 16(%rsp), %rsi movq %rbx, %rdi callq _ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .Ltmp239: # %bb.4: xorl %ebp, %ebp .Ltmp240: movl $_ZTIN6thrust6system6detail9bad_allocE, %esi movl $_ZN6thrust6system6detail9bad_allocD2Ev, %edx movq %rbx, %rdi callq __cxa_throw .Ltmp241: # %bb.12: .LBB58_6: .Ltmp242: movq %rax, %r14 movq 16(%rsp), %rdi leaq 32(%rsp), %rax cmpq %rax, %rdi jne .LBB58_7 # %bb.8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit testb %bpl, %bpl jne .LBB58_9 .LBB58_10: movq %r14, %rdi callq _Unwind_Resume@PLT .LBB58_7: # %.critedge.i.i callq _ZdlPv testb %bpl, %bpl je .LBB58_10 jmp .LBB58_9 .LBB58_5: .Ltmp237: movq %rax, %r14 movb $1, %bpl testb %bpl, %bpl je .LBB58_10 .LBB58_9: movq %rbx, %rdi callq __cxa_free_exception movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end58: .size _ZN6thrust6detail19temporary_allocatorIiNS_11hip_rocprim3tagEE8allocateEm, .Lfunc_end58-_ZN6thrust6detail19temporary_allocatorIiNS_11hip_rocprim3tagEE8allocateEm .cfi_endproc .section .gcc_except_table._ZN6thrust6detail19temporary_allocatorIiNS_11hip_rocprim3tagEE8allocateEm,"aG",@progbits,_ZN6thrust6detail19temporary_allocatorIiNS_11hip_rocprim3tagEE8allocateEm,comdat .p2align 2, 0x0 GCC_except_table58: .Lexception19: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end19-.Lcst_begin19 .Lcst_begin19: .uleb128 .Lfunc_begin19-.Lfunc_begin19 # >> Call Site 1 << .uleb128 .Ltmp235-.Lfunc_begin19 # Call between .Lfunc_begin19 and .Ltmp235 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp235-.Lfunc_begin19 # >> Call Site 2 << .uleb128 .Ltmp236-.Ltmp235 # Call between .Ltmp235 and .Ltmp236 .uleb128 .Ltmp237-.Lfunc_begin19 # jumps to .Ltmp237 .byte 0 # On action: cleanup .uleb128 .Ltmp238-.Lfunc_begin19 # >> Call Site 3 << .uleb128 .Ltmp241-.Ltmp238 # Call between .Ltmp238 and .Ltmp241 .uleb128 .Ltmp242-.Lfunc_begin19 # jumps to .Ltmp242 .byte 0 # On action: cleanup .uleb128 .Ltmp241-.Lfunc_begin19 # >> Call Site 4 << .uleb128 .Lfunc_end58-.Ltmp241 # Call between .Ltmp241 and .Lfunc_end58 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end19: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust11hip_rocprim6mallocINS0_3tagEEEPvRNS0_16execution_policyIT_EEm,"axG",@progbits,_ZN6thrust11hip_rocprim6mallocINS0_3tagEEEPvRNS0_16execution_policyIT_EEm,comdat .weak _ZN6thrust11hip_rocprim6mallocINS0_3tagEEEPvRNS0_16execution_policyIT_EEm # -- Begin function _ZN6thrust11hip_rocprim6mallocINS0_3tagEEEPvRNS0_16execution_policyIT_EEm .p2align 4, 0x90 .type _ZN6thrust11hip_rocprim6mallocINS0_3tagEEEPvRNS0_16execution_policyIT_EEm,@function _ZN6thrust11hip_rocprim6mallocINS0_3tagEEEPvRNS0_16execution_policyIT_EEm: # @_ZN6thrust11hip_rocprim6mallocINS0_3tagEEEPvRNS0_16execution_policyIT_EEm .Lfunc_begin20: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception20 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $80, %rsp .cfi_def_cfa_offset 112 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movq $0, 8(%rsp) leaq 8(%rsp), %rdi callq hipMalloc testl %eax, %eax jne .LBB59_1 # %bb.15: movq 8(%rsp), %rax addq $80, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB59_1: .cfi_def_cfa_offset 112 movl %eax, %ebp callq hipGetLastError movl $40, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp243: callq _ZN6thrust6system12hip_categoryEv .Ltmp244: # %bb.2: movq (%rax), %rcx .Ltmp245: leaq 16(%rsp), %rdi movq %rax, %rsi movl %ebp, %edx callq *48(%rcx) .Ltmp246: # %bb.3: movq 16(%rsp), %rsi .Ltmp248: leaq 48(%rsp), %rdi leaq 7(%rsp), %rdx callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .Ltmp249: # %bb.4: movb $1, %bpl .Ltmp251: leaq 48(%rsp), %rsi movq %rbx, %rdi callq _ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE .Ltmp252: # %bb.5: xorl %ebp, %ebp .Ltmp253: movl $_ZTIN6thrust6system6detail9bad_allocE, %esi movl $_ZN6thrust6system6detail9bad_allocD2Ev, %edx movq %rbx, %rdi callq __cxa_throw .Ltmp254: # %bb.16: .LBB59_8: .Ltmp255: movq %rax, %r14 movq 48(%rsp), %rdi leaq 64(%rsp), %rax cmpq %rax, %rdi je .LBB59_10 # %bb.9: # %.critedge.i.i callq _ZdlPv jmp .LBB59_10 .LBB59_7: .Ltmp250: movq %rax, %r14 movb $1, %bpl .LBB59_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit movq 16(%rsp), %rdi leaq 32(%rsp), %rax cmpq %rax, %rdi jne .LBB59_11 # %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit14 testb %bpl, %bpl jne .LBB59_13 .LBB59_14: movq %r14, %rdi callq _Unwind_Resume@PLT .LBB59_11: # %.critedge.i.i12 callq _ZdlPv testb %bpl, %bpl je .LBB59_14 jmp .LBB59_13 .LBB59_6: .Ltmp247: movq %rax, %r14 movb $1, %bpl testb %bpl, %bpl je .LBB59_14 .LBB59_13: movq %rbx, %rdi callq __cxa_free_exception movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end59: .size _ZN6thrust11hip_rocprim6mallocINS0_3tagEEEPvRNS0_16execution_policyIT_EEm, .Lfunc_end59-_ZN6thrust11hip_rocprim6mallocINS0_3tagEEEPvRNS0_16execution_policyIT_EEm .cfi_endproc .section .gcc_except_table._ZN6thrust11hip_rocprim6mallocINS0_3tagEEEPvRNS0_16execution_policyIT_EEm,"aG",@progbits,_ZN6thrust11hip_rocprim6mallocINS0_3tagEEEPvRNS0_16execution_policyIT_EEm,comdat .p2align 2, 0x0 GCC_except_table59: .Lexception20: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end20-.Lcst_begin20 .Lcst_begin20: .uleb128 .Lfunc_begin20-.Lfunc_begin20 # >> Call Site 1 << .uleb128 .Ltmp243-.Lfunc_begin20 # Call between .Lfunc_begin20 and .Ltmp243 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp243-.Lfunc_begin20 # >> Call Site 2 << .uleb128 .Ltmp246-.Ltmp243 # Call between .Ltmp243 and .Ltmp246 .uleb128 .Ltmp247-.Lfunc_begin20 # jumps to .Ltmp247 .byte 0 # On action: cleanup .uleb128 .Ltmp248-.Lfunc_begin20 # >> Call Site 3 << .uleb128 .Ltmp249-.Ltmp248 # Call between .Ltmp248 and .Ltmp249 .uleb128 .Ltmp250-.Lfunc_begin20 # jumps to .Ltmp250 .byte 0 # On action: cleanup .uleb128 .Ltmp251-.Lfunc_begin20 # >> Call Site 4 << .uleb128 .Ltmp254-.Ltmp251 # Call between .Ltmp251 and .Ltmp254 .uleb128 .Ltmp255-.Lfunc_begin20 # jumps to .Ltmp255 .byte 0 # On action: cleanup .uleb128 .Ltmp254-.Lfunc_begin20 # >> Call Site 5 << .uleb128 .Lfunc_end59-.Ltmp254 # Call between .Ltmp254 and .Lfunc_end59 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end20: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_,"axG",@progbits,_ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_,comdat .weak _ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_ # -- Begin function _ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_ .p2align 4, 0x90 .type _ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_,@function _ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_: # @_ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_ .Lfunc_begin21: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception21 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movq %rsi, %rdi callq hipFree movl %eax, %ebp callq hipGetLastError testl %ebp, %ebp jne .LBB60_1 # %bb.5: # %_ZN6thrust11hip_rocprim14throw_on_errorE10hipError_tPKc.exit popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB60_1: .cfi_def_cfa_offset 32 movl $64, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp256: callq _ZN6thrust6system12hip_categoryEv .Ltmp257: # %bb.2: .Ltmp258: movl $.L.str.26, %ecx movq %rbx, %rdi movl %ebp, %esi movq %rax, %rdx callq _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc .Ltmp259: # %bb.3: movl $_ZTIN6thrust6system12system_errorE, %esi movl $_ZN6thrust6system12system_errorD2Ev, %edx movq %rbx, %rdi callq __cxa_throw .LBB60_4: .Ltmp260: movq %rax, %r14 movq %rbx, %rdi callq __cxa_free_exception movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end60: .size _ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_, .Lfunc_end60-_ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_ .cfi_endproc .section .gcc_except_table._ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_,"aG",@progbits,_ZN6thrust11hip_rocprim4freeINS0_3tagENS_7pointerIiS2_NS_11use_defaultES4_EEEEvRNS0_16execution_policyIT_EET0_,comdat .p2align 2, 0x0 GCC_except_table60: .Lexception21: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end21-.Lcst_begin21 .Lcst_begin21: .uleb128 .Lfunc_begin21-.Lfunc_begin21 # >> Call Site 1 << .uleb128 .Ltmp256-.Lfunc_begin21 # Call between .Lfunc_begin21 and .Ltmp256 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp256-.Lfunc_begin21 # >> Call Site 2 << .uleb128 .Ltmp259-.Ltmp256 # Call between .Ltmp256 and .Ltmp259 .uleb128 .Ltmp260-.Lfunc_begin21 # jumps to .Ltmp260 .byte 0 # On action: cleanup .uleb128 .Ltmp259-.Lfunc_begin21 # >> Call Site 3 << .uleb128 .Lfunc_end60-.Ltmp259 # Call between .Ltmp259 and .Lfunc_end60 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end21: .p2align 2, 0x0 # -- End function .section .text._ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiS2_NS_11use_defaultES9_EEEET1_RNS0_16execution_policyIT_EET0_SG_SB_EN10workaround3parERNSC_IS2_EES7_S7_SA_,"axG",@progbits,_ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiS2_NS_11use_defaultES9_EEEET1_RNS0_16execution_policyIT_EET0_SG_SB_EN10workaround3parERNSC_IS2_EES7_S7_SA_,comdat .weak _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiS2_NS_11use_defaultES9_EEEET1_RNS0_16execution_policyIT_EET0_SG_SB_EN10workaround3parERNSC_IS2_EES7_S7_SA_ # -- Begin function _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiS2_NS_11use_defaultES9_EEEET1_RNS0_16execution_policyIT_EET0_SG_SB_EN10workaround3parERNSC_IS2_EES7_S7_SA_ .p2align 4, 0x90 .type _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiS2_NS_11use_defaultES9_EEEET1_RNS0_16execution_policyIT_EET0_SG_SB_EN10workaround3parERNSC_IS2_EES7_S7_SA_,@function _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiS2_NS_11use_defaultES9_EEEET1_RNS0_16execution_policyIT_EET0_SG_SB_EN10workaround3parERNSC_IS2_EES7_S7_SA_: # @_ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiS2_NS_11use_defaultES9_EEEET1_RNS0_16execution_policyIT_EET0_SG_SB_EN10workaround3parERNSC_IS2_EES7_S7_SA_ .Lfunc_begin22: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception22 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movq %rcx, %rbx movq %rdx, %r14 subq %rsi, %r14 testq %r14, %r14 jle .LBB61_8 # %bb.1: movq %rbx, %rdi movq %r14, %rdx movl $3, %ecx xorl %r8d, %r8d callq hipMemcpyAsync movl %eax, %ebp testl %eax, %eax jne .LBB61_3 # %bb.2: xorl %edi, %edi callq hipStreamSynchronize movl %eax, %ebp .LBB61_3: # %_ZN6thrust11hip_rocprim29trivial_copy_device_to_deviceINS0_16execution_policyINS0_3tagEEEiEE10hipError_tRT_PT0_PKS8_m.exit.i.i callq hipGetLastError testl %ebp, %ebp jne .LBB61_4 .LBB61_8: # %_ZN6thrust11hip_rocprim6__copy16device_to_deviceINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiS3_NS_11use_defaultESA_EEEET1_RNS0_16execution_policyIT_EET0_SH_SC_.exit addq %r14, %rbx movq %rbx, %rax popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB61_4: .cfi_def_cfa_offset 32 movl $64, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp261: callq _ZN6thrust6system12hip_categoryEv .Ltmp262: # %bb.5: .Ltmp263: movl $.L.str.27, %ecx movq %rbx, %rdi movl %ebp, %esi movq %rax, %rdx callq _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc .Ltmp264: # %bb.6: movl $_ZTIN6thrust6system12system_errorE, %esi movl $_ZN6thrust6system12system_errorD2Ev, %edx movq %rbx, %rdi callq __cxa_throw .LBB61_7: .Ltmp265: movq %rax, %r14 movq %rbx, %rdi callq __cxa_free_exception movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end61: .size _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiS2_NS_11use_defaultES9_EEEET1_RNS0_16execution_policyIT_EET0_SG_SB_EN10workaround3parERNSC_IS2_EES7_S7_SA_, .Lfunc_end61-_ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiS2_NS_11use_defaultES9_EEEET1_RNS0_16execution_policyIT_EET0_SG_SB_EN10workaround3parERNSC_IS2_EES7_S7_SA_ .cfi_endproc .section .gcc_except_table._ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiS2_NS_11use_defaultES9_EEEET1_RNS0_16execution_policyIT_EET0_SG_SB_EN10workaround3parERNSC_IS2_EES7_S7_SA_,"aG",@progbits,_ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiS2_NS_11use_defaultES9_EEEET1_RNS0_16execution_policyIT_EET0_SG_SB_EN10workaround3parERNSC_IS2_EES7_S7_SA_,comdat .p2align 2, 0x0 GCC_except_table61: .Lexception22: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end22-.Lcst_begin22 .Lcst_begin22: .uleb128 .Lfunc_begin22-.Lfunc_begin22 # >> Call Site 1 << .uleb128 .Ltmp261-.Lfunc_begin22 # Call between .Lfunc_begin22 and .Ltmp261 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp261-.Lfunc_begin22 # >> Call Site 2 << .uleb128 .Ltmp264-.Ltmp261 # Call between .Ltmp261 and .Ltmp264 .uleb128 .Ltmp265-.Lfunc_begin22 # jumps to .Ltmp265 .byte 0 # On action: cleanup .uleb128 .Ltmp264-.Lfunc_begin22 # >> Call Site 3 << .uleb128 .Lfunc_end61-.Ltmp264 # Call between .Ltmp264 and .Lfunc_end61 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end22: .p2align 2, 0x0 # -- End function .section .text._ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_7pointerIiS2_NS_11use_defaultES6_EEEENS4_INS_10device_ptrIiEEEEEET1_RNS0_16execution_policyIT_EET0_SH_SC_EN10workaround3parERNSD_IS2_EES8_S8_SB_,"axG",@progbits,_ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_7pointerIiS2_NS_11use_defaultES6_EEEENS4_INS_10device_ptrIiEEEEEET1_RNS0_16execution_policyIT_EET0_SH_SC_EN10workaround3parERNSD_IS2_EES8_S8_SB_,comdat .weak _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_7pointerIiS2_NS_11use_defaultES6_EEEENS4_INS_10device_ptrIiEEEEEET1_RNS0_16execution_policyIT_EET0_SH_SC_EN10workaround3parERNSD_IS2_EES8_S8_SB_ # -- Begin function _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_7pointerIiS2_NS_11use_defaultES6_EEEENS4_INS_10device_ptrIiEEEEEET1_RNS0_16execution_policyIT_EET0_SH_SC_EN10workaround3parERNSD_IS2_EES8_S8_SB_ .p2align 4, 0x90 .type _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_7pointerIiS2_NS_11use_defaultES6_EEEENS4_INS_10device_ptrIiEEEEEET1_RNS0_16execution_policyIT_EET0_SH_SC_EN10workaround3parERNSD_IS2_EES8_S8_SB_,@function _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_7pointerIiS2_NS_11use_defaultES6_EEEENS4_INS_10device_ptrIiEEEEEET1_RNS0_16execution_policyIT_EET0_SH_SC_EN10workaround3parERNSD_IS2_EES8_S8_SB_: # @_ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_7pointerIiS2_NS_11use_defaultES6_EEEENS4_INS_10device_ptrIiEEEEEET1_RNS0_16execution_policyIT_EET0_SH_SC_EN10workaround3parERNSD_IS2_EES8_S8_SB_ .Lfunc_begin23: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception23 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movq %rcx, %rbx movq %rdx, %r14 subq %rsi, %r14 testq %r14, %r14 jle .LBB62_8 # %bb.1: movq %rbx, %rdi movq %r14, %rdx movl $3, %ecx xorl %r8d, %r8d callq hipMemcpyAsync movl %eax, %ebp testl %eax, %eax jne .LBB62_3 # %bb.2: xorl %edi, %edi callq hipStreamSynchronize movl %eax, %ebp .LBB62_3: # %_ZN6thrust11hip_rocprim29trivial_copy_device_to_deviceINS0_16execution_policyINS0_3tagEEEiEE10hipError_tRT_PT0_PKS8_m.exit.i.i callq hipGetLastError testl %ebp, %ebp jne .LBB62_4 .LBB62_8: # %_ZN6thrust11hip_rocprim6__copy16device_to_deviceINS0_3tagENS_6detail15normal_iteratorINS_7pointerIiS3_NS_11use_defaultES7_EEEENS5_INS_10device_ptrIiEEEEEET1_RNS0_16execution_policyIT_EET0_SI_SD_.exit addq %r14, %rbx movq %rbx, %rax popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB62_4: .cfi_def_cfa_offset 32 movl $64, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp266: callq _ZN6thrust6system12hip_categoryEv .Ltmp267: # %bb.5: .Ltmp268: movl $.L.str.27, %ecx movq %rbx, %rdi movl %ebp, %esi movq %rax, %rdx callq _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc .Ltmp269: # %bb.6: movl $_ZTIN6thrust6system12system_errorE, %esi movl $_ZN6thrust6system12system_errorD2Ev, %edx movq %rbx, %rdi callq __cxa_throw .LBB62_7: .Ltmp270: movq %rax, %r14 movq %rbx, %rdi callq __cxa_free_exception movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end62: .size _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_7pointerIiS2_NS_11use_defaultES6_EEEENS4_INS_10device_ptrIiEEEEEET1_RNS0_16execution_policyIT_EET0_SH_SC_EN10workaround3parERNSD_IS2_EES8_S8_SB_, .Lfunc_end62-_ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_7pointerIiS2_NS_11use_defaultES6_EEEENS4_INS_10device_ptrIiEEEEEET1_RNS0_16execution_policyIT_EET0_SH_SC_EN10workaround3parERNSD_IS2_EES8_S8_SB_ .cfi_endproc .section .gcc_except_table._ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_7pointerIiS2_NS_11use_defaultES6_EEEENS4_INS_10device_ptrIiEEEEEET1_RNS0_16execution_policyIT_EET0_SH_SC_EN10workaround3parERNSD_IS2_EES8_S8_SB_,"aG",@progbits,_ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_7pointerIiS2_NS_11use_defaultES6_EEEENS4_INS_10device_ptrIiEEEEEET1_RNS0_16execution_policyIT_EET0_SH_SC_EN10workaround3parERNSD_IS2_EES8_S8_SB_,comdat .p2align 2, 0x0 GCC_except_table62: .Lexception23: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end23-.Lcst_begin23 .Lcst_begin23: .uleb128 .Lfunc_begin23-.Lfunc_begin23 # >> Call Site 1 << .uleb128 .Ltmp266-.Lfunc_begin23 # Call between .Lfunc_begin23 and .Ltmp266 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp266-.Lfunc_begin23 # >> Call Site 2 << .uleb128 .Ltmp269-.Ltmp266 # Call between .Ltmp266 and .Ltmp269 .uleb128 .Ltmp270-.Lfunc_begin23 # jumps to .Ltmp270 .byte 0 # On action: cleanup .uleb128 .Ltmp269-.Lfunc_begin23 # >> Call Site 3 << .uleb128 .Lfunc_end62-.Ltmp269 # Call between .Ltmp269 and .Lfunc_end62 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end23: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev,"axG",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev,comdat .weak _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev # -- Begin function _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev .p2align 4, 0x90 .type _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev,@function _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev: # @_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev .Lfunc_begin24: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception24 # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq 16(%rdi), %rdx testq %rdx, %rdx je .LBB63_3 # %bb.1: movq %rdi, %rbx movq (%rdi), %rax movq 8(%rdi), %rsi shlq $2, %rdx movq 8(%rax), %rdi .Ltmp271: movl $4, %ecx callq _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm .Ltmp272: # %bb.2: # %.noexc.i addq $8, %rbx xorps %xmm0, %xmm0 movups %xmm0, (%rbx) .LBB63_3: # %_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev.exit popq %rbx .cfi_def_cfa_offset 8 retq .LBB63_4: .cfi_def_cfa_offset 16 .Ltmp273: movq %rax, %rdi callq __clang_call_terminate .Lfunc_end63: .size _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev, .Lfunc_end63-_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev .cfi_endproc .section .gcc_except_table._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev,"aG",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev,comdat .p2align 2, 0x0 GCC_except_table63: .Lexception24: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase9-.Lttbaseref9 .Lttbaseref9: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end24-.Lcst_begin24 .Lcst_begin24: .uleb128 .Ltmp271-.Lfunc_begin24 # >> Call Site 1 << .uleb128 .Ltmp272-.Ltmp271 # Call between .Ltmp271 and .Ltmp272 .uleb128 .Ltmp273-.Lfunc_begin24 # jumps to .Ltmp273 .byte 1 # On action: 1 .Lcst_end24: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase9: .p2align 2, 0x0 # -- End function .section .text._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SB_RNS0_18contiguous_storageIiS3_EE,"axG",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SB_RNS0_18contiguous_storageIiS3_EE,comdat .weak _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SB_RNS0_18contiguous_storageIiS3_EE # -- Begin function _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SB_RNS0_18contiguous_storageIiS3_EE .p2align 4, 0x90 .type _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SB_RNS0_18contiguous_storageIiS3_EE,@function _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SB_RNS0_18contiguous_storageIiS3_EE: # @_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SB_RNS0_18contiguous_storageIiS3_EE .Lfunc_begin25: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception25 # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 pushq %rax .cfi_def_cfa_offset 48 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %r8, %rbx testq %rsi, %rsi je .LBB64_1 # %bb.4: # %_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE8allocateEm.exit movq %rcx, %r14 movq %rdx, %r15 movq 16(%rdi), %r12 addq %r12, %r12 cmpq %r12, %rsi cmovaq %rsi, %r12 movq (%rbx), %rax leaq (,%r12,4), %rsi movq 8(%rax), %rdi movl $4, %edx callq _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm movq %rax, 8(%rbx) movq %r12, 16(%rbx) .Ltmp274: leaq 7(%rsp), %rdi movq %r15, %rsi movq %r14, %rdx movq %rax, %rcx callq _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEENS5_IiEEEET1_RNS0_16execution_policyIT_EET0_SF_SA_EN10workaround3parERNSB_IS2_EES8_S8_S9_ .Ltmp275: jmp .LBB64_3 .LBB64_1: movq 16(%rbx), %rdx testq %rdx, %rdx je .LBB64_3 # %bb.2: movq (%rbx), %rax movq 8(%rbx), %rsi shlq $2, %rdx movq 8(%rax), %rdi movl $4, %ecx callq _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm xorps %xmm0, %xmm0 movups %xmm0, 8(%rbx) .LBB64_3: # %_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv.exit addq $8, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB64_5: .cfi_def_cfa_offset 48 .Ltmp276: movq %rax, %rdi callq __cxa_begin_catch .Ltmp277: movq %rbx, %rdi callq _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEE10deallocateEv .Ltmp278: # %bb.6: .Ltmp279: callq __cxa_rethrow .Ltmp280: # %bb.10: .LBB64_7: .Ltmp281: movq %rax, %rbx .Ltmp282: callq __cxa_end_catch .Ltmp283: # %bb.8: movq %rbx, %rdi callq _Unwind_Resume@PLT .LBB64_9: .Ltmp284: movq %rax, %rdi callq __clang_call_terminate .Lfunc_end64: .size _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SB_RNS0_18contiguous_storageIiS3_EE, .Lfunc_end64-_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SB_RNS0_18contiguous_storageIiS3_EE .cfi_endproc .section .gcc_except_table._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SB_RNS0_18contiguous_storageIiS3_EE,"aG",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKiEEEEEEvmT_SB_RNS0_18contiguous_storageIiS3_EE,comdat .p2align 2, 0x0 GCC_except_table64: .Lexception25: .byte 255 # @LPStart Encoding = omit .byte 3 # @TType Encoding = udata4 .uleb128 .Lttbase10-.Lttbaseref10 .Lttbaseref10: .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end25-.Lcst_begin25 .Lcst_begin25: .uleb128 .Lfunc_begin25-.Lfunc_begin25 # >> Call Site 1 << .uleb128 .Ltmp274-.Lfunc_begin25 # Call between .Lfunc_begin25 and .Ltmp274 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp274-.Lfunc_begin25 # >> Call Site 2 << .uleb128 .Ltmp275-.Ltmp274 # Call between .Ltmp274 and .Ltmp275 .uleb128 .Ltmp276-.Lfunc_begin25 # jumps to .Ltmp276 .byte 1 # On action: 1 .uleb128 .Ltmp275-.Lfunc_begin25 # >> Call Site 3 << .uleb128 .Ltmp277-.Ltmp275 # Call between .Ltmp275 and .Ltmp277 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp277-.Lfunc_begin25 # >> Call Site 4 << .uleb128 .Ltmp280-.Ltmp277 # Call between .Ltmp277 and .Ltmp280 .uleb128 .Ltmp281-.Lfunc_begin25 # jumps to .Ltmp281 .byte 0 # On action: cleanup .uleb128 .Ltmp282-.Lfunc_begin25 # >> Call Site 5 << .uleb128 .Ltmp283-.Ltmp282 # Call between .Ltmp282 and .Ltmp283 .uleb128 .Ltmp284-.Lfunc_begin25 # jumps to .Ltmp284 .byte 1 # On action: 1 .uleb128 .Ltmp283-.Lfunc_begin25 # >> Call Site 6 << .uleb128 .Lfunc_end64-.Ltmp283 # Call between .Ltmp283 and .Lfunc_end64 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end25: .byte 1 # >> Action Record 1 << # Catch TypeInfo 1 .byte 0 # No further actions .p2align 2, 0x0 # >> Catch TypeInfos << .long 0 # TypeInfo 1 .Lttbase10: .p2align 2, 0x0 # -- End function .section .text._ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEENS5_IiEEEET1_RNS0_16execution_policyIT_EET0_SF_SA_EN10workaround3parERNSB_IS2_EES8_S8_S9_,"axG",@progbits,_ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEENS5_IiEEEET1_RNS0_16execution_policyIT_EET0_SF_SA_EN10workaround3parERNSB_IS2_EES8_S8_S9_,comdat .weak _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEENS5_IiEEEET1_RNS0_16execution_policyIT_EET0_SF_SA_EN10workaround3parERNSB_IS2_EES8_S8_S9_ # -- Begin function _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEENS5_IiEEEET1_RNS0_16execution_policyIT_EET0_SF_SA_EN10workaround3parERNSB_IS2_EES8_S8_S9_ .p2align 4, 0x90 .type _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEENS5_IiEEEET1_RNS0_16execution_policyIT_EET0_SF_SA_EN10workaround3parERNSB_IS2_EES8_S8_S9_,@function _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEENS5_IiEEEET1_RNS0_16execution_policyIT_EET0_SF_SA_EN10workaround3parERNSB_IS2_EES8_S8_S9_: # @_ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEENS5_IiEEEET1_RNS0_16execution_policyIT_EET0_SF_SA_EN10workaround3parERNSB_IS2_EES8_S8_S9_ .Lfunc_begin26: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception26 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movq %rcx, %rbx movq %rdx, %r14 subq %rsi, %r14 testq %r14, %r14 jle .LBB65_8 # %bb.1: movq %rbx, %rdi movq %r14, %rdx movl $3, %ecx xorl %r8d, %r8d callq hipMemcpyAsync movl %eax, %ebp testl %eax, %eax jne .LBB65_3 # %bb.2: xorl %edi, %edi callq hipStreamSynchronize movl %eax, %ebp .LBB65_3: # %_ZN6thrust11hip_rocprim29trivial_copy_device_to_deviceINS0_16execution_policyINS0_3tagEEEiEE10hipError_tRT_PT0_PKS8_m.exit.i.i callq hipGetLastError testl %ebp, %ebp jne .LBB65_4 .LBB65_8: # %_ZN6thrust11hip_rocprim6__copy16device_to_deviceINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEENS6_IiEEEET1_RNS0_16execution_policyIT_EET0_SG_SB_.exit addq %r14, %rbx movq %rbx, %rax popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB65_4: .cfi_def_cfa_offset 32 movl $64, %edi callq __cxa_allocate_exception movq %rax, %rbx .Ltmp285: callq _ZN6thrust6system12hip_categoryEv .Ltmp286: # %bb.5: .Ltmp287: movl $.L.str.27, %ecx movq %rbx, %rdi movl %ebp, %esi movq %rax, %rdx callq _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc .Ltmp288: # %bb.6: movl $_ZTIN6thrust6system12system_errorE, %esi movl $_ZN6thrust6system12system_errorD2Ev, %edx movq %rbx, %rdi callq __cxa_throw .LBB65_7: .Ltmp289: movq %rax, %r14 movq %rbx, %rdi callq __cxa_free_exception movq %r14, %rdi callq _Unwind_Resume@PLT .Lfunc_end65: .size _ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEENS5_IiEEEET1_RNS0_16execution_policyIT_EET0_SF_SA_EN10workaround3parERNSB_IS2_EES8_S8_S9_, .Lfunc_end65-_ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEENS5_IiEEEET1_RNS0_16execution_policyIT_EET0_SF_SA_EN10workaround3parERNSB_IS2_EES8_S8_S9_ .cfi_endproc .section .gcc_except_table._ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEENS5_IiEEEET1_RNS0_16execution_policyIT_EET0_SF_SA_EN10workaround3parERNSB_IS2_EES8_S8_S9_,"aG",@progbits,_ZZN6thrust11hip_rocprim4copyINS0_3tagENS_6detail15normal_iteratorINS_10device_ptrIKiEEEENS5_IiEEEET1_RNS0_16execution_policyIT_EET0_SF_SA_EN10workaround3parERNSB_IS2_EES8_S8_S9_,comdat .p2align 2, 0x0 GCC_except_table65: .Lexception26: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end26-.Lcst_begin26 .Lcst_begin26: .uleb128 .Lfunc_begin26-.Lfunc_begin26 # >> Call Site 1 << .uleb128 .Ltmp285-.Lfunc_begin26 # Call between .Lfunc_begin26 and .Ltmp285 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp285-.Lfunc_begin26 # >> Call Site 2 << .uleb128 .Ltmp288-.Ltmp285 # Call between .Ltmp285 and .Ltmp288 .uleb128 .Ltmp289-.Lfunc_begin26 # jumps to .Ltmp289 .byte 0 # On action: cleanup .uleb128 .Ltmp288-.Lfunc_begin26 # >> Call Site 3 << .uleb128 .Lfunc_end65-.Ltmp288 # Call between .Ltmp288 and .Lfunc_end65 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end26: .p2align 2, 0x0 # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB66_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB66_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7reduce0PiS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end66: .size __hip_module_ctor, .Lfunc_end66-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB67_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB67_2: retq .Lfunc_end67: .size __hip_module_dtor, .Lfunc_end67-__hip_module_dtor .cfi_endproc # -- End function .type _Z7reduce0PiS_i,@object # @_Z7reduce0PiS_i .section .rodata,"a",@progbits .globl _Z7reduce0PiS_i .p2align 3, 0x0 _Z7reduce0PiS_i: .quad _Z22__device_stub__reduce0PiS_i .size _Z7reduce0PiS_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Failed to create start event (error code %s)!\n" .size .L.str, 47 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed to create stop event (error code %s)!\n" .size .L.str.1, 46 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed to record start event (error code %s)!\n" .size .L.str.2, 47 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed to record stop event (error code %s)!\n" .size .L.str.3, 46 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Failed to synchronize on the stop event (error code %s)!\n" .size .L.str.4, 58 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Failed to get time elapsed between events (error code %s)!\n" .size .L.str.5, 60 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Wynik: " .size .L.str.6, 8 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "W czasie:" .size .L.str.7, 10 .type _ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource,@object # @_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource .section .bss._ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource,"awG",@nobits,_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource,comdat .weak _ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource .p2align 3, 0x0 _ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource: .zero 16 .size _ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, 16 .type _ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource,@object # @_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource .section .bss._ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource,"awG",@nobits,_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource,comdat .weak _ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource .p2align 3, 0x0 _ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource: .quad 0 # 0x0 .size _ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, 8 .type _ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,@object # @_ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE .section .rodata._ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,"aG",@progbits,_ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,comdat .weak _ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE .p2align 3, 0x0 _ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE: .quad 0 .quad _ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE .quad _ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev .quad _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev .quad _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm .quad _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm .quad _ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_ .size _ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE, 56 .type _ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,@object # @_ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE .section .rodata._ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,"aG",@progbits,_ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,comdat .weak _ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE _ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE: .asciz "N6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE" .size _ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE, 200 .type _ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE,@object # @_ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE .section .rodata._ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE,"aG",@progbits,_ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE,comdat .weak _ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE _ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE: .asciz "N6thrust2mr15memory_resourceINS_10device_ptrIvEEEE" .size _ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE, 51 .type _ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE,@object # @_ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE .section .rodata._ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE,"aG",@progbits,_ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE,comdat .weak _ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE .p2align 3, 0x0 _ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE: .quad _ZTVN10__cxxabiv117__class_type_infoE+16 .quad _ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE .size _ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE, 16 .type _ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,@object # @_ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE .section .rodata._ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,"aG",@progbits,_ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,comdat .weak _ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE .p2align 3, 0x0 _ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE .quad _ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE .size _ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE, 24 .type _ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource,@object # @_ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource .section .data._ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource,"awG",@progbits,_ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource,comdat .weak _ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource .p2align 3, 0x0 _ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource: .quad _ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE+16 .size _ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource, 8 .type _ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE,@object # @_ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE .section .rodata._ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE,"aG",@progbits,_ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE,comdat .weak _ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE .p2align 3, 0x0 _ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE: .quad 0 .quad _ZTIN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE .quad _ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev .quad _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev .quad _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm .quad _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm .quad _ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_ .size _ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE, 56 .type _ZTSN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE,@object # @_ZTSN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE .section .rodata._ZTSN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE,"aG",@progbits,_ZTSN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE,comdat .weak _ZTSN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE _ZTSN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE: .asciz "N6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE" .size _ZTSN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE, 166 .type _ZTSN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE,@object # @_ZTSN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE .section .rodata._ZTSN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE,"aG",@progbits,_ZTSN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE,comdat .weak _ZTSN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE _ZTSN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE: .asciz "N6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE" .size _ZTSN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE, 113 .type _ZTIN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE,@object # @_ZTIN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE .section .rodata._ZTIN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE,"aG",@progbits,_ZTIN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE,comdat .weak _ZTIN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE .p2align 3, 0x0 _ZTIN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE: .quad _ZTVN10__cxxabiv117__class_type_infoE+16 .quad _ZTSN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE .size _ZTIN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE, 16 .type _ZTIN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE,@object # @_ZTIN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE .section .rodata._ZTIN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE,"aG",@progbits,_ZTIN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE,comdat .weak _ZTIN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE .p2align 3, 0x0 _ZTIN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE .quad _ZTIN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE .size _ZTIN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE, 24 .type _ZTSN6thrust6system6detail9bad_allocE,@object # @_ZTSN6thrust6system6detail9bad_allocE .section .rodata._ZTSN6thrust6system6detail9bad_allocE,"aG",@progbits,_ZTSN6thrust6system6detail9bad_allocE,comdat .weak _ZTSN6thrust6system6detail9bad_allocE _ZTSN6thrust6system6detail9bad_allocE: .asciz "N6thrust6system6detail9bad_allocE" .size _ZTSN6thrust6system6detail9bad_allocE, 34 .type _ZTIN6thrust6system6detail9bad_allocE,@object # @_ZTIN6thrust6system6detail9bad_allocE .section .rodata._ZTIN6thrust6system6detail9bad_allocE,"aG",@progbits,_ZTIN6thrust6system6detail9bad_allocE,comdat .weak _ZTIN6thrust6system6detail9bad_allocE .p2align 3, 0x0 _ZTIN6thrust6system6detail9bad_allocE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust6system6detail9bad_allocE .quad _ZTISt9bad_alloc .size _ZTIN6thrust6system6detail9bad_allocE, 24 .type _ZZN6thrust6system12hip_categoryEvE6result,@object # @_ZZN6thrust6system12hip_categoryEvE6result .section .bss._ZZN6thrust6system12hip_categoryEvE6result,"awG",@nobits,_ZZN6thrust6system12hip_categoryEvE6result,comdat .weak _ZZN6thrust6system12hip_categoryEvE6result .p2align 3, 0x0 _ZZN6thrust6system12hip_categoryEvE6result: .zero 8 .size _ZZN6thrust6system12hip_categoryEvE6result, 8 .type _ZGVZN6thrust6system12hip_categoryEvE6result,@object # @_ZGVZN6thrust6system12hip_categoryEvE6result .section .bss._ZGVZN6thrust6system12hip_categoryEvE6result,"awG",@nobits,_ZGVZN6thrust6system12hip_categoryEvE6result,comdat .weak _ZGVZN6thrust6system12hip_categoryEvE6result .p2align 3, 0x0 _ZGVZN6thrust6system12hip_categoryEvE6result: .quad 0 # 0x0 .size _ZGVZN6thrust6system12hip_categoryEvE6result, 8 .hidden __dso_handle .type _ZTVN6thrust6system11hip_rocprim6detail18hip_error_categoryE,@object # @_ZTVN6thrust6system11hip_rocprim6detail18hip_error_categoryE .section .rodata._ZTVN6thrust6system11hip_rocprim6detail18hip_error_categoryE,"aG",@progbits,_ZTVN6thrust6system11hip_rocprim6detail18hip_error_categoryE,comdat .weak _ZTVN6thrust6system11hip_rocprim6detail18hip_error_categoryE .p2align 3, 0x0 _ZTVN6thrust6system11hip_rocprim6detail18hip_error_categoryE: .quad 0 .quad _ZTIN6thrust6system11hip_rocprim6detail18hip_error_categoryE .quad _ZN6thrust6system14error_categoryD2Ev .quad _ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev .quad _ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv .quad _ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi .quad _ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE .quad _ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi .quad _ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei .size _ZTVN6thrust6system11hip_rocprim6detail18hip_error_categoryE, 72 .type _ZTSN6thrust6system11hip_rocprim6detail18hip_error_categoryE,@object # @_ZTSN6thrust6system11hip_rocprim6detail18hip_error_categoryE .section .rodata._ZTSN6thrust6system11hip_rocprim6detail18hip_error_categoryE,"aG",@progbits,_ZTSN6thrust6system11hip_rocprim6detail18hip_error_categoryE,comdat .weak _ZTSN6thrust6system11hip_rocprim6detail18hip_error_categoryE _ZTSN6thrust6system11hip_rocprim6detail18hip_error_categoryE: .asciz "N6thrust6system11hip_rocprim6detail18hip_error_categoryE" .size _ZTSN6thrust6system11hip_rocprim6detail18hip_error_categoryE, 57 .type _ZTSN6thrust6system14error_categoryE,@object # @_ZTSN6thrust6system14error_categoryE .section .rodata._ZTSN6thrust6system14error_categoryE,"aG",@progbits,_ZTSN6thrust6system14error_categoryE,comdat .weak _ZTSN6thrust6system14error_categoryE _ZTSN6thrust6system14error_categoryE: .asciz "N6thrust6system14error_categoryE" .size _ZTSN6thrust6system14error_categoryE, 33 .type _ZTIN6thrust6system14error_categoryE,@object # @_ZTIN6thrust6system14error_categoryE .section .rodata._ZTIN6thrust6system14error_categoryE,"aG",@progbits,_ZTIN6thrust6system14error_categoryE,comdat .weak _ZTIN6thrust6system14error_categoryE .p2align 3, 0x0 _ZTIN6thrust6system14error_categoryE: .quad _ZTVN10__cxxabiv117__class_type_infoE+16 .quad _ZTSN6thrust6system14error_categoryE .size _ZTIN6thrust6system14error_categoryE, 16 .type _ZTIN6thrust6system11hip_rocprim6detail18hip_error_categoryE,@object # @_ZTIN6thrust6system11hip_rocprim6detail18hip_error_categoryE .section .rodata._ZTIN6thrust6system11hip_rocprim6detail18hip_error_categoryE,"aG",@progbits,_ZTIN6thrust6system11hip_rocprim6detail18hip_error_categoryE,comdat .weak _ZTIN6thrust6system11hip_rocprim6detail18hip_error_categoryE .p2align 3, 0x0 _ZTIN6thrust6system11hip_rocprim6detail18hip_error_categoryE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust6system11hip_rocprim6detail18hip_error_categoryE .quad _ZTIN6thrust6system14error_categoryE .size _ZTIN6thrust6system11hip_rocprim6detail18hip_error_categoryE, 24 .type _ZTVN6thrust6system14error_categoryE,@object # @_ZTVN6thrust6system14error_categoryE .section .rodata._ZTVN6thrust6system14error_categoryE,"aG",@progbits,_ZTVN6thrust6system14error_categoryE,comdat .weak _ZTVN6thrust6system14error_categoryE .p2align 3, 0x0 _ZTVN6thrust6system14error_categoryE: .quad 0 .quad _ZTIN6thrust6system14error_categoryE .quad _ZN6thrust6system14error_categoryD2Ev .quad _ZN6thrust6system14error_categoryD0Ev .quad __cxa_pure_virtual .quad _ZNK6thrust6system14error_category23default_error_conditionEi .quad _ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE .quad _ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi .quad __cxa_pure_virtual .size _ZTVN6thrust6system14error_categoryE, 72 .type .L.str.8,@object # @.str.8 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.8: .asciz "hip" .size .L.str.8, 4 .type _ZZN6thrust6system15system_categoryEvE6result,@object # @_ZZN6thrust6system15system_categoryEvE6result .section .bss._ZZN6thrust6system15system_categoryEvE6result,"awG",@nobits,_ZZN6thrust6system15system_categoryEvE6result,comdat .weak _ZZN6thrust6system15system_categoryEvE6result .p2align 3, 0x0 _ZZN6thrust6system15system_categoryEvE6result: .zero 8 .size _ZZN6thrust6system15system_categoryEvE6result, 8 .type _ZGVZN6thrust6system15system_categoryEvE6result,@object # @_ZGVZN6thrust6system15system_categoryEvE6result .section .bss._ZGVZN6thrust6system15system_categoryEvE6result,"awG",@nobits,_ZGVZN6thrust6system15system_categoryEvE6result,comdat .weak _ZGVZN6thrust6system15system_categoryEvE6result .p2align 3, 0x0 _ZGVZN6thrust6system15system_categoryEvE6result: .quad 0 # 0x0 .size _ZGVZN6thrust6system15system_categoryEvE6result, 8 .type _ZTVN6thrust6system6detail21system_error_categoryE,@object # @_ZTVN6thrust6system6detail21system_error_categoryE .section .rodata._ZTVN6thrust6system6detail21system_error_categoryE,"aG",@progbits,_ZTVN6thrust6system6detail21system_error_categoryE,comdat .weak _ZTVN6thrust6system6detail21system_error_categoryE .p2align 3, 0x0 _ZTVN6thrust6system6detail21system_error_categoryE: .quad 0 .quad _ZTIN6thrust6system6detail21system_error_categoryE .quad _ZN6thrust6system14error_categoryD2Ev .quad _ZN6thrust6system6detail21system_error_categoryD0Ev .quad _ZNK6thrust6system6detail21system_error_category4nameEv .quad _ZNK6thrust6system6detail21system_error_category23default_error_conditionEi .quad _ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE .quad _ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi .quad _ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei .size _ZTVN6thrust6system6detail21system_error_categoryE, 72 .type _ZTSN6thrust6system6detail21system_error_categoryE,@object # @_ZTSN6thrust6system6detail21system_error_categoryE .section .rodata._ZTSN6thrust6system6detail21system_error_categoryE,"aG",@progbits,_ZTSN6thrust6system6detail21system_error_categoryE,comdat .weak _ZTSN6thrust6system6detail21system_error_categoryE _ZTSN6thrust6system6detail21system_error_categoryE: .asciz "N6thrust6system6detail21system_error_categoryE" .size _ZTSN6thrust6system6detail21system_error_categoryE, 47 .type _ZTIN6thrust6system6detail21system_error_categoryE,@object # @_ZTIN6thrust6system6detail21system_error_categoryE .section .rodata._ZTIN6thrust6system6detail21system_error_categoryE,"aG",@progbits,_ZTIN6thrust6system6detail21system_error_categoryE,comdat .weak _ZTIN6thrust6system6detail21system_error_categoryE .p2align 3, 0x0 _ZTIN6thrust6system6detail21system_error_categoryE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust6system6detail21system_error_categoryE .quad _ZTIN6thrust6system14error_categoryE .size _ZTIN6thrust6system6detail21system_error_categoryE, 24 .type .L.str.9,@object # @.str.9 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.9: .asciz "system" .size .L.str.9, 7 .type _ZZN6thrust6system16generic_categoryEvE6result,@object # @_ZZN6thrust6system16generic_categoryEvE6result .section .bss._ZZN6thrust6system16generic_categoryEvE6result,"awG",@nobits,_ZZN6thrust6system16generic_categoryEvE6result,comdat .weak _ZZN6thrust6system16generic_categoryEvE6result .p2align 3, 0x0 _ZZN6thrust6system16generic_categoryEvE6result: .zero 8 .size _ZZN6thrust6system16generic_categoryEvE6result, 8 .type _ZGVZN6thrust6system16generic_categoryEvE6result,@object # @_ZGVZN6thrust6system16generic_categoryEvE6result .section .bss._ZGVZN6thrust6system16generic_categoryEvE6result,"awG",@nobits,_ZGVZN6thrust6system16generic_categoryEvE6result,comdat .weak _ZGVZN6thrust6system16generic_categoryEvE6result .p2align 3, 0x0 _ZGVZN6thrust6system16generic_categoryEvE6result: .quad 0 # 0x0 .size _ZGVZN6thrust6system16generic_categoryEvE6result, 8 .type _ZTVN6thrust6system6detail22generic_error_categoryE,@object # @_ZTVN6thrust6system6detail22generic_error_categoryE .section .rodata._ZTVN6thrust6system6detail22generic_error_categoryE,"aG",@progbits,_ZTVN6thrust6system6detail22generic_error_categoryE,comdat .weak _ZTVN6thrust6system6detail22generic_error_categoryE .p2align 3, 0x0 _ZTVN6thrust6system6detail22generic_error_categoryE: .quad 0 .quad _ZTIN6thrust6system6detail22generic_error_categoryE .quad _ZN6thrust6system14error_categoryD2Ev .quad _ZN6thrust6system6detail22generic_error_categoryD0Ev .quad _ZNK6thrust6system6detail22generic_error_category4nameEv .quad _ZNK6thrust6system14error_category23default_error_conditionEi .quad _ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE .quad _ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi .quad _ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei .size _ZTVN6thrust6system6detail22generic_error_categoryE, 72 .type _ZTSN6thrust6system6detail22generic_error_categoryE,@object # @_ZTSN6thrust6system6detail22generic_error_categoryE .section .rodata._ZTSN6thrust6system6detail22generic_error_categoryE,"aG",@progbits,_ZTSN6thrust6system6detail22generic_error_categoryE,comdat .weak _ZTSN6thrust6system6detail22generic_error_categoryE _ZTSN6thrust6system6detail22generic_error_categoryE: .asciz "N6thrust6system6detail22generic_error_categoryE" .size _ZTSN6thrust6system6detail22generic_error_categoryE, 48 .type _ZTIN6thrust6system6detail22generic_error_categoryE,@object # @_ZTIN6thrust6system6detail22generic_error_categoryE .section .rodata._ZTIN6thrust6system6detail22generic_error_categoryE,"aG",@progbits,_ZTIN6thrust6system6detail22generic_error_categoryE,comdat .weak _ZTIN6thrust6system6detail22generic_error_categoryE .p2align 3, 0x0 _ZTIN6thrust6system6detail22generic_error_categoryE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust6system6detail22generic_error_categoryE .quad _ZTIN6thrust6system14error_categoryE .size _ZTIN6thrust6system6detail22generic_error_categoryE, 24 .type .L.str.10,@object # @.str.10 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.10: .asciz "generic" .size .L.str.10, 8 .type _ZZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11,@object # @_ZZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11 .section .rodata._ZZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11,"aG",@progbits,_ZZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11,comdat .weak _ZZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11 .p2align 3, 0x0 _ZZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11: .quad _ZZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11+16 .quad 13 # 0xd .asciz "Unknown error\000\000" .size _ZZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11, 32 .type .L.str.11,@object # @.str.11 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.11: .asciz "basic_string::_M_create" .size .L.str.11, 24 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz "unknown error" .size .L.str.12, 14 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz "hipErrorUnknown" .size .L.str.13, 16 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz ": " .size .L.str.14, 3 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "basic_string::append" .size .L.str.15, 21 .type .L.str.16,@object # @.str.16 .L.str.16: .asciz "basic_string: construction from null is not valid" .size .L.str.16, 50 .type _ZTVN6thrust6system6detail9bad_allocE,@object # @_ZTVN6thrust6system6detail9bad_allocE .section .rodata._ZTVN6thrust6system6detail9bad_allocE,"aG",@progbits,_ZTVN6thrust6system6detail9bad_allocE,comdat .weak _ZTVN6thrust6system6detail9bad_allocE .p2align 3, 0x0 _ZTVN6thrust6system6detail9bad_allocE: .quad 0 .quad _ZTIN6thrust6system6detail9bad_allocE .quad _ZN6thrust6system6detail9bad_allocD2Ev .quad _ZN6thrust6system6detail9bad_allocD0Ev .quad _ZNK6thrust6system6detail9bad_alloc4whatEv .size _ZTVN6thrust6system6detail9bad_allocE, 40 .type .L.str.17,@object # @.str.17 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.17: .asciz "basic_string::_M_replace" .size .L.str.17, 25 .type .L.str.18,@object # @.str.18 .L.str.18: .asciz "HIP free failed" .size .L.str.18, 16 .type _ZTSN6thrust6system12system_errorE,@object # @_ZTSN6thrust6system12system_errorE .section .rodata._ZTSN6thrust6system12system_errorE,"aG",@progbits,_ZTSN6thrust6system12system_errorE,comdat .weak _ZTSN6thrust6system12system_errorE _ZTSN6thrust6system12system_errorE: .asciz "N6thrust6system12system_errorE" .size _ZTSN6thrust6system12system_errorE, 31 .type _ZTIN6thrust6system12system_errorE,@object # @_ZTIN6thrust6system12system_errorE .section .rodata._ZTIN6thrust6system12system_errorE,"aG",@progbits,_ZTIN6thrust6system12system_errorE,comdat .weak _ZTIN6thrust6system12system_errorE .p2align 3, 0x0 _ZTIN6thrust6system12system_errorE: .quad _ZTVN10__cxxabiv120__si_class_type_infoE+16 .quad _ZTSN6thrust6system12system_errorE .quad _ZTISt13runtime_error .size _ZTIN6thrust6system12system_errorE, 24 .type _ZTVN6thrust6system12system_errorE,@object # @_ZTVN6thrust6system12system_errorE .section .rodata._ZTVN6thrust6system12system_errorE,"aG",@progbits,_ZTVN6thrust6system12system_errorE,comdat .weak _ZTVN6thrust6system12system_errorE .p2align 3, 0x0 _ZTVN6thrust6system12system_errorE: .quad 0 .quad _ZTIN6thrust6system12system_errorE .quad _ZN6thrust6system12system_errorD2Ev .quad _ZN6thrust6system12system_errorD0Ev .quad _ZNK6thrust6system12system_error4whatEv .size _ZTVN6thrust6system12system_errorE, 40 .type .L.str.19,@object # @.str.19 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.19: .asciz "assignment exceeds max_size()." .size .L.str.19, 31 .type .L.str.20,@object # @.str.20 .L.str.20: .asciz "__copy::trivial_device_copy H->D: failed" .size .L.str.20, 41 .type .L.str.21,@object # @.str.21 .L.str.21: .asciz "parallel_for failed" .size .L.str.21, 20 .type .L.str.22,@object # @.str.22 .L.str.22: .asciz "parallel_for: failed to synchronize" .size .L.str.22, 36 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@object # @_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .section .rodata._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"aG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat .weak _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .p2align 3, 0x0 _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_: .quad _ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, 8 .type .L.str.24,@object # @.str.24 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.24: .asciz "trivial_device_copy D->H failed" .size .L.str.24, 32 .type .L.str.25,@object # @.str.25 .L.str.25: .asciz "temporary_buffer::allocate: get_temporary_buffer failed" .size .L.str.25, 56 .type .L.str.26,@object # @.str.26 .L.str.26: .asciz "device free failed" .size .L.str.26, 19 .type .L.str.27,@object # @.str.27 .L.str.27: .asciz "__copy:: D->D: failed" .size .L.str.27, 22 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z7reduce0PiS_i" .size .L__unnamed_1, 16 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_" .size .L__unnamed_2, 128 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__reduce0PiS_i .addrsig_sym __gxx_personality_v0 .addrsig_sym _ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Unwind_Resume .addrsig_sym _Z7reduce0PiS_i .addrsig_sym _ZSt4cout .addrsig_sym _ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource .addrsig_sym _ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource .addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE .addrsig_sym _ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE .addrsig_sym _ZTVN10__cxxabiv117__class_type_infoE .addrsig_sym _ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE .addrsig_sym _ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE .addrsig_sym _ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE .addrsig_sym _ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource .addrsig_sym _ZTSN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE .addrsig_sym _ZTSN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE .addrsig_sym _ZTIN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEEE .addrsig_sym _ZTIN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE .addrsig_sym _ZTSN6thrust6system6detail9bad_allocE .addrsig_sym _ZTISt9bad_alloc .addrsig_sym _ZTIN6thrust6system6detail9bad_allocE .addrsig_sym _ZZN6thrust6system12hip_categoryEvE6result .addrsig_sym _ZGVZN6thrust6system12hip_categoryEvE6result .addrsig_sym __dso_handle .addrsig_sym _ZTSN6thrust6system11hip_rocprim6detail18hip_error_categoryE .addrsig_sym _ZTSN6thrust6system14error_categoryE .addrsig_sym _ZTIN6thrust6system14error_categoryE .addrsig_sym _ZTIN6thrust6system11hip_rocprim6detail18hip_error_categoryE .addrsig_sym _ZZN6thrust6system15system_categoryEvE6result .addrsig_sym _ZGVZN6thrust6system15system_categoryEvE6result .addrsig_sym _ZTSN6thrust6system6detail21system_error_categoryE .addrsig_sym _ZTIN6thrust6system6detail21system_error_categoryE .addrsig_sym _ZZN6thrust6system16generic_categoryEvE6result .addrsig_sym _ZGVZN6thrust6system16generic_categoryEvE6result .addrsig_sym _ZTSN6thrust6system6detail22generic_error_categoryE .addrsig_sym _ZTIN6thrust6system6detail22generic_error_categoryE .addrsig_sym _ZZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11 .addrsig_sym _ZTSN6thrust6system12system_errorE .addrsig_sym _ZTISt13runtime_error .addrsig_sym _ZTIN6thrust6system12system_errorE .addrsig_sym _ZTISt12length_error .addrsig_sym _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
2,110
280,415
5,671
123,170
180
code for sm_80 Function : _Z27convolution_1D_basic_kernalPfS_S_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R8, SR_CTAID.X ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x178] ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R7, RZ, RZ, RZ ; S2R R11, SR_TID.X ; ISETP.GE.AND P0, PT, R9, 0x1, PT ; IMAD R0, R8, c[0x0][0x0], R11 ; @!P0 BRA 0x580 ; IADD3 R2, R9.reuse, -0x1, RZ ; IMAD.MOV.U32 R7, RZ, RZ, RZ ; LOP3.LUT R6, R9.reuse, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; LEA.HI R9, R9, c[0x0][0x178], RZ, 0x1 ; ISETP.NE.AND P4, PT, R6, RZ, PT ; SHF.R.S32.HI R9, RZ, 0x1, R9 ; @!P0 BRA 0x400 ; IADD3 R2, R0, -R9, RZ ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; HFMA2.MMA R10, -RZ, RZ, 0, 0 ; IADD3 R13, R6, -c[0x0][0x178], RZ ; IMAD.MOV.U32 R7, RZ, RZ, RZ ; IADD3 R21, -R9, 0x3, R0 ; IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; IMAD.MOV.U32 R15, RZ, RZ, R3 ; IMAD.MOV.U32 R14, RZ, RZ, R2 ; IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x168] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; IADD3 R2, R21.reuse, -0x3, RZ ; IADD3 R4, R21, -0x2, RZ ; ISETP.GE.AND P0, PT, R2, c[0x0][0x17c], PT ; IADD3 R5, R21, -0x1, RZ ; ISETP.LT.OR P0, PT, R2, RZ, P0 ; ISETP.GE.AND P1, PT, R4.reuse, c[0x0][0x17c], PT ; ISETP.GE.AND P2, PT, R5.reuse, c[0x0][0x17c], PT ; ISETP.LT.OR P1, PT, R4, RZ, P1 ; IMAD.MOV.U32 R4, RZ, RZ, R14 ; ISETP.LT.OR P2, PT, R5, RZ, P2 ; IMAD.MOV.U32 R5, RZ, RZ, R15 ; MOV R2, R12 ; ISETP.GE.AND P3, PT, R21.reuse, c[0x0][0x17c], PT ; @!P0 LDG.E R12, [R4.64] ; ISETP.LT.OR P3, PT, R21, RZ, P3 ; @!P0 LDG.E R14, [R2.64] ; @!P1 LDG.E R16, [R2.64+0x4] ; @!P1 LDG.E R15, [R4.64+0x4] ; @!P2 LDG.E R18, [R2.64+0x8] ; @!P2 LDG.E R17, [R4.64+0x8] ; @!P3 LDG.E R20, [R2.64+0xc] ; @!P3 LDG.E R19, [R4.64+0xc] ; IADD3 R10, R10, 0x4, RZ ; IADD3 R21, R21, 0x4, RZ ; @!P0 FFMA R7, R12, R14, R7 ; IMAD.IADD R12, R13, 0x1, R10 ; ISETP.NE.AND P0, PT, R12, RZ, PT ; @!P1 FFMA R7, R16, R15, R7 ; IADD3 R14, P1, R4, 0x10, RZ ; IADD3 R12, P5, R2, 0x10, RZ ; @!P2 FFMA R7, R18, R17, R7 ; IMAD.X R15, RZ, RZ, R5, P1 ; IMAD.X R3, RZ, RZ, R3, P5 ; @!P3 FFMA R7, R20, R19, R7 ; @P0 BRA 0x1d0 ; @!P4 BRA 0x580 ; IMAD.IADD R11, R11, 0x1, R10 ; MOV R3, 0x4 ; IMAD R8, R8, c[0x0][0x0], R11 ; IMAD.WIDE R10, R10, R3, c[0x0][0x168] ; IMAD.IADD R8, R8, 0x1, -R9 ; IMAD.WIDE R2, R8, R3, c[0x0][0x160] ; IMAD.MOV.U32 R9, RZ, RZ, R2 ; ISETP.GE.AND P0, PT, R8, c[0x0][0x17c], PT ; ISETP.LT.OR P0, PT, R8, RZ, P0 ; @!P0 IMAD.MOV.U32 R2, RZ, RZ, R9 ; @!P0 MOV R5, R11 ; @!P0 IMAD.MOV.U32 R4, RZ, RZ, R10 ; @!P0 LDG.E R2, [R2.64] ; @!P0 LDG.E R4, [R4.64] ; IADD3 R6, R6, -0x1, RZ ; IADD3 R10, P2, R10, 0x4, RZ ; ISETP.NE.AND P1, PT, R6, RZ, PT ; IADD3 R9, P3, R9, 0x4, RZ ; IMAD.X R11, RZ, RZ, R11, P2 ; IADD3 R8, R8, 0x1, RZ ; IMAD.X R3, RZ, RZ, R3, P3 ; @!P0 FFMA R7, R2, R4, R7 ; @P1 BRA 0x480 ; IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; STG.E [R2.64], R7 ; EXIT ; BRA 0x5c0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0010b69f_00000000-6_a1241984ee469fb49a113ad95e7b4f8099ab4062.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4931: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4931: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii .type _Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii, @function _Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii: .LFB4920: .cfi_startproc endbr64 movl $0, (%rdx) testl %r9d, %r9d jle .L12 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 movq %rdi, %r10 movq %rsi, %r11 movq %rdx, %rsi movl %ecx, %ebp movl %ecx, %eax shrl $31, %eax addl %ecx, %eax sarl %eax negl %eax movl %eax, %r12d leal (%rax,%rcx), %ecx movslq %eax, %rbx salq $2, %rbx addl %eax, %r9d leal (%r9,%rbp), %r13d jmp .L8 .L6: addl $1, %eax addq $4, %rdx cmpl %ecx, %eax je .L5 .L7: cmpl %eax, %r8d jle .L6 testl %eax, %eax js .L6 movq %rdx, %r9 addq (%r10), %r9 movq (%r11), %rdi movss (%r9,%rbx), %xmm0 mulss (%rdi,%rdx), %xmm0 pxor %xmm1, %xmm1 cvtsi2ssl (%rsi), %xmm1 addss %xmm1, %xmm0 cvttss2sil %xmm0, %edi movl %edi, (%rsi) jmp .L6 .L5: addl $1, %ecx addq $4, %rbx addl $1, %r12d cmpl %r13d, %ecx je .L15 .L8: testl %ebp, %ebp jle .L5 movl %r12d, %eax movl $0, %edx jmp .L7 .L15: popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L12: .cfi_restore 3 .cfi_restore 6 .cfi_restore 12 .cfi_restore 13 ret .cfi_endproc .LFE4920: .size _Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii, .-_Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii .globl _Z10checkArrayRSt6vectorIfSaIfEERii .type _Z10checkArrayRSt6vectorIfSaIfEERii, @function _Z10checkArrayRSt6vectorIfSaIfEERii: .LFB4921: .cfi_startproc endbr64 movl $0, (%rsi) testl %edx, %edx jle .L16 movslq %edx, %rdx leaq 0(,%rdx,4), %rcx movl $0, %eax .L18: movq (%rdi), %rdx pxor %xmm0, %xmm0 cvtsi2ssl (%rsi), %xmm0 addss (%rdx,%rax), %xmm0 cvttss2sil %xmm0, %edx movl %edx, (%rsi) addq $4, %rax cmpq %rcx, %rax jne .L18 .L16: ret .cfi_endproc .LFE4921: .size _Z10checkArrayRSt6vectorIfSaIfEERii, .-_Z10checkArrayRSt6vectorIfSaIfEERii .globl _Z53__device_stub__Z27convolution_1D_basic_kernalPfS_S_iiPfS_S_ii .type _Z53__device_stub__Z27convolution_1D_basic_kernalPfS_S_iiPfS_S_ii, @function _Z53__device_stub__Z27convolution_1D_basic_kernalPfS_S_iiPfS_S_ii: .LFB4953: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L24 .L20: movq 136(%rsp), %rax subq %fs:40, %rax jne .L25 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L24: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z27convolution_1D_basic_kernalPfS_S_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L20 .L25: call __stack_chk_fail@PLT .cfi_endproc .LFE4953: .size _Z53__device_stub__Z27convolution_1D_basic_kernalPfS_S_iiPfS_S_ii, .-_Z53__device_stub__Z27convolution_1D_basic_kernalPfS_S_iiPfS_S_ii .globl _Z27convolution_1D_basic_kernalPfS_S_ii .type _Z27convolution_1D_basic_kernalPfS_S_ii, @function _Z27convolution_1D_basic_kernalPfS_S_ii: .LFB4954: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z53__device_stub__Z27convolution_1D_basic_kernalPfS_S_iiPfS_S_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4954: .size _Z27convolution_1D_basic_kernalPfS_S_ii, .-_Z27convolution_1D_basic_kernalPfS_S_ii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z27convolution_1D_basic_kernalPfS_S_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4956: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z27convolution_1D_basic_kernalPfS_S_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4956: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .rodata._ZNSt6vectorIfSaIfEEC2EmRKS0_.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "cannot create std::vector larger than max_size()" .section .text._ZNSt6vectorIfSaIfEEC2EmRKS0_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC5EmRKS0_,comdat .align 2 .weak _ZNSt6vectorIfSaIfEEC2EmRKS0_ .type _ZNSt6vectorIfSaIfEEC2EmRKS0_, @function _ZNSt6vectorIfSaIfEEC2EmRKS0_: .LFB5271: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rsi, %rax shrq $61, %rax jne .L40 movq %rdi, %rbx movq %rsi, %rbp movq $0, (%rdi) movq $0, 8(%rdi) movq $0, 16(%rdi) testq %rsi, %rsi je .L32 leaq 0(,%rsi,4), %r12 movq %r12, %rdi call _Znwm@PLT movq %rax, (%rbx) movq %rax, 8(%rbx) leaq (%rax,%r12), %rdx movq %rdx, 16(%rbx) movl $0x00000000, (%rax) addq $4, %rax cmpq $1, %rbp je .L35 cmpq %rax, %rdx je .L36 .L34: movl $0x00000000, (%rax) addq $4, %rax cmpq %rax, %rdx jne .L34 jmp .L33 .L40: leaq .LC1(%rip), %rdi call _ZSt20__throw_length_errorPKc@PLT .L35: movq %rax, %rdx jmp .L33 .L36: movq %rax, %rdx jmp .L33 .L32: movq $0, (%rdi) movq $0, 16(%rdi) movl $0, %edx .L33: movq %rdx, 8(%rbx) popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE5271: .size _ZNSt6vectorIfSaIfEEC2EmRKS0_, .-_ZNSt6vectorIfSaIfEEC2EmRKS0_ .weak _ZNSt6vectorIfSaIfEEC1EmRKS0_ .set _ZNSt6vectorIfSaIfEEC1EmRKS0_,_ZNSt6vectorIfSaIfEEC2EmRKS0_ .section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat .align 2 .weak _ZNSt6vectorIfSaIfEED2Ev .type _ZNSt6vectorIfSaIfEED2Ev, @function _ZNSt6vectorIfSaIfEED2Ev: .LFB5274: .cfi_startproc endbr64 movq (%rdi), %rax testq %rax, %rax je .L44 subq $8, %rsp .cfi_def_cfa_offset 16 movq 16(%rdi), %rsi subq %rax, %rsi movq %rax, %rdi call _ZdlPvm@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .L44: ret .cfi_endproc .LFE5274: .size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev .weak _ZNSt6vectorIfSaIfEED1Ev .set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev .section .rodata.str1.8 .align 8 .LC3: .string "/home/ubuntu/Datasets/Stack_v2_cuda-hip/train/a1241984ee469fb49a113ad95e7b4f8099ab4062.cu" .section .rodata.str1.1,"aMS",@progbits,1 .LC4: .string "Error at %s:%d\n" .LC5: .string "Using Device %d: %s\n" .LC6: .string "size of i array: %d\n" .LC7: .string "size of k array: %d\n" .LC8: .string "size of block: %d\n" .section .rodata.str1.8 .align 8 .LC9: .string "Compute time on GPU: %3.6f ms \n" .align 8 .LC10: .string "Compute time on CPU: %3.6f ms \n" .section .rodata.str1.1 .LC11: .string "Check Result: Arrays matched\n" .section .rodata.str1.8 .align 8 .LC12: .string "Check Result: Arrays do not match\n" .text .globl main .type main, @function main: .LFB4922: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA4922 endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $1256, %rsp .cfi_def_cfa_offset 1296 movq %fs:40, %rax movq %rax, 1240(%rsp) xorl %eax, %eax leaq 208(%rsp), %rdi movl $0, %esi .LEHB0: call cudaGetDeviceProperties_v2@PLT testl %eax, %eax jne .L71 leaq 208(%rsp), %rcx movl $0, %edx leaq .LC5(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %edi call cudaSetDevice@PLT testl %eax, %eax jne .L72 movl $0, (%rsp) movl $0, 4(%rsp) movl $2000, %edx leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $500, %edx leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $10, %edx leaq .LC8(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 176(%rsp), %rbx leaq 80(%rsp), %rdi movq %rbx, %rdx movl $2000, %esi call _ZNSt6vectorIfSaIfEEC1EmRKS0_ .LEHE0: leaq 112(%rsp), %rdi movq %rbx, %rdx movl $500, %esi .LEHB1: call _ZNSt6vectorIfSaIfEEC1EmRKS0_ .LEHE1: jmp .L73 .L71: movl $76, %ecx leaq .LC3(%rip), %rdx leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax .LEHB2: call __printf_chk@PLT movl $1, %eax jmp .L47 .L72: movl $78, %ecx leaq .LC3(%rip), %rdx leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .LEHE2: movl $1, %eax jmp .L47 .L73: movq %rbx, %rdx leaq 144(%rsp), %rdi movl $2499, %esi .LEHB3: call _ZNSt6vectorIfSaIfEEC1EmRKS0_ .LEHE3: leaq 68(%rsp), %rdx movq %rbx, %rdi movl $2499, %esi .LEHB4: call _ZNSt6vectorIfSaIfEEC1EmRKS0_ .LEHE4: movl $0, %edi call time@PLT movl %eax, %edi call srand@PLT movq 88(%rsp), %rbp movq 80(%rsp), %r13 cmpq %rbp, %r13 je .L51 movq %r13, %rbx .L52: call rand@PLT movslq %eax, %rdx imulq $954437177, %rdx, %rdx sarq $33, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx leal (%rdx,%rdx,8), %edx subl %edx, %eax pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 movss %xmm0, (%rbx) addq $4, %rbx cmpq %rbx, %rbp jne .L52 .L51: movq 120(%rsp), %rbp movq 112(%rsp), %r12 cmpq %rbp, %r12 je .L53 movq %r12, %rbx .L54: call rand@PLT movslq %eax, %rdx imulq $954437177, %rdx, %rdx sarq $33, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx leal (%rdx,%rdx,8), %edx subl %edx, %eax pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 movss %xmm0, (%rbx) addq $4, %rbx cmpq %rbx, %rbp jne .L54 .L53: leaq 16(%rsp), %rdi movl $8000, %esi .LEHB5: call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $2000, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $9996, %esi call cudaMalloc@PLT movl $1, %ecx movl $8000, %edx movq %r13, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $2000, %edx movq %r12, %rsi movq 24(%rsp), %rdi call cudaMemcpy@PLT movl $200, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $10, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) leaq 40(%rsp), %rdi call cudaEventCreate@PLT leaq 48(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 40(%rsp), %rdi call cudaEventRecord@PLT movl 64(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 56(%rsp), %rdx movq 68(%rsp), %rdi movl 76(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L55 movl $200, %r8d movl $401, %ecx movq 32(%rsp), %rdx movq 24(%rsp), %rsi movq 16(%rsp), %rdi call _Z53__device_stub__Z27convolution_1D_basic_kernalPfS_S_iiPfS_S_ii .L55: movl $2, %ecx movl $9996, %edx movq 32(%rsp), %rsi movq 144(%rsp), %rdi call cudaMemcpy@PLT movl $0, %esi movq 48(%rsp), %rdi call cudaEventRecord@PLT movq 48(%rsp), %rdi call cudaEventSynchronize@PLT leaq 8(%rsp), %rdi movq 48(%rsp), %rdx movq 40(%rsp), %rsi call cudaEventElapsedTime@PLT leaq 40(%rsp), %rdi call cudaEventCreate@PLT leaq 48(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 40(%rsp), %rdi call cudaEventRecord@PLT movq %rsp, %rdx leaq 112(%rsp), %rsi leaq 80(%rsp), %rdi movl $2499, %r9d movl $200, %r8d movl $401, %ecx call _Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii movl $0, %esi movq 48(%rsp), %rdi call cudaEventRecord@PLT movq 48(%rsp), %rdi call cudaEventSynchronize@PLT leaq 12(%rsp), %rdi movq 48(%rsp), %rdx movq 40(%rsp), %rsi call cudaEventElapsedTime@PLT pxor %xmm0, %xmm0 cvtss2sd 8(%rsp), %xmm0 leaq .LC9(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT pxor %xmm0, %xmm0 cvtss2sd 12(%rsp), %xmm0 leaq .LC10(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT leaq 4(%rsp), %rsi leaq 144(%rsp), %rdi movl $2499, %edx call _Z10checkArrayRSt6vectorIfSaIfEERii movl 4(%rsp), %eax cmpl %eax, (%rsp) je .L74 leaq .LC12(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L57 .L74: leaq .LC11(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L57: movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT .LEHE5: leaq 176(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev leaq 144(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev leaq 112(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev leaq 80(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev movl $0, %eax .L47: movq 1240(%rsp), %rdx subq %fs:40, %rdx jne .L75 addq $1256, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L67: .cfi_restore_state endbr64 movq %rax, %rbx leaq 176(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev .L59: leaq 144(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev .L60: leaq 112(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev .L61: leaq 80(%rsp), %rdi call _ZNSt6vectorIfSaIfEED1Ev movq 1240(%rsp), %rax subq %fs:40, %rax je .L62 call __stack_chk_fail@PLT .L66: endbr64 movq %rax, %rbx jmp .L59 .L65: endbr64 movq %rax, %rbx jmp .L60 .L64: endbr64 movq %rax, %rbx jmp .L61 .L62: movq %rbx, %rdi .LEHB6: call _Unwind_Resume@PLT .LEHE6: .L75: call __stack_chk_fail@PLT .cfi_endproc .LFE4922: .globl __gxx_personality_v0 .section .gcc_except_table,"a",@progbits .LLSDA4922: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE4922-.LLSDACSB4922 .LLSDACSB4922: .uleb128 .LEHB0-.LFB4922 .uleb128 .LEHE0-.LEHB0 .uleb128 0 .uleb128 0 .uleb128 .LEHB1-.LFB4922 .uleb128 .LEHE1-.LEHB1 .uleb128 .L64-.LFB4922 .uleb128 0 .uleb128 .LEHB2-.LFB4922 .uleb128 .LEHE2-.LEHB2 .uleb128 0 .uleb128 0 .uleb128 .LEHB3-.LFB4922 .uleb128 .LEHE3-.LEHB3 .uleb128 .L65-.LFB4922 .uleb128 0 .uleb128 .LEHB4-.LFB4922 .uleb128 .LEHE4-.LEHB4 .uleb128 .L66-.LFB4922 .uleb128 0 .uleb128 .LEHB5-.LFB4922 .uleb128 .LEHE5-.LEHB5 .uleb128 .L67-.LFB4922 .uleb128 0 .uleb128 .LEHB6-.LFB4922 .uleb128 .LEHE6-.LEHB6 .uleb128 0 .uleb128 0 .LLSDACSE4922: .text .size main, .-main .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z27convolution_1D_basic_kernalPfS_S_ii ; -- Begin function _Z27convolution_1D_basic_kernalPfS_S_ii .globl _Z27convolution_1D_basic_kernalPfS_S_ii .p2align 8 .type _Z27convolution_1D_basic_kernalPfS_S_ii,@function _Z27convolution_1D_basic_kernalPfS_S_ii: ; @_Z27convolution_1D_basic_kernalPfS_S_ii ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_cmp_lt_i32 s3, 1 v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_cbranch_scc1 .LBB0_5 ; %bb.1: ; %.lr.ph.preheader s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b32 s8, s[0:1], 0x1c s_lshr_b32 s2, s3, 31 v_mov_b32_e32 v3, 0 s_add_i32 s2, s3, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_ashr_i32 s2, s2, 1 v_subrev_nc_u32_e32 v2, s2, v1 s_delay_alu instid0(VALU_DEP_2) v_mov_b32_e32 v0, v3 s_branch .LBB0_3 .p2align 6 .LBB0_2: ; in Loop: Header=BB0_3 Depth=1 s_or_b32 exec_lo, exec_lo, s2 s_add_i32 s3, s3, -1 v_add_nc_u32_e32 v2, 1, v2 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_cmp_eq_u32 s3, 0 s_cbranch_scc1 .LBB0_6 .LBB0_3: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cmp_lt_i32_e32 vcc_lo, -1, v2 s_waitcnt lgkmcnt(0) v_cmp_gt_i32_e64 s2, s8, v2 s_and_b32 s9, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s2, s9 s_cbranch_execz .LBB0_2 ; %bb.4: ; in Loop: Header=BB0_3 Depth=1 v_lshlrev_b64 v[4:5], 2, v[2:3] s_load_b32 s9, s[6:7], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, s4, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo global_load_b32 v4, v[4:5], off s_waitcnt vmcnt(0) lgkmcnt(0) v_fmac_f32_e32 v0, s9, v4 s_branch .LBB0_2 .LBB0_5: v_mov_b32_e32 v0, 0 .LBB0_6: ; %Flow37 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v1, vcc_lo, s0, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo global_store_b32 v[1:2], v0, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z27convolution_1D_basic_kernalPfS_S_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z27convolution_1D_basic_kernalPfS_S_ii, .Lfunc_end0-_Z27convolution_1D_basic_kernalPfS_S_ii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 288 ; NumSgprs: 18 ; NumVgprs: 6 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 6 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z27convolution_1D_basic_kernalPfS_S_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z27convolution_1D_basic_kernalPfS_S_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "a1241984ee469fb49a113ad95e7b4f8099ab4062.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z42__device_stub__convolution_1D_basic_kernalPfS_S_ii # -- Begin function _Z42__device_stub__convolution_1D_basic_kernalPfS_S_ii .p2align 4, 0x90 .type _Z42__device_stub__convolution_1D_basic_kernalPfS_S_ii,@function _Z42__device_stub__convolution_1D_basic_kernalPfS_S_ii: # @_Z42__device_stub__convolution_1D_basic_kernalPfS_S_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %rsp, %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z27convolution_1D_basic_kernalPfS_S_ii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z42__device_stub__convolution_1D_basic_kernalPfS_S_ii, .Lfunc_end0-_Z42__device_stub__convolution_1D_basic_kernalPfS_S_ii .cfi_endproc # -- End function .globl _Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii # -- Begin function _Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii .p2align 4, 0x90 .type _Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii,@function _Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii: # @_Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii .cfi_startproc # %bb.0: movl $0, (%rdx) testl %r9d, %r9d jle .LBB1_10 # %bb.1: # %.lr.ph24 pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %ecx, %eax shrl $31, %eax addl %ecx, %eax sarl %eax negl %eax movslq %r8d, %r8 movl %r9d, %r9d movl %ecx, %r10d xorl %r11d, %r11d jmp .LBB1_2 .p2align 4, 0x90 .LBB1_8: # %._crit_edge # in Loop: Header=BB1_2 Depth=1 incq %r11 incl %eax cmpq %r9, %r11 je .LBB1_9 .LBB1_2: # =>This Loop Header: Depth=1 # Child Loop BB1_4 Depth 2 testl %ecx, %ecx jle .LBB1_8 # %bb.3: # %.lr.ph # in Loop: Header=BB1_2 Depth=1 movslq %eax, %rbx leaq (,%rbx,4), %r14 movl (%rdx), %ebp movq (%rsi), %r15 addq (%rdi), %r14 xorl %r12d, %r12d jmp .LBB1_4 .p2align 4, 0x90 .LBB1_7: # in Loop: Header=BB1_4 Depth=2 incq %r12 cmpq %r12, %r10 je .LBB1_8 .LBB1_4: # Parent Loop BB1_2 Depth=1 # => This Inner Loop Header: Depth=2 movq %rbx, %r13 addq %r12, %r13 js .LBB1_7 # %bb.5: # in Loop: Header=BB1_4 Depth=2 cmpq %r8, %r13 jge .LBB1_7 # %bb.6: # in Loop: Header=BB1_4 Depth=2 movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero mulss (%r15,%r12,4), %xmm0 xorps %xmm1, %xmm1 cvtsi2ss %ebp, %xmm1 addss %xmm0, %xmm1 cvttss2si %xmm1, %ebp movl %ebp, (%rdx) jmp .LBB1_7 .LBB1_9: popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 .cfi_restore %rbx .cfi_restore %r12 .cfi_restore %r13 .cfi_restore %r14 .cfi_restore %r15 .cfi_restore %rbp .LBB1_10: # %._crit_edge25 retq .Lfunc_end1: .size _Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii, .Lfunc_end1-_Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii .cfi_endproc # -- End function .globl _Z10checkArrayRSt6vectorIfSaIfEERii # -- Begin function _Z10checkArrayRSt6vectorIfSaIfEERii .p2align 4, 0x90 .type _Z10checkArrayRSt6vectorIfSaIfEERii,@function _Z10checkArrayRSt6vectorIfSaIfEERii: # @_Z10checkArrayRSt6vectorIfSaIfEERii .cfi_startproc # %bb.0: movl $0, (%rsi) testl %edx, %edx jle .LBB2_4 # %bb.1: # %.lr.ph movl (%rsi), %ecx movq (%rdi), %rax movl %edx, %edx xorl %edi, %edi .p2align 4, 0x90 .LBB2_2: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtsi2ss %ecx, %xmm0 addss (%rax,%rdi,4), %xmm0 cvttss2si %xmm0, %ecx incq %rdi cmpq %rdi, %rdx jne .LBB2_2 # %bb.3: # %._crit_edge movl %ecx, (%rsi) .LBB2_4: retq .Lfunc_end2: .size _Z10checkArrayRSt6vectorIfSaIfEERii, .Lfunc_end2-_Z10checkArrayRSt6vectorIfSaIfEERii .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $1640, %rsp # imm = 0x668 .cfi_def_cfa_offset 1680 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 .cfi_escape 0x2e, 0x00 leaq 168(%rsp), %rdi xorl %esi, %esi callq hipGetDevicePropertiesR0600 testl %eax, %eax je .LBB3_3 # %bb.1: .cfi_escape 0x2e, 0x00 movl $.L.str, %edi movl $.L.str.1, %esi movl $77, %edx jmp .LBB3_2 .LBB3_3: .cfi_escape 0x2e, 0x00 leaq 168(%rsp), %rdx movl $.L.str.2, %edi xorl %esi, %esi xorl %eax, %eax callq printf .cfi_escape 0x2e, 0x00 xorl %edi, %edi callq hipSetDevice testl %eax, %eax je .LBB3_5 # %bb.4: .cfi_escape 0x2e, 0x00 movl $.L.str, %edi movl $.L.str.1, %esi movl $79, %edx .LBB3_2: xorl %eax, %eax callq printf movl $1, %eax .LBB3_45: addq $1640, %rsp # imm = 0x668 .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB3_5: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit .cfi_def_cfa_offset 1680 .cfi_escape 0x2e, 0x00 movl $.L.str.3, %edi movl $2000, %esi # imm = 0x7D0 xorl %eax, %eax callq printf .cfi_escape 0x2e, 0x00 movl $.L.str.4, %edi movl $500, %esi # imm = 0x1F4 xorl %eax, %eax callq printf .cfi_escape 0x2e, 0x00 movl $.L.str.5, %edi movl $10, %esi xorl %eax, %eax callq printf .cfi_escape 0x2e, 0x00 movl $8000, %edi # imm = 0x1F40 callq _Znwm movq %rax, %rbx .cfi_escape 0x2e, 0x00 movl $8000, %edx # imm = 0x1F40 movq %rax, %rdi xorl %esi, %esi callq memset@PLT .Ltmp0: .cfi_escape 0x2e, 0x00 movl $2000, %edi # imm = 0x7D0 callq _Znwm .Ltmp1: # %bb.6: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit56 movq %rax, %r14 .cfi_escape 0x2e, 0x00 movl $2000, %edx # imm = 0x7D0 movq %rax, %rdi xorl %esi, %esi callq memset@PLT .Ltmp3: .cfi_escape 0x2e, 0x00 movl $9996, %edi # imm = 0x270C callq _Znwm .Ltmp4: # %bb.7: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit57 movq %rax, %r15 .cfi_escape 0x2e, 0x00 xorl %r12d, %r12d movl $9996, %edx # imm = 0x270C movq %rax, %rdi xorl %esi, %esi callq memset@PLT .cfi_escape 0x2e, 0x00 xorl %edi, %edi callq time .cfi_escape 0x2e, 0x00 movl %eax, %edi callq srand .p2align 4, 0x90 .LBB3_8: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 .cfi_escape 0x2e, 0x00 callq rand cltq imulq $954437177, %rax, %rcx # imm = 0x38E38E39 movq %rcx, %rdx shrq $63, %rdx sarq $33, %rcx addl %edx, %ecx leal (%rcx,%rcx,8), %ecx subl %ecx, %eax xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 movss %xmm0, (%rbx,%r12) addq $4, %r12 cmpq $8000, %r12 # imm = 0x1F40 jne .LBB3_8 # %bb.9: # %.lr.ph.i59.preheader xorl %r12d, %r12d .p2align 4, 0x90 .LBB3_10: # %.lr.ph.i59 # =>This Inner Loop Header: Depth=1 .cfi_escape 0x2e, 0x00 callq rand cltq imulq $954437177, %rax, %rcx # imm = 0x38E38E39 movq %rcx, %rdx shrq $63, %rdx sarq $33, %rcx addl %edx, %ecx leal (%rcx,%rcx,8), %ecx subl %ecx, %eax xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 movss %xmm0, (%r14,%r12) addq $4, %r12 cmpq $2000, %r12 # imm = 0x7D0 jne .LBB3_10 # %bb.11: # %_ZSt8generateIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEEZ4mainEUlvE0_EvT_S8_T0_.exit .Ltmp6: .cfi_escape 0x2e, 0x00 leaq 32(%rsp), %rdi movl $8000, %esi # imm = 0x1F40 callq hipMalloc .Ltmp7: # %bb.12: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit .Ltmp8: .cfi_escape 0x2e, 0x00 leaq 24(%rsp), %rdi movl $2000, %esi # imm = 0x7D0 callq hipMalloc .Ltmp9: # %bb.13: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit61 .Ltmp10: .cfi_escape 0x2e, 0x00 leaq 16(%rsp), %rdi movl $9996, %esi # imm = 0x270C callq hipMalloc .Ltmp11: # %bb.14: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit62 movq 32(%rsp), %rdi .Ltmp12: .cfi_escape 0x2e, 0x00 movl $8000, %edx # imm = 0x1F40 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy .Ltmp13: # %bb.15: movq 24(%rsp), %rdi .Ltmp14: .cfi_escape 0x2e, 0x00 movl $2000, %edx # imm = 0x7D0 movq %r14, %rsi movl $1, %ecx callq hipMemcpy .Ltmp15: # %bb.16: .Ltmp17: .cfi_escape 0x2e, 0x00 leaq 8(%rsp), %rdi callq hipEventCreate .Ltmp18: # %bb.17: .Ltmp19: .cfi_escape 0x2e, 0x00 movq %rsp, %rdi callq hipEventCreate .Ltmp20: # %bb.18: movq 8(%rsp), %rdi .Ltmp21: .cfi_escape 0x2e, 0x00 xorl %esi, %esi callq hipEventRecord .Ltmp22: # %bb.19: .Ltmp23: .cfi_escape 0x2e, 0x00 movabsq $4294967306, %rdi # imm = 0x10000000A movabsq $4294967496, %rdx # imm = 0x1000000C8 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration .Ltmp24: # %bb.20: testl %eax, %eax jne .LBB3_23 # %bb.21: movq 32(%rsp), %rax movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq %rax, 120(%rsp) movq %rcx, 112(%rsp) movq %rdx, 104(%rsp) movl $401, 52(%rsp) # imm = 0x191 movl $200, 48(%rsp) leaq 120(%rsp), %rax movq %rax, 128(%rsp) leaq 112(%rsp), %rax movq %rax, 136(%rsp) leaq 104(%rsp), %rax movq %rax, 144(%rsp) leaq 52(%rsp), %rax movq %rax, 152(%rsp) leaq 48(%rsp), %rax movq %rax, 160(%rsp) .Ltmp25: .cfi_escape 0x2e, 0x00 leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration .Ltmp26: # %bb.22: # %.noexc movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d .Ltmp27: .cfi_escape 0x2e, 0x10 leaq 128(%rsp), %r9 movl $_Z27convolution_1D_basic_kernalPfS_S_ii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .Ltmp28: .LBB3_23: movq 16(%rsp), %rsi .Ltmp29: .cfi_escape 0x2e, 0x00 movl $9996, %edx # imm = 0x270C movq %r15, %rdi movl $2, %ecx callq hipMemcpy .Ltmp30: # %bb.24: movq (%rsp), %rdi .Ltmp31: .cfi_escape 0x2e, 0x00 xorl %esi, %esi callq hipEventRecord .Ltmp32: # %bb.25: movq (%rsp), %rdi .Ltmp33: .cfi_escape 0x2e, 0x00 callq hipEventSynchronize .Ltmp34: # %bb.26: movq 8(%rsp), %rsi movq (%rsp), %rdx .Ltmp35: .cfi_escape 0x2e, 0x00 leaq 44(%rsp), %rdi callq hipEventElapsedTime .Ltmp36: # %bb.27: .Ltmp37: .cfi_escape 0x2e, 0x00 leaq 8(%rsp), %rdi callq hipEventCreate .Ltmp38: # %bb.28: .Ltmp39: .cfi_escape 0x2e, 0x00 movq %rsp, %rdi callq hipEventCreate .Ltmp40: # %bb.29: movq 8(%rsp), %rdi .Ltmp41: .cfi_escape 0x2e, 0x00 xorl %r12d, %r12d xorl %esi, %esi callq hipEventRecord .Ltmp42: # %bb.30: # %.preheader.preheader movq %rbx, %rax xorl %ecx, %ecx jmp .LBB3_31 .p2align 4, 0x90 .LBB3_35: # %._crit_edge.i # in Loop: Header=BB3_31 Depth=1 incq %rcx addq $4, %rax cmpq $2499, %rcx # imm = 0x9C3 je .LBB3_36 .LBB3_31: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB3_32 Depth 2 movq $-200, %rdx jmp .LBB3_32 .p2align 4, 0x90 .LBB3_34: # in Loop: Header=BB3_32 Depth=2 incq %rdx cmpq $201, %rdx je .LBB3_35 .LBB3_32: # Parent Loop BB3_31 Depth=1 # => This Inner Loop Header: Depth=2 leaq (%rcx,%rdx), %rsi cmpq $199, %rsi ja .LBB3_34 # %bb.33: # in Loop: Header=BB3_32 Depth=2 movss (%rax,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero mulss 800(%r14,%rdx,4), %xmm0 xorps %xmm1, %xmm1 cvtsi2ss %r12d, %xmm1 addss %xmm0, %xmm1 cvttss2si %xmm1, %r12d jmp .LBB3_34 .LBB3_36: # %_Z31convolution_1D_basic_kernal_CPURSt6vectorIfSaIfEES2_Riiii.exit movq (%rsp), %rdi .Ltmp43: .cfi_escape 0x2e, 0x00 xorl %esi, %esi callq hipEventRecord .Ltmp44: # %bb.37: movq (%rsp), %rdi .Ltmp45: .cfi_escape 0x2e, 0x00 callq hipEventSynchronize .Ltmp46: # %bb.38: movq 8(%rsp), %rsi movq (%rsp), %rdx .Ltmp47: .cfi_escape 0x2e, 0x00 leaq 40(%rsp), %rdi callq hipEventElapsedTime .Ltmp48: # %bb.39: movss 44(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .cfi_escape 0x2e, 0x00 movl $.L.str.6, %edi movb $1, %al callq printf movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .cfi_escape 0x2e, 0x00 movl $.L.str.7, %edi movb $1, %al callq printf xorl %eax, %eax xorl %ecx, %ecx .p2align 4, 0x90 .LBB3_40: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtsi2ss %ecx, %xmm0 addss (%r15,%rax,4), %xmm0 cvttss2si %xmm0, %ecx incq %rax cmpq $2499, %rax # imm = 0x9C3 jne .LBB3_40 # %bb.41: # %_Z10checkArrayRSt6vectorIfSaIfEERii.exit cmpl %ecx, %r12d movl $.Lstr.1, %eax movl $.Lstr, %edi cmoveq %rax, %rdi .cfi_escape 0x2e, 0x00 callq puts@PLT movq 32(%rsp), %rdi .Ltmp50: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp51: # %bb.42: movq 24(%rsp), %rdi .Ltmp52: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp53: # %bb.43: movq 16(%rsp), %rdi .Ltmp54: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp55: # %bb.44: # %_ZNSt6vectorIfSaIfEED2Ev.exit .cfi_escape 0x2e, 0x00 movq %r15, %rdi callq _ZdlPv .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _ZdlPv .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _ZdlPv xorl %eax, %eax jmp .LBB3_45 .LBB3_47: .Ltmp5: movq %rax, %r12 jmp .LBB3_51 .LBB3_46: .Ltmp2: movq %rax, %r12 jmp .LBB3_52 .LBB3_53: .Ltmp56: jmp .LBB3_50 .LBB3_48: .Ltmp16: jmp .LBB3_50 .LBB3_49: .Ltmp49: .LBB3_50: # %_ZNSt6vectorIfSaIfEED2Ev.exit78 movq %rax, %r12 .cfi_escape 0x2e, 0x00 movq %r15, %rdi callq _ZdlPv .LBB3_51: # %_ZNSt6vectorIfSaIfEED2Ev.exit82 .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq _ZdlPv .LBB3_52: # %_ZNSt6vectorIfSaIfEED2Ev.exit84 .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq _ZdlPv .cfi_escape 0x2e, 0x00 movq %r12, %rdi callq _Unwind_Resume@PLT .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table3: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1 .uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2 .byte 0 # On action: cleanup .uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4 .uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5 .byte 0 # On action: cleanup .uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Ltmp15-.Ltmp6 # Call between .Ltmp6 and .Ltmp15 .uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16 .byte 0 # On action: cleanup .uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 7 << .uleb128 .Ltmp48-.Ltmp17 # Call between .Ltmp17 and .Ltmp48 .uleb128 .Ltmp49-.Lfunc_begin0 # jumps to .Ltmp49 .byte 0 # On action: cleanup .uleb128 .Ltmp50-.Lfunc_begin0 # >> Call Site 8 << .uleb128 .Ltmp55-.Ltmp50 # Call between .Ltmp50 and .Ltmp55 .uleb128 .Ltmp56-.Lfunc_begin0 # jumps to .Ltmp56 .byte 0 # On action: cleanup .uleb128 .Ltmp55-.Lfunc_begin0 # >> Call Site 9 << .uleb128 .Lfunc_end3-.Ltmp55 # Call between .Ltmp55 and .Lfunc_end3 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .p2align 2, 0x0 # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z27convolution_1D_basic_kernalPfS_S_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z27convolution_1D_basic_kernalPfS_S_ii,@object # @_Z27convolution_1D_basic_kernalPfS_S_ii .section .rodata,"a",@progbits .globl _Z27convolution_1D_basic_kernalPfS_S_ii .p2align 3, 0x0 _Z27convolution_1D_basic_kernalPfS_S_ii: .quad _Z42__device_stub__convolution_1D_basic_kernalPfS_S_ii .size _Z27convolution_1D_basic_kernalPfS_S_ii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Error at %s:%d\n" .size .L.str, 16 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "/home/ubuntu/Datasets/Stack_v2_cuda-hip-as/a1241984ee469fb49a113ad95e7b4f8099ab4062.hip" .size .L.str.1, 88 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Using Device %d: %s\n" .size .L.str.2, 21 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "size of i array: %d\n" .size .L.str.3, 21 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "size of k array: %d\n" .size .L.str.4, 21 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "size of block: %d\n" .size .L.str.5, 19 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Compute time on GPU: %3.6f ms \n" .size .L.str.6, 32 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Compute time on CPU: %3.6f ms \n" .size .L.str.7, 32 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z27convolution_1D_basic_kernalPfS_S_ii" .size .L__unnamed_1, 40 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Check Result: Arrays do not match" .size .Lstr, 34 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "Check Result: Arrays matched" .size .Lstr.1, 29 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z42__device_stub__convolution_1D_basic_kernalPfS_S_ii .addrsig_sym __gxx_personality_v0 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Unwind_Resume .addrsig_sym _Z27convolution_1D_basic_kernalPfS_S_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80
.file "tmpxft_000de37a_00000000-6_489b3831788844d4353556bee9ad94599d83a90a.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2059: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2059: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2082: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2082: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "489b3831788844d4353556bee9ad94599d83a90a.hip" .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
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code for sm_80 Function : sgemm_nn_vec_128x32 .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R4, SR_TID.X ; HFMA2.MMA R7, -RZ, RZ, 1.875, 0 ; MOV R3, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IADD3 R0, -R4, 0x7f, RZ ; STS [R4.X4], R7 ; IMAD.WIDE R2, R4, R3, c[0x0][0x178] ; LDS R5, [R0.X4] ; STG.E [R2.64], R5 ; EXIT ; BRA 0xb0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0003380d_00000000-6_2e14101331549c72b0296c0c59c0a39e079d1c94.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z60__device_stub__Z19sgemm_nn_vec_128x32PjPKfS1_PfiiiiiiffiiiiiPjPKfS1_Pfiiiiiiffiiiii .type _Z60__device_stub__Z19sgemm_nn_vec_128x32PjPKfS1_PfiiiiiiffiiiiiPjPKfS1_Pfiiiiiiffiiiii, @function _Z60__device_stub__Z19sgemm_nn_vec_128x32PjPKfS1_PfiiiiiiffiiiiiPjPKfS1_Pfiiiiiiffiiiii: .LFB2051: .cfi_startproc endbr64 subq $264, %rsp .cfi_def_cfa_offset 272 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movl %r8d, 12(%rsp) movl %r9d, 8(%rsp) movss %xmm0, 4(%rsp) movss %xmm1, (%rsp) movq %fs:40, %rax movq %rax, 248(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 12(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) leaq 272(%rsp), %rax movq %rax, 160(%rsp) leaq 280(%rsp), %rax movq %rax, 168(%rsp) leaq 288(%rsp), %rax movq %rax, 176(%rsp) leaq 296(%rsp), %rax movq %rax, 184(%rsp) leaq 4(%rsp), %rax movq %rax, 192(%rsp) movq %rsp, %rax movq %rax, 200(%rsp) leaq 304(%rsp), %rax movq %rax, 208(%rsp) leaq 312(%rsp), %rax movq %rax, 216(%rsp) leaq 320(%rsp), %rax movq %rax, 224(%rsp) leaq 328(%rsp), %rax movq %rax, 232(%rsp) leaq 336(%rsp), %rax movq %rax, 240(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 248(%rsp), %rax subq %fs:40, %rax jne .L8 addq $264, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 280 pushq 56(%rsp) .cfi_def_cfa_offset 288 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq sgemm_nn_vec_128x32(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 272 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z60__device_stub__Z19sgemm_nn_vec_128x32PjPKfS1_PfiiiiiiffiiiiiPjPKfS1_Pfiiiiiiffiiiii, .-_Z60__device_stub__Z19sgemm_nn_vec_128x32PjPKfS1_PfiiiiiiffiiiiiPjPKfS1_Pfiiiiiiffiiiii .globl sgemm_nn_vec_128x32 .type sgemm_nn_vec_128x32, @function sgemm_nn_vec_128x32: .LFB2052: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 56 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 64 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 72 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 80 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 88 movl 88(%rsp), %eax pushq %rax .cfi_def_cfa_offset 96 call _Z60__device_stub__Z19sgemm_nn_vec_128x32PjPKfS1_PfiiiiiiffiiiiiPjPKfS1_Pfiiiiiiffiiiii addq $88, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size sgemm_nn_vec_128x32, .-sgemm_nn_vec_128x32 .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "sgemm_nn_vec_128x32" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq sgemm_nn_vec_128x32(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected sgemm_nn_vec_128x32 ; -- Begin function sgemm_nn_vec_128x32 .globl sgemm_nn_vec_128x32 .p2align 8 .type sgemm_nn_vec_128x32,@function sgemm_nn_vec_128x32: ; @sgemm_nn_vec_128x32 ; %bb.0: v_xor_b32_e32 v1, 0x7f, v0 v_lshlrev_b32_e32 v0, 2, v0 v_mov_b32_e32 v2, 1.0 s_load_b64 s[0:1], s[0:1], 0x18 s_delay_alu instid0(VALU_DEP_3) v_lshlrev_b32_e32 v1, 2, v1 ds_store_b32 v0, v2 ds_load_b32 v1, v1 s_waitcnt lgkmcnt(0) global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel sgemm_nn_vec_128x32 .amdhsa_group_segment_fixed_size 20752 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 84 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 2 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size sgemm_nn_vec_128x32, .Lfunc_end0-sgemm_nn_vec_128x32 ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 72 ; NumSgprs: 2 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 20752 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 2 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 6 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: by_value - .offset: 44 .size: 4 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: by_value - .offset: 52 .size: 4 .value_kind: by_value - .offset: 56 .size: 4 .value_kind: by_value - .offset: 60 .size: 4 .value_kind: by_value - .offset: 64 .size: 4 .value_kind: by_value - .offset: 68 .size: 4 .value_kind: by_value - .offset: 72 .size: 4 .value_kind: by_value - .offset: 76 .size: 4 .value_kind: by_value - .offset: 80 .size: 4 .value_kind: by_value .group_segment_fixed_size: 20752 .kernarg_segment_align: 8 .kernarg_segment_size: 84 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 128 .name: sgemm_nn_vec_128x32 .private_segment_fixed_size: 0 .sgpr_count: 2 .sgpr_spill_count: 0 .symbol: sgemm_nn_vec_128x32.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "2e14101331549c72b0296c0c59c0a39e079d1c94.hip" .globl __device_stub__sgemm_nn_vec_128x32 # -- Begin function __device_stub__sgemm_nn_vec_128x32 .p2align 4, 0x90 .type __device_stub__sgemm_nn_vec_128x32,@function __device_stub__sgemm_nn_vec_128x32: # @__device_stub__sgemm_nn_vec_128x32 .cfi_startproc # %bb.0: subq $232, %rsp .cfi_def_cfa_offset 240 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movl %r8d, 12(%rsp) movl %r9d, 8(%rsp) movss %xmm0, 4(%rsp) movss %xmm1, (%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) leaq 8(%rsp), %rax movq %rax, 136(%rsp) leaq 240(%rsp), %rax movq %rax, 144(%rsp) leaq 248(%rsp), %rax movq %rax, 152(%rsp) leaq 256(%rsp), %rax movq %rax, 160(%rsp) leaq 264(%rsp), %rax movq %rax, 168(%rsp) leaq 4(%rsp), %rax movq %rax, 176(%rsp) movq %rsp, %rax movq %rax, 184(%rsp) leaq 272(%rsp), %rax movq %rax, 192(%rsp) leaq 280(%rsp), %rax movq %rax, 200(%rsp) leaq 288(%rsp), %rax movq %rax, 208(%rsp) leaq 296(%rsp), %rax movq %rax, 216(%rsp) leaq 304(%rsp), %rax movq %rax, 224(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 96(%rsp), %r9 movl $sgemm_nn_vec_128x32, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $248, %rsp .cfi_adjust_cfa_offset -248 retq .Lfunc_end0: .size __device_stub__sgemm_nn_vec_128x32, .Lfunc_end0-__device_stub__sgemm_nn_vec_128x32 .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $sgemm_nn_vec_128x32, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type sgemm_nn_vec_128x32,@object # @sgemm_nn_vec_128x32 .section .rodata,"a",@progbits .globl sgemm_nn_vec_128x32 .p2align 3, 0x0 sgemm_nn_vec_128x32: .quad __device_stub__sgemm_nn_vec_128x32 .size sgemm_nn_vec_128x32, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "sgemm_nn_vec_128x32" .size .L__unnamed_1, 20 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __device_stub__sgemm_nn_vec_128x32 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym sgemm_nn_vec_128x32 .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z11forceKernelPdS_S_S_S_S_S_m .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R40, SR_CTAID.X ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x0], PT ; ULDC.64 UR6, c[0x0][0x118] ; CS2R R28, SRZ ; S2R R41, SR_TID.X ; CS2R R26, SRZ ; CS2R R24, SRZ ; IMAD R40, R40, c[0x0][0x0], R41 ; @!P0 BRA 0x2280 ; IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; IMAD.WIDE.U32 R22, R40, R17, c[0x0][0x160] ; IMAD.WIDE.U32 R20, R40.reuse, R17.reuse, c[0x0][0x168] ; LDG.E.64 R22, [R22.64] ; IMAD.WIDE.U32 R18, R40.reuse, R17.reuse, c[0x0][0x170] ; LDG.E.64 R20, [R20.64] ; IMAD.WIDE.U32 R16, R40, R17, c[0x0][0x178] ; LDG.E.64 R18, [R18.64] ; LDG.E.64 R16, [R16.64] ; CS2R R38, SRZ ; CS2R R24, SRZ ; CS2R R26, SRZ ; CS2R R28, SRZ ; IMAD.WIDE.U32 R2, R39, c[0x0][0x0], RZ ; IMAD R5, R38, c[0x0][0x0], RZ ; IADD3 R0, P0, R41, R2, RZ ; IMAD.IADD R14, R3, 0x1, R5 ; IMAD.SHL.U32 R8, R0, 0x8, RZ ; IMAD.X R5, RZ, RZ, R14, P0 ; IADD3 R4, P0, R8, c[0x0][0x160], RZ ; SHF.L.U64.HI R0, R0, 0x3, R5 ; IADD3 R6, P1, R8, c[0x0][0x168], RZ ; IADD3.X R5, R0, c[0x0][0x164], RZ, P0, !PT ; IADD3 R8, P2, R8, c[0x0][0x170], RZ ; IADD3.X R7, R0, c[0x0][0x16c], RZ, P1, !PT ; LDG.E.64 R4, [R4.64] ; IADD3.X R9, R0, c[0x0][0x174], RZ, P2, !PT ; LDG.E.64 R6, [R6.64] ; LDG.E.64 R8, [R8.64] ; IADD3 R11, P3, R2.reuse, c[0x0][0x0], RZ ; ISETP.GE.U32.AND P2, PT, R2.reuse, c[0x0][0x198], PT ; ULDC UR4, c[0x0][0x0] ; ISETP.GE.U32.AND P1, PT, R2, R11, PT ; IMAD.X R0, RZ, RZ, R14, P3 ; ISETP.GE.U32.AND.EX P2, PT, R14, c[0x0][0x19c], PT, P2 ; UIADD3 UR4, UP0, URZ, -UR4, URZ ; IADD3 R10, P4, R2, -c[0x0][0x198], RZ ; ISETP.GE.U32.OR.EX P1, PT, R14, R0, P2, P1 ; UIADD3.X UR5, URZ, -0x1, URZ, UP0, !UPT ; ISETP.GT.U32.AND P0, PT, R10, UR4, PT ; STS.64 [R41.X8], R4 ; STS.64 [R41.X8+0x2000], R6 ; IADD3.X R4, R14, ~c[0x0][0x19c], RZ, P4, !PT ; STS.64 [R41.X8+0x4000], R8 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GT.U32.AND.EX P0, PT, R4, UR5, PT, P0 ; SEL R11, R10, UR4, P0 ; SEL R4, R4, UR5, P0 ; @P1 BRA 0x2200 ; ISETP.GT.U32.AND P0, PT, R11, -0x4, PT ; IMAD.MOV R12, RZ, RZ, -R11 ; IMAD.MOV.U32 R15, RZ, RZ, R2 ; ISETP.GT.U32.AND.EX P0, PT, R4, -0x1, PT, P0 ; IMAD.MOV.U32 R13, RZ, RZ, RZ ; LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ; @P0 BRA 0x1550 ; IADD3 R11, P0, R12, R11, RZ ; BSSY B0, 0x1550 ; IMAD.MOV.U32 R15, RZ, RZ, R2 ; IADD3 R11, P1, RZ, -R11, RZ ; IMAD.X R10, RZ, RZ, R4, P0 ; IMAD.MOV.U32 R13, RZ, RZ, RZ ; IMAD.X R10, RZ, RZ, ~R10, P1 ; ISETP.NE.U32.AND P1, PT, R15, R40, PT ; IADD3 R11, P0, R11, -0x4, RZ ; ISETP.NE.AND.EX P1, PT, R14, RZ, PT, P1 ; IADD3.X R10, R10, -0x1, RZ, P0, !PT ; ISETP.NE.U32.AND P0, PT, R11, RZ, PT ; ISETP.NE.AND.EX P0, PT, R10, RZ, PT, P0 ; @!P1 BRA 0x8c0 ; LDS.64 R32, [R13.X8+0x2000] ; IMAD.MOV.U32 R44, RZ, RZ, 0x0 ; WARPSYNC 0xffffffff ; IMAD.MOV.U32 R45, RZ, RZ, 0x3fd80000 ; LDS.64 R34, [R13.X8] ; LEA R36, P2, R15.reuse, c[0x0][0x178], 0x3 ; BSSY B1, 0x750 ; LDS.64 R30, [R13.X8+0x4000] ; LEA.HI.X R37, R15, c[0x0][0x17c], R14, 0x3, P2 ; DADD R32, R20, -R32 ; DADD R34, R22, -R34 ; DMUL R2, R32, R32 ; DADD R30, R18, -R30 ; DFMA R2, R34, R34, R2 ; DFMA R8, R30, R30, R2 ; MUFU.RSQ64H R43, R9 ; IADD3 R42, R9, -0x3500000, RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.U32.AND P1, PT, R42, 0x7ca00000, PT ; DMUL R2, R42, R42 ; DFMA R2, R8, -R2, 1 ; DFMA R44, R2, R44, 0.5 ; DMUL R2, R42, R2 ; DFMA R44, R44, R2, R42 ; DMUL R4, R8, R44 ; IADD3 R3, R45, -0x100000, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R44 ; DFMA R6, R4, -R4, R8 ; DFMA R46, R6, R2, R4 ; @!P1 BRA 0x740 ; IMAD.MOV.U32 R0, RZ, RZ, R42 ; MOV R42, 0x720 ; IMAD.MOV.U32 R2, RZ, RZ, R44 ; CALL.REL.NOINC 0x2650 ; IMAD.MOV.U32 R46, RZ, RZ, R0 ; IMAD.MOV.U32 R47, RZ, RZ, R3 ; BSYNC B1 ; DMUL R4, R46, R46.reuse ; BSSY B1, 0x860 ; DMUL R4, R4, R46 ; MUFU.RCP64H R3, R5 ; IADD3 R2, R5, 0x300402, RZ ; FSETP.GEU.AND P1, PT, |R2|, 5.8789094863358348022e-39, PT ; DFMA R6, -R4, R2, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R2, R6, R2 ; DFMA R8, -R4, R6, 1 ; DFMA R2, R6, R8, R6 ; @P1 BRA 0x850 ; LOP3.LUT R2, R5, 0x7fffffff, RZ, 0xc0, !PT ; MOV R0, 0x850 ; IADD3 R2, R2, -0x100000, RZ ; CALL.REL.NOINC 0x23a0 ; BSYNC B1 ; LDG.E.64 R36, [R36.64] ; DMUL R4, R16, R36 ; DMUL R2, R4, R2 ; DFMA R28, R34, R2, R28 ; DFMA R26, R32, R2, R26 ; DFMA R24, R30, R2, R24 ; IADD3 R3, P2, R15, 0x1, RZ ; ISETP.NE.U32.AND P1, PT, R3, R40, PT ; IMAD.X R0, RZ, RZ, R14, P2 ; ISETP.NE.AND.EX P1, PT, R0, RZ, PT, P1 ; @!P1 BRA 0xcd0 ; LDS.64 R32, [R13.X8+0x2008] ; IMAD.MOV.U32 R44, RZ, RZ, 0x0 ; WARPSYNC 0xffffffff ; IMAD.MOV.U32 R45, RZ, RZ, 0x3fd80000 ; LDS.64 R34, [R13.X8+0x8] ; LEA R36, P2, R15.reuse, c[0x0][0x178], 0x3 ; BSSY B1, 0xb60 ; LDS.64 R30, [R13.X8+0x4008] ; LEA.HI.X R37, R15, c[0x0][0x17c], R14, 0x3, P2 ; DADD R32, R20, -R32 ; DADD R34, R22, -R34 ; DMUL R2, R32, R32 ; DADD R30, R18, -R30 ; DFMA R2, R34, R34, R2 ; DFMA R8, R30, R30, R2 ; MUFU.RSQ64H R43, R9 ; IADD3 R42, R9, -0x3500000, RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.U32.AND P1, PT, R42, 0x7ca00000, PT ; DMUL R2, R42, R42 ; DFMA R2, R8, -R2, 1 ; DFMA R44, R2, R44, 0.5 ; DMUL R2, R42, R2 ; DFMA R44, R44, R2, R42 ; DMUL R4, R8, R44 ; IADD3 R3, R45, -0x100000, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R44 ; DFMA R6, R4, -R4, R8 ; DFMA R46, R6, R2, R4 ; @!P1 BRA 0xb50 ; IMAD.MOV.U32 R0, RZ, RZ, R42 ; MOV R42, 0xb30 ; IMAD.MOV.U32 R2, RZ, RZ, R44 ; CALL.REL.NOINC 0x2650 ; IMAD.MOV.U32 R46, RZ, RZ, R0 ; IMAD.MOV.U32 R47, RZ, RZ, R3 ; BSYNC B1 ; DMUL R4, R46, R46.reuse ; BSSY B1, 0xc70 ; DMUL R4, R4, R46 ; MUFU.RCP64H R3, R5 ; IADD3 R2, R5, 0x300402, RZ ; FSETP.GEU.AND P1, PT, |R2|, 5.8789094863358348022e-39, PT ; DFMA R6, -R4, R2, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R2, R6, R2 ; DFMA R8, -R4, R6, 1 ; DFMA R2, R6, R8, R6 ; @P1 BRA 0xc60 ; LOP3.LUT R2, R5, 0x7fffffff, RZ, 0xc0, !PT ; MOV R0, 0xc60 ; IADD3 R2, R2, -0x100000, RZ ; CALL.REL.NOINC 0x23a0 ; BSYNC B1 ; LDG.E.64 R36, [R36.64+0x8] ; DMUL R4, R16, R36 ; DMUL R2, R4, R2 ; DFMA R28, R34, R2, R28 ; DFMA R26, R32, R2, R26 ; DFMA R24, R30, R2, R24 ; IADD3 R3, P2, R15, 0x2, RZ ; ISETP.NE.U32.AND P1, PT, R3, R40, PT ; IMAD.X R0, RZ, RZ, R14, P2 ; ISETP.NE.AND.EX P1, PT, R0, RZ, PT, P1 ; @!P1 BRA 0x10e0 ; LDS.64 R30, [R13.X8+0x2010] ; IMAD.MOV.U32 R44, RZ, RZ, 0x0 ; WARPSYNC 0xffffffff ; IMAD.MOV.U32 R45, RZ, RZ, 0x3fd80000 ; LDS.64 R32, [R13.X8+0x10] ; LEA R36, P2, R15.reuse, c[0x0][0x178], 0x3 ; BSSY B1, 0xf70 ; LDS.64 R34, [R13.X8+0x4010] ; LEA.HI.X R37, R15, c[0x0][0x17c], R14, 0x3, P2 ; DADD R30, R20, -R30 ; DADD R32, R22, -R32 ; DMUL R2, R30, R30 ; DADD R34, R18, -R34 ; DFMA R2, R32, R32, R2 ; DFMA R8, R34, R34, R2 ; MUFU.RSQ64H R43, R9 ; IADD3 R42, R9, -0x3500000, RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.U32.AND P1, PT, R42, 0x7ca00000, PT ; DMUL R2, R42, R42 ; DFMA R2, R8, -R2, 1 ; DFMA R44, R2, R44, 0.5 ; DMUL R2, R42, R2 ; DFMA R44, R44, R2, R42 ; DMUL R4, R8, R44 ; IADD3 R3, R45, -0x100000, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R44 ; DFMA R6, R4, -R4, R8 ; DFMA R46, R6, R2, R4 ; @!P1 BRA 0xf60 ; IMAD.MOV.U32 R0, RZ, RZ, R42 ; MOV R42, 0xf40 ; IMAD.MOV.U32 R2, RZ, RZ, R44 ; CALL.REL.NOINC 0x2650 ; IMAD.MOV.U32 R46, RZ, RZ, R0 ; IMAD.MOV.U32 R47, RZ, RZ, R3 ; BSYNC B1 ; DMUL R4, R46, R46.reuse ; BSSY B1, 0x1080 ; DMUL R4, R4, R46 ; MUFU.RCP64H R3, R5 ; IADD3 R2, R5, 0x300402, RZ ; FSETP.GEU.AND P1, PT, |R2|, 5.8789094863358348022e-39, PT ; DFMA R6, -R4, R2, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R2, R6, R2 ; DFMA R8, -R4, R6, 1 ; DFMA R2, R6, R8, R6 ; @P1 BRA 0x1070 ; LOP3.LUT R2, R5, 0x7fffffff, RZ, 0xc0, !PT ; MOV R0, 0x1070 ; IADD3 R2, R2, -0x100000, RZ ; CALL.REL.NOINC 0x23a0 ; BSYNC B1 ; LDG.E.64 R36, [R36.64+0x10] ; DMUL R4, R16, R36 ; DMUL R2, R4, R2 ; DFMA R28, R32, R2, R28 ; DFMA R26, R30, R2, R26 ; DFMA R24, R34, R2, R24 ; IADD3 R3, P2, R15, 0x3, RZ ; ISETP.NE.U32.AND P1, PT, R3, R40, PT ; IMAD.X R0, RZ, RZ, R14, P2 ; ISETP.NE.AND.EX P1, PT, R0, RZ, PT, P1 ; @!P1 BRA 0x14f0 ; LDS.64 R30, [R13.X8+0x2018] ; IMAD.MOV.U32 R44, RZ, RZ, 0x0 ; WARPSYNC 0xffffffff ; IMAD.MOV.U32 R45, RZ, RZ, 0x3fd80000 ; LDS.64 R32, [R13.X8+0x18] ; LEA R36, P2, R15.reuse, c[0x0][0x178], 0x3 ; BSSY B1, 0x1380 ; LDS.64 R34, [R13.X8+0x4018] ; LEA.HI.X R37, R15, c[0x0][0x17c], R14, 0x3, P2 ; DADD R30, R20, -R30 ; DADD R32, R22, -R32 ; DMUL R2, R30, R30 ; DADD R34, R18, -R34 ; DFMA R2, R32, R32, R2 ; DFMA R8, R34, R34, R2 ; MUFU.RSQ64H R43, R9 ; IADD3 R42, R9, -0x3500000, RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.U32.AND P1, PT, R42, 0x7ca00000, PT ; DMUL R2, R42, R42 ; DFMA R2, R8, -R2, 1 ; DFMA R44, R2, R44, 0.5 ; DMUL R2, R42, R2 ; DFMA R44, R44, R2, R42 ; DMUL R4, R8, R44 ; IADD3 R3, R45, -0x100000, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R44 ; DFMA R6, R4, -R4, R8 ; DFMA R46, R6, R2, R4 ; @!P1 BRA 0x1370 ; IMAD.MOV.U32 R0, RZ, RZ, R42 ; MOV R42, 0x1350 ; IMAD.MOV.U32 R2, RZ, RZ, R44 ; CALL.REL.NOINC 0x2650 ; IMAD.MOV.U32 R46, RZ, RZ, R0 ; IMAD.MOV.U32 R47, RZ, RZ, R3 ; BSYNC B1 ; DMUL R4, R46, R46.reuse ; BSSY B1, 0x1490 ; DMUL R4, R4, R46 ; MUFU.RCP64H R3, R5 ; IADD3 R2, R5, 0x300402, RZ ; FSETP.GEU.AND P1, PT, |R2|, 5.8789094863358348022e-39, PT ; DFMA R6, -R4, R2, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R2, R6, R2 ; DFMA R8, -R4, R6, 1 ; DFMA R2, R6, R8, R6 ; @P1 BRA 0x1480 ; LOP3.LUT R2, R5, 0x7fffffff, RZ, 0xc0, !PT ; MOV R0, 0x1480 ; IADD3 R2, R2, -0x100000, RZ ; CALL.REL.NOINC 0x23a0 ; BSYNC B1 ; LDG.E.64 R36, [R36.64+0x18] ; DMUL R4, R16, R36 ; DMUL R2, R4, R2 ; DFMA R28, R32, R2, R28 ; DFMA R26, R30, R2, R26 ; DFMA R24, R34, R2, R24 ; IADD3 R15, P1, R15, 0x4, RZ ; IADD3 R13, R13, 0x4, RZ ; IMAD.X R14, RZ, RZ, R14, P1 ; @!P0 CALL.REL.NOINC 0x1540 ; BRA 0x490 ; BSYNC B0 ; ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; @!P0 BRA 0x2200 ; ISETP.NE.U32.AND P0, PT, R15, R40, PT ; ISETP.NE.AND.EX P0, PT, R14, RZ, PT, P0 ; @!P0 BRA 0x1970 ; LDS.64 R30, [R13.X8+0x2000] ; IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; WARPSYNC 0xffffffff ; IMAD.MOV.U32 R5, RZ, RZ, 0x3fd80000 ; LDS.64 R32, [R13.X8] ; LEA R34, P1, R15.reuse, c[0x0][0x178], 0x3 ; BSSY B0, 0x1800 ; LDS.64 R10, [R13.X8+0x4000] ; LEA.HI.X R35, R15, c[0x0][0x17c], R14, 0x3, P1 ; DADD R30, R20, -R30 ; DADD R32, R22, -R32 ; DMUL R2, R30, R30 ; DADD R10, R18, -R10 ; DFMA R2, R32, R32, R2 ; DFMA R8, R10, R10, R2 ; MUFU.RSQ64H R37, R9 ; IADD3 R36, R9, -0x3500000, RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.U32.AND P0, PT, R36, 0x7ca00000, PT ; DMUL R2, R36, R36 ; DFMA R2, R8, -R2, 1 ; DFMA R4, R2, R4, 0.5 ; DMUL R2, R36, R2 ; DFMA R44, R4, R2, R36 ; DMUL R4, R8, R44 ; IADD3 R3, R45, -0x100000, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R44 ; DFMA R6, R4, -R4, R8 ; DFMA R42, R6, R2, R4 ; @!P0 BRA 0x17f0 ; IMAD.MOV.U32 R2, RZ, RZ, R44 ; MOV R42, 0x17d0 ; IMAD.MOV.U32 R0, RZ, RZ, R36 ; CALL.REL.NOINC 0x2650 ; IMAD.MOV.U32 R42, RZ, RZ, R0 ; IMAD.MOV.U32 R43, RZ, RZ, R3 ; BSYNC B0 ; DMUL R4, R42, R42.reuse ; BSSY B0, 0x1910 ; DMUL R4, R4, R42 ; MUFU.RCP64H R3, R5 ; IADD3 R2, R5, 0x300402, RZ ; FSETP.GEU.AND P0, PT, |R2|, 5.8789094863358348022e-39, PT ; DFMA R6, -R4, R2, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R2, R6, R2 ; DFMA R8, -R4, R6, 1 ; DFMA R2, R6, R8, R6 ; @P0 BRA 0x1900 ; LOP3.LUT R2, R5, 0x7fffffff, RZ, 0xc0, !PT ; MOV R0, 0x1900 ; IADD3 R2, R2, -0x100000, RZ ; CALL.REL.NOINC 0x23a0 ; BSYNC B0 ; LDG.E.64 R34, [R34.64] ; DMUL R4, R16, R34 ; DMUL R2, R4, R2 ; DFMA R28, R32, R2, R28 ; DFMA R26, R30, R2, R26 ; DFMA R24, R10, R2, R24 ; ISETP.NE.U32.AND P0, PT, R12, 0x1, PT ; ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; @!P0 BRA 0x2200 ; IADD3 R3, P1, R15, 0x1, RZ ; ISETP.NE.U32.AND P0, PT, R3, R40, PT ; IMAD.X R0, RZ, RZ, R14, P1 ; ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; @!P0 BRA 0x1db0 ; LDS.64 R30, [R13.X8+0x2008] ; IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; WARPSYNC 0xffffffff ; IMAD.MOV.U32 R5, RZ, RZ, 0x3fd80000 ; LDS.64 R32, [R13.X8+0x8] ; LEA R34, P1, R15.reuse, c[0x0][0x178], 0x3 ; BSSY B0, 0x1c40 ; LDS.64 R10, [R13.X8+0x4008] ; LEA.HI.X R35, R15, c[0x0][0x17c], R14, 0x3, P1 ; DADD R30, R20, -R30 ; DADD R32, R22, -R32 ; DMUL R2, R30, R30 ; DADD R10, R18, -R10 ; DFMA R2, R32, R32, R2 ; DFMA R8, R10, R10, R2 ; MUFU.RSQ64H R37, R9 ; IADD3 R36, R9, -0x3500000, RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.U32.AND P0, PT, R36, 0x7ca00000, PT ; DMUL R2, R36, R36 ; DFMA R2, R8, -R2, 1 ; DFMA R4, R2, R4, 0.5 ; DMUL R2, R36, R2 ; DFMA R44, R4, R2, R36 ; DMUL R4, R8, R44 ; IADD3 R3, R45, -0x100000, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R44 ; DFMA R6, R4, -R4, R8 ; DFMA R42, R6, R2, R4 ; @!P0 BRA 0x1c30 ; IMAD.MOV.U32 R2, RZ, RZ, R44 ; MOV R42, 0x1c10 ; IMAD.MOV.U32 R0, RZ, RZ, R36 ; CALL.REL.NOINC 0x2650 ; IMAD.MOV.U32 R42, RZ, RZ, R0 ; IMAD.MOV.U32 R43, RZ, RZ, R3 ; BSYNC B0 ; DMUL R4, R42, R42.reuse ; BSSY B0, 0x1d50 ; DMUL R4, R4, R42 ; MUFU.RCP64H R3, R5 ; IADD3 R2, R5, 0x300402, RZ ; FSETP.GEU.AND P0, PT, |R2|, 5.8789094863358348022e-39, PT ; DFMA R6, -R4, R2, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R2, R6, R2 ; DFMA R8, -R4, R6, 1 ; DFMA R2, R6, R8, R6 ; @P0 BRA 0x1d40 ; LOP3.LUT R2, R5, 0x7fffffff, RZ, 0xc0, !PT ; MOV R0, 0x1d40 ; IADD3 R2, R2, -0x100000, RZ ; CALL.REL.NOINC 0x23a0 ; BSYNC B0 ; LDG.E.64 R34, [R34.64+0x8] ; DMUL R4, R16, R34 ; DMUL R2, R4, R2 ; DFMA R28, R32, R2, R28 ; DFMA R26, R30, R2, R26 ; DFMA R24, R10, R2, R24 ; IADD3 R3, P1, R15, 0x2, RZ ; ISETP.NE.U32.AND P0, PT, R3, R40, PT ; IMAD.X R0, RZ, RZ, R14, P1 ; ISETP.EQ.U32.AND P1, PT, R12, 0x2, PT ; ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; ISETP.EQ.OR.EX P0, PT, RZ, RZ, !P0, P1 ; @P0 BRA 0x2200 ; LDS.64 R30, [R13.X8+0x2010] ; IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; WARPSYNC 0xffffffff ; IMAD.MOV.U32 R5, RZ, RZ, 0x3fd80000 ; LDS.64 R32, [R13.X8+0x10] ; LEA R12, P1, R15.reuse, c[0x0][0x178], 0x3 ; BSSY B0, 0x2070 ; LDS.64 R10, [R13.X8+0x4010] ; LEA.HI.X R13, R15, c[0x0][0x17c], R14, 0x3, P1 ; DADD R30, R20, -R30 ; DADD R32, R22, -R32 ; DMUL R2, R30, R30 ; DADD R10, R18, -R10 ; DFMA R2, R32, R32, R2 ; DFMA R8, R10, R10, R2 ; MUFU.RSQ64H R35, R9 ; IADD3 R34, R9, -0x3500000, RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.U32.AND P0, PT, R34, 0x7ca00000, PT ; DMUL R2, R34, R34 ; DFMA R2, R8, -R2, 1 ; DFMA R4, R2, R4, 0.5 ; DMUL R2, R34, R2 ; DFMA R42, R4, R2, R34 ; DMUL R4, R8, R42 ; IADD3 R3, R43, -0x100000, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R42 ; DFMA R6, R4, -R4, R8 ; DFMA R36, R6, R2, R4 ; @!P0 BRA 0x2060 ; IMAD.MOV.U32 R2, RZ, RZ, R42 ; MOV R42, 0x2040 ; IMAD.MOV.U32 R0, RZ, RZ, R34 ; CALL.REL.NOINC 0x2650 ; IMAD.MOV.U32 R36, RZ, RZ, R0 ; IMAD.MOV.U32 R37, RZ, RZ, R3 ; BSYNC B0 ; DMUL R2, R36, R36.reuse ; BSSY B0, 0x21a0 ; DMUL R36, R2, R36 ; MUFU.RCP64H R3, R37 ; IADD3 R2, R37, 0x300402, RZ ; FSETP.GEU.AND P0, PT, |R2|, 5.8789094863358348022e-39, PT ; DFMA R4, -R36, R2, 1 ; DFMA R4, R4, R4, R4 ; DFMA R4, R2, R4, R2 ; DFMA R6, -R36, R4, 1 ; DFMA R2, R4, R6, R4 ; @P0 BRA 0x2190 ; LOP3.LUT R2, R37, 0x7fffffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R4, RZ, RZ, R36 ; MOV R0, 0x2190 ; IMAD.MOV.U32 R5, RZ, RZ, R37 ; IADD3 R2, R2, -0x100000, RZ ; CALL.REL.NOINC 0x23a0 ; BSYNC B0 ; LDG.E.64 R12, [R12.64+0x10] ; DMUL R4, R16, R12 ; DMUL R2, R4, R2 ; DFMA R28, R32, R2, R28 ; DFMA R26, R30, R2, R26 ; DFMA R24, R10, R2, R24 ; IADD3 R39, P0, R39, 0x1, RZ ; WARPSYNC 0xffffffff ; BAR.SYNC.DEFER_BLOCKING 0x0 ; IMAD.X R38, RZ, RZ, R38, P0 ; ISETP.GE.U32.AND P0, PT, R39, c[0x0][0x0], PT ; ISETP.GE.U32.AND.EX P0, PT, R38, RZ, PT, P0 ; @P0 CALL.REL.NOINC 0x2280 ; BRA 0x170 ; IMAD.SHL.U32 R10, R40, 0x8, RZ ; SHF.R.U32.HI R40, RZ, 0x1d, R40 ; IADD3 R2, P0, R10, c[0x0][0x180], RZ ; IADD3.X R3, R40, c[0x0][0x184], RZ, P0, !PT ; LDG.E.64 R4, [R2.64] ; IADD3 R6, P0, R10, c[0x0][0x188], RZ ; IADD3.X R7, R40, c[0x0][0x18c], RZ, P0, !PT ; DADD R4, R4, R28 ; STG.E.64 [R2.64], R4 ; LDG.E.64 R8, [R6.64] ; IADD3 R10, P0, R10, c[0x0][0x190], RZ ; IADD3.X R11, R40, c[0x0][0x194], RZ, P0, !PT ; DADD R8, R8, R26 ; STG.E.64 [R6.64], R8 ; LDG.E.64 R12, [R10.64] ; DADD R12, R12, R24 ; STG.E.64 [R10.64], R12 ; EXIT ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; BSSY B2, 0x2600 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.GTU.AND P1, PT, |R6|, +INF , PT ; @P1 BRA 0x25d0 ; LOP3.LUT R3, R5, 0x7fffffff, RZ, 0xc0, !PT ; IADD3 R4, R3, -0x1, RZ ; ISETP.GE.U32.AND P1, PT, R4, 0x7fefffff, PT ; @P1 LOP3.LUT R5, R7, 0x7ff00000, RZ, 0x3c, !PT ; @P1 IMAD.MOV.U32 R4, RZ, RZ, RZ ; @P1 BRA 0x25f0 ; ISETP.GE.U32.AND P1, PT, R3, 0x1000001, PT ; @!P1 BRA 0x2540 ; IADD3 R5, R7, -0x3fe00000, RZ ; IMAD.MOV.U32 R4, RZ, RZ, R6 ; MUFU.RCP64H R3, R5 ; DFMA R8, -R4, R2, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R2, R8, R2 ; DFMA R2, -R4, R8, 1 ; DFMA R2, R8, R2, R8 ; DMUL R2, R2, 2.2250738585072013831e-308 ; DFMA R6, -R6, R2, 1 ; DFMA R6, R6, R6, R6 ; DFMA R4, R2, R6, R2 ; BRA 0x25f0 ; DMUL R6, R6, 8.11296384146066816958e+31 ; MUFU.RCP64H R3, R7 ; DFMA R4, -R6, R2, 1 ; DFMA R4, R4, R4, R4 ; DFMA R4, R2, R4, R2 ; DFMA R2, -R6, R4, 1 ; DFMA R2, R4, R2, R4 ; DMUL R4, R2, 8.11296384146066816958e+31 ; BRA 0x25f0 ; LOP3.LUT R5, R7, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R4, RZ, RZ, R6 ; BSYNC B2 ; IMAD.MOV.U32 R2, RZ, RZ, R4 ; IMAD.MOV.U32 R3, RZ, RZ, R5 ; IMAD.MOV.U32 R4, RZ, RZ, R0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; RET.REL.NODEC R4 0x0 ; ISETP.GE.U32.AND P1, PT, R0, -0x3400000, PT ; BSSY B2, 0x28a0 ; @!P1 BRA 0x2700 ; DFMA.RM R4, R6, R2, R4 ; IADD3 R2, P1, R4, 0x1, RZ ; IMAD.X R3, RZ, RZ, R5, P1 ; DFMA.RP R8, -R4, R2, R8 ; DSETP.GT.AND P1, PT, R8, RZ, PT ; FSEL R2, R2, R4, P1 ; FSEL R3, R3, R5, P1 ; BRA 0x2890 ; DSETP.NE.AND P1, PT, R8, RZ, PT ; @!P1 BRA 0x2880 ; ISETP.GE.AND P1, PT, R9, RZ, PT ; @!P1 IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; @!P1 IMAD.MOV.U32 R3, RZ, RZ, -0x80000 ; @!P1 BRA 0x2890 ; ISETP.GT.AND P1, PT, R9, 0x7fefffff, PT ; @P1 BRA 0x2880 ; DMUL R8, R8, 8.11296384146066816958e+31 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; IMAD.MOV.U32 R3, RZ, RZ, 0x3fd80000 ; MUFU.RSQ64H R7, R9 ; DMUL R4, R6, R6 ; DFMA R4, R8, -R4, 1 ; DFMA R2, R4, R2, 0.5 ; DMUL R4, R6, R4 ; DFMA R4, R2, R4, R6 ; DMUL R6, R8, R4 ; IADD3 R5, R5, -0x100000, RZ ; DFMA R2, R6, -R6, R8 ; DFMA R2, R4, R2, R6 ; IADD3 R3, R3, -0x3500000, RZ ; BRA 0x2890 ; DADD R2, R8, R8 ; BSYNC B2 ; IMAD.MOV.U32 R43, RZ, RZ, 0x0 ; IMAD.MOV.U32 R0, RZ, RZ, R2 ; RET.REL.NODEC R42 0x0 ; BRA 0x28d0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000eb4b5_00000000-6_45b13f1395da6990c6695d5c995b204ef1646100.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2163: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2163: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA Error: %s: %s.\n" .text .globl _Z14checkCUDAErrorPKc .type _Z14checkCUDAErrorPKc, @function _Z14checkCUDAErrorPKc: .LFB2160: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx call cudaGetLastError@PLT testl %eax, %eax jne .L6 popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L6: .cfi_restore_state movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %r8 movq %rbx, %rcx leaq .LC0(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .cfi_endproc .LFE2160: .size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc .globl _Z44__device_stub__Z11forceKernelPdS_S_S_S_S_S_mPdS_S_S_S_S_S_m .type _Z44__device_stub__Z11forceKernelPdS_S_S_S_S_S_mPdS_S_S_S_S_S_m, @function _Z44__device_stub__Z11forceKernelPdS_S_S_S_S_S_mPdS_S_S_S_S_S_m: .LFB2185: .cfi_startproc endbr64 subq $216, %rsp .cfi_def_cfa_offset 224 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) movq %rdx, 40(%rsp) movq %rcx, 32(%rsp) movq %r8, 24(%rsp) movq %r9, 16(%rsp) movq 224(%rsp), %rax movq %rax, 8(%rsp) movq %fs:40, %rax movq %rax, 200(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) leaq 32(%rsp), %rax movq %rax, 152(%rsp) leaq 24(%rsp), %rax movq %rax, 160(%rsp) leaq 16(%rsp), %rax movq %rax, 168(%rsp) leaq 8(%rsp), %rax movq %rax, 176(%rsp) leaq 232(%rsp), %rax movq %rax, 184(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 200(%rsp), %rax subq %fs:40, %rax jne .L12 addq $216, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 232 pushq 72(%rsp) .cfi_def_cfa_offset 240 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z11forceKernelPdS_S_S_S_S_S_m(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 224 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE2185: .size _Z44__device_stub__Z11forceKernelPdS_S_S_S_S_S_mPdS_S_S_S_S_S_m, .-_Z44__device_stub__Z11forceKernelPdS_S_S_S_S_S_mPdS_S_S_S_S_S_m .globl _Z11forceKernelPdS_S_S_S_S_S_m .type _Z11forceKernelPdS_S_S_S_S_S_m, @function _Z11forceKernelPdS_S_S_S_S_S_m: .LFB2186: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 pushq 24(%rsp) .cfi_def_cfa_offset 24 pushq 24(%rsp) .cfi_def_cfa_offset 32 call _Z44__device_stub__Z11forceKernelPdS_S_S_S_S_S_mPdS_S_S_S_S_S_m addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2186: .size _Z11forceKernelPdS_S_S_S_S_S_m, .-_Z11forceKernelPdS_S_S_S_S_S_m .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC3: .string "Unable to allocate storage on the device" .align 8 .LC4: .string "Failed Initial Conditions Memcpy" .section .rodata.str1.1 .LC5: .string "Failed Force Kernel" .section .rodata.str1.8 .align 8 .LC6: .string "Failed Final Conditions Memcpy" .section .rodata.str1.1 .LC8: .string " Net Force: %.6f\n" .LC9: .string "Absolute Force: %.6f\n" .section .rodata.str1.8 .align 8 .LC11: .string "Verification Failed: Net force is not a finite value!\n" .align 8 .LC13: .string "Verification Failed: Force equilibrium not conserved!\n" .align 8 .LC14: .string "Verification Failed: Absolute Force is not a finite value!\n" .section .rodata.str1.1 .LC16: .string "Time: %.8fs\n" .text .globl main .type main, @function main: .LFB2156: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $136, %rsp .cfi_def_cfa_offset 192 movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax movl $8, %esi movl $512000, %edi call calloc@PLT movq %rax, %r15 movl $8, %esi movl $512000, %edi call calloc@PLT movq %rax, %r14 movl $8, %esi movl $512000, %edi call calloc@PLT movq %rax, %r13 movl $8, %esi movl $512000, %edi call calloc@PLT movq %rax, %rbx movl $8, %esi movl $512000, %edi call calloc@PLT movq %rax, %rbp movl $8, %esi movl $512000, %edi call calloc@PLT movq %rax, %r12 movl $8, %esi movl $512000, %edi call calloc@PLT movq %rax, %r8 movq %rax, 16(%rsp) movl $0, %esi movl $0, %eax movsd .LC2(%rip), %xmm1 jmp .L16 .L17: movq %rsi, %rdi shrq %rdi orq %r11, %rdi pxor %xmm0, %xmm0 cvtsi2sdq %rdi, %xmm0 addsd %xmm0, %xmm0 jmp .L18 .L19: movq %rcx, %rdi shrq %rdi orq %r10, %rdi pxor %xmm0, %xmm0 cvtsi2sdq %rdi, %xmm0 addsd %xmm0, %xmm0 jmp .L20 .L21: movq %rdx, %rdi shrq %rdi movq %rdx, %r9 andl $1, %r9d orq %r9, %rdi pxor %xmm0, %xmm0 cvtsi2sdq %rdi, %xmm0 addsd %xmm0, %xmm0 .L22: movsd %xmm0, 0(%r13,%rax,8) movsd %xmm1, (%r8,%rax,8) movq $0x000000000, (%rbx,%rax,8) movq $0x000000000, 0(%rbp,%rax,8) movq $0x000000000, (%r12,%rax,8) addq $1, %rax addq $1, %rdx cmpq $80, %rdx je .L47 .L23: testq %rsi, %rsi js .L17 pxor %xmm0, %xmm0 cvtsi2sdq %rsi, %xmm0 .L18: movsd %xmm0, (%r15,%rax,8) testq %rcx, %rcx js .L19 pxor %xmm0, %xmm0 cvtsi2sdq %rcx, %xmm0 .L20: movsd %xmm0, (%r14,%rax,8) testq %rdx, %rdx js .L21 pxor %xmm0, %xmm0 cvtsi2sdq %rdx, %xmm0 jmp .L22 .L47: movq 8(%rsp), %r9 addq $80, %r9 addq $1, %rcx cmpq $80, %rcx je .L24 .L26: movq %r9, %rax movl $0, %edx movq %rcx, %r10 andl $1, %r10d movq %r9, 8(%rsp) jmp .L23 .L24: movq 24(%rsp), %rax addq $6400, %rax addq $1, %rsi cmpq $512000, %rax je .L25 .L16: movq %rax, %r9 movl $0, %ecx movq %rsi, %r11 andl $1, %r11d movq %rax, 24(%rsp) jmp .L26 .L25: leaq 40(%rsp), %rdi movl $4096000, %esi call cudaMalloc@PLT leaq .LC3(%rip), %rdi call _Z14checkCUDAErrorPKc leaq 48(%rsp), %rdi movl $4096000, %esi call cudaMalloc@PLT leaq .LC3(%rip), %rdi call _Z14checkCUDAErrorPKc leaq 56(%rsp), %rdi movl $4096000, %esi call cudaMalloc@PLT leaq .LC3(%rip), %rdi call _Z14checkCUDAErrorPKc leaq 64(%rsp), %rdi movl $4096000, %esi call cudaMalloc@PLT leaq .LC3(%rip), %rdi call _Z14checkCUDAErrorPKc leaq 72(%rsp), %rdi movl $4096000, %esi call cudaMalloc@PLT leaq .LC3(%rip), %rdi call _Z14checkCUDAErrorPKc leaq 80(%rsp), %rdi movl $4096000, %esi call cudaMalloc@PLT leaq .LC3(%rip), %rdi call _Z14checkCUDAErrorPKc leaq 88(%rsp), %rdi movl $4096000, %esi call cudaMalloc@PLT leaq .LC3(%rip), %rdi call _Z14checkCUDAErrorPKc movl $1, %ecx movl $4096000, %edx movq %r15, %rsi movq 40(%rsp), %rdi call cudaMemcpy@PLT leaq .LC4(%rip), %r15 movq %r15, %rdi call _Z14checkCUDAErrorPKc movl $1, %ecx movl $4096000, %edx movq %r14, %rsi movq 48(%rsp), %rdi call cudaMemcpy@PLT movq %r15, %rdi call _Z14checkCUDAErrorPKc movl $1, %ecx movl $4096000, %edx movq %r13, %rsi movq 56(%rsp), %rdi call cudaMemcpy@PLT movq %r15, %rdi call _Z14checkCUDAErrorPKc movl $1, %ecx movl $4096000, %edx movq %rbx, %rsi movq 64(%rsp), %rdi call cudaMemcpy@PLT movq %r15, %rdi call _Z14checkCUDAErrorPKc movl $1, %ecx movl $4096000, %edx movq %rbp, %rsi movq 72(%rsp), %rdi call cudaMemcpy@PLT movq %r15, %rdi call _Z14checkCUDAErrorPKc movl $1, %ecx movl $4096000, %edx movq %r12, %rsi movq 80(%rsp), %rdi call cudaMemcpy@PLT movq %r15, %rdi call _Z14checkCUDAErrorPKc movl $1, %ecx movl $4096000, %edx movq 16(%rsp), %rsi movq 88(%rsp), %rdi call cudaMemcpy@PLT movq %r15, %rdi call _Z14checkCUDAErrorPKc call _ZNSt6chrono3_V212system_clock3nowEv@PLT movq %rax, %r15 movl $1024, 108(%rsp) movl $1, 112(%rsp) movl $500, 96(%rsp) movl $1, 100(%rsp) movl $0, %r9d movl $0, %r8d movq 108(%rsp), %rdx movl $1, %ecx movq 96(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L48 .L27: leaq .LC5(%rip), %rdi call _Z14checkCUDAErrorPKc call cudaDeviceSynchronize@PLT call _ZNSt6chrono3_V212system_clock3nowEv@PLT movq %rax, %r14 movl $2, %ecx movl $4096000, %edx movq 64(%rsp), %rsi movq %rbx, %rdi call cudaMemcpy@PLT leaq .LC6(%rip), %r13 movq %r13, %rdi call _Z14checkCUDAErrorPKc movl $2, %ecx movl $4096000, %edx movq 72(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT movq %r13, %rdi call _Z14checkCUDAErrorPKc movl $2, %ecx movl $4096000, %edx movq 80(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT movq %r13, %rdi call _Z14checkCUDAErrorPKc movl $0, %eax movl $0x000000000, %r13d movq %r13, %xmm4 .L28: movsd (%rbx,%rax,8), %xmm0 addsd 0(%rbp,%rax,8), %xmm0 addsd (%r12,%rax,8), %xmm0 addsd %xmm4, %xmm0 movapd %xmm0, %xmm4 addq $1, %rax cmpq $512000, %rax jne .L28 movq %xmm0, %r13 movl $0, %eax movq $0x000000000, 8(%rsp) movq .LC7(%rip), %xmm1 .L29: movsd (%rbx,%rax,8), %xmm0 addsd 0(%rbp,%rax,8), %xmm0 addsd (%r12,%rax,8), %xmm0 andpd %xmm1, %xmm0 addsd 8(%rsp), %xmm0 movsd %xmm0, 8(%rsp) addq $1, %rax cmpq $512000, %rax jne .L29 movq %r13, %xmm0 leaq .LC8(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movsd 8(%rsp), %xmm0 leaq .LC9(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq %r13, %xmm0 andpd .LC7(%rip), %xmm0 movsd .LC10(%rip), %xmm1 ucomisd %xmm0, %xmm1 jb .L49 comisd .LC12(%rip), %xmm0 ja .L50 movsd 8(%rsp), %xmm0 andpd .LC7(%rip), %xmm0 movsd .LC10(%rip), %xmm1 ucomisd %xmm0, %xmm1 jb .L51 subq %r15, %r14 pxor %xmm0, %xmm0 cvtsi2sdq %r14, %xmm0 divsd .LC15(%rip), %xmm0 leaq .LC16(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq 120(%rsp), %rax subq %fs:40, %rax jne .L52 movl $0, %eax addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L48: .cfi_restore_state pushq $512000 .cfi_def_cfa_offset 200 pushq 88(%rsp) .cfi_def_cfa_offset 208 movq 88(%rsp), %r9 movq 80(%rsp), %r8 movq 104(%rsp), %rcx movq 72(%rsp), %rdx movq 64(%rsp), %rsi movq 56(%rsp), %rdi call _Z44__device_stub__Z11forceKernelPdS_S_S_S_S_S_mPdS_S_S_S_S_S_m addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L27 .L49: leaq .LC11(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $-1, %edi call exit@PLT .L50: leaq .LC13(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $-1, %edi call exit@PLT .L51: leaq .LC14(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $-1, %edi call exit@PLT .L52: call __stack_chk_fail@PLT .cfi_endproc .LFE2156: .size main, .-main .section .rodata.str1.8 .align 8 .LC17: .string "_Z11forceKernelPdS_S_S_S_S_S_m" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2188: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC17(%rip), %rdx movq %rdx, %rcx leaq _Z11forceKernelPdS_S_S_S_S_S_m(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2188: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC2: .long 0 .long 1072693248 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC7: .long -1 .long 2147483647 .long 0 .long 0 .section .rodata.cst8 .align 8 .LC10: .long -1 .long 2146435071 .align 8 .LC12: .long -1998362383 .long 1055193269 .align 8 .LC15: .long 0 .long 1104006501 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11forceKernelPdS_S_S_S_S_S_m ; -- Begin function _Z11forceKernelPdS_S_S_S_S_S_m .globl _Z11forceKernelPdS_S_S_S_S_S_m .p2align 8 .type _Z11forceKernelPdS_S_S_S_S_S_m,@function _Z11forceKernelPdS_S_S_S_S_S_m: ; @_Z11forceKernelPdS_S_S_S_S_S_m ; %bb.0: s_load_b32 s2, s[0:1], 0x4c v_mov_b32_e32 v3, 0 v_mov_b32_e32 v4, 0 s_mov_b32 s3, 0 s_mov_b64 s[12:13], 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 s_waitcnt lgkmcnt(0) v_cmp_eq_u16_e64 s4, s2, 0 s_and_b32 s2, s2, 0xffff v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_3) s_and_b32 vcc_lo, exec_lo, s4 s_cbranch_vccnz .LBB0_8 ; %bb.1: ; %.lr.ph100 s_load_b256 s[4:11], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[3:4], 3, v[1:2] s_load_b64 s[14:15], s[0:1], 0x38 v_lshlrev_b32_e32 v0, 3, v0 s_lshl_b32 s16, s2, 3 s_mov_b32 s17, s3 s_waitcnt lgkmcnt(0) v_add_co_u32 v5, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo v_add_co_u32 v7, vcc_lo, s6, v3 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo v_add_co_u32 v13, vcc_lo, s8, v3 v_add_co_ci_u32_e32 v14, vcc_lo, s9, v4, vcc_lo v_add_co_u32 v3, vcc_lo, s10, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo global_load_b64 v[9:10], v[5:6], off global_load_b64 v[11:12], v[7:8], off global_load_b64 v[13:14], v[13:14], off global_load_b64 v[15:16], v[3:4], off v_mov_b32_e32 v3, 0 v_add_co_u32 v17, s4, s4, v0 v_mov_b32_e32 v4, 0 v_add_co_ci_u32_e64 v18, null, s5, 0, s4 v_add_co_u32 v19, s4, s6, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v20, null, s7, 0, s4 v_add_co_u32 v21, s4, s8, v0 v_add_co_ci_u32_e64 v22, null, s9, 0, s4 v_or_b32_e32 v23, 0x2000, v0 v_or_b32_e32 v24, 0x4000, v0 v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 s_branch .LBB0_3 .LBB0_2: ; %._crit_edge ; in Loop: Header=BB0_3 Depth=1 s_add_u32 s10, s10, s16 s_addc_u32 s11, s11, s17 s_cmp_eq_u64 s[12:13], s[2:3] s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_8 .LBB0_3: ; =>This Loop Header: Depth=1 ; Child Loop BB0_6 Depth 2 s_mul_i32 s5, s13, s2 s_mul_hi_u32 s6, s12, s2 s_mul_i32 s4, s12, s2 s_add_i32 s5, s6, s5 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b64 s[6:7], s[4:5], 3 s_add_u32 s12, s12, 1 v_add_co_u32 v25, vcc_lo, v17, s6 v_add_co_ci_u32_e32 v26, vcc_lo, s7, v18, vcc_lo v_add_co_u32 v27, vcc_lo, v19, s6 v_add_co_ci_u32_e32 v28, vcc_lo, s7, v20, vcc_lo v_add_co_u32 v29, vcc_lo, v21, s6 v_add_co_ci_u32_e32 v30, vcc_lo, s7, v22, vcc_lo global_load_b64 v[25:26], v[25:26], off global_load_b64 v[27:28], v[27:28], off global_load_b64 v[29:30], v[29:30], off s_addc_u32 s13, s13, 0 s_mul_hi_u32 s7, s12, s2 s_mul_i32 s8, s13, s2 s_mul_i32 s6, s12, s2 s_add_i32 s7, s7, s8 s_waitcnt vmcnt(2) ds_store_b64 v0, v[25:26] s_waitcnt vmcnt(1) ds_store_b64 v23, v[27:28] s_waitcnt vmcnt(0) ds_store_b64 v24, v[29:30] v_cmp_lt_u64_e64 s8, s[6:7], s[14:15] s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_and_b32 s8, s8, exec_lo s_cselect_b32 s7, s7, s15 s_cselect_b32 s6, s6, s14 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_ge_u64_e64 s8, s[4:5], s[6:7] s_and_b32 vcc_lo, exec_lo, s8 s_cbranch_vccnz .LBB0_2 ; %bb.4: ; %.lr.ph.preheader ; in Loop: Header=BB0_3 Depth=1 s_mov_b32 s18, 0 s_mov_b64 s[8:9], s[10:11] s_branch .LBB0_6 .LBB0_5: ; in Loop: Header=BB0_6 Depth=2 s_or_b32 exec_lo, exec_lo, s19 s_add_u32 s4, s4, 1 s_addc_u32 s5, s5, 0 s_add_i32 s18, s18, 8 v_cmp_ge_u64_e64 s19, s[4:5], s[6:7] s_add_u32 s8, s8, 8 s_addc_u32 s9, s9, 0 s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s19 s_cbranch_vccnz .LBB0_2 .LBB0_6: ; %.lr.ph ; Parent Loop BB0_3 Depth=1 ; => This Inner Loop Header: Depth=2 s_mov_b32 s19, exec_lo v_cmpx_ne_u64_e64 s[4:5], v[1:2] s_cbranch_execz .LBB0_5 ; %bb.7: ; in Loop: Header=BB0_6 Depth=2 v_mov_b32_e32 v31, s18 ds_load_2addr_stride64_b64 v[25:28], v31 offset1:16 ds_load_b64 v[31:32], v31 offset:16384 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_load_b64 s[20:21], s[8:9], 0x0 v_add_f64 v[27:28], v[11:12], -v[27:28] v_add_f64 v[25:26], v[9:10], -v[25:26] v_add_f64 v[31:32], v[13:14], -v[31:32] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[29:30], v[27:28], v[27:28] v_fma_f64 v[29:30], v[25:26], v[25:26], v[29:30] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[29:30], v[31:32], v[31:32], v[29:30] v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[29:30] v_cndmask_b32_e64 v33, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b32_e32 v33, 8, v33 v_ldexp_f64 v[29:30], v[29:30], v33 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_rsq_f64_e32 v[33:34], v[29:30] s_waitcnt_depctr 0xfff v_mul_f64 v[35:36], v[29:30], v[33:34] v_mul_f64 v[33:34], v[33:34], 0.5 v_fma_f64 v[37:38], -v[33:34], v[35:36], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[35:36], v[35:36], v[37:38], v[35:36] v_fma_f64 v[33:34], v[33:34], v[37:38], v[33:34] v_fma_f64 v[37:38], -v[35:36], v[35:36], v[29:30] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[35:36], v[37:38], v[33:34], v[35:36] v_fma_f64 v[37:38], -v[35:36], v[35:36], v[29:30] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_fma_f64 v[33:34], v[37:38], v[33:34], v[35:36] v_cndmask_b32_e64 v35, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[29:30], 0x260 v_ldexp_f64 v[33:34], v[33:34], v35 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v30, v34, v30 :: v_dual_cndmask_b32 v29, v33, v29 v_mul_f64 v[33:34], v[29:30], v[29:30] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[29:30], v[29:30], v[33:34] v_div_scale_f64 v[33:34], null, v[29:30], v[29:30], 1.0 v_div_scale_f64 v[39:40], vcc_lo, 1.0, v[29:30], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[35:36], v[33:34] s_waitcnt_depctr 0xfff v_fma_f64 v[37:38], -v[33:34], v[35:36], 1.0 v_fma_f64 v[35:36], v[35:36], v[37:38], v[35:36] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[37:38], -v[33:34], v[35:36], 1.0 v_fma_f64 v[35:36], v[35:36], v[37:38], v[35:36] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[37:38], v[39:40], v[35:36] v_fma_f64 v[33:34], -v[33:34], v[37:38], v[39:40] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_div_fmas_f64 v[33:34], v[33:34], v[35:36], v[37:38] s_waitcnt lgkmcnt(0) v_mul_f64 v[35:36], v[15:16], s[20:21] v_div_fixup_f64 v[29:30], v[33:34], v[29:30], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[29:30], v[35:36], v[29:30] v_fma_f64 v[3:4], v[25:26], v[29:30], v[3:4] v_fma_f64 v[7:8], v[27:28], v[29:30], v[7:8] v_fma_f64 v[5:6], v[31:32], v[29:30], v[5:6] s_branch .LBB0_5 .LBB0_8: ; %Flow129 s_load_b128 s[4:7], s[0:1], 0x20 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[1:2] s_load_b64 s[0:1], s[0:1], 0x30 s_waitcnt lgkmcnt(0) v_add_co_u32 v9, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v10, vcc_lo, s5, v1, vcc_lo global_load_b64 v[11:12], v[9:10], off s_waitcnt vmcnt(0) v_add_f64 v[2:3], v[3:4], v[11:12] v_add_co_u32 v11, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v12, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b64 v[9:10], v[2:3], off global_load_b64 v[2:3], v[11:12], off s_waitcnt vmcnt(0) v_add_f64 v[2:3], v[7:8], v[2:3] global_store_b64 v[11:12], v[2:3], off global_load_b64 v[2:3], v[0:1], off s_waitcnt vmcnt(0) v_add_f64 v[2:3], v[5:6], v[2:3] global_store_b64 v[0:1], v[2:3], off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11forceKernelPdS_S_S_S_S_S_m .amdhsa_group_segment_fixed_size 24576 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 320 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 41 .amdhsa_next_free_sgpr 22 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11forceKernelPdS_S_S_S_S_S_m, .Lfunc_end0-_Z11forceKernelPdS_S_S_S_S_S_m ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1224 ; NumSgprs: 24 ; NumVgprs: 41 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 24576 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 5 ; NumSGPRsForWavesPerEU: 24 ; NumVGPRsForWavesPerEU: 41 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .offset: 56 .size: 8 .value_kind: by_value - .offset: 64 .size: 4 .value_kind: hidden_block_count_x - .offset: 68 .size: 4 .value_kind: hidden_block_count_y - .offset: 72 .size: 4 .value_kind: hidden_block_count_z - .offset: 76 .size: 2 .value_kind: hidden_group_size_x - .offset: 78 .size: 2 .value_kind: hidden_group_size_y - .offset: 80 .size: 2 .value_kind: hidden_group_size_z - .offset: 82 .size: 2 .value_kind: hidden_remainder_x - .offset: 84 .size: 2 .value_kind: hidden_remainder_y - .offset: 86 .size: 2 .value_kind: hidden_remainder_z - .offset: 104 .size: 8 .value_kind: hidden_global_offset_x - .offset: 112 .size: 8 .value_kind: hidden_global_offset_y - .offset: 120 .size: 8 .value_kind: hidden_global_offset_z - .offset: 128 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 24576 .kernarg_segment_align: 8 .kernarg_segment_size: 320 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11forceKernelPdS_S_S_S_S_S_m .private_segment_fixed_size: 0 .sgpr_count: 24 .sgpr_spill_count: 0 .symbol: _Z11forceKernelPdS_S_S_S_S_S_m.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 41 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "45b13f1395da6990c6695d5c995b204ef1646100.hip" .globl _Z26__device_stub__forceKernelPdS_S_S_S_S_S_m # -- Begin function _Z26__device_stub__forceKernelPdS_S_S_S_S_S_m .p2align 4, 0x90 .type _Z26__device_stub__forceKernelPdS_S_S_S_S_S_m,@function _Z26__device_stub__forceKernelPdS_S_S_S_S_S_m: # @_Z26__device_stub__forceKernelPdS_S_S_S_S_S_m .cfi_startproc # %bb.0: subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movq %r9, 48(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 176(%rsp), %rax movq %rax, 144(%rsp) leaq 184(%rsp), %rax movq %rax, 152(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z11forceKernelPdS_S_S_S_S_S_m, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $184, %rsp .cfi_adjust_cfa_offset -184 retq .Lfunc_end0: .size _Z26__device_stub__forceKernelPdS_S_S_S_S_S_m, .Lfunc_end0-_Z26__device_stub__forceKernelPdS_S_S_S_S_S_m .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI1_0: .long 1127219200 # 0x43300000 .long 1160773632 # 0x45300000 .long 0 # 0x0 .long 0 # 0x0 .LCPI1_1: .quad 0x4330000000000000 # double 4503599627370496 .quad 0x4530000000000000 # double 1.9342813113834067E+25 .LCPI1_2: .quad 0x7fffffffffffffff # double NaN .quad 0x7fffffffffffffff # double NaN .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI1_3: .quad 0x7ff0000000000000 # double +Inf .LCPI1_4: .quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5 .LCPI1_5: .quad 0x41cdcd6500000000 # double 1.0E+9 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $328, %rsp # imm = 0x148 .cfi_def_cfa_offset 384 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $512000, %edi # imm = 0x7D000 movl $8, %esi callq calloc movq %rax, %rbx movl $512000, %edi # imm = 0x7D000 movl $8, %esi callq calloc movq %rax, %rbp movl $512000, %edi # imm = 0x7D000 movl $8, %esi callq calloc movq %rax, %r13 movl $512000, %edi # imm = 0x7D000 movl $8, %esi callq calloc movq %rax, 56(%rsp) # 8-byte Spill movl $512000, %edi # imm = 0x7D000 movl $8, %esi callq calloc movq %rax, 48(%rsp) # 8-byte Spill movl $512000, %edi # imm = 0x7D000 movl $8, %esi callq calloc movq %rax, 40(%rsp) # 8-byte Spill movl $512000, %edi # imm = 0x7D000 movl $8, %esi callq calloc movq %rax, 32(%rsp) # 8-byte Spill xorl %eax, %eax movdqa .LCPI1_0(%rip), %xmm2 # xmm2 = [1127219200,1160773632,0,0] movapd .LCPI1_1(%rip), %xmm3 # xmm3 = [4.503599627370496E+15,1.9342813113834067E+25] movabsq $4607182418800017408, %r14 # imm = 0x3FF0000000000000 xorl %edx, %edx .p2align 4, 0x90 .LBB1_1: # %.preheader147 # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 # Child Loop BB1_3 Depth 3 movq %rdx, 136(%rsp) # 8-byte Spill movq %rdx, %xmm0 punpckldq %xmm2, %xmm0 # xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] subpd %xmm3, %xmm0 movapd %xmm0, %xmm4 unpckhpd %xmm0, %xmm4 # xmm4 = xmm4[1],xmm0[1] addsd %xmm0, %xmm4 xorl %r12d, %r12d movapd %xmm4, 112(%rsp) # 16-byte Spill .p2align 4, 0x90 .LBB1_2: # %.preheader146 # Parent Loop BB1_1 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB1_3 Depth 3 movq %rax, %r15 movq %r12, %xmm0 punpckldq %xmm2, %xmm0 # xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] subpd %xmm3, %xmm0 movapd %xmm0, %xmm1 unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1] addsd %xmm0, %xmm1 movapd %xmm1, 96(%rsp) # 16-byte Spill movq 56(%rsp), %rax # 8-byte Reload leaq (%rax,%r15,8), %rdi movl $640, %edx # imm = 0x280 xorl %esi, %esi callq memset@PLT movq 48(%rsp), %rax # 8-byte Reload leaq (%rax,%r15,8), %rdi movl $640, %edx # imm = 0x280 xorl %esi, %esi callq memset@PLT movq 40(%rsp), %rax # 8-byte Reload leaq (%rax,%r15,8), %rdi movl $640, %edx # imm = 0x280 xorl %esi, %esi callq memset@PLT movaps 96(%rsp), %xmm5 # 16-byte Reload movaps 112(%rsp), %xmm4 # 16-byte Reload movapd .LCPI1_1(%rip), %xmm3 # xmm3 = [4.503599627370496E+15,1.9342813113834067E+25] movdqa .LCPI1_0(%rip), %xmm2 # xmm2 = [1127219200,1160773632,0,0] leaq (%rbx,%r15,8), %rax leaq (%rbp,%r15,8), %rdx leaq (,%r15,8), %rsi addq %r13, %rsi movq 32(%rsp), %rcx # 8-byte Reload leaq (%rcx,%r15,8), %rdi xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_3: # Parent Loop BB1_1 Depth=1 # Parent Loop BB1_2 Depth=2 # => This Inner Loop Header: Depth=3 movsd %xmm4, (%rax,%rcx,8) movsd %xmm5, (%rdx,%rcx,8) movq %rcx, %xmm0 punpckldq %xmm2, %xmm0 # xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] subpd %xmm3, %xmm0 movapd %xmm0, %xmm1 unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1] addsd %xmm0, %xmm1 movsd %xmm1, (%rsi,%rcx,8) movq %r14, (%rdi,%rcx,8) incq %rcx cmpq $80, %rcx jne .LBB1_3 # %bb.4: # in Loop: Header=BB1_2 Depth=2 incq %r12 leaq (%r15,%rcx), %rax cmpq $80, %r12 jne .LBB1_2 # %bb.5: # in Loop: Header=BB1_1 Depth=1 movq 136(%rsp), %rdx # 8-byte Reload incq %rdx addq %rcx, %r15 movq %r15, %rax cmpq $80, %rdx jne .LBB1_1 # %bb.6: leaq 88(%rsp), %rdi movl $4096000, %esi # imm = 0x3E8000 callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB1_7 # %bb.9: # %_Z14checkCUDAErrorPKc.exit leaq 80(%rsp), %rdi movl $4096000, %esi # imm = 0x3E8000 callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB1_7 # %bb.10: # %_Z14checkCUDAErrorPKc.exit106 leaq 72(%rsp), %rdi movl $4096000, %esi # imm = 0x3E8000 callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB1_7 # %bb.11: # %_Z14checkCUDAErrorPKc.exit108 leaq 24(%rsp), %rdi movl $4096000, %esi # imm = 0x3E8000 callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB1_7 # %bb.12: # %_Z14checkCUDAErrorPKc.exit110 leaq 16(%rsp), %rdi movl $4096000, %esi # imm = 0x3E8000 callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB1_7 # %bb.13: # %_Z14checkCUDAErrorPKc.exit112 leaq 8(%rsp), %rdi movl $4096000, %esi # imm = 0x3E8000 callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB1_7 # %bb.14: # %_Z14checkCUDAErrorPKc.exit114 leaq 64(%rsp), %rdi movl $4096000, %esi # imm = 0x3E8000 callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB1_7 # %bb.15: # %_Z14checkCUDAErrorPKc.exit116 movq 88(%rsp), %rdi movl $4096000, %edx # imm = 0x3E8000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB1_16 # %bb.17: # %_Z14checkCUDAErrorPKc.exit118 movq 80(%rsp), %rdi movl $4096000, %edx # imm = 0x3E8000 movq %rbp, %rsi movl $1, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB1_16 # %bb.18: # %_Z14checkCUDAErrorPKc.exit120 movq 72(%rsp), %rdi movl $4096000, %edx # imm = 0x3E8000 movq %r13, %rsi movl $1, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB1_16 # %bb.19: # %_Z14checkCUDAErrorPKc.exit122 movq 24(%rsp), %rdi movl $4096000, %edx # imm = 0x3E8000 movq 56(%rsp), %r14 # 8-byte Reload movq %r14, %rsi movl $1, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax movq 48(%rsp), %r15 # 8-byte Reload movq 40(%rsp), %r13 # 8-byte Reload jne .LBB1_16 # %bb.20: # %_Z14checkCUDAErrorPKc.exit124 movq 16(%rsp), %rdi movl $4096000, %edx # imm = 0x3E8000 movq %r15, %rsi movl $1, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB1_16 # %bb.21: # %_Z14checkCUDAErrorPKc.exit126 movq 8(%rsp), %rdi movl $4096000, %edx # imm = 0x3E8000 movq %r13, %rsi movl $1, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB1_16 # %bb.22: # %_Z14checkCUDAErrorPKc.exit128 movq 64(%rsp), %rdi movl $4096000, %edx # imm = 0x3E8000 movq 32(%rsp), %rsi # 8-byte Reload movl $1, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB1_16 # %bb.23: # %_Z14checkCUDAErrorPKc.exit130 callq _ZNSt6chrono3_V212system_clock3nowEv movq %rax, %rbx movabsq $4294967796, %rdi # imm = 0x1000001F4 leaq 524(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_25 # %bb.24: movq 88(%rsp), %rax movq 80(%rsp), %rcx movq 72(%rsp), %rdx movq 64(%rsp), %rsi movq 24(%rsp), %rdi movq 16(%rsp), %r8 movq 8(%rsp), %r9 movq %rax, 248(%rsp) movq %rcx, 240(%rsp) movq %rdx, 232(%rsp) movq %rsi, 224(%rsp) movq %rdi, 216(%rsp) movq %r8, 208(%rsp) movq %r9, 200(%rsp) movq $512000, 192(%rsp) # imm = 0x7D000 leaq 248(%rsp), %rax movq %rax, 256(%rsp) leaq 240(%rsp), %rax movq %rax, 264(%rsp) leaq 232(%rsp), %rax movq %rax, 272(%rsp) leaq 224(%rsp), %rax movq %rax, 280(%rsp) leaq 216(%rsp), %rax movq %rax, 288(%rsp) leaq 208(%rsp), %rax movq %rax, 296(%rsp) leaq 200(%rsp), %rax movq %rax, 304(%rsp) leaq 192(%rsp), %rax movq %rax, 312(%rsp) leaq 176(%rsp), %rdi leaq 160(%rsp), %rsi leaq 152(%rsp), %rdx leaq 144(%rsp), %rcx callq __hipPopCallConfiguration movq 176(%rsp), %rsi movl 184(%rsp), %edx movq 160(%rsp), %rcx movl 168(%rsp), %r8d leaq 256(%rsp), %r9 movl $_Z11forceKernelPdS_S_S_S_S_S_m, %edi pushq 144(%rsp) .cfi_adjust_cfa_offset 8 pushq 160(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_25: callq hipGetLastError testl %eax, %eax jne .LBB1_26 # %bb.27: # %_Z14checkCUDAErrorPKc.exit132 callq hipDeviceSynchronize callq _ZNSt6chrono3_V212system_clock3nowEv movq %rax, %r12 movq 24(%rsp), %rsi movl $4096000, %edx # imm = 0x3E8000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB1_28 # %bb.29: # %_Z14checkCUDAErrorPKc.exit134 movq 16(%rsp), %rsi movl $4096000, %edx # imm = 0x3E8000 movq %r15, %rdi movl $2, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB1_28 # %bb.30: # %_Z14checkCUDAErrorPKc.exit136 movq 8(%rsp), %rsi movl $4096000, %edx # imm = 0x3E8000 movq %r13, %rdi movl $2, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB1_28 # %bb.31: # %_Z14checkCUDAErrorPKc.exit138.preheader xorpd %xmm0, %xmm0 xorl %eax, %eax .p2align 4, 0x90 .LBB1_32: # %_Z14checkCUDAErrorPKc.exit138 # =>This Inner Loop Header: Depth=1 movsd (%r14,%rax,8), %xmm1 # xmm1 = mem[0],zero addsd (%r15,%rax,8), %xmm1 addsd (%r13,%rax,8), %xmm1 addsd %xmm1, %xmm0 incq %rax cmpq $512000, %rax # imm = 0x7D000 jne .LBB1_32 # %bb.33: # %.preheader.preheader xorpd %xmm3, %xmm3 xorl %eax, %eax movapd .LCPI1_2(%rip), %xmm2 # xmm2 = [NaN,NaN] .p2align 4, 0x90 .LBB1_34: # %.preheader # =>This Inner Loop Header: Depth=1 movsd (%r14,%rax,8), %xmm1 # xmm1 = mem[0],zero addsd (%r15,%rax,8), %xmm1 addsd (%r13,%rax,8), %xmm1 andpd %xmm2, %xmm1 addsd %xmm1, %xmm3 incq %rax cmpq $512000, %rax # imm = 0x7D000 jne .LBB1_34 # %bb.35: movl $.L.str.4, %edi movb $1, %al movapd %xmm0, 112(%rsp) # 16-byte Spill movapd %xmm3, 96(%rsp) # 16-byte Spill callq printf movl $.L.str.5, %edi movaps 96(%rsp), %xmm0 # 16-byte Reload movb $1, %al callq printf movapd 112(%rsp), %xmm0 # 16-byte Reload andpd .LCPI1_2(%rip), %xmm0 ucomisd .LCPI1_3(%rip), %xmm0 je .LBB1_36 # %bb.38: ucomisd .LCPI1_4(%rip), %xmm0 ja .LBB1_39 # %bb.40: movapd 96(%rsp), %xmm0 # 16-byte Reload andpd .LCPI1_2(%rip), %xmm0 ucomisd .LCPI1_3(%rip), %xmm0 je .LBB1_41 # %bb.42: subq %rbx, %r12 xorps %xmm0, %xmm0 cvtsi2sd %r12, %xmm0 divsd .LCPI1_5(%rip), %xmm0 movl $.L.str.9, %edi movb $1, %al callq printf xorl %eax, %eax addq $328, %rsp # imm = 0x148 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_7: .cfi_def_cfa_offset 384 movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.10, %esi movl $.L.str, %edx jmp .LBB1_8 .LBB1_16: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.10, %esi movl $.L.str.1, %edx jmp .LBB1_8 .LBB1_28: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.10, %esi movl $.L.str.3, %edx jmp .LBB1_8 .LBB1_26: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.10, %esi movl $.L.str.2, %edx .LBB1_8: movq %rbx, %rdi movq %rax, %rcx xorl %eax, %eax callq fprintf movl $1, %edi callq exit .LBB1_36: movl $.Lstr.2, %edi jmp .LBB1_37 .LBB1_39: movl $.Lstr.1, %edi jmp .LBB1_37 .LBB1_41: movl $.Lstr, %edi .LBB1_37: callq puts@PLT movl $-1, %edi callq exit .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc .p2align 4, 0x90 .type _Z14checkCUDAErrorPKc,@function _Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rdi, %rbx callq hipGetLastError testl %eax, %eax jne .LBB2_2 # %bb.1: addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB2_2: .cfi_def_cfa_offset 32 movq stderr(%rip), %r14 movl %eax, %edi callq hipGetErrorString movl $.L.str.10, %esi movq %r14, %rdi movq %rbx, %rdx movq %rax, %rcx xorl %eax, %eax callq fprintf movl $1, %edi callq exit .Lfunc_end2: .size _Z14checkCUDAErrorPKc, .Lfunc_end2-_Z14checkCUDAErrorPKc .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11forceKernelPdS_S_S_S_S_S_m, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z11forceKernelPdS_S_S_S_S_S_m,@object # @_Z11forceKernelPdS_S_S_S_S_S_m .section .rodata,"a",@progbits .globl _Z11forceKernelPdS_S_S_S_S_S_m .p2align 3, 0x0 _Z11forceKernelPdS_S_S_S_S_S_m: .quad _Z26__device_stub__forceKernelPdS_S_S_S_S_S_m .size _Z11forceKernelPdS_S_S_S_S_S_m, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Unable to allocate storage on the device" .size .L.str, 41 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Failed Initial Conditions Memcpy" .size .L.str.1, 33 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Failed Force Kernel" .size .L.str.2, 20 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Failed Final Conditions Memcpy" .size .L.str.3, 31 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz " Net Force: %.6f\n" .size .L.str.4, 22 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Absolute Force: %.6f\n" .size .L.str.5, 22 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Time: %.8fs\n" .size .L.str.9, 13 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "CUDA Error: %s: %s.\n" .size .L.str.10, 21 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z11forceKernelPdS_S_S_S_S_S_m" .size .L__unnamed_1, 31 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Verification Failed: Absolute Force is not a finite value!" .size .Lstr, 59 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "Verification Failed: Force equilibrium not conserved!" .size .Lstr.1, 54 .type .Lstr.2,@object # @str.2 .Lstr.2: .asciz "Verification Failed: Net force is not a finite value!" .size .Lstr.2, 54 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub__forceKernelPdS_S_S_S_S_S_m .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z11forceKernelPdS_S_S_S_S_S_m .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z5helloPci .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_TID.X ; ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; @P0 EXIT ; IADD3 R2, P0, R0, c[0x0][0x160], RZ ; ULDC.64 UR4, c[0x0][0x118] ; LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; LDG.E.U8 R0, [R2.64] ; IADD3 R5, R0, -0x20, RZ ; STG.E.U8 [R2.64], R5 ; EXIT ; BRA 0xb0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0000d03c_00000000-6_00cafd25104071658165380e7b05ac1844f0c2d6.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z25__device_stub__Z5helloPciPci .type _Z25__device_stub__Z5helloPciPci, @function _Z25__device_stub__Z5helloPciPci: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z5helloPci(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z25__device_stub__Z5helloPciPci, .-_Z25__device_stub__Z5helloPciPci .globl _Z5helloPci .type _Z5helloPci, @function _Z5helloPci: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z25__device_stub__Z5helloPciPci addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z5helloPci, .-_Z5helloPci .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Last CUDA error %s\n" .LC1: .string "%s!\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $88, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movabsq $8031959307743159656, %rax movl $6581362, %edx movq %rax, 32(%rsp) movq %rdx, 40(%rsp) movq $0, 48(%rsp) movq $0, 56(%rsp) leaq 32(%rsp), %rbp movq %rbp, %rdi call strlen@PLT movq %rax, %rbx movq %rsp, %rdi movl $32, %esi call cudaMalloc@PLT movl $1, %ecx movl $32, %edx movq %rbp, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $32, 20(%rsp) movl $1, 24(%rsp) movl $1, 8(%rsp) movl $1, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L16 .L12: call cudaDeviceSynchronize@PLT leaq 32(%rsp), %rdi movl $2, %ecx movl $32, %edx movq (%rsp), %rsi call cudaMemcpy@PLT call cudaGetLastError@PLT testl %eax, %eax jne .L17 .L13: leaq 32(%rsp), %rdx leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq (%rsp), %rdi call cudaFree@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L18 movl $0, %eax addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L16: .cfi_restore_state movl %ebx, %esi movq (%rsp), %rdi call _Z25__device_stub__Z5helloPciPci jmp .L12 .L17: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L13 .L18: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC2: .string "_Z5helloPci" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z5helloPci(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z5helloPci ; -- Begin function _Z5helloPci .globl _Z5helloPci .p2align 8 .type _Z5helloPci,@function _Z5helloPci: ; @_Z5helloPci ; %bb.0: s_load_b32 s2, s[0:1], 0x8 s_waitcnt lgkmcnt(0) v_cmp_gt_i32_e32 vcc_lo, s2, v0 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b64 s[0:1], s[0:1], 0x0 s_waitcnt lgkmcnt(0) global_load_u8 v1, v0, s[0:1] s_waitcnt vmcnt(0) v_sub_nc_u16 v1, v1, 32 global_store_b8 v0, v1, s[0:1] .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5helloPci .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 12 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 3 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z5helloPci, .Lfunc_end0-_Z5helloPci ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 76 ; NumSgprs: 5 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 5 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 12 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5helloPci .private_segment_fixed_size: 0 .sgpr_count: 5 .sgpr_spill_count: 0 .symbol: _Z5helloPci.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "00cafd25104071658165380e7b05ac1844f0c2d6.hip" .globl _Z20__device_stub__helloPci # -- Begin function _Z20__device_stub__helloPci .p2align 4, 0x90 .type _Z20__device_stub__helloPci,@function _Z20__device_stub__helloPci: # @_Z20__device_stub__helloPci .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z5helloPci, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z20__device_stub__helloPci, .Lfunc_end0-_Z20__device_stub__helloPci .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $136, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movabsq $8031959307743159656, %rax # imm = 0x6F77406F6C6C6568 movq %rax, 16(%rsp) movw $27762, 24(%rsp) # imm = 0x6C72 movb $100, 26(%rsp) xorps %xmm0, %xmm0 movups %xmm0, 27(%rsp) movq $0, 40(%rsp) leaq 16(%rsp), %r14 movq %r14, %rdi callq strlen movq %rax, %rbx movq %rsp, %rdi movl $32, %esi callq hipMalloc movq (%rsp), %rdi movl $32, %edx movq %r14, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 31(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq (%rsp), %rax movq %rax, 104(%rsp) movl %ebx, 12(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z5helloPci, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: callq hipDeviceSynchronize movq (%rsp), %rsi leaq 16(%rsp), %rdi movl $32, %edx movl $2, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax je .LBB1_4 # %bb.3: movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movq %rax, %rsi xorl %eax, %eax callq printf .LBB1_4: leaq 16(%rsp), %rsi movl $.L.str.1, %edi xorl %eax, %eax callq printf movq (%rsp), %rdi callq hipFree xorl %eax, %eax addq $136, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5helloPci, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z5helloPci,@object # @_Z5helloPci .section .rodata,"a",@progbits .globl _Z5helloPci .p2align 3, 0x0 _Z5helloPci: .quad _Z20__device_stub__helloPci .size _Z5helloPci, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Last CUDA error %s\n" .size .L.str, 20 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "%s!\n" .size .L.str.1, 5 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z5helloPci" .size .L__unnamed_1, 12 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z20__device_stub__helloPci .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z5helloPci .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z9scan_inclPiS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R7, SR_TID.X ; IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R7, R2, c[0x0][0x168] ; LDG.E R2, [R2.64] ; MOV R0, c[0x0][0x170] ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; ISETP.GE.AND P0, PT, R0, 0x2, PT ; IMAD.SHL.U32 R0, R7, 0x4, RZ ; STS [R7.X4], R2 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P0 BRA 0x1f0 ; HFMA2.MMA R4, -RZ, RZ, 0, 0 ; IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; IMAD R9, R4, c[0x0][0x170], RZ ; ISETP.GE.AND P0, PT, R7, R2, PT ; IADD3 R4, -R4, 0x1, RZ ; LEA R3, R9, R0, 0x2 ; IMAD R5, R4, c[0x0][0x170], RZ ; LDS R8, [R3] ; IMAD R11, R5, 0x4, R0 ; @P0 IADD3 R5, -R2.reuse, R9, R7 ; IMAD.SHL.U32 R2, R2, 0x2, RZ ; STS [R11], R8 ; @P0 LDS R5, [R5.X4] ; @P0 IADD3 R6, R8, R5, RZ ; @P0 STS [R11], R6 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; @!P0 BRA 0xf0 ; IMAD R3, R4, c[0x0][0x170], RZ ; SHF.R.S32.HI R4, RZ, 0x1f, R7 ; LEA R2, P0, R7, c[0x0][0x160], 0x2 ; LEA R0, R3, R0, 0x2 ; LEA.HI.X R3, R7, c[0x0][0x164], R4, 0x2, P0 ; LDS R5, [R0] ; STG.E [R2.64], R5 ; EXIT ; BRA 0x270; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0005fab4_00000000-6_b25982e7c67c39e0e676dee1856decac06a7d9d2.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "\n%s\n" .LC1: .string "-" .LC2: .string "\n" .LC3: .string " %d" .LC4: .string " ..." .text .globl _Z11show_vectorPciPi .type _Z11show_vectorPciPi, @function _Z11show_vectorPciPi: .LFB2057: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $8, %rsp .cfi_def_cfa_offset 48 movl %esi, %r12d movq %rdx, %rbp movq %rdi, %rdx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT testl %r12d, %r12d jle .L4 movl $0, %ebx leaq .LC1(%rip), %r13 .L5: movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addl $1, %ebx cmpl %ebx, %r12d jne .L5 .L4: leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 40(%rbp), %r13 movq %rbp, %rbx leaq .LC3(%rip), %r12 .L6: movl (%rbx), %edx movq %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %r13, %rbx jne .L6 leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 4194264(%rbp), %rbx addq $4194304, %rbp leaq .LC3(%rip), %r12 .L7: movl (%rbx), %edx movq %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L7 leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $8, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z11show_vectorPciPi, .-_Z11show_vectorPciPi .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC7: .string "CPU scan kernel processing time: %f millisec. (n\302\272 elements %d)\n" .text .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 leaq -8388608(%rsp), %r11 .cfi_def_cfa 11, 8388640 .LPSRL0: subq $4096, %rsp orq $0, (%rsp) cmpq %r11, %rsp jne .LPSRL0 .cfi_def_cfa_register 7 subq $48, %rsp .cfi_def_cfa_offset 8388688 movq %fs:40, %rax movq %rax, 8388648(%rsp) xorl %eax, %eax movl $0, %edi call time@PLT movl %eax, %edi call srand@PLT movq %rsp, %rbx leaq 4194304(%rsp), %rbp .L13: call rand@PLT movslq %eax, %rdx imulq $1374389535, %rdx, %rdx sarq $37, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx imull $100, %edx, %edx subl %edx, %eax subl $50, %eax movl %eax, (%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L13 movabsq $8007525960484349270, %rax movabsq $30506424327432562, %rdx movq %rax, 8388608(%rsp) movq %rdx, 8388616(%rsp) leaq 8388608(%rsp), %rbx movq %rbx, %rdi call strlen@PLT movq %rsp, %rdx movl %eax, %esi movq %rbx, %rdi call _Z11show_vectorPciPi call clock@PLT movq %rax, %rbx movl (%rsp), %eax movl %eax, 4194304(%rsp) leaq 4(%rsp), %rdx leaq 4194308(%rsp), %rax .L14: movl -4(%rax), %ecx addl (%rdx), %ecx movl %ecx, (%rax) addq $4, %rdx addq $4, %rax cmpq %rbp, %rdx jne .L14 call clock@PLT movq %rax, %rbp movabsq $8295756336636061014, %rax movabsq $6147487330982584675, %rdx movq %rax, 8388624(%rsp) movq %rdx, 8388632(%rsp) movw $41, 8388640(%rsp) leaq 8388624(%rsp), %r12 movq %r12, %rdi call strlen@PLT leaq 4194304(%rsp), %rdx movl %eax, %esi movq %r12, %rdi call _Z11show_vectorPciPi subq %rbx, %rbp pxor %xmm0, %xmm0 cvtsi2sdq %rbp, %xmm0 mulsd .LC5(%rip), %xmm0 divsd .LC6(%rip), %xmm0 movl $1048576, %edx leaq .LC7(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq 8388648(%rsp), %rax subq %fs:40, %rax jne .L19 movl $0, %eax addq $8388656, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size main, .-main .globl _Z31__device_stub__Z9scan_inclPiS_iPiS_i .type _Z31__device_stub__Z9scan_inclPiS_iPiS_i, @function _Z31__device_stub__Z9scan_inclPiS_iPiS_i: .LFB2083: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L24 .L20: movq 120(%rsp), %rax subq %fs:40, %rax jne .L25 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L24: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z9scan_inclPiS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L20 .L25: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z31__device_stub__Z9scan_inclPiS_iPiS_i, .-_Z31__device_stub__Z9scan_inclPiS_iPiS_i .globl _Z9scan_inclPiS_i .type _Z9scan_inclPiS_i, @function _Z9scan_inclPiS_i: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z9scan_inclPiS_iPiS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z9scan_inclPiS_i, .-_Z9scan_inclPiS_i .section .rodata.str1.1 .LC8: .string "_Z9scan_inclPiS_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC8(%rip), %rdx movq %rdx, %rcx leaq _Z9scan_inclPiS_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC5: .long 0 .long 1083129856 .align 8 .LC6: .long 0 .long 1093567616 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9scan_inclPiS_i ; -- Begin function _Z9scan_inclPiS_i .globl _Z9scan_inclPiS_i .p2align 8 .type _Z9scan_inclPiS_i,@function _Z9scan_inclPiS_i: ; @_Z9scan_inclPiS_i ; %bb.0: s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x8 s_load_b32 s2, s[0:1], 0x10 v_lshlrev_b32_e32 v1, 2, v0 s_mov_b32 s3, 0 s_waitcnt lgkmcnt(0) global_load_b32 v2, v1, s[4:5] v_add_nc_u32_e32 v1, 0, v1 s_cmp_lt_i32 s2, 2 s_waitcnt vmcnt(0) ds_store_b32 v1, v2 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_5 ; %bb.1: ; %.lr.ph.preheader s_mov_b32 s4, 1 s_set_inst_prefetch_distance 0x1 s_branch .LBB0_3 .p2align 6 .LBB0_2: ; in Loop: Header=BB0_3 Depth=1 s_or_b32 exec_lo, exec_lo, s5 s_lshl_b32 s4, s4, 1 s_waitcnt lgkmcnt(0) s_cmp_ge_i32 s4, s2 s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_5 .LBB0_3: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 v_mad_u64_u32 v[1:2], null, s3, s2, v[0:1] s_sub_i32 s3, 1, s3 s_mov_b32 s5, exec_lo s_delay_alu instid0(VALU_DEP_1) v_lshl_add_u32 v2, v1, 2, 0 v_mad_u64_u32 v[3:4], null, s3, s2, v[0:1] ds_load_b32 v2, v2 v_lshl_add_u32 v3, v3, 2, 0 s_waitcnt lgkmcnt(0) ds_store_b32 v3, v2 v_cmpx_le_u32_e64 s4, v0 s_cbranch_execz .LBB0_2 ; %bb.4: ; in Loop: Header=BB0_3 Depth=1 v_subrev_nc_u32_e32 v1, s4, v1 s_delay_alu instid0(VALU_DEP_1) v_lshl_add_u32 v1, v1, 2, 0 ds_load_b32 v1, v1 s_waitcnt lgkmcnt(0) v_add_nc_u32_e32 v1, v1, v2 ds_store_b32 v3, v1 s_branch .LBB0_2 .LBB0_5: ; %Flow40 s_set_inst_prefetch_distance 0x2 v_mad_u64_u32 v[1:2], null, s3, s2, v[0:1] s_load_b64 s[0:1], s[0:1], 0x0 v_lshlrev_b32_e32 v0, 2, v0 s_delay_alu instid0(VALU_DEP_2) v_lshl_add_u32 v1, v1, 2, 0 ds_load_b32 v1, v1 s_waitcnt lgkmcnt(0) global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9scan_inclPiS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 20 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 6 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9scan_inclPiS_i, .Lfunc_end0-_Z9scan_inclPiS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 312 ; NumSgprs: 6 ; NumVgprs: 5 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 6 ; NumVGPRsForWavesPerEU: 5 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 20 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9scan_inclPiS_i .private_segment_fixed_size: 0 .sgpr_count: 6 .sgpr_spill_count: 0 .symbol: _Z9scan_inclPiS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "b25982e7c67c39e0e676dee1856decac06a7d9d2.hip" .globl _Z24__device_stub__scan_inclPiS_i # -- Begin function _Z24__device_stub__scan_inclPiS_i .p2align 4, 0x90 .type _Z24__device_stub__scan_inclPiS_i,@function _Z24__device_stub__scan_inclPiS_i: # @_Z24__device_stub__scan_inclPiS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9scan_inclPiS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z24__device_stub__scan_inclPiS_i, .Lfunc_end0-_Z24__device_stub__scan_inclPiS_i .cfi_endproc # -- End function .globl _Z11show_vectorPciPi # -- Begin function _Z11show_vectorPciPi .p2align 4, 0x90 .type _Z11show_vectorPciPi,@function _Z11show_vectorPciPi: # @_Z11show_vectorPciPi .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movq %rdx, %rbx movl %esi, %ebp movq %rdi, %rsi movl $.L.str, %edi xorl %eax, %eax callq printf testl %ebp, %ebp jle .LBB1_2 .p2align 4, 0x90 .LBB1_1: # %.lr.ph # =>This Inner Loop Header: Depth=1 movl $45, %edi callq putchar@PLT decl %ebp jne .LBB1_1 .LBB1_2: # %._crit_edge movl $10, %edi callq putchar@PLT xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_3: # =>This Inner Loop Header: Depth=1 movl (%rbx,%r14,4), %esi movl $.L.str.3, %edi xorl %eax, %eax callq printf incq %r14 cmpq $10, %r14 jne .LBB1_3 # %bb.4: movl $.L.str.4, %edi xorl %eax, %eax callq printf xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 movl 4194264(%rbx,%r14,4), %esi movl $.L.str.3, %edi xorl %eax, %eax callq printf incq %r14 cmpq $10, %r14 jne .LBB1_5 # %bb.6: movl $10, %edi popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 jmp putchar@PLT # TAILCALL .Lfunc_end1: .size _Z11show_vectorPciPi, .Lfunc_end1-_Z11show_vectorPciPi .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI2_0: .byte 86 # 0x56 .byte 101 # 0x65 .byte 99 # 0x63 .byte 116 # 0x74 .byte 111 # 0x6f .byte 114 # 0x72 .byte 32 # 0x20 .byte 111 # 0x6f .byte 114 # 0x72 .byte 105 # 0x69 .byte 103 # 0x67 .byte 105 # 0x69 .byte 110 # 0x6e .byte 97 # 0x61 .byte 108 # 0x6c .byte 0 # 0x0 .LCPI2_1: .byte 86 # 0x56 .byte 101 # 0x65 .byte 99 # 0x63 .byte 116 # 0x74 .byte 111 # 0x6f .byte 114 # 0x72 .byte 32 # 0x20 .byte 115 # 0x73 .byte 99 # 0x63 .byte 97 # 0x61 .byte 110 # 0x6e .byte 32 # 0x20 .byte 40 # 0x28 .byte 67 # 0x43 .byte 80 # 0x50 .byte 85 # 0x55 .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI2_2: .quad 0x408f400000000000 # double 1000 .LCPI2_3: .quad 0x412e848000000000 # double 1.0E+6 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $8388656, %rsp # imm = 0x800030 .cfi_def_cfa_offset 8388688 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 xorl %ebx, %ebx xorl %edi, %edi callq time movl %eax, %edi callq srand .p2align 4, 0x90 .LBB2_1: # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1374389535, %rax, %rcx # imm = 0x51EB851F movq %rcx, %rdx shrq $63, %rdx sarq $37, %rcx addl %edx, %ecx imull $100, %ecx, %ecx negl %ecx addl %ecx, %eax addl $-50, %eax movl %eax, 48(%rsp,%rbx,4) incq %rbx cmpq $1048576, %rbx # imm = 0x100000 jne .LBB2_1 # %bb.2: movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [86,101,99,116,111,114,32,111,114,105,103,105,110,97,108,0] movaps %xmm0, 32(%rsp) leaq 32(%rsp), %rbx movq %rbx, %rdi callq strlen leaq 48(%rsp), %rdx movq %rbx, %rdi movl %eax, %esi callq _Z11show_vectorPciPi callq clock movq %rax, %rbx movl 48(%rsp), %eax movl %eax, 4194352(%rsp) movl $1, %ecx .p2align 4, 0x90 .LBB2_3: # =>This Inner Loop Header: Depth=1 addl 48(%rsp,%rcx,4), %eax movl %eax, 4194352(%rsp,%rcx,4) incq %rcx cmpq $1048576, %rcx # imm = 0x100000 jne .LBB2_3 # %bb.4: callq clock movq %rax, %r14 movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [86,101,99,116,111,114,32,115,99,97,110,32,40,67,80,85] movaps %xmm0, (%rsp) movw $41, 16(%rsp) movq %rsp, %r15 movq %r15, %rdi callq strlen leaq 4194352(%rsp), %rdx movq %r15, %rdi movl %eax, %esi callq _Z11show_vectorPciPi subq %rbx, %r14 xorps %xmm0, %xmm0 cvtsi2sd %r14, %xmm0 mulsd .LCPI2_2(%rip), %xmm0 divsd .LCPI2_3(%rip), %xmm0 movl $.L.str.5, %edi movl $1048576, %esi # imm = 0x100000 movb $1, %al callq printf xorl %eax, %eax addq $8388656, %rsp # imm = 0x800030 .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9scan_inclPiS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z9scan_inclPiS_i,@object # @_Z9scan_inclPiS_i .section .rodata,"a",@progbits .globl _Z9scan_inclPiS_i .p2align 3, 0x0 _Z9scan_inclPiS_i: .quad _Z24__device_stub__scan_inclPiS_i .size _Z9scan_inclPiS_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "\n%s\n" .size .L.str, 5 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz " %d" .size .L.str.3, 4 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz " ..." .size .L.str.4, 5 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "CPU scan kernel processing time: %f millisec. (n elements %d)\n" .size .L.str.5, 63 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9scan_inclPiS_i" .size .L__unnamed_1, 18 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__scan_inclPiS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9scan_inclPiS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
987
4,269
2,470
4,527
186
code for sm_80 Function : _Z4gemmPfS_S_ffS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R0, SR_CTAID.Y ; S2R R3, SR_TID.Y ; S2R R5, SR_CTAID.X ; S2R R2, SR_TID.X ; IMAD R13, R0, c[0x0][0x4], R3 ; ISETP.GE.AND P0, PT, R13, c[0x0][0x188], PT ; IMAD R4, R5, c[0x0][0x0], R2 ; ISETP.GE.OR P0, PT, R4, c[0x0][0x188], P0 ; @P0 EXIT ; MOV R6, c[0x0][0x188] ; ULDC.64 UR6, c[0x0][0x118] ; ISETP.GE.AND P0, PT, R6.reuse, -0x5, PT ; IMAD.HI R5, R6, 0x2aaaaaab, RZ ; LEA.HI R5, R5, R5, RZ, 0x1 ; @!P0 BRA 0xda0 ; IMAD R6, R5.reuse, -0x6, R6 ; HFMA2.MMA R23, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD R9, R5, 0x6, R3 ; HFMA2.MMA R10, -RZ, RZ, 0, 0 ; IMAD R8, R13, c[0x0][0x188], R2 ; IADD3 R7, R6.reuse, -0x1, RZ ; IMAD R9, R9, c[0x0][0x188], R4 ; LOP3.LUT R11, R6.reuse, 0x3, RZ, 0xc0, !PT ; IMAD R22, R5, 0x6, R8 ; ISETP.GE.U32.AND P1, PT, R7, 0x3, PT ; IMAD R7, R3, 0x18, RZ ; MOV R19, RZ ; IMAD.WIDE R20, R9, R23, c[0x0][0x168] ; IADD3 R9, R6, -R11, RZ ; LEA R12, R2, R7, 0x2 ; IMAD.WIDE R22, R22, R23, c[0x0][0x160] ; ISETP.GE.AND P2, PT, R10, R5, PT ; @!P2 BRA 0xbc0 ; ISETP.NE.AND P0, PT, R10, R5, PT ; ISETP.LT.OR P0, PT, R6, 0x1, P0 ; @P0 BRA 0xd70 ; LDG.E R14, [R22.64] ; LDG.E R17, [R20.64] ; ISETP.GE.U32.AND P0, PT, R0, R5, PT ; FMUL R15, R14, c[0x0][0x178] ; STS [R12+0x90], R17 ; STS [R12], R15 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @!P0 BRA 0x3d0 ; LDS R18, [R2.X4+0x90] ; LDS.64 R16, [R7] ; LDS R24, [R2.X4+0xa8] ; LDS R25, [R2.X4+0xc0] ; LDS.64 R14, [R7+0x8] ; LDS R26, [R2.X4+0x108] ; FFMA R16, R16, R18, R19 ; LDS R18, [R2.X4+0xd8] ; FFMA R24, R24, R17, R16 ; LDS R19, [R2.X4+0xf0] ; LDS.64 R16, [R7+0x10] ; FFMA R14, R25, R14, R24 ; FFMA R15, R18, R15, R14 ; FFMA R16, R19, R16, R15 ; FFMA R19, R26, R17, R16 ; BRA 0xd70 ; UMOV UR4, URZ ; @!P1 BRA 0xa80 ; ISETP.GT.AND P0, PT, R9, RZ, PT ; UMOV UR4, URZ ; MOV R18, R9 ; @!P0 BRA 0x960 ; ISETP.GT.AND P3, PT, R18, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P3 BRA 0x770 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; UMOV UR5, 0x18 ; MOV R24, UR4 ; UIMAD UR5, UR4, UR5, 0x90 ; IADD3 R18, R18, -0x10, RZ ; UIADD3 UR4, UR4, 0x10, URZ ; IMAD R24, R3, 0x6, R24 ; ISETP.GT.AND P3, PT, R18, 0xc, PT ; LDS R14, [R2.X4+UR5] ; LDS.64 R16, [R24.X4] ; LDS R25, [R2.X4+UR5+0x18] ; LDS R27, [R2.X4+UR5+0x138] ; FFMA R16, R14, R16, R19 ; LDS R19, [R2.X4+UR5+0x30] ; FFMA R17, R25, R17, R16 ; LDS.64 R14, [R24.X4+0x8] ; LDS R25, [R2.X4+UR5+0x48] ; FFMA R14, R19, R14, R17 ; LDS R19, [R2.X4+UR5+0x60] ; FFMA R15, R25, R15, R14 ; LDS.64 R16, [R24.X4+0x10] ; LDS R25, [R2.X4+UR5+0x78] ; FFMA R16, R19, R16, R15 ; LDS R19, [R2.X4+UR5+0x90] ; FFMA R17, R25, R17, R16 ; LDS.64 R14, [R24.X4+0x18] ; LDS R25, [R2.X4+UR5+0xa8] ; FFMA R14, R19, R14, R17 ; LDS R19, [R2.X4+UR5+0xc0] ; FFMA R15, R25, R15, R14 ; LDS.64 R16, [R24.X4+0x20] ; LDS R25, [R2.X4+UR5+0xd8] ; FFMA R16, R19, R16, R15 ; LDS R19, [R2.X4+UR5+0xf0] ; FFMA R17, R25, R17, R16 ; LDS.64 R14, [R24.X4+0x28] ; LDS R25, [R2.X4+UR5+0x108] ; FFMA R14, R19, R14, R17 ; LDS R19, [R2.X4+UR5+0x120] ; FFMA R26, R25, R15, R14 ; LDS.64 R16, [R24.X4+0x30] ; LDS R25, [R2.X4+UR5+0x150] ; LDS.64 R14, [R24.X4+0x38] ; FFMA R16, R19, R16, R26 ; LDS R19, [R2.X4+UR5+0x168] ; FFMA R16, R27, R17, R16 ; FFMA R14, R25, R14, R16 ; FFMA R19, R19, R15, R14 ; @P3 BRA 0x470 ; ISETP.GT.AND P3, PT, R18, 0x4, PT ; @!P3 BRA 0x940 ; UMOV UR5, 0x18 ; MOV R24, UR4 ; UIMAD UR5, UR4, UR5, 0x90 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; UIADD3 UR4, UR4, 0x8, URZ ; IADD3 R18, R18, -0x8, RZ ; IMAD R24, R3, 0x6, R24 ; LDS R14, [R2.X4+UR5] ; LDS.64 R16, [R24.X4] ; LDS R25, [R2.X4+UR5+0x18] ; LDS R27, [R2.X4+UR5+0x78] ; FFMA R16, R14, R16, R19 ; LDS R19, [R2.X4+UR5+0x30] ; FFMA R17, R25, R17, R16 ; LDS.64 R14, [R24.X4+0x8] ; LDS R25, [R2.X4+UR5+0x48] ; FFMA R14, R19, R14, R17 ; LDS R19, [R2.X4+UR5+0x60] ; FFMA R26, R25, R15, R14 ; LDS.64 R16, [R24.X4+0x10] ; LDS R25, [R2.X4+UR5+0x90] ; LDS.64 R14, [R24.X4+0x18] ; FFMA R16, R19, R16, R26 ; LDS R19, [R2.X4+UR5+0xa8] ; FFMA R16, R27, R17, R16 ; FFMA R14, R25, R14, R16 ; FFMA R19, R19, R15, R14 ; ISETP.NE.OR P0, PT, R18, RZ, P0 ; @!P0 BRA 0xa80 ; UMOV UR5, 0x18 ; MOV R14, UR4 ; UIMAD UR8, UR4, UR5, 0x90 ; IADD3 R18, R18, -0x4, RZ ; UIADD3 UR4, UR4, 0x4, URZ ; IMAD R27, R3, 0x6, R14 ; ISETP.NE.AND P0, PT, R18, RZ, PT ; LDS R24, [R2.X4+UR8] ; LDS.64 R14, [R27.X4] ; LDS R26, [R2.X4+UR8+0x18] ; LDS R25, [R2.X4+UR8+0x30] ; LDS.64 R16, [R27.X4+0x8] ; FFMA R14, R24, R14, R19 ; LDS R19, [R2.X4+UR8+0x48] ; FFMA R14, R26, R15, R14 ; FFMA R14, R25, R16, R14 ; FFMA R19, R19, R17, R14 ; @P0 BRA 0x970 ; ISETP.NE.AND P0, PT, R11, RZ, PT ; @!P0 BRA 0xd70 ; MOV R14, UR4 ; UMOV UR5, 0x18 ; ISETP.NE.AND P0, PT, R11, 0x1, PT ; UIMAD UR4, UR4, UR5, 0x90 ; IMAD R14, R3, 0x6, R14 ; SHF.L.U32 R17, R14, 0x2, RZ ; LDS R16, [R2.X4+UR4] ; LDS.64 R14, [R17] ; FFMA R19, R16, R14, R19 ; @!P0 BRA 0xd70 ; LDS R14, [R2.X4+UR4+0x18] ; ISETP.NE.AND P0, PT, R11, 0x2, PT ; FFMA R19, R14, R15, R19 ; @!P0 BRA 0xd70 ; LDS R15, [R17+0x8] ; LDS R14, [R2.X4+UR4+0x30] ; FFMA R19, R14, R15, R19 ; BRA 0xd70 ; HFMA2.MMA R24, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD R14, R10.reuse, 0x6, R8 ; IMAD R17, R10, 0x6, R3 ; IMAD R17, R17, c[0x0][0x188], R4 ; IMAD.WIDE R14, R14, R24, c[0x0][0x160] ; IMAD.WIDE R24, R17, R24, c[0x0][0x168] ; LDG.E R14, [R14.64] ; LDG.E R25, [R24.64] ; FMUL R29, R14, c[0x0][0x178] ; STS [R12+0x90], R25 ; STS [R12], R29 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDS R18, [R2.X4+0x90] ; LDS.64 R16, [R7] ; LDS R26, [R2.X4+0xa8] ; LDS R27, [R2.X4+0xc0] ; LDS.64 R14, [R7+0x8] ; LDS R24, [R2.X4+0x108] ; FFMA R16, R18, R16, R19 ; LDS R18, [R2.X4+0xd8] ; FFMA R26, R26, R17, R16 ; LDS R19, [R2.X4+0xf0] ; LDS.64 R16, [R7+0x10] ; FFMA R14, R27, R14, R26 ; FFMA R15, R18, R15, R14 ; FFMA R16, R19, R16, R15 ; FFMA R19, R24, R17, R16 ; IADD3 R10, R10, 0x1, RZ ; @!P2 BRA 0x200 ; BRA 0xdb0 ; MOV R19, RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD R4, R13, c[0x0][0x188], R4 ; IMAD.WIDE R2, R4, R5, c[0x0][0x170] ; LDG.E R2, [R2.64] ; IMAD.WIDE R4, R4, R5, c[0x0][0x180] ; FFMA R19, R2, c[0x0][0x17c], R19 ; STG.E [R4.64], R19 ; EXIT ; BRA 0xe40; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z7maxpoolPfS_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IABS R6, c[0x0][0x174] ; S2R R7, SR_TID.Y ; IABS R4, c[0x0][0x170] ; ULDC.64 UR4, c[0x0][0x170] ; I2F.RP R0, R6 ; ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; ISETP.LE.AND P2, PT, RZ, UR4, PT ; MUFU.RCP R0, R0 ; IADD3 R2, R0, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.MOV R5, RZ, RZ, -R3 ; IMAD R5, R5, R6, RZ ; IMAD.HI.U32 R3, R3, R5, R2 ; S2R R5, SR_CTAID.X ; IMAD.HI.U32 R0, R3, R4, RZ ; S2R R2, SR_TID.X ; IMAD.MOV R3, RZ, RZ, -R0 ; IMAD R3, R6.reuse, R3, R4 ; S2R R4, SR_CTAID.Y ; ISETP.GT.U32.AND P1, PT, R6, R3, PT ; IMAD R5, R5, c[0x0][0x0], R2 ; @!P1 IADD3 R0, R0, 0x1, RZ ; @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; ISETP.NE.AND P1, PT, RZ, c[0x0][0x174], PT ; ISETP.GE.U32.AND P0, PT, R3, R6, PT ; IMAD R3, R4, c[0x0][0x4], R7 ; @P0 IADD3 R0, R0, 0x1, RZ ; @!P2 IMAD.MOV R0, RZ, RZ, -R0 ; @!P1 LOP3.LUT R0, RZ, c[0x0][0x174], RZ, 0x33, !PT ; ISETP.GE.AND P0, PT, R3, R0, PT ; ISETP.GE.OR P0, PT, R5, R0, P0 ; @P0 EXIT ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x174] ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.MOV.U32 R18, RZ, RZ, -0x368bdc02 ; ISETP.GE.AND P0, PT, R4, 0x1, PT ; @!P0 BRA 0xe70 ; IADD3 R2, R4.reuse, -0x1, RZ ; IMAD.MOV.U32 R18, RZ, RZ, -0x368bdc02 ; LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; IADD3 R7, -R4, c[0x0][0x174], RZ ; IMAD R8, R5, c[0x0][0x174], R6 ; IADD3 R6, R6, 0x1, RZ ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; ISETP.GE.AND P2, PT, R6, c[0x0][0x174], PT ; @!P1 BRA 0xce0 ; ISETP.GT.AND P0, PT, R7, RZ, PT ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R7 ; @!P0 BRA 0xb70 ; ISETP.GT.AND P3, PT, R2, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P3 BRA 0x8a0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IMAD R11, R3, c[0x0][0x174], R10 ; IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; IMAD R16, R11, c[0x0][0x170], R8 ; IMAD.WIDE R16, R16, R9, c[0x0][0x160] ; LDG.E R19, [R16.64] ; IMAD.WIDE R22, R9, c[0x0][0x170], R16 ; LDG.E R11, [R22.64] ; IMAD.WIDE R14, R9, c[0x0][0x170], R22 ; IADD3 R20, R10, 0x4, RZ ; LDG.E R12, [R14.64] ; IMAD R13, R3, c[0x0][0x174], R20 ; IMAD.WIDE R28, R9, c[0x0][0x170], R14 ; IMAD R24, R13, c[0x0][0x170], R8 ; LDG.E R13, [R28.64] ; IMAD.WIDE R24, R24, R9, c[0x0][0x160] ; LDG.E R20, [R24.64] ; IMAD.WIDE R16, R9, c[0x0][0x170], R24 ; LDG.E R21, [R16.64] ; IMAD.WIDE R26, R9, c[0x0][0x170], R16 ; IADD3 R23, R10, 0x8, RZ ; LDG.E R22, [R26.64] ; IMAD R23, R3, c[0x0][0x174], R23 ; IMAD.WIDE R14, R9, c[0x0][0x170], R26 ; IMAD R28, R23, c[0x0][0x170], R8 ; LDG.E R23, [R14.64] ; IMAD.WIDE R28, R28, R9, c[0x0][0x160] ; LDG.E R24, [R28.64] ; IMAD.WIDE R28, R9, c[0x0][0x170], R28 ; LDG.E R25, [R28.64] ; IMAD.WIDE R16, R9, c[0x0][0x170], R28 ; IADD3 R27, R10, 0xc, RZ ; LDG.E R26, [R16.64] ; IMAD.WIDE R14, R9, c[0x0][0x170], R16 ; IMAD R17, R3, c[0x0][0x174], R27 ; LDG.E R27, [R14.64] ; IMAD R14, R17, c[0x0][0x170], R8 ; IMAD.WIDE R14, R14, R9, c[0x0][0x160] ; LDG.E R28, [R14.64] ; IMAD.WIDE R16, R9, c[0x0][0x170], R14 ; LDG.E R29, [R16.64] ; FSETP.GEU.AND P3, PT, R18, R19, PT ; FSEL R14, R19, R18, !P3 ; IMAD.WIDE R18, R9, c[0x0][0x170], R16 ; FSETP.GEU.AND P3, PT, R14, R11, PT ; FSEL R17, R11, R14, !P3 ; LDG.E R11, [R18.64] ; IMAD.WIDE R18, R9, c[0x0][0x170], R18 ; LDG.E R9, [R18.64] ; FSETP.GEU.AND P3, PT, R17, R12, PT ; FSEL R12, R12, R17, !P3 ; FSETP.GEU.AND P3, PT, R12, R13, PT ; FSEL R13, R13, R12, !P3 ; FSETP.GEU.AND P3, PT, R13, R20, PT ; FSEL R20, R20, R13, !P3 ; FSETP.GEU.AND P3, PT, R20, R21, PT ; FSEL R21, R21, R20, !P3 ; FSETP.GEU.AND P3, PT, R21, R22, PT ; FSEL R22, R22, R21, !P3 ; FSETP.GEU.AND P3, PT, R22, R23, PT ; FSEL R23, R23, R22, !P3 ; FSETP.GEU.AND P3, PT, R23, R24, PT ; FSEL R24, R24, R23, !P3 ; FSETP.GEU.AND P3, PT, R24, R25, PT ; FSEL R25, R25, R24, !P3 ; FSETP.GEU.AND P3, PT, R25, R26, PT ; FSEL R26, R26, R25, !P3 ; FSETP.GEU.AND P3, PT, R26, R27, PT ; FSEL R27, R27, R26, !P3 ; FSETP.GEU.AND P3, PT, R27, R28, PT ; FSEL R28, R28, R27, !P3 ; IADD3 R2, R2, -0x10, RZ ; FSETP.GEU.AND P3, PT, R28, R29, PT ; ISETP.GT.AND P4, PT, R2, 0xc, PT ; FSEL R28, R29, R28, !P3 ; IADD3 R10, R10, 0x10, RZ ; FSETP.GEU.AND P3, PT, R28, R11, PT ; FSEL R18, R11, R28, !P3 ; FSETP.GEU.AND P3, PT, R18, R9, PT ; FSEL R18, R9, R18, !P3 ; @P4 BRA 0x3a0 ; ISETP.GT.AND P3, PT, R2, 0x4, PT ; @!P3 BRA 0xb50 ; IMAD R9, R3, c[0x0][0x174], R10 ; IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; IMAD R20, R9, c[0x0][0x170], R8 ; IMAD.WIDE R20, R20, R11, c[0x0][0x160] ; LDG.E R9, [R20.64] ; IMAD.WIDE R22, R11, c[0x0][0x170], R20 ; IADD3 R14, R10, 0x4, RZ ; LDG.E R19, [R22.64] ; IMAD.WIDE R12, R11, c[0x0][0x170], R22 ; IMAD R17, R3, c[0x0][0x174], R14 ; LDG.E R24, [R12.64] ; IMAD.WIDE R14, R11, c[0x0][0x170], R12 ; IMAD R16, R17, c[0x0][0x170], R8 ; LDG.E R14, [R14.64] ; IMAD.WIDE R16, R16, R11, c[0x0][0x160] ; LDG.E R25, [R16.64] ; IMAD.WIDE R20, R11, c[0x0][0x170], R16 ; LDG.E R26, [R20.64] ; IMAD.WIDE R22, R11, c[0x0][0x170], R20 ; LDG.E R28, [R22.64] ; IMAD.WIDE R12, R11, c[0x0][0x170], R22 ; LDG.E R13, [R12.64] ; IADD3 R2, R2, -0x8, RZ ; IADD3 R10, R10, 0x8, RZ ; FSETP.GEU.AND P0, PT, R18, R9, PT ; FSEL R18, R9, R18, !P0 ; FSETP.GEU.AND P0, PT, R18, R19, PT ; FSEL R19, R19, R18, !P0 ; FSETP.GEU.AND P0, PT, R19, R24, PT ; FSEL R19, R24, R19, !P0 ; FSETP.GEU.AND P0, PT, R19, R14, PT ; FSEL R14, R14, R19, !P0 ; FSETP.GEU.AND P0, PT, R14, R25, PT ; FSEL R25, R25, R14, !P0 ; FSETP.GEU.AND P0, PT, R25, R26, PT ; FSEL R25, R26, R25, !P0 ; FSETP.GEU.AND P0, PT, R25, R28, PT ; FSEL R18, R28, R25, !P0 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; FSETP.GEU.AND P3, PT, R18, R13, PT ; FSEL R18, R13, R18, !P3 ; ISETP.NE.OR P0, PT, R2, RZ, P0 ; @!P0 BRA 0xce0 ; IMAD R9, R3, c[0x0][0x174], R10 ; IMAD.MOV.U32 R21, RZ, RZ, 0x4 ; IMAD R9, R9, c[0x0][0x170], R8 ; IMAD.WIDE R14, R9, R21, c[0x0][0x160] ; LDG.E R9, [R14.64] ; IMAD.WIDE R16, R21, c[0x0][0x170], R14 ; LDG.E R22, [R16.64] ; IMAD.WIDE R12, R21, c[0x0][0x170], R16 ; LDG.E R24, [R12.64] ; IMAD.WIDE R20, R21, c[0x0][0x170], R12 ; LDG.E R20, [R20.64] ; IADD3 R2, R2, -0x4, RZ ; IADD3 R10, R10, 0x4, RZ ; ISETP.NE.AND P3, PT, R2, RZ, PT ; FSETP.GEU.AND P0, PT, R18, R9, PT ; FSEL R9, R9, R18, !P0 ; FSETP.GEU.AND P0, PT, R9, R22, PT ; FSEL R9, R22, R9, !P0 ; FSETP.GEU.AND P0, PT, R9, R24, PT ; FSEL R9, R24, R9, !P0 ; FSETP.GEU.AND P0, PT, R9, R20, PT ; FSEL R18, R20, R9, !P0 ; @P3 BRA 0xb70 ; ISETP.NE.AND P0, PT, R4, RZ, PT ; @!P0 BRA 0xe60 ; IMAD R13, R3, c[0x0][0x174], R10 ; IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; IMAD R10, R13, c[0x0][0x170], R8 ; IMAD.WIDE R10, R10, R15, c[0x0][0x160] ; LDG.E R11, [R10.64] ; ISETP.NE.AND P3, PT, R4, 0x1, PT ; FSETP.GEU.AND P0, PT, R18, R11, PT ; FSEL R18, R11, R18, !P0 ; @!P3 BRA 0xe60 ; ISETP.NE.AND P3, PT, R4, 0x2, PT ; IADD3 R9, R13, 0x1, RZ ; IMAD R9, R9, c[0x0][0x170], R8 ; IMAD.WIDE R10, R9, R15, c[0x0][0x160] ; @P3 IADD3 R13, R13, 0x2, RZ ; LDG.E R11, [R10.64] ; @P3 IMAD R8, R13, c[0x0][0x170], R8 ; @P3 IMAD.WIDE R8, R8, R15, c[0x0][0x160] ; @P3 LDG.E R9, [R8.64] ; FSETP.GEU.AND P0, PT, R18, R11, PT ; FSEL R18, R11, R18, !P0 ; @P3 FSETP.GEU.AND P0, PT, R18, R9, PT ; @P3 FSEL R18, R9, R18, !P0 ; @!P2 BRA 0x2d0 ; IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; IMAD R3, R3, R0, R5 ; IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; STG.E [R2.64], R18 ; EXIT ; BRA 0xec0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000fd7b6_00000000-6_1fea697b976a957608aafde96cf25b25108b198f.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4166: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4166: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z30__device_stub__Z7maxpoolPfS_iiPfS_ii .type _Z30__device_stub__Z7maxpoolPfS_iiPfS_ii, @function _Z30__device_stub__Z7maxpoolPfS_iiPfS_ii: .LFB4188: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7maxpoolPfS_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE4188: .size _Z30__device_stub__Z7maxpoolPfS_iiPfS_ii, .-_Z30__device_stub__Z7maxpoolPfS_iiPfS_ii .globl _Z7maxpoolPfS_ii .type _Z7maxpoolPfS_ii, @function _Z7maxpoolPfS_ii: .LFB4189: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z7maxpoolPfS_iiPfS_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4189: .size _Z7maxpoolPfS_ii, .-_Z7maxpoolPfS_ii .globl _Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i .type _Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i, @function _Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i: .LFB4190: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movss %xmm0, 20(%rsp) movss %xmm1, 16(%rsp) movq %rcx, 8(%rsp) movl %r8d, 4(%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 20(%rsp), %rax movq %rax, 136(%rsp) leaq 16(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) leaq 4(%rsp), %rax movq %rax, 160(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 168(%rsp), %rax subq %fs:40, %rax jne .L16 addq $184, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 200 pushq 56(%rsp) .cfi_def_cfa_offset 208 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z4gemmPfS_S_ffS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE4190: .size _Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i, .-_Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i .globl _Z4gemmPfS_S_ffS_i .type _Z4gemmPfS_S_ffS_i, @function _Z4gemmPfS_S_ffS_i: .LFB4191: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4191: .size _Z4gemmPfS_S_ffS_i, .-_Z4gemmPfS_S_ffS_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z4gemmPfS_S_ffS_i" .LC1: .string "_Z7maxpoolPfS_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4193: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z4gemmPfS_S_ffS_i(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z7maxpoolPfS_ii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4193: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat .weak _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_ .type _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_: .LFB4267: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA4267 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $40, %rsp .cfi_def_cfa_offset 96 movq %rdi, %r13 movq %rsi, 8(%rsp) movq %rdx, %rbp movq %rcx, %r12 movl %r8d, %r14d movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax call __errno_location@PLT movq %rax, %rbx movl (%rax), %r15d movl $0, (%rax) leaq 16(%rsp), %rsi movl %r14d, %edx movq %rbp, %rdi .LEHB0: call *%r13 movq 16(%rsp), %rcx cmpq %rbp, %rcx je .L35 cmpl $34, (%rbx) je .L24 movl $2147483648, %edx addq %rax, %rdx shrq $32, %rdx jne .L24 testq %r12, %r12 je .L27 subq %rbp, %rcx movq %rcx, (%r12) .L27: cmpl $0, (%rbx) jne .L21 movl %r15d, (%rbx) .L21: movq 24(%rsp), %rdx subq %fs:40, %rdx jne .L36 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L35: .cfi_restore_state movq 24(%rsp), %rax subq %fs:40, %rax jne .L37 movq 8(%rsp), %rdi call _ZSt24__throw_invalid_argumentPKc@PLT .L37: call __stack_chk_fail@PLT .L24: movq 24(%rsp), %rax subq %fs:40, %rax jne .L38 movq 8(%rsp), %rdi call _ZSt20__throw_out_of_rangePKc@PLT .LEHE0: .L33: endbr64 movq %rax, %rdi cmpl $0, (%rbx) jne .L30 movl %r15d, (%rbx) .L30: movq 24(%rsp), %rax subq %fs:40, %rax je .L31 call __stack_chk_fail@PLT .L38: call __stack_chk_fail@PLT .L31: .LEHB1: call _Unwind_Resume@PLT .LEHE1: .L36: call __stack_chk_fail@PLT .cfi_endproc .LFE4267: .globl __gxx_personality_v0 .section .gcc_except_table._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat .LLSDA4267: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE4267-.LLSDACSB4267 .LLSDACSB4267: .uleb128 .LEHB0-.LFB4267 .uleb128 .LEHE0-.LEHB0 .uleb128 .L33-.LFB4267 .uleb128 0 .uleb128 .LEHB1-.LFB4267 .uleb128 .LEHE1-.LEHB1 .uleb128 0 .uleb128 0 .LLSDACSE4267: .section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat .size _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_ .section .text._ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat .weak _ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_ .type _ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function _ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_: .LFB4312: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA4312 endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $24, %rsp .cfi_def_cfa_offset 80 movq %rdi, %r15 movq %rsi, %r14 movq %rdx, %rbp movq %rcx, %r12 movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax call __errno_location@PLT movq %rax, %rbx movl (%rax), %r13d movl $0, (%rax) movq %rsp, %rsi movq %rbp, %rdi .LEHB2: call *%r15 movq (%rsp), %rax cmpq %rbp, %rax je .L52 cmpl $34, (%rbx) je .L53 testq %r12, %r12 je .L44 subq %rbp, %rax movq %rax, (%r12) .L44: cmpl $0, (%rbx) jne .L39 movl %r13d, (%rbx) .L39: movq 8(%rsp), %rax subq %fs:40, %rax jne .L54 addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L52: .cfi_restore_state movq 8(%rsp), %rax subq %fs:40, %rax jne .L55 movq %r14, %rdi call _ZSt24__throw_invalid_argumentPKc@PLT .L50: endbr64 movq %rax, %rdi cmpl $0, (%rbx) jne .L47 movl %r13d, (%rbx) .L47: movq 8(%rsp), %rax subq %fs:40, %rax je .L48 call __stack_chk_fail@PLT .L55: call __stack_chk_fail@PLT .L53: movq 8(%rsp), %rax subq %fs:40, %rax jne .L56 movq %r14, %rdi call _ZSt20__throw_out_of_rangePKc@PLT .LEHE2: .L56: call __stack_chk_fail@PLT .L48: .LEHB3: call _Unwind_Resume@PLT .LEHE3: .L54: call __stack_chk_fail@PLT .cfi_endproc .LFE4312: .section .gcc_except_table._ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat .LLSDA4312: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE4312-.LLSDACSB4312 .LLSDACSB4312: .uleb128 .LEHB2-.LFB4312 .uleb128 .LEHE2-.LEHB2 .uleb128 .L50-.LFB4312 .uleb128 0 .uleb128 .LEHB3-.LFB4312 .uleb128 .LEHE3-.LEHB3 .uleb128 0 .uleb128 0 .LLSDACSE4312: .section .text._ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat .size _ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_ .section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1 .align 8 .LC2: .string "basic_string: construction from null is not valid" .section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat .align 2 .weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_: .LFB4511: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $24, %rsp .cfi_def_cfa_offset 64 movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax leaq 16(%rdi), %r12 movq %r12, (%rdi) testq %rsi, %rsi je .L66 movq %rdi, %rbx movq %rsi, %r13 movq %rsi, %rdi call strlen@PLT movq %rax, %rbp movq %rax, (%rsp) cmpq $15, %rax ja .L67 cmpq $1, %rax jne .L62 movzbl 0(%r13), %eax movb %al, 16(%rbx) .L63: movq (%rsp), %rax movq %rax, 8(%rbx) movq (%rbx), %rdx movb $0, (%rdx,%rax) movq 8(%rsp), %rax subq %fs:40, %rax jne .L68 addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L66: .cfi_restore_state movq 8(%rsp), %rax subq %fs:40, %rax jne .L69 leaq .LC2(%rip), %rdi call _ZSt19__throw_logic_errorPKc@PLT .L69: call __stack_chk_fail@PLT .L67: movq %rsp, %rsi movl $0, %edx movq %rbx, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT movq %rax, %r12 movq %rax, (%rbx) movq (%rsp), %rax movq %rax, 16(%rbx) .L61: movq %rbp, %rdx movq %r13, %rsi movq %r12, %rdi call memcpy@PLT jmp .L63 .L62: testq %rax, %rax je .L63 jmp .L61 .L68: call __stack_chk_fail@PLT .cfi_endproc .LFE4511: .size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ .section .rodata.str1.1 .LC3: .string "usage : " .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC4: .string " input_size filter_size alpha beta\n" .section .rodata.str1.1 .LC5: .string "example : " .LC6: .string " 100 2 0.5 0.8\n" .LC7: .string "stoi" .LC8: .string "stof" .LC9: .string "filter_size cannot be 0\n" .LC10: .string "input.txt" .LC11: .string "a.txt" .LC12: .string "b.txt" .LC13: .string "c.txt" .LC14: .string "filter size : " .section .rodata.str1.8 .align 8 .LC15: .string "\n========== MAXPOOL_INPUT ==========\n" .section .rodata.str1.1 .LC16: .string "\n" .LC17: .string " " .LC18: .string "\nalpha : " .LC19: .string "========== A ==========\n" .LC20: .string "\n========== B ==========\n" .LC21: .string "\nbeta : " .LC22: .string "========== C ==========\n" .LC23: .string "ERROR %s\n" .section .rodata.str1.8 .align 8 .LC24: .string "\n========== GEMM OUTPUT ==========\n" .align 8 .LC25: .string "\n========== MAXPOOL OUTPUT ==========\n" .text .globl main .type main, @function main: .LFB4163: .cfi_startproc .cfi_personality 0x9b,DW.ref.__gxx_personality_v0 .cfi_lsda 0x1b,.LLSDA4163 endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsp, %rbp .cfi_def_cfa_register 6 pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $2296, %rsp .cfi_offset 15, -24 .cfi_offset 14, -32 .cfi_offset 13, -40 .cfi_offset 12, -48 .cfi_offset 3, -56 movq %rsi, %rbx movq %fs:40, %rax movq %rax, -56(%rbp) xorl %eax, %eax cmpl $3, %edi jle .L145 leaq -2172(%rbp), %rdx movq 8(%rsi), %rsi leaq -576(%rbp), %rdi .LEHB4: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .LEHE4: movl $10, %r8d movl $0, %ecx movq -576(%rbp), %rdx leaq .LC7(%rip), %rsi movq __isoc23_strtol@GOTPCREL(%rip), %rdi .LEHB5: call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_ .LEHE5: jmp .L146 .L145: leaq .LC3(%rip), %rsi leaq _ZSt4cout(%rip), %rdi .LEHB6: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq (%rbx), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi leaq .LC4(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi leaq .LC5(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq (%rbx), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi leaq .LC6(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl $1, %ebx jmp .L70 .L146: movl %eax, %r15d leaq -576(%rbp), %r12 movq %r12, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq -2172(%rbp), %rdx movq 16(%rbx), %rsi movq %r12, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .LEHE6: movl $10, %r8d movl $0, %ecx movq -576(%rbp), %rdx leaq .LC7(%rip), %rsi movq __isoc23_strtol@GOTPCREL(%rip), %rdi .LEHB7: call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_ .LEHE7: movl %eax, %r14d movl %eax, -2320(%rbp) movq %r12, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq -2172(%rbp), %rdx movq 24(%rbx), %rsi movq %r12, %rdi .LEHB8: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .LEHE8: movl $0, %ecx movq -576(%rbp), %rdx leaq .LC8(%rip), %rsi movq strtof@GOTPCREL(%rip), %rdi .LEHB9: call _ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_ .LEHE9: movss %xmm0, -2324(%rbp) movq %r12, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT leaq -2172(%rbp), %rdx movq 32(%rbx), %rsi movq %r12, %rdi .LEHB10: call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_ .LEHE10: movl $0, %ecx movq -576(%rbp), %rdx leaq .LC8(%rip), %rsi movq strtof@GOTPCREL(%rip), %rdi .LEHB11: call _ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_ .LEHE11: movss %xmm0, -2328(%rbp) movq %r12, %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT testl %r14d, %r14d je .L147 movl %r15d, %eax imull %r15d, %eax movl %eax, -2316(%rbp) cltq movq %rax, -2264(%rbp) salq $2, %rax movq %rax, -2304(%rbp) addq $15, %rax movq %rax, %rcx andq $-16, %rcx andq $-4096, %rax movq %rsp, %rdx subq %rax, %rdx .L74: cmpq %rdx, %rsp je .L75 subq $4096, %rsp orq $0, 4088(%rsp) jmp .L74 .L147: leaq .LC9(%rip), %rsi leaq _ZSt4cout(%rip), %rdi .LEHB12: call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl $1, %ebx jmp .L70 .L75: movq %rcx, %rax andl $4095, %eax subq %rax, %rsp testq %rax, %rax je .L76 orq $0, -8(%rsp,%rax) .L76: movq %rsp, -2272(%rbp) movq -2304(%rbp), %rax addq $15, %rax movq %rax, %rcx andq $-16, %rcx andq $-4096, %rax movq %rsp, %rdx subq %rax, %rdx .L77: cmpq %rdx, %rsp je .L78 subq $4096, %rsp orq $0, 4088(%rsp) jmp .L77 .L78: movq %rcx, %rax andl $4095, %eax subq %rax, %rsp testq %rax, %rax je .L79 orq $0, -8(%rsp,%rax) .L79: movq %rsp, -2280(%rbp) movq -2304(%rbp), %rax addq $15, %rax movq %rax, %rcx andq $-16, %rcx andq $-4096, %rax movq %rsp, %rdx subq %rax, %rdx .L80: cmpq %rdx, %rsp je .L81 subq $4096, %rsp orq $0, 4088(%rsp) jmp .L80 .L81: movq %rcx, %rax andl $4095, %eax subq %rax, %rsp testq %rax, %rax je .L82 orq $0, -8(%rsp,%rax) .L82: movq %rsp, -2288(%rbp) movq -2304(%rbp), %rax addq $15, %rax movq %rax, %rdx andq $-16, %rdx andq $-4096, %rax movq %rsp, %rcx subq %rax, %rcx .L83: cmpq %rcx, %rsp je .L84 subq $4096, %rsp orq $0, 4088(%rsp) jmp .L83 .L84: movq %rdx, %rax andl $4095, %eax subq %rax, %rsp testq %rax, %rax je .L85 orq $0, -8(%rsp,%rax) .L85: movq %rsp, %r12 movq %r12, -2296(%rbp) leaq -2160(%rbp), %rdi movl $8, %edx leaq .LC10(%rip), %rsi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT .LEHE12: leaq -1632(%rbp), %rdi movl $8, %edx leaq .LC11(%rip), %rsi .LEHB13: call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT .LEHE13: leaq -1104(%rbp), %rdi movl $8, %edx leaq .LC12(%rip), %rsi .LEHB14: call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT .LEHE14: leaq -576(%rbp), %rdi movl $8, %edx leaq .LC13(%rip), %rsi .LEHB15: call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT .LEHE15: cmpl $0, -2316(%rbp) jle .L86 movq -2272(%rbp), %rcx movq %rcx, %rbx movq -2288(%rbp), %r14 movq -2280(%rbp), %r13 movq -2304(%rbp), %rax addq %rcx, %rax movq %rax, -2304(%rbp) leaq -2160(%rbp), %rax movq %rax, -2312(%rbp) jmp .L87 .L148: leaq -1632(%rbp), %rdi movq %r13, %rsi .LEHB16: call _ZNSi10_M_extractIfEERSiRT_@PLT leaq -1104(%rbp), %rdi movq %r14, %rsi call _ZNSi10_M_extractIfEERSiRT_@PLT leaq -576(%rbp), %rdi movq %r12, %rsi call _ZNSi10_M_extractIfEERSiRT_@PLT addq $4, %rbx addq $4, %r12 addq $4, %r14 addq $4, %r13 movq -2304(%rbp), %rax cmpq %rax, %rbx je .L86 .L87: movq %rbx, %rsi movq -2312(%rbp), %rdi call _ZNSi10_M_extractIfEERSiRT_@PLT jmp .L148 .L86: leaq .LC14(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl -2320(%rbp), %esi call _ZNSolsEi@PLT leaq .LC15(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpl $0, -2316(%rbp) jle .L88 movl $0, %ebx leaq .LC16(%rip), %r14 leaq _ZSt4cout(%rip), %r12 leaq .LC17(%rip), %r13 jmp .L90 .L89: movq -2272(%rbp), %rax pxor %xmm0, %xmm0 cvtss2sd (%rax,%rbx,4), %xmm0 movq %r12, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi movl $1, %edx movq %r13, %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT addq $1, %rbx cmpq %rbx, -2264(%rbp) je .L88 .L90: movl %ebx, %eax cltd idivl %r15d testl %edx, %edx jne .L89 movl $1, %edx movq %r14, %rsi movq %r12, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT jmp .L89 .L88: leaq .LC18(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd -2324(%rbp), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi movl $10, %esi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT leaq .LC19(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpl $0, -2316(%rbp) jle .L91 movl $0, %ebx leaq .LC16(%rip), %r14 leaq _ZSt4cout(%rip), %r12 leaq .LC17(%rip), %r13 jmp .L93 .L92: movq -2280(%rbp), %rax pxor %xmm0, %xmm0 cvtss2sd (%rax,%rbx,4), %xmm0 movq %r12, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi movl $1, %edx movq %r13, %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT addq $1, %rbx cmpq %rbx, -2264(%rbp) je .L91 .L93: movl %ebx, %eax cltd idivl %r15d testl %edx, %edx jne .L92 movl $1, %edx movq %r14, %rsi movq %r12, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT jmp .L92 .L91: leaq .LC20(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpl $0, -2316(%rbp) jle .L94 movl $0, %ebx leaq .LC16(%rip), %r14 leaq _ZSt4cout(%rip), %r12 leaq .LC17(%rip), %r13 jmp .L96 .L95: movq -2288(%rbp), %rax pxor %xmm0, %xmm0 cvtss2sd (%rax,%rbx,4), %xmm0 movq %r12, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi movl $1, %edx movq %r13, %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT addq $1, %rbx cmpq %rbx, -2264(%rbp) je .L94 .L96: movl %ebx, %eax cltd idivl %r15d testl %edx, %edx jne .L95 movl $1, %edx movq %r14, %rsi movq %r12, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT jmp .L95 .L94: leaq .LC21(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd -2328(%rbp), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi movl $10, %esi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT leaq .LC22(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpl $0, -2316(%rbp) jle .L97 movl $0, %ebx leaq .LC16(%rip), %r14 leaq _ZSt4cout(%rip), %r12 leaq .LC17(%rip), %r13 jmp .L99 .L98: movq -2296(%rbp), %rax pxor %xmm0, %xmm0 cvtss2sd (%rax,%rbx,4), %xmm0 movq %r12, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi movl $1, %edx movq %r13, %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT addq $1, %rbx cmpq %rbx, -2264(%rbp) je .L97 .L99: movl %ebx, %eax cltd idivl %r15d testl %edx, %edx jne .L98 movl $1, %edx movq %r14, %rsi movq %r12, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT jmp .L98 .L97: movl $10, %esi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT movl %r15d, %eax cltd idivl -2320(%rbp) movl %eax, -2312(%rbp) movl %eax, %r14d movl %eax, -2304(%rbp) movl $1, -2188(%rbp) movl $6, %ecx movl $0, %edx divl %ecx addl $1, %eax movl %eax, -2184(%rbp) movl %eax, -2180(%rbp) movl $1, -2176(%rbp) movl %r15d, %eax movl $0, %edx divl %ecx addl $1, %eax movl %eax, -2172(%rbp) movl %eax, -2168(%rbp) movl $1, -2164(%rbp) movslq %r15d, %rbx imulq %rbx, %rbx salq $2, %rbx leaq -2248(%rbp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq -2240(%rbp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq -2232(%rbp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq -2216(%rbp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq -2224(%rbp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movslq %r14d, %rax imulq %rax, %rax leaq 0(,%rax,4), %r12 leaq -2208(%rbp), %rdi movq %r12, %rsi call cudaMalloc@PLT movl $1, %ecx movq %rbx, %rdx movq -2280(%rbp), %rsi movq -2248(%rbp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq -2288(%rbp), %rsi movq -2240(%rbp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq -2296(%rbp), %rsi movq -2232(%rbp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq -2272(%rbp), %rsi movq -2224(%rbp), %rdi call cudaMemcpy@PLT movl $6, -2196(%rbp) movl $6, -2192(%rbp) movl -2188(%rbp), %ecx movl $0, %r9d movl $0, %r8d movq -2196(%rbp), %rdx movq -2172(%rbp), %rdi movl -2164(%rbp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L100 movl %r15d, %r8d movq -2216(%rbp), %rcx movss -2328(%rbp), %xmm1 movss -2324(%rbp), %xmm0 movq -2232(%rbp), %rdx movq -2240(%rbp), %rsi movq -2248(%rbp), %rdi call _Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i .L100: call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT testl %eax, %eax jne .L149 movl -2188(%rbp), %ecx movl $0, %r9d movl $0, %r8d movq -2196(%rbp), %rdx movq -2184(%rbp), %rdi movl -2176(%rbp), %esi call __cudaPushCallConfiguration@PLT jmp .L150 .L149: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC23(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L151 .L150: testl %eax, %eax jne .L103 movl -2320(%rbp), %ecx movl %r15d, %edx movq -2208(%rbp), %rsi movq -2224(%rbp), %rdi call _Z30__device_stub__Z7maxpoolPfS_iiPfS_ii .L103: call cudaDeviceSynchronize@PLT call cudaGetLastError@PLT testl %eax, %eax jne .L152 movq %rbx, %rdi call malloc@PLT movq %rax, %r14 movq %r12, %rdi call malloc@PLT movq %rax, %r13 movl $2, %ecx movq %rbx, %rdx movq -2216(%rbp), %rsi movq %r14, %rdi call cudaMemcpy@PLT jmp .L153 .L152: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC23(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L154 .L153: movl $2, %ecx movq %r12, %rdx movq -2208(%rbp), %rsi movq %r13, %rdi call cudaMemcpy@PLT leaq .LC24(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT cmpl $0, -2316(%rbp) jle .L105 movl $0, %ebx leaq _ZSt4cout(%rip), %r12 jmp .L107 .L106: pxor %xmm0, %xmm0 cvtss2sd (%r14,%rbx,4), %xmm0 movq %r12, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC17(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT addq $1, %rbx cmpq %rbx, -2264(%rbp) je .L105 .L107: movl %ebx, %eax cltd idivl %r15d testl %edx, %edx jne .L106 leaq .LC16(%rip), %rsi movq %r12, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT jmp .L106 .L105: leaq .LC25(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl -2312(%rbp), %r15d imull %r15d, %r15d testl %r15d, %r15d jle .L108 movslq %r15d, %r12 movl $0, %ebx leaq _ZSt4cout(%rip), %r15 jmp .L110 .L109: pxor %xmm0, %xmm0 cvtss2sd 0(%r13,%rbx,4), %xmm0 movq %r15, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC17(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT addq $1, %rbx cmpq %r12, %rbx je .L108 .L110: movl %ebx, %eax cltd idivl -2304(%rbp) testl %edx, %edx jne .L109 leaq .LC16(%rip), %rsi movq %r15, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT jmp .L109 .L108: movl $10, %esi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT movq -2248(%rbp), %rdi call cudaFree@PLT movq -2240(%rbp), %rdi call cudaFree@PLT movq -2232(%rbp), %rdi call cudaFree@PLT movq -2216(%rbp), %rdi call cudaFree@PLT movq -2224(%rbp), %rdi call cudaFree@PLT movq -2208(%rbp), %rdi call cudaFree@PLT .LEHE16: movq %r14, %rdi call free@PLT movq %r13, %rdi call free@PLT movl $0, %ebx .L102: leaq -576(%rbp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT leaq -1104(%rbp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT leaq -1632(%rbp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT leaq -2160(%rbp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT .L70: movq -56(%rbp), %rax subq %fs:40, %rax jne .L155 movl %ebx, %eax leaq -40(%rbp), %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 popq %rbp .cfi_remember_state .cfi_def_cfa 7, 8 ret .L151: .cfi_restore_state movl $1, %ebx jmp .L102 .L154: movl $1, %ebx jmp .L102 .L127: endbr64 movq %rax, %rbx leaq -576(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq -56(%rbp), %rax subq %fs:40, %rax je .L112 call __stack_chk_fail@PLT .L112: movq %rbx, %rdi .LEHB17: call _Unwind_Resume@PLT .L128: endbr64 movq %rax, %rbx leaq -576(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq -56(%rbp), %rax subq %fs:40, %rax je .L114 call __stack_chk_fail@PLT .L114: movq %rbx, %rdi call _Unwind_Resume@PLT .L129: endbr64 movq %rax, %rbx leaq -576(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq -56(%rbp), %rax subq %fs:40, %rax je .L116 call __stack_chk_fail@PLT .L116: movq %rbx, %rdi call _Unwind_Resume@PLT .L130: endbr64 movq %rax, %rbx leaq -576(%rbp), %rdi call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT movq -56(%rbp), %rax subq %fs:40, %rax je .L118 call __stack_chk_fail@PLT .L118: movq %rbx, %rdi call _Unwind_Resume@PLT .L134: endbr64 movq %rax, %rbx leaq -576(%rbp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT .L120: leaq -1104(%rbp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT .L121: leaq -1632(%rbp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT .L122: leaq -2160(%rbp), %rdi call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT movq -56(%rbp), %rax subq %fs:40, %rax je .L123 call __stack_chk_fail@PLT .L133: endbr64 movq %rax, %rbx jmp .L120 .L132: endbr64 movq %rax, %rbx jmp .L121 .L131: endbr64 movq %rax, %rbx jmp .L122 .L123: movq %rbx, %rdi call _Unwind_Resume@PLT .LEHE17: .L155: call __stack_chk_fail@PLT .cfi_endproc .LFE4163: .section .gcc_except_table,"a",@progbits .LLSDA4163: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE4163-.LLSDACSB4163 .LLSDACSB4163: .uleb128 .LEHB4-.LFB4163 .uleb128 .LEHE4-.LEHB4 .uleb128 0 .uleb128 0 .uleb128 .LEHB5-.LFB4163 .uleb128 .LEHE5-.LEHB5 .uleb128 .L127-.LFB4163 .uleb128 0 .uleb128 .LEHB6-.LFB4163 .uleb128 .LEHE6-.LEHB6 .uleb128 0 .uleb128 0 .uleb128 .LEHB7-.LFB4163 .uleb128 .LEHE7-.LEHB7 .uleb128 .L128-.LFB4163 .uleb128 0 .uleb128 .LEHB8-.LFB4163 .uleb128 .LEHE8-.LEHB8 .uleb128 0 .uleb128 0 .uleb128 .LEHB9-.LFB4163 .uleb128 .LEHE9-.LEHB9 .uleb128 .L129-.LFB4163 .uleb128 0 .uleb128 .LEHB10-.LFB4163 .uleb128 .LEHE10-.LEHB10 .uleb128 0 .uleb128 0 .uleb128 .LEHB11-.LFB4163 .uleb128 .LEHE11-.LEHB11 .uleb128 .L130-.LFB4163 .uleb128 0 .uleb128 .LEHB12-.LFB4163 .uleb128 .LEHE12-.LEHB12 .uleb128 0 .uleb128 0 .uleb128 .LEHB13-.LFB4163 .uleb128 .LEHE13-.LEHB13 .uleb128 .L131-.LFB4163 .uleb128 0 .uleb128 .LEHB14-.LFB4163 .uleb128 .LEHE14-.LEHB14 .uleb128 .L132-.LFB4163 .uleb128 0 .uleb128 .LEHB15-.LFB4163 .uleb128 .LEHE15-.LEHB15 .uleb128 .L133-.LFB4163 .uleb128 0 .uleb128 .LEHB16-.LFB4163 .uleb128 .LEHE16-.LEHB16 .uleb128 .L134-.LFB4163 .uleb128 0 .uleb128 .LEHB17-.LFB4163 .uleb128 .LEHE17-.LEHB17 .uleb128 0 .uleb128 0 .LLSDACSE4163: .text .size main, .-main .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .hidden DW.ref.__gxx_personality_v0 .weak DW.ref.__gxx_personality_v0 .section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat .align 8 .type DW.ref.__gxx_personality_v0, @object .size DW.ref.__gxx_personality_v0, 8 DW.ref.__gxx_personality_v0: .quad __gxx_personality_v0 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z7maxpoolPfS_ii ; -- Begin function _Z7maxpoolPfS_ii .globl _Z7maxpoolPfS_ii .p2align 8 .type _Z7maxpoolPfS_ii,@function _Z7maxpoolPfS_ii: ; @_Z7maxpoolPfS_ii ; %bb.0: s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x10 s_load_b32 s4, s[0:1], 0x24 v_bfe_u32 v3, v0, 10, 10 v_and_b32_e32 v2, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_ashr_i32 s5, s3, 31 s_ashr_i32 s10, s2, 31 s_add_i32 s6, s3, s5 s_add_i32 s11, s2, s10 s_xor_b32 s6, s6, s5 s_xor_b32 s11, s11, s10 v_cvt_f32_u32_e32 v1, s6 s_sub_i32 s9, 0, s6 s_and_b32 s8, s4, 0xffff s_lshr_b32 s4, s4, 16 s_mul_i32 s14, s14, s8 v_rcp_iflag_f32_e32 v1, v1 s_xor_b32 s5, s10, s5 s_waitcnt_depctr 0xfff v_mul_f32_e32 v1, 0x4f7ffffe, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v1, v1 v_readfirstlane_b32 s7, v1 v_mad_u64_u32 v[0:1], null, s15, s4, v[3:4] v_add_nc_u32_e32 v1, s14, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s9, s9, s7 s_mul_hi_u32 s9, s7, s9 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_max_i32_e32 v3, v1, v0 s_add_i32 s7, s7, s9 s_mul_hi_u32 s7, s11, s7 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_mul_i32 s4, s7, s6 s_add_i32 s8, s7, 1 s_sub_i32 s4, s11, s4 s_sub_i32 s9, s4, s6 s_cmp_ge_u32 s4, s6 s_cselect_b32 s7, s8, s7 s_cselect_b32 s4, s9, s4 s_add_i32 s8, s7, 1 s_cmp_ge_u32 s4, s6 s_cselect_b32 s4, s8, s7 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_xor_b32 s4, s4, s5 s_sub_i32 s6, s4, s5 s_mov_b32 s4, exec_lo v_cmpx_gt_i32_e64 s6, v3 s_cbranch_execz .LBB0_8 ; %bb.1: ; %.preheader39 s_cmp_lt_i32 s3, 1 s_cbranch_scc1 .LBB0_6 ; %bb.2: ; %.preheader.lr.ph v_mul_lo_u32 v3, s2, v0 s_load_b64 s[4:5], s[0:1], 0x0 v_mov_b32_e32 v4, 0xc97423fe s_mov_b32 s7, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add3_u32 v2, v2, v3, s14 v_mul_lo_u32 v5, s3, v2 .p2align 6 .LBB0_3: ; %.preheader ; =>This Loop Header: Depth=1 ; Child Loop BB0_4 Depth 2 s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v2, v5 s_mov_b32 s8, s3 .LBB0_4: ; Parent Loop BB0_3 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_ashrrev_i32_e32 v3, 31, v2 s_add_i32 s8, s8, -1 s_cmp_eq_u32 s8, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_lshlrev_b64 v[6:7], 2, v[2:3] v_add_nc_u32_e32 v2, s2, v2 s_waitcnt lgkmcnt(0) v_add_co_u32 v6, vcc_lo, s4, v6 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo global_load_b32 v3, v[6:7], off s_waitcnt vmcnt(0) v_cmp_lt_f32_e32 vcc_lo, v4, v3 v_cndmask_b32_e32 v4, v4, v3, vcc_lo s_cbranch_scc0 .LBB0_4 ; %bb.5: ; %._crit_edge ; in Loop: Header=BB0_3 Depth=1 v_add_nc_u32_e32 v5, 1, v5 s_add_i32 s7, s7, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s7, s3 s_cbranch_scc0 .LBB0_3 s_branch .LBB0_7 .LBB0_6: v_mov_b32_e32 v4, 0xc97423fe .LBB0_7: ; %._crit_edge44 s_load_b64 s[0:1], s[0:1], 0x8 v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[0:1], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v4, off .LBB0_8: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z7maxpoolPfS_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z7maxpoolPfS_ii, .Lfunc_end0-_Z7maxpoolPfS_ii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 480 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .protected _Z4gemmPfS_S_ffS_i ; -- Begin function _Z4gemmPfS_S_ffS_i .globl _Z4gemmPfS_S_ffS_i .p2align 8 .type _Z4gemmPfS_S_ffS_i,@function _Z4gemmPfS_S_ffS_i: ; @_Z4gemmPfS_S_ffS_i ; %bb.0: s_clause 0x1 s_load_b32 s3, s[0:1], 0x3c s_load_b32 s2, s[0:1], 0x28 v_bfe_u32 v3, v0, 10, 10 v_and_b32_e32 v6, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_lshr_b32 s4, s3, 16 s_and_b32 s3, s3, 0xffff v_mad_u64_u32 v[0:1], null, s15, s4, v[3:4] v_mad_u64_u32 v[1:2], null, s14, s3, v[6:7] s_mov_b32 s3, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_max_i32_e32 v2, v0, v1 v_cmpx_gt_i32_e64 s2, v2 s_cbranch_execz .LBB1_20 ; %bb.1: ; %.preheader98 v_mov_b32_e32 v9, 0 s_cmp_lt_i32 s2, -5 s_cbranch_scc1 .LBB1_19 ; %bb.2: ; %.lr.ph108 s_mul_hi_i32 s3, s2, 0x2aaaaaab v_dual_mov_b32 v8, 0 :: v_dual_lshlrev_b32 v7, 2, v6 s_lshr_b32 s4, s3, 31 s_mov_b32 s13, 0 s_add_i32 s3, s3, s4 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b32 s8, s[0:1], 0x18 s_mul_i32 s9, s3, 6 v_add_nc_u32_e32 v2, 0x90, v7 s_sub_i32 s9, s2, s9 v_mad_u64_u32 v[4:5], null, v0, s2, v[6:7] s_cmp_lt_i32 s9, 1 v_mad_u32_u24 v5, v3, 24, v7 s_cselect_b32 s10, -1, 0 s_cmp_ge_u32 s15, s3 v_mul_u32_u24_e32 v6, 24, v3 v_mad_u32_u24 v7, v3, 24, v2 s_cselect_b32 s11, -1, 0 s_cmp_gt_i32 s9, 0 s_cselect_b32 s12, -1, 0 .LBB1_3: ; =>This Loop Header: Depth=1 ; Child Loop BB1_11 Depth 2 ; Child Loop BB1_7 Depth 2 ; Child Loop BB1_15 Depth 2 s_cmp_ge_i32 s13, s3 s_mov_b32 s14, -1 ; implicit-def: $vgpr9 s_cbranch_scc0 .LBB1_13 ; %bb.4: ; in Loop: Header=BB1_3 Depth=1 s_cmp_lg_u32 s13, s3 v_mov_b32_e32 v9, v8 s_cselect_b32 s14, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_or_b32 s14, s14, s10 s_and_b32 vcc_lo, exec_lo, s14 s_cbranch_vccnz .LBB1_12 ; %bb.5: ; in Loop: Header=BB1_3 Depth=1 s_mul_i32 s14, s13, 6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v13, s14, v3 v_add_nc_u32_e32 v9, s14, v4 v_mad_u64_u32 v[11:12], null, v13, s2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v10, 31, v9 v_lshlrev_b64 v[9:10], 2, v[9:10] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v12, 31, v11 s_waitcnt lgkmcnt(0) v_add_co_u32 v9, vcc_lo, s4, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[11:12], 2, v[11:12] v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo global_load_b32 v13, v[9:10], off v_add_co_u32 v9, vcc_lo, s6, v11 v_add_co_ci_u32_e32 v10, vcc_lo, s7, v12, vcc_lo s_and_not1_b32 vcc_lo, exec_lo, s11 global_load_b32 v9, v[9:10], off s_waitcnt vmcnt(1) v_mul_f32_e32 v10, s8, v13 ds_store_b32 v5, v10 s_waitcnt vmcnt(0) ds_store_b32 v7, v9 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_vccnz .LBB1_9 ; %bb.6: ; %.preheader96.preheader ; in Loop: Header=BB1_3 Depth=1 v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v9, v8 s_mov_b32 s14, 0 .LBB1_7: ; %.preheader96 ; Parent Loop BB1_3 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) v_add_nc_u32_e32 v11, s14, v6 s_add_i32 s14, s14, 4 ds_load_b32 v12, v10 ds_load_b32 v11, v11 v_add_nc_u32_e32 v10, 24, v10 s_cmp_eq_u32 s14, 24 s_waitcnt lgkmcnt(0) v_fmac_f32_e32 v9, v11, v12 s_cbranch_scc0 .LBB1_7 ; %bb.8: ; %Flow ; in Loop: Header=BB1_3 Depth=1 s_branch .LBB1_12 .LBB1_9: ; in Loop: Header=BB1_3 Depth=1 ; implicit-def: $vgpr9 s_cbranch_execz .LBB1_12 ; %bb.10: ; %.preheader ; in Loop: Header=BB1_3 Depth=1 v_dual_mov_b32 v9, v8 :: v_dual_mov_b32 v10, v2 v_mov_b32_e32 v11, v6 s_and_not1_b32 vcc_lo, exec_lo, s12 s_mov_b32 s14, s9 s_cbranch_vccnz .LBB1_12 .LBB1_11: ; %.lr.ph ; Parent Loop BB1_3 Depth=1 ; => This Inner Loop Header: Depth=2 ds_load_b32 v12, v11 ds_load_b32 v13, v10 v_add_nc_u32_e32 v11, 4, v11 v_add_nc_u32_e32 v10, 24, v10 s_add_i32 s14, s14, -1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s14, 0 s_waitcnt lgkmcnt(0) v_fmac_f32_e32 v9, v12, v13 s_cbranch_scc0 .LBB1_11 .LBB1_12: ; %Flow164 ; in Loop: Header=BB1_3 Depth=1 s_mov_b32 s14, 0 .LBB1_13: ; %Flow166 ; in Loop: Header=BB1_3 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s14 s_cbranch_vccnz .LBB1_17 ; %bb.14: ; in Loop: Header=BB1_3 Depth=1 s_mul_i32 s14, s13, 6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v13, s14, v3 v_add_nc_u32_e32 v9, s14, v4 s_mov_b32 s14, 0 v_mad_u64_u32 v[11:12], null, v13, s2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v10, 31, v9 v_lshlrev_b64 v[9:10], 2, v[9:10] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v12, 31, v11 s_waitcnt lgkmcnt(0) v_add_co_u32 v9, vcc_lo, s4, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[11:12], 2, v[11:12] v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo global_load_b32 v13, v[9:10], off v_add_co_u32 v9, vcc_lo, s6, v11 v_add_co_ci_u32_e32 v10, vcc_lo, s7, v12, vcc_lo global_load_b32 v10, v[9:10], off v_mov_b32_e32 v9, v2 s_waitcnt vmcnt(1) v_mul_f32_e32 v11, s8, v13 ds_store_b32 v5, v11 s_waitcnt vmcnt(0) ds_store_b32 v7, v10 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv .LBB1_15: ; Parent Loop BB1_3 Depth=1 ; => This Inner Loop Header: Depth=2 v_add_nc_u32_e32 v10, s14, v6 s_add_i32 s14, s14, 4 ds_load_b32 v11, v9 ds_load_b32 v10, v10 v_add_nc_u32_e32 v9, 24, v9 s_cmp_eq_u32 s14, 24 s_waitcnt lgkmcnt(0) v_fmac_f32_e32 v8, v10, v11 s_cbranch_scc0 .LBB1_15 ; %bb.16: ; %Flow165 ; in Loop: Header=BB1_3 Depth=1 s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v9, v8 .LBB1_17: ; %.loopexit ; in Loop: Header=BB1_3 Depth=1 s_add_i32 s14, s13, 1 s_cmp_eq_u32 s13, s3 s_cbranch_scc1 .LBB1_19 ; %bb.18: ; in Loop: Header=BB1_3 Depth=1 s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v8, v9 s_mov_b32 s13, s14 s_branch .LBB1_3 .LBB1_19: ; %Flow169 s_waitcnt lgkmcnt(0) s_load_b64 s[4:5], s[0:1], 0x10 v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2] s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b64 s[0:1], s[0:1], 0x20 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[2:3] v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b32 v2, v[2:3], off s_waitcnt vmcnt(0) v_fmac_f32_e32 v9, s2, v2 global_store_b32 v[0:1], v9, off .LBB1_20: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z4gemmPfS_S_ffS_i .amdhsa_group_segment_fixed_size 288 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 304 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 14 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z4gemmPfS_S_ffS_i, .Lfunc_end1-_Z4gemmPfS_S_ffS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 944 ; NumSgprs: 18 ; NumVgprs: 14 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 288 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 14 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z7maxpoolPfS_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z7maxpoolPfS_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: hidden_block_count_x - .offset: 52 .size: 4 .value_kind: hidden_block_count_y - .offset: 56 .size: 4 .value_kind: hidden_block_count_z - .offset: 60 .size: 2 .value_kind: hidden_group_size_x - .offset: 62 .size: 2 .value_kind: hidden_group_size_y - .offset: 64 .size: 2 .value_kind: hidden_group_size_z - .offset: 66 .size: 2 .value_kind: hidden_remainder_x - .offset: 68 .size: 2 .value_kind: hidden_remainder_y - .offset: 70 .size: 2 .value_kind: hidden_remainder_z - .offset: 88 .size: 8 .value_kind: hidden_global_offset_x - .offset: 96 .size: 8 .value_kind: hidden_global_offset_y - .offset: 104 .size: 8 .value_kind: hidden_global_offset_z - .offset: 112 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 288 .kernarg_segment_align: 8 .kernarg_segment_size: 304 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z4gemmPfS_S_ffS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z4gemmPfS_S_ffS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 14 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "1fea697b976a957608aafde96cf25b25108b198f.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z22__device_stub__maxpoolPfS_ii # -- Begin function _Z22__device_stub__maxpoolPfS_ii .p2align 4, 0x90 .type _Z22__device_stub__maxpoolPfS_ii,@function _Z22__device_stub__maxpoolPfS_ii: # @_Z22__device_stub__maxpoolPfS_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7maxpoolPfS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z22__device_stub__maxpoolPfS_ii, .Lfunc_end0-_Z22__device_stub__maxpoolPfS_ii .cfi_endproc # -- End function .globl _Z19__device_stub__gemmPfS_S_ffS_i # -- Begin function _Z19__device_stub__gemmPfS_S_ffS_i .p2align 4, 0x90 .type _Z19__device_stub__gemmPfS_S_ffS_i,@function _Z19__device_stub__gemmPfS_S_ffS_i: # @_Z19__device_stub__gemmPfS_S_ffS_i .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movss %xmm0, 12(%rsp) movss %xmm1, 8(%rsp) movq %rcx, 64(%rsp) movl %r8d, 4(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 8(%rsp), %rax movq %rax, 128(%rsp) leaq 64(%rsp), %rax movq %rax, 136(%rsp) leaq 4(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z4gemmPfS_S_ffS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end1: .size _Z19__device_stub__gemmPfS_S_ffS_i, .Lfunc_end1-_Z19__device_stub__gemmPfS_S_ffS_i .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset %rbp, -16 movq %rsp, %rbp .cfi_def_cfa_register %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $2376, %rsp # imm = 0x948 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 movq %rsi, %r15 cmpl $3, %edi jg .LBB2_3 # %bb.1: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str, %esi movl $8, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%r15), %rbx testq %rbx, %rbx je .LBB2_12 # %bb.2: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq strlen .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_13 .LBB2_3: movq 8(%r15), %rbx leaq -832(%rbp), %r13 movq %r13, -848(%rbp) testq %rbx, %rbx je .LBB2_202 # %bb.4: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq strlen movq %rax, %r14 cmpq $16, %rax jb .LBB2_9 # %bb.5: testq %r14, %r14 js .LBB2_222 # %bb.6: movq %r14, %rdi incq %rdi js .LBB2_194 # %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i .Ltmp0: .cfi_escape 0x2e, 0x00 callq _Znwm .Ltmp1: # %bb.8: # %.noexc195 movq %rax, -848(%rbp) movq %r14, -832(%rbp) .LBB2_9: testq %r14, %r14 je .LBB2_18 # %bb.10: movq -848(%rbp), %rdi cmpq $1, %r14 jne .LBB2_17 # %bb.11: movzbl (%rbx), %eax movb %al, (%rdi) jmp .LBB2_18 .LBB2_12: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi .cfi_escape 0x2e, 0x00 callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $35, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.2, %esi movl $10, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%r15), %rbx testq %rbx, %rbx je .LBB2_15 # %bb.14: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq strlen .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movq %rbx, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB2_16 .LBB2_15: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi .cfi_escape 0x2e, 0x00 callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB2_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit192 .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $15, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $1, %ebx jmp .LBB2_188 .LBB2_17: .cfi_escape 0x2e, 0x00 movq %rbx, %rsi movq %r14, %rdx callq memcpy@PLT .LBB2_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit movq %r14, -840(%rbp) movq -848(%rbp), %rax movb $0, (%rax,%r14) movq -848(%rbp), %rbx .cfi_escape 0x2e, 0x00 callq __errno_location movq %rax, %r14 movl (%rax), %r12d movl $0, (%rax) .cfi_escape 0x2e, 0x00 leaq -1368(%rbp), %rsi movq %rbx, %rdi movl $10, %edx callq __isoc23_strtol cmpq %rbx, -1368(%rbp) je .LBB2_204 # %bb.19: movslq %eax, %rcx movq %rax, -48(%rbp) # 8-byte Spill cmpq %rax, %rcx jne .LBB2_206 # %bb.20: movl (%r14), %eax cmpl $34, %eax je .LBB2_206 # %bb.21: testl %eax, %eax jne .LBB2_23 # %bb.22: movl %r12d, (%r14) .LBB2_23: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit movq -848(%rbp), %rdi cmpq %r13, %rdi je .LBB2_25 # %bb.24: # %.critedge.i.i196 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit movq 16(%r15), %rbx movq %r13, -848(%rbp) testq %rbx, %rbx je .LBB2_208 # %bb.26: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq strlen movq %rax, %r12 cmpq $16, %rax jb .LBB2_31 # %bb.27: testq %r12, %r12 js .LBB2_224 # %bb.28: movq %r12, %rdi incq %rdi js .LBB2_196 # %bb.29: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i197 .Ltmp2: .cfi_escape 0x2e, 0x00 callq _Znwm .Ltmp3: # %bb.30: # %.noexc203 movq %rax, -848(%rbp) movq %r12, -832(%rbp) .LBB2_31: testq %r12, %r12 je .LBB2_35 # %bb.32: movq -848(%rbp), %rdi cmpq $1, %r12 jne .LBB2_34 # %bb.33: movzbl (%rbx), %eax movb %al, (%rdi) jmp .LBB2_35 .LBB2_34: .cfi_escape 0x2e, 0x00 movq %rbx, %rsi movq %r12, %rdx callq memcpy@PLT .LBB2_35: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit204 movq %r12, -840(%rbp) movq -848(%rbp), %rax movb $0, (%rax,%r12) movq -848(%rbp), %rbx movl (%r14), %r12d movl $0, (%r14) .cfi_escape 0x2e, 0x00 leaq -1368(%rbp), %rsi movq %rbx, %rdi movl $10, %edx callq __isoc23_strtol cmpq %rbx, -1368(%rbp) je .LBB2_210 # %bb.36: movabsq $-4294967296, %rdx # imm = 0xFFFFFFFF00000000 movq %rax, %rcx movq %rax, -72(%rbp) # 8-byte Spill leaq -2147483648(%rax), %rcx cmpq %rdx, %rcx jb .LBB2_212 # %bb.37: movl (%r14), %eax cmpl $34, %eax je .LBB2_212 # %bb.38: testl %eax, %eax jne .LBB2_40 # %bb.39: movl %r12d, (%r14) .LBB2_40: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit210 movq -848(%rbp), %rdi cmpq %r13, %rdi je .LBB2_42 # %bb.41: # %.critedge.i.i211 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_42: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit213 movq 24(%r15), %rbx movq %r13, -848(%rbp) testq %rbx, %rbx je .LBB2_214 # %bb.43: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq strlen movq %rax, %r12 cmpq $16, %rax jb .LBB2_48 # %bb.44: testq %r12, %r12 js .LBB2_226 # %bb.45: movq %r12, %rdi incq %rdi js .LBB2_198 # %bb.46: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i214 .Ltmp4: .cfi_escape 0x2e, 0x00 callq _Znwm .Ltmp5: # %bb.47: # %.noexc220 movq %rax, -848(%rbp) movq %r12, -832(%rbp) .LBB2_48: testq %r12, %r12 je .LBB2_52 # %bb.49: movq -848(%rbp), %rdi cmpq $1, %r12 jne .LBB2_51 # %bb.50: movzbl (%rbx), %eax movb %al, (%rdi) jmp .LBB2_52 .LBB2_51: .cfi_escape 0x2e, 0x00 movq %rbx, %rsi movq %r12, %rdx callq memcpy@PLT .LBB2_52: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit221 movq %r12, -840(%rbp) movq -848(%rbp), %rax movb $0, (%rax,%r12) movq -848(%rbp), %rbx movl (%r14), %r12d movl $0, (%r14) .cfi_escape 0x2e, 0x00 leaq -1368(%rbp), %rsi movq %rbx, %rdi callq strtof movss %xmm0, -60(%rbp) # 4-byte Spill cmpq %rbx, -1368(%rbp) je .LBB2_216 # %bb.53: movl (%r14), %eax testl %eax, %eax je .LBB2_57 # %bb.54: cmpl $34, %eax jne .LBB2_58 # %bb.55: # %.critedge.i.i222 .Ltmp6: .cfi_escape 0x2e, 0x00 movl $.L.str.25, %edi callq _ZSt20__throw_out_of_rangePKc .Ltmp7: # %bb.56: .LBB2_57: movl %r12d, (%r14) .LBB2_58: # %_ZNSt7__cxx114stofERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPm.exit movq -848(%rbp), %rdi cmpq %r13, %rdi je .LBB2_60 # %bb.59: # %.critedge.i.i225 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_60: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit227 movq 32(%r15), %rbx movq %r13, -848(%rbp) testq %rbx, %rbx je .LBB2_218 # %bb.61: .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq strlen movq %rax, %r15 cmpq $16, %rax jb .LBB2_66 # %bb.62: testq %r15, %r15 js .LBB2_228 # %bb.63: movq %r15, %rdi incq %rdi js .LBB2_200 # %bb.64: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i228 .Ltmp8: .cfi_escape 0x2e, 0x00 callq _Znwm .Ltmp9: # %bb.65: # %.noexc234 movq %rax, -848(%rbp) movq %r15, -832(%rbp) .LBB2_66: testq %r15, %r15 je .LBB2_70 # %bb.67: movq -848(%rbp), %rdi cmpq $1, %r15 jne .LBB2_69 # %bb.68: movzbl (%rbx), %eax movb %al, (%rdi) jmp .LBB2_70 .LBB2_69: .cfi_escape 0x2e, 0x00 movq %rbx, %rsi movq %r15, %rdx callq memcpy@PLT .LBB2_70: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit235 movq %r15, -840(%rbp) movq -848(%rbp), %rax movb $0, (%rax,%r15) movq -848(%rbp), %rbx movl (%r14), %r15d movl $0, (%r14) .cfi_escape 0x2e, 0x00 leaq -1368(%rbp), %rsi movq %rbx, %rdi callq strtof movss %xmm0, -56(%rbp) # 4-byte Spill cmpq %rbx, -1368(%rbp) je .LBB2_220 # %bb.71: movl (%r14), %eax testl %eax, %eax je .LBB2_75 # %bb.72: cmpl $34, %eax jne .LBB2_76 # %bb.73: # %.critedge.i.i236 .Ltmp10: .cfi_escape 0x2e, 0x00 movl $.L.str.25, %edi callq _ZSt20__throw_out_of_rangePKc .Ltmp11: # %bb.74: .LBB2_75: movl %r15d, (%r14) .LBB2_76: # %_ZNSt7__cxx114stofERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPm.exit240 movq -848(%rbp), %rdi cmpq %r13, %rdi je .LBB2_78 # %bb.77: # %.critedge.i.i241 .cfi_escape 0x2e, 0x00 callq _ZdlPv .LBB2_78: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit243 movq %rsp, -328(%rbp) # 8-byte Spill movq -48(%rbp), %rcx # 8-byte Reload movl %ecx, %eax cltd idivl -72(%rbp) # 4-byte Folded Reload movl %eax, -52(%rbp) # 4-byte Spill movl %ecx, %ebx imull %ebx, %ebx .cfi_escape 0x2e, 0x00 movq %rsp, %r14 leaq 15(,%rbx,4), %rax andq $-16, %rax subq %rax, %r14 movq %r14, %rsp .cfi_escape 0x2e, 0x00 movq %rsp, %rcx subq %rax, %rcx movq %rcx, -96(%rbp) # 8-byte Spill movq %rcx, %rsp .cfi_escape 0x2e, 0x00 movq %rsp, %rcx subq %rax, %rcx movq %rcx, -88(%rbp) # 8-byte Spill movq %rcx, %rsp .cfi_escape 0x2e, 0x00 movq %rsp, %r15 subq %rax, %r15 movq %r15, %rsp .cfi_escape 0x2e, 0x00 leaq -848(%rbp), %rdi movl $.L.str.6, %esi movl $8, %edx callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode .Ltmp12: .cfi_escape 0x2e, 0x00 leaq -1368(%rbp), %rdi movl $.L.str.7, %esi movl $8, %edx callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode .Ltmp13: # %bb.79: .Ltmp15: .cfi_escape 0x2e, 0x00 leaq -2408(%rbp), %rdi movl $.L.str.8, %esi movl $8, %edx callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode .Ltmp16: # %bb.80: .Ltmp18: movq %r15, -80(%rbp) # 8-byte Spill movq %r14, -312(%rbp) # 8-byte Spill movq %rbx, -320(%rbp) # 8-byte Spill .cfi_escape 0x2e, 0x00 leaq -1888(%rbp), %rdi movl $.L.str.9, %esi movl $8, %edx callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode .Ltmp19: # %bb.81: # %.preheader cmpl $0, -48(%rbp) # 4-byte Folded Reload je .LBB2_88 # %bb.82: # %.lr.ph.preheader movq -320(%rbp), %r14 # 8-byte Reload cmpl $1, %r14d # kill: def $r14d killed $r14d killed $r14 def $r14 adcl $0, %r14d movq -312(%rbp), %rbx # 8-byte Reload movq -96(%rbp), %r12 # 8-byte Reload movq -88(%rbp), %r13 # 8-byte Reload movq -80(%rbp), %r15 # 8-byte Reload .p2align 4, 0x90 .LBB2_83: # %.lr.ph # =>This Inner Loop Header: Depth=1 .Ltmp21: .cfi_escape 0x2e, 0x00 leaq -848(%rbp), %rdi movq %rbx, %rsi callq _ZNSi10_M_extractIfEERSiRT_ .Ltmp22: # %bb.84: # %_ZNSirsERf.exit # in Loop: Header=BB2_83 Depth=1 .Ltmp23: .cfi_escape 0x2e, 0x00 leaq -1368(%rbp), %rdi movq %r12, %rsi callq _ZNSi10_M_extractIfEERSiRT_ .Ltmp24: # %bb.85: # %_ZNSirsERf.exit260 # in Loop: Header=BB2_83 Depth=1 .Ltmp25: .cfi_escape 0x2e, 0x00 leaq -2408(%rbp), %rdi movq %r13, %rsi callq _ZNSi10_M_extractIfEERSiRT_ .Ltmp26: # %bb.86: # %_ZNSirsERf.exit262 # in Loop: Header=BB2_83 Depth=1 .Ltmp27: .cfi_escape 0x2e, 0x00 leaq -1888(%rbp), %rdi movq %r15, %rsi callq _ZNSi10_M_extractIfEERSiRT_ .Ltmp28: # %bb.87: # %_ZNSirsERf.exit264 # in Loop: Header=BB2_83 Depth=1 addq $4, %r15 addq $4, %r13 addq $4, %r12 addq $4, %rbx decq %r14 jne .LBB2_83 .LBB2_88: # %._crit_edge .Ltmp30: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.10, %esi movl $14, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp31: movq -320(%rbp), %r13 # 8-byte Reload movq -312(%rbp), %r15 # 8-byte Reload movq -80(%rbp), %r12 # 8-byte Reload # %bb.89: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit257 .Ltmp32: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movq -72(%rbp), %rsi # 8-byte Reload # kill: def $esi killed $esi killed $rsi callq _ZNSolsEi .Ltmp33: # %bb.90: .Ltmp34: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.11, %esi movl $37, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp35: # %bb.91: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit266.preheader cmpl $0, -48(%rbp) # 4-byte Folded Reload je .LBB2_98 # %bb.92: # %.lr.ph370.preheader cmpl $1, %r13d movl %r13d, %r14d adcl $0, %r14d xorl %ebx, %ebx .p2align 4, 0x90 .LBB2_93: # %.lr.ph370 # =>This Inner Loop Header: Depth=1 movl %ebx, %eax cltd idivl -48(%rbp) # 4-byte Folded Reload testl %edx, %edx jne .LBB2_95 # %bb.94: # in Loop: Header=BB2_93 Depth=1 .Ltmp36: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.12, %esi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp37: .LBB2_95: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit270 # in Loop: Header=BB2_93 Depth=1 movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp38: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp39: # %bb.96: # %_ZNSolsEf.exit # in Loop: Header=BB2_93 Depth=1 .Ltmp40: .cfi_escape 0x2e, 0x00 movl $.L.str.13, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp41: # %bb.97: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit273 # in Loop: Header=BB2_93 Depth=1 incq %rbx cmpq %rbx, %r14 jne .LBB2_93 .LBB2_98: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit266._crit_edge .Ltmp43: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.14, %esi movl $9, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp44: # %bb.99: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit268 movss -60(%rbp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp45: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp46: # %bb.100: # %_ZNSolsEf.exit275 movb $10, -304(%rbp) movq (%rax), %rcx movq -24(%rcx), %rcx cmpq $0, 16(%rax,%rcx) je .LBB2_102 # %bb.101: .Ltmp47: .cfi_escape 0x2e, 0x00 leaq -304(%rbp), %rsi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp48: jmp .LBB2_103 .LBB2_102: .Ltmp49: .cfi_escape 0x2e, 0x00 movq %rax, %rdi movl $10, %esi callq _ZNSo3putEc .Ltmp50: .LBB2_103: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit .Ltmp51: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.15, %esi movl $24, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp52: # %bb.104: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit280.preheader cmpl $0, -48(%rbp) # 4-byte Folded Reload je .LBB2_111 # %bb.105: # %.lr.ph372.preheader cmpl $1, %r13d movl %r13d, %r14d adcl $0, %r14d xorl %ebx, %ebx .p2align 4, 0x90 .LBB2_106: # %.lr.ph372 # =>This Inner Loop Header: Depth=1 movl %ebx, %eax cltd idivl -48(%rbp) # 4-byte Folded Reload testl %edx, %edx jne .LBB2_108 # %bb.107: # in Loop: Header=BB2_106 Depth=1 .Ltmp53: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.12, %esi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp54: .LBB2_108: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit284 # in Loop: Header=BB2_106 Depth=1 movq -96(%rbp), %rax # 8-byte Reload movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp55: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp56: # %bb.109: # %_ZNSolsEf.exit286 # in Loop: Header=BB2_106 Depth=1 .Ltmp57: .cfi_escape 0x2e, 0x00 movl $.L.str.13, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp58: # %bb.110: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit288 # in Loop: Header=BB2_106 Depth=1 incq %rbx cmpq %rbx, %r14 jne .LBB2_106 .LBB2_111: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit280._crit_edge .Ltmp60: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.16, %esi movl $25, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp61: # %bb.112: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit282.preheader cmpl $0, -48(%rbp) # 4-byte Folded Reload je .LBB2_119 # %bb.113: # %.lr.ph374.preheader cmpl $1, %r13d movl %r13d, %r14d adcl $0, %r14d xorl %ebx, %ebx .p2align 4, 0x90 .LBB2_114: # %.lr.ph374 # =>This Inner Loop Header: Depth=1 movl %ebx, %eax cltd idivl -48(%rbp) # 4-byte Folded Reload testl %edx, %edx jne .LBB2_116 # %bb.115: # in Loop: Header=BB2_114 Depth=1 .Ltmp62: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.12, %esi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp63: .LBB2_116: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit292 # in Loop: Header=BB2_114 Depth=1 movq -88(%rbp), %rax # 8-byte Reload movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp64: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp65: # %bb.117: # %_ZNSolsEf.exit294 # in Loop: Header=BB2_114 Depth=1 .Ltmp66: .cfi_escape 0x2e, 0x00 movl $.L.str.13, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp67: # %bb.118: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit296 # in Loop: Header=BB2_114 Depth=1 incq %rbx cmpq %rbx, %r14 jne .LBB2_114 .LBB2_119: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit282._crit_edge .Ltmp69: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.17, %esi movl $8, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp70: # %bb.120: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit290 movss -56(%rbp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp71: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp72: # %bb.121: # %_ZNSolsEf.exit298 movb $10, -304(%rbp) movq (%rax), %rcx movq -24(%rcx), %rcx cmpq $0, 16(%rax,%rcx) je .LBB2_123 # %bb.122: .Ltmp73: .cfi_escape 0x2e, 0x00 leaq -304(%rbp), %rsi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp74: jmp .LBB2_124 .LBB2_123: .Ltmp75: .cfi_escape 0x2e, 0x00 movq %rax, %rdi movl $10, %esi callq _ZNSo3putEc .Ltmp76: .LBB2_124: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit303 .Ltmp77: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.18, %esi movl $24, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp78: # %bb.125: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit305.preheader cmpl $0, -48(%rbp) # 4-byte Folded Reload je .LBB2_132 # %bb.126: # %.lr.ph376.preheader cmpl $1, %r13d movl %r13d, %r14d adcl $0, %r14d xorl %ebx, %ebx .p2align 4, 0x90 .LBB2_127: # %.lr.ph376 # =>This Inner Loop Header: Depth=1 movl %ebx, %eax cltd idivl -48(%rbp) # 4-byte Folded Reload testl %edx, %edx jne .LBB2_129 # %bb.128: # in Loop: Header=BB2_127 Depth=1 .Ltmp79: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.12, %esi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp80: .LBB2_129: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit312 # in Loop: Header=BB2_127 Depth=1 movss (%r12,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp81: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp82: # %bb.130: # %_ZNSolsEf.exit314 # in Loop: Header=BB2_127 Depth=1 .Ltmp83: .cfi_escape 0x2e, 0x00 movl $.L.str.13, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp84: # %bb.131: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit316 # in Loop: Header=BB2_127 Depth=1 incq %rbx cmpq %rbx, %r14 jne .LBB2_127 .LBB2_132: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit305._crit_edge movb $10, -304(%rbp) movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax cmpq $0, _ZSt4cout+16(%rax) je .LBB2_134 # %bb.133: .Ltmp86: .cfi_escape 0x2e, 0x00 leaq -304(%rbp), %rsi movl $_ZSt4cout, %edi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp87: jmp .LBB2_135 .LBB2_134: .Ltmp88: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $10, %esi callq _ZNSo3putEc .Ltmp89: .LBB2_135: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit310 movslq -48(%rbp), %r12 # 4-byte Folded Reload imulq %r12, %r12 shlq $2, %r12 .Ltmp91: .cfi_escape 0x2e, 0x00 leaq -144(%rbp), %rdi movq %r12, %rsi callq hipMalloc .Ltmp92: # %bb.136: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit .Ltmp93: .cfi_escape 0x2e, 0x00 leaq -136(%rbp), %rdi movq %r12, %rsi callq hipMalloc .Ltmp94: # %bb.137: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit319 .Ltmp95: .cfi_escape 0x2e, 0x00 leaq -128(%rbp), %rdi movq %r12, %rsi callq hipMalloc .Ltmp96: # %bb.138: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit321 .Ltmp97: .cfi_escape 0x2e, 0x00 leaq -112(%rbp), %rdi movq %r12, %rsi callq hipMalloc .Ltmp98: # %bb.139: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit323 .Ltmp99: .cfi_escape 0x2e, 0x00 leaq -120(%rbp), %rdi movq %r12, %rsi callq hipMalloc .Ltmp100: # %bb.140: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit325 movslq -52(%rbp), %r14 # 4-byte Folded Reload imulq %r14, %r14 shlq $2, %r14 .Ltmp101: .cfi_escape 0x2e, 0x00 leaq -104(%rbp), %rdi movq %r14, %rsi callq hipMalloc .Ltmp102: # %bb.141: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit327 movq -144(%rbp), %rdi .Ltmp103: .cfi_escape 0x2e, 0x00 movq -96(%rbp), %rsi # 8-byte Reload movq %r12, %rdx movl $1, %ecx callq hipMemcpy .Ltmp104: # %bb.142: movq -136(%rbp), %rdi .Ltmp105: .cfi_escape 0x2e, 0x00 movq -88(%rbp), %rsi # 8-byte Reload movq %r12, %rdx movl $1, %ecx callq hipMemcpy .Ltmp106: # %bb.143: movq -128(%rbp), %rdi .Ltmp107: .cfi_escape 0x2e, 0x00 movq -80(%rbp), %rsi # 8-byte Reload movq %r12, %rdx movl $1, %ecx callq hipMemcpy .Ltmp108: # %bb.144: movq -120(%rbp), %rdi .Ltmp109: .cfi_escape 0x2e, 0x00 movq %r15, %rsi movq %r12, %rdx movl $1, %ecx callq hipMemcpy .Ltmp110: # %bb.145: .Ltmp111: movl $2863311531, %ebx # imm = 0xAAAAAAAB movl -48(%rbp), %eax # 4-byte Reload imulq %rbx, %rax shrq $34, %rax leaq 1(%rax), %rcx shlq $32, %rcx leaq (%rax,%rcx), %rdi incq %rdi .cfi_escape 0x2e, 0x00 movabsq $25769803782, %rdx # imm = 0x600000006 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration .Ltmp112: # %bb.146: testl %eax, %eax jne .LBB2_149 # %bb.147: movq -144(%rbp), %rax movq -136(%rbp), %rcx movq -128(%rbp), %rdx movq -112(%rbp), %rsi movq %rax, -224(%rbp) movq %rcx, -216(%rbp) movq %rdx, -176(%rbp) movss -60(%rbp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, -236(%rbp) movss -56(%rbp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, -232(%rbp) movq %rsi, -168(%rbp) movq -48(%rbp), %rax # 8-byte Reload movl %eax, -228(%rbp) leaq -224(%rbp), %rax movq %rax, -304(%rbp) leaq -216(%rbp), %rax movq %rax, -296(%rbp) leaq -176(%rbp), %rax movq %rax, -288(%rbp) leaq -236(%rbp), %rax movq %rax, -280(%rbp) leaq -232(%rbp), %rax movq %rax, -272(%rbp) leaq -168(%rbp), %rax movq %rax, -264(%rbp) leaq -228(%rbp), %rax movq %rax, -256(%rbp) .Ltmp113: .cfi_escape 0x2e, 0x00 leaq -208(%rbp), %rdi leaq -192(%rbp), %rsi leaq -160(%rbp), %rdx leaq -152(%rbp), %rcx callq __hipPopCallConfiguration .Ltmp114: # %bb.148: # %.noexc328 movq -208(%rbp), %rsi movl -200(%rbp), %edx movq -192(%rbp), %rcx movl -184(%rbp), %r8d .Ltmp115: .cfi_escape 0x2e, 0x10 leaq -304(%rbp), %r9 movl $_Z4gemmPfS_S_ffS_i, %edi pushq -152(%rbp) pushq -160(%rbp) callq hipLaunchKernel addq $16, %rsp .Ltmp116: .LBB2_149: .Ltmp117: .cfi_escape 0x2e, 0x00 callq hipDeviceSynchronize .Ltmp118: # %bb.150: .Ltmp120: .cfi_escape 0x2e, 0x00 callq hipGetLastError .Ltmp121: # %bb.151: testl %eax, %eax jne .LBB2_189 # %bb.152: .Ltmp124: movl -52(%rbp), %eax # 4-byte Reload imulq %rbx, %rax shrq $34, %rax leaq 1(%rax), %rcx shlq $32, %rcx leaq (%rax,%rcx), %rdi incq %rdi .cfi_escape 0x2e, 0x00 movabsq $25769803782, %rdx # imm = 0x600000006 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration .Ltmp125: # %bb.153: testl %eax, %eax jne .LBB2_156 # %bb.154: movq -120(%rbp), %rax movq -104(%rbp), %rcx movq %rax, -224(%rbp) movq %rcx, -216(%rbp) movq -48(%rbp), %rax # 8-byte Reload movl %eax, -160(%rbp) movq -72(%rbp), %rax # 8-byte Reload movl %eax, -152(%rbp) leaq -224(%rbp), %rax movq %rax, -304(%rbp) leaq -216(%rbp), %rax movq %rax, -296(%rbp) leaq -160(%rbp), %rax movq %rax, -288(%rbp) leaq -152(%rbp), %rax movq %rax, -280(%rbp) .Ltmp126: .cfi_escape 0x2e, 0x00 leaq -208(%rbp), %rdi leaq -192(%rbp), %rsi leaq -176(%rbp), %rdx leaq -168(%rbp), %rcx callq __hipPopCallConfiguration .Ltmp127: # %bb.155: # %.noexc336 movq -208(%rbp), %rsi movl -200(%rbp), %edx movq -192(%rbp), %rcx movl -184(%rbp), %r8d .Ltmp128: .cfi_escape 0x2e, 0x10 leaq -304(%rbp), %r9 movl $_Z7maxpoolPfS_ii, %edi pushq -168(%rbp) pushq -176(%rbp) callq hipLaunchKernel addq $16, %rsp .Ltmp129: .LBB2_156: .Ltmp130: .cfi_escape 0x2e, 0x00 callq hipDeviceSynchronize .Ltmp131: # %bb.157: .Ltmp132: .cfi_escape 0x2e, 0x00 callq hipGetLastError .Ltmp133: # %bb.158: testl %eax, %eax jne .LBB2_191 # %bb.159: .cfi_escape 0x2e, 0x00 movq %r12, %rdi callq malloc movq %r14, %rbx movq %rax, %r14 .cfi_escape 0x2e, 0x00 movq %rbx, %rdi callq malloc movq %rax, %r15 movq -112(%rbp), %rsi .Ltmp137: .cfi_escape 0x2e, 0x00 movq %r14, %rdi movq %r12, %rdx movl $2, %ecx callq hipMemcpy .Ltmp138: # %bb.160: movq -104(%rbp), %rsi .Ltmp139: .cfi_escape 0x2e, 0x00 movq %r15, %rdi movq %rbx, %rdx movl $2, %ecx callq hipMemcpy .Ltmp140: # %bb.161: .Ltmp141: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.20, %esi movl $35, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp142: # %bb.162: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit339.preheader cmpl $0, -48(%rbp) # 4-byte Folded Reload je .LBB2_169 # %bb.163: # %.lr.ph378.preheader cmpl $1, %r13d adcl $0, %r13d xorl %ebx, %ebx .p2align 4, 0x90 .LBB2_164: # %.lr.ph378 # =>This Inner Loop Header: Depth=1 movl %ebx, %eax cltd idivl -48(%rbp) # 4-byte Folded Reload testl %edx, %edx jne .LBB2_166 # %bb.165: # in Loop: Header=BB2_164 Depth=1 .Ltmp143: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.12, %esi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp144: .LBB2_166: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit343 # in Loop: Header=BB2_164 Depth=1 movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp145: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp146: # %bb.167: # %_ZNSolsEf.exit345 # in Loop: Header=BB2_164 Depth=1 .Ltmp147: .cfi_escape 0x2e, 0x00 movl $.L.str.13, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp148: # %bb.168: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit347 # in Loop: Header=BB2_164 Depth=1 incq %rbx cmpq %rbx, %r13 jne .LBB2_164 .LBB2_169: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit339._crit_edge .Ltmp150: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.21, %esi movl $38, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp151: # %bb.170: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit341.preheader cmpl $0, -52(%rbp) # 4-byte Folded Reload je .LBB2_177 # %bb.171: # %.lr.ph380.preheader movl -52(%rbp), %eax # 4-byte Reload movl %eax, %r12d imull %r12d, %r12d cmpl $1, %r12d adcl $0, %r12d xorl %ebx, %ebx .p2align 4, 0x90 .LBB2_172: # %.lr.ph380 # =>This Inner Loop Header: Depth=1 movl %ebx, %eax cltd idivl -52(%rbp) # 4-byte Folded Reload testl %edx, %edx jne .LBB2_174 # %bb.173: # in Loop: Header=BB2_172 Depth=1 .Ltmp152: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $.L.str.12, %esi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp153: .LBB2_174: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit354 # in Loop: Header=BB2_172 Depth=1 movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 .Ltmp154: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ .Ltmp155: # %bb.175: # %_ZNSolsEf.exit356 # in Loop: Header=BB2_172 Depth=1 .Ltmp156: .cfi_escape 0x2e, 0x00 movl $.L.str.13, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp157: # %bb.176: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit358 # in Loop: Header=BB2_172 Depth=1 incq %rbx cmpq %rbx, %r12 jne .LBB2_172 .LBB2_177: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit341._crit_edge movb $10, -304(%rbp) movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax cmpq $0, _ZSt4cout+16(%rax) je .LBB2_179 # %bb.178: .Ltmp159: .cfi_escape 0x2e, 0x00 leaq -304(%rbp), %rsi movl $_ZSt4cout, %edi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp160: jmp .LBB2_180 .LBB2_179: .Ltmp161: .cfi_escape 0x2e, 0x00 movl $_ZSt4cout, %edi movl $10, %esi callq _ZNSo3putEc .Ltmp162: .LBB2_180: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit352 movq -144(%rbp), %rdi .Ltmp163: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp164: # %bb.181: movq -136(%rbp), %rdi .Ltmp165: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp166: # %bb.182: movq -128(%rbp), %rdi .Ltmp167: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp168: # %bb.183: movq -112(%rbp), %rdi .Ltmp169: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp170: # %bb.184: movq -120(%rbp), %rdi .Ltmp171: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp172: # %bb.185: movq -104(%rbp), %rdi .Ltmp173: .cfi_escape 0x2e, 0x00 callq hipFree .Ltmp174: # %bb.186: .cfi_escape 0x2e, 0x00 movq %r14, %rdi callq free .cfi_escape 0x2e, 0x00 movq %r15, %rdi callq free xorl %ebx, %ebx .LBB2_187: .cfi_escape 0x2e, 0x00 leaq -1888(%rbp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq -1632(%rbp), %rdi .cfi_escape 0x2e, 0x00 callq _ZNSt8ios_baseD2Ev .cfi_escape 0x2e, 0x00 leaq -2408(%rbp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq -2152(%rbp), %rdi .cfi_escape 0x2e, 0x00 callq _ZNSt8ios_baseD2Ev .cfi_escape 0x2e, 0x00 leaq -1368(%rbp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq -1112(%rbp), %rdi .cfi_escape 0x2e, 0x00 callq _ZNSt8ios_baseD2Ev .cfi_escape 0x2e, 0x00 leaq -848(%rbp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq -592(%rbp), %rdi .cfi_escape 0x2e, 0x00 callq _ZNSt8ios_baseD2Ev movq -328(%rbp), %rsp # 8-byte Reload .LBB2_188: movl %ebx, %eax leaq -40(%rbp), %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 popq %rbp .cfi_def_cfa %rsp, 8 retq .LBB2_189: .cfi_def_cfa %rbp, 16 movq stderr(%rip), %rbx .Ltmp122: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp123: # %bb.190: .cfi_escape 0x2e, 0x00 jmp .LBB2_193 .LBB2_191: movq stderr(%rip), %rbx .Ltmp134: .cfi_escape 0x2e, 0x00 movl %eax, %edi callq hipGetErrorString .Ltmp135: # %bb.192: .cfi_escape 0x2e, 0x00 .LBB2_193: movl $.L.str.19, %esi movq %rbx, %rdi movq %rax, %rdx xorl %eax, %eax callq fprintf movl $1, %ebx jmp .LBB2_187 .LBB2_194: # %.noexc11.i .Ltmp213: .cfi_escape 0x2e, 0x00 callq _ZSt17__throw_bad_allocv .Ltmp214: # %bb.195: # %.noexc194 .LBB2_196: # %.noexc11.i198 .Ltmp201: .cfi_escape 0x2e, 0x00 callq _ZSt17__throw_bad_allocv .Ltmp202: # %bb.197: # %.noexc202 .LBB2_198: # %.noexc11.i215 .Ltmp189: .cfi_escape 0x2e, 0x00 callq _ZSt17__throw_bad_allocv .Ltmp190: # %bb.199: # %.noexc219 .LBB2_200: # %.noexc11.i229 .Ltmp179: .cfi_escape 0x2e, 0x00 callq _ZSt17__throw_bad_allocv .Ltmp180: # %bb.201: # %.noexc233 .LBB2_202: .Ltmp217: .cfi_escape 0x2e, 0x00 movl $.L.str.23, %edi callq _ZSt19__throw_logic_errorPKc .Ltmp218: # %bb.203: # %.noexc .LBB2_204: .Ltmp210: .cfi_escape 0x2e, 0x00 movl $.L.str.22, %edi callq _ZSt24__throw_invalid_argumentPKc .Ltmp211: # %bb.205: .LBB2_206: # %.critedge.i.i .Ltmp208: .cfi_escape 0x2e, 0x00 movl $.L.str.22, %edi callq _ZSt20__throw_out_of_rangePKc .Ltmp209: # %bb.207: .LBB2_208: .Ltmp205: .cfi_escape 0x2e, 0x00 movl $.L.str.23, %edi callq _ZSt19__throw_logic_errorPKc .Ltmp206: # %bb.209: # %.noexc200 .LBB2_210: .Ltmp198: .cfi_escape 0x2e, 0x00 movl $.L.str.22, %edi callq _ZSt24__throw_invalid_argumentPKc .Ltmp199: # %bb.211: .LBB2_212: # %.critedge.i.i206 .Ltmp196: .cfi_escape 0x2e, 0x00 movl $.L.str.22, %edi callq _ZSt20__throw_out_of_rangePKc .Ltmp197: # %bb.213: .LBB2_214: .Ltmp193: .cfi_escape 0x2e, 0x00 movl $.L.str.23, %edi callq _ZSt19__throw_logic_errorPKc .Ltmp194: # %bb.215: # %.noexc217 .LBB2_216: .Ltmp186: .cfi_escape 0x2e, 0x00 movl $.L.str.25, %edi callq _ZSt24__throw_invalid_argumentPKc .Ltmp187: # %bb.217: .LBB2_218: .Ltmp183: .cfi_escape 0x2e, 0x00 movl $.L.str.23, %edi callq _ZSt19__throw_logic_errorPKc .Ltmp184: # %bb.219: # %.noexc231 .LBB2_220: .Ltmp176: .cfi_escape 0x2e, 0x00 movl $.L.str.25, %edi callq _ZSt24__throw_invalid_argumentPKc .Ltmp177: # %bb.221: .LBB2_222: # %.noexc.i .Ltmp215: .cfi_escape 0x2e, 0x00 movl $.L.str.24, %edi callq _ZSt20__throw_length_errorPKc .Ltmp216: # %bb.223: # %.noexc193 .LBB2_224: # %.noexc.i199 .Ltmp203: .cfi_escape 0x2e, 0x00 movl $.L.str.24, %edi callq _ZSt20__throw_length_errorPKc .Ltmp204: # %bb.225: # %.noexc201 .LBB2_226: # %.noexc.i216 .Ltmp191: .cfi_escape 0x2e, 0x00 movl $.L.str.24, %edi callq _ZSt20__throw_length_errorPKc .Ltmp192: # %bb.227: # %.noexc218 .LBB2_228: # %.noexc.i230 .Ltmp181: .cfi_escape 0x2e, 0x00 movl $.L.str.24, %edi callq _ZSt20__throw_length_errorPKc .Ltmp182: # %bb.229: # %.noexc232 .LBB2_230: .Ltmp20: movq %rax, %rbx jmp .LBB2_262 .LBB2_231: .Ltmp17: movq %rax, %rbx jmp .LBB2_263 .LBB2_232: .Ltmp14: movq %rax, %rbx jmp .LBB2_264 .LBB2_233: .Ltmp178: movq %rax, %rbx cmpl $0, (%r14) jne .LBB2_235 # %bb.234: movl %r15d, (%r14) .LBB2_235: # %_ZZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i237 movq -848(%rbp), %rdi cmpq %r13, %rdi je .LBB2_265 # %bb.236: # %.critedge.i.i253 .cfi_escape 0x2e, 0x00 jmp .LBB2_249 .LBB2_237: .Ltmp188: movq %rax, %rbx cmpl $0, (%r14) jne .LBB2_239 # %bb.238: movl %r12d, (%r14) .LBB2_239: # %_ZZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i movq -848(%rbp), %rdi cmpq %r13, %rdi je .LBB2_265 # %bb.240: # %.critedge.i.i250 .cfi_escape 0x2e, 0x00 jmp .LBB2_249 .LBB2_241: .Ltmp200: movq %rax, %rbx cmpl $0, (%r14) jne .LBB2_243 # %bb.242: movl %r12d, (%r14) .LBB2_243: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i207 movq -848(%rbp), %rdi cmpq %r13, %rdi je .LBB2_265 # %bb.244: # %.critedge.i.i247 .cfi_escape 0x2e, 0x00 jmp .LBB2_249 .LBB2_245: .Ltmp212: movq %rax, %rbx cmpl $0, (%r14) jne .LBB2_247 # %bb.246: movl %r12d, (%r14) .LBB2_247: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i movq -848(%rbp), %rdi cmpq %r13, %rdi je .LBB2_265 # %bb.248: # %.critedge.i.i244 .cfi_escape 0x2e, 0x00 .LBB2_249: # %.critedge.i.i244 callq _ZdlPv movq %rbx, %rdi .cfi_escape 0x2e, 0x00 callq _Unwind_Resume@PLT .LBB2_250: .Ltmp136: jmp .LBB2_261 .LBB2_251: .Ltmp175: jmp .LBB2_261 .LBB2_252: .Ltmp119: jmp .LBB2_261 .LBB2_253: .Ltmp90: jmp .LBB2_261 .LBB2_254: .Ltmp158: jmp .LBB2_261 .LBB2_255: .Ltmp149: jmp .LBB2_261 .LBB2_256: .Ltmp85: jmp .LBB2_261 .LBB2_257: .Ltmp68: jmp .LBB2_261 .LBB2_258: .Ltmp59: jmp .LBB2_261 .LBB2_259: .Ltmp42: jmp .LBB2_261 .LBB2_260: .Ltmp29: .LBB2_261: movq %rax, %rbx .cfi_escape 0x2e, 0x00 leaq -1888(%rbp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq -1632(%rbp), %rdi .cfi_escape 0x2e, 0x00 callq _ZNSt8ios_baseD2Ev .LBB2_262: .cfi_escape 0x2e, 0x00 leaq -2408(%rbp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq -2152(%rbp), %rdi .cfi_escape 0x2e, 0x00 callq _ZNSt8ios_baseD2Ev .LBB2_263: .cfi_escape 0x2e, 0x00 leaq -1368(%rbp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq -1112(%rbp), %rdi .cfi_escape 0x2e, 0x00 callq _ZNSt8ios_baseD2Ev .LBB2_264: .cfi_escape 0x2e, 0x00 leaq -848(%rbp), %rdi movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev leaq -592(%rbp), %rdi .cfi_escape 0x2e, 0x00 callq _ZNSt8ios_baseD2Ev .LBB2_265: movq %rbx, %rdi .cfi_escape 0x2e, 0x00 callq _Unwind_Resume@PLT .LBB2_266: .Ltmp185: movq %rax, %rdi .cfi_escape 0x2e, 0x00 callq _Unwind_Resume@PLT .LBB2_267: .Ltmp195: movq %rax, %rdi .cfi_escape 0x2e, 0x00 callq _Unwind_Resume@PLT .LBB2_268: .Ltmp207: movq %rax, %rdi .cfi_escape 0x2e, 0x00 callq _Unwind_Resume@PLT .LBB2_269: .Ltmp219: movq %rax, %rdi .cfi_escape 0x2e, 0x00 callq _Unwind_Resume@PLT .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table2: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1 .uleb128 .Ltmp219-.Lfunc_begin0 # jumps to .Ltmp219 .byte 0 # On action: cleanup .uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp2-.Ltmp1 # Call between .Ltmp1 and .Ltmp2 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp3-.Ltmp2 # Call between .Ltmp2 and .Ltmp3 .uleb128 .Ltmp207-.Lfunc_begin0 # jumps to .Ltmp207 .byte 0 # On action: cleanup .uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 6 << .uleb128 .Ltmp5-.Ltmp4 # Call between .Ltmp4 and .Ltmp5 .uleb128 .Ltmp195-.Lfunc_begin0 # jumps to .Ltmp195 .byte 0 # On action: cleanup .uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 7 << .uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 8 << .uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7 .uleb128 .Ltmp188-.Lfunc_begin0 # jumps to .Ltmp188 .byte 0 # On action: cleanup .uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 9 << .uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9 .uleb128 .Ltmp185-.Lfunc_begin0 # jumps to .Ltmp185 .byte 0 # On action: cleanup .uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 10 << .uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 11 << .uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11 .uleb128 .Ltmp178-.Lfunc_begin0 # jumps to .Ltmp178 .byte 0 # On action: cleanup .uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 12 << .uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 13 << .uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13 .uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14 .byte 0 # On action: cleanup .uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 14 << .uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16 .uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17 .byte 0 # On action: cleanup .uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 15 << .uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19 .uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20 .byte 0 # On action: cleanup .uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 16 << .uleb128 .Ltmp28-.Ltmp21 # Call between .Ltmp21 and .Ltmp28 .uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29 .byte 0 # On action: cleanup .uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 17 << .uleb128 .Ltmp35-.Ltmp30 # Call between .Ltmp30 and .Ltmp35 .uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90 .byte 0 # On action: cleanup .uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 18 << .uleb128 .Ltmp41-.Ltmp36 # Call between .Ltmp36 and .Ltmp41 .uleb128 .Ltmp42-.Lfunc_begin0 # jumps to .Ltmp42 .byte 0 # On action: cleanup .uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 19 << .uleb128 .Ltmp52-.Ltmp43 # Call between .Ltmp43 and .Ltmp52 .uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90 .byte 0 # On action: cleanup .uleb128 .Ltmp53-.Lfunc_begin0 # >> Call Site 20 << .uleb128 .Ltmp58-.Ltmp53 # Call between .Ltmp53 and .Ltmp58 .uleb128 .Ltmp59-.Lfunc_begin0 # jumps to .Ltmp59 .byte 0 # On action: cleanup .uleb128 .Ltmp60-.Lfunc_begin0 # >> Call Site 21 << .uleb128 .Ltmp61-.Ltmp60 # Call between .Ltmp60 and .Ltmp61 .uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90 .byte 0 # On action: cleanup .uleb128 .Ltmp62-.Lfunc_begin0 # >> Call Site 22 << .uleb128 .Ltmp67-.Ltmp62 # Call between .Ltmp62 and .Ltmp67 .uleb128 .Ltmp68-.Lfunc_begin0 # jumps to .Ltmp68 .byte 0 # On action: cleanup .uleb128 .Ltmp69-.Lfunc_begin0 # >> Call Site 23 << .uleb128 .Ltmp78-.Ltmp69 # Call between .Ltmp69 and .Ltmp78 .uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90 .byte 0 # On action: cleanup .uleb128 .Ltmp79-.Lfunc_begin0 # >> Call Site 24 << .uleb128 .Ltmp84-.Ltmp79 # Call between .Ltmp79 and .Ltmp84 .uleb128 .Ltmp85-.Lfunc_begin0 # jumps to .Ltmp85 .byte 0 # On action: cleanup .uleb128 .Ltmp86-.Lfunc_begin0 # >> Call Site 25 << .uleb128 .Ltmp89-.Ltmp86 # Call between .Ltmp86 and .Ltmp89 .uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90 .byte 0 # On action: cleanup .uleb128 .Ltmp91-.Lfunc_begin0 # >> Call Site 26 << .uleb128 .Ltmp118-.Ltmp91 # Call between .Ltmp91 and .Ltmp118 .uleb128 .Ltmp119-.Lfunc_begin0 # jumps to .Ltmp119 .byte 0 # On action: cleanup .uleb128 .Ltmp120-.Lfunc_begin0 # >> Call Site 27 << .uleb128 .Ltmp133-.Ltmp120 # Call between .Ltmp120 and .Ltmp133 .uleb128 .Ltmp136-.Lfunc_begin0 # jumps to .Ltmp136 .byte 0 # On action: cleanup .uleb128 .Ltmp137-.Lfunc_begin0 # >> Call Site 28 << .uleb128 .Ltmp142-.Ltmp137 # Call between .Ltmp137 and .Ltmp142 .uleb128 .Ltmp175-.Lfunc_begin0 # jumps to .Ltmp175 .byte 0 # On action: cleanup .uleb128 .Ltmp143-.Lfunc_begin0 # >> Call Site 29 << .uleb128 .Ltmp148-.Ltmp143 # Call between .Ltmp143 and .Ltmp148 .uleb128 .Ltmp149-.Lfunc_begin0 # jumps to .Ltmp149 .byte 0 # On action: cleanup .uleb128 .Ltmp150-.Lfunc_begin0 # >> Call Site 30 << .uleb128 .Ltmp151-.Ltmp150 # Call between .Ltmp150 and .Ltmp151 .uleb128 .Ltmp175-.Lfunc_begin0 # jumps to .Ltmp175 .byte 0 # On action: cleanup .uleb128 .Ltmp152-.Lfunc_begin0 # >> Call Site 31 << .uleb128 .Ltmp157-.Ltmp152 # Call between .Ltmp152 and .Ltmp157 .uleb128 .Ltmp158-.Lfunc_begin0 # jumps to .Ltmp158 .byte 0 # On action: cleanup .uleb128 .Ltmp159-.Lfunc_begin0 # >> Call Site 32 << .uleb128 .Ltmp174-.Ltmp159 # Call between .Ltmp159 and .Ltmp174 .uleb128 .Ltmp175-.Lfunc_begin0 # jumps to .Ltmp175 .byte 0 # On action: cleanup .uleb128 .Ltmp122-.Lfunc_begin0 # >> Call Site 33 << .uleb128 .Ltmp135-.Ltmp122 # Call between .Ltmp122 and .Ltmp135 .uleb128 .Ltmp136-.Lfunc_begin0 # jumps to .Ltmp136 .byte 0 # On action: cleanup .uleb128 .Ltmp213-.Lfunc_begin0 # >> Call Site 34 << .uleb128 .Ltmp214-.Ltmp213 # Call between .Ltmp213 and .Ltmp214 .uleb128 .Ltmp219-.Lfunc_begin0 # jumps to .Ltmp219 .byte 0 # On action: cleanup .uleb128 .Ltmp201-.Lfunc_begin0 # >> Call Site 35 << .uleb128 .Ltmp202-.Ltmp201 # Call between .Ltmp201 and .Ltmp202 .uleb128 .Ltmp207-.Lfunc_begin0 # jumps to .Ltmp207 .byte 0 # On action: cleanup .uleb128 .Ltmp189-.Lfunc_begin0 # >> Call Site 36 << .uleb128 .Ltmp190-.Ltmp189 # Call between .Ltmp189 and .Ltmp190 .uleb128 .Ltmp195-.Lfunc_begin0 # jumps to .Ltmp195 .byte 0 # On action: cleanup .uleb128 .Ltmp179-.Lfunc_begin0 # >> Call Site 37 << .uleb128 .Ltmp180-.Ltmp179 # Call between .Ltmp179 and .Ltmp180 .uleb128 .Ltmp185-.Lfunc_begin0 # jumps to .Ltmp185 .byte 0 # On action: cleanup .uleb128 .Ltmp217-.Lfunc_begin0 # >> Call Site 38 << .uleb128 .Ltmp218-.Ltmp217 # Call between .Ltmp217 and .Ltmp218 .uleb128 .Ltmp219-.Lfunc_begin0 # jumps to .Ltmp219 .byte 0 # On action: cleanup .uleb128 .Ltmp210-.Lfunc_begin0 # >> Call Site 39 << .uleb128 .Ltmp209-.Ltmp210 # Call between .Ltmp210 and .Ltmp209 .uleb128 .Ltmp212-.Lfunc_begin0 # jumps to .Ltmp212 .byte 0 # On action: cleanup .uleb128 .Ltmp205-.Lfunc_begin0 # >> Call Site 40 << .uleb128 .Ltmp206-.Ltmp205 # Call between .Ltmp205 and .Ltmp206 .uleb128 .Ltmp207-.Lfunc_begin0 # jumps to .Ltmp207 .byte 0 # On action: cleanup .uleb128 .Ltmp198-.Lfunc_begin0 # >> Call Site 41 << .uleb128 .Ltmp197-.Ltmp198 # Call between .Ltmp198 and .Ltmp197 .uleb128 .Ltmp200-.Lfunc_begin0 # jumps to .Ltmp200 .byte 0 # On action: cleanup .uleb128 .Ltmp193-.Lfunc_begin0 # >> Call Site 42 << .uleb128 .Ltmp194-.Ltmp193 # Call between .Ltmp193 and .Ltmp194 .uleb128 .Ltmp195-.Lfunc_begin0 # jumps to .Ltmp195 .byte 0 # On action: cleanup .uleb128 .Ltmp186-.Lfunc_begin0 # >> Call Site 43 << .uleb128 .Ltmp187-.Ltmp186 # Call between .Ltmp186 and .Ltmp187 .uleb128 .Ltmp188-.Lfunc_begin0 # jumps to .Ltmp188 .byte 0 # On action: cleanup .uleb128 .Ltmp183-.Lfunc_begin0 # >> Call Site 44 << .uleb128 .Ltmp184-.Ltmp183 # Call between .Ltmp183 and .Ltmp184 .uleb128 .Ltmp185-.Lfunc_begin0 # jumps to .Ltmp185 .byte 0 # On action: cleanup .uleb128 .Ltmp176-.Lfunc_begin0 # >> Call Site 45 << .uleb128 .Ltmp177-.Ltmp176 # Call between .Ltmp176 and .Ltmp177 .uleb128 .Ltmp178-.Lfunc_begin0 # jumps to .Ltmp178 .byte 0 # On action: cleanup .uleb128 .Ltmp215-.Lfunc_begin0 # >> Call Site 46 << .uleb128 .Ltmp216-.Ltmp215 # Call between .Ltmp215 and .Ltmp216 .uleb128 .Ltmp219-.Lfunc_begin0 # jumps to .Ltmp219 .byte 0 # On action: cleanup .uleb128 .Ltmp203-.Lfunc_begin0 # >> Call Site 47 << .uleb128 .Ltmp204-.Ltmp203 # Call between .Ltmp203 and .Ltmp204 .uleb128 .Ltmp207-.Lfunc_begin0 # jumps to .Ltmp207 .byte 0 # On action: cleanup .uleb128 .Ltmp191-.Lfunc_begin0 # >> Call Site 48 << .uleb128 .Ltmp192-.Ltmp191 # Call between .Ltmp191 and .Ltmp192 .uleb128 .Ltmp195-.Lfunc_begin0 # jumps to .Ltmp195 .byte 0 # On action: cleanup .uleb128 .Ltmp181-.Lfunc_begin0 # >> Call Site 49 << .uleb128 .Ltmp182-.Ltmp181 # Call between .Ltmp181 and .Ltmp182 .uleb128 .Ltmp185-.Lfunc_begin0 # jumps to .Ltmp185 .byte 0 # On action: cleanup .uleb128 .Ltmp182-.Lfunc_begin0 # >> Call Site 50 << .uleb128 .Lfunc_end2-.Ltmp182 # Call between .Ltmp182 and .Lfunc_end2 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .p2align 2, 0x0 # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7maxpoolPfS_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z4gemmPfS_S_ffS_i, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z7maxpoolPfS_ii,@object # @_Z7maxpoolPfS_ii .section .rodata,"a",@progbits .globl _Z7maxpoolPfS_ii .p2align 3, 0x0 _Z7maxpoolPfS_ii: .quad _Z22__device_stub__maxpoolPfS_ii .size _Z7maxpoolPfS_ii, 8 .type _Z4gemmPfS_S_ffS_i,@object # @_Z4gemmPfS_S_ffS_i .globl _Z4gemmPfS_S_ffS_i .p2align 3, 0x0 _Z4gemmPfS_S_ffS_i: .quad _Z19__device_stub__gemmPfS_S_ffS_i .size _Z4gemmPfS_S_ffS_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "usage : " .size .L.str, 9 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " input_size filter_size alpha beta\n" .size .L.str.1, 36 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "example : " .size .L.str.2, 11 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz " 100 2 0.5 0.8\n" .size .L.str.3, 16 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "input.txt" .size .L.str.6, 10 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "a.txt" .size .L.str.7, 6 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "b.txt" .size .L.str.8, 6 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "c.txt" .size .L.str.9, 6 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "filter size : " .size .L.str.10, 15 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "\n========== MAXPOOL_INPUT ==========\n" .size .L.str.11, 38 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz "\n" .size .L.str.12, 2 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz " " .size .L.str.13, 2 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz "\nalpha : " .size .L.str.14, 10 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "========== A ==========\n" .size .L.str.15, 25 .type .L.str.16,@object # @.str.16 .L.str.16: .asciz "\n========== B ==========\n" .size .L.str.16, 26 .type .L.str.17,@object # @.str.17 .L.str.17: .asciz "\nbeta : " .size .L.str.17, 9 .type .L.str.18,@object # @.str.18 .L.str.18: .asciz "========== C ==========\n" .size .L.str.18, 25 .type .L.str.19,@object # @.str.19 .L.str.19: .asciz "ERROR %s\n" .size .L.str.19, 10 .type .L.str.20,@object # @.str.20 .L.str.20: .asciz "\n========== GEMM OUTPUT ==========\n" .size .L.str.20, 36 .type .L.str.21,@object # @.str.21 .L.str.21: .asciz "\n========== MAXPOOL OUTPUT ==========\n" .size .L.str.21, 39 .type .L.str.22,@object # @.str.22 .L.str.22: .asciz "stoi" .size .L.str.22, 5 .type .L.str.23,@object # @.str.23 .L.str.23: .asciz "basic_string: construction from null is not valid" .size .L.str.23, 50 .type .L.str.24,@object # @.str.24 .L.str.24: .asciz "basic_string::_M_create" .size .L.str.24, 24 .type .L.str.25,@object # @.str.25 .L.str.25: .asciz "stof" .size .L.str.25, 5 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z7maxpoolPfS_ii" .size .L__unnamed_1, 17 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z4gemmPfS_S_ffS_i" .size .L__unnamed_2, 19 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__maxpoolPfS_ii .addrsig_sym _Z19__device_stub__gemmPfS_S_ffS_i .addrsig_sym __gxx_personality_v0 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Unwind_Resume .addrsig_sym _Z7maxpoolPfS_ii .addrsig_sym _Z4gemmPfS_S_ffS_i .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
11,143
19,614
9,423
31,977
187
code for sm_80
.file "tmpxft_0008e036_00000000-6_a782c837ce5ceb12c3058894f7318c46af493c58.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "a782c837ce5ceb12c3058894f7318c46af493c58.hip" .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
8
771
301
228
188
code for sm_80 Function : _Z13createVoronoiP5PointiiPci .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; BAR.SYNC.DEFER_BLOCKING 0x0 ; IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x160] ; IMAD.MOV.U32 R25, RZ, RZ, c[0x0][0x164] ; ULDC.64 UR4, c[0x0][0x118] ; LDG.E R3, [R24.64] ; BSSY B0, 0x160 ; IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x160] ; MOV R4, 0x150 ; S2R R2, SR_CTAID.X ; IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x164] ; S2R R5, SR_TID.X ; S2R R0, SR_CTAID.Y ; IMAD R2, R2, 0x10, R5 ; S2R R5, SR_TID.Y ; I2F.F64 R6, R2 ; IMAD R0, R0, 0x10, R5 ; I2F.F64 R12, R3 ; DADD R12, R12, -R6 ; DADD R18, -RZ, |R12| ; CALL.REL.NOINC 0x1040 ; BSYNC B0 ; DADD R4, R12.reuse, 2 ; BSSY B0, 0x280 ; DSETP.NEU.AND P0, PT, R12, RZ, PT ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R4, 0x7ff00000, PT ; @!P0 CS2R R28, SRZ ; @P1 BRA 0x270 ; DSETP.GTU.AND P0, PT, |R12|, +INF , PT ; @P0 BRA 0x260 ; ISETP.NE.AND P0, PT, R12, RZ, PT ; LOP3.LUT R3, R13, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0x270 ; IMAD.MOV.U32 R28, RZ, RZ, 0x0 ; IMAD.MOV.U32 R29, RZ, RZ, 0x7ff00000 ; BRA 0x270 ; DADD R28, R12, 2 ; BSYNC B0 ; LDG.E R3, [R24.64+0x4] ; I2F.F64 R8, R0 ; DSETP.NEU.AND P0, PT, R12, 1, PT ; BSSY B0, 0x340 ; MOV R4, 0x330 ; FSEL R12, R28, RZ, P0 ; FSEL R13, R29, 1.875, P0 ; I2F.F64 R10, R3 ; DADD R10, R10, -R8 ; DADD R18, -RZ, |R10| ; CALL.REL.NOINC 0x1040 ; BSYNC B0 ; DADD R4, R10.reuse, 2 ; BSSY B0, 0x460 ; DSETP.NEU.AND P0, PT, R10, RZ, PT ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R4, 0x7ff00000, PT ; @!P0 CS2R R28, SRZ ; @P1 BRA 0x450 ; DSETP.GTU.AND P0, PT, |R10|, +INF , PT ; @P0 BRA 0x440 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; LOP3.LUT R3, R11, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0x450 ; IMAD.MOV.U32 R28, RZ, RZ, 0x0 ; IMAD.MOV.U32 R29, RZ, RZ, 0x7ff00000 ; BRA 0x450 ; DADD R28, R10, 2 ; BSYNC B0 ; LDG.E.U8 R3, [R24.64+0x8] ; DSETP.NEU.AND P0, PT, R10, 1, PT ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; FSEL R16, R28, RZ, P0 ; FSEL R17, R29, 1.875, P0 ; ISETP.GE.AND P0, PT, R4, 0x2, PT ; DADD R16, R12, R16 ; @!P0 BRA 0xd40 ; MUFU.RSQ64H R11, R17 ; IADD3 R10, R17, -0x3500000, RZ ; IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; BSSY B0, 0x6a0 ; IMAD.MOV.U32 R13, RZ, RZ, 0x3fd80000 ; ISETP.GE.U32.AND P0, PT, R10, 0x7ca00000, PT ; DMUL R4, R10, R10 ; DFMA R4, R16, -R4, 1 ; DFMA R12, R4, R12, 0.5 ; DMUL R4, R10, R4 ; DFMA R18, R12, R4, R10 ; DMUL R20, R16, R18 ; IADD3 R5, R19, -0x100000, RZ ; IMAD.MOV.U32 R4, RZ, RZ, R18 ; DFMA R22, R20, -R20, R16 ; DFMA R12, R22, R4, R20 ; @!P0 BRA 0x690 ; IMAD.MOV.U32 R4, RZ, RZ, R18 ; IMAD.MOV.U32 R18, RZ, RZ, R22 ; MOV R22, 0x670 ; IMAD.MOV.U32 R19, RZ, RZ, R23 ; IMAD.MOV.U32 R25, RZ, RZ, R17 ; IMAD.MOV.U32 R23, RZ, RZ, R10 ; IMAD.MOV.U32 R27, RZ, RZ, R5 ; CALL.REL.NOINC 0xda0 ; IMAD.MOV.U32 R12, RZ, RZ, R18 ; IMAD.MOV.U32 R13, RZ, RZ, R19 ; BSYNC B0 ; IMAD.MOV.U32 R10, RZ, RZ, R12 ; MOV R5, 0x1 ; IMAD.MOV.U32 R11, RZ, RZ, R13 ; IMAD.MOV.U32 R12, RZ, RZ, R14 ; IMAD.MOV.U32 R13, RZ, RZ, R15 ; LDG.E R4, [R12.64+0xc] ; IADD3 R5, R5, 0x1, RZ ; BSSY B0, 0x7d0 ; ISETP.GE.AND P1, PT, R5, c[0x0][0x178], PT ; I2F.F64 R24, R4 ; DADD R24, -R6, R24 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; @!P0 BRA 0x7b0 ; DADD R18, -RZ, |R24| ; MOV R4, 0x7a0 ; CALL.REL.NOINC 0x1040 ; BRA 0x7c0 ; CS2R R28, SRZ ; BSYNC B0 ; DADD R14, R24, 2 ; BSSY B0, 0x8d0 ; LOP3.LUT R14, R15, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R14, 0x7ff00000, PT ; @P0 BRA 0x8c0 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x8b0 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R4, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R4, 0x7ff00000, P0 ; @P0 BRA 0x8c0 ; IMAD.MOV.U32 R28, RZ, RZ, 0x0 ; IMAD.MOV.U32 R29, RZ, RZ, 0x7ff00000 ; BRA 0x8c0 ; DADD R28, R24, 2 ; BSYNC B0 ; LDG.E R4, [R12.64+0x10] ; DSETP.NEU.AND P0, PT, R24, 1, PT ; BSSY B0, 0x9c0 ; FSEL R24, R28, RZ, P0 ; FSEL R25, R29, 1.875, P0 ; I2F.F64 R14, R4 ; DADD R14, -R8, R14 ; DSETP.NEU.AND P2, PT, R14, RZ, PT ; @!P2 BRA 0x9a0 ; DADD R18, -RZ, |R14| ; MOV R4, 0x990 ; CALL.REL.NOINC 0x1040 ; BRA 0x9b0 ; CS2R R28, SRZ ; BSYNC B0 ; DADD R16, R14, 2 ; BSSY B0, 0xac0 ; LOP3.LUT R16, R17, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; @P0 BRA 0xab0 ; DSETP.GTU.AND P0, PT, |R14|, +INF , PT ; @P0 BRA 0xaa0 ; ISETP.NE.AND P0, PT, R14, RZ, PT ; LOP3.LUT R4, R15, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R4, 0x7ff00000, P0 ; @P0 BRA 0xab0 ; IMAD.MOV.U32 R28, RZ, RZ, 0x0 ; IMAD.MOV.U32 R29, RZ, RZ, 0x7ff00000 ; BRA 0xab0 ; DADD R28, R14, 2 ; BSYNC B0 ; DSETP.NEU.AND P0, PT, R14, 1, PT ; IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; BSSY B0, 0xca0 ; IMAD.MOV.U32 R19, RZ, RZ, 0x3fd80000 ; FSEL R14, R28, RZ, P0 ; FSEL R15, R29, 1.875, P0 ; DADD R24, R24, R14 ; MUFU.RSQ64H R15, R25 ; IADD3 R14, R25, -0x3500000, RZ ; ISETP.GE.U32.AND P0, PT, R14, 0x7ca00000, PT ; DMUL R16, R14, R14 ; DFMA R16, R24, -R16, 1 ; DFMA R18, R16, R18, 0.5 ; DMUL R16, R14, R16 ; DFMA R26, R18, R16, R14 ; DMUL R20, R24, R26 ; IADD3 R17, R27, -0x100000, RZ ; IMAD.MOV.U32 R16, RZ, RZ, R26 ; DFMA R18, R20, -R20, R24 ; DFMA R22, R18, R16, R20 ; @!P0 BRA 0xc90 ; IMAD.MOV.U32 R4, RZ, RZ, R26 ; MOV R22, 0xc70 ; IMAD.MOV.U32 R16, RZ, RZ, R24 ; IMAD.MOV.U32 R23, RZ, RZ, R14 ; IMAD.MOV.U32 R27, RZ, RZ, R17 ; CALL.REL.NOINC 0xda0 ; IMAD.MOV.U32 R22, RZ, RZ, R18 ; IMAD.MOV.U32 R23, RZ, RZ, R19 ; BSYNC B0 ; DSETP.GEU.AND P0, PT, R22, R10, PT ; BSSY B0, 0xd10 ; @P0 BRA 0xd00 ; LDG.E.U8 R3, [R12.64+0x14] ; IMAD.MOV.U32 R10, RZ, RZ, R22 ; IMAD.MOV.U32 R11, RZ, RZ, R23 ; BSYNC B0 ; IADD3 R14, P0, R12, 0xc, RZ ; IADD3.X R15, RZ, R13, RZ, P0, !PT ; @!P1 BRA 0x6d0 ; IMAD.SHL.U32 R5, R0, 0x10, RZ ; IMAD R5, R5, c[0x0][0x168], R2 ; IADD3 R4, P0, R5, c[0x0][0x170], RZ ; LEA.HI.X.SX32 R5, R5, c[0x0][0x174], 0x1, P0 ; STG.E.U8 [R4.64], R3 ; EXIT ; ISETP.GE.U32.AND P0, PT, R23, -0x3400000, PT ; BSSY B1, 0x1020 ; IMAD.MOV.U32 R17, RZ, RZ, R25 ; IMAD.MOV.U32 R24, RZ, RZ, R4 ; IMAD.MOV.U32 R25, RZ, RZ, R27 ; @!P0 BRA 0xe80 ; DFMA.RM R18, R18, R24, R20 ; IADD3 R20, P0, R18, 0x1, RZ ; IMAD.X R21, RZ, RZ, R19, P0 ; DFMA.RP R16, -R18, R20, R16 ; DSETP.GT.AND P0, PT, R16, RZ, PT ; FSEL R18, R20, R18, P0 ; FSEL R19, R21, R19, P0 ; BRA 0x1010 ; DSETP.NE.AND P0, PT, R16, RZ, PT ; @!P0 BRA 0x1000 ; ISETP.GE.AND P0, PT, R17, RZ, PT ; @!P0 IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; @!P0 IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; @!P0 BRA 0x1010 ; ISETP.GT.AND P0, PT, R17, 0x7fefffff, PT ; @P0 BRA 0x1000 ; DMUL R16, R16, 8.11296384146066816958e+31 ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; IMAD.MOV.U32 R24, RZ, RZ, 0x0 ; IMAD.MOV.U32 R25, RZ, RZ, 0x3fd80000 ; MUFU.RSQ64H R19, R17 ; DMUL R20, R18, R18 ; DFMA R20, R16, -R20, 1 ; DFMA R24, R20, R24, 0.5 ; DMUL R20, R18, R20 ; DFMA R20, R24, R20, R18 ; DMUL R18, R16, R20 ; IADD3 R21, R21, -0x100000, RZ ; DFMA R24, R18, -R18, R16 ; DFMA R18, R20, R24, R18 ; IADD3 R19, R19, -0x3500000, RZ ; BRA 0x1010 ; DADD R18, R16, R16 ; BSYNC B1 ; IMAD.MOV.U32 R23, RZ, RZ, 0x0 ; RET.REL.NODEC R22 0x0 ; SHF.R.U32.HI R22, RZ, 0x14, R19.reuse ; IMAD.MOV.U32 R16, RZ, RZ, R18 ; IMAD.MOV.U32 R17, RZ, RZ, R19 ; ISETP.NE.AND P0, PT, R22, RZ, PT ; @!P0 DMUL R16, R16, 1.80143985094819840000e+16 ; @!P0 IMAD.MOV.U32 R19, RZ, RZ, R17 ; @!P0 LEA.HI R22, R17, 0xffffffca, RZ, 0xc ; @!P0 IMAD.MOV.U32 R18, RZ, RZ, R16 ; LOP3.LUT R19, R19, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R28, RZ, RZ, R18 ; MOV R18, RZ ; LOP3.LUT R29, R19, 0x3ff00000, RZ, 0xfc, !PT ; ISETP.GE.U32.AND P2, PT, R29, 0x3ff6a09f, PT ; @P2 IADD3 R19, R29, -0x100000, RZ ; @P2 IMAD.MOV.U32 R29, RZ, RZ, R19 ; DADD R30, R28, 1 ; DADD R28, R28, -1 ; MUFU.RCP64H R19, R31 ; DFMA R26, -R30, R18, 1 ; DFMA R26, R26, R26, R26 ; DFMA R26, R18, R26, R18 ; IMAD.MOV.U32 R18, RZ, RZ, 0x7d2cafe2 ; IMAD.MOV.U32 R19, RZ, RZ, 0x3eb0f5ff ; DMUL R34, R26, R28 ; DFMA R34, R26, R28, R34 ; DMUL R20, R34, R34 ; DADD R32, R28, -R34 ; DFMA R18, R20, R18, c[0x2][0x0] ; DADD R32, R32, R32 ; DFMA R18, R20, R18, c[0x2][0x8] ; DFMA R32, R28, -R34, R32 ; DFMA R18, R20, R18, c[0x2][0x10] ; DMUL R32, R26, R32 ; DFMA R18, R20, R18, c[0x2][0x18] ; DMUL R26, R34, R34 ; DFMA R18, R20, R18, c[0x2][0x20] ; DFMA R18, R20, R18, c[0x2][0x28] ; DFMA R30, R20, R18, c[0x2][0x30] ; DADD R28, -R30, c[0x2][0x30] ; DFMA R28, R20, R18, R28 ; IADD3 R21, R33, 0x100000, RZ ; IMAD.MOV.U32 R20, RZ, RZ, R32 ; DFMA R18, R34, R34, -R26 ; DFMA R20, R34, R20, R18 ; DMUL R18, R34, R26 ; DFMA R16, R34, R26, -R18 ; DFMA R16, R32, R26, R16 ; DADD R26, RZ, R28 ; DFMA R16, R34, R20, R16 ; DADD R26, R26, c[0x2][0x38] ; DADD R20, R30, R26 ; DADD R30, R30, -R20 ; DMUL R28, R20, R18 ; DADD R30, R26, R30 ; DFMA R26, R20, R18, -R28 ; DFMA R16, R20, R16, R26 ; DFMA R30, R30, R18, R16 ; DADD R18, R28, R30 ; DADD R16, R34, R18 ; DADD R28, R28, -R18 ; DADD R34, R34, -R16 ; DADD R28, R30, R28 ; DADD R34, R18, R34 ; IADD3 R18, R22.reuse, -0x3ff, RZ ; IMAD.MOV.U32 R19, RZ, RZ, 0x43300000 ; @P2 IADD3 R18, R22, -0x3fe, RZ ; DADD R28, R28, R34 ; LOP3.LUT R18, R18, 0x80000000, RZ, 0x3c, !PT ; DADD R32, R32, R28 ; DADD R20, R18, c[0x2][0x40] ; DADD R22, R16, R32 ; DFMA R18, R20, c[0x2][0x48], R22 ; DADD R26, R16, -R22 ; DFMA R16, -R20, c[0x2][0x48], R18 ; DADD R26, R32, R26 ; DADD R16, -R22, R16 ; DADD R16, R26, -R16 ; IMAD.MOV.U32 R26, RZ, RZ, 0x69ce2bdf ; IMAD.MOV.U32 R27, RZ, RZ, 0x3e5ade15 ; DFMA R22, R20, c[0x2][0x50], R16 ; DADD R20, R18, R22 ; DADD R18, R18, -R20 ; DMUL R16, R20, 2 ; DADD R18, R22, R18 ; IMAD.MOV.U32 R22, RZ, RZ, 0x652b82fe ; DFMA R20, R20, 2, -R16 ; IMAD.MOV.U32 R23, RZ, RZ, 0x3ff71547 ; DFMA R18, R18, 2, R20 ; DADD R20, R16, R18 ; DFMA R22, R20, R22, 6.75539944105574400000e+15 ; FSETP.GEU.AND P0, PT, |R21|, 4.1917929649353027344, PT ; DADD R30, R22, -6.75539944105574400000e+15 ; DFMA R28, R30, c[0x2][0x58], R20 ; DFMA R28, R30, c[0x2][0x60], R28 ; DFMA R26, R28, R26, c[0x2][0x68] ; DFMA R26, R28, R26, c[0x2][0x70] ; DFMA R26, R28, R26, c[0x2][0x78] ; DFMA R26, R28, R26, c[0x2][0x80] ; DFMA R26, R28, R26, c[0x2][0x88] ; DFMA R26, R28, R26, c[0x2][0x90] ; DFMA R26, R28, R26, c[0x2][0x98] ; DFMA R26, R28, R26, c[0x2][0xa0] ; DFMA R26, R28, R26, c[0x2][0xa8] ; DFMA R26, R28, R26, 1 ; DFMA R26, R28, R26, 1 ; IMAD R29, R22, 0x100000, R27 ; IMAD.MOV.U32 R28, RZ, RZ, R26 ; @!P0 BRA 0x17c0 ; FSETP.GEU.AND P2, PT, |R21|, 4.2275390625, PT ; DADD R28, R20, +INF ; DSETP.GEU.AND P0, PT, R20, RZ, PT ; FSEL R28, R28, RZ, P0 ; @!P2 LEA.HI R23, R22, R22, RZ, 0x1 ; FSEL R29, R29, RZ, P0 ; @!P2 SHF.R.S32.HI R23, RZ, 0x1, R23 ; @!P2 IMAD R27, R23, 0x100000, R27 ; @!P2 IMAD.IADD R23, R22, 0x1, -R23 ; @!P2 IMAD.MOV.U32 R22, RZ, RZ, RZ ; @!P2 LEA R23, R23, 0x3ff00000, 0x14 ; @!P2 DMUL R28, R26, R22 ; LOP3.LUT R22, R29, 0x7fffffff, RZ, 0xc0, !PT ; DADD R16, R16, -R20 ; ISETP.NE.AND P0, PT, R22, 0x7ff00000, PT ; DADD R16, R18, R16 ; ISETP.EQ.AND P0, PT, R28, RZ, !P0 ; @!P0 DFMA R28, R16, R28, R28 ; IMAD.MOV.U32 R16, RZ, RZ, R4 ; IMAD.MOV.U32 R17, RZ, RZ, 0x0 ; RET.REL.NODEC R16 0x0 ; BRA 0x1850; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000d26c3_00000000-6_c34cf998bfff40d7bb89170bac3470b008fc5776.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2063: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2063: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z7getZoneP5Pointiii .type _Z7getZoneP5Pointiii, @function _Z7getZoneP5Pointiii: .LFB2059: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2059: .size _Z7getZoneP5Pointiii, .-_Z7getZoneP5Pointiii .globl _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci .type _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci, @function _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci: .LFB2085: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movl %esi, 20(%rsp) movl %edx, 16(%rsp) movq %rcx, 8(%rsp) movl %r8d, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 20(%rsp), %rax movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L9 .L5: movq 136(%rsp), %rax subq %fs:40, %rax jne .L10 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L9: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z13createVoronoiP5PointiiPci(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L5 .L10: call __stack_chk_fail@PLT .cfi_endproc .LFE2085: .size _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci, .-_Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci .globl _Z13createVoronoiP5PointiiPci .type _Z13createVoronoiP5PointiiPci, @function _Z13createVoronoiP5PointiiPci: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _Z13createVoronoiP5PointiiPci, .-_Z13createVoronoiP5PointiiPci .section .rodata.str1.1,"aMS",@progbits,1 .LC2: .string "CUDA malloc result array: %s\n" .LC3: .string "CUDA malloc Points: %s\n" .LC4: .string "Copy Points to GPU: %s\n" .LC5: .string "Run kernel: %s\n" .LC6: .string "Copy result from device: %s\n" .text .globl _Z15getVoronoiArrayPciiP5Pointi .type _Z15getVoronoiArrayPciiP5Pointi, @function _Z15getVoronoiArrayPciiP5Pointi: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $72, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, %ebp movl %edx, %ebx movq %rcx, %r15 movl %r8d, %r13d movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movl %edx, %eax imull %esi, %eax pxor %xmm0, %xmm0 cvtsi2sdl %eax, %xmm0 mulsd .LC0(%rip), %xmm0 comisd .LC1(%rip), %xmm0 jnb .L14 cvttsd2siq %xmm0, %r14 .L15: leaq 16(%rsp), %rdi movq %r14, %rsi call cudaMalloc@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movslq %r13d, %rax leaq (%rax,%rax,2), %r12 salq $2, %r12 leaq 24(%rsp), %rdi movq %r12, %rsi call cudaMalloc@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %ecx movq %r12, %rdx movq %r15, %rsi movq 24(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $16, 32(%rsp) movl $16, 36(%rsp) movl %ebx, 44(%rsp) movl %ebp, 48(%rsp) movl $0, %r9d movl $0, %r8d movq 32(%rsp), %rdx movl $1, %ecx movq 44(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L19 .L16: call cudaThreadSynchronize@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC5(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $2, %ecx movq %r14, %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L20 addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L14: .cfi_restore_state subsd .LC1(%rip), %xmm0 cvttsd2siq %xmm0, %r14 btcq $63, %r14 jmp .L15 .L19: movl %r13d, %r8d movq 16(%rsp), %rcx movl %ebp, %edx movl %ebx, %esi movq 24(%rsp), %rdi call _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci jmp .L16 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z15getVoronoiArrayPciiP5Pointi, .-_Z15getVoronoiArrayPciiP5Pointi .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC7: .string "Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char." .section .rodata.str1.1 .LC8: .string "Success\n\n" .LC9: .string "Height:%d, Width:%d\n\n" .LC10: .string "%c " .LC11: .string "\n" .text .globl main .type main, @function main: .LFB2060: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 cmpl $5, %edi jle .L35 movq %rsi, %rbx leal -3(%rdi), %ebp movslq %ebp, %rax imulq $1431655766, %rax, %rax shrq $32, %rax movl %ebp, %edx sarl $31, %edx subl %edx, %eax leal (%rax,%rax,2), %eax cmpl %eax, %ebp jne .L36 movq 8(%rsi), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %r13 movl %eax, %r14d movq 16(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, 16(%rsp) movl %eax, 4(%rsp) movl $3, %ecx movl %ebp, %eax cltd idivl %ecx movl %eax, %ebp movslq %eax, %r15 imulq $12, %r15, %rdi call malloc@PLT movq %rax, 8(%rsp) addq $24, %rbx movq %rax, %r12 imulq $24, %r15, %r15 addq %rbx, %r15 .L25: movq (%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl %eax, (%r12) movq 8(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl %eax, 4(%r12) movq 16(%rbx), %rax movzbl (%rax), %eax movb %al, 8(%r12) addq $24, %rbx addq $12, %r12 cmpq %r15, %rbx jne .L25 movl $16, %ecx movl 4(%rsp), %eax cltd idivl %ecx movl %eax, %ebx leal 1(%rax), %esi movl %esi, (%rsp) movl %r14d, %eax cltd idivl %ecx leal 1(%rax), %r12d movl %esi, %eax imull %r12d, %eax pxor %xmm0, %xmm0 cvtsi2sdl %eax, %xmm0 mulsd .LC0(%rip), %xmm0 comisd .LC1(%rip), %xmm0 jnb .L26 cvttsd2siq %xmm0, %rdi .L27: call malloc@PLT movq %rax, 24(%rsp) movl %ebp, %r8d movq 8(%rsp), %rcx movl (%rsp), %r15d movl %r15d, %edx movl %r12d, %esi movq %rax, %rbp movq %rax, %rdi call _Z15getVoronoiArrayPciiP5Pointi leaq .LC8(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl 4(%rsp), %ecx movl %r14d, %edx leaq .LC9(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl %r15d, %eax sall $4, %eax movl %eax, %ecx movl 16(%rsp), %edi subl %edi, %ecx testl %r13d, %r13d jle .L23 imull $-16, %r15d, %edi movl %edi, 4(%rsp) imull %r15d, %r13d movl %r13d, %r15d sall $4, %r15d leal 1(%rbx), %edx sall $4, %edx movslq %edx, %rsi movq %rsi, 32(%rsp) movslq %ebx, %rbx salq $4, %rbx subl $1, %edx subl %ecx, %edx subq %rbx, %rdx leaq -15(%rbp,%rdx), %rsi movq %rsi, 40(%rsp) movl %eax, 8(%rsp) movl %ecx, 16(%rsp) jmp .L28 .L35: leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L23 .L36: leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L23: movl $1, %eax addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L26: .cfi_restore_state subsd .LC1(%rip), %xmm0 cvttsd2siq %xmm0, %rdi btcq $63, %rdi jmp .L27 .L30: movslq %r15d, %rbx movq 32(%rsp), %rax subq %rax, %rbx movq 24(%rsp), %rax addq %rax, %rbx movslq %r13d, %rbp salq $4, %rbp movq 40(%rsp), %rax addq %rax, %rbp leaq .LC10(%rip), %r12 .L29: movsbl (%rbx), %edx movq %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $1, %rbx cmpq %rbp, %rbx jne .L29 .L31: leaq .LC11(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl 4(%rsp), %eax addl %eax, %r15d movl (%rsp), %eax subl %eax, %r13d subl $1, %r14d je .L23 .L28: movl 16(%rsp), %ecx cmpl %ecx, 8(%rsp) jg .L30 jmp .L31 .cfi_endproc .LFE2060: .size main, .-main .section .rodata.str1.1 .LC12: .string "_Z13createVoronoiP5PointiiPci" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2088: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _Z13createVoronoiP5PointiiPci(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2088: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC0: .long 0 .long 1081081856 .align 8 .LC1: .long 0 .long 1138753536 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13createVoronoiP5PointiiPci ; -- Begin function _Z13createVoronoiP5PointiiPci .globl _Z13createVoronoiP5PointiiPci .p2align 8 .type _Z13createVoronoiP5PointiiPci,@function _Z13createVoronoiP5PointiiPci: ; @_Z13createVoronoiP5PointiiPci ; %bb.0: s_clause 0x1 s_load_b64 s[40:41], s[0:1], 0x0 s_load_b32 s7, s[0:1], 0x18 v_dual_mov_b32 v10, 0 :: v_dual_and_b32 v1, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_bfe_u32 v0, v0, 10, 10 v_lshl_add_u32 v9, s14, 4, v1 s_delay_alu instid0(VALU_DEP_2) v_lshl_add_u32 v11, s15, 4, v0 global_load_u8 v8, v10, s[40:41] offset:8 s_cmp_lt_i32 s7, 2 s_cbranch_scc1 .LBB0_5 ; %bb.1: ; %.lr.ph.preheader.i s_load_b64 s[2:3], s[40:41], 0x0 v_cvt_f64_i32_e32 v[0:1], v9 v_cvt_f64_i32_e32 v[2:3], v11 s_mov_b32 s9, 0x3fe55555 s_mov_b32 s8, 0x55555555 s_mov_b32 s11, 0x3fba6564 s_mov_b32 s10, 0x968915a9 s_mov_b32 s13, 0x3fbdee67 s_mov_b32 s12, 0x4222de17 s_mov_b32 s15, 0x3fbe25e4 s_mov_b32 s14, 0x3abe935a s_mov_b32 s17, 0x3fc110ef s_mov_b32 s16, 0x47e6c9c2 s_mov_b32 s19, 0x3fc3b13b s_mov_b32 s18, 0xcfa74449 s_mov_b32 s21, 0x3fc745d1 s_mov_b32 s20, 0x71bf3c30 s_mov_b32 s23, 0x3fcc71c7 s_mov_b32 s22, 0x1c7792ce s_mov_b32 s25, 0x3fd24924 s_waitcnt lgkmcnt(0) v_cvt_f64_i32_e32 v[4:5], s2 v_cvt_f64_i32_e32 v[12:13], s3 s_mov_b32 s24, 0x924920da s_mov_b32 s27, 0x3fd99999 s_mov_b32 s26, 0x9999999c s_mov_b32 s29, 0xbfe55555 s_mov_b32 s28, s8 s_mov_b32 s31, 0x3c8543b0 s_mov_b32 s30, 0xd5df274d s_mov_b32 s35, 0x3fe62e42 s_mov_b32 s34, 0xfefa39ef s_mov_b32 s37, 0x3c7abc9e s_mov_b32 s36, 0x3b39803f s_mov_b32 s39, 0x3ff71547 s_mov_b32 s38, 0x652b82fe s_mov_b32 s43, 0xbfe62e42 s_mov_b32 s42, s34 s_mov_b32 s45, 0xbc7abc9e s_mov_b32 s44, s36 s_mov_b32 s47, 0x3e928af3 s_mov_b32 s46, 0xfca7ab0c s_mov_b32 s49, 0x3e5ade15 s_mov_b32 s48, 0x6a5dcb37 s_mov_b32 s51, 0x3ec71dee s_mov_b32 s50, 0x623fde64 s_mov_b32 s53, 0x3efa0199 s_mov_b32 s52, 0x7c89e6b0 s_mov_b32 s55, 0x3f2a01a0 s_mov_b32 s54, 0x14761f6e s_mov_b32 s57, 0x3f56c16c s_mov_b32 s56, 0x1852b7b0 s_mov_b32 s59, 0x3f811111 s_mov_b32 s58, 0x11122322 s_mov_b32 s61, 0x3fa55555 s_mov_b32 s60, 0x555502a1 s_mov_b32 s63, 0x3fc55555 s_mov_b32 s62, 0x55555511 s_mov_b32 s65, 0x3fe00000 v_add_f64 v[6:7], v[4:5], -v[0:1] v_add_f64 v[4:5], v[12:13], -v[2:3] s_mov_b32 s64, 11 s_add_i32 s7, s7, -1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_frexp_mant_f64_e64 v[12:13], |v[6:7]| v_frexp_mant_f64_e64 v[14:15], |v[4:5]| s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_f64_e32 vcc_lo, s[8:9], v[12:13] v_cmp_gt_f64_e64 s2, s[8:9], v[14:15] v_cndmask_b32_e64 v16, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v17, 0, 1, s2 v_ldexp_f64 v[12:13], v[12:13], v16 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ldexp_f64 v[14:15], v[14:15], v17 v_add_f64 v[16:17], v[12:13], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[18:19], v[14:15], 1.0 v_add_f64 v[28:29], v[12:13], -1.0 v_rcp_f64_e32 v[20:21], v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_rcp_f64_e32 v[22:23], v[18:19] v_add_f64 v[32:33], v[16:17], -1.0 v_add_f64 v[36:37], v[18:19], -1.0 v_add_f64 v[12:13], v[12:13], -v[32:33] s_waitcnt_depctr 0xfff v_fma_f64 v[24:25], -v[16:17], v[20:21], 1.0 v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[20:21], v[24:25], v[20:21], v[20:21] v_fma_f64 v[22:23], v[26:27], v[22:23], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[24:25], -v[16:17], v[20:21], 1.0 v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[20:21], v[24:25], v[20:21], v[20:21] v_add_f64 v[24:25], v[14:15], -1.0 v_fma_f64 v[22:23], v[26:27], v[22:23], v[22:23] v_add_f64 v[14:15], v[14:15], -v[36:37] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f64 v[26:27], v[28:29], v[20:21] v_mul_f64 v[30:31], v[24:25], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[34:35], v[16:17], v[26:27] v_mul_f64 v[38:39], v[18:19], v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[16:17], v[26:27], v[16:17], -v[34:35] v_fma_f64 v[18:19], v[30:31], v[18:19], -v[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[12:13], v[26:27], v[12:13], v[16:17] v_fma_f64 v[14:15], v[30:31], v[14:15], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[34:35], v[12:13] v_add_f64 v[18:19], v[38:39], v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[32:33], v[28:29], -v[16:17] v_add_f64 v[34:35], v[16:17], -v[34:35] v_add_f64 v[36:37], v[24:25], -v[18:19] v_add_f64 v[38:39], v[18:19], -v[38:39] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[28:29], v[28:29], -v[32:33] v_add_f64 v[12:13], v[34:35], -v[12:13] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[24:25], v[24:25], -v[36:37] v_add_f64 v[14:15], v[38:39], -v[14:15] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[16:17], v[28:29], -v[16:17] v_add_f64 v[18:19], v[24:25], -v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[12:13], v[12:13], v[16:17] v_add_f64 v[14:15], v[14:15], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[12:13], v[32:33], v[12:13] v_add_f64 v[14:15], v[36:37], v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[12:13], v[20:21], v[12:13] v_mul_f64 v[14:15], v[22:23], v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[26:27], v[12:13] v_add_f64 v[18:19], v[30:31], v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[20:21], v[16:17], -v[26:27] v_mul_f64 v[24:25], v[16:17], v[16:17] v_add_f64 v[22:23], v[18:19], -v[30:31] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[12:13], v[12:13], -v[20:21] v_mul_f64 v[20:21], v[18:19], v[18:19] v_add_f64 v[14:15], v[14:15], -v[22:23] v_fma_f64 v[22:23], v[16:17], v[16:17], -v[24:25] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[26:27], v[12:13], v[12:13] v_fma_f64 v[28:29], v[18:19], v[18:19], -v[20:21] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[30:31], v[14:15], v[14:15] v_fma_f64 v[22:23], v[16:17], v[26:27], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[18:19], v[30:31], v[28:29] v_add_f64 v[28:29], v[24:25], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[30:31], v[20:21], v[26:27] v_fma_f64 v[32:33], v[28:29], s[12:13], s[10:11] v_add_f64 v[24:25], v[28:29], -v[24:25] s_delay_alu instid0(VALU_DEP_3) v_fma_f64 v[34:35], v[30:31], s[12:13], s[10:11] v_add_f64 v[20:21], v[30:31], -v[20:21] v_mul_f64 v[42:43], v[16:17], v[28:29] v_mul_f64 v[46:47], v[18:19], v[30:31] v_fma_f64 v[32:33], v[28:29], v[32:33], s[14:15] v_add_f64 v[22:23], v[22:23], -v[24:25] v_fma_f64 v[34:35], v[30:31], v[34:35], s[14:15] v_add_f64 v[20:21], v[26:27], -v[20:21] v_fma_f64 v[48:49], v[28:29], v[16:17], -v[42:43] v_fma_f64 v[50:51], v[30:31], v[18:19], -v[46:47] v_fma_f64 v[32:33], v[28:29], v[32:33], s[16:17] v_fma_f64 v[34:35], v[30:31], v[34:35], s[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[32:33], v[28:29], v[32:33], s[18:19] v_fma_f64 v[34:35], v[30:31], v[34:35], s[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[32:33], v[28:29], v[32:33], s[20:21] v_fma_f64 v[34:35], v[30:31], v[34:35], s[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[32:33], v[28:29], v[32:33], s[22:23] v_fma_f64 v[34:35], v[30:31], v[34:35], s[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[32:33], v[28:29], v[32:33], s[24:25] v_fma_f64 v[34:35], v[30:31], v[34:35], s[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[32:33], v[28:29], v[32:33], s[26:27] v_fma_f64 v[34:35], v[30:31], v[34:35], s[26:27] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[36:37], v[28:29], v[32:33] v_mul_f64 v[38:39], v[30:31], v[34:35] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[24:25], v[28:29], v[32:33], -v[36:37] v_fma_f64 v[28:29], v[28:29], v[12:13], v[48:49] v_fma_f64 v[26:27], v[30:31], v[34:35], -v[38:39] v_fma_f64 v[30:31], v[30:31], v[14:15], v[50:51] v_ldexp_f64 v[12:13], v[12:13], 1 v_ldexp_f64 v[14:15], v[14:15], 1 v_fma_f64 v[24:25], v[22:23], v[32:33], v[24:25] v_fma_f64 v[22:23], v[22:23], v[16:17], v[28:29] v_fma_f64 v[26:27], v[20:21], v[34:35], v[26:27] v_fma_f64 v[20:21], v[20:21], v[18:19], v[30:31] v_ldexp_f64 v[16:17], v[16:17], 1 v_ldexp_f64 v[18:19], v[18:19], 1 v_add_f64 v[32:33], v[36:37], v[24:25] v_add_f64 v[30:31], v[42:43], v[22:23] v_add_f64 v[34:35], v[38:39], v[26:27] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[36:37], v[32:33], -v[36:37] v_add_f64 v[40:41], v[32:33], s[8:9] v_add_f64 v[38:39], v[34:35], -v[38:39] v_add_f64 v[44:45], v[34:35], s[8:9] v_add_f64 v[42:43], v[30:31], -v[42:43] v_add_f64 v[24:25], v[24:25], -v[36:37] v_add_f64 v[36:37], v[40:41], s[28:29] v_add_f64 v[26:27], v[26:27], -v[38:39] v_add_f64 v[38:39], v[44:45], s[28:29] v_add_f64 v[22:23], v[22:23], -v[42:43] v_add_f64 v[24:25], v[24:25], s[30:31] v_add_f64 v[32:33], v[32:33], -v[36:37] v_add_f64 v[26:27], v[26:27], s[30:31] v_add_f64 v[34:35], v[34:35], -v[38:39] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[24:25], v[24:25], v[32:33] v_add_f64 v[26:27], v[26:27], v[34:35] v_add_f64 v[34:35], v[46:47], v[20:21] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[28:29], v[40:41], v[24:25] v_add_f64 v[32:33], v[44:45], v[26:27] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[46:47], v[34:35], -v[46:47] v_add_f64 v[36:37], v[40:41], -v[28:29] v_mul_f64 v[38:39], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_4) v_add_f64 v[40:41], v[44:45], -v[32:33] v_mul_f64 v[44:45], v[34:35], v[32:33] v_add_f64 v[20:21], v[20:21], -v[46:47] v_add_f64 v[24:25], v[24:25], v[36:37] v_fma_f64 v[36:37], v[30:31], v[28:29], -v[38:39] v_add_f64 v[26:27], v[26:27], v[40:41] v_fma_f64 v[40:41], v[34:35], v[32:33], -v[44:45] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[24:25], v[30:31], v[24:25], v[36:37] v_fma_f64 v[26:27], v[34:35], v[26:27], v[40:41] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[22:23], v[22:23], v[28:29], v[24:25] v_frexp_exp_i32_f64_e32 v28, v[6:7] v_fma_f64 v[20:21], v[20:21], v[32:33], v[26:27] v_frexp_exp_i32_f64_e32 v29, v[4:5] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[24:25], v[38:39], v[22:23] v_subrev_co_ci_u32_e32 v28, vcc_lo, 0, v28, vcc_lo s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[26:27], v[44:45], v[20:21] v_subrev_co_ci_u32_e64 v30, vcc_lo, 0, v29, s2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_f64_i32_e32 v[28:29], v28 v_cvt_f64_i32_e32 v[30:31], v30 v_add_f64 v[32:33], v[24:25], -v[38:39] v_add_f64 v[34:35], v[16:17], v[24:25] v_add_f64 v[36:37], v[26:27], -v[44:45] v_add_f64 v[38:39], v[18:19], v[26:27] v_mul_f64 v[40:41], v[28:29], s[34:35] v_mul_f64 v[42:43], v[30:31], s[34:35] v_add_f64 v[22:23], v[22:23], -v[32:33] v_add_f64 v[16:17], v[34:35], -v[16:17] v_add_f64 v[20:21], v[20:21], -v[36:37] v_add_f64 v[18:19], v[38:39], -v[18:19] v_fma_f64 v[32:33], v[28:29], s[34:35], -v[40:41] v_add_f64 v[12:13], v[12:13], v[22:23] v_add_f64 v[16:17], v[24:25], -v[16:17] v_fma_f64 v[22:23], v[30:31], s[34:35], -v[42:43] v_add_f64 v[14:15], v[14:15], v[20:21] v_add_f64 v[18:19], v[26:27], -v[18:19] v_fma_f64 v[20:21], v[28:29], s[36:37], v[32:33] v_add_f64 v[12:13], v[12:13], v[16:17] v_fma_f64 v[16:17], v[30:31], s[36:37], v[22:23] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[14:15], v[14:15], v[18:19] v_add_f64 v[18:19], v[40:41], v[20:21] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[22:23], v[34:35], v[12:13] v_add_f64 v[24:25], v[42:43], v[16:17] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[26:27], v[38:39], v[14:15] v_add_f64 v[40:41], v[18:19], -v[40:41] s_delay_alu instid0(VALU_DEP_4) v_add_f64 v[28:29], v[18:19], v[22:23] v_add_f64 v[34:35], v[22:23], -v[34:35] v_add_f64 v[42:43], v[24:25], -v[42:43] v_add_f64 v[30:31], v[24:25], v[26:27] v_add_f64 v[38:39], v[26:27], -v[38:39] v_add_f64 v[20:21], v[20:21], -v[40:41] v_add_f64 v[32:33], v[28:29], -v[18:19] v_add_f64 v[12:13], v[12:13], -v[34:35] v_add_f64 v[16:17], v[16:17], -v[42:43] v_add_f64 v[36:37], v[30:31], -v[24:25] v_add_f64 v[14:15], v[14:15], -v[38:39] v_add_f64 v[44:45], v[28:29], -v[32:33] v_add_f64 v[22:23], v[22:23], -v[32:33] v_add_f64 v[32:33], v[20:21], v[12:13] v_add_f64 v[46:47], v[30:31], -v[36:37] v_add_f64 v[26:27], v[26:27], -v[36:37] v_add_f64 v[18:19], v[18:19], -v[44:45] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[24:25], v[24:25], -v[46:47] v_add_f64 v[18:19], v[22:23], v[18:19] v_add_f64 v[22:23], v[16:17], v[14:15] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[24:25], v[26:27], v[24:25] v_add_f64 v[26:27], v[32:33], -v[20:21] v_add_f64 v[18:19], v[32:33], v[18:19] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[34:35], v[22:23], -v[16:17] v_add_f64 v[24:25], v[22:23], v[24:25] s_delay_alu instid0(VALU_DEP_4) v_add_f64 v[32:33], v[32:33], -v[26:27] v_add_f64 v[12:13], v[12:13], -v[26:27] v_add_f64 v[36:37], v[28:29], v[18:19] v_add_f64 v[22:23], v[22:23], -v[34:35] v_add_f64 v[14:15], v[14:15], -v[34:35] v_add_f64 v[38:39], v[30:31], v[24:25] v_add_f64 v[20:21], v[20:21], -v[32:33] v_add_f64 v[26:27], v[36:37], -v[28:29] v_add_f64 v[16:17], v[16:17], -v[22:23] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[22:23], v[38:39], -v[30:31] v_add_f64 v[12:13], v[12:13], v[20:21] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[18:19], v[18:19], -v[26:27] v_add_f64 v[14:15], v[14:15], v[16:17] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[16:17], v[24:25], -v[22:23] v_add_f64 v[12:13], v[12:13], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[14:15], v[14:15], v[16:17] v_add_f64 v[16:17], v[36:37], v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[38:39], v[14:15] v_add_f64 v[20:21], v[16:17], -v[36:37] v_add_f64 v[22:23], v[16:17], v[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[24:25], v[18:19], -v[38:39] v_add_f64 v[26:27], v[18:19], v[18:19] v_add_f64 v[12:13], v[12:13], -v[20:21] s_delay_alu instid0(VALU_DEP_4) v_fma_f64 v[16:17], v[16:17], 2.0, -v[22:23] v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204 v_add_f64 v[14:15], v[14:15], -v[24:25] v_fma_f64 v[18:19], v[18:19], 2.0, -v[26:27] v_cmp_class_f64_e64 s2, v[26:27], 0x204 v_fma_f64 v[12:13], v[12:13], 2.0, v[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[14:15], v[14:15], 2.0, v[18:19] v_add_f64 v[16:17], v[22:23], v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[26:27], v[14:15] v_dual_cndmask_b32 v21, v17, v23 :: v_dual_cndmask_b32 v20, v16, v22 v_add_f64 v[16:17], v[16:17], -v[22:23] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v25, v19, v27, s2 v_cndmask_b32_e64 v24, v18, v26, s2 v_add_f64 v[18:19], v[18:19], -v[26:27] v_mul_f64 v[28:29], v[20:21], s[38:39] v_cmp_nlt_f64_e64 s3, 0x40900000, v[20:21] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[20:21]| v_mul_f64 v[30:31], v[24:25], s[38:39] v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[20:21] v_cmp_nlt_f64_e64 s5, 0x40900000, v[24:25] v_cmp_ngt_f64_e64 s6, 0xc090cc00, v[24:25] v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[24:25]| v_add_f64 v[12:13], v[12:13], -v[16:17] v_add_f64 v[14:15], v[14:15], -v[18:19] v_rndne_f64_e32 v[28:29], v[28:29] v_rndne_f64_e32 v[30:31], v[30:31] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_dual_cndmask_b32 v13, 0, v13 :: v_dual_cndmask_b32 v12, 0, v12 s_and_b32 vcc_lo, s4, s3 v_cndmask_b32_e64 v15, 0, v15, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_fma_f64 v[32:33], v[28:29], s[42:43], v[20:21] v_cvt_i32_f64_e32 v40, v[28:29] v_cndmask_b32_e64 v14, 0, v14, s2 v_fma_f64 v[34:35], v[30:31], s[42:43], v[24:25] v_fma_f64 v[32:33], v[28:29], s[44:45], v[32:33] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[34:35], v[30:31], s[44:45], v[34:35] v_fma_f64 v[36:37], v[32:33], s[48:49], s[46:47] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[38:39], v[34:35], s[48:49], s[46:47] v_fma_f64 v[36:37], v[32:33], v[36:37], s[50:51] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[38:39], v[34:35], v[38:39], s[50:51] v_fma_f64 v[36:37], v[32:33], v[36:37], s[52:53] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[38:39], v[34:35], v[38:39], s[52:53] v_fma_f64 v[36:37], v[32:33], v[36:37], s[54:55] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[38:39], v[34:35], v[38:39], s[54:55] v_fma_f64 v[36:37], v[32:33], v[36:37], s[56:57] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[38:39], v[34:35], v[38:39], s[56:57] v_fma_f64 v[36:37], v[32:33], v[36:37], s[58:59] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[38:39], v[34:35], v[38:39], s[58:59] v_fma_f64 v[36:37], v[32:33], v[36:37], s[60:61] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[38:39], v[34:35], v[38:39], s[60:61] v_fma_f64 v[36:37], v[32:33], v[36:37], s[62:63] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[38:39], v[34:35], v[38:39], s[62:63] v_fma_f64 v[36:37], v[32:33], v[36:37], s[64:65] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[38:39], v[34:35], v[38:39], s[64:65] v_fma_f64 v[36:37], v[32:33], v[36:37], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[38:39], v[34:35], v[38:39], 1.0 v_fma_f64 v[28:29], v[32:33], v[36:37], 1.0 v_cvt_i32_f64_e32 v32, v[30:31] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[30:31], v[34:35], v[38:39], 1.0 v_ldexp_f64 v[22:23], v[28:29], v40 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ldexp_f64 v[26:27], v[30:31], v32 v_cndmask_b32_e64 v16, 0x7ff00000, v23, s3 v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[6:7]| s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v18, 0x7ff00000, v27, s5 v_cndmask_b32_e64 v17, 0, v16, s4 v_cndmask_b32_e32 v16, 0, v22, vcc_lo s_and_b32 vcc_lo, s6, s5 s_delay_alu instid0(VALU_DEP_3) v_cndmask_b32_e64 v19, 0, v18, s6 v_cndmask_b32_e32 v18, 0, v26, vcc_lo v_cmp_neq_f64_e64 s5, 0x7ff00000, |v[4:5]| v_fma_f64 v[12:13], v[16:17], v[12:13], v[16:17] v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204 v_cmp_neq_f64_e64 s4, 0, v[6:7] v_cmp_neq_f64_e64 s6, 0, v[4:5] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v13, v13, v17 :: v_dual_cndmask_b32 v4, v12, v16 s_and_b32 vcc_lo, s4, s3 s_delay_alu instid0(VALU_DEP_1) v_and_b32_e32 v13, 0x7fffffff, v13 v_fma_f64 v[14:15], v[18:19], v[14:15], v[18:19] v_cmp_class_f64_e64 s2, v[18:19], 0x204 v_cndmask_b32_e32 v4, 0, v4, vcc_lo s_and_b32 vcc_lo, s6, s5 v_cndmask_b32_e64 v13, 0x7ff00000, v13, s3 s_add_u32 s40, s40, 12 s_addc_u32 s41, s41, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v5, 0, v13, s4 v_cndmask_b32_e64 v15, v15, v19, s2 v_cndmask_b32_e64 v12, v14, v18, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v15, 0x7fffffff, v15 v_cndmask_b32_e64 v6, 0x7ff00000, v15, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v7, 0, v6, s6 v_cndmask_b32_e32 v6, 0, v12, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[4:5], v[4:5], v[6:7] v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[4:5] v_cndmask_b32_e64 v6, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b32_e32 v6, 8, v6 v_ldexp_f64 v[4:5], v[4:5], v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_rsq_f64_e32 v[6:7], v[4:5] s_waitcnt_depctr 0xfff v_mul_f64 v[12:13], v[4:5], v[6:7] v_mul_f64 v[6:7], v[6:7], 0.5 v_fma_f64 v[14:15], -v[6:7], v[12:13], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7] v_fma_f64 v[14:15], -v[12:13], v[12:13], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], v[14:15], v[6:7], v[12:13] v_fma_f64 v[14:15], -v[12:13], v[12:13], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_fma_f64 v[6:7], v[14:15], v[6:7], v[12:13] v_cndmask_b32_e64 v12, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[4:5], 0x260 v_ldexp_f64 v[6:7], v[6:7], v12 s_delay_alu instid0(VALU_DEP_1) v_dual_cndmask_b32 v5, v7, v5 :: v_dual_cndmask_b32 v4, v6, v4 s_branch .LBB0_3 .LBB0_2: ; in Loop: Header=BB0_3 Depth=1 s_or_b32 exec_lo, exec_lo, s2 s_add_i32 s7, s7, -1 s_add_u32 s40, s40, 12 s_addc_u32 s41, s41, 0 s_cmp_lg_u32 s7, 0 s_cbranch_scc0 .LBB0_5 .LBB0_3: ; %.lr.ph.i ; =>This Inner Loop Header: Depth=1 s_load_b64 s[2:3], s[40:41], 0x0 s_waitcnt lgkmcnt(0) v_cvt_f64_i32_e32 v[6:7], s2 v_cvt_f64_i32_e32 v[12:13], s3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[6:7], v[6:7], -v[0:1] v_add_f64 v[12:13], v[12:13], -v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_frexp_mant_f64_e64 v[14:15], |v[6:7]| v_frexp_mant_f64_e64 v[16:17], |v[12:13]| s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_f64_e32 vcc_lo, s[8:9], v[14:15] v_cmp_gt_f64_e64 s2, s[8:9], v[16:17] v_cndmask_b32_e64 v18, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v19, 0, 1, s2 v_ldexp_f64 v[14:15], v[14:15], v18 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ldexp_f64 v[16:17], v[16:17], v19 v_add_f64 v[18:19], v[14:15], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[20:21], v[16:17], 1.0 v_add_f64 v[30:31], v[14:15], -1.0 v_rcp_f64_e32 v[22:23], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_rcp_f64_e32 v[24:25], v[20:21] v_add_f64 v[34:35], v[18:19], -1.0 v_add_f64 v[38:39], v[20:21], -1.0 v_add_f64 v[14:15], v[14:15], -v[34:35] s_waitcnt_depctr 0xfff v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0 v_fma_f64 v[28:29], -v[20:21], v[24:25], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[22:23], v[26:27], v[22:23], v[22:23] v_fma_f64 v[24:25], v[28:29], v[24:25], v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0 v_fma_f64 v[28:29], -v[20:21], v[24:25], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[22:23], v[26:27], v[22:23], v[22:23] v_add_f64 v[26:27], v[16:17], -1.0 v_fma_f64 v[24:25], v[28:29], v[24:25], v[24:25] v_add_f64 v[16:17], v[16:17], -v[38:39] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f64 v[28:29], v[30:31], v[22:23] v_mul_f64 v[32:33], v[26:27], v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[36:37], v[18:19], v[28:29] v_mul_f64 v[40:41], v[20:21], v[32:33] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[18:19], v[28:29], v[18:19], -v[36:37] v_fma_f64 v[20:21], v[32:33], v[20:21], -v[40:41] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[14:15], v[28:29], v[14:15], v[18:19] v_fma_f64 v[16:17], v[32:33], v[16:17], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[36:37], v[14:15] v_add_f64 v[20:21], v[40:41], v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[34:35], v[30:31], -v[18:19] v_add_f64 v[36:37], v[18:19], -v[36:37] v_add_f64 v[38:39], v[26:27], -v[20:21] v_add_f64 v[40:41], v[20:21], -v[40:41] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[30:31], v[30:31], -v[34:35] v_add_f64 v[14:15], v[36:37], -v[14:15] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[26:27], v[26:27], -v[38:39] v_add_f64 v[16:17], v[40:41], -v[16:17] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[18:19], v[30:31], -v[18:19] v_add_f64 v[20:21], v[26:27], -v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[14:15], v[14:15], v[18:19] v_add_f64 v[16:17], v[16:17], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[14:15], v[34:35], v[14:15] v_add_f64 v[16:17], v[38:39], v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[14:15], v[22:23], v[14:15] v_mul_f64 v[16:17], v[24:25], v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[28:29], v[14:15] v_add_f64 v[20:21], v[32:33], v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[22:23], v[18:19], -v[28:29] v_mul_f64 v[26:27], v[18:19], v[18:19] v_add_f64 v[24:25], v[20:21], -v[32:33] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[14:15], v[14:15], -v[22:23] v_mul_f64 v[22:23], v[20:21], v[20:21] v_add_f64 v[16:17], v[16:17], -v[24:25] v_fma_f64 v[24:25], v[18:19], v[18:19], -v[26:27] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[28:29], v[14:15], v[14:15] v_fma_f64 v[30:31], v[20:21], v[20:21], -v[22:23] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[32:33], v[16:17], v[16:17] v_fma_f64 v[24:25], v[18:19], v[28:29], v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[28:29], v[20:21], v[32:33], v[30:31] v_add_f64 v[30:31], v[26:27], v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[32:33], v[22:23], v[28:29] v_fma_f64 v[34:35], v[30:31], s[12:13], s[10:11] v_add_f64 v[26:27], v[30:31], -v[26:27] s_delay_alu instid0(VALU_DEP_3) v_fma_f64 v[36:37], v[32:33], s[12:13], s[10:11] v_add_f64 v[22:23], v[32:33], -v[22:23] v_mul_f64 v[44:45], v[18:19], v[30:31] v_mul_f64 v[48:49], v[20:21], v[32:33] v_fma_f64 v[34:35], v[30:31], v[34:35], s[14:15] v_add_f64 v[24:25], v[24:25], -v[26:27] v_fma_f64 v[36:37], v[32:33], v[36:37], s[14:15] v_add_f64 v[22:23], v[28:29], -v[22:23] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[34:35], v[30:31], v[34:35], s[16:17] v_fma_f64 v[36:37], v[32:33], v[36:37], s[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[34:35], v[30:31], v[34:35], s[18:19] v_fma_f64 v[36:37], v[32:33], v[36:37], s[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[34:35], v[30:31], v[34:35], s[20:21] v_fma_f64 v[36:37], v[32:33], v[36:37], s[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[34:35], v[30:31], v[34:35], s[22:23] v_fma_f64 v[36:37], v[32:33], v[36:37], s[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[34:35], v[30:31], v[34:35], s[24:25] v_fma_f64 v[36:37], v[32:33], v[36:37], s[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[34:35], v[30:31], v[34:35], s[26:27] v_fma_f64 v[36:37], v[32:33], v[36:37], s[26:27] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[38:39], v[30:31], v[34:35] v_mul_f64 v[40:41], v[32:33], v[36:37] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[30:31], v[34:35], -v[38:39] v_fma_f64 v[28:29], v[32:33], v[36:37], -v[40:41] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[24:25], v[34:35], v[26:27] v_fma_f64 v[28:29], v[22:23], v[36:37], v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[34:35], v[38:39], v[26:27] v_add_f64 v[36:37], v[40:41], v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[42:43], v[34:35], s[8:9] v_add_f64 v[38:39], v[34:35], -v[38:39] v_add_f64 v[46:47], v[36:37], s[8:9] v_add_f64 v[40:41], v[36:37], -v[40:41] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[50:51], v[42:43], s[28:29] v_add_f64 v[26:27], v[26:27], -v[38:39] v_fma_f64 v[38:39], v[30:31], v[18:19], -v[44:45] v_add_f64 v[52:53], v[46:47], s[28:29] v_add_f64 v[28:29], v[28:29], -v[40:41] v_fma_f64 v[40:41], v[32:33], v[20:21], -v[48:49] v_add_f64 v[34:35], v[34:35], -v[50:51] v_add_f64 v[26:27], v[26:27], s[30:31] v_fma_f64 v[30:31], v[30:31], v[14:15], v[38:39] v_add_f64 v[36:37], v[36:37], -v[52:53] v_add_f64 v[28:29], v[28:29], s[30:31] v_fma_f64 v[32:33], v[32:33], v[16:17], v[40:41] v_ldexp_f64 v[14:15], v[14:15], 1 v_ldexp_f64 v[16:17], v[16:17], 1 v_add_f64 v[26:27], v[26:27], v[34:35] v_fma_f64 v[24:25], v[24:25], v[18:19], v[30:31] v_ldexp_f64 v[18:19], v[18:19], 1 v_add_f64 v[28:29], v[28:29], v[36:37] v_fma_f64 v[22:23], v[22:23], v[20:21], v[32:33] v_ldexp_f64 v[20:21], v[20:21], 1 v_add_f64 v[30:31], v[42:43], v[26:27] v_add_f64 v[32:33], v[44:45], v[24:25] v_add_f64 v[34:35], v[46:47], v[28:29] v_add_f64 v[36:37], v[48:49], v[22:23] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[38:39], v[42:43], -v[30:31] v_mul_f64 v[40:41], v[32:33], v[30:31] v_add_f64 v[44:45], v[32:33], -v[44:45] v_add_f64 v[42:43], v[46:47], -v[34:35] v_mul_f64 v[46:47], v[36:37], v[34:35] v_add_f64 v[48:49], v[36:37], -v[48:49] v_add_f64 v[26:27], v[26:27], v[38:39] v_fma_f64 v[38:39], v[32:33], v[30:31], -v[40:41] v_add_f64 v[24:25], v[24:25], -v[44:45] v_add_f64 v[28:29], v[28:29], v[42:43] v_fma_f64 v[42:43], v[36:37], v[34:35], -v[46:47] v_add_f64 v[22:23], v[22:23], -v[48:49] v_fma_f64 v[26:27], v[32:33], v[26:27], v[38:39] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[28:29], v[36:37], v[28:29], v[42:43] v_fma_f64 v[24:25], v[24:25], v[30:31], v[26:27] v_frexp_exp_i32_f64_e32 v30, v[6:7] v_frexp_exp_i32_f64_e32 v31, v[12:13] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[22:23], v[22:23], v[34:35], v[28:29] v_add_f64 v[26:27], v[40:41], v[24:25] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_subrev_co_ci_u32_e32 v30, vcc_lo, 0, v30, vcc_lo v_add_f64 v[28:29], v[46:47], v[22:23] v_subrev_co_ci_u32_e64 v32, vcc_lo, 0, v31, s2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_f64_i32_e32 v[30:31], v30 v_cvt_f64_i32_e32 v[32:33], v32 v_add_f64 v[34:35], v[18:19], v[26:27] v_add_f64 v[36:37], v[26:27], -v[40:41] v_add_f64 v[38:39], v[20:21], v[28:29] v_add_f64 v[40:41], v[28:29], -v[46:47] v_mul_f64 v[42:43], v[30:31], s[34:35] v_mul_f64 v[44:45], v[32:33], s[34:35] v_add_f64 v[18:19], v[34:35], -v[18:19] v_add_f64 v[24:25], v[24:25], -v[36:37] v_add_f64 v[20:21], v[38:39], -v[20:21] v_add_f64 v[22:23], v[22:23], -v[40:41] v_fma_f64 v[36:37], v[30:31], s[34:35], -v[42:43] v_add_f64 v[18:19], v[26:27], -v[18:19] v_add_f64 v[14:15], v[14:15], v[24:25] v_fma_f64 v[24:25], v[32:33], s[34:35], -v[44:45] v_add_f64 v[20:21], v[28:29], -v[20:21] v_add_f64 v[16:17], v[16:17], v[22:23] v_fma_f64 v[22:23], v[30:31], s[36:37], v[36:37] v_add_f64 v[14:15], v[14:15], v[18:19] v_fma_f64 v[18:19], v[32:33], s[36:37], v[24:25] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[16:17], v[16:17], v[20:21] v_add_f64 v[20:21], v[42:43], v[22:23] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[24:25], v[34:35], v[14:15] v_add_f64 v[26:27], v[44:45], v[18:19] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[28:29], v[38:39], v[16:17] v_add_f64 v[42:43], v[20:21], -v[42:43] s_delay_alu instid0(VALU_DEP_4) v_add_f64 v[30:31], v[20:21], v[24:25] v_add_f64 v[34:35], v[24:25], -v[34:35] v_add_f64 v[44:45], v[26:27], -v[44:45] v_add_f64 v[32:33], v[26:27], v[28:29] v_add_f64 v[38:39], v[28:29], -v[38:39] v_add_f64 v[22:23], v[22:23], -v[42:43] v_add_f64 v[36:37], v[30:31], -v[20:21] v_add_f64 v[14:15], v[14:15], -v[34:35] v_add_f64 v[18:19], v[18:19], -v[44:45] v_add_f64 v[40:41], v[32:33], -v[26:27] v_add_f64 v[16:17], v[16:17], -v[38:39] v_add_f64 v[46:47], v[30:31], -v[36:37] v_add_f64 v[24:25], v[24:25], -v[36:37] v_add_f64 v[34:35], v[22:23], v[14:15] v_add_f64 v[48:49], v[32:33], -v[40:41] v_add_f64 v[28:29], v[28:29], -v[40:41] v_add_f64 v[20:21], v[20:21], -v[46:47] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[26:27], v[26:27], -v[48:49] v_add_f64 v[20:21], v[24:25], v[20:21] v_add_f64 v[24:25], v[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[26:27], v[28:29], v[26:27] v_add_f64 v[28:29], v[34:35], -v[22:23] v_add_f64 v[20:21], v[34:35], v[20:21] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[36:37], v[24:25], -v[18:19] v_add_f64 v[26:27], v[24:25], v[26:27] s_delay_alu instid0(VALU_DEP_4) v_add_f64 v[34:35], v[34:35], -v[28:29] v_add_f64 v[14:15], v[14:15], -v[28:29] v_add_f64 v[38:39], v[30:31], v[20:21] v_add_f64 v[24:25], v[24:25], -v[36:37] v_add_f64 v[16:17], v[16:17], -v[36:37] v_add_f64 v[40:41], v[32:33], v[26:27] v_add_f64 v[22:23], v[22:23], -v[34:35] v_add_f64 v[28:29], v[38:39], -v[30:31] v_add_f64 v[18:19], v[18:19], -v[24:25] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[24:25], v[40:41], -v[32:33] v_add_f64 v[14:15], v[14:15], v[22:23] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[20:21], v[20:21], -v[28:29] v_add_f64 v[16:17], v[16:17], v[18:19] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[18:19], v[26:27], -v[24:25] v_add_f64 v[14:15], v[14:15], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[16:17], v[18:19] v_add_f64 v[18:19], v[38:39], v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[40:41], v[16:17] v_add_f64 v[22:23], v[18:19], -v[38:39] v_add_f64 v[24:25], v[18:19], v[18:19] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[26:27], v[20:21], -v[40:41] v_add_f64 v[28:29], v[20:21], v[20:21] v_add_f64 v[14:15], v[14:15], -v[22:23] s_delay_alu instid0(VALU_DEP_4) v_fma_f64 v[18:19], v[18:19], 2.0, -v[24:25] v_cmp_class_f64_e64 vcc_lo, v[24:25], 0x204 v_add_f64 v[16:17], v[16:17], -v[26:27] v_fma_f64 v[20:21], v[20:21], 2.0, -v[28:29] v_cmp_class_f64_e64 s2, v[28:29], 0x204 v_fma_f64 v[14:15], v[14:15], 2.0, v[18:19] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[16:17], v[16:17], 2.0, v[20:21] v_add_f64 v[18:19], v[24:25], v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[28:29], v[16:17] v_dual_cndmask_b32 v23, v19, v25 :: v_dual_cndmask_b32 v22, v18, v24 v_add_f64 v[18:19], v[18:19], -v[24:25] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v27, v21, v29, s2 v_cndmask_b32_e64 v26, v20, v28, s2 v_add_f64 v[20:21], v[20:21], -v[28:29] v_mul_f64 v[30:31], v[22:23], s[38:39] v_cmp_nlt_f64_e64 s3, 0x40900000, v[22:23] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]| v_mul_f64 v[32:33], v[26:27], s[38:39] v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[22:23] v_cmp_nlt_f64_e64 s5, 0x40900000, v[26:27] v_cmp_ngt_f64_e64 s6, 0xc090cc00, v[26:27] v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[26:27]| v_add_f64 v[14:15], v[14:15], -v[18:19] v_add_f64 v[16:17], v[16:17], -v[20:21] v_rndne_f64_e32 v[30:31], v[30:31] v_rndne_f64_e32 v[32:33], v[32:33] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_dual_cndmask_b32 v15, 0, v15 :: v_dual_cndmask_b32 v14, 0, v14 s_and_b32 vcc_lo, s4, s3 v_cndmask_b32_e64 v17, 0, v17, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_fma_f64 v[34:35], v[30:31], s[42:43], v[22:23] v_cvt_i32_f64_e32 v42, v[30:31] v_cndmask_b32_e64 v16, 0, v16, s2 v_fma_f64 v[36:37], v[32:33], s[42:43], v[26:27] v_fma_f64 v[34:35], v[30:31], s[44:45], v[34:35] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[36:37], v[32:33], s[44:45], v[36:37] v_fma_f64 v[38:39], v[34:35], s[48:49], s[46:47] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[40:41], v[36:37], s[48:49], s[46:47] v_fma_f64 v[38:39], v[34:35], v[38:39], s[50:51] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[40:41], v[36:37], v[40:41], s[50:51] v_fma_f64 v[38:39], v[34:35], v[38:39], s[52:53] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[40:41], v[36:37], v[40:41], s[52:53] v_fma_f64 v[38:39], v[34:35], v[38:39], s[54:55] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[40:41], v[36:37], v[40:41], s[54:55] v_fma_f64 v[38:39], v[34:35], v[38:39], s[56:57] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[40:41], v[36:37], v[40:41], s[56:57] v_fma_f64 v[38:39], v[34:35], v[38:39], s[58:59] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[40:41], v[36:37], v[40:41], s[58:59] v_fma_f64 v[38:39], v[34:35], v[38:39], s[60:61] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[40:41], v[36:37], v[40:41], s[60:61] v_fma_f64 v[38:39], v[34:35], v[38:39], s[62:63] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[40:41], v[36:37], v[40:41], s[62:63] v_fma_f64 v[38:39], v[34:35], v[38:39], s[64:65] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[40:41], v[36:37], v[40:41], s[64:65] v_fma_f64 v[38:39], v[34:35], v[38:39], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[40:41], v[36:37], v[40:41], 1.0 v_fma_f64 v[30:31], v[34:35], v[38:39], 1.0 v_cvt_i32_f64_e32 v34, v[32:33] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[32:33], v[36:37], v[40:41], 1.0 v_ldexp_f64 v[24:25], v[30:31], v42 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ldexp_f64 v[28:29], v[32:33], v34 v_cndmask_b32_e64 v18, 0x7ff00000, v25, s3 v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[6:7]| s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v20, 0x7ff00000, v29, s5 v_cndmask_b32_e64 v19, 0, v18, s4 v_cndmask_b32_e32 v18, 0, v24, vcc_lo s_and_b32 vcc_lo, s6, s5 s_delay_alu instid0(VALU_DEP_3) v_cndmask_b32_e64 v21, 0, v20, s6 v_cndmask_b32_e32 v20, 0, v28, vcc_lo v_cmp_neq_f64_e64 s5, 0x7ff00000, |v[12:13]| v_fma_f64 v[14:15], v[18:19], v[14:15], v[18:19] v_cmp_class_f64_e64 vcc_lo, v[18:19], 0x204 v_cmp_neq_f64_e64 s4, 0, v[6:7] v_cmp_neq_f64_e64 s6, 0, v[12:13] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v15, v15, v19 :: v_dual_cndmask_b32 v12, v14, v18 s_and_b32 vcc_lo, s4, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_and_b32_e32 v15, 0x7fffffff, v15 v_fma_f64 v[16:17], v[20:21], v[16:17], v[20:21] v_cmp_class_f64_e64 s2, v[20:21], 0x204 v_cndmask_b32_e64 v15, 0x7ff00000, v15, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v7, 0, v15, s4 v_cndmask_b32_e64 v17, v17, v21, s2 v_cndmask_b32_e64 v14, v16, v20, s2 s_mov_b32 s2, exec_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v17, 0x7fffffff, v17 v_cndmask_b32_e64 v6, 0x7ff00000, v17, s5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v13, 0, v6, s6 v_cndmask_b32_e32 v6, 0, v12, vcc_lo s_and_b32 vcc_lo, s6, s5 v_cndmask_b32_e32 v12, 0, v14, vcc_lo v_add_f64 v[6:7], v[6:7], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[6:7] v_cndmask_b32_e64 v12, 0, 1, vcc_lo v_lshlrev_b32_e32 v12, 8, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[6:7], v[6:7], v12 v_rsq_f64_e32 v[12:13], v[6:7] s_waitcnt_depctr 0xfff v_mul_f64 v[14:15], v[6:7], v[12:13] v_mul_f64 v[12:13], v[12:13], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], -v[12:13], v[14:15], 0.5 v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15] v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], -v[14:15], v[14:15], v[6:7] v_fma_f64 v[14:15], v[16:17], v[12:13], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], -v[14:15], v[14:15], v[6:7] v_fma_f64 v[12:13], v[16:17], v[12:13], v[14:15] v_cndmask_b32_e64 v14, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x260 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[12:13], v[12:13], v14 v_dual_cndmask_b32 v7, v13, v7 :: v_dual_cndmask_b32 v6, v12, v6 s_delay_alu instid0(VALU_DEP_1) v_cmpx_lt_f64_e32 v[6:7], v[4:5] s_cbranch_execz .LBB0_2 ; %bb.4: ; in Loop: Header=BB0_3 Depth=1 global_load_u8 v8, v10, s[40:41] offset:8 v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7 s_branch .LBB0_2 .LBB0_5: ; %_Z7getZoneP5Pointiii.exit s_clause 0x1 s_load_b32 s2, s[0:1], 0x8 s_load_b64 s[0:1], s[0:1], 0x10 s_waitcnt lgkmcnt(0) v_mul_lo_u32 v0, v11, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshl_add_u32 v0, v0, 4, v9 v_ashrrev_i32_e32 v1, 31, v0 v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) global_store_b8 v[0:1], v8, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13createVoronoiP5PointiiPci .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 28 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 54 .amdhsa_next_free_sgpr 66 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13createVoronoiP5PointiiPci, .Lfunc_end0-_Z13createVoronoiP5PointiiPci ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 6760 ; NumSgprs: 68 ; NumVgprs: 54 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 8 ; VGPRBlocks: 6 ; NumSGPRsForWavesPerEU: 68 ; NumVGPRsForWavesPerEU: 54 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 14 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 28 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13createVoronoiP5PointiiPci .private_segment_fixed_size: 0 .sgpr_count: 68 .sgpr_spill_count: 0 .symbol: _Z13createVoronoiP5PointiiPci.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 54 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "c34cf998bfff40d7bb89170bac3470b008fc5776.hip" .globl _Z15getVoronoiArrayPciiP5Pointi # -- Begin function _Z15getVoronoiArrayPciiP5Pointi .p2align 4, 0x90 .type _Z15getVoronoiArrayPciiP5Pointi,@function _Z15getVoronoiArrayPciiP5Pointi: # @_Z15getVoronoiArrayPciiP5Pointi .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $152, %rsp .cfi_def_cfa_offset 208 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %r8d, %ebp movq %rcx, %r13 movl %edx, %r15d movl %esi, %r12d movq %rdi, 40(%rsp) # 8-byte Spill movl %edx, %eax imull %esi, %eax movslq %eax, %r14 shlq $8, %r14 leaq 16(%rsp), %rdi movq %r14, %rsi callq hipMalloc movl %eax, %edi callq hipGetErrorString movl $.L.str, %edi movq %rax, %rsi xorl %eax, %eax callq printf movslq %ebp, %rax shlq $2, %rax leaq (%rax,%rax,2), %rbx leaq 8(%rsp), %rdi movq %rbx, %rsi callq hipMalloc movl %eax, %edi callq hipGetErrorString movl $.L.str.1, %edi movq %rax, %rsi xorl %eax, %eax callq printf movq 8(%rsp), %rdi movq %r13, %rsi movq %rbx, %rdx movl $1, %ecx callq hipMemcpy movl %eax, %edi callq hipGetErrorString movl $.L.str.2, %edi movq %rax, %rsi xorl %eax, %eax callq printf movl %r15d, %eax movq %r12, %rdi shlq $32, %rdi orq %rax, %rdi movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB0_2 # %bb.1: movq 8(%rsp), %rax movq 16(%rsp), %rcx movq %rax, 104(%rsp) movl %r15d, 36(%rsp) movl %r12d, 32(%rsp) movq %rcx, 96(%rsp) movl %ebp, 28(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 36(%rsp), %rax movq %rax, 120(%rsp) leaq 32(%rsp), %rax movq %rax, 128(%rsp) leaq 96(%rsp), %rax movq %rax, 136(%rsp) leaq 28(%rsp), %rax movq %rax, 144(%rsp) leaq 80(%rsp), %rdi leaq 64(%rsp), %rsi leaq 56(%rsp), %rdx leaq 48(%rsp), %rcx callq __hipPopCallConfiguration movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 64(%rsp), %rcx movl 72(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z13createVoronoiP5PointiiPci, %edi pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB0_2: callq hipDeviceSynchronize movl %eax, %edi callq hipGetErrorString movl $.L.str.3, %edi movq %rax, %rsi xorl %eax, %eax callq printf movq 16(%rsp), %rsi movq 40(%rsp), %rdi # 8-byte Reload movq %r14, %rdx movl $2, %ecx callq hipMemcpy movl %eax, %edi callq hipGetErrorString movl $.L.str.4, %edi movq %rax, %rsi xorl %eax, %eax callq printf movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree addq $152, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z15getVoronoiArrayPciiP5Pointi, .Lfunc_end0-_Z15getVoronoiArrayPciiP5Pointi .cfi_endproc # -- End function .globl _Z28__device_stub__createVoronoiP5PointiiPci # -- Begin function _Z28__device_stub__createVoronoiP5PointiiPci .p2align 4, 0x90 .type _Z28__device_stub__createVoronoiP5PointiiPci,@function _Z28__device_stub__createVoronoiP5PointiiPci: # @_Z28__device_stub__createVoronoiP5PointiiPci .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movl %esi, 12(%rsp) movl %edx, 8(%rsp) movq %rcx, 64(%rsp) movl %r8d, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 12(%rsp), %rax movq %rax, 88(%rsp) leaq 8(%rsp), %rax movq %rax, 96(%rsp) leaq 64(%rsp), %rax movq %rax, 104(%rsp) leaq 4(%rsp), %rax movq %rax, 112(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z13createVoronoiP5PointiiPci, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end1: .size _Z28__device_stub__createVoronoiP5PointiiPci, .Lfunc_end1-_Z28__device_stub__createVoronoiP5PointiiPci .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 cmpl $6, %edi jl .LBB2_10 # %bb.1: movl %edi, %ebp addl $-3, %ebp imull $-1431655765, %ebp, %eax # imm = 0xAAAAAAAB cmpl $1431655765, %eax # imm = 0x55555555 jbe .LBB2_2 .LBB2_10: # %.loopexit.sink.split movl $.L.str.5, %edi xorl %eax, %eax callq printf .LBB2_11: # %.loopexit movl $1, %eax addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB2_2: .cfi_def_cfa_offset 80 movq %rsi, %r12 movl $2863311531, %ebx # imm = 0xAAAAAAAB imulq %rbp, %rbx shrq $33, %rbx movq 8(%rsi), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, (%rsp) # 8-byte Spill movq 16(%r12), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, 8(%rsp) # 8-byte Spill movq %rbx, 16(%rsp) # 8-byte Spill movl %ebx, %ebx leaq (,%rbx,4), %rax leaq (%rax,%rax,2), %rdi callq malloc movq %rax, %r13 cmpl $3, %ebp jb .LBB2_5 # %bb.3: # %.lr.ph.preheader shlq $2, %rbx leaq (%rbx,%rbx,2), %r14 xorl %ebp, %ebp .p2align 4, 0x90 .LBB2_4: # %.lr.ph # =>This Inner Loop Header: Depth=1 movq 24(%r12,%rbp,2), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movl %eax, (%r13,%rbp) movq 32(%r12,%rbp,2), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movl %eax, 4(%r13,%rbp) movq 40(%r12,%rbp,2), %rax movzbl (%rax), %eax movb %al, 8(%r13,%rbp) addq $12, %rbp cmpq %rbp, %r14 jne .LBB2_4 .LBB2_5: # %._crit_edge movq 8(%rsp), %r12 # 8-byte Reload leal 15(%r12), %ebp testl %r12d, %r12d cmovnsl %r12d, %ebp sarl $4, %ebp incl %ebp movq (%rsp), %r15 # 8-byte Reload leal 15(%r15), %r14d testl %r15d, %r15d cmovnsl %r15d, %r14d sarl $4, %r14d incl %r14d movl %ebp, %eax imull %r14d, %eax movslq %eax, %rdi shlq $8, %rdi callq malloc movq %rax, %rbx movq %rax, %rdi movl %r14d, %esi movl %ebp, %edx movq %r13, %rcx movq 16(%rsp), %r8 # 8-byte Reload # kill: def $r8d killed $r8d killed $r8 callq _Z15getVoronoiArrayPciiP5Pointi movl $.Lstr, %edi callq puts@PLT movl $.L.str.7, %edi movl %r15d, %esi movl %r12d, %edx movq %r15, %r14 xorl %eax, %eax callq printf testl %r14d, %r14d jle .LBB2_11 # %bb.6: # %.preheader.lr.ph shll $4, %ebp movslq %ebp, %rcx subl 8(%rsp), %ebp # 4-byte Folded Reload movslq %ebp, %r15 movl %r14d, %r13d leaq -1(%r13), %rax imulq %rcx, %rax addq %rax, %rbx movq %rcx, (%rsp) # 8-byte Spill movq %rcx, %rbp negq %rbp jmp .LBB2_7 .p2align 4, 0x90 .LBB2_8: # %._crit_edge55 # in Loop: Header=BB2_7 Depth=1 movl $10, %edi callq putchar@PLT leaq -1(%r13), %rax addq %rbp, %rbx cmpq $1, %r13 movq %rax, %r13 jle .LBB2_11 .LBB2_7: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB2_9 Depth 2 movq %rbx, %r12 movq (%rsp), %r14 # 8-byte Reload cmpl $0, 8(%rsp) # 4-byte Folded Reload jle .LBB2_8 .p2align 4, 0x90 .LBB2_9: # Parent Loop BB2_7 Depth=1 # => This Inner Loop Header: Depth=2 movsbl (%r12), %esi movl $.L.str.8, %edi xorl %eax, %eax callq printf decq %r14 incq %r12 cmpq %r15, %r14 jg .LBB2_9 jmp .LBB2_8 .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13createVoronoiP5PointiiPci, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA malloc result array: %s\n" .size .L.str, 30 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "CUDA malloc Points: %s\n" .size .L.str.1, 24 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Copy Points to GPU: %s\n" .size .L.str.2, 24 .type _Z13createVoronoiP5PointiiPci,@object # @_Z13createVoronoiP5PointiiPci .section .rodata,"a",@progbits .globl _Z13createVoronoiP5PointiiPci .p2align 3, 0x0 _Z13createVoronoiP5PointiiPci: .quad _Z28__device_stub__createVoronoiP5PointiiPci .size _Z13createVoronoiP5PointiiPci, 8 .type .L.str.3,@object # @.str.3 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.3: .asciz "Run kernel: %s\n" .size .L.str.3, 16 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Copy result from device: %s\n" .size .L.str.4, 29 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char." .size .L.str.5, 108 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Height:%d, Width:%d\n\n" .size .L.str.7, 22 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "%c " .size .L.str.8, 4 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z13createVoronoiP5PointiiPci" .size .L__unnamed_1, 30 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Success\n" .size .Lstr, 9 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__createVoronoiP5PointiiPci .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13createVoronoiP5PointiiPci .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z8arrayaddPiS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R6, SR_TID.X ; ISETP.GT.AND P0, PT, R6, 0x63, PT ; @P0 EXIT ; HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; LDG.E R4, [R4.64] ; LDG.E R3, [R2.64] ; IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; IADD3 R9, R4, R3, RZ ; STG.E [R6.64], R9 ; EXIT ; BRA 0xe0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00084d28_00000000-6_e1f1cce8a8074255abe82b915a9169b16377cc5f.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z31__device_stub__Z8arrayaddPiS_S_PiS_S_ .type _Z31__device_stub__Z8arrayaddPiS_S_PiS_S_, @function _Z31__device_stub__Z8arrayaddPiS_S_PiS_S_: .LFB3694: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z8arrayaddPiS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z31__device_stub__Z8arrayaddPiS_S_PiS_S_, .-_Z31__device_stub__Z8arrayaddPiS_S_PiS_S_ .globl _Z8arrayaddPiS_S_ .type _Z8arrayaddPiS_S_, @function _Z8arrayaddPiS_S_: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z8arrayaddPiS_S_PiS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z8arrayaddPiS_S_, .-_Z8arrayaddPiS_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string " + " .LC1: .string " = " .LC2: .string "\n" .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsp, %rbp .cfi_def_cfa_register 6 pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $72, %rsp .cfi_offset 15, -24 .cfi_offset 14, -32 .cfi_offset 13, -40 .cfi_offset 12, -48 .cfi_offset 3, -56 movq %fs:40, %rax movq %rax, -56(%rbp) xorl %eax, %eax movq %rsp, %rax .L12: cmpq %rax, %rsp je .L13 subq $4096, %rsp orq $0, 4088(%rsp) jmp .L12 .L13: subq $400, %rsp orq $0, 392(%rsp) movq %rsp, %r13 movq %rsp, %rax .L15: cmpq %rax, %rsp je .L16 subq $4096, %rsp orq $0, 4088(%rsp) jmp .L15 .L16: subq $400, %rsp orq $0, 392(%rsp) movq %rsp, %r15 movq %rsp, %rax .L18: cmpq %rax, %rsp je .L19 subq $4096, %rsp orq $0, 4088(%rsp) jmp .L18 .L19: subq $400, %rsp orq $0, 392(%rsp) movq %rsp, %r14 movl $0, %eax .L21: leal (%rax,%rax), %edx movl %edx, 0(%r13,%rax) movl %edx, (%r15,%rax) movl $0, (%r14,%rax) addq $4, %rax cmpq $400, %rax jne .L21 leaq -104(%rbp), %rdi movl $400, %esi call cudaMalloc@PLT leaq -96(%rbp), %rdi movl $400, %esi call cudaMalloc@PLT leaq -88(%rbp), %rdi movl $400, %esi call cudaMalloc@PLT movl $1, %ecx movl $400, %edx movq %r13, %rsi movq -104(%rbp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $400, %edx movq %r15, %rsi movq -96(%rbp), %rdi call cudaMemcpy@PLT movl $1024, -68(%rbp) movl $1, -64(%rbp) movl $1, -60(%rbp) movl $1, -80(%rbp) movl $1, -76(%rbp) movl $1, -72(%rbp) movl $0, %r9d movl $0, %r8d movq -68(%rbp), %rdx movl $1, %ecx movq -80(%rbp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L28 .L22: movl $2, %ecx movl $400, %edx movq -88(%rbp), %rsi movq %r14, %rdi call cudaMemcpy@PLT movl $0, %ebx .L23: movl 0(%r13,%rbx), %esi leaq _ZSt4cout(%rip), %rdi call _ZNSolsEi@PLT movq %rax, %r12 movl $3, %edx leaq .LC0(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl (%r15,%rbx), %esi movq %r12, %rdi call _ZNSolsEi@PLT movq %rax, %r12 movl $3, %edx leaq .LC1(%rip), %rsi movq %rax, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl (%r14,%rbx), %esi movq %r12, %rdi call _ZNSolsEi@PLT movq %rax, %rdi movl $1, %edx leaq .LC2(%rip), %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT addq $4, %rbx cmpq $400, %rbx jne .L23 movq -56(%rbp), %rax subq %fs:40, %rax jne .L29 movl $0, %eax leaq -40(%rbp), %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 popq %rbp .cfi_remember_state .cfi_def_cfa 7, 8 ret .L28: .cfi_restore_state movq -88(%rbp), %rdx movq -96(%rbp), %rsi movq -104(%rbp), %rdi call _Z31__device_stub__Z8arrayaddPiS_S_PiS_S_ jmp .L22 .L29: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z8arrayaddPiS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _Z8arrayaddPiS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z8arrayaddPiS_S_ ; -- Begin function _Z8arrayaddPiS_S_ .globl _Z8arrayaddPiS_S_ .p2align 8 .type _Z8arrayaddPiS_S_,@function _Z8arrayaddPiS_S_: ; @_Z8arrayaddPiS_S_ ; %bb.0: s_mov_b32 s2, exec_lo v_cmpx_gt_u32_e32 0x64, v0 s_cbranch_execz .LBB0_2 ; %bb.1: s_load_b128 s[4:7], s[0:1], 0x0 v_lshlrev_b32_e32 v0, 2, v0 s_load_b64 s[0:1], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b32 v1, v0, s[4:5] global_load_b32 v2, v0, s[6:7] s_waitcnt vmcnt(0) v_add_nc_u32_e32 v1, v2, v1 global_store_b32 v0, v1, s[0:1] .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z8arrayaddPiS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 8 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z8arrayaddPiS_S_, .Lfunc_end0-_Z8arrayaddPiS_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 88 ; NumSgprs: 8 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 8 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z8arrayaddPiS_S_ .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z8arrayaddPiS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "e1f1cce8a8074255abe82b915a9169b16377cc5f.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z23__device_stub__arrayaddPiS_S_ # -- Begin function _Z23__device_stub__arrayaddPiS_S_ .p2align 4, 0x90 .type _Z23__device_stub__arrayaddPiS_S_,@function _Z23__device_stub__arrayaddPiS_S_: # @_Z23__device_stub__arrayaddPiS_S_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z8arrayaddPiS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z23__device_stub__arrayaddPiS_S_, .Lfunc_end0-_Z23__device_stub__arrayaddPiS_S_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $1336, %rsp # imm = 0x538 .cfi_def_cfa_offset 1360 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 leaq 128(%rsp), %rdi xorl %ebx, %ebx movl $400, %edx # imm = 0x190 xorl %esi, %esi callq memset@PLT xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl %ebx, 928(%rsp,%rax,4) movl %ebx, 528(%rsp,%rax,4) incq %rax addl $8, %ebx cmpq $100, %rax jne .LBB1_1 # %bb.2: leaq 16(%rsp), %rdi movl $400, %esi # imm = 0x190 callq hipMalloc leaq 8(%rsp), %rdi movl $400, %esi # imm = 0x190 callq hipMalloc movq %rsp, %rdi movl $400, %esi # imm = 0x190 callq hipMalloc movq 16(%rsp), %rdi leaq 928(%rsp), %rsi movl $400, %edx # imm = 0x190 movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi leaq 528(%rsp), %rsi movl $400, %edx # imm = 0x190 movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 1023(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 16(%rsp), %rax movq 8(%rsp), %rcx movq (%rsp), %rdx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movq %rdx, 72(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z8arrayaddPiS_S_, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: movq (%rsp), %rsi leaq 128(%rsp), %rdi movl $400, %edx # imm = 0x190 movl $2, %ecx callq hipMemcpy xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 movl 928(%rsp,%r14,4), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq %rax, %rbx movl $.L.str, %esi movl $3, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 528(%rsp,%r14,4), %esi movq %rbx, %rdi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.1, %esi movl $3, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 128(%rsp,%r14,4), %esi movq %rbx, %rdi callq _ZNSolsEi movl $.L.str.2, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l incq %r14 cmpq $100, %r14 jne .LBB1_5 # %bb.6: xorl %eax, %eax addq $1336, %rsp # imm = 0x538 .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z8arrayaddPiS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z8arrayaddPiS_S_,@object # @_Z8arrayaddPiS_S_ .section .rodata,"a",@progbits .globl _Z8arrayaddPiS_S_ .p2align 3, 0x0 _Z8arrayaddPiS_S_: .quad _Z23__device_stub__arrayaddPiS_S_ .size _Z8arrayaddPiS_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz " + " .size .L.str, 4 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " = " .size .L.str.1, 4 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "\n" .size .L.str.2, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z8arrayaddPiS_S_" .size .L__unnamed_1, 18 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z23__device_stub__arrayaddPiS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z8arrayaddPiS_S_ .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
448
3,604
1,823
3,540
190
code for sm_80
.file "tmpxft_000b7aee_00000000-6_f64fa5706577c3e7c2919775cbae585237847300.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "f64fa5706577c3e7c2919775cbae585237847300.hip" .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
8
771
301
229
191
code for sm_80 Function : _Z7computeffffffffff .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; ULDC UR4, c[0x0][0x164] ; IMAD.MOV.U32 R3, RZ, RZ, 0x7925de1a ; IADD3 R1, R1, -0x8, RZ ; IMAD.U32 R4, RZ, RZ, UR4 ; IMAD.MOV.U32 R2, RZ, RZ, 0x5c58e20 ; FCHK P0, R4, 1.8577999448525069129e-35 ; FFMA R0, R3, -R2, 1 ; FFMA R0, R0, R3, 5.38271085326551625259e+34 ; FFMA R3, R0, c[0x0][0x164], RZ ; FFMA R2, R3, -R2, c[0x0][0x164] ; FFMA R0, R0, R2, R3 ; @!P0 BRA 0x120 ; HFMA2.MMA R9, -RZ, RZ, 8.8036060333251953125e-05, -0.00037384033203125 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x164] ; MOV R2, 0x110 ; CALL.REL.NOINC 0x540 ; IMAD.MOV.U32 R0, RZ, RZ, R4 ; MUFU.RCP R2, c[0x0][0x170] ; ULDC UR4, c[0x0][0x16c] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; IMAD.U32 R6, RZ, RZ, UR4 ; FCHK P0, R6, c[0x0][0x170] ; FFMA R3, R2, -R5, 1 ; FFMA R3, R2, R3, R2 ; FFMA R2, R3, c[0x0][0x16c], RZ ; FFMA R4, R2, -R5, c[0x0][0x16c] ; FFMA R2, R3, R4, R2 ; @!P0 BRA 0x220 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x16c] ; MOV R9, c[0x0][0x170] ; MOV R2, 0x210 ; CALL.REL.NOINC 0x540 ; IMAD.MOV.U32 R2, RZ, RZ, R4 ; IMAD.MOV.U32 R3, RZ, RZ, 0x3bbb989d ; MUFU.RCP R4, c[0x0][0x184] ; FADD R2, R2, c[0x0][0x168] ; ULDC UR4, c[0x0][0x180] ; IMAD.MOV.U32 R6, RZ, RZ, 0x437c0000 ; MOV R8, UR4 ; FFMA.SAT R3, R2, R3, 0.5 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; FCHK P0, R8, c[0x0][0x184] ; FFMA.RM R3, R3, R6, 12582913 ; IADD3 R6, P1, R1, c[0x0][0x20], RZ ; FADD R5, R3.reuse, -12583039 ; IMAD.SHL.U32 R3, R3, 0x800000, RZ ; FFMA R5, R2, 1.4426950216293334961, -R5 ; FFMA R7, R4, -R9, 1 ; FFMA R5, R2, 1.925963033500011079e-08, R5 ; FFMA R7, R4, R7, R4 ; MUFU.EX2 R5, R5 ; FFMA R2, R7, c[0x0][0x180], RZ ; FFMA R4, R2, -R9, c[0x0][0x180] ; FFMA R2, R7, R4, R2 ; IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; FFMA R0, R3, R5, R0 ; @!P0 BRA 0x3f0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; MOV R2, 0x3e0 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; CALL.REL.NOINC 0x540 ; MOV R2, R4 ; FADD R2, R2, c[0x0][0x17c] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; FADD R2, R2, c[0x0][0x178] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; FMUL R2, RZ, -R2 ; FMUL R3, R2, c[0x0][0x174] ; MOV R2, 0x0 ; FSETP.GE.AND P0, PT, R0, R3, PT ; LDC.64 R2, c[0x4][R2] ; @P0 FADD R0, RZ, R0 ; F2F.F64.F32 R8, R0 ; STL.64 [R1], R8 ; LEPC R8 ; MOV R11, 0x530 ; MOV R20, 0x4b0 ; MOV R21, 0x0 ; MOV R0, 0x0 ; IADD3 R20, P0, P1, -R20, R11, R8 ; IADD3.X R21, ~R0, R21, R9, P0, P1 ; CALL.ABS.NOINC R2 ; EXIT ; SHF.R.U32.HI R4, RZ, 0x17, R9.reuse ; SHF.R.U32.HI R3, RZ, 0x17, R8.reuse ; LOP3.LUT R13, R4, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R4, RZ, RZ, R9 ; LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R3, RZ, RZ, R8 ; IADD3 R12, R13, -0x1, RZ ; IADD3 R10, R11, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; @!P0 MOV R5, RZ ; @!P0 BRA 0x770 ; FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; FSETP.GTU.FTZ.AND P1, PT, |R9|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0xb50 ; LOP3.LUT P0, RZ, R4, 0x7fffffff, R3, 0xc8, !PT ; @!P0 BRA 0xb30 ; FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P1, PT, |R9|, +INF , PT ; FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; @!P1 BRA !P2, 0xb30 ; LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; @P1 BRA 0xb10 ; LOP3.LUT P1, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; @P0 BRA 0xae0 ; ISETP.GE.AND P0, PT, R10, RZ, PT ; ISETP.GE.AND P1, PT, R12, RZ, PT ; @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; @!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x40 ; @!P0 FFMA R3, R8, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R4, R9, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R5, R5, 0x40, RZ ; LEA R9, R13, 0xc0800000, 0x17 ; IMAD.IADD R9, R4, 0x1, -R9 ; IADD3 R4, R11, -0x7f, RZ ; MUFU.RCP R8, R9 ; FADD.FTZ R10, -R9, -RZ ; IMAD R3, R4, -0x800000, R3 ; FFMA R11, R8, R10, 1 ; FFMA R12, R8, R11, R8 ; FFMA R8, R3, R12, RZ ; FFMA R11, R10, R8, R3 ; FFMA R11, R12, R11, R8 ; IADD3 R8, R4, 0x7f, -R13 ; FFMA R10, R10, R11, R3 ; IADD3 R8, R8, R5, RZ ; FFMA R3, R12, R10, R11 ; SHF.R.U32.HI R4, RZ, 0x17, R3 ; LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; IMAD.IADD R13, R4, 0x1, R8 ; IADD3 R4, R13, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; @!P0 BRA 0xac0 ; ISETP.GT.AND P0, PT, R13, 0xfe, PT ; @P0 BRA 0xa90 ; ISETP.GE.AND P0, PT, R13, 0x1, PT ; @P0 BRA 0xb60 ; ISETP.GE.AND P0, PT, R13, -0x18, PT ; LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0xb60 ; FFMA.RZ R4, R12.reuse, R10.reuse, R11.reuse ; IADD3 R9, R13.reuse, 0x20, RZ ; FFMA.RM R5, R12, R10.reuse, R11.reuse ; ISETP.NE.AND P2, PT, R13.reuse, RZ, PT ; LOP3.LUT R8, R4, 0x7fffff, RZ, 0xc0, !PT ; FFMA.RP R4, R12, R10, R11 ; ISETP.NE.AND P1, PT, R13, RZ, PT ; IMAD.MOV R10, RZ, RZ, -R13 ; LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; SHF.L.U32 R9, R8, R9, RZ ; SEL R5, R10, RZ, P2 ; ISETP.NE.AND P1, PT, R9, RZ, P1 ; SHF.R.U32.HI R5, RZ, R5, R8 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R9, RZ, 0x1, R5 ; SEL R4, RZ, 0x1, !P0 ; LOP3.LUT R4, R4, 0x1, R9, 0xf8, !PT ; LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; IMAD.IADD R4, R9, 0x1, R4 ; LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; BRA 0xb60 ; LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; BRA 0xb60 ; LEA R3, R8, R3, 0x17 ; BRA 0xb60 ; LOP3.LUT R3, R4, 0x80000000, R3, 0x48, !PT ; LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; BRA 0xb60 ; LOP3.LUT R3, R4, 0x80000000, R3, 0x48, !PT ; BRA 0xb60 ; MUFU.RSQ R3, -QNAN ; BRA 0xb60 ; FADD.FTZ R3, R8, R9 ; IMAD.MOV.U32 R4, RZ, RZ, R3 ; IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; RET.REL.NODEC R2 0x0 ; BRA 0xb90; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0007ab04_00000000-6_382416efd2abb46e8b8b611957842fb3e5795a37.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z11initPointerf .type _Z11initPointerf, @function _Z11initPointerf: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movd %xmm0, %ebx movl $40, %edi call malloc@PLT movq %rax, %rdx leaq 40(%rax), %rcx .L4: movl %ebx, (%rdx) addq $4, %rdx cmpq %rcx, %rdx jne .L4 popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z11initPointerf, .-_Z11initPointerf .globl _Z34__device_stub__Z7computeffffffffffffffffffff .type _Z34__device_stub__Z7computeffffffffffffffffffff, @function _Z34__device_stub__Z7computeffffffffffffffffffff: .LFB2083: .cfi_startproc endbr64 subq $200, %rsp .cfi_def_cfa_offset 208 movss %xmm0, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm2, 20(%rsp) movss %xmm3, 16(%rsp) movss %xmm4, 12(%rsp) movss %xmm5, 8(%rsp) movss %xmm6, 4(%rsp) movss %xmm7, (%rsp) movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 24(%rsp), %rax movq %rax, 104(%rsp) leaq 20(%rsp), %rax movq %rax, 112(%rsp) leaq 16(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) leaq 8(%rsp), %rax movq %rax, 136(%rsp) leaq 4(%rsp), %rax movq %rax, 144(%rsp) movq %rsp, %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 184(%rsp), %rax subq %fs:40, %rax jne .L12 addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 216 pushq 40(%rsp) .cfi_def_cfa_offset 224 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7computeffffffffff(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 208 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z34__device_stub__Z7computeffffffffffffffffffff, .-_Z34__device_stub__Z7computeffffffffffffffffffff .globl _Z7computeffffffffff .type _Z7computeffffffffff, @function _Z7computeffffffffff: .LFB2084: .cfi_startproc endbr64 subq $24, %rsp .cfi_def_cfa_offset 32 movss 40(%rsp), %xmm8 movss %xmm8, 8(%rsp) movss 32(%rsp), %xmm8 movss %xmm8, (%rsp) call _Z34__device_stub__Z7computeffffffffffffffffffff addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z7computeffffffffff, .-_Z7computeffffffffff .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 subq $112, %rsp .cfi_def_cfa_offset 128 movq %rsi, %rbx movq 8(%rsi), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 72(%rsp) movq 16(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 64(%rsp) movq 24(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 56(%rsp) movq 32(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 48(%rsp) movq 40(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 40(%rsp) movq 48(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 32(%rsp) movq 56(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 24(%rsp) movq 64(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 16(%rsp) movq 72(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 8(%rsp) movq 80(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, (%rsp) movl $1, 100(%rsp) movl $1, 104(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $0, %r9d movl $0, %r8d movq 100(%rsp), %rdx movl $1, %ecx movq 88(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L18 .L16: call cudaDeviceSynchronize@PLT movl $0, %eax addq $112, %rsp .cfi_remember_state .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 ret .L18: .cfi_restore_state pxor %xmm0, %xmm0 cvtsd2ss 72(%rsp), %xmm0 pxor %xmm1, %xmm1 cvtsd2ss (%rsp), %xmm1 leaq -16(%rsp), %rsp .cfi_def_cfa_offset 144 movss %xmm1, 8(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 24(%rsp), %xmm1 movss %xmm1, (%rsp) pxor %xmm7, %xmm7 cvtsd2ss 32(%rsp), %xmm7 pxor %xmm6, %xmm6 cvtsd2ss 40(%rsp), %xmm6 pxor %xmm5, %xmm5 cvtsd2ss 48(%rsp), %xmm5 pxor %xmm4, %xmm4 cvtsd2ss 56(%rsp), %xmm4 pxor %xmm3, %xmm3 cvtsd2ss 64(%rsp), %xmm3 pxor %xmm2, %xmm2 cvtsd2ss 72(%rsp), %xmm2 pxor %xmm1, %xmm1 cvtsd2ss 80(%rsp), %xmm1 call _Z34__device_stub__Z7computeffffffffffffffffffff addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L16 .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z7computeffffffffff" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z7computeffffffffff(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z7computeffffffffff ; -- Begin function _Z7computeffffffffff .globl _Z7computeffffffffff .p2align 8 .type _Z7computeffffffffff,@function _Z7computeffffffffff: ; @_Z7computeffffffffff ; %bb.0: s_load_b64 s[8:9], s[0:1], 0x78 v_mbcnt_lo_u32_b32 v20, -1, 0 v_mov_b32_e32 v6, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20 ;;#ASMSTART ;;#ASMEND v_readfirstlane_b32 s2, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s2, s2, v4 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_6 ; %bb.1: v_mov_b32_e32 v0, 0 s_mov_b32 s4, exec_lo s_waitcnt lgkmcnt(0) global_load_b64 v[8:9], v0, s[8:9] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[8:9] offset:40 global_load_b64 v[5:6], v0, s[8:9] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[8:9] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB0_5 ; %bb.2: ; %.preheader3.i.i.i.preheader s_mov_b32 s5, 0 .p2align 6 .LBB0_3: ; %.preheader3.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[8:9] offset:40 global_load_b64 v[10:11], v0, s[8:9] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[8:9] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_3 ; %bb.4: ; %Flow311 s_or_b32 exec_lo, exec_lo, s5 .LBB0_5: ; %Flow313 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB0_6: ; %.loopexit4.i.i.i s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s3 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s4, v6 v_readfirstlane_b32 s5, v7 s_mov_b32 s10, exec_lo s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[8:9], v5, s[8:9] offset:40 global_load_b128 v[0:3], v5, s[8:9] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_8 ; %bb.7: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, 0 s_mul_i32 s10, s7, 24 s_mul_hi_u32 s11, s6, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s11, s11, s10 s_mul_i32 s10, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s10 v_add_co_ci_u32_e32 v11, vcc_lo, s11, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB0_8: s_or_b32 exec_lo, exec_lo, s3 s_lshl_b64 s[10:11], s[6:7], 12 v_lshlrev_b64 v[4:5], 6, v[4:5] s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v2, s10 v_add_co_ci_u32_e32 v7, vcc_lo, s11, v3, vcc_lo v_mov_b32_e32 v3, 0 s_mov_b32 s12, 0 s_delay_alu instid0(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, v2, v4 v_mov_b32_e32 v2, 33 s_mov_b32 s13, s12 s_mov_b32 s14, s12 s_mov_b32 s15, s12 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v4, v3 v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s12 v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14 v_mov_b32_e32 v11, s15 s_clause 0x3 global_store_b128 v[6:7], v[2:5], off global_store_b128 v[6:7], v[8:11], off offset:16 global_store_b128 v[6:7], v[8:11], off offset:32 global_store_b128 v[6:7], v[8:11], off offset:48 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_16 ; %bb.9: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4 v_mov_b32_e32 v12, s5 s_clause 0x1 global_load_b64 v[13:14], v10, s[8:9] offset:32 glc global_load_b64 v[2:3], v10, s[8:9] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s10, v2 v_readfirstlane_b32 s11, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[10:11], s[10:11], s[4:5] s_mul_i32 s11, s11, 24 s_mul_hi_u32 s12, s10, 24 s_mul_i32 s10, s10, 24 s_add_i32 s12, s12, s11 v_add_co_u32 v8, vcc_lo, v0, s10 v_add_co_ci_u32_e32 v9, vcc_lo, s12, v1, vcc_lo s_mov_b32 s10, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[8:9] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[13:14] s_cbranch_execz .LBB0_12 ; %bb.10: ; %.preheader1.i.i.i.preheader s_mov_b32 s11, 0 .LBB0_11: ; %.preheader1.i.i.i ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 s_sleep 1 global_store_b64 v[8:9], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[8:9] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s11, vcc_lo, s11 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s11 s_cbranch_execnz .LBB0_11 .LBB0_12: ; %Flow309 s_or_b32 exec_lo, exec_lo, s10 v_mov_b32_e32 v2, 0 s_mov_b32 s11, exec_lo s_mov_b32 s10, exec_lo v_mbcnt_lo_u32_b32 v4, s11, 0 global_load_b64 v[2:3], v2, s[8:9] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB0_14 ; %bb.13: s_bcnt1_i32_b32 s11, s11 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s11 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB0_14: s_or_b32 exec_lo, exec_lo, s10 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB0_16 ; %bb.15: global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s10, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s10, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_16: ; %Flow310 s_or_b32 exec_lo, exec_lo, s3 s_mul_i32 s3, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s3 s_mul_i32 s3, s6, 24 v_add_co_u32 v0, vcc_lo, v0, s3 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_20 .p2align 6 .LBB0_17: ; in Loop: Header=BB0_20 Depth=1 s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s3, v2 s_cmp_eq_u32 s3, 0 s_cbranch_scc1 .LBB0_19 ; %bb.18: ; in Loop: Header=BB0_20 Depth=1 s_sleep 1 s_cbranch_execnz .LBB0_20 s_branch .LBB0_22 .p2align 6 .LBB0_19: s_branch .LBB0_22 .LBB0_20: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_17 ; %bb.21: ; in Loop: Header=BB0_20 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_17 .LBB0_22: global_load_b64 v[21:22], v[6:7], off s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_26 ; %bb.23: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[8:9] offset:40 global_load_b64 v[7:8], v6, s[8:9] offset:24 glc global_load_b64 v[4:5], v6, s[8:9] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s4 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[8:9] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_26 ; %bb.24: ; %.preheader.i.i.i.preheader s_mov_b32 s2, 0 .LBB0_25: ; %.preheader.i.i.i ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[8:9] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB0_25 .LBB0_26: ; %__ockl_printf_begin.exit s_or_b32 exec_lo, exec_lo, s3 s_getpc_b64 s[4:5] s_add_u32 s4, s4, .str@rel32@lo+4 s_addc_u32 s5, s5, .str@rel32@hi+12 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u64 s[4:5], 0 s_cbranch_scc0 .LBB0_104 ; %bb.27: s_waitcnt vmcnt(0) v_dual_mov_b32 v24, 0 :: v_dual_and_b32 v23, 2, v21 v_and_b32_e32 v0, -3, v21 s_mov_b64 s[6:7], 7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_mov_b32 v1, v22 :: v_dual_mov_b32 v26, v24 v_mov_b32_e32 v25, v23 s_branch .LBB0_29 .LBB0_28: ; %__ockl_hostcall_preview.exit20.i ; in Loop: Header=BB0_29 Depth=1 s_or_b32 exec_lo, exec_lo, s3 s_sub_u32 s6, s6, s10 s_subb_u32 s7, s7, s11 s_add_u32 s4, s4, s10 s_addc_u32 s5, s5, s11 s_cmp_lg_u64 s[6:7], 0 s_cbranch_scc0 .LBB0_105 .LBB0_29: ; =>This Loop Header: Depth=1 ; Child Loop BB0_32 Depth 2 ; Child Loop BB0_39 Depth 2 ; Child Loop BB0_46 Depth 2 ; Child Loop BB0_53 Depth 2 ; Child Loop BB0_60 Depth 2 ; Child Loop BB0_67 Depth 2 ; Child Loop BB0_74 Depth 2 ; Child Loop BB0_81 Depth 2 ; Child Loop BB0_89 Depth 2 ; Child Loop BB0_98 Depth 2 ; Child Loop BB0_103 Depth 2 v_cmp_lt_u64_e64 s2, s[6:7], 56 ; implicit-def: $vgpr2_vgpr3 ; implicit-def: $sgpr17 s_delay_alu instid0(VALU_DEP_1) s_and_b32 s2, s2, exec_lo s_cselect_b32 s10, s6, 56 s_cselect_b32 s11, s7, 0 s_cmp_gt_u32 s10, 7 s_mov_b32 s2, -1 s_cbranch_scc1 .LBB0_34 ; %bb.30: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 s_cmp_eq_u32 s10, 0 s_cbranch_scc1 .LBB0_33 ; %bb.31: ; %.preheader31.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_lshl_b64 s[2:3], s[10:11], 3 s_mov_b64 s[12:13], 0 s_mov_b64 s[14:15], s[4:5] .LBB0_32: ; %.preheader31.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v4, v24, s[14:15] s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v4 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[4:5], s12, v[23:24] s_add_u32 s12, s12, 8 s_addc_u32 s13, s13, 0 s_add_u32 s14, s14, 1 s_addc_u32 s15, s15, 0 s_cmp_lg_u32 s2, s12 v_or_b32_e32 v2, v4, v2 v_or_b32_e32 v3, v5, v3 s_cbranch_scc1 .LBB0_32 .LBB0_33: ; %Flow280 ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s2, 0 s_mov_b32 s17, 0 .LBB0_34: ; %Flow282 ; in Loop: Header=BB0_29 Depth=1 s_and_not1_b32 vcc_lo, exec_lo, s2 s_mov_b64 s[2:3], s[4:5] s_cbranch_vccnz .LBB0_36 ; %bb.35: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[2:3], v24, s[4:5] s_add_i32 s17, s10, -8 s_add_u32 s2, s4, 8 s_addc_u32 s3, s5, 0 .LBB0_36: ; %.loopexit32.i ; in Loop: Header=BB0_29 Depth=1 s_cmp_gt_u32 s17, 7 s_cbranch_scc1 .LBB0_41 ; %bb.37: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_cmp_eq_u32 s17, 0 s_cbranch_scc1 .LBB0_40 ; %bb.38: ; %.preheader29.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b64 s[12:13], 0 s_mov_b64 s[14:15], 0 .LBB0_39: ; %.preheader29.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s18, s2, s14 s_addc_u32 s19, s3, s15 s_add_u32 s14, s14, 1 global_load_u8 v6, v24, s[18:19] s_addc_u32 s15, s15, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], s12, v[23:24] s_add_u32 s12, s12, 8 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s17, s14 v_or_b32_e32 v4, v6, v4 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v5, v7, v5 s_cbranch_scc1 .LBB0_39 .LBB0_40: ; %Flow275 ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s16, 0 s_cbranch_execz .LBB0_42 s_branch .LBB0_43 .LBB0_41: ; in Loop: Header=BB0_29 Depth=1 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $sgpr16 .LBB0_42: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[4:5], v24, s[2:3] s_add_i32 s16, s17, -8 s_add_u32 s2, s2, 8 s_addc_u32 s3, s3, 0 .LBB0_43: ; %.loopexit30.i ; in Loop: Header=BB0_29 Depth=1 s_cmp_gt_u32 s16, 7 s_cbranch_scc1 .LBB0_48 ; %bb.44: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_cmp_eq_u32 s16, 0 s_cbranch_scc1 .LBB0_47 ; %bb.45: ; %.preheader27.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b64 s[12:13], 0 s_mov_b64 s[14:15], 0 .LBB0_46: ; %.preheader27.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s18, s2, s14 s_addc_u32 s19, s3, s15 s_add_u32 s14, s14, 1 global_load_u8 v8, v24, s[18:19] s_addc_u32 s15, s15, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], s12, v[23:24] s_add_u32 s12, s12, 8 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s16, s14 v_or_b32_e32 v6, v8, v6 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v7, v9, v7 s_cbranch_scc1 .LBB0_46 .LBB0_47: ; %Flow270 ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s17, 0 s_cbranch_execz .LBB0_49 s_branch .LBB0_50 .LBB0_48: ; in Loop: Header=BB0_29 Depth=1 ; implicit-def: $sgpr17 .LBB0_49: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[6:7], v24, s[2:3] s_add_i32 s17, s16, -8 s_add_u32 s2, s2, 8 s_addc_u32 s3, s3, 0 .LBB0_50: ; %.loopexit28.i ; in Loop: Header=BB0_29 Depth=1 s_cmp_gt_u32 s17, 7 s_cbranch_scc1 .LBB0_55 ; %bb.51: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 s_cmp_eq_u32 s17, 0 s_cbranch_scc1 .LBB0_54 ; %bb.52: ; %.preheader25.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b64 s[12:13], 0 s_mov_b64 s[14:15], 0 .LBB0_53: ; %.preheader25.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s18, s2, s14 s_addc_u32 s19, s3, s15 s_add_u32 s14, s14, 1 global_load_u8 v10, v24, s[18:19] s_addc_u32 s15, s15, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[10:11], s12, v[23:24] s_add_u32 s12, s12, 8 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s17, s14 v_or_b32_e32 v8, v10, v8 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v9, v11, v9 s_cbranch_scc1 .LBB0_53 .LBB0_54: ; %Flow265 ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s16, 0 s_cbranch_execz .LBB0_56 s_branch .LBB0_57 .LBB0_55: ; in Loop: Header=BB0_29 Depth=1 ; implicit-def: $vgpr8_vgpr9 ; implicit-def: $sgpr16 .LBB0_56: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[8:9], v24, s[2:3] s_add_i32 s16, s17, -8 s_add_u32 s2, s2, 8 s_addc_u32 s3, s3, 0 .LBB0_57: ; %.loopexit26.i ; in Loop: Header=BB0_29 Depth=1 s_cmp_gt_u32 s16, 7 s_cbranch_scc1 .LBB0_62 ; %bb.58: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_cmp_eq_u32 s16, 0 s_cbranch_scc1 .LBB0_61 ; %bb.59: ; %.preheader23.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b64 s[12:13], 0 s_mov_b64 s[14:15], 0 .LBB0_60: ; %.preheader23.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s18, s2, s14 s_addc_u32 s19, s3, s15 s_add_u32 s14, s14, 1 global_load_u8 v12, v24, s[18:19] s_addc_u32 s15, s15, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[12:13], s12, v[23:24] s_add_u32 s12, s12, 8 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s16, s14 v_or_b32_e32 v10, v12, v10 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v11, v13, v11 s_cbranch_scc1 .LBB0_60 .LBB0_61: ; %Flow260 ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s17, 0 s_cbranch_execz .LBB0_63 s_branch .LBB0_64 .LBB0_62: ; in Loop: Header=BB0_29 Depth=1 ; implicit-def: $sgpr17 .LBB0_63: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[10:11], v24, s[2:3] s_add_i32 s17, s16, -8 s_add_u32 s2, s2, 8 s_addc_u32 s3, s3, 0 .LBB0_64: ; %.loopexit24.i ; in Loop: Header=BB0_29 Depth=1 s_cmp_gt_u32 s17, 7 s_cbranch_scc1 .LBB0_69 ; %bb.65: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_cmp_eq_u32 s17, 0 s_cbranch_scc1 .LBB0_68 ; %bb.66: ; %.preheader21.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b64 s[12:13], 0 s_mov_b64 s[14:15], 0 .LBB0_67: ; %.preheader21.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s18, s2, s14 s_addc_u32 s19, s3, s15 s_add_u32 s14, s14, 1 global_load_u8 v14, v24, s[18:19] s_addc_u32 s15, s15, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[14:15], s12, v[23:24] s_add_u32 s12, s12, 8 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s17, s14 v_or_b32_e32 v12, v14, v12 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v13, v15, v13 s_cbranch_scc1 .LBB0_67 .LBB0_68: ; %Flow255 ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s16, 0 s_cbranch_execz .LBB0_70 s_branch .LBB0_71 .LBB0_69: ; in Loop: Header=BB0_29 Depth=1 ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $sgpr16 .LBB0_70: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[12:13], v24, s[2:3] s_add_i32 s16, s17, -8 s_add_u32 s2, s2, 8 s_addc_u32 s3, s3, 0 .LBB0_71: ; %.loopexit22.i ; in Loop: Header=BB0_29 Depth=1 s_cmp_gt_u32 s16, 7 s_cbranch_scc1 .LBB0_76 ; %bb.72: ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v14, 0 v_mov_b32_e32 v15, 0 s_cmp_eq_u32 s16, 0 s_cbranch_scc1 .LBB0_75 ; %bb.73: ; %.preheader.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b64 s[12:13], 0 s_mov_b64 s[14:15], s[2:3] .LBB0_74: ; %.preheader.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_u8 v16, v24, s[14:15] s_add_i32 s16, s16, -1 s_waitcnt vmcnt(0) v_and_b32_e32 v23, 0xffff, v16 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[16:17], s12, v[23:24] s_add_u32 s12, s12, 8 s_addc_u32 s13, s13, 0 s_add_u32 s14, s14, 1 s_addc_u32 s15, s15, 0 s_cmp_lg_u32 s16, 0 v_or_b32_e32 v14, v16, v14 v_or_b32_e32 v15, v17, v15 s_cbranch_scc1 .LBB0_74 .LBB0_75: ; %Flow250 ; in Loop: Header=BB0_29 Depth=1 s_cbranch_execz .LBB0_77 s_branch .LBB0_78 .LBB0_76: ; in Loop: Header=BB0_29 Depth=1 .LBB0_77: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[14:15], v24, s[2:3] .LBB0_78: ; %.loopexit.i ; in Loop: Header=BB0_29 Depth=1 v_mov_b32_e32 v23, v20 v_mov_b32_e32 v27, 0 v_mov_b32_e32 v28, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s2, v23 v_cmp_eq_u32_e64 s2, s2, v23 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_84 ; %bb.79: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[18:19], v24, s[8:9] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[16:17], v24, s[8:9] offset:40 global_load_b64 v[27:28], v24, s[8:9] s_mov_b32 s12, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v17, v17, v19 v_and_b32_e32 v16, v16, v18 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v17, v17, 24 v_mul_hi_u32 v29, v16, 24 v_mul_lo_u32 v16, v16, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v17, v29, v17 s_waitcnt vmcnt(0) v_add_co_u32 v16, vcc_lo, v27, v16 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v17, vcc_lo, v28, v17, vcc_lo global_load_b64 v[16:17], v[16:17], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[27:28], v24, v[16:19], s[8:9] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[27:28], v[18:19] s_cbranch_execz .LBB0_83 ; %bb.80: ; %.preheader3.i.i19.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s13, 0 .p2align 6 .LBB0_81: ; %.preheader3.i.i19.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 s_clause 0x1 global_load_b64 v[16:17], v24, s[8:9] offset:40 global_load_b64 v[29:30], v24, s[8:9] v_dual_mov_b32 v18, v27 :: v_dual_mov_b32 v19, v28 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v16, v16, v18 s_waitcnt vmcnt(0) v_mad_u64_u32 v[27:28], null, v16, 24, v[29:30] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v16, v28 :: v_dual_and_b32 v17, v17, v19 v_mad_u64_u32 v[28:29], null, v17, 24, v[16:17] global_load_b64 v[16:17], v[27:28], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[27:28], v24, v[16:19], s[8:9] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[27:28], v[18:19] s_or_b32 s13, vcc_lo, s13 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s13 s_cbranch_execnz .LBB0_81 ; %bb.82: ; %Flow245 ; in Loop: Header=BB0_29 Depth=1 s_or_b32 exec_lo, exec_lo, s13 .LBB0_83: ; %Flow247 ; in Loop: Header=BB0_29 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s12 .LBB0_84: ; %.loopexit4.i.i14.i ; in Loop: Header=BB0_29 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s3 s_clause 0x1 global_load_b64 v[29:30], v24, s[8:9] offset:40 global_load_b128 v[16:19], v24, s[8:9] v_readfirstlane_b32 s12, v27 v_readfirstlane_b32 s13, v28 s_mov_b32 s16, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s14, v29 v_readfirstlane_b32 s15, v30 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[14:15], s[12:13], s[14:15] s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_86 ; %bb.85: ; in Loop: Header=BB0_29 Depth=1 v_dual_mov_b32 v27, s16 :: v_dual_mov_b32 v28, 0 s_mul_i32 s16, s15, 24 s_mul_hi_u32 s17, s14, 24 v_dual_mov_b32 v29, 2 :: v_dual_mov_b32 v30, 1 s_add_i32 s17, s17, s16 s_mul_i32 s16, s14, 24 s_waitcnt vmcnt(0) v_add_co_u32 v31, vcc_lo, v16, s16 v_add_co_ci_u32_e32 v32, vcc_lo, s17, v17, vcc_lo global_store_b128 v[31:32], v[27:30], off offset:8 .LBB0_86: ; in Loop: Header=BB0_29 Depth=1 s_or_b32 exec_lo, exec_lo, s3 v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56 v_or_b32_e32 v27, v1, v26 v_or_b32_e32 v28, v0, v25 s_lshl_b64 s[16:17], s[14:15], 12 s_lshl_b32 s3, s10, 2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_add_i32 s3, s3, 28 v_dual_cndmask_b32 v1, v27, v1 :: v_dual_cndmask_b32 v0, v28, v0 v_lshlrev_b64 v[27:28], 6, v[23:24] s_waitcnt vmcnt(0) v_add_co_u32 v18, vcc_lo, v18, s16 v_add_co_ci_u32_e32 v19, vcc_lo, s17, v19, vcc_lo s_and_b32 s3, s3, 0x1e0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v18, vcc_lo, v18, v27 v_and_or_b32 v0, v0, 0xffffff1f, s3 v_add_co_ci_u32_e32 v19, vcc_lo, v19, v28, vcc_lo s_clause 0x3 global_store_b128 v[18:19], v[0:3], off global_store_b128 v[18:19], v[4:7], off offset:16 global_store_b128 v[18:19], v[8:11], off offset:32 global_store_b128 v[18:19], v[12:15], off offset:48 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_94 ; %bb.87: ; in Loop: Header=BB0_29 Depth=1 s_clause 0x1 global_load_b64 v[8:9], v24, s[8:9] offset:32 glc global_load_b64 v[0:1], v24, s[8:9] offset:40 v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, s13 s_waitcnt vmcnt(0) v_readfirstlane_b32 s16, v0 v_readfirstlane_b32 s17, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[16:17], s[16:17], s[12:13] s_mul_i32 s17, s17, 24 s_mul_hi_u32 s18, s16, 24 s_mul_i32 s16, s16, 24 s_add_i32 s18, s18, s17 v_add_co_u32 v4, vcc_lo, v16, s16 v_add_co_ci_u32_e32 v5, vcc_lo, s18, v17, vcc_lo s_mov_b32 s16, exec_lo global_store_b64 v[4:5], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v24, v[6:9], s[8:9] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[8:9] s_cbranch_execz .LBB0_90 ; %bb.88: ; %.preheader1.i.i17.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s17, 0 .LBB0_89: ; %.preheader1.i.i17.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v24, v[0:3], s[8:9] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s17, vcc_lo, s17 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s17 s_cbranch_execnz .LBB0_89 .LBB0_90: ; %Flow243 ; in Loop: Header=BB0_29 Depth=1 s_or_b32 exec_lo, exec_lo, s16 global_load_b64 v[0:1], v24, s[8:9] offset:16 s_mov_b32 s17, exec_lo s_mov_b32 s16, exec_lo v_mbcnt_lo_u32_b32 v2, s17, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB0_92 ; %bb.91: ; in Loop: Header=BB0_29 Depth=1 s_bcnt1_i32_b32 s17, s17 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s17 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB0_92: ; in Loop: Header=BB0_29 Depth=1 s_or_b32 exec_lo, exec_lo, s16 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB0_94 ; %bb.93: ; in Loop: Header=BB0_29 Depth=1 global_load_b32 v23, v[0:1], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s16, v23 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[23:24], off s_and_b32 m0, s16, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_94: ; %Flow244 ; in Loop: Header=BB0_29 Depth=1 s_or_b32 exec_lo, exec_lo, s3 s_mul_i32 s3, s15, 24 s_mul_hi_u32 s15, s14, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s15, s15, s3 s_mul_i32 s3, s14, 24 v_add_co_u32 v0, vcc_lo, v16, s3 v_add_co_ci_u32_e32 v1, vcc_lo, s15, v17, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_98 .p2align 6 .LBB0_95: ; in Loop: Header=BB0_98 Depth=2 s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s3, v2 s_cmp_eq_u32 s3, 0 s_cbranch_scc1 .LBB0_97 ; %bb.96: ; in Loop: Header=BB0_98 Depth=2 s_sleep 1 s_cbranch_execnz .LBB0_98 s_branch .LBB0_100 .p2align 6 .LBB0_97: ; in Loop: Header=BB0_29 Depth=1 s_branch .LBB0_100 .LBB0_98: ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_95 ; %bb.99: ; in Loop: Header=BB0_98 Depth=2 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_95 .LBB0_100: ; in Loop: Header=BB0_29 Depth=1 global_load_b64 v[0:1], v[18:19], off s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_28 ; %bb.101: ; in Loop: Header=BB0_29 Depth=1 s_clause 0x2 global_load_b64 v[4:5], v24, s[8:9] offset:40 global_load_b64 v[8:9], v24, s[8:9] offset:24 glc global_load_b64 v[6:7], v24, s[8:9] s_waitcnt vmcnt(2) v_add_co_u32 v10, vcc_lo, v4, 1 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, v10, s12 v_add_co_ci_u32_e32 v3, vcc_lo, s13, v11, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10 v_and_b32_e32 v5, v3, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v4, v2, v4 v_mul_hi_u32 v10, v4, 24 v_mul_lo_u32 v4, v4, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v6, vcc_lo, v6, v4 v_mov_b32_e32 v4, v8 v_mul_lo_u32 v5, v5, 24 v_add_nc_u32_e32 v5, v10, v5 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v5, v9 global_store_b64 v[6:7], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v24, v[2:5], s[8:9] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_28 ; %bb.102: ; %.preheader.i.i16.i.preheader ; in Loop: Header=BB0_29 Depth=1 s_mov_b32 s2, 0 .LBB0_103: ; %.preheader.i.i16.i ; Parent Loop BB0_29 Depth=1 ; => This Inner Loop Header: Depth=2 s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v24, v[2:5], s[8:9] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5] v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9 s_or_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB0_103 s_branch .LBB0_28 .LBB0_104: ; implicit-def: $vgpr0_vgpr1 s_cbranch_execnz .LBB0_106 s_branch .LBB0_133 .LBB0_105: ; %Flow283 s_branch .LBB0_133 .LBB0_106: v_mov_b32_e32 v4, v20 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 ;;#ASMSTART ;;#ASMEND s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s2, v4 v_cmp_eq_u32_e64 s2, s2, v4 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_112 ; %bb.107: s_waitcnt vmcnt(0) v_mov_b32_e32 v0, 0 s_mov_b32 s4, exec_lo global_load_b64 v[8:9], v0, s[8:9] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[8:9] offset:40 global_load_b64 v[5:6], v0, s[8:9] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[8:9] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB0_111 ; %bb.108: ; %.preheader3.i.i.i19.preheader s_mov_b32 s5, 0 .p2align 6 .LBB0_109: ; %.preheader3.i.i.i19 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[8:9] offset:40 global_load_b64 v[10:11], v0, s[8:9] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[8:9] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_109 ; %bb.110: ; %Flow295 s_or_b32 exec_lo, exec_lo, s5 .LBB0_111: ; %Flow297 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB0_112: ; %.loopexit4.i.i.i14 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s3 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s4, v6 v_readfirstlane_b32 s5, v7 s_mov_b32 s10, exec_lo s_clause 0x1 global_load_b64 v[8:9], v5, s[8:9] offset:40 global_load_b128 v[0:3], v5, s[8:9] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_114 ; %bb.113: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, 0 s_mul_i32 s10, s7, 24 s_mul_hi_u32 s11, s6, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s11, s11, s10 s_mul_i32 s10, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s10 v_add_co_ci_u32_e32 v11, vcc_lo, s11, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB0_114: s_or_b32 exec_lo, exec_lo, s3 s_lshl_b64 s[10:11], s[6:7], 12 s_mov_b32 s12, 0 s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v2, s10 v_add_co_ci_u32_e32 v7, vcc_lo, s11, v3, vcc_lo v_lshlrev_b64 v[2:3], 6, v[4:5] s_mov_b32 s13, s12 s_mov_b32 s14, s12 s_mov_b32 s15, s12 v_mov_b32_e32 v8, 0 v_and_or_b32 v21, v21, 0xffffff1f, 32 v_add_co_u32 v6, vcc_lo, v6, v2 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo v_dual_mov_b32 v2, s12 :: v_dual_mov_b32 v5, s15 v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, s14 v_mov_b32_e32 v9, v8 s_clause 0x4 global_store_b64 v[6:7], v[21:22], off global_store_b128 v[6:7], v[2:5], off offset:8 global_store_b128 v[6:7], v[2:5], off offset:24 global_store_b128 v[6:7], v[2:5], off offset:40 global_store_b64 v[6:7], v[8:9], off offset:56 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_122 ; %bb.115: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4 v_mov_b32_e32 v12, s5 s_clause 0x1 global_load_b64 v[13:14], v10, s[8:9] offset:32 glc global_load_b64 v[2:3], v10, s[8:9] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s10, v2 v_readfirstlane_b32 s11, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[10:11], s[10:11], s[4:5] s_mul_i32 s11, s11, 24 s_mul_hi_u32 s12, s10, 24 s_mul_i32 s10, s10, 24 s_add_i32 s12, s12, s11 v_add_co_u32 v8, vcc_lo, v0, s10 v_add_co_ci_u32_e32 v9, vcc_lo, s12, v1, vcc_lo s_mov_b32 s10, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[8:9] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[13:14] s_cbranch_execz .LBB0_118 ; %bb.116: ; %.preheader1.i.i.i17.preheader s_mov_b32 s11, 0 .LBB0_117: ; %.preheader1.i.i.i17 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 s_sleep 1 global_store_b64 v[8:9], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[8:9] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s11, vcc_lo, s11 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s11 s_cbranch_execnz .LBB0_117 .LBB0_118: ; %Flow293 s_or_b32 exec_lo, exec_lo, s10 v_mov_b32_e32 v2, 0 s_mov_b32 s11, exec_lo s_mov_b32 s10, exec_lo v_mbcnt_lo_u32_b32 v4, s11, 0 global_load_b64 v[2:3], v2, s[8:9] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB0_120 ; %bb.119: s_bcnt1_i32_b32 s11, s11 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s11 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB0_120: s_or_b32 exec_lo, exec_lo, s10 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB0_122 ; %bb.121: global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s10, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s10, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_122: ; %Flow294 s_or_b32 exec_lo, exec_lo, s3 s_mul_i32 s3, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s3 s_mul_i32 s3, s6, 24 v_add_co_u32 v0, vcc_lo, v0, s3 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_126 .p2align 6 .LBB0_123: ; in Loop: Header=BB0_126 Depth=1 s_or_b32 exec_lo, exec_lo, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s3, v2 s_cmp_eq_u32 s3, 0 s_cbranch_scc1 .LBB0_125 ; %bb.124: ; in Loop: Header=BB0_126 Depth=1 s_sleep 1 s_cbranch_execnz .LBB0_126 s_branch .LBB0_128 .p2align 6 .LBB0_125: s_branch .LBB0_128 .LBB0_126: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_123 ; %bb.127: ; in Loop: Header=BB0_126 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_123 .LBB0_128: global_load_b64 v[0:1], v[6:7], off s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_132 ; %bb.129: v_mov_b32_e32 v8, 0 s_clause 0x2 global_load_b64 v[4:5], v8, s[8:9] offset:40 global_load_b64 v[9:10], v8, s[8:9] offset:24 glc global_load_b64 v[6:7], v8, s[8:9] s_waitcnt vmcnt(2) v_add_co_u32 v11, vcc_lo, v4, 1 v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, v11, s4 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11 v_and_b32_e32 v5, v3, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v4, v2, v4 v_mul_lo_u32 v5, v5, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v11, v4, 24 v_mul_lo_u32 v4, v4, 24 v_add_nc_u32_e32 v5, v11, v5 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, v6, v4 v_mov_b32_e32 v4, v9 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v5, v10 global_store_b64 v[6:7], v[9:10], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[8:9] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_132 ; %bb.130: ; %.preheader.i.i.i16.preheader s_mov_b32 s2, 0 .LBB0_131: ; %.preheader.i.i.i16 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[8:9] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5] v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10 s_or_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s2 s_cbranch_execnz .LBB0_131 .LBB0_132: ; %__ockl_hostcall_preview.exit.i s_or_b32 exec_lo, exec_lo, s3 .LBB0_133: ; %__ockl_printf_append_string_n.exit ;;#ASMSTART ;;#ASMEND v_readfirstlane_b32 s2, v20 v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s2, s2, v20 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_139 ; %bb.134: v_mov_b32_e32 v4, 0 s_mov_b32 s4, exec_lo global_load_b64 v[7:8], v4, s[8:9] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[2:3], v4, s[8:9] offset:40 global_load_b64 v[5:6], v4, s[8:9] s_waitcnt vmcnt(1) v_and_b32_e32 v3, v3, v8 v_and_b32_e32 v2, v2, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v3, v3, 24 v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v5, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, v6, v3, vcc_lo global_load_b64 v[5:6], v[2:3], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[2:3], v4, v[5:8], s[8:9] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[2:3], v[7:8] s_cbranch_execz .LBB0_138 ; %bb.135: ; %.preheader3.i.i.i26.preheader s_mov_b32 s5, 0 .p2align 6 .LBB0_136: ; %.preheader3.i.i.i26 ; =>This Inner Loop Header: Depth=1 s_sleep 1 s_clause 0x1 global_load_b64 v[5:6], v4, s[8:9] offset:40 global_load_b64 v[9:10], v4, s[8:9] v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v5, v5, v7 s_waitcnt vmcnt(0) v_mad_u64_u32 v[2:3], null, v5, 24, v[9:10] v_and_b32_e32 v9, v6, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v9, 24, v[3:4] v_mov_b32_e32 v3, v5 global_load_b64 v[5:6], v[2:3], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[2:3], v4, v[5:8], s[8:9] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[7:8] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_136 ; %bb.137: ; %Flow231 s_or_b32 exec_lo, exec_lo, s5 .LBB0_138: ; %Flow233 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB0_139: ; %.loopexit4.i.i.i20 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s3 s_waitcnt vmcnt(0) v_mov_b32_e32 v21, 0 v_readfirstlane_b32 s10, v2 v_readfirstlane_b32 s11, v3 s_mov_b32 s4, exec_lo s_clause 0x1 global_load_b64 v[8:9], v21, s[8:9] offset:40 global_load_b128 v[4:7], v21, s[8:9] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[12:13], s[10:11], s[6:7] s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_141 ; %bb.140: v_dual_mov_b32 v8, s4 :: v_dual_mov_b32 v9, 0 s_mul_i32 s4, s13, 24 s_mul_hi_u32 s5, s12, 24 v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1 s_add_i32 s5, s5, s4 s_mul_i32 s4, s12, 24 s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v4, s4 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo global_store_b128 v[2:3], v[8:11], off offset:8 .LBB0_141: s_or_b32 exec_lo, exec_lo, s3 s_load_b128 s[4:7], s[0:1], 0x4 s_mov_b32 s0, 0x5c58e20 v_and_or_b32 v0, v0, 0xffffff1d, 34 s_waitcnt lgkmcnt(0) v_div_scale_f32 v2, null, s0, s0, s4 v_div_scale_f32 v3, null, s7, s7, s6 v_div_scale_f32 v12, vcc_lo, s4, 0x5c58e20, s4 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_rcp_f32_e32 v8, v2 v_rcp_f32_e32 v9, v3 s_waitcnt_depctr 0xfff v_fma_f32 v10, -v2, v8, 1.0 v_fma_f32 v11, -v3, v9, 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_fmac_f32 v8, v10, v8 :: v_dual_fmac_f32 v9, v11, v9 v_div_scale_f32 v10, s0, s6, s7, s6 v_mul_f32_e32 v11, v12, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f32_e32 v13, v10, v9 v_fma_f32 v14, -v2, v11, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v15, -v3, v13, v10 v_fmac_f32_e32 v11, v14, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fmac_f32_e32 v13, v15, v9 v_fma_f32 v2, -v2, v11, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v3, -v3, v13, v10 v_div_fmas_f32 v2, v2, v8, v11 s_mov_b32 vcc_lo, s0 s_lshl_b64 s[0:1], s[12:13], 12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_fmas_f32 v3, v3, v9, v13 v_div_fixup_f32 v2, v2, 0x5c58e20, s4 s_mov_b32 s4, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_div_fixup_f32 v3, v3, s7, s6 s_mov_b32 s6, s4 s_mov_b32 s7, s4 v_add_f32_e32 v3, s5, v3 s_mov_b32 s5, s4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f32_e32 v8, 0x3fb8aa3b, v3 v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3 v_fma_f32 v9, v3, 0x3fb8aa3b, -v8 v_rndne_f32_e32 v10, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_fmamk_f32 v9, v3, 0x32a5705f, v9 :: v_dual_sub_f32 v8, v8, v10 v_add_f32_e32 v8, v8, v9 v_cvt_i32_f32_e32 v9, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_exp_f32_e32 v8, v8 s_waitcnt_depctr 0xfff v_ldexp_f32 v8, v8, v9 v_cndmask_b32_e32 v8, 0, v8, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3 s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e32 v3, 0x7f800000, v8, vcc_lo v_lshlrev_b64 v[8:9], 6, v[20:21] s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, v6, s0 v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo v_add_f32_e32 v2, v2, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v10, vcc_lo, v6, v8 v_add_co_ci_u32_e32 v11, vcc_lo, v7, v9, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_cvt_f64_f32_e32 v[2:3], v2 v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v6, s4 v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v7, s5 s_clause 0x3 global_store_b128 v[10:11], v[0:3], off global_store_b128 v[10:11], v[6:9], off offset:16 global_store_b128 v[10:11], v[6:9], off offset:32 global_store_b128 v[10:11], v[6:9], off offset:48 s_and_saveexec_b32 s0, s2 s_cbranch_execz .LBB0_149 ; %bb.142: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s10 v_mov_b32_e32 v10, s11 s_clause 0x1 global_load_b64 v[11:12], v8, s[8:9] offset:32 glc global_load_b64 v[0:1], v8, s[8:9] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s4, v0 v_readfirstlane_b32 s5, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[4:5], s[4:5], s[10:11] s_mul_i32 s1, s5, 24 s_mul_hi_u32 s3, s4, 24 s_mul_i32 s4, s4, 24 s_add_i32 s3, s3, s1 v_add_co_u32 v6, vcc_lo, v4, s4 v_add_co_ci_u32_e32 v7, vcc_lo, s3, v5, vcc_lo s_mov_b32 s1, exec_lo global_store_b64 v[6:7], v[11:12], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[8:9] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[11:12] s_cbranch_execz .LBB0_145 ; %bb.143: ; %.preheader1.i.i.i24.preheader s_mov_b32 s3, 0 .LBB0_144: ; %.preheader1.i.i.i24 ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11 s_sleep 1 global_store_b64 v[6:7], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[8:9] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s3, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB0_144 .LBB0_145: ; %Flow229 s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v0, 0 s_mov_b32 s3, exec_lo s_mov_b32 s1, exec_lo v_mbcnt_lo_u32_b32 v2, s3, 0 global_load_b64 v[0:1], v0, s[8:9] offset:16 v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB0_147 ; %bb.146: s_bcnt1_i32_b32 s3, s3 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s3 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB0_147: s_or_b32 exec_lo, exec_lo, s1 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB0_149 ; %bb.148: global_load_b32 v0, v[0:1], off offset:24 v_mov_b32_e32 v1, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s1, v0 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[0:1], off s_and_b32 m0, s1, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_149: ; %Flow230 s_or_b32 exec_lo, exec_lo, s0 s_mul_i32 s0, s13, 24 s_mul_hi_u32 s1, s12, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s1, s1, s0 s_mul_i32 s0, s12, 24 v_add_co_u32 v0, vcc_lo, v4, s0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_153 .p2align 6 .LBB0_150: ; in Loop: Header=BB0_153 Depth=1 s_or_b32 exec_lo, exec_lo, s0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v2 s_cmp_eq_u32 s0, 0 s_cbranch_scc1 .LBB0_152 ; %bb.151: ; in Loop: Header=BB0_153 Depth=1 s_sleep 1 s_cbranch_execnz .LBB0_153 s_branch .LBB0_155 .p2align 6 .LBB0_152: s_branch .LBB0_155 .LBB0_153: ; =>This Inner Loop Header: Depth=1 v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s0, s2 s_cbranch_execz .LBB0_150 ; %bb.154: ; in Loop: Header=BB0_153 Depth=1 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_150 .LBB0_155: s_and_saveexec_b32 s0, s2 s_cbranch_execz .LBB0_159 ; %bb.156: v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[8:9] offset:40 global_load_b64 v[7:8], v6, s[8:9] offset:24 glc global_load_b64 v[4:5], v6, s[8:9] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s10 v_add_co_ci_u32_e32 v1, vcc_lo, s11, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[8:9] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_159 ; %bb.157: ; %.preheader.i.i.i23.preheader s_mov_b32 s0, 0 .LBB0_158: ; %.preheader.i.i.i23 ; =>This Inner Loop Header: Depth=1 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[8:9] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_158 .LBB0_159: ; %__ockl_printf_append_args.exit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z7computeffffffffff .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 33 .amdhsa_next_free_sgpr 20 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z7computeffffffffff, .Lfunc_end0-_Z7computeffffffffff ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 6968 ; NumSgprs: 22 ; NumVgprs: 33 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 4 ; NumSGPRsForWavesPerEU: 22 ; NumVGPRsForWavesPerEU: 33 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type .str,@object ; @.str .section .rodata.str1.1,"aMS",@progbits,1 .str: .asciz "%.17g\n" .size .str, 7 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims - .offset: 120 .size: 8 .value_kind: hidden_hostcall_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z7computeffffffffff .private_segment_fixed_size: 0 .sgpr_count: 22 .sgpr_spill_count: 0 .symbol: _Z7computeffffffffff.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 33 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "382416efd2abb46e8b8b611957842fb3e5795a37.hip" .globl _Z22__device_stub__computeffffffffff # -- Begin function _Z22__device_stub__computeffffffffff .p2align 4, 0x90 .type _Z22__device_stub__computeffffffffff,@function _Z22__device_stub__computeffffffffff: # @_Z22__device_stub__computeffffffffff .cfi_startproc # %bb.0: subq $168, %rsp .cfi_def_cfa_offset 176 movss %xmm0, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm2, 20(%rsp) movss %xmm3, 16(%rsp) movss %xmm4, 12(%rsp) movss %xmm5, 8(%rsp) movss %xmm6, 4(%rsp) movss %xmm7, (%rsp) leaq 28(%rsp), %rax movq %rax, 80(%rsp) leaq 24(%rsp), %rax movq %rax, 88(%rsp) leaq 20(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movq %rsp, %rax movq %rax, 136(%rsp) leaq 176(%rsp), %rax movq %rax, 144(%rsp) leaq 184(%rsp), %rax movq %rax, 152(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7computeffffffffff, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $184, %rsp .cfi_adjust_cfa_offset -184 retq .Lfunc_end0: .size _Z22__device_stub__computeffffffffff, .Lfunc_end0-_Z22__device_stub__computeffffffffff .cfi_endproc # -- End function .globl _Z11initPointerf # -- Begin function _Z11initPointerf .p2align 4, 0x90 .type _Z11initPointerf,@function _Z11initPointerf: # @_Z11initPointerf .cfi_startproc # %bb.0: pushq %rax .cfi_def_cfa_offset 16 movss %xmm0, 4(%rsp) # 4-byte Spill movl $40, %edi callq malloc movss 4(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movss %xmm0, (%rax,%rcx,4) incq %rcx cmpq $10, %rcx jne .LBB1_1 # %bb.2: popq %rcx .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $256, %rsp # imm = 0x100 .cfi_def_cfa_offset 272 .cfi_offset %rbx, -16 movq %rsi, %rbx movq 8(%rsi), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 120(%rsp) # 8-byte Spill movq 16(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 112(%rsp) # 8-byte Spill movq 24(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 104(%rsp) # 8-byte Spill movq 32(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 96(%rsp) # 8-byte Spill movq 40(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 88(%rsp) # 8-byte Spill movq 48(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 80(%rsp) # 8-byte Spill movq 56(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 72(%rsp) # 8-byte Spill movq 64(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 64(%rsp) # 8-byte Spill movq 72(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 56(%rsp) # 8-byte Spill movq 80(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 48(%rsp) # 8-byte Spill movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: movsd 48(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movsd 56(%rsp), %xmm1 # 8-byte Reload # xmm1 = mem[0],zero cvtsd2ss %xmm1, %xmm1 movsd 64(%rsp), %xmm2 # 8-byte Reload # xmm2 = mem[0],zero cvtsd2ss %xmm2, %xmm2 movsd 72(%rsp), %xmm3 # 8-byte Reload # xmm3 = mem[0],zero cvtsd2ss %xmm3, %xmm3 movsd 80(%rsp), %xmm4 # 8-byte Reload # xmm4 = mem[0],zero cvtsd2ss %xmm4, %xmm4 movsd 88(%rsp), %xmm5 # 8-byte Reload # xmm5 = mem[0],zero cvtsd2ss %xmm5, %xmm5 movsd 96(%rsp), %xmm6 # 8-byte Reload # xmm6 = mem[0],zero cvtsd2ss %xmm6, %xmm6 movsd 104(%rsp), %xmm7 # 8-byte Reload # xmm7 = mem[0],zero cvtsd2ss %xmm7, %xmm7 movsd 112(%rsp), %xmm8 # 8-byte Reload # xmm8 = mem[0],zero cvtsd2ss %xmm8, %xmm8 movsd 120(%rsp), %xmm9 # 8-byte Reload # xmm9 = mem[0],zero cvtsd2ss %xmm9, %xmm9 movss %xmm9, 44(%rsp) movss %xmm8, 40(%rsp) movss %xmm7, 36(%rsp) movss %xmm6, 32(%rsp) movss %xmm5, 28(%rsp) movss %xmm4, 24(%rsp) movss %xmm3, 20(%rsp) movss %xmm2, 16(%rsp) movss %xmm1, 12(%rsp) movss %xmm0, 8(%rsp) leaq 44(%rsp), %rax movq %rax, 176(%rsp) leaq 40(%rsp), %rax movq %rax, 184(%rsp) leaq 36(%rsp), %rax movq %rax, 192(%rsp) leaq 32(%rsp), %rax movq %rax, 200(%rsp) leaq 28(%rsp), %rax movq %rax, 208(%rsp) leaq 24(%rsp), %rax movq %rax, 216(%rsp) leaq 20(%rsp), %rax movq %rax, 224(%rsp) leaq 16(%rsp), %rax movq %rax, 232(%rsp) leaq 12(%rsp), %rax movq %rax, 240(%rsp) leaq 8(%rsp), %rax movq %rax, 248(%rsp) leaq 160(%rsp), %rdi leaq 144(%rsp), %rsi leaq 136(%rsp), %rdx leaq 128(%rsp), %rcx callq __hipPopCallConfiguration movq 160(%rsp), %rsi movl 168(%rsp), %edx movq 144(%rsp), %rcx movl 152(%rsp), %r8d leaq 176(%rsp), %r9 movl $_Z7computeffffffffff, %edi pushq 128(%rsp) .cfi_adjust_cfa_offset 8 pushq 144(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_2: callq hipDeviceSynchronize xorl %eax, %eax addq $256, %rsp # imm = 0x100 .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7computeffffffffff, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z7computeffffffffff,@object # @_Z7computeffffffffff .section .rodata,"a",@progbits .globl _Z7computeffffffffff .p2align 3, 0x0 _Z7computeffffffffff: .quad _Z22__device_stub__computeffffffffff .size _Z7computeffffffffff, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z7computeffffffffff" .size .L__unnamed_1, 21 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__computeffffffffff .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7computeffffffffff .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
4,996
3,424
30,117
4,117
192
code for sm_80 Function : _Z4cubePfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R4, SR_TID.X ; HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; LDG.E R2, [R2.64] ; IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; FMUL R7, R2, R2 ; FMUL R7, R2, R7 ; STG.E [R4.64], R7 ; EXIT ; BRA 0xb0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0000ad68_00000000-6_1572bfa564a3cabc2ccf5abb3145708f83dd165a.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z25__device_stub__Z4cubePfS_PfS_ .type _Z25__device_stub__Z4cubePfS_PfS_, @function _Z25__device_stub__Z4cubePfS_PfS_: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z4cubePfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z25__device_stub__Z4cubePfS_PfS_, .-_Z25__device_stub__Z4cubePfS_PfS_ .globl _Z4cubePfS_ .type _Z4cubePfS_, @function _Z4cubePfS_: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z25__device_stub__Z4cubePfS_PfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z4cubePfS_, .-_Z4cubePfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "\t" .LC1: .string "\n" .LC2: .string "%f" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $832, %rsp .cfi_def_cfa_offset 880 movq %fs:40, %rax movq %rax, 824(%rsp) xorl %eax, %eax .L12: pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 movss %xmm0, 48(%rsp,%rax,4) addq $1, %rax cmpq $96, %rax jne .L12 leaq 8(%rsp), %rdi movl $384, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $384, %esi call cudaMalloc@PLT leaq 48(%rsp), %rsi movl $1, %ecx movl $384, %edx movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $96, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $0, %r9d movl $0, %r8d movq 36(%rsp), %rdx movl $1, %ecx movq 24(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L21 .L13: leaq 432(%rsp), %rdi movl $2, %ecx movl $384, %edx movq 16(%rsp), %rsi call cudaMemcpy@PLT movl $0, %ebx leaq 432(%rsp), %r14 leaq .LC2(%rip), %r13 leaq .LC1(%rip), %r12 leaq .LC0(%rip), %rbp .L15: pxor %xmm0, %xmm0 cvtss2sd (%r14,%rbx,4), %xmm0 movq %r13, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl %ebx, %edx sarl $31, %edx shrl $30, %edx leal (%rdx,%rbx), %eax andl $3, %eax subl %edx, %eax cmpl $3, %eax movq %rbp, %rsi cmove %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $1, %rbx cmpq $96, %rbx jne .L15 movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 824(%rsp), %rax subq %fs:40, %rax jne .L22 movl $0, %eax addq $832, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L21: .cfi_restore_state movq 8(%rsp), %rsi movq 16(%rsp), %rdi call _Z25__device_stub__Z4cubePfS_PfS_ jmp .L13 .L22: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z4cubePfS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _Z4cubePfS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z4cubePfS_ ; -- Begin function _Z4cubePfS_ .globl _Z4cubePfS_ .p2align 8 .type _Z4cubePfS_,@function _Z4cubePfS_: ; @_Z4cubePfS_ ; %bb.0: s_load_b128 s[0:3], s[0:1], 0x0 v_lshlrev_b32_e32 v0, 2, v0 s_waitcnt lgkmcnt(0) global_load_b32 v1, v0, s[2:3] s_waitcnt vmcnt(0) v_mul_f32_e32 v2, v1, v1 s_delay_alu instid0(VALU_DEP_1) v_mul_f32_e32 v1, v1, v2 global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z4cubePfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 4 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z4cubePfS_, .Lfunc_end0-_Z4cubePfS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 60 ; NumSgprs: 4 ; NumVgprs: 3 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 4 ; NumVGPRsForWavesPerEU: 3 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z4cubePfS_ .private_segment_fixed_size: 0 .sgpr_count: 4 .sgpr_spill_count: 0 .symbol: _Z4cubePfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "1572bfa564a3cabc2ccf5abb3145708f83dd165a.hip" .globl _Z19__device_stub__cubePfS_ # -- Begin function _Z19__device_stub__cubePfS_ .p2align 4, 0x90 .type _Z19__device_stub__cubePfS_,@function _Z19__device_stub__cubePfS_: # @_Z19__device_stub__cubePfS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z4cubePfS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z19__device_stub__cubePfS_, .Lfunc_end0-_Z19__device_stub__cubePfS_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $856, %rsp # imm = 0x358 .cfi_def_cfa_offset 880 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 movss %xmm0, 464(%rsp,%rax,4) incq %rax cmpq $96, %rax jne .LBB1_1 # %bb.2: leaq 8(%rsp), %rdi movl $384, %esi # imm = 0x180 callq hipMalloc movq %rsp, %rdi movl $384, %esi # imm = 0x180 callq hipMalloc movq 8(%rsp), %rdi leaq 464(%rsp), %rsi movl $384, %edx # imm = 0x180 movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 95(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq (%rsp), %rax movq 8(%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z4cubePfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: movq (%rsp), %rsi leaq 80(%rsp), %rdi movl $384, %edx # imm = 0x180 movl $2, %ecx callq hipMemcpy movl $.L.str.2, %ebx xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 movss 80(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str, %edi movb $1, %al callq printf movl %r14d, %eax notl %eax testb $3, %al movl $.L.str.1, %edi cmoveq %rbx, %rdi xorl %eax, %eax callq printf incq %r14 cmpq $96, %r14 jne .LBB1_5 # %bb.6: movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree xorl %eax, %eax addq $856, %rsp # imm = 0x358 .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z4cubePfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z4cubePfS_,@object # @_Z4cubePfS_ .section .rodata,"a",@progbits .globl _Z4cubePfS_ .p2align 3, 0x0 _Z4cubePfS_: .quad _Z19__device_stub__cubePfS_ .size _Z4cubePfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%f" .size .L.str, 3 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "\t" .size .L.str.1, 2 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "\n" .size .L.str.2, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z4cubePfS_" .size .L__unnamed_1, 12 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z19__device_stub__cubePfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z4cubePfS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
392
3,057
1,707
3,053
193
code for sm_80 Function : default_function_kernel0 .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" MOV R1, c[0x0][0x28] ; S2R R3, SR_TID.X ; HFMA2.MMA R48, -RZ, RZ, 0, 0 ; MOV R41, RZ ; HFMA2.MMA R17, -RZ, RZ, 0, 0 ; S2R R2, SR_CTAID.X ; HFMA2.MMA R45, -RZ, RZ, 0, 0 ; MOV R7, RZ ; HFMA2.MMA R53, -RZ, RZ, 0, 0 ; MOV R5, RZ ; HFMA2.MMA R43, -RZ, RZ, 0, 0 ; MOV R47, RZ ; ULDC.64 UR6, c[0x0][0x118] ; SHF.L.U32 R51, R3, 0x1, RZ ; SHF.L.U32 R50, R3, 0x3, RZ ; LEA R49, R2, R51, 0xf ; LEA R9, R48, R51, 0x6 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; MOV R0, 0x4 ; IMAD.WIDE R8, R9, R0.reuse, c[0x0][0x160] ; LEA R35, R48, R49, 0x6 ; UMOV UR4, 0x400 ; ULDC.64 UR8, c[0x0][0x168] ; LDG.E.CONSTANT R10, [R8.64] ; LDG.E.CONSTANT R11, [R8.64+0x4] ; LDG.E.CONSTANT R12, [R8.64+0x800] ; LDG.E.CONSTANT R13, [R8.64+0x804] ; LDG.E.CONSTANT R14, [R8.64+0x1000] ; LDG.E.CONSTANT R15, [R8.64+0x1004] ; LDG.E.CONSTANT R18, [R8.64+0x1800] ; LDG.E.CONSTANT R19, [R8.64+0x1804] ; IMAD.WIDE R34, R35, R0, c[0x2][0x0] ; STS.64 [R3.X8], R10 ; STS.64 [R3.X8+0x100], R12 ; STS.64 [R3.X8+0x200], R14 ; STS.64 [R3.X8+0x300], R18 ; IADD3 R36, P0, R34, UR8, RZ ; IADD3.X R37, R35, UR9, RZ, P0, !PT ; LDG.E.CONSTANT R10, [R36.64+-0x4] ; LDG.E.CONSTANT R11, [R36.64] ; LDG.E.CONSTANT R12, [R36.64+0x7fc] ; LDG.E.CONSTANT R13, [R36.64+0x800] ; LDG.E.CONSTANT R14, [R36.64+0xffc] ; LDG.E.CONSTANT R15, [R36.64+0x1000] ; LDG.E.CONSTANT R18, [R36.64+0x17fc] ; LDG.E.CONSTANT R19, [R36.64+0x1800] ; LDG.E.CONSTANT R20, [R36.64+0x1ffc] ; LDG.E.CONSTANT R21, [R36.64+0x2000] ; LDG.E.CONSTANT R22, [R36.64+0x27fc] ; LDG.E.CONSTANT R23, [R36.64+0x2800] ; LDG.E.CONSTANT R24, [R36.64+0x2ffc] ; LDG.E.CONSTANT R25, [R36.64+0x3000] ; LDG.E.CONSTANT R26, [R36.64+0x37fc] ; LDG.E.CONSTANT R27, [R36.64+0x3800] ; LDG.E.CONSTANT R28, [R36.64+0x3ffc] ; LDG.E.CONSTANT R29, [R36.64+0x4000] ; LDG.E.CONSTANT R8, [R36.64+0x47fc] ; LDG.E.CONSTANT R9, [R36.64+0x4800] ; LDG.E.CONSTANT R30, [R36.64+0x97fc] ; LDG.E.CONSTANT R31, [R36.64+0x9800] ; LDG.E.CONSTANT R32, [R36.64+0xf7fc] ; LDG.E.CONSTANT R33, [R36.64+0xf800] ; STS.64 [R50+UR4], R10 ; STS.64 [R50+UR4+0x100], R12 ; LDG.E.CONSTANT R10, [R36.64+0x4ffc] ; STS.64 [R50+UR4+0x200], R14 ; LDG.E.CONSTANT R11, [R36.64+0x5000] ; STS.64 [R50+UR4+0x300], R18 ; LDG.E.CONSTANT R12, [R36.64+0x57fc] ; STS.64 [R50+UR4+0x400], R20 ; LDG.E.CONSTANT R13, [R36.64+0x5800] ; STS.64 [R50+UR4+0x500], R22 ; LDG.E.CONSTANT R14, [R36.64+0x5ffc] ; STS.64 [R50+UR4+0x600], R24 ; LDG.E.CONSTANT R15, [R36.64+0x6000] ; STS.64 [R50+UR4+0x700], R26 ; LDG.E.CONSTANT R18, [R36.64+0x67fc] ; STS.64 [R50+UR4+0x800], R28 ; LDG.E.CONSTANT R19, [R36.64+0x6800] ; LDG.E.CONSTANT R20, [R36.64+0x6ffc] ; LDG.E.CONSTANT R21, [R36.64+0x7000] ; LDG.E.CONSTANT R22, [R36.64+0x77fc] ; LDG.E.CONSTANT R23, [R36.64+0x7800] ; LDG.E.CONSTANT R24, [R36.64+0x7ffc] ; LDG.E.CONSTANT R25, [R36.64+0x8000] ; LDG.E.CONSTANT R26, [R36.64+0x87fc] ; LDG.E.CONSTANT R27, [R36.64+0x8800] ; LDG.E.CONSTANT R28, [R36.64+0x8ffc] ; LDG.E.CONSTANT R29, [R36.64+0x9000] ; STS.64 [R50+UR4+0x900], R8 ; STS.64 [R50+UR4+0x1300], R30 ; LDG.E.CONSTANT R8, [R36.64+0x9ffc] ; LDG.E.CONSTANT R9, [R36.64+0xa000] ; LDG.E.CONSTANT R30, [R36.64+0xeffc] ; LDG.E.CONSTANT R31, [R36.64+0xf000] ; STS.64 [R50+UR4+0xa00], R10 ; LDG.E.CONSTANT R10, [R36.64+0xa7fc] ; STS.64 [R50+UR4+0xb00], R12 ; LDG.E.CONSTANT R11, [R36.64+0xa800] ; LDG.E.CONSTANT R12, [R36.64+0xaffc] ; STS.64 [R50+UR4+0xc00], R14 ; LDG.E.CONSTANT R13, [R36.64+0xb000] ; LDG.E.CONSTANT R14, [R36.64+0xb7fc] ; STS.64 [R50+UR4+0xd00], R18 ; LDG.E.CONSTANT R15, [R36.64+0xb800] ; STS.64 [R50+UR4+0xe00], R20 ; LDG.E.CONSTANT R18, [R36.64+0xbffc] ; STS.64 [R50+UR4+0xf00], R22 ; LDG.E.CONSTANT R19, [R36.64+0xc000] ; STS.64 [R50+UR4+0x1000], R24 ; LDG.E.CONSTANT R20, [R36.64+0xc7fc] ; STS.64 [R50+UR4+0x1100], R26 ; LDG.E.CONSTANT R21, [R36.64+0xc800] ; STS.64 [R50+UR4+0x1200], R28 ; LDG.E.CONSTANT R22, [R36.64+0xcffc] ; LDG.E.CONSTANT R23, [R36.64+0xd000] ; LDG.E.CONSTANT R24, [R36.64+0xd7fc] ; LDG.E.CONSTANT R25, [R36.64+0xd800] ; LDG.E.CONSTANT R26, [R36.64+0xdffc] ; LDG.E.CONSTANT R27, [R36.64+0xe000] ; LDG.E.CONSTANT R28, [R36.64+0xe7fc] ; LDG.E.CONSTANT R29, [R36.64+0xe800] ; STS.64 [R50+UR4+0x1400], R8 ; STS.64 [R50+UR4+0x1e00], R30 ; STS.64 [R50+UR4+0x1f00], R32 ; UIADD3 UR8, UP1, UR8, 0x10000, URZ ; UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; STS.64 [R50+UR4+0x1500], R10 ; STS.64 [R50+UR4+0x1600], R12 ; STS.64 [R50+UR4+0x1700], R14 ; STS.64 [R50+UR4+0x1800], R18 ; STS.64 [R50+UR4+0x1900], R20 ; STS.64 [R50+UR4+0x1a00], R22 ; STS.64 [R50+UR4+0x1b00], R24 ; STS.64 [R50+UR4+0x1c00], R26 ; STS.64 [R50+UR4+0x1d00], R28 ; UIADD3 UR4, UR4, 0x2000, URZ ; UISETP.NE.AND UP0, UPT, UR4, 0x4400, UPT ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; @P0 BRA 0x240 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; SHF.L.U32 R52, R3, 0x9, RZ ; IADD3 R48, R48, 0x1, RZ ; ISETP.GE.U32.AND P0, PT, R48, 0x8, PT ; LDS.128 R28, [R52+0x400] ; LDS.128 R8, [RZ] ; LDS.128 R20, [R52+0x500] ; LDS.128 R36, [0x100] ; LDS.128 R12, [0x200] ; LDS.128 R32, [0x300] ; LDS.128 R24, [R52+0x410] ; FFMA R4, R28, R8, R17 ; FFMA R8, R8, R20, R41 ; FFMA R6, R28, R36.reuse, R7 ; FFMA R36, R20, R36, R45 ; FFMA R7, R29, R9, R4 ; FFMA R9, R9, R21, R8 ; FFMA R17, R29, R37, R6 ; FFMA R37, R21, R37, R36 ; FFMA R8, R30, R10, R7 ; FFMA R36, R10, R22, R9 ; FFMA R10, R30, R38, R17 ; FFMA R40, R28, R12.reuse, R5 ; LDS.128 R16, [0x10] ; FFMA R12, R20, R12, R53 ; FFMA R28, R28, R32.reuse, R47 ; LDS.128 R4, [R52+0x510] ; FFMA R20, R20, R32, R43 ; FFMA R38, R22, R38, R37 ; FFMA R43, R31, R11, R8 ; FFMA R47, R11, R23, R36 ; FFMA R41, R31, R39, R10 ; FFMA R37, R29, R13.reuse, R40 ; LDS.128 R8, [0x110] ; FFMA R13, R21, R13, R12 ; FFMA R12, R30, R14, R37 ; FFMA R45, R23, R39, R38 ; FFMA R29, R29, R33.reuse, R28 ; LDS.128 R36, [0x210] ; FFMA R21, R21, R33, R20 ; FFMA R14, R22, R14, R13 ; FFMA R30, R30, R34.reuse, R29 ; FFMA R22, R22, R34, R21 ; FFMA R21, R31, R15.reuse, R12 ; FFMA R29, R23, R15, R14 ; LDS.128 R12, [0x310] ; FFMA R31, R31, R35, R30 ; FFMA R20, R24, R16, R43 ; FFMA R23, R23, R35, R22 ; FFMA R16, R16, R4, R47 ; FFMA R33, R25, R17, R20 ; FFMA R17, R17, R5, R16 ; FFMA R20, R26, R18, R33 ; FFMA R18, R18, R6, R17 ; LDS.128 R32, [0x120] ; FFMA R16, R24, R8.reuse, R41 ; FFMA R8, R4, R8, R45 ; FFMA R17, R25, R9.reuse, R16 ; FFMA R9, R5, R9, R8 ; FFMA R16, R24, R36, R21 ; FFMA R36, R4, R36, R29 ; FFMA R8, R26, R10.reuse, R17 ; FFMA R10, R6, R10, R9 ; FFMA R9, R25, R37, R16 ; FFMA R41, R27, R19, R20 ; FFMA R43, R19, R7, R18 ; FFMA R37, R5, R37, R36 ; LDS.128 R16, [0x20] ; FFMA R24, R24, R12.reuse, R31 ; FFMA R12, R4, R12, R23 ; LDS.128 R28, [R52+0x420] ; FFMA R4, R26, R38.reuse, R9 ; FFMA R38, R6, R38, R37 ; LDS.128 R20, [R52+0x520] ; FFMA R9, R25, R13, R24 ; FFMA R37, R5, R13, R12 ; FFMA R25, R27, R11.reuse, R8 ; FFMA R45, R7, R11, R10 ; FFMA R26, R26, R14, R9 ; FFMA R13, R27, R39.reuse, R4 ; LDS.128 R8, [0x220] ; FFMA R5, R7, R39, R38 ; FFMA R6, R6, R14, R37 ; LDS.128 R36, [0x320] ; FFMA R27, R27, R15.reuse, R26 ; FFMA R7, R7, R15, R6 ; FFMA R4, R28.reuse, R16, R41 ; FFMA R6, R28, R32, R25 ; FFMA R16, R16, R20, R43 ; FFMA R32, R20, R32, R45 ; FFMA R15, R29, R17, R4 ; FFMA R17, R17, R21, R16 ; FFMA R25, R29, R33.reuse, R6 ; FFMA R33, R21, R33, R32 ; FFMA R40, R30, R18, R15 ; FFMA R32, R18, R22, R17 ; FFMA R16, R28, R8, R13 ; FFMA R18, R30, R34, R25 ; LDS.128 R12, [0x30] ; FFMA R8, R20, R8, R5 ; FFMA R28, R28, R36.reuse, R27 ; FFMA R20, R20, R36, R7 ; LDS.128 R24, [R52+0x430] ; FFMA R34, R22, R34, R33 ; FFMA R45, R31, R19, R40 ; LDS.128 R4, [R52+0x530] ; FFMA R47, R19, R23, R32 ; FFMA R41, R31, R35, R18 ; FFMA R33, R29, R9.reuse, R16 ; LDS.128 R16, [0x130] ; FFMA R9, R21, R9, R8 ; FFMA R43, R23, R35, R34 ; FFMA R8, R30, R10.reuse, R33 ; LDS.128 R32, [0x230] ; FFMA R29, R29, R37.reuse, R28 ; FFMA R21, R21, R37, R20 ; FFMA R10, R22, R10, R9 ; FFMA R30, R30, R38.reuse, R29 ; FFMA R22, R22, R38, R21 ; FFMA R21, R31, R11.reuse, R8 ; FFMA R29, R23, R11, R10 ; LDS.128 R8, [0x330] ; FFMA R31, R31, R39.reuse, R30 ; FFMA R23, R23, R39, R22 ; FFMA R20, R24, R12, R45 ; FFMA R12, R12, R4, R47 ; FFMA R37, R25, R13, R20 ; FFMA R13, R13, R5, R12 ; FFMA R20, R26, R14, R37 ; FFMA R12, R24, R16, R41 ; LDS.128 R36, [0x140] ; FFMA R14, R14, R6, R13 ; FFMA R16, R4, R16, R43 ; FFMA R13, R25, R17.reuse, R12 ; FFMA R12, R24, R32, R21 ; FFMA R17, R5, R17, R16 ; FFMA R16, R26, R18, R13 ; FFMA R13, R25, R33, R12 ; FFMA R32, R4, R32, R29 ; FFMA R41, R27, R15, R20 ; FFMA R43, R15, R7, R14 ; FFMA R24, R24, R8.reuse, R31 ; FFMA R8, R4, R8, R23 ; LDS.128 R28, [R52+0x440] ; FFMA R33, R5, R33, R32 ; FFMA R4, R26, R34, R13 ; LDS.128 R20, [R52+0x540] ; FFMA R18, R6, R18, R17 ; FFMA R34, R6, R34, R33 ; LDS.128 R12, [0x40] ; FFMA R17, R25, R9.reuse, R24 ; FFMA R33, R5, R9, R8 ; FFMA R25, R27, R19.reuse, R16 ; FFMA R45, R7, R19, R18 ; FFMA R26, R26, R10, R17 ; FFMA R9, R27, R35.reuse, R4 ; LDS.128 R16, [0x240] ; FFMA R5, R7, R35, R34 ; FFMA R6, R6, R10, R33 ; LDS.128 R32, [0x340] ; FFMA R27, R27, R11.reuse, R26 ; FFMA R7, R7, R11, R6 ; FFMA R6, R28, R36, R25 ; FFMA R36, R20, R36, R45 ; FFMA R25, R29.reuse, R37, R6 ; FFMA R4, R28, R12, R41 ; FFMA R12, R12, R20, R43 ; FFMA R11, R29, R13, R4 ; FFMA R13, R13, R21, R12 ; FFMA R37, R21, R37, R36 ; FFMA R40, R30, R14, R11 ; FFMA R36, R14, R22, R13 ; FFMA R12, R28, R16, R9 ; FFMA R14, R30, R38, R25 ; LDS.128 R8, [0x50] ; FFMA R16, R20, R16, R5 ; FFMA R28, R28, R32.reuse, R27 ; FFMA R20, R20, R32, R7 ; LDS.128 R24, [R52+0x450] ; FFMA R38, R22, R38, R37 ; FFMA R45, R31, R15, R40 ; LDS.128 R4, [R52+0x550] ; FFMA R47, R15, R23, R36 ; FFMA R41, R31, R39, R14 ; FFMA R37, R29, R17.reuse, R12 ; LDS.128 R12, [0x150] ; FFMA R17, R21, R17, R16 ; FFMA R43, R23, R39, R38 ; FFMA R16, R30, R18, R37 ; LDS.128 R36, [0x250] ; FFMA R29, R29, R33, R28 ; FFMA R21, R21, R33, R20 ; FFMA R18, R22, R18, R17 ; FFMA R30, R30, R34.reuse, R29 ; FFMA R22, R22, R34, R21 ; FFMA R21, R31, R19.reuse, R16 ; FFMA R29, R23, R19, R18 ; LDS.128 R16, [0x350] ; FFMA R31, R31, R35.reuse, R30 ; FFMA R23, R23, R35, R22 ; FFMA R20, R24, R8, R45 ; FFMA R8, R8, R4, R47 ; FFMA R33, R25, R9, R20 ; FFMA R9, R9, R5, R8 ; FFMA R20, R26, R10, R33 ; FFMA R8, R24, R12, R41 ; LDS.128 R32, [0x160] ; FFMA R10, R10, R6, R9 ; FFMA R12, R4, R12, R43 ; FFMA R9, R25, R13, R8 ; FFMA R8, R24, R36, R21 ; FFMA R13, R5, R13, R12 ; FFMA R12, R26, R14, R9 ; FFMA R9, R25, R37, R8 ; FFMA R36, R4, R36, R29 ; FFMA R41, R27, R11, R20 ; FFMA R43, R11, R7, R10 ; FFMA R24, R24, R16.reuse, R31 ; FFMA R16, R4, R16, R23 ; LDS.128 R28, [R52+0x460] ; FFMA R37, R5, R37, R36 ; FFMA R4, R26, R38, R9 ; LDS.128 R20, [R52+0x560] ; FFMA R14, R6.reuse, R14, R13 ; FFMA R38, R6, R38, R37 ; LDS.128 R8, [0x60] ; FFMA R13, R25, R17, R24 ; FFMA R37, R5, R17, R16 ; FFMA R25, R27, R15.reuse, R12 ; FFMA R45, R7, R15, R14 ; FFMA R26, R26, R18, R13 ; FFMA R17, R27, R39.reuse, R4 ; LDS.128 R12, [0x260] ; FFMA R5, R7, R39, R38 ; FFMA R6, R6, R18, R37 ; LDS.128 R36, [0x360] ; FFMA R27, R27, R19.reuse, R26 ; FFMA R7, R7, R19, R6 ; FFMA R6, R28, R32.reuse, R25 ; FFMA R32, R20, R32, R45 ; FFMA R25, R29, R33, R6 ; FFMA R4, R28, R8, R41 ; FFMA R8, R8, R20, R43 ; FFMA R19, R29, R9, R4 ; FFMA R9, R9, R21, R8 ; FFMA R33, R21, R33, R32 ; FFMA R40, R30, R10, R19 ; FFMA R32, R10, R22, R9 ; FFMA R8, R28, R12, R17 ; FFMA R10, R30, R34, R25 ; LDS.128 R16, [0x70] ; FFMA R12, R20, R12, R5 ; FFMA R28, R28, R36.reuse, R27 ; FFMA R20, R20, R36, R7 ; LDS.128 R24, [R52+0x470] ; FFMA R34, R22, R34, R33 ; FFMA R45, R31, R11, R40 ; LDS.128 R4, [R52+0x570] ; FFMA R47, R11, R23, R32 ; FFMA R41, R31, R35, R10 ; FFMA R33, R29, R13.reuse, R8 ; LDS.128 R8, [0x170] ; FFMA R13, R21, R13, R12 ; FFMA R12, R30, R14, R33 ; FFMA R43, R23, R35, R34 ; FFMA R29, R29, R37.reuse, R28 ; LDS.128 R32, [0x270] ; FFMA R21, R21, R37, R20 ; FFMA R14, R22, R14, R13 ; FFMA R30, R30, R38.reuse, R29 ; FFMA R22, R22, R38, R21 ; FFMA R21, R31, R15.reuse, R12 ; FFMA R29, R23, R15, R14 ; LDS.128 R12, [0x370] ; FFMA R31, R31, R39.reuse, R30 ; FFMA R23, R23, R39, R22 ; FFMA R20, R24, R16, R45 ; FFMA R16, R16, R4, R47 ; FFMA R37, R25, R17, R20 ; FFMA R17, R17, R5, R16 ; FFMA R20, R26, R18, R37 ; FFMA R16, R24, R8.reuse, R41 ; LDS.128 R36, [0x180] ; FFMA R8, R4, R8, R43 ; FFMA R18, R18, R6, R17 ; FFMA R17, R25, R9.reuse, R16 ; FFMA R9, R5, R9, R8 ; FFMA R16, R24, R32.reuse, R21 ; FFMA R32, R4, R32, R29 ; FFMA R8, R26, R10.reuse, R17 ; FFMA R10, R6, R10, R9 ; FFMA R9, R25, R33, R16 ; FFMA R41, R27, R19, R20 ; FFMA R43, R19, R7, R18 ; FFMA R33, R5, R33, R32 ; LDS.128 R16, [0x80] ; FFMA R24, R24, R12.reuse, R31 ; FFMA R12, R4, R12, R23 ; LDS.128 R28, [R52+0x480] ; FFMA R4, R26, R34, R9 ; FFMA R34, R6, R34, R33 ; LDS.128 R20, [R52+0x580] ; FFMA R9, R25, R13.reuse, R24 ; FFMA R33, R5, R13, R12 ; FFMA R25, R27, R11.reuse, R8 ; FFMA R45, R7, R11, R10 ; FFMA R26, R26, R14, R9 ; FFMA R13, R27, R35.reuse, R4 ; LDS.128 R8, [0x280] ; FFMA R5, R7, R35, R34 ; FFMA R6, R6, R14, R33 ; LDS.128 R32, [0x380] ; FFMA R27, R27, R15.reuse, R26 ; FFMA R7, R7, R15, R6 ; FFMA R4, R28, R16, R41 ; FFMA R6, R28, R36, R25 ; FFMA R16, R16, R20, R43 ; FFMA R36, R20, R36, R45 ; FFMA R15, R29, R17, R4 ; FFMA R17, R17, R21, R16 ; FFMA R25, R29, R37, R6 ; FFMA R37, R21, R37, R36 ; FFMA R40, R30, R18, R15 ; FFMA R36, R18, R22, R17 ; FFMA R16, R28, R8, R13 ; FFMA R18, R30, R38, R25 ; LDS.128 R12, [0x90] ; FFMA R8, R20, R8, R5 ; FFMA R28, R28, R32.reuse, R27 ; FFMA R20, R20, R32, R7 ; LDS.128 R24, [R52+0x490] ; FFMA R38, R22, R38, R37 ; FFMA R45, R31, R19, R40 ; LDS.128 R4, [R52+0x590] ; FFMA R47, R19, R23, R36 ; FFMA R41, R31, R39, R18 ; FFMA R37, R29, R9.reuse, R16 ; LDS.128 R16, [0x190] ; FFMA R9, R21, R9, R8 ; FFMA R43, R23, R39, R38 ; FFMA R8, R30, R10, R37 ; LDS.128 R36, [0x290] ; FFMA R29, R29, R33, R28 ; FFMA R21, R21, R33, R20 ; FFMA R10, R22, R10, R9 ; FFMA R30, R30, R34.reuse, R29 ; FFMA R22, R22, R34, R21 ; FFMA R21, R31, R11.reuse, R8 ; FFMA R29, R23, R11, R10 ; LDS.128 R8, [0x390] ; FFMA R31, R31, R35.reuse, R30 ; FFMA R23, R23, R35, R22 ; FFMA R20, R24, R12, R45 ; FFMA R12, R12, R4, R47 ; FFMA R33, R25, R13, R20 ; FFMA R13, R13, R5, R12 ; FFMA R20, R26, R14, R33 ; FFMA R12, R24, R16, R41 ; LDS.128 R32, [0x1a0] ; FFMA R14, R14, R6, R13 ; FFMA R16, R4, R16, R43 ; FFMA R13, R25, R17, R12 ; FFMA R12, R24, R36, R21 ; FFMA R17, R5, R17, R16 ; FFMA R16, R26, R18, R13 ; FFMA R36, R4, R36, R29 ; FFMA R13, R25, R37, R12 ; FFMA R41, R27, R15, R20 ; FFMA R37, R5, R37, R36 ; FFMA R24, R24, R8.reuse, R31 ; FFMA R8, R4, R8, R23 ; LDS.128 R28, [0xa0] ; FFMA R43, R15, R7, R14 ; FFMA R4, R26, R38, R13 ; LDS.128 R20, [R52+0x4a0] ; FFMA R18, R6.reuse, R18, R17 ; FFMA R38, R6, R38, R37 ; LDS.128 R12, [R52+0x5a0] ; FFMA R17, R25, R9, R24 ; FFMA R37, R5, R9, R8 ; FFMA R25, R27, R19.reuse, R16 ; FFMA R45, R7, R19, R18 ; FFMA R26, R26, R10, R17 ; FFMA R9, R27, R39.reuse, R4 ; LDS.128 R16, [0x2a0] ; FFMA R5, R7, R39, R38 ; FFMA R6, R6, R10, R37 ; LDS.128 R36, [0x3a0] ; FFMA R27, R27, R11.reuse, R26 ; FFMA R7, R7, R11, R6 ; FFMA R4, R20.reuse, R28, R41 ; FFMA R6, R20, R32, R25 ; FFMA R28, R28, R12, R43 ; FFMA R32, R12, R32, R45 ; FFMA R11, R21, R29, R4 ; FFMA R29, R29, R13, R28 ; FFMA R25, R21, R33.reuse, R6 ; FFMA R33, R13, R33, R32 ; FFMA R40, R22, R30, R11 ; FFMA R32, R30, R14, R29 ; FFMA R28, R20, R16, R9 ; FFMA R30, R22, R34, R25 ; LDS.128 R8, [0xb0] ; FFMA R16, R12, R16, R5 ; FFMA R20, R20, R36.reuse, R27 ; FFMA R12, R12, R36, R7 ; LDS.128 R24, [R52+0x4b0] ; FFMA R34, R14, R34, R33 ; FFMA R45, R23, R31, R40 ; LDS.128 R4, [R52+0x5b0] ; FFMA R47, R31, R15, R32 ; FFMA R41, R23, R35, R30 ; FFMA R33, R21, R17.reuse, R28 ; FFMA R17, R13.reuse, R17, R16 ; LDS.128 R28, [0x1b0] ; FFMA R13, R13, R37, R12 ; FFMA R12, R22, R18.reuse, R33 ; FFMA R43, R15, R35, R34 ; FFMA R21, R21, R37, R20 ; LDS.128 R32, [0x2b0] ; FFMA R18, R14, R18, R17 ; FFMA R22, R22, R38.reuse, R21 ; FFMA R14, R14, R38, R13 ; FFMA R13, R23, R19.reuse, R12 ; FFMA R21, R15, R19, R18 ; LDS.128 R16, [0x3b0] ; FFMA R23, R23, R39.reuse, R22 ; FFMA R15, R15, R39, R14 ; FFMA R12, R24, R8, R45 ; FFMA R8, R8, R4, R47 ; FFMA R37, R25, R9, R12 ; FFMA R9, R9, R5, R8 ; FFMA R12, R26, R10, R37 ; FFMA R8, R24, R28, R41 ; LDS.128 R36, [0x1c0] ; FFMA R10, R10, R6, R9 ; FFMA R28, R4, R28, R43 ; FFMA R9, R25, R29.reuse, R8 ; FFMA R8, R24, R32.reuse, R13 ; FFMA R29, R5, R29, R28 ; FFMA R32, R4, R32, R21 ; FFMA R28, R26, R30, R9 ; FFMA R9, R25, R33, R8 ; FFMA R33, R5, R33, R32 ; FFMA R24, R24, R16.reuse, R23 ; FFMA R16, R4, R16, R15 ; LDS.128 R20, [R52+0x4c0] ; FFMA R41, R27, R11, R12 ; FFMA R43, R11, R7, R10 ; LDS.128 R12, [R52+0x5c0] ; FFMA R4, R26, R34, R9 ; FFMA R25, R25, R17.reuse, R24 ; LDS.128 R8, [0xc0] ; FFMA R34, R6.reuse, R34, R33 ; FFMA R30, R6, R30, R29 ; FFMA R29, R5, R17, R16 ; FFMA R26, R26, R18, R25 ; FFMA R17, R27, R35, R4 ; FFMA R5, R7, R35, R34 ; FFMA R6, R6, R18, R29 ; LDS.128 R32, [0x2c0] ; FFMA R45, R27.reuse, R31, R28 ; FFMA R29, R27, R19, R26 ; LDS.128 R24, [0x3c0] ; FFMA R31, R7.reuse, R31, R30 ; FFMA R7, R7, R19, R6 ; FFMA R6, R20, R36.reuse, R45 ; FFMA R36, R12, R36, R31 ; FFMA R31, R21.reuse, R37, R6 ; FFMA R4, R20, R8, R41 ; FFMA R8, R8, R12, R43 ; FFMA R19, R21, R9, R4 ; FFMA R9, R9, R13, R8 ; FFMA R37, R13, R37, R36 ; FFMA R40, R22, R10, R19 ; FFMA R36, R10, R14, R9 ; FFMA R8, R20, R32.reuse, R17 ; FFMA R32, R12, R32, R5 ; LDS.128 R16, [R52+0x4d0] ; FFMA R10, R22, R38, R31 ; FFMA R12, R12, R24.reuse, R7 ; FFMA R20, R20, R24, R29 ; LDS.128 R4, [0xd0] ; FFMA R38, R14, R38, R37 ; FFMA R45, R23, R11, R40 ; LDS.128 R28, [R52+0x5d0] ; FFMA R47, R11, R15, R36 ; FFMA R41, R23, R39, R10 ; FFMA R37, R21, R33.reuse, R8 ; FFMA R33, R13.reuse, R33, R32 ; LDS.128 R8, [0x1d0] ; FFMA R13, R13, R25, R12 ; FFMA R12, R22, R34.reuse, R37 ; FFMA R43, R15, R39, R38 ; FFMA R21, R21, R25, R20 ; LDS.128 R36, [0x2d0] ; FFMA R34, R14, R34, R33 ; FFMA R22, R22, R26.reuse, R21 ; FFMA R14, R14, R26, R13 ; FFMA R13, R23, R35.reuse, R12 ; FFMA R21, R15, R35, R34 ; LDS.128 R32, [0x3d0] ; FFMA R23, R23, R27.reuse, R22 ; FFMA R15, R15, R27, R14 ; FFMA R12, R16, R4, R45 ; FFMA R4, R4, R28, R47 ; FFMA R25, R17, R5, R12 ; FFMA R5, R5, R29, R4 ; FFMA R12, R18, R6, R25 ; FFMA R4, R16, R8, R41 ; LDS.128 R24, [0xe0] ; FFMA R6, R6, R30, R5 ; FFMA R8, R28, R8, R43 ; FFMA R5, R17, R9.reuse, R4 ; FFMA R4, R16, R36, R13 ; FFMA R9, R29, R9, R8 ; FFMA R8, R18, R10, R5 ; FFMA R5, R17, R37, R4 ; FFMA R36, R28, R36, R21 ; FFMA R41, R19, R7, R12 ; FFMA R4, R16, R32.reuse, R23 ; FFMA R28, R28, R32, R15 ; LDS.128 R20, [0x1e0] ; FFMA R10, R30, R10, R9 ; FFMA R17, R17, R33, R4 ; LDS.128 R12, [R52+0x4e0] ; FFMA R43, R7, R31, R6 ; FFMA R37, R29.reuse, R37, R36 ; FFMA R16, R18.reuse, R38, R5 ; FFMA R9, R29, R33, R28 ; LDS.128 R4, [R52+0x5e0] ; FFMA R18, R18, R34, R17 ; FFMA R38, R30, R38, R37 ; FFMA R33, R19, R11, R8 ; FFMA R37, R31, R11, R10 ; FFMA R30, R30, R34, R9 ; LDS.128 R8, [0x2e0] ; FFMA R29, R19.reuse, R39, R16 ; FFMA R45, R19, R35, R18 ; LDS.128 R16, [0x3e0] ; FFMA R39, R31, R39, R38 ; FFMA R31, R31, R35, R30 ; FFMA R30, R12.reuse, R20, R33 ; FFMA R28, R12, R24, R41 ; FFMA R35, R13.reuse, R21, R30 ; FFMA R33, R13, R25, R28 ; FFMA R20, R4, R20, R37 ; FFMA R24, R24, R4, R43 ; FFMA R21, R5, R21, R20 ; LDS.128 R40, [0x3f0] ; FFMA R25, R25, R5, R24 ; FFMA R24, R14, R22.reuse, R35 ; FFMA R22, R6, R22, R21 ; FFMA R28, R12, R8, R29 ; FFMA R8, R4.reuse, R8, R39 ; FFMA R4, R4, R16, R31 ; LDS.128 R36, [0x2f0] ; FFMA R21, R13, R9.reuse, R28 ; FFMA R9, R5.reuse, R9, R8 ; LDS.128 R28, [0xf0] ; FFMA R5, R5, R17, R4 ; FFMA R4, R14, R10, R21 ; FFMA R12, R12, R16, R45 ; FFMA R10, R6, R10, R9 ; LDS.128 R44, [R52+0x4f0] ; FFMA R20, R14, R26, R33 ; FFMA R13, R13, R17, R12 ; LDS.128 R32, [0x1f0] ; FFMA R17, R15, R11.reuse, R4 ; FFMA R21, R7, R11, R10 ; LDS.128 R8, [R52+0x5f0] ; FFMA R26, R26, R6, R25 ; FFMA R14, R14, R18.reuse, R13 ; FFMA R6, R6, R18, R5 ; FFMA R5, R15.reuse, R27, R20 ; FFMA R13, R15, R23, R24 ; FFMA R27, R27, R7, R26 ; FFMA R23, R7, R23, R22 ; FFMA R15, R15, R19.reuse, R14 ; FFMA R19, R7, R19, R6 ; FFMA R4, R44.reuse, R28, R5 ; FFMA R12, R44.reuse, R36, R17 ; FFMA R6, R44, R32, R13 ; FFMA R44, R44, R40, R15 ; FFMA R5, R45, R29, R4 ; FFMA R28, R28, R8, R27 ; FFMA R32, R8.reuse, R32, R23 ; FFMA R36, R8.reuse, R36, R21 ; FFMA R8, R8, R40, R19 ; FFMA R7, R45.reuse, R33, R6 ; FFMA R13, R45.reuse, R37, R12 ; FFMA R45, R45, R41, R44 ; FFMA R29, R29, R9, R28 ; FFMA R33, R9.reuse, R33, R32 ; FFMA R37, R9, R37, R36 ; FFMA R9, R9, R41, R8 ; FFMA R4, R46.reuse, R30, R5 ; FFMA R6, R46.reuse, R34, R7 ; FFMA R12, R46.reuse, R38, R13 ; FFMA R46, R46, R42, R45 ; FFMA R30, R30, R10, R29 ; FFMA R34, R10.reuse, R34, R33 ; FFMA R38, R10.reuse, R38, R37 ; FFMA R10, R10, R42, R9 ; FFMA R17, R47.reuse, R31, R4 ; FFMA R7, R47.reuse, R35, R6 ; FFMA R5, R47, R39, R12 ; FFMA R47, R47, R43, R46 ; FFMA R41, R31, R11, R30 ; FFMA R45, R11.reuse, R35, R34 ; FFMA R53, R11.reuse, R39, R38 ; FFMA R43, R11, R43, R10 ; @P0 CALL.REL.NOINC 0x2f20 ; BRA 0x100 ; LEA R3, R2, R51, 0x6 ; IMAD.WIDE R2, R3, R0, c[0x0][0x170] ; STG.E [R2.64], R17 ; STG.E [R2.64+0x4], R41 ; STG.E [R2.64+0x10000], R7 ; STG.E [R2.64+0x10004], R45 ; STG.E [R2.64+0x20000], R5 ; STG.E [R2.64+0x20004], R53 ; STG.E [R2.64+0x30000], R47 ; STG.E [R2.64+0x30004], R43 ; EXIT ; BRA 0x2fd0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00047212_00000000-6_059eb5a379aab5c8fc14b91072b07823a61faf59.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z48__device_stub__Z24default_function_kernel0PvS_S_PvS_S_ .type _Z48__device_stub__Z24default_function_kernel0PvS_S_PvS_S_, @function _Z48__device_stub__Z24default_function_kernel0PvS_S_PvS_S_: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax movq %rdi, 8(%rsp) leaq 8(%rsp), %rax movq %rax, 96(%rsp) movq %rsi, 16(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) movq %rdx, 24(%rsp) leaq 24(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq default_function_kernel0(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z48__device_stub__Z24default_function_kernel0PvS_S_PvS_S_, .-_Z48__device_stub__Z24default_function_kernel0PvS_S_PvS_S_ .globl default_function_kernel0 .type default_function_kernel0, @function default_function_kernel0: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z48__device_stub__Z24default_function_kernel0PvS_S_PvS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size default_function_kernel0, .-default_function_kernel0 .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "default_function_kernel0" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq default_function_kernel0(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected default_function_kernel0 ; -- Begin function default_function_kernel0 .globl default_function_kernel0 .p2align 8 .type default_function_kernel0,@function default_function_kernel0: ; @default_function_kernel0 ; %bb.0: s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 s_mov_b32 s10, 0 s_mov_b64 s[2:3], 0 ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 .LBB0_1: ; %.preheader95 ; =>This Loop Header: Depth=1 ; Child Loop BB0_2 Depth 2 s_mov_b64 s[8:9], 0 .LBB0_2: ; Parent Loop BB0_1 Depth=1 ; => This Inner Loop Header: Depth=2 s_delay_alu instid0(SALU_CYCLE_1) s_add_i32 s11, s2, s8 s_add_u32 s8, s8, 1 s_addc_u32 s9, s9, 0 s_mov_b32 m0, s11 s_cmp_lg_u32 s8, 1 v_movreld_b32_e32 v1, 0 s_cbranch_scc0 .LBB0_2 ; %bb.3: ; in Loop: Header=BB0_1 Depth=1 s_add_i32 s10, s10, 1 s_add_u32 s2, s2, 2 s_addc_u32 s3, s3, 0 s_cmp_eq_u32 s10, 4 s_cbranch_scc0 .LBB0_1 ; %bb.4: ; %.preheader94 s_waitcnt lgkmcnt(0) s_add_u32 s2, s4, 0x800 s_addc_u32 s3, s5, 0 s_add_u32 s8, s4, 0x804 v_dual_mov_b32 v10, 0 :: v_dual_lshlrev_b32 v13, 1, v0 v_lshlrev_b32_e32 v14, 3, v0 s_addc_u32 s9, s5, 0 s_add_u32 s10, s4, 0x1000 s_addc_u32 s11, s5, 0 s_add_u32 s12, s4, 0x1004 s_addc_u32 s13, s5, 0 v_lshl_or_b32 v15, s15, 15, v13 v_or_b32_e32 v16, 0x4000, v14 v_or_b32_e32 v17, 0x4004, v14 v_add_nc_u32_e32 v18, 0x4100, v14 v_add_nc_u32_e32 v19, 0x4104, v14 v_add_nc_u32_e32 v20, 0x4200, v14 v_add_nc_u32_e32 v21, 0x4204, v14 s_add_u32 s14, s4, 0x1800 v_add_nc_u32_e32 v22, 0x4300, v14 v_add_nc_u32_e32 v23, 0x4304, v14 v_lshlrev_b32_e32 v24, 9, v0 s_addc_u32 s16, s5, 0 s_add_u32 s17, s4, 0x1804 s_addc_u32 s18, s5, 0 s_mov_b32 s19, 0 .LBB0_5: ; %.preheader92 ; =>This Loop Header: Depth=1 ; Child Loop BB0_6 Depth 2 ; Child Loop BB0_8 Depth 2 s_delay_alu instid0(SALU_CYCLE_1) v_lshl_add_u32 v9, s19, 6, v13 s_barrier buffer_gl0_inv s_mov_b32 s20, 0 v_lshlrev_b64 v[11:12], 2, v[9:10] v_or_b32_e32 v9, 1, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[25:26], 2, v[9:10] v_add_co_u32 v27, vcc_lo, s4, v11 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v28, vcc_lo, s5, v12, vcc_lo v_add_co_u32 v25, vcc_lo, s4, v25 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v26, vcc_lo, s5, v26, vcc_lo v_add_co_u32 v29, vcc_lo, s2, v11 v_add_co_ci_u32_e32 v30, vcc_lo, s3, v12, vcc_lo v_add_co_u32 v31, vcc_lo, s8, v11 v_add_co_ci_u32_e32 v32, vcc_lo, s9, v12, vcc_lo v_add_co_u32 v33, vcc_lo, s10, v11 v_add_co_ci_u32_e32 v34, vcc_lo, s11, v12, vcc_lo v_add_co_u32 v35, vcc_lo, s12, v11 v_add_co_ci_u32_e32 v36, vcc_lo, s13, v12, vcc_lo v_add_co_u32 v37, vcc_lo, s14, v11 v_add_co_ci_u32_e32 v38, vcc_lo, s16, v12, vcc_lo v_add_co_u32 v11, vcc_lo, s17, v11 v_add_co_ci_u32_e32 v12, vcc_lo, s18, v12, vcc_lo s_clause 0x7 global_load_b32 v9, v[27:28], off global_load_b32 v25, v[25:26], off global_load_b32 v26, v[29:30], off global_load_b32 v27, v[31:32], off global_load_b32 v28, v[33:34], off global_load_b32 v29, v[35:36], off global_load_b32 v30, v[37:38], off global_load_b32 v12, v[11:12], off v_mov_b32_e32 v11, v15 s_waitcnt vmcnt(7) ds_store_b32 v16, v9 s_waitcnt vmcnt(6) ds_store_b32 v17, v25 s_waitcnt vmcnt(5) ds_store_b32 v18, v26 s_waitcnt vmcnt(4) ds_store_b32 v19, v27 s_waitcnt vmcnt(3) ds_store_b32 v20, v28 s_waitcnt vmcnt(2) ds_store_b32 v21, v29 s_waitcnt vmcnt(1) ds_store_b32 v22, v30 s_waitcnt vmcnt(0) ds_store_b32 v23, v12 .p2align 6 .LBB0_6: ; %.preheader91 ; Parent Loop BB0_5 Depth=1 ; => This Inner Loop Header: Depth=2 v_add_nc_u32_e32 v25, 1, v11 v_ashrrev_i32_e32 v12, 31, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v26, 31, v25 v_lshlrev_b64 v[27:28], 2, v[11:12] v_add_nc_u32_e32 v11, 0x200, v11 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[25:26], 2, v[25:26] v_add_co_u32 v27, vcc_lo, s6, v27 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v28, vcc_lo, s7, v28, vcc_lo v_add_co_u32 v25, vcc_lo, s6, v25 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v26, vcc_lo, s7, v26, vcc_lo s_clause 0x1 global_load_b32 v9, v[27:28], off global_load_b32 v12, v[25:26], off v_add_nc_u32_e32 v25, s20, v14 s_addk_i32 s20, 0x100 s_delay_alu instid0(SALU_CYCLE_1) s_cmpk_lg_i32 s20, 0x4000 s_waitcnt vmcnt(0) ds_store_2addr_b32 v25, v9, v12 offset1:1 s_cbranch_scc1 .LBB0_6 ; %bb.7: ; in Loop: Header=BB0_5 Depth=1 s_mov_b32 s20, 0 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv .p2align 6 .LBB0_8: ; %.preheader90 ; Parent Loop BB0_5 Depth=1 ; => This Inner Loop Header: Depth=2 v_add_nc_u32_e32 v9, s20, v24 v_mov_b32_e32 v27, s20 s_add_i32 s20, s20, 4 ds_load_2addr_stride64_b32 v[11:12], v9 offset1:1 ds_load_2addr_stride64_b32 v[25:26], v27 offset0:64 offset1:65 ds_load_2addr_stride64_b32 v[27:28], v27 offset0:66 offset1:67 s_cmpk_lg_i32 s20, 0x100 s_waitcnt lgkmcnt(1) v_fmac_f32_e32 v2, v25, v12 v_dual_fmac_f32 v1, v25, v11 :: v_dual_fmac_f32 v4, v26, v12 s_waitcnt lgkmcnt(0) v_dual_fmac_f32 v3, v26, v11 :: v_dual_fmac_f32 v6, v27, v12 v_dual_fmac_f32 v5, v27, v11 :: v_dual_fmac_f32 v8, v28, v12 v_fmac_f32_e32 v7, v28, v11 s_cbranch_scc1 .LBB0_8 ; %bb.9: ; in Loop: Header=BB0_5 Depth=1 v_add_nc_u32_e32 v15, 64, v15 s_add_i32 s19, s19, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s19, 8 s_cbranch_scc0 .LBB0_5 ; %bb.10: ; %.preheader86 s_lshl_b32 s2, s15, 6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshl_add_u32 v9, v0, 1, s2 v_or_b32_e32 v11, 1, v9 v_ashrrev_i32_e32 v10, 31, v9 v_add_nc_u32_e32 v13, 0x4000, v9 v_add_nc_u32_e32 v15, 0x4001, v9 v_add_nc_u32_e32 v17, 0x8000, v9 v_ashrrev_i32_e32 v12, 31, v11 v_lshlrev_b64 v[20:21], 2, v[9:10] v_ashrrev_i32_e32 v14, 31, v13 v_add_nc_u32_e32 v19, 0x8001, v9 v_ashrrev_i32_e32 v16, 31, v15 v_ashrrev_i32_e32 v18, 31, v17 v_lshlrev_b64 v[10:11], 2, v[11:12] v_lshlrev_b64 v[12:13], 2, v[13:14] v_add_co_u32 v22, vcc_lo, s0, v20 v_lshlrev_b64 v[14:15], 2, v[15:16] v_add_co_ci_u32_e32 v23, vcc_lo, s1, v21, vcc_lo v_lshlrev_b64 v[16:17], 2, v[17:18] v_ashrrev_i32_e32 v20, 31, v19 v_add_nc_u32_e32 v18, 0xc000, v9 v_add_co_u32 v10, vcc_lo, s0, v10 v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo v_add_nc_u32_e32 v24, 0xc001, v9 v_add_co_u32 v12, vcc_lo, s0, v12 v_lshlrev_b64 v[20:21], 2, v[19:20] v_ashrrev_i32_e32 v19, 31, v18 v_add_co_ci_u32_e32 v13, vcc_lo, s1, v13, vcc_lo v_add_co_u32 v14, vcc_lo, s0, v14 v_ashrrev_i32_e32 v25, 31, v24 v_add_co_ci_u32_e32 v15, vcc_lo, s1, v15, vcc_lo v_add_co_u32 v16, vcc_lo, s0, v16 v_lshlrev_b64 v[18:19], 2, v[18:19] v_add_co_ci_u32_e32 v17, vcc_lo, s1, v17, vcc_lo v_add_co_u32 v20, vcc_lo, s0, v20 v_lshlrev_b64 v[24:25], 2, v[24:25] v_add_co_ci_u32_e32 v21, vcc_lo, s1, v21, vcc_lo v_add_co_u32 v18, vcc_lo, s0, v18 v_add_co_ci_u32_e32 v19, vcc_lo, s1, v19, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v24, vcc_lo, s0, v24 v_add_co_ci_u32_e32 v25, vcc_lo, s1, v25, vcc_lo s_clause 0x7 global_store_b32 v[22:23], v1, off global_store_b32 v[10:11], v2, off global_store_b32 v[12:13], v3, off global_store_b32 v[14:15], v4, off global_store_b32 v[16:17], v5, off global_store_b32 v[20:21], v6, off global_store_b32 v[18:19], v7, off global_store_b32 v[24:25], v8, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel default_function_kernel0 .amdhsa_group_segment_fixed_size 17408 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 39 .amdhsa_next_free_sgpr 21 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size default_function_kernel0, .Lfunc_end0-default_function_kernel0 ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1172 ; NumSgprs: 23 ; NumVgprs: 39 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 17408 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 4 ; NumSGPRsForWavesPerEU: 23 ; NumVGPRsForWavesPerEU: 39 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .actual_access: read_only .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .actual_access: read_only .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .actual_access: write_only .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 17408 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: default_function_kernel0 .private_segment_fixed_size: 0 .sgpr_count: 23 .sgpr_spill_count: 0 .symbol: default_function_kernel0.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 39 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "059eb5a379aab5c8fc14b91072b07823a61faf59.hip" .globl __device_stub__default_function_kernel0 # -- Begin function __device_stub__default_function_kernel0 .p2align 4, 0x90 .type __device_stub__default_function_kernel0,@function __device_stub__default_function_kernel0: # @__device_stub__default_function_kernel0 .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $default_function_kernel0, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size __device_stub__default_function_kernel0, .Lfunc_end0-__device_stub__default_function_kernel0 .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $default_function_kernel0, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type default_function_kernel0,@object # @default_function_kernel0 .section .rodata,"a",@progbits .globl default_function_kernel0 .p2align 3, 0x0 default_function_kernel0: .quad __device_stub__default_function_kernel0 .size default_function_kernel0, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "default_function_kernel0" .size .L__unnamed_1, 25 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __device_stub__default_function_kernel0 .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym default_function_kernel0 .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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code for sm_80 Function : _Z7encryptiPcS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R2, SR_CTAID.X ; S2R R3, SR_TID.X ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; @P0 EXIT ; SHF.R.S32.HI R3, RZ, 0x1f, R2 ; ULDC.64 UR4, c[0x0][0x118] ; IADD3 R4, P0, R2.reuse, c[0x0][0x168], RZ ; IADD3 R6, P1, R2, c[0x0][0x170], RZ ; IADD3.X R5, R3.reuse, c[0x0][0x16c], RZ, P0, !PT ; IADD3.X R7, R3, c[0x0][0x174], RZ, P1, !PT ; LDG.E.U8 R9, [R4.64] ; LDG.E.U8 R0, [R6.64] ; IADD3 R2, P0, R2, c[0x0][0x178], RZ ; IADD3.X R3, R3, c[0x0][0x17c], RZ, P0, !PT ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R9, [R4.64] ; LOP3.LUT R9, R0, R9, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R9 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R11, [R4.64] ; LOP3.LUT R11, R0, R11, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R11 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R13, [R4.64] ; LOP3.LUT R13, R0, R13, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R13 ; LDG.E.U8 R0, [R6.64] ; LDG.E.U8 R15, [R4.64] ; LOP3.LUT R15, R0, R15, RZ, 0x3c, !PT ; STG.E.U8 [R2.64], R15 ; EXIT ; BRA 0x19f0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000636b4_00000000-6_a226bbf15ca6d6362bf0e194f70db1c42aa34838.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2073: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2073: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z31__device_stub__Z7encryptiPcS_S_iPcS_S_ .type _Z31__device_stub__Z7encryptiPcS_S_iPcS_S_, @function _Z31__device_stub__Z7encryptiPcS_S_iPcS_S_: .LFB2095: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 28(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %rcx, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7encryptiPcS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2095: .size _Z31__device_stub__Z7encryptiPcS_S_iPcS_S_, .-_Z31__device_stub__Z7encryptiPcS_S_iPcS_S_ .globl _Z7encryptiPcS_S_ .type _Z7encryptiPcS_S_, @function _Z7encryptiPcS_S_: .LFB2096: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z7encryptiPcS_S_iPcS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2096: .size _Z7encryptiPcS_S_, .-_Z7encryptiPcS_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "r" .LC2: .string "../../file.txt" .LC3: .string "failed to read message file\n" .LC4: .string "%c" .LC5: .string "../../key.txt" .LC6: .string "failed to read key\n" .LC7: .string "Failed on malloc for m\n" .LC8: .string "Failed on malloc for k\n" .LC9: .string "Failed on malloc for c\n" .LC10: .string "mallocs gpu...\n" .LC11: .string "read data...\n" .LC12: .string "Copy to device...\n" .LC13: .string "Setting up streams...\n" .LC14: .string "moving on...\n" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC15: .string "Failed to create start event (error code %s)!\n" .align 8 .LC16: .string "Failed to create stop event (error code %s)!\n" .align 8 .LC17: .string "Failed to record start event (error code %s)!\n" .align 8 .LC18: .string "Failed to record stop event (error code %s)!\n" .align 8 .LC19: .string "Failed to synchronize on the stop event (error code %s)!\n" .align 8 .LC20: .string "cudaMemcpy (c,d_c) returned error code %d, line(%d)\n" .align 8 .LC21: .string "Failed to get time elapsed between events (error code %s)!\n" .section .rodata.str1.1 .LC23: .string "Performance= %.06f sec\n" .section .rodata.str1.8 .align 8 .LC24: .string "WRONG! c[%d] != m[%d]^k[%d] ==> c='%c',m^k=%c\n" .text .globl main .type main, @function main: .LFB2070: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsp, %rbp .cfi_def_cfa_register 6 pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $152, %rsp .cfi_offset 15, -24 .cfi_offset 14, -32 .cfi_offset 13, -40 .cfi_offset 12, -48 .cfi_offset 3, -56 movq %fs:40, %rax movq %rax, -56(%rbp) xorl %eax, %eax movl $0x00000000, -124(%rbp) leaq .LC1(%rip), %rsi leaq .LC2(%rip), %rdi call fopen@PLT movq %rax, %r14 testq %rax, %rax je .L49 .L12: leaq .LC4(%rip), %r13 jmp .L13 .L49: leaq .LC3(%rip), %rdi call perror@PLT jmp .L12 .L14: addl $1, %ebx .L13: leaq -125(%rbp), %rdx movq %r13, %rsi movq %r14, %rdi movl $0, %eax call __isoc23_fscanf@PLT cmpl $-1, %eax jne .L14 leaq .LC1(%rip), %rsi leaq .LC5(%rip), %rdi call fopen@PLT movq %rax, -144(%rbp) testq %rax, %rax je .L50 .L15: leaq .LC4(%rip), %r13 movq -144(%rbp), %r12 jmp .L16 .L50: leaq .LC6(%rip), %rdi call perror@PLT jmp .L15 .L17: addl $1, %r15d .L16: leaq -125(%rbp), %rdx movq %r13, %rsi movq %r12, %rdi movl $0, %eax call __isoc23_fscanf@PLT cmpl $-1, %eax jne .L17 movslq %ebx, %rax movq %rax, -136(%rbp) movq %rax, %rdi call malloc@PLT movq %rax, -152(%rbp) testq %rax, %rax je .L51 movslq %r15d, %r15 movq %r15, %rdi call malloc@PLT movq %rax, -160(%rbp) testq %rax, %rax je .L52 movq -136(%rbp), %rdi call malloc@PLT movq %rax, -168(%rbp) testq %rax, %rax je .L53 leaq .LC10(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq -120(%rbp), %rdi movq -136(%rbp), %r13 movq %r13, %rsi call cudaMalloc@PLT leaq -112(%rbp), %rdi movq %r15, %rsi call cudaMalloc@PLT leaq -104(%rbp), %rdi movq %r13, %rsi call cudaMalloc@PLT movl $0, %edx movl $0, %esi movq %r14, %rdi call fseek@PLT movl $0, %edx movl $0, %esi movq -144(%rbp), %rdi call fseek@PLT leaq .LC11(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq -152(%rbp), %r12 leaq .LC4(%rip), %r13 jmp .L21 .L51: leaq .LC7(%rip), %rsi movl $2, %edi call __printf_chk@PLT movl $1, %edi call exit@PLT .L52: leaq .LC8(%rip), %rsi movl $2, %edi call __printf_chk@PLT movl $1, %edi call exit@PLT .L53: leaq .LC9(%rip), %rsi movl $2, %edi call __printf_chk@PLT movl $1, %edi call exit@PLT .L22: movzbl -125(%rbp), %eax movb %al, (%r12) addq $1, %r12 .L21: leaq -125(%rbp), %rdx movq %r13, %rsi movq %r14, %rdi movl $0, %eax call __isoc23_fscanf@PLT cmpl $-1, %eax jne .L22 movq -160(%rbp), %r12 leaq .LC4(%rip), %r13 movl %ebx, -176(%rbp) movq -144(%rbp), %rbx jmp .L23 .L24: movzbl -125(%rbp), %eax movb %al, (%r12) addq $1, %r12 .L23: leaq -125(%rbp), %rdx movq %r13, %rsi movq %rbx, %rdi movl $0, %eax call __isoc23_fscanf@PLT cmpl $-1, %eax jne .L24 movl -176(%rbp), %ebx leaq .LC12(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %ecx movq -136(%rbp), %rdx movq -152(%rbp), %rsi movq -120(%rbp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %r15, %rdx movq -160(%rbp), %rsi movq -112(%rbp), %rdi call cudaMemcpy@PLT leaq .LC13(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leal 67108863(%rbx), %r15d testl %ebx, %ebx cmovns %ebx, %r15d sarl $26, %r15d movslq %r15d, %rax leaq 15(,%rax,8), %rax movq %rax, %rcx andq $-16, %rcx andq $-4096, %rax movq %rsp, %rdx subq %rax, %rdx .L25: cmpq %rdx, %rsp je .L26 subq $4096, %rsp orq $0, 4088(%rsp) jmp .L25 .L26: movq %rcx, %rax andl $4095, %eax subq %rax, %rsp testq %rax, %rax je .L27 orq $0, -8(%rsp,%rax) .L27: movq %rsp, %r13 movq %r13, -184(%rbp) cmpl $67108863, %ebx jle .L28 movl $0, %r12d .L29: movq %r13, %rdi call cudaStreamCreate@PLT addl $1, %r12d addq $8, %r13 cmpl %r12d, %r15d jg .L29 .L28: leaq .LC14(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT call cudaDeviceSynchronize@PLT leaq -96(%rbp), %rdi call cudaEventCreate@PLT testl %eax, %eax jne .L54 leaq -88(%rbp), %rdi call cudaEventCreate@PLT testl %eax, %eax jne .L55 movl $0, %esi movq -96(%rbp), %rdi call cudaEventRecord@PLT testl %eax, %eax jne .L32 subl $1, %r15d cmpl $134217727, %ebx jle .L34 leal 2046(%rbx), %eax movl %ebx, %edx addl $1023, %edx cmovns %edx, %eax sarl $10, %eax movl %eax, %r13d movl $0, %r12d movq %r14, -176(%rbp) movq -184(%rbp), %r14 jmp .L36 .L54: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC15(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L55: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC16(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L32: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC17(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L35: movq (%r14,%r12,8), %rdi call cudaStreamSynchronize@PLT addq $1, %r12 cmpl %r12d, %r15d jle .L56 .L36: movl $1024, -68(%rbp) movl $1, -64(%rbp) movl $1, -60(%rbp) movl %r13d, -80(%rbp) movl $1, -76(%rbp) movl $1, -72(%rbp) movl $0, %r9d movl $0, %r8d movq -68(%rbp), %rdx movl $1, %ecx movq -80(%rbp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L35 movq -104(%rbp), %rcx movq -112(%rbp), %rdx movq -120(%rbp), %rsi movl %ebx, %edi call _Z31__device_stub__Z7encryptiPcS_S_iPcS_S_ jmp .L35 .L56: movq -176(%rbp), %r14 .L34: movl $0, %esi movq -88(%rbp), %rdi call cudaEventRecord@PLT testl %eax, %eax jne .L57 movq -88(%rbp), %rdi call cudaEventSynchronize@PLT testl %eax, %eax jne .L58 movl $2, %ecx movq -136(%rbp), %rdx movq -104(%rbp), %rsi movq -168(%rbp), %rdi call cudaMemcpy@PLT testl %eax, %eax jne .L59 leaq -124(%rbp), %rdi movq -88(%rbp), %rdx movq -96(%rbp), %rsi call cudaEventElapsedTime@PLT testl %eax, %eax jne .L60 pxor %xmm0, %xmm0 cvtss2sd -124(%rbp), %xmm0 divsd .LC22(%rip), %xmm0 leaq .LC23(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT testl %ebx, %ebx jle .L41 movl $0, %ebx leaq .LC24(%rip), %r12 movq %r14, -176(%rbp) movq -152(%rbp), %r14 movq -160(%rbp), %r13 movq -168(%rbp), %r15 jmp .L43 .L57: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC18(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L58: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC19(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L59: movl $154, %ecx movl %eax, %edx leaq .LC20(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %edi call exit@PLT .L60: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC21(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .L42: addq $1, %rbx cmpq %rbx, -136(%rbp) je .L61 .L43: movzbl (%r15,%rbx), %r9d movzbl (%r14,%rbx), %eax xorb 0(%r13,%rbx), %al cmpb %al, %r9b je .L42 movl %ebx, %edx subq $8, %rsp movsbl %al, %eax pushq %rax movsbl %r9b, %r9d movl %ebx, %r8d movl %ebx, %ecx movq %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $16, %rsp jmp .L42 .L61: movq -176(%rbp), %r14 .L41: movq -152(%rbp), %rdi call free@PLT movq -160(%rbp), %rdi call free@PLT movq -168(%rbp), %rdi call free@PLT movq -120(%rbp), %rdi call cudaFree@PLT movq -112(%rbp), %rdi call cudaFree@PLT movq -104(%rbp), %rdi call cudaFree@PLT movq %r14, %rdi call fclose@PLT movq -144(%rbp), %rdi call fclose@PLT movq -56(%rbp), %rax subq %fs:40, %rax jne .L62 movl $0, %eax leaq -40(%rbp), %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 popq %rbp .cfi_remember_state .cfi_def_cfa 7, 8 ret .L62: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2070: .size main, .-main .section .rodata.str1.1 .LC25: .string "_Z7encryptiPcS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2098: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC25(%rip), %rdx movq %rdx, %rcx leaq _Z7encryptiPcS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2098: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC22: .long 0 .long 1083129856 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z7encryptiPcS_S_ ; -- Begin function _Z7encryptiPcS_S_ .globl _Z7encryptiPcS_S_ .p2align 8 .type _Z7encryptiPcS_S_,@function _Z7encryptiPcS_S_: ; @_Z7encryptiPcS_S_ ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v4 s_cbranch_execz .LBB0_3 ; %bb.1: ; %.preheader s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x8 s_load_b64 s[0:1], s[0:1], 0x18 v_ashrrev_i32_e32 v5, 31, v4 s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s4, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo v_add_co_u32 v2, vcc_lo, s6, v4 v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo v_add_co_u32 v4, vcc_lo, s0, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo s_movk_i32 s0, 0x64 .LBB0_2: ; =>This Inner Loop Header: Depth=1 global_load_u8 v6, v[0:1], off global_load_u8 v7, v[2:3], off s_add_i32 s0, s0, -1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u32 s0, 0 s_waitcnt vmcnt(0) v_xor_b32_e32 v6, v7, v6 global_store_b8 v[4:5], v6, off s_cbranch_scc1 .LBB0_2 .LBB0_3: ; %.loopexit s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z7encryptiPcS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z7encryptiPcS_S_, .Lfunc_end0-_Z7encryptiPcS_S_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 192 ; NumSgprs: 18 ; NumVgprs: 8 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 8 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z7encryptiPcS_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z7encryptiPcS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "a226bbf15ca6d6362bf0e194f70db1c42aa34838.hip" .globl _Z22__device_stub__encryptiPcS_S_ # -- Begin function _Z22__device_stub__encryptiPcS_S_ .p2align 4, 0x90 .type _Z22__device_stub__encryptiPcS_S_,@function _Z22__device_stub__encryptiPcS_S_: # @_Z22__device_stub__encryptiPcS_S_ .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 4(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) movq %rcx, 56(%rsp) leaq 4(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 56(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7encryptiPcS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z22__device_stub__encryptiPcS_S_, .Lfunc_end0-_Z22__device_stub__encryptiPcS_S_ .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI1_0: .quad 0x408f400000000000 # double 1000 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset %rbp, -16 movq %rsp, %rbp .cfi_def_cfa_register %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $232, %rsp .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 movl $0, -48(%rbp) movl $.L.str, %edi movl $.L.str.1, %esi callq fopen movq %rax, %rbx testq %rax, %rax je .LBB1_1 .LBB1_2: # %.preheader160 movq $-1, %r15 leaq -41(%rbp), %r14 # implicit-def: $r12d .p2align 4, 0x90 .LBB1_3: # =>This Inner Loop Header: Depth=1 movl $.L.str.3, %esi movq %rbx, %rdi movq %r14, %rdx xorl %eax, %eax callq __isoc23_fscanf incq %r15 incl %r12d cmpl $-1, %eax jne .LBB1_3 # %bb.4: movq %rbx, -136(%rbp) # 8-byte Spill movl $.L.str.4, %edi movl $.L.str.1, %esi callq fopen movq %rax, %r14 testq %rax, %rax je .LBB1_5 .LBB1_6: # %.preheader159 movq $-1, %r13 leaq -41(%rbp), %rbx .p2align 4, 0x90 .LBB1_7: # =>This Inner Loop Header: Depth=1 movl $.L.str.3, %esi movq %r14, %rdi movq %rbx, %rdx xorl %eax, %eax callq __isoc23_fscanf incq %r13 cmpl $-1, %eax jne .LBB1_7 # %bb.8: movq %r15, %rdi callq malloc movq %rax, -64(%rbp) # 8-byte Spill testq %rax, %rax je .LBB1_9 # %bb.11: movq %r13, %rdi callq malloc movq %rax, -56(%rbp) # 8-byte Spill testq %rax, %rax movq -136(%rbp), %rbx # 8-byte Reload je .LBB1_12 # %bb.13: movq %r15, %rdi callq malloc movq %rax, -72(%rbp) # 8-byte Spill testq %rax, %rax je .LBB1_14 # %bb.15: movl $.Lstr.3, %edi callq puts@PLT leaq -104(%rbp), %rdi movq %r15, %rsi callq hipMalloc leaq -96(%rbp), %rdi movq %r13, %rsi callq hipMalloc leaq -88(%rbp), %rdi movq %r15, %rsi callq hipMalloc movq %rbx, %rdi xorl %esi, %esi xorl %edx, %edx callq fseek movq %r14, -128(%rbp) # 8-byte Spill movq %r14, %rdi xorl %esi, %esi xorl %edx, %edx callq fseek movl $.Lstr.4, %edi callq puts@PLT leaq -41(%rbp), %rdx movl $.L.str.3, %esi movq %rbx, %rdi xorl %eax, %eax callq __isoc23_fscanf cmpl $-1, %eax je .LBB1_18 # %bb.16: movq -64(%rbp), %r14 # 8-byte Reload .p2align 4, 0x90 .LBB1_17: # %.lr.ph # =>This Inner Loop Header: Depth=1 movzbl -41(%rbp), %eax movb %al, (%r14) movl $.L.str.3, %esi movq %rbx, %rdi leaq -41(%rbp), %rdx xorl %eax, %eax callq __isoc23_fscanf incq %r14 cmpl $-1, %eax jne .LBB1_17 .LBB1_18: # %.preheader124 leaq -41(%rbp), %rdx movl $.L.str.3, %esi movq -128(%rbp), %rbx # 8-byte Reload movq %rbx, %rdi xorl %eax, %eax callq __isoc23_fscanf cmpl $-1, %eax je .LBB1_21 # %bb.19: movq -56(%rbp), %r14 # 8-byte Reload .p2align 4, 0x90 .LBB1_20: # %.lr.ph129 # =>This Inner Loop Header: Depth=1 movzbl -41(%rbp), %eax movb %al, (%r14) movl $.L.str.3, %esi movq %rbx, %rdi leaq -41(%rbp), %rdx xorl %eax, %eax callq __isoc23_fscanf incq %r14 cmpl $-1, %eax jne .LBB1_20 .LBB1_21: # %._crit_edge movl $.Lstr.5, %edi callq puts@PLT movq -104(%rbp), %rdi movq -64(%rbp), %rsi # 8-byte Reload movq %r15, %rdx movl $1, %ecx callq hipMemcpy movq -96(%rbp), %rdi movq -56(%rbp), %rsi # 8-byte Reload movq %r13, %rdx movl $1, %ecx callq hipMemcpy movl $.Lstr.6, %edi callq puts@PLT leal 67108863(%r15), %eax testl %r15d, %r15d cmovnsl %r15d, %eax movq %rsp, %r13 sarl $26, %eax movq %rax, -120(%rbp) # 8-byte Spill leaq 15(,%rax,8), %rax andq $-16, %rax movq %rsp, %rcx subq %rax, %rcx movq %rcx, -144(%rbp) # 8-byte Spill movq %rcx, %rsp cmpl $67108864, %r15d # imm = 0x4000000 jl .LBB1_24 # %bb.22: # %.lr.ph132.preheader movl -120(%rbp), %r14d # 4-byte Reload movq -144(%rbp), %rbx # 8-byte Reload .p2align 4, 0x90 .LBB1_23: # %.lr.ph132 # =>This Inner Loop Header: Depth=1 movq %rbx, %rdi callq hipStreamCreate addq $8, %rbx decq %r14 jne .LBB1_23 .LBB1_24: # %._crit_edge133 movl $.Lstr.7, %edi callq puts@PLT callq hipDeviceSynchronize leaq -152(%rbp), %rdi callq hipEventCreate testl %eax, %eax jne .LBB1_25 # %bb.27: leaq -80(%rbp), %rdi callq hipEventCreate testl %eax, %eax jne .LBB1_28 # %bb.29: movq %r13, -160(%rbp) # 8-byte Spill movq -152(%rbp), %rdi xorl %esi, %esi callq hipEventRecord testl %eax, %eax jne .LBB1_48 # %bb.30: # %.preheader cmpl $134217728, %r15d # imm = 0x8000000 jl .LBB1_35 # %bb.31: # %.lr.ph135 movabsq $4294967296, %r13 # imm = 0x100000000 shrl $10, %r12d orq %r13, %r12 movq -120(%rbp), %rax # 8-byte Reload cmpl $3, %eax movl $2, %ebx cmovgel %eax, %ebx decl %ebx xorl %r14d, %r14d addq $1024, %r13 # imm = 0x400 jmp .LBB1_32 .p2align 4, 0x90 .LBB1_34: # in Loop: Header=BB1_32 Depth=1 movq -144(%rbp), %rax # 8-byte Reload movq (%rax,%r14,8), %rdi callq hipStreamSynchronize incq %r14 cmpq %r14, %rbx je .LBB1_35 .LBB1_32: # =>This Inner Loop Header: Depth=1 movq %r12, %rdi movl $1, %esi movq %r13, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_34 # %bb.33: # in Loop: Header=BB1_32 Depth=1 movq -104(%rbp), %rax movq -96(%rbp), %rcx movq -88(%rbp), %rdx movl %r15d, -108(%rbp) movq %rax, -232(%rbp) movq %rcx, -224(%rbp) movq %rdx, -216(%rbp) leaq -108(%rbp), %rax movq %rax, -272(%rbp) leaq -232(%rbp), %rax movq %rax, -264(%rbp) leaq -224(%rbp), %rax movq %rax, -256(%rbp) leaq -216(%rbp), %rax movq %rax, -248(%rbp) leaq -208(%rbp), %rdi leaq -192(%rbp), %rsi leaq -176(%rbp), %rdx leaq -168(%rbp), %rcx callq __hipPopCallConfiguration movq -208(%rbp), %rsi movl -200(%rbp), %edx movq -192(%rbp), %rcx movl -184(%rbp), %r8d movl $_Z7encryptiPcS_S_, %edi leaq -272(%rbp), %r9 pushq -168(%rbp) pushq -176(%rbp) callq hipLaunchKernel addq $16, %rsp jmp .LBB1_34 .LBB1_35: # %._crit_edge136 movq -80(%rbp), %rdi xorl %esi, %esi callq hipEventRecord testl %eax, %eax jne .LBB1_36 # %bb.37: movq -80(%rbp), %rdi callq hipEventSynchronize testl %eax, %eax movq -128(%rbp), %r14 # 8-byte Reload movq -64(%rbp), %r12 # 8-byte Reload movq -56(%rbp), %r13 # 8-byte Reload jne .LBB1_38 # %bb.39: movq -88(%rbp), %rsi movq -72(%rbp), %rdi # 8-byte Reload movq %r15, %rdx movl $2, %ecx callq hipMemcpy testl %eax, %eax jne .LBB1_49 # %bb.40: movq -152(%rbp), %rsi movq -80(%rbp), %rdx leaq -48(%rbp), %rdi callq hipEventElapsedTime testl %eax, %eax jne .LBB1_41 # %bb.42: movss -48(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 divsd .LCPI1_0(%rip), %xmm0 movl $.L.str.21, %edi movb $1, %al callq printf testl %r15d, %r15d jle .LBB1_47 # %bb.43: # %.lr.ph139.preheader movl %r15d, %ebx xorl %r15d, %r15d jmp .LBB1_44 .p2align 4, 0x90 .LBB1_46: # in Loop: Header=BB1_44 Depth=1 incq %r15 cmpq %r15, %rbx je .LBB1_47 .LBB1_44: # %.lr.ph139 # =>This Inner Loop Header: Depth=1 movq -72(%rbp), %rax # 8-byte Reload movsbl (%rax,%r15), %r8d movzbl (%r13,%r15), %eax xorb (%r12,%r15), %al cmpb %al, %r8b je .LBB1_46 # %bb.45: # in Loop: Header=BB1_44 Depth=1 movsbl %al, %r9d movl $.L.str.22, %edi movl %r15d, %esi movl %r15d, %edx movl %r15d, %ecx xorl %eax, %eax callq printf jmp .LBB1_46 .LBB1_47: # %._crit_edge140 movq %r12, %rdi callq free movq %r13, %rdi callq free movq -72(%rbp), %rdi # 8-byte Reload callq free movq -104(%rbp), %rdi callq hipFree movq -96(%rbp), %rdi callq hipFree movq -88(%rbp), %rdi callq hipFree movq -136(%rbp), %rdi # 8-byte Reload callq fclose movq %r14, %rdi callq fclose movq -160(%rbp), %rsp # 8-byte Reload xorl %eax, %eax leaq -40(%rbp), %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 popq %rbp .cfi_def_cfa %rsp, 8 retq .LBB1_1: .cfi_def_cfa %rbp, 16 movl $.L.str.2, %edi callq perror jmp .LBB1_2 .LBB1_5: movl $.L.str.5, %edi callq perror jmp .LBB1_6 .LBB1_9: movl $.Lstr, %edi jmp .LBB1_10 .LBB1_12: movl $.Lstr.1, %edi jmp .LBB1_10 .LBB1_14: movl $.Lstr.2, %edi .LBB1_10: callq puts@PLT movl $1, %edi callq exit .LBB1_25: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.14, %esi jmp .LBB1_26 .LBB1_28: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.15, %esi jmp .LBB1_26 .LBB1_48: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.16, %esi jmp .LBB1_26 .LBB1_36: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.17, %esi jmp .LBB1_26 .LBB1_38: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.18, %esi jmp .LBB1_26 .LBB1_49: movl $.L.str.19, %edi movl %eax, %esi movl $156, %edx xorl %eax, %eax callq printf movl $1, %edi callq exit .LBB1_41: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.20, %esi .LBB1_26: movq %rbx, %rdi movq %rax, %rdx xorl %eax, %eax callq fprintf movl $1, %edi callq exit .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7encryptiPcS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z7encryptiPcS_S_,@object # @_Z7encryptiPcS_S_ .section .rodata,"a",@progbits .globl _Z7encryptiPcS_S_ .p2align 3, 0x0 _Z7encryptiPcS_S_: .quad _Z22__device_stub__encryptiPcS_S_ .size _Z7encryptiPcS_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "../../file.txt" .size .L.str, 15 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "r" .size .L.str.1, 2 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "failed to read message file\n" .size .L.str.2, 29 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "%c" .size .L.str.3, 3 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "../../key.txt" .size .L.str.4, 14 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "failed to read key\n" .size .L.str.5, 20 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz "Failed to create start event (error code %s)!\n" .size .L.str.14, 47 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "Failed to create stop event (error code %s)!\n" .size .L.str.15, 46 .type .L.str.16,@object # @.str.16 .L.str.16: .asciz "Failed to record start event (error code %s)!\n" .size .L.str.16, 47 .type .L.str.17,@object # @.str.17 .L.str.17: .asciz "Failed to record stop event (error code %s)!\n" .size .L.str.17, 46 .type .L.str.18,@object # @.str.18 .L.str.18: .asciz "Failed to synchronize on the stop event (error code %s)!\n" .size .L.str.18, 58 .type .L.str.19,@object # @.str.19 .L.str.19: .asciz "hipMemcpy (c,d_c) returned error code %d, line(%d)\n" .size .L.str.19, 52 .type .L.str.20,@object # @.str.20 .L.str.20: .asciz "Failed to get time elapsed between events (error code %s)!\n" .size .L.str.20, 60 .type .L.str.21,@object # @.str.21 .L.str.21: .asciz "Performance= %.06f sec\n" .size .L.str.21, 24 .type .L.str.22,@object # @.str.22 .L.str.22: .asciz "WRONG! c[%d] != m[%d]^k[%d] ==> c='%c',m^k=%c\n" .size .L.str.22, 47 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z7encryptiPcS_S_" .size .L__unnamed_1, 18 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Failed on malloc for m" .size .Lstr, 23 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "Failed on malloc for k" .size .Lstr.1, 23 .type .Lstr.2,@object # @str.2 .Lstr.2: .asciz "Failed on malloc for c" .size .Lstr.2, 23 .type .Lstr.3,@object # @str.3 .Lstr.3: .asciz "mallocs gpu..." .size .Lstr.3, 15 .type .Lstr.4,@object # @str.4 .Lstr.4: .asciz "read data..." .size .Lstr.4, 13 .type .Lstr.5,@object # @str.5 .Lstr.5: .asciz "Copy to device..." .size .Lstr.5, 18 .type .Lstr.6,@object # @str.6 .Lstr.6: .asciz "Setting up streams..." .size .Lstr.6, 22 .type .Lstr.7,@object # @str.7 .Lstr.7: .asciz "moving on..." .size .Lstr.7, 13 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__encryptiPcS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7encryptiPcS_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
9,714
7,130
2,610
8,151
195
code for sm_80 Function : _Z3sumPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_TID.X ; IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; ULDC.64 UR12, c[0x0][0x118] ; IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; LDG.E R7, [R2.64] ; IMAD.WIDE R4, R0.reuse, R5, c[0x0][0x168] ; ISETP.GT.AND P0, PT, R0, 0x3, PT ; BSSY B0, 0x410 ; STG.E [R4.64], R7 ; @P0 BRA 0x2b0 ; IMNMX.U32 R6, R0, 0x3, PT ; UMOV UR9, 0x1 ; ULDC.64 UR4, c[0x2][0x10] ; SHF.L.U32 R12, R6, 0x2, RZ ; ULDC.64 UR6, c[0x0][0x168] ; UIMAD.WIDE.U32 UR4, UR9, UR6, UR4 ; LDC R10, c[0x2][R12] ; UIMAD UR8, UR9, UR7, URZ ; ULDC.64 UR10, c[0x0][0x160] ; ULDC.64 UR6, c[0x2][0x18] ; IMAD.U32 R7, RZ, RZ, UR5 ; UIMAD.WIDE.U32 UR6, UR9, UR10, UR6 ; IMAD.U32 R6, RZ, RZ, UR4 ; UIMAD UR9, UR9, UR11, URZ ; UIADD3 UR8, UR5, UR8, URZ ; UIADD3 UR9, UR7, UR9, URZ ; IMAD.U32 R9, RZ, RZ, UR7 ; MOV R8, UR6 ; IMAD.U32 R7, RZ, RZ, UR8 ; MOV R9, UR9 ; SHF.R.S32.HI R11, RZ, 0x1f, R10 ; BRX R10 -0x210 ; LDG.E R9, [R8.64] ; LDG.E R10, [R6.64] ; IMAD.IADD R11, R10, 0x1, R9 ; STG.E [R6.64], R11 ; BRA 0x400 ; LDG.E R9, [R8.64+-0x8] ; LDG.E R10, [R6.64+-0x8] ; IADD3 R11, R10, R9, RZ ; STG.E [R6.64+-0x8], R11 ; BRA 0x400 ; ISETP.NE.AND P0, PT, R0, 0x4, PT ; @!P0 BRA 0x380 ; ISETP.NE.AND P0, PT, R0, 0x6, PT ; @P0 BRA 0x400 ; MOV R9, c[0x0][0x164] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; MOV R7, c[0x0][0x16c] ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; LDG.E R9, [R8.64+0x1c] ; LDG.E R10, [R6.64+0x18] ; IMAD.IADD R11, R10, 0x1, R9 ; STG.E [R6.64+0x18], R11 ; BRA 0x400 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; MOV R8, c[0x0][0x160] ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; MOV R6, c[0x0][0x168] ; LDG.E R9, [R8.64+0x14] ; LDG.E R10, [R6.64+0x10] ; IADD3 R11, R10, R9, RZ ; STG.E [R6.64+0x10], R11 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; UMOV UR8, 0x1 ; ULDC.64 UR4, c[0x2][0x10] ; ULDC.64 UR6, c[0x0][0x168] ; LDG.E R11, [R4.64] ; ISETP.NE.AND P0, PT, R0, RZ, PT ; UIMAD.WIDE.U32 UR4, UR8, UR6, UR4 ; BSSY B0, 0x600 ; UIMAD UR7, UR8, UR7, URZ ; MOV R8, c[0x0][0x160] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; UIADD3 UR7, UR5, UR7, URZ ; MOV R7, UR5 ; IMAD.U32 R6, RZ, RZ, UR4 ; IMAD.U32 R7, RZ, RZ, UR7 ; STG.E [R2.64], R11 ; @!P0 BRA 0x5b0 ; ISETP.NE.AND P0, PT, R0, 0x4, PT ; @P0 BRA 0x5f0 ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; MOV R10, c[0x0][0x168] ; LDG.E R12, [R8.64+0x10] ; LDG.E R11, [R10.64+0x18] ; IADD3 R13, R12, R11, RZ ; STG.E [R8.64+0x10], R13 ; BRA 0x5f0 ; LDG.E R10, [R8.64] ; LDG.E R11, [R6.64] ; IMAD.IADD R11, R10, 0x1, R11 ; STG.E [R8.64], R11 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDG.E R11, [R2.64] ; ISETP.NE.AND P0, PT, R0, RZ, PT ; STG.E [R4.64], R11 ; @!P0 LDG.E R9, [R8.64+0x10] ; @!P0 LDG.E R0, [R6.64+-0x8] ; @!P0 IADD3 R13, R0, R9, RZ ; @!P0 STG.E [R6.64+-0x8], R13 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; LDG.E R15, [R4.64] ; STG.E [R2.64], R15 ; EXIT ; BRA 0x6c0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_0008af45_00000000-6_d9285c76cb23c3f75ec66349d64dd9f598fca74f.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z24__device_stub__Z3sumPiS_PiS_ .type _Z24__device_stub__Z3sumPiS_PiS_, @function _Z24__device_stub__Z3sumPiS_PiS_: .LFB3694: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z3sumPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z24__device_stub__Z3sumPiS_PiS_, .-_Z24__device_stub__Z3sumPiS_PiS_ .globl _Z3sumPiS_ .type _Z3sumPiS_, @function _Z3sumPiS_: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z24__device_stub__Z3sumPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z3sumPiS_, .-_Z3sumPiS_ .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $48, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $32, %edi call malloc@PLT movq %rax, %rbp movl $0, %eax .L12: movl %eax, 0(%rbp,%rax,4) addq $1, %rax cmpq $8, %rax jne .L12 movq %rsp, %rdi movl $32, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $32, %esi call cudaMalloc@PLT movl $1, %ecx movl $32, %edx movq %rbp, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $8, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L21 .L13: call cudaDeviceSynchronize@PLT movl $2, %ecx movl $32, %edx movq (%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT movq %rbp, %rbx addq $32, %rbp leaq _ZSt4cout(%rip), %r12 jmp .L16 .L21: movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z24__device_stub__Z3sumPiS_PiS_ jmp .L13 .L14: movl $32, %esi call _ZNSo3putEc@PLT .L15: addq $4, %rbx cmpq %rbp, %rbx je .L22 .L16: movl (%rbx), %esi movq %r12, %rdi call _ZNSolsEi@PLT movq %rax, %rdi movb $32, 28(%rsp) movq (%rax), %rax movq -24(%rax), %rax cmpq $0, 16(%rdi,%rax) je .L14 leaq 28(%rsp), %rsi movl $1, %edx call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT jmp .L15 .L22: movl $10, %esi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L23 movl $0, %eax addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z3sumPiS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z3sumPiS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z3sumPiS_ ; -- Begin function _Z3sumPiS_ .globl _Z3sumPiS_ .p2align 8 .type _Z3sumPiS_,@function _Z3sumPiS_: ; @_Z3sumPiS_ ; %bb.0: s_load_b128 s[0:3], s[0:1], 0x0 v_lshlrev_b32_e32 v5, 2, v0 s_mov_b32 s8, 0 ; implicit-def: $vgpr7_vgpr8 s_waitcnt lgkmcnt(0) global_load_b32 v6, v5, s[0:1] v_add_co_u32 v1, s4, s0, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v2, null, s1, 0, s4 v_add_co_u32 v3, s4, s2, v5 v_add_co_ci_u32_e64 v4, null, s3, 0, s4 s_mov_b32 s4, exec_lo s_waitcnt vmcnt(0) global_store_b32 v5, v6, s[2:3] ; implicit-def: $vgpr5_vgpr6 v_cmpx_lt_i32_e32 3, v0 s_xor_b32 s9, exec_lo, s4 s_cbranch_execz .LBB0_10 ; %bb.1: ; %NodeBlock52 s_mov_b32 s10, exec_lo ; implicit-def: $sgpr4_sgpr5 ; implicit-def: $sgpr6_sgpr7 v_cmpx_lt_i32_e32 5, v0 s_xor_b32 s10, exec_lo, s10 s_cbranch_execz .LBB0_5 ; %bb.2: ; %LeafBlock50 s_mov_b32 s11, exec_lo ; implicit-def: $sgpr4_sgpr5 ; implicit-def: $sgpr6_sgpr7 v_cmpx_eq_u32_e32 6, v0 ; %bb.3: s_add_u32 s4, s0, 28 s_addc_u32 s5, s1, 0 s_add_u32 s6, s2, 24 s_mov_b32 s8, exec_lo s_addc_u32 s7, s3, 0 ; %bb.4: ; %Flow67 s_or_b32 exec_lo, exec_lo, s11 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 s8, s8, exec_lo .LBB0_5: ; %Flow66 s_or_saveexec_b32 s10, s10 v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4 v_dual_mov_b32 v8, s7 :: v_dual_mov_b32 v7, s6 s_xor_b32 exec_lo, exec_lo, s10 s_cbranch_execz .LBB0_9 ; %bb.6: ; %LeafBlock48 s_mov_b32 s11, s8 s_mov_b32 s12, exec_lo ; implicit-def: $sgpr4_sgpr5 ; implicit-def: $sgpr6_sgpr7 v_cmpx_eq_u32_e32 4, v0 ; %bb.7: s_add_u32 s4, s0, 20 s_addc_u32 s5, s1, 0 s_add_u32 s6, s2, 16 s_addc_u32 s7, s3, 0 s_or_b32 s11, s8, exec_lo ; %bb.8: ; %Flow69 s_or_b32 exec_lo, exec_lo, s12 v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4 v_dual_mov_b32 v8, s7 :: v_dual_mov_b32 v7, s6 s_and_not1_b32 s4, s8, exec_lo s_and_b32 s5, s11, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s8, s4, s5 .LBB0_9: ; %Flow68 s_or_b32 exec_lo, exec_lo, s10 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 s8, s8, exec_lo .LBB0_10: ; %Flow65 s_and_not1_saveexec_b32 s9, s9 s_cbranch_execz .LBB0_20 ; %bb.11: ; %NodeBlock s_mov_b32 s10, s8 s_mov_b32 s11, exec_lo ; implicit-def: $sgpr4_sgpr5 ; implicit-def: $sgpr6_sgpr7 v_cmpx_lt_i32_e32 1, v0 s_xor_b32 s11, exec_lo, s11 s_cbranch_execz .LBB0_15 ; %bb.12: ; %LeafBlock46 s_mov_b32 s12, s8 s_mov_b32 s10, exec_lo ; implicit-def: $sgpr4_sgpr5 ; implicit-def: $sgpr6_sgpr7 v_cmpx_eq_u32_e32 2, v0 ; %bb.13: s_add_u32 s4, s0, 12 s_addc_u32 s5, s1, 0 s_add_u32 s6, s2, 8 s_addc_u32 s7, s3, 0 s_or_b32 s12, s8, exec_lo ; %bb.14: ; %Flow72 s_or_b32 exec_lo, exec_lo, s10 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_and_not1_b32 s10, s8, exec_lo s_and_b32 s12, s12, exec_lo s_or_b32 s10, s10, s12 .LBB0_15: ; %Flow71 s_or_saveexec_b32 s11, s11 v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4 v_dual_mov_b32 v8, s7 :: v_dual_mov_b32 v7, s6 s_xor_b32 exec_lo, exec_lo, s11 s_cbranch_execz .LBB0_19 ; %bb.16: ; %LeafBlock s_mov_b32 s6, s10 s_mov_b32 s7, exec_lo ; implicit-def: $sgpr4_sgpr5 v_cmpx_eq_u32_e32 0, v0 ; %bb.17: s_add_u32 s4, s0, 4 s_addc_u32 s5, s1, 0 s_or_b32 s6, s10, exec_lo ; %bb.18: ; %Flow74 s_or_b32 exec_lo, exec_lo, s7 v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4 s_and_not1_b32 s4, s10, exec_lo s_and_b32 s5, s6, exec_lo v_dual_mov_b32 v8, s3 :: v_dual_mov_b32 v7, s2 s_or_b32 s10, s4, s5 .LBB0_19: ; %Flow73 s_or_b32 exec_lo, exec_lo, s11 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_and_not1_b32 s4, s8, exec_lo s_and_b32 s5, s10, exec_lo s_or_b32 s8, s4, s5 .LBB0_20: ; %Flow70 s_or_b32 exec_lo, exec_lo, s9 s_and_saveexec_b32 s4, s8 s_cbranch_execz .LBB0_22 ; %bb.21: ; %.sink.split global_load_b32 v5, v[5:6], off global_load_b32 v6, v[7:8], off s_waitcnt vmcnt(0) v_add_nc_u32_e32 v5, v6, v5 global_store_b32 v[7:8], v5, off .LBB0_22: s_or_b32 exec_lo, exec_lo, s4 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv global_load_b32 v5, v[3:4], off s_mov_b32 s8, 0 s_mov_b32 s9, exec_lo ; implicit-def: $sgpr4_sgpr5 ; implicit-def: $sgpr6_sgpr7 s_waitcnt vmcnt(0) global_store_b32 v[1:2], v5, off v_cmpx_lt_i32_e32 3, v0 s_xor_b32 s9, exec_lo, s9 s_cbranch_execz .LBB0_26 ; %bb.23: ; %LeafBlock58 s_mov_b32 s10, exec_lo ; implicit-def: $sgpr4_sgpr5 ; implicit-def: $sgpr6_sgpr7 v_cmpx_eq_u32_e32 4, v0 ; %bb.24: s_add_u32 s4, s2, 24 s_addc_u32 s5, s3, 0 s_add_u32 s6, s0, 16 s_mov_b32 s8, exec_lo s_addc_u32 s7, s1, 0 ; %bb.25: ; %Flow62 s_or_b32 exec_lo, exec_lo, s10 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 s8, s8, exec_lo .LBB0_26: ; %Flow s_or_saveexec_b32 s9, s9 v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4 v_dual_mov_b32 v8, s7 :: v_dual_mov_b32 v7, s6 s_xor_b32 exec_lo, exec_lo, s9 s_cbranch_execz .LBB0_30 ; %bb.27: ; %LeafBlock56 s_mov_b32 s6, s8 s_mov_b32 s7, exec_lo ; implicit-def: $sgpr4_sgpr5 v_cmpx_eq_u32_e32 0, v0 ; %bb.28: s_add_u32 s4, s2, 8 s_addc_u32 s5, s3, 0 s_or_b32 s6, s8, exec_lo ; %bb.29: ; %Flow64 s_or_b32 exec_lo, exec_lo, s7 v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4 v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0 s_and_not1_b32 s4, s8, exec_lo s_and_b32 s5, s6, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s8, s4, s5 .LBB0_30: ; %Flow63 s_or_b32 exec_lo, exec_lo, s9 s_and_saveexec_b32 s4, s8 s_cbranch_execz .LBB0_32 ; %bb.31: ; %.sink.split37 global_load_b32 v5, v[5:6], off global_load_b32 v6, v[7:8], off s_waitcnt vmcnt(0) v_add_nc_u32_e32 v5, v6, v5 global_store_b32 v[7:8], v5, off .LBB0_32: s_or_b32 exec_lo, exec_lo, s4 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv global_load_b32 v5, v[1:2], off s_mov_b32 s4, exec_lo s_waitcnt vmcnt(0) global_store_b32 v[3:4], v5, off v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_34 ; %bb.33: v_mov_b32_e32 v0, 0 s_clause 0x1 global_load_b32 v5, v0, s[0:1] offset:16 global_load_b32 v6, v0, s[2:3] s_waitcnt vmcnt(0) v_add_nc_u32_e32 v5, v6, v5 global_store_b32 v0, v5, s[2:3] .LBB0_34: s_or_b32 exec_lo, exec_lo, s4 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv global_load_b32 v0, v[3:4], off s_waitcnt vmcnt(0) global_store_b32 v[1:2], v0, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z3sumPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 13 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z3sumPiS_, .Lfunc_end0-_Z3sumPiS_ ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 860 ; NumSgprs: 13 ; NumVgprs: 9 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 1 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 13 ; NumVGPRsForWavesPerEU: 9 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z3sumPiS_ .private_segment_fixed_size: 0 .sgpr_count: 13 .sgpr_spill_count: 0 .symbol: _Z3sumPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "d9285c76cb23c3f75ec66349d64dd9f598fca74f.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z18__device_stub__sumPiS_ # -- Begin function _Z18__device_stub__sumPiS_ .p2align 4, 0x90 .type _Z18__device_stub__sumPiS_,@function _Z18__device_stub__sumPiS_: # @_Z18__device_stub__sumPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z3sumPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z18__device_stub__sumPiS_, .Lfunc_end0-_Z18__device_stub__sumPiS_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $112, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $32, %edi callq malloc movq %rax, %rbx xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl %eax, (%rbx,%rax,4) incq %rax cmpq $8, %rax jne .LBB1_1 # %bb.2: leaq 8(%rsp), %rdi movl $32, %esi callq hipMalloc leaq 40(%rsp), %rdi movl $32, %esi callq hipMalloc movq 8(%rsp), %rdi movl $32, %edx movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 7(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 8(%rsp), %rax movq 40(%rsp), %rcx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) leaq 104(%rsp), %rax movq %rax, 16(%rsp) leaq 96(%rsp), %rax movq %rax, 24(%rsp) leaq 80(%rsp), %rdi leaq 64(%rsp), %rsi leaq 56(%rsp), %rdx leaq 48(%rsp), %rcx callq __hipPopCallConfiguration movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 64(%rsp), %rcx movl 72(%rsp), %r8d leaq 16(%rsp), %r9 movl $_Z3sumPiS_, %edi pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: callq hipDeviceSynchronize movq 8(%rsp), %rsi movl $32, %edx movq %rbx, %rdi movl $2, %ecx callq hipMemcpy xorl %r15d, %r15d leaq 16(%rsp), %r14 jmp .LBB1_5 .p2align 4, 0x90 .LBB1_11: # in Loop: Header=BB1_5 Depth=1 movq %rax, %rdi movl $32, %esi callq _ZNSo3putEc .LBB1_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit16 # in Loop: Header=BB1_5 Depth=1 incq %r15 cmpq $8, %r15 je .LBB1_7 .LBB1_5: # =>This Inner Loop Header: Depth=1 movl (%rbx,%r15,4), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movb $32, 16(%rsp) movq (%rax), %rcx movq -24(%rcx), %rcx cmpq $0, 16(%rax,%rcx) je .LBB1_11 # %bb.6: # in Loop: Header=BB1_5 Depth=1 movl $1, %edx movq %rax, %rdi movq %r14, %rsi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_12 .LBB1_7: movb $10, 16(%rsp) movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax cmpq $0, _ZSt4cout+16(%rax) je .LBB1_9 # %bb.8: leaq 16(%rsp), %rsi movl $_ZSt4cout, %edi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_10 .LBB1_9: movl $_ZSt4cout, %edi movl $10, %esi callq _ZNSo3putEc .LBB1_10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit xorl %eax, %eax addq $112, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3sumPiS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z3sumPiS_,@object # @_Z3sumPiS_ .section .rodata,"a",@progbits .globl _Z3sumPiS_ .p2align 3, 0x0 _Z3sumPiS_: .quad _Z18__device_stub__sumPiS_ .size _Z3sumPiS_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z3sumPiS_" .size .L__unnamed_1, 11 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__sumPiS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3sumPiS_ .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
2,440
2,917
4,815
3,339
196
code for sm_80 Function : _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R11, SR_CTAID.Y ; S2R R0, SR_TID.Y ; S2R R2, SR_CTAID.X ; S2R R3, SR_TID.X ; S2R R8, SR_CTAID.Z ; S2R R5, SR_TID.Z ; IMAD R11, R11, c[0x0][0x4], R0 ; ISETP.GE.AND P0, PT, R11, c[0x0][0x1f4], PT ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GE.OR P0, PT, R2, c[0x0][0x1f0], P0 ; IMAD R8, R8, c[0x0][0x8], R5 ; ISETP.GE.OR P0, PT, R8, c[0x0][0x1f8], P0 ; @P0 EXIT ; I2F.F64 R8, R8 ; ULDC UR4, c[0x0][0x1f8] ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; UIADD3 UR4, UR4, -0x1, URZ ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; ULDC.64 UR6, c[0x0][0x1f0] ; IMAD.MOV.U32 R10, RZ, RZ, 0x8 ; UIADD3 UR5, UR7, -0x1, URZ ; I2F.F64 R4, R11 ; DSETP.MAX.AND P2, P5, RZ, R8, PT ; I2F.F64 R2, R2 ; IMAD.MOV.U32 R13, RZ, RZ, R8 ; FSEL R19, R0, R9, P2 ; DSETP.MAX.AND P3, P4, RZ, R4, PT ; I2F.F64 R6, UR4 ; SEL R12, R12, R13, P2 ; UIADD3 UR4, UR6, -0x1, URZ ; @P5 LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; ULDC.64 UR6, c[0x0][0x118] ; DSETP.MAX.AND P0, P1, RZ, R2, PT ; IMAD.MOV.U32 R17, RZ, RZ, R3 ; MOV R13, R19 ; IMAD.MOV.U32 R3, RZ, RZ, R4 ; I2F.F64 R8, UR5 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; FSEL R19, R0, R5, P3 ; IMAD.MOV.U32 R15, RZ, RZ, R2 ; DSETP.GT.AND P2, PT, R12, R6, PT ; @P4 LOP3.LUT R19, R5, 0x80000, RZ, 0xfc, !PT ; SEL R4, R4, R3, P3 ; I2F.F64 R2, UR4 ; FSEL R12, R6, R12, P2 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R13, R7, R13, P2 ; IMAD.MOV.U32 R5, RZ, RZ, R19 ; FSEL R7, R0, R17, P0 ; SEL R6, R6, R15, P0 ; F2I.F64.TRUNC R12, R12 ; @P1 LOP3.LUT R7, R17, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P2, PT, R4, R8, PT ; DSETP.GT.AND P0, PT, R6, R2, PT ; FSEL R14, R8, R4, P2 ; FSEL R15, R9, R5, P2 ; FSEL R6, R2, R6, P0 ; F2I.F64.TRUNC R5, R14 ; FSEL R7, R3, R7, P0 ; F2I.F64.TRUNC R4, R6 ; IMAD R3, R12, c[0x0][0x1f4], R5 ; IMAD R13, R3, c[0x0][0x1f0], R4 ; IMAD.WIDE R56, R13, R10, c[0x0][0x190] ; LDG.E.64 R56, [R56.64] ; IMAD.MOV.U32 R40, RZ, RZ, c[0x0][0x200] ; BSSY B0, 0x135b0 ; IMAD.MOV.U32 R41, RZ, RZ, c[0x0][0x204] ; DMUL R18, R40, c[0x2][0x0] ; DSETP.GEU.AND P0, PT, R56, R18, PT ; @!P0 BRA 0x135a0 ; IMAD.SHL.U32 R2, R13, 0x8, RZ ; SHF.R.S32.HI R0, RZ, 0x1f, R13 ; SHF.L.U64.HI R0, R13, 0x3, R0 ; IADD3 R6, P0, R2, c[0x0][0x198], RZ ; IADD3.X R7, R0, c[0x0][0x19c], RZ, P0, !PT ; LDG.E.64 R6, [R6.64] ; DSETP.GEU.AND P0, PT, R6, R18, PT ; @!P0 BRA 0x135a0 ; IADD3 R16, P0, R2, c[0x0][0x1a0], RZ ; IADD3.X R17, R0, c[0x0][0x1a4], RZ, P0, !PT ; LDG.E.64 R16, [R16.64] ; DSETP.GEU.AND P0, PT, R16, R18, PT ; @!P0 BRA 0x135a0 ; IADD3 R14, P0, R2, c[0x0][0x1a8], RZ ; IADD3.X R15, R0, c[0x0][0x1ac], RZ, P0, !PT ; LDG.E.64 R14, [R14.64] ; DSETP.GEU.AND P0, PT, R14, R18, PT ; @!P0 BRA 0x135a0 ; IADD3 R46, P0, R2, c[0x0][0x1b0], RZ ; IADD3.X R47, R0, c[0x0][0x1b4], RZ, P0, !PT ; LDG.E.64 R46, [R46.64] ; DSETP.GEU.AND P0, PT, R46, R18, PT ; @!P0 BRA 0x135a0 ; IADD3 R50, P0, R2, c[0x0][0x1b8], RZ ; IADD3.X R51, R0, c[0x0][0x1bc], RZ, P0, !PT ; LDG.E.64 R50, [R50.64] ; DSETP.GEU.AND P0, PT, R50, R18, PT ; @!P0 BRA 0x135a0 ; IADD3 R18, R11.reuse, 0x1, RZ ; IADD3 R20, R11.reuse, 0x2, RZ ; IADD3 R24, R11.reuse, -0x1, RZ ; I2F.F64 R18, R18 ; IADD3 R22, R11.reuse, 0x3, RZ ; IADD3 R26, R11, -0x3, RZ ; I2F.F64 R20, R20 ; I2F.F64 R24, R24 ; DSETP.MAX.AND P0, P3, RZ, R18, PT ; MOV R13, R18 ; DSETP.MAX.AND P5, P6, RZ, R20, PT ; IMAD.MOV.U32 R27, RZ, RZ, R20 ; I2F.F64 R22, R22 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; IMAD.MOV.U32 R18, RZ, RZ, R21 ; SEL R20, R20, R13, P0 ; IMAD.MOV.U32 R13, RZ, RZ, RZ ; MOV R32, R25 ; IMAD.MOV.U32 R31, RZ, RZ, R24 ; FSEL R21, R13, R19, P0 ; DSETP.MAX.AND P1, P0, RZ, R24, PT ; @P3 LOP3.LUT R21, R19, 0x80000, RZ, 0xfc, !PT ; IADD3 R24, R11, -0x2, RZ ; DSETP.MAX.AND P2, P4, RZ, R22, PT ; IMAD.MOV.U32 R29, RZ, RZ, R22 ; IMAD.MOV.U32 R30, RZ, RZ, R23 ; FSEL R23, R13, R18, P5 ; I2F.F64 R24, R24 ; IMAD.MOV.U32 R22, RZ, RZ, RZ ; @P6 LOP3.LUT R23, R18, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P3, PT, R20, R8, PT ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; IMAD.MOV.U32 R11, RZ, RZ, RZ ; SEL R22, R22, R27, P5 ; I2F.F64 R26, R26 ; SEL R18, R18, R29, P2 ; FSEL R28, R8, R20, P3 ; DSETP.GT.AND P5, PT, R22, R8, PT ; FSEL R29, R9, R21, P3 ; FSEL R19, R11.reuse, R30, P2 ; DSETP.MAX.AND P2, P3, RZ, R24, PT ; @P4 LOP3.LUT R19, R30, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R34, RZ, RZ, R25 ; MOV R20, RZ ; IMAD.MOV.U32 R13, RZ, RZ, R24 ; FSEL R21, R11, R32, P1 ; F2I.F64.TRUNC R29, R28 ; @P0 LOP3.LUT R21, R32, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P0, PT, R18, R8, PT ; SEL R20, R20, R31, P1 ; IMAD.MOV.U32 R33, RZ, RZ, R26 ; FSEL R22, R8, R22, P5 ; IMAD.MOV.U32 R30, RZ, RZ, R27 ; FSEL R23, R9, R23, P5 ; DSETP.MAX.AND P4, P5, RZ, R26, PT ; FSEL R11, R11, R34, P2 ; FSEL R24, R8, R18, P0 ; DSETP.GT.AND P1, PT, R20, R8.reuse, PT ; IMAD.MOV.U32 R18, RZ, RZ, RZ ; @P3 LOP3.LUT R11, R34, 0x80000, RZ, 0xfc, !PT ; F2I.F64.TRUNC R23, R22 ; FSEL R25, R9.reuse, R19, P0 ; IMAD R29, R12, c[0x0][0x1f4], R29 ; SEL R18, R18, R13, P2 ; IMAD.MOV.U32 R19, RZ, RZ, R11 ; FSEL R26, R8, R20, P1 ; IMAD.MOV.U32 R13, RZ, RZ, RZ ; FSEL R27, R9, R21, P1 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; F2I.F64.TRUNC R25, R24 ; DSETP.GT.AND P0, PT, R18, R8, PT ; FSEL R21, R13, R30, P4 ; SEL R20, R20, R33, P4 ; @P5 LOP3.LUT R21, R30, 0x80000, RZ, 0xfc, !PT ; IMAD R23, R12, c[0x0][0x1f4], R23 ; FSEL R18, R8, R18, P0 ; F2I.F64.TRUNC R27, R26 ; FSEL R19, R9, R19, P0 ; DSETP.GT.AND P0, PT, R20, R8, PT ; IMAD R25, R12, c[0x0][0x1f4], R25 ; F2I.F64.TRUNC R19, R18 ; FSEL R9, R9, R21, P0 ; FSEL R8, R8, R20, P0 ; IMAD R21, R29, c[0x0][0x1f0], R4 ; IADD3 R48, P0, R2, c[0x0][0x170], RZ ; F2I.F64.TRUNC R9, R8 ; IMAD R27, R12, c[0x0][0x1f4], R27 ; IADD3.X R49, R0, c[0x0][0x174], RZ, P0, !PT ; IMAD R23, R23, c[0x0][0x1f0], R4 ; IMAD R11, R12, c[0x0][0x1f4], R19 ; LDG.E.64 R48, [R48.64] ; IMAD R27, R27, c[0x0][0x1f0], R4.reuse ; IMAD R11, R11, c[0x0][0x1f0], R4.reuse ; IMAD R13, R12, c[0x0][0x1f4], R9 ; IMAD R35, R25, c[0x0][0x1f0], R4.reuse ; IMAD R13, R13, c[0x0][0x1f0], R4 ; IMAD.WIDE R36, R11, R10, c[0x0][0x170] ; IMAD.WIDE R28, R13, R10.reuse, c[0x0][0x170] ; LDG.E.64 R36, [R36.64] ; IMAD.WIDE R24, R27, R10.reuse, c[0x0][0x170] ; LDG.E.64 R28, [R28.64] ; IMAD.WIDE R20, R21, R10.reuse, c[0x0][0x170] ; LDG.E.64 R24, [R24.64] ; IMAD.WIDE R32, R23, R10, c[0x0][0x170] ; LDG.E.64 R20, [R20.64] ; IMAD.WIDE R34, R35, R10, c[0x0][0x170] ; LDG.E.64 R32, [R32.64] ; LDG.E.64 R34, [R34.64] ; DSETP.GEU.AND P0, PT, R6, c[0x0][0x200], PT ; DSETP.GEU.AND P1, PT, R56, c[0x0][0x200], PT ; BSSY B2, 0x6a50 ; IMAD.MOV.U32 R72, RZ, RZ, c[0x0][0x200] ; MOV R19, c[0x0][0x20c] ; IMAD.MOV.U32 R73, RZ, RZ, c[0x0][0x204] ; IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x208] ; IMAD.MOV.U32 R44, RZ, RZ, c[0x0][0x210] ; IMAD.MOV.U32 R45, RZ, RZ, c[0x0][0x214] ; @P0 BRA P1, 0x28e0 ; IADD3 R22, P1, R2, c[0x0][0x1c0], RZ ; IADD3.X R23, R0, c[0x0][0x1c4], RZ, P1, !PT ; LDG.E.64 R22, [R22.64] ; IADD3 R30, P1, R2, c[0x0][0x1c8], RZ ; IADD3.X R31, R0, c[0x0][0x1cc], RZ, P1, !PT ; LDG.E.64 R30, [R30.64] ; DSETP.GEU.AND P1, PT, R56, c[0x0][0x200], PT ; IMAD.MOV.U32 R52, RZ, RZ, c[0x0][0x200] ; BSSY B3, 0x1150 ; IMAD.MOV.U32 R53, RZ, RZ, c[0x0][0x204] ; DADD R54, R40.reuse, c[0x0][0x200] ; IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; @!P0 MOV R72, R6 ; @!P0 IMAD.MOV.U32 R73, RZ, RZ, R7 ; DMUL R42, R40, -2 ; @!P0 IMAD.MOV.U32 R28, RZ, RZ, R36 ; @!P0 IMAD.MOV.U32 R29, RZ, RZ, R37 ; @P1 DMUL R8, R40.reuse, 3 ; @P1 IMAD.MOV.U32 R52, RZ, RZ, R54 ; @P1 IMAD.MOV.U32 R53, RZ, RZ, R55 ; @P0 DMUL R40, R40, -3 ; @P1 IMAD.MOV.U32 R56, RZ, RZ, c[0x0][0x200] ; @P1 IMAD.MOV.U32 R57, RZ, RZ, c[0x0][0x204] ; @P1 IMAD.MOV.U32 R54, RZ, RZ, R8 ; @P1 MOV R55, R9 ; @!P0 IMAD.MOV.U32 R40, RZ, RZ, R42 ; @!P0 IMAD.MOV.U32 R41, RZ, RZ, R43 ; @!P0 DADD R42, -RZ, -c[0x0][0x200] ; DADD R8, -R52, R54 ; MUFU.RCP64H R11, R9 ; DFMA R12, -R8, R10, 1 ; DFMA R12, R12, R12, R12 ; DFMA R12, R10, R12, R10 ; DFMA R10, -R8, R12, 1 ; DFMA R10, R12, R10, R12 ; @P1 IMAD.MOV.U32 R22, RZ, RZ, R20 ; @P1 IMAD.MOV.U32 R23, RZ, RZ, R21 ; @P1 IMAD.MOV.U32 R20, RZ, RZ, R32 ; @P1 IMAD.MOV.U32 R21, RZ, RZ, R33 ; @P1 IMAD.MOV.U32 R32, RZ, RZ, R34 ; @P1 IMAD.MOV.U32 R33, RZ, RZ, R35 ; @P0 IMAD.MOV.U32 R30, RZ, RZ, R24 ; @P0 MOV R24, R36 ; @P0 IMAD.MOV.U32 R31, RZ, RZ, R25 ; DADD R32, R32, -R20 ; @P0 IMAD.MOV.U32 R25, RZ, RZ, R37 ; DMUL R26, R32, R10 ; FSETP.GEU.AND P3, PT, |R33|, 6.5827683646048100446e-37, PT ; DFMA R12, -R8, R26, R32 ; DFMA R26, R10, R12, R26 ; FFMA R10, RZ, R9, R27 ; FSETP.GT.AND P2, PT, |R10|, 1.469367938527859385e-39, PT ; @P2 BRA P3, 0x1140 ; IMAD.MOV.U32 R10, RZ, RZ, R32 ; MOV R6, 0x1120 ; IMAD.MOV.U32 R7, RZ, RZ, R33 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R26, RZ, RZ, R8 ; IMAD.MOV.U32 R27, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, R52, -R56 ; MOV R6, 0x1 ; BSSY B3, 0x12d0 ; DADD R12, -R22, R20 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R20, R12, R6 ; DFMA R10, -R8, R20, R12 ; DFMA R20, R6, R10, R20 ; FFMA R6, RZ, R9, R21 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x12c0 ; IMAD.MOV.U32 R10, RZ, RZ, R12 ; MOV R6, 0x12a0 ; IMAD.MOV.U32 R7, RZ, RZ, R13 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R20, RZ, RZ, R8 ; IMAD.MOV.U32 R21, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R57 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R48, R22 ; BSSY B3, 0x1450 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R56, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R56, 1 ; DFMA R6, R8, R6, R8 ; DMUL R38, R10, R6 ; DFMA R8, R38, -R56, R10 ; DFMA R38, R6, R8, R38 ; FFMA R6, RZ, R57, R39 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1440 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R9, R57 ; IMAD.MOV.U32 R8, RZ, RZ, R56 ; MOV R6, 0x1420 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R38, RZ, RZ, R8 ; IMAD.MOV.U32 R39, RZ, RZ, R7 ; BSYNC B3 ; DADD R22, RZ, R72 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x15e0 ; DADD R10, R48, -R30 ; MUFU.RCP64H R7, R23 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R22, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R22, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R36, R10, R6 ; DFMA R8, -R22, R36, R10 ; DFMA R36, R6, R8, R36 ; FFMA R6, RZ, R23, R37 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x15d0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x15b0 ; IMAD.MOV.U32 R8, RZ, RZ, R22 ; IMAD.MOV.U32 R9, RZ, RZ, R23 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R36, RZ, RZ, R8 ; MOV R37, R7 ; BSYNC B3 ; DADD R8, -R42, -R72 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x1760 ; DADD R30, R30, -R24 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R31|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R34, R30, R6 ; DFMA R10, -R8, R34, R30 ; DFMA R34, R6, R10, R34 ; FFMA R6, RZ, R9, R35 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1750 ; IMAD.MOV.U32 R10, RZ, RZ, R30 ; MOV R6, 0x1730 ; IMAD.MOV.U32 R7, RZ, RZ, R31 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R34, RZ, RZ, R8 ; IMAD.MOV.U32 R35, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, -R40, R42 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x18e0 ; DADD R24, R24, -R28 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R25|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R32, R24, R6 ; DFMA R10, -R8, R32, R24 ; DFMA R32, R6, R10, R32 ; FFMA R6, RZ, R9, R33 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x18d0 ; IMAD.MOV.U32 R10, RZ, RZ, R24 ; MOV R7, R25 ; MOV R6, 0x18b0 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R32, RZ, RZ, R8 ; IMAD.MOV.U32 R33, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, R54, -R56 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x1a60 ; DADD R26, -R20, R26 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R27|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R30, R26, R6 ; DFMA R10, -R8, R30, R26 ; DFMA R30, R6, R10, R30 ; FFMA R6, RZ, R9, R31 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1a50 ; IMAD.MOV.U32 R10, RZ, RZ, R26 ; MOV R6, 0x1a30 ; IMAD.MOV.U32 R7, RZ, RZ, R27 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; IMAD.MOV.U32 R31, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R53 ; MOV R6, 0x1 ; DADD R10, -R38, R20 ; BSSY B3, 0x1be0 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R52, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R52, 1 ; DFMA R6, R8, R6, R8 ; DMUL R28, R10, R6 ; DFMA R8, R28, -R52, R10 ; DFMA R28, R6, R8, R28 ; FFMA R6, RZ, R53, R29 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1bd0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x1bb0 ; IMAD.MOV.U32 R8, RZ, RZ, R52 ; IMAD.MOV.U32 R9, RZ, RZ, R53 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R28, RZ, RZ, R8 ; IMAD.MOV.U32 R29, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, R56, R72 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x1d60 ; DADD R12, -R36, R38 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R26, R12, R6 ; DFMA R10, -R8, R26, R12 ; DFMA R26, R6, R10, R26 ; FFMA R6, RZ, R9, R27 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1d50 ; IMAD.MOV.U32 R10, RZ, RZ, R12 ; MOV R7, R13 ; MOV R6, 0x1d30 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R26, RZ, RZ, R8 ; IMAD.MOV.U32 R27, RZ, RZ, R7 ; BSYNC B3 ; DADD R20, RZ, -R42 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x1ef0 ; DADD R10, -R34, R36 ; MUFU.RCP64H R7, R21 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R20, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R20, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R24, R10, R6 ; DFMA R8, -R20, R24, R10 ; DFMA R24, R6, R8, R24 ; FFMA R6, RZ, R21, R25 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1ee0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x1ec0 ; IMAD.MOV.U32 R8, RZ, RZ, R20 ; IMAD.MOV.U32 R9, RZ, RZ, R21 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R24, RZ, RZ, R8 ; MOV R25, R7 ; BSYNC B3 ; DADD R8, -R40, -R72 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x2070 ; DADD R34, -R32, R34 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R35|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R32, R34, R6 ; DFMA R10, -R8, R32, R34 ; DFMA R32, R6, R10, R32 ; FFMA R6, RZ, R9, R33 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2060 ; IMAD.MOV.U32 R10, RZ, RZ, R34 ; MOV R6, 0x2040 ; IMAD.MOV.U32 R7, RZ, RZ, R35 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R32, RZ, RZ, R8 ; IMAD.MOV.U32 R33, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R55 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R28, R30 ; BSSY B3, 0x21f0 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R54, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R54, 1 ; DFMA R6, R8, R6, R8 ; DMUL R30, R10, R6 ; DFMA R8, R30, -R54, R10 ; DFMA R30, R6, R8, R30 ; FFMA R6, RZ, R55, R31 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x21e0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R8, R54 ; IMAD.MOV.U32 R9, RZ, RZ, R55 ; MOV R6, 0x21c0 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; IMAD.MOV.U32 R31, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, R52, R72 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x2370 ; DADD R12, -R26, R28 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R34, R12, R6 ; DFMA R10, -R8, R34, R12 ; DFMA R34, R6, R10, R34 ; FFMA R6, RZ, R9, R35 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2360 ; IMAD.MOV.U32 R10, RZ, RZ, R12 ; MOV R6, 0x2340 ; IMAD.MOV.U32 R7, RZ, RZ, R13 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R34, RZ, RZ, R8 ; MOV R35, R7 ; BSYNC B3 ; DADD R8, -R42, R56 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x24f0 ; DADD R12, -R24, R26 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R42, R12, R6 ; DFMA R10, -R8, R42, R12 ; DFMA R42, R6, R10, R42 ; FFMA R6, RZ, R9, R43 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x24e0 ; IMAD.MOV.U32 R10, RZ, RZ, R12 ; MOV R6, 0x24c0 ; IMAD.MOV.U32 R7, RZ, RZ, R13 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R42, RZ, RZ, R8 ; IMAD.MOV.U32 R43, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, RZ, -R40 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x2660 ; DADD R32, -R32, R24 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R33|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R10, R32, R6 ; DFMA R12, -R8, R10, R32 ; DFMA R6, R6, R12, R10 ; FFMA R10, RZ, R9, R7 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2650 ; IMAD.MOV.U32 R10, RZ, RZ, R32 ; MOV R7, R33 ; MOV R6, 0x2640 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; BSYNC B3 ; DMUL R8, R24, R26 ; DSETP.GEU.AND P0, PT, |R42|, |R6|, PT ; DSETP.GEU.AND P4, PT, R8, RZ, PT ; FSEL R8, R42, R6, !P0 ; FSEL R9, R43, R7, !P0 ; DADD R56, RZ, -R56 ; DADD R52, RZ, -R52 ; DSETP.GEU.AND P2, PT, |R34|, |R30|, PT ; DMUL R10, R26, R28 ; FSEL R12, R34, R30, !P2 ; DMUL R6, R22, R20 ; FSEL R13, R35, R31, !P2 ; DSETP.GEU.AND P0, PT, |R42|, |R34|, PT ; DMUL R52, R56, R52 ; DSETP.GEU.AND P5, PT, R10, RZ, PT ; FSEL R10, R42, R34, !P0 ; DMUL R6, R6, R8 ; FSEL R11, R43, R35, !P0 ; DSETP.GEU.AND P1, PT, |R24|, |R26|, PT ; DSETP.GEU.AND P3, PT, |R26|, |R28|, PT ; FSEL R20, R24, R26, !P1 ; DMUL R8, R22, R56 ; FSEL R24, R25, R27, !P1 ; DMUL R52, R52, R12 ; FSEL R12, R26, R28, !P3 ; FSEL R26, R27, R29, !P3 ; DMUL R8, R8, R10 ; FSEL R12, R12, RZ, P5 ; FSEL R10, R20, RZ, P4 ; FSEL R11, R24, RZ, P4 ; FSEL R13, R26, RZ, P5 ; FSEL R42, R6, R8, !P1 ; DFMA R22, R22, R10, R36 ; FSEL R43, R7, R9, !P1 ; FSEL R40, R8, R52, !P3 ; DFMA R38, R56, R12, R38 ; FSEL R41, R9, R53, !P3 ; DADD R42, R22, R42 ; DADD R40, R38, R40 ; BRA 0x6a40 ; MUFU.RCP64H R7, c[0x0][0x204] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, R36, -R28 ; BSSY B3, 0x2a60 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R40, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R40, R8, -R40, 1 ; DFMA R40, R8, R40, R8 ; DMUL R30, R10, R40 ; DFMA R6, R30, -c[0x0][0x200], R10 ; DFMA R30, R40, R6, R30 ; FFMA R6, RZ, c[0x0][0x204], R31 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2a50 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x2a30 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x200] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x204] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; IMAD.MOV.U32 R31, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x204] ; MOV R8, c[0x0][0x200] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x204] ; BSSY B3, 0x2c00 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, -R36, R24 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R28, R8, R10 ; DFMA R6, R28, -c[0x0][0x200], R10 ; DFMA R28, R8, R6, R28 ; FFMA R6, RZ, c[0x0][0x204], R29 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2bf0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x2bd0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x200] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x204] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R28, RZ, RZ, R8 ; IMAD.MOV.U32 R29, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x204] ; MOV R8, c[0x0][0x200] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x204] ; BSSY B3, 0x2da0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, R48, -R24 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R26, R8, R10 ; DFMA R6, R26, -c[0x0][0x200], R10 ; DFMA R26, R8, R6, R26 ; FFMA R6, RZ, c[0x0][0x204], R27 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2d90 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x2d70 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x200] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x204] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R26, RZ, RZ, R8 ; IMAD.MOV.U32 R27, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x204] ; MOV R8, c[0x0][0x200] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x204] ; BSSY B3, 0x2f40 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, -R48, R20 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R24, R8, R10 ; DFMA R6, R24, -c[0x0][0x200], R10 ; DFMA R24, R8, R6, R24 ; FFMA R6, RZ, c[0x0][0x204], R25 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2f30 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x2f10 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x200] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x204] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R24, RZ, RZ, R8 ; IMAD.MOV.U32 R25, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x204] ; MOV R8, c[0x0][0x200] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x204] ; BSSY B3, 0x30e0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, -R20, R32 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R22, R8, R10 ; DFMA R6, R22, -c[0x0][0x200], R10 ; DFMA R22, R8, R6, R22 ; FFMA R6, RZ, c[0x0][0x204], R23 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x30d0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x30b0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x200] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x204] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R22, RZ, RZ, R8 ; IMAD.MOV.U32 R23, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x204] ; MOV R8, c[0x0][0x200] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x204] ; BSSY B3, 0x3280 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, R34, -R32 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R20, R8, R10 ; DFMA R6, R20, -c[0x0][0x200], R10 ; DFMA R20, R8, R6, R20 ; FFMA R6, RZ, c[0x0][0x204], R21 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x3270 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x3250 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x200] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x204] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R20, RZ, RZ, R8 ; IMAD.MOV.U32 R21, RZ, RZ, R7 ; BSYNC B3 ; DADD R6, R28.reuse, R28 ; BSSY B1, 0x3390 ; DMUL R8, R28, c[0x2][0x20] ; DADD R38, -R6, R30 ; DMUL R6, R28, c[0x2][0x8] ; DADD R38, R38, R26 ; DFMA R8, R26, c[0x2][0x28], -R8 ; DADD R10, -RZ, |R38| ; DFMA R6, R30, c[0x2][0x10], R6 ; DFMA R34, R24, c[0x2][0x10], R8 ; MOV R8, R10 ; DFMA R36, R26, c[0x2][0x18], R6 ; MOV R10, 0x3380 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R38, 2 ; BSSY B1, 0x34d0 ; IMAD.MOV.U32 R32, RZ, RZ, R6 ; DSETP.NEU.AND P0, PT, R38, RZ, PT ; IMAD.MOV.U32 R33, RZ, RZ, R7 ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R32, SRZ ; @P1 BRA 0x34c0 ; DSETP.GTU.AND P0, PT, |R38|, +INF , PT ; @P0 BRA 0x34b0 ; ISETP.NE.AND P0, PT, R38, RZ, PT ; LOP3.LUT R38, R39, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R38, 0x7ff00000, P0 ; @P0 BRA 0x34c0 ; IMAD.MOV.U32 R32, RZ, RZ, 0x0 ; IMAD.MOV.U32 R33, RZ, RZ, 0x7ff00000 ; BRA 0x34c0 ; DADD R32, R38, 2 ; BSYNC B1 ; DFMA R38, R28, -4, R30 ; BSSY B1, 0x3570 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R10, 0x3560 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DFMA R38, R26, 3, R38 ; DADD R8, -RZ, |R38| ; MOV R11, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R28, R28 ; BSSY B1, 0x3700 ; DSETP.NEU.AND P1, PT, R38, RZ, PT ; DADD R30, -R8, R30 ; DADD R8, R38, 2 ; DADD R30, R30, R26 ; @!P1 CS2R R6, SRZ ; DMUL R10, R32, c[0x2][0x30] ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; DSETP.NEU.AND P0, PT, R30, 1, PT ; ISETP.NE.AND P2, PT, R8, 0x7ff00000, PT ; FSEL R10, R10, 1.46601546874880000000e+13, P0 ; FSEL R11, R11, 1.8854166269302368164, P0 ; @P2 BRA 0x36f0 ; DSETP.GTU.AND P0, PT, |R38|, +INF , PT ; @P0 BRA 0x36e0 ; ISETP.NE.AND P0, PT, R38, RZ, PT ; LOP3.LUT R8, R39, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x36f0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x36f0 ; DADD R6, R38, 2 ; BSYNC B1 ; DADD R8, R26, R26 ; BSSY B1, 0x3800 ; DMUL R6, R6, 0.25 ; DADD R8, -R8, R28 ; DSETP.NEU.AND P0, PT, R38, 1, PT ; DADD R32, R8, R24 ; FSEL R38, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R39, R7, 1.625, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R8, -RZ, |R32| ; DADD R38, R10, R38 ; MOV R10, 0x37f0 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R32.reuse, 2 ; BSSY B1, 0x3920 ; DSETP.NEU.AND P0, PT, R32, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x3910 ; DSETP.GTU.AND P0, PT, |R32|, +INF , PT ; @P0 BRA 0x3900 ; ISETP.NE.AND P0, PT, R32, RZ, PT ; LOP3.LUT R8, R33, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x3910 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; MOV R7, 0x7ff00000 ; BRA 0x3910 ; DADD R6, R32, 2 ; BSYNC B1 ; DADD R30, -R24, R28 ; BSSY B1, 0x39f0 ; MOV R10, 0x39e0 ; DMUL R6, R6, c[0x2][0x30] ; DADD R8, -RZ, |R30| ; DSETP.NEU.AND P0, PT, R32, 1, PT ; FSEL R32, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; FSEL R33, R7, 1.8854166269302368164, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R30.reuse, 2 ; BSSY B1, 0x3b20 ; DSETP.NEU.AND P0, PT, R30, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x3b10 ; DADD R8, -R24, R28 ; DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; @P0 BRA 0x3b00 ; ISETP.NE.AND P0, PT, R8, RZ, PT ; LOP3.LUT R8, R9, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x3b10 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x3b10 ; DADD R6, R30, 2 ; BSYNC B1 ; DADD R8, R24, R24 ; BSSY B1, 0x3c20 ; MOV R10, 0x3c10 ; DMUL R6, R6, 0.25 ; DADD R8, -R8, R26 ; DSETP.NEU.AND P0, PT, R30, 1, PT ; DADD R40, R8, R22 ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R8, -RZ, |R40| ; DADD R32, R32, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R7, 0x40000000 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R40.reuse, 2 ; BSSY B1, 0x3d40 ; DSETP.NEU.AND P0, PT, R40, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x3d30 ; DSETP.GTU.AND P0, PT, |R40|, +INF , PT ; @P0 BRA 0x3d20 ; ISETP.NE.AND P0, PT, R40, RZ, PT ; LOP3.LUT R8, R41, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x3d30 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x3d30 ; DADD R6, R40, 2 ; BSYNC B1 ; DMUL R8, R26, 3 ; BSSY B1, 0x3e30 ; MOV R10, 0x3e20 ; DMUL R6, R6, c[0x2][0x30] ; DFMA R8, R24, -4, R8 ; DSETP.NEU.AND P0, PT, R40, 1, PT ; DADD R30, R8, R22 ; FSEL R40, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R41, R7, 1.8854166269302368164, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R8, -RZ, |R30| ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R30.reuse, 2 ; BSSY B1, 0x3f50 ; DSETP.NEU.AND P0, PT, R30, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x3f40 ; DSETP.GTU.AND P0, PT, |R30|, +INF , PT ; @P0 BRA 0x3f30 ; ISETP.NE.AND P0, PT, R30, RZ, PT ; LOP3.LUT R8, R31, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x3f40 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x3f40 ; DADD R6, R30, 2 ; BSYNC B1 ; DMUL R6, R6, 0.25 ; BSSY B1, 0x4030 ; MOV R10, 0x4020 ; DADD R38, R38, c[0x2][0x0] ; DSETP.NEU.AND P0, PT, R30, 1, PT ; DADD R8, -RZ, |R38| ; FSEL R30, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R31, R7, 1.625, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R30, R40, R30 ; MOV R11, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R38.reuse, 2 ; BSSY B1, 0x4150 ; DSETP.NEU.AND P0, PT, R38, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x4140 ; DSETP.GTU.AND P0, PT, |R38|, +INF , PT ; @P0 BRA 0x4130 ; ISETP.NE.AND P0, PT, R38, RZ, PT ; LOP3.LUT R8, R39, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x4140 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x4140 ; DADD R6, R38, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0x42b0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x38] ; DFMA R12, R10, -R6, c[0x2][0x38] ; DFMA R8, R8, R12, R10 ; FFMA R10, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA 0x42a0 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R10, 0x9999999a ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; MOV R6, 0x4290 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fb99999 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DADD R32, R32, c[0x2][0x0] ; BSSY B1, 0x4370 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R38, 1, PT ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R32| ; FSEL R38, R8, -1.5881868392106855534e-23, P0 ; FSEL R39, R9, 1.4499999284744262695, P0 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MOV R10, 0x4360 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R32.reuse, 2 ; BSSY B1, 0x4490 ; DSETP.NEU.AND P0, PT, R32, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x4480 ; DSETP.GTU.AND P0, PT, |R32|, +INF , PT ; @P0 BRA 0x4470 ; ISETP.NE.AND P0, PT, R32, RZ, PT ; LOP3.LUT R8, R33, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x4480 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x4480 ; DADD R6, R32, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; MOV R8, 0x1 ; BSSY B3, 0x45f0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x40] ; DFMA R12, R10, -R6, c[0x2][0x40] ; DFMA R8, R8, R12, R10 ; FFMA R10, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA 0x45e0 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x45d0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fe33333 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DADD R30, R30, c[0x2][0x0] ; BSSY B1, 0x46b0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R7, 0x40000000 ; DSETP.NEU.AND P0, PT, R32, 1, PT ; DADD R10, -RZ, |R30| ; FSEL R32, R8, 4.172325063223070174e-08, P0 ; FSEL R33, R9, 1.7749999761581420898, P0 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MOV R10, 0x46a0 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R30.reuse, 2 ; BSSY B1, 0x47d0 ; DSETP.NEU.AND P0, PT, R30, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x47c0 ; DSETP.GTU.AND P0, PT, |R30|, +INF , PT ; @P0 BRA 0x47b0 ; ISETP.NE.AND P0, PT, R30, RZ, PT ; LOP3.LUT R8, R31, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x47c0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x47c0 ; DADD R6, R30, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; DMUL R42, R24, c[0x2][0x28] ; BSSY B3, 0x4970 ; DMUL R52, R22, c[0x2][0x20] ; DMUL R40, R24, c[0x2][0x10] ; DFMA R42, R26, c[0x2][0x10], R42 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x48] ; DFMA R12, R10, -R6, c[0x2][0x48] ; DFMA R8, R8, R12, R10 ; FFMA R10, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA 0x4960 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x4950 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fd33333 ; CALL.REL.NOINC 0x135e0 ; MOV R9, R7 ; BSYNC B3 ; DSETP.NEU.AND P0, PT, R30, 1, PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R39|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x4b40 ; DADD R30, R38, R32 ; FSEL R54, R8, 4.172325063223070174e-08, P0 ; FSEL R55, R9, 1.6499999761581420898, P0 ; DADD R30, R30, R54 ; MUFU.RCP64H R7, R31 ; DFMA R8, -R30, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R30, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R56, R6, R38 ; DFMA R8, -R30, R56, R38 ; DFMA R56, R6, R8, R56 ; FFMA R6, RZ, R31, R57 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x4b30 ; IMAD.MOV.U32 R10, RZ, RZ, R38 ; MOV R6, 0x4b10 ; IMAD.MOV.U32 R7, RZ, RZ, R39 ; IMAD.MOV.U32 R8, RZ, RZ, R30 ; IMAD.MOV.U32 R9, RZ, RZ, R31 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R56, RZ, RZ, R8 ; IMAD.MOV.U32 R57, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R31 ; MOV R6, 0x1 ; BSSY B3, 0x4ce0 ; FSETP.GEU.AND P1, PT, |R33|, 6.5827683646048100446e-37, PT ; DFMA R8, -R30, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R30, R8, 1 ; DFMA R8, R8, R6, R8 ; IMAD.MOV.U32 R6, RZ, RZ, R32 ; IMAD.MOV.U32 R7, RZ, RZ, R33 ; DMUL R38, R8, R6 ; DFMA R6, -R30, R38, R6 ; DFMA R38, R8, R6, R38 ; FFMA R6, RZ, R31, R39 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x4cd0 ; IMAD.MOV.U32 R10, RZ, RZ, R32 ; MOV R6, 0x4cb0 ; IMAD.MOV.U32 R7, RZ, RZ, R33 ; IMAD.MOV.U32 R8, RZ, RZ, R30 ; IMAD.MOV.U32 R9, RZ, RZ, R31 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R38, RZ, RZ, R8 ; MOV R39, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R31 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R55|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x4e70 ; DFMA R8, -R30, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R30, R8, 1 ; DFMA R10, R8, R6, R8 ; IMAD.MOV.U32 R8, RZ, RZ, R54 ; IMAD.MOV.U32 R9, RZ, RZ, R55 ; DMUL R6, R10, R8 ; DFMA R8, -R30, R6, R8 ; DFMA R6, R10, R8, R6 ; FFMA R8, RZ, R31, R7 ; FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x4e60 ; IMAD.MOV.U32 R8, RZ, RZ, R30 ; MOV R6, 0x4e50 ; IMAD.MOV.U32 R9, RZ, RZ, R31 ; IMAD.MOV.U32 R10, RZ, RZ, R54 ; IMAD.MOV.U32 R7, RZ, RZ, R55 ; CALL.REL.NOINC 0x135e0 ; MOV R6, R8 ; BSYNC B3 ; DADD R8, R22, R22 ; BSSY B1, 0x4fd0 ; MOV R10, 0x4fc0 ; DMUL R34, R34, R38 ; DADD R8, -R8, R20 ; DADD R42, -R52, R42 ; DFMA R34, R36, R56, R34 ; DADD R38, R8, R24 ; DFMA R42, R42, R6, R34 ; DMUL R6, R22, c[0x2][0x8] ; DADD R8, -RZ, |R38| ; DFMA R30, R24, c[0x2][0x28], -R52 ; DFMA R40, R26, c[0x2][0x28], R40 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; DFMA R6, R20, c[0x2][0x10], R6 ; DFMA R30, R26, c[0x2][0x10], R30 ; DFMA R40, R28, c[0x2][0x50], R40 ; DFMA R32, R24, c[0x2][0x18], R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R38.reuse, 2 ; BSSY B1, 0x50f0 ; DSETP.NEU.AND P0, PT, R38, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x50e0 ; DSETP.GTU.AND P0, PT, |R38|, +INF , PT ; @P0 BRA 0x50d0 ; ISETP.NE.AND P0, PT, R38, RZ, PT ; LOP3.LUT R8, R39, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x50e0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x50e0 ; DADD R6, R38, 2 ; BSYNC B1 ; DFMA R34, R22, -4, R20 ; BSSY B1, 0x51e0 ; MOV R10, 0x51d0 ; DMUL R36, R24, 3 ; DMUL R6, R6, c[0x2][0x30] ; DADD R34, R34, R36 ; DSETP.NEU.AND P0, PT, R38, 1, PT ; DADD R8, -RZ, |R34| ; FSEL R38, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R39, R7, 1.8854166269302368164, P0 ; MOV R7, 0x40000000 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R34.reuse, 2 ; BSSY B1, 0x5300 ; DSETP.NEU.AND P0, PT, R34, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x52f0 ; DSETP.GTU.AND P0, PT, |R34|, +INF , PT ; @P0 BRA 0x52e0 ; ISETP.NE.AND P0, PT, R34, RZ, PT ; LOP3.LUT R8, R35, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x52f0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x52f0 ; DADD R6, R34, 2 ; BSYNC B1 ; DADD R20, R24, R24 ; BSSY B1, 0x5400 ; MOV R10, 0x53f0 ; DMUL R6, R6, 0.25 ; DADD R20, -R20, R22 ; DSETP.NEU.AND P0, PT, R34, 1, PT ; DADD R20, R20, R26 ; FSEL R34, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R35, R7, 1.625, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R8, -RZ, |R20| ; DADD R34, R38, R34 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R20.reuse, 2 ; BSSY B1, 0x5520 ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x5510 ; DSETP.GTU.AND P0, PT, |R20|, +INF , PT ; @P0 BRA 0x5500 ; ISETP.NE.AND P0, PT, R20, RZ, PT ; LOP3.LUT R8, R21, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x5510 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x5510 ; DADD R6, R20, 2 ; BSYNC B1 ; DADD R22, R22, -R26 ; BSSY B1, 0x55f0 ; MOV R10, 0x55e0 ; DMUL R6, R6, c[0x2][0x30] ; DADD R8, -RZ, |R22| ; DSETP.NEU.AND P0, PT, R20, 1, PT ; FSEL R20, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R21, R7, 1.8854166269302368164, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; MOV R11, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R22.reuse, 2 ; BSSY B1, 0x5710 ; DSETP.NEU.AND P0, PT, R22, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x5700 ; DSETP.GTU.AND P0, PT, |R22|, +INF , PT ; @P0 BRA 0x56f0 ; ISETP.NE.AND P0, PT, R22, RZ, PT ; LOP3.LUT R8, R23, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x5700 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x5700 ; DADD R6, R22, 2 ; BSYNC B1 ; DADD R8, R26, R26 ; BSSY B1, 0x5810 ; MOV R10, 0x5800 ; DMUL R6, R6, 0.25 ; DADD R24, -R8, R24 ; DSETP.NEU.AND P0, PT, R22, 1, PT ; DADD R24, R24, R28 ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R8, -RZ, |R24| ; DADD R20, R20, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R24.reuse, 2 ; BSSY B1, 0x5930 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x5920 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x5910 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x5920 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x5920 ; DADD R6, R24, 2 ; BSYNC B1 ; DFMA R26, R26, -4, R36 ; BSSY B1, 0x5a10 ; MOV R10, 0x5a00 ; DMUL R6, R6, c[0x2][0x30] ; DADD R28, R26, R28 ; DSETP.NEU.AND P0, PT, R24, 1, PT ; DADD R8, -RZ, |R28| ; FSEL R24, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R25, R7, 1.8854166269302368164, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R28.reuse, 2 ; BSSY B1, 0x5b30 ; DSETP.NEU.AND P0, PT, R28, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x5b20 ; DSETP.GTU.AND P0, PT, |R28|, +INF , PT ; @P0 BRA 0x5b10 ; ISETP.NE.AND P0, PT, R28, RZ, PT ; LOP3.LUT R8, R29, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x5b20 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x5b20 ; DADD R6, R28, 2 ; BSYNC B1 ; DMUL R6, R6, 0.25 ; BSSY B1, 0x5c10 ; MOV R10, 0x5c00 ; DADD R22, R34, c[0x2][0x0] ; DSETP.NEU.AND P0, PT, R28, 1, PT ; DADD R8, -RZ, |R22| ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R24, R24, R6 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; MOV R6, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R22.reuse, 2 ; BSSY B1, 0x5d30 ; DSETP.NEU.AND P0, PT, R22, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x5d20 ; DSETP.GTU.AND P0, PT, |R22|, +INF , PT ; @P0 BRA 0x5d10 ; ISETP.NE.AND P0, PT, R22, RZ, PT ; LOP3.LUT R8, R23, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x5d20 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x5d20 ; DADD R6, R22, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0x5e90 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x38] ; DFMA R12, R10, -R6, c[0x2][0x38] ; DFMA R8, R8, R12, R10 ; FFMA R10, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA 0x5e80 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x5e70 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; MOV R7, 0x3fb99999 ; IMAD.MOV.U32 R10, RZ, RZ, -0x66666666 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DADD R20, R20, c[0x2][0x0] ; BSSY B1, 0x5f50 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R22, 1, PT ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R20| ; FSEL R22, R8, -1.5881868392106855534e-23, P0 ; FSEL R23, R9, 1.4499999284744262695, P0 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MOV R10, 0x5f40 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R20.reuse, 2 ; BSSY B1, 0x6070 ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x6060 ; DSETP.GTU.AND P0, PT, |R20|, +INF , PT ; @P0 BRA 0x6050 ; ISETP.NE.AND P0, PT, R20, RZ, PT ; LOP3.LUT R8, R21, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x6060 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x6060 ; DADD R6, R20, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0x61d0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x40] ; DFMA R12, R10, -R6, c[0x2][0x40] ; DFMA R8, R8, R12, R10 ; FFMA R10, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA 0x61c0 ; MOV R8, R6 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; MOV R6, 0x61b0 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fe33333 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DADD R24, R24, c[0x2][0x0] ; BSSY B1, 0x6290 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R20, 1, PT ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R24| ; FSEL R20, R8, 4.172325063223070174e-08, P0 ; FSEL R21, R9, 1.7749999761581420898, P0 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MOV R10, 0x6280 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R24.reuse, 2 ; BSSY B1, 0x63b0 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x63a0 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x6390 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x63a0 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x63a0 ; DADD R6, R24, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0x6510 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x48] ; DFMA R12, R10, -R6, c[0x2][0x48] ; DFMA R8, R8, R12, R10 ; FFMA R10, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA 0x6500 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x64f0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fd33333 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DSETP.NEU.AND P0, PT, R24, 1, PT ; MOV R6, 0x1 ; BSSY B3, 0x66e0 ; FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; DADD R24, R22, R20 ; FSEL R26, R8, 4.172325063223070174e-08, P0 ; FSEL R27, R9, 1.6499999761581420898, P0 ; DADD R24, R24, R26 ; MUFU.RCP64H R7, R25 ; DFMA R8, -R24, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R24, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R28, R6, R22 ; DFMA R8, -R24, R28, R22 ; DFMA R28, R6, R8, R28 ; FFMA R6, RZ, R25, R29 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x66d0 ; IMAD.MOV.U32 R10, RZ, RZ, R22 ; MOV R6, 0x66b0 ; IMAD.MOV.U32 R7, RZ, RZ, R23 ; IMAD.MOV.U32 R8, RZ, RZ, R24 ; IMAD.MOV.U32 R9, RZ, RZ, R25 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R28, RZ, RZ, R8 ; IMAD.MOV.U32 R29, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R25 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x6880 ; DFMA R8, -R24, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R24, R8, 1 ; DFMA R8, R8, R6, R8 ; MOV R6, R20 ; IMAD.MOV.U32 R7, RZ, RZ, R21 ; DMUL R22, R8, R6 ; DFMA R6, -R24, R22, R6 ; DFMA R22, R8, R6, R22 ; FFMA R6, RZ, R25, R23 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x6870 ; IMAD.MOV.U32 R10, RZ, RZ, R20 ; MOV R6, 0x6850 ; IMAD.MOV.U32 R7, RZ, RZ, R21 ; IMAD.MOV.U32 R8, RZ, RZ, R24 ; IMAD.MOV.U32 R9, RZ, RZ, R25 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R22, RZ, RZ, R8 ; IMAD.MOV.U32 R23, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R25 ; MOV R6, 0x1 ; BSSY B3, 0x6a10 ; FSETP.GEU.AND P1, PT, |R27|, 6.5827683646048100446e-37, PT ; DFMA R8, -R24, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R24, R8, 1 ; DFMA R10, R8, R6, R8 ; IMAD.MOV.U32 R8, RZ, RZ, R26 ; IMAD.MOV.U32 R9, RZ, RZ, R27 ; DMUL R6, R10, R8 ; DFMA R8, -R24, R6, R8 ; DFMA R6, R10, R8, R6 ; FFMA R8, RZ, R25, R7 ; FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x6a00 ; IMAD.MOV.U32 R8, RZ, RZ, R24 ; MOV R6, 0x69f0 ; IMAD.MOV.U32 R9, RZ, RZ, R25 ; IMAD.MOV.U32 R10, RZ, RZ, R26 ; IMAD.MOV.U32 R7, RZ, RZ, R27 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; BSYNC B3 ; DMUL R30, R30, R22 ; DFMA R30, R32, R28, R30 ; DFMA R40, R40, R6, R30 ; BSYNC B2 ; S2R R6, SR_TID.X ; ULDC UR4, c[0x0][0x1f0] ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; UIADD3 UR4, UR4, -0x1, URZ ; S2R R7, SR_CTAID.X ; IMAD R24, R7, c[0x0][0x0], R6 ; IADD3 R6, R24.reuse, 0x1, RZ ; IADD3 R8, R24.reuse, 0x2, RZ ; IADD3 R10, R24.reuse, 0x3, RZ ; I2F.F64 R6, R6 ; IADD3 R20, R24.reuse, -0x1, RZ ; IADD3 R22, R24.reuse, -0x2, RZ ; IADD3 R24, R24, -0x3, RZ ; I2F.F64 R8, R8 ; I2F.F64 R10, R10 ; DSETP.MAX.AND P2, P3, RZ, R6, PT ; MOV R13, R6 ; IMAD.MOV.U32 R23, RZ, RZ, R7 ; SEL R12, R12, R13, P2 ; I2F.F64 R20, R20 ; DSETP.MAX.AND P5, P6, RZ, R8, PT ; IMAD.MOV.U32 R25, RZ, RZ, R8 ; IMAD.MOV.U32 R27, RZ, RZ, R9 ; DSETP.MAX.AND P0, P1, RZ, R10, PT ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; I2F.F64 R6, UR4 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; IMAD.MOV.U32 R9, RZ, RZ, R11 ; FSEL R13, R10.reuse, R23, P2 ; DSETP.MAX.AND P2, P4, RZ, R20, PT ; @P3 LOP3.LUT R13, R23, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R28, RZ, RZ, R21 ; MOV R11, R20 ; I2F.F64 R22, R22 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; FSEL R21, R10.reuse, R27, P5 ; SEL R10, R10, R11, P2 ; DSETP.GT.AND P3, PT, R12, R6, PT ; SEL R20, R20, R25, P5 ; IMAD.MOV.U32 R11, RZ, RZ, RZ ; I2F.F64 R24, R24 ; @P6 LOP3.LUT R21, R27, 0x80000, RZ, 0xfc, !PT ; FSEL R26, R6, R12, P3 ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; FSEL R27, R7, R13, P3 ; FSEL R11, R11, R28, P2 ; DSETP.GT.AND P5, PT, R20, R6, PT ; @P4 LOP3.LUT R11, R28, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R13, RZ, RZ, R22 ; F2I.F64.TRUNC R26, R26 ; DSETP.MAX.AND P3, P2, RZ, R22, PT ; FSEL R20, R6, R20, P5 ; FSEL R21, R7, R21, P5 ; DSETP.MAX.AND P5, P4, RZ, R24, PT ; FSEL R29, R12.reuse, R23, P3 ; IMAD.MOV.U32 R31, RZ, RZ, R24 ; SEL R12, R12, R13, P3 ; IMAD.MOV.U32 R13, RZ, RZ, RZ ; F2I.F64.TRUNC R20, R20 ; IMAD.MOV.U32 R24, RZ, RZ, RZ ; @P2 LOP3.LUT R29, R23, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P2, PT, R10, R6.reuse, PT ; FSEL R27, R13, R25, P5 ; MOV R13, R29 ; @P4 LOP3.LUT R27, R25, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R21, RZ, RZ, RZ ; FSEL R22, R6, R10, P2 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; FSEL R25, R24, R9, P0 ; DSETP.GT.AND P3, PT, R12, R6.reuse, PT ; @P1 LOP3.LUT R25, R9, 0x80000, RZ, 0xfc, !PT ; IMAD R24, R3, c[0x0][0x1f0], R26 ; FSEL R23, R7, R11, P2 ; IMAD.MOV.U32 R11, RZ, RZ, R27 ; SEL R10, R10, R31, P5 ; IMAD.MOV.U32 R9, RZ, RZ, R25 ; SEL R8, R21, R8, P0 ; F2I.F64.TRUNC R22, R22 ; FSEL R12, R6, R12, P3 ; IMAD R20, R3, c[0x0][0x1f0], R20 ; DSETP.GT.AND P2, PT, R10, R6, PT ; FSEL R13, R7, R13, P3 ; DSETP.GT.AND P0, PT, R8, R6, PT ; F2I.F64.TRUNC R12, R12 ; FSEL R10, R6.reuse, R10, P2 ; IMAD.MOV.U32 R23, RZ, RZ, 0x8 ; FSEL R11, R7.reuse, R11, P2 ; FSEL R6, R6, R8, P0 ; IMAD.WIDE R24, R24, R23, c[0x0][0x170] ; FSEL R7, R7, R9, P0 ; F2I.F64.TRUNC R10, R10 ; IMAD R26, R3, c[0x0][0x1f0], R22 ; IMAD.WIDE R20, R20, R23.reuse, c[0x0][0x170] ; LDG.E.64 R24, [R24.64] ; F2I.F64.TRUNC R6, R6 ; IMAD R12, R3, c[0x0][0x1f0], R12 ; LDG.E.64 R20, [R20.64] ; IMAD.WIDE R26, R26, R23, c[0x0][0x170] ; IMAD.WIDE R28, R12, R23.reuse, c[0x0][0x170] ; LDG.E.64 R26, [R26.64] ; IMAD R38, R3, c[0x0][0x1f0], R10 ; LDG.E.64 R28, [R28.64] ; IMAD.WIDE R38, R38, R23, c[0x0][0x170] ; IMAD R22, R3, c[0x0][0x1f0], R6 ; LDG.E.64 R38, [R38.64] ; IMAD.WIDE R22, R22, R23, c[0x0][0x170] ; LDG.E.64 R22, [R22.64] ; DSETP.GEU.AND P0, PT, R14, c[0x0][0x208], PT ; DSETP.GEU.AND P1, PT, R16, c[0x0][0x208], PT ; BSSY B2, 0xcde0 ; @P0 BRA P1, 0x8cc0 ; IADD3 R34, P1, R2, c[0x0][0x1d0], RZ ; IADD3.X R35, R0, c[0x0][0x1d4], RZ, P1, !PT ; LDG.E.64 R34, [R34.64] ; IADD3 R36, P1, R2, c[0x0][0x1d8], RZ ; IADD3.X R37, R0, c[0x0][0x1dc], RZ, P1, !PT ; LDG.E.64 R36, [R36.64] ; DSETP.GEU.AND P1, PT, R16, c[0x0][0x208], PT ; IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x208] ; MOV R13, c[0x0][0x20c] ; IMAD.MOV.U32 R30, RZ, RZ, c[0x0][0x208] ; BSSY B3, 0x7520 ; IMAD.MOV.U32 R31, RZ, RZ, c[0x0][0x20c] ; @!P0 IMAD.MOV.U32 R18, RZ, RZ, R14 ; DADD R32, R12, c[0x0][0x208] ; @!P0 IMAD.MOV.U32 R19, RZ, RZ, R15 ; @!P0 IMAD.MOV.U32 R38, RZ, RZ, R28 ; DMUL R52, R12.reuse, -2 ; @!P0 IMAD.MOV.U32 R39, RZ, RZ, R29 ; @P1 MOV R16, c[0x0][0x208] ; @P1 IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x20c] ; @P1 DMUL R6, R12, 3 ; @P1 IMAD.MOV.U32 R30, RZ, RZ, R32 ; @P1 IMAD.MOV.U32 R31, RZ, RZ, R33 ; @P1 IMAD.MOV.U32 R32, RZ, RZ, R6 ; @P1 IMAD.MOV.U32 R33, RZ, RZ, R7 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R8, -R30, R32 ; MUFU.RCP64H R7, R9 ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; @P1 MOV R34, R24 ; @P1 IMAD.MOV.U32 R35, RZ, RZ, R25 ; @P1 IMAD.MOV.U32 R24, RZ, RZ, R20 ; @P1 IMAD.MOV.U32 R25, RZ, RZ, R21 ; @P1 IMAD.MOV.U32 R20, RZ, RZ, R22 ; @P1 IMAD.MOV.U32 R21, RZ, RZ, R23 ; @P0 DMUL R22, R12, -3 ; @P0 IMAD.MOV.U32 R36, RZ, RZ, R26 ; @P0 IMAD.MOV.U32 R37, RZ, RZ, R27 ; DADD R54, R20, -R24 ; @!P0 MOV R22, R52 ; @!P0 IMAD.MOV.U32 R23, RZ, RZ, R53 ; @!P0 DADD R52, -RZ, -c[0x0][0x208] ; @P0 IMAD.MOV.U32 R26, RZ, RZ, R28 ; @P0 IMAD.MOV.U32 R27, RZ, RZ, R29 ; DMUL R20, R54, R6 ; FSETP.GEU.AND P3, PT, |R55|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R20, R54 ; DFMA R20, R6, R10, R20 ; FFMA R6, RZ, R9, R21 ; FSETP.GT.AND P2, PT, |R6|, 1.469367938527859385e-39, PT ; @P2 BRA P3, 0x7510 ; IMAD.MOV.U32 R10, RZ, RZ, R54 ; MOV R6, 0x74f0 ; IMAD.MOV.U32 R7, RZ, RZ, R55 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R20, RZ, RZ, R8 ; IMAD.MOV.U32 R21, RZ, RZ, R7 ; BSYNC B3 ; DADD R12, R30, -R16 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x76b0 ; DADD R10, -R34, R24 ; MUFU.RCP64H R7, R13 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R12, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R12, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R14, R10, R6 ; DFMA R8, -R12, R14, R10 ; DFMA R14, R6, R8, R14 ; FFMA R6, RZ, R13, R15 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x76a0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R8, R12 ; IMAD.MOV.U32 R9, RZ, RZ, R13 ; MOV R6, 0x7680 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R14, RZ, RZ, R8 ; IMAD.MOV.U32 R15, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R17 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R48, R34 ; BSSY B3, 0x7830 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R16, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R16, 1 ; DFMA R6, R8, R6, R8 ; DMUL R34, R10, R6 ; DFMA R8, R34, -R16, R10 ; DFMA R34, R6, R8, R34 ; FFMA R6, RZ, R17, R35 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7820 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x7800 ; IMAD.MOV.U32 R8, RZ, RZ, R16 ; IMAD.MOV.U32 R9, RZ, RZ, R17 ; CALL.REL.NOINC 0x135e0 ; MOV R34, R8 ; IMAD.MOV.U32 R35, RZ, RZ, R7 ; BSYNC B3 ; DADD R24, RZ, R18 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x79c0 ; DADD R10, R48, -R36 ; MUFU.RCP64H R7, R25 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R24, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R24, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R28, R10, R6 ; DFMA R8, -R24, R28, R10 ; DFMA R28, R6, R8, R28 ; FFMA R6, RZ, R25, R29 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x79b0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x7990 ; IMAD.MOV.U32 R8, RZ, RZ, R24 ; IMAD.MOV.U32 R9, RZ, RZ, R25 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R28, RZ, RZ, R8 ; IMAD.MOV.U32 R29, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, -R52, -R18 ; MOV R6, 0x1 ; BSSY B3, 0x7b40 ; DADD R12, R36, -R26 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R36, R12, R6 ; DFMA R10, -R8, R36, R12 ; DFMA R36, R6, R10, R36 ; FFMA R6, RZ, R9, R37 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7b30 ; IMAD.MOV.U32 R10, RZ, RZ, R12 ; MOV R6, 0x7b10 ; IMAD.MOV.U32 R7, RZ, RZ, R13 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R36, RZ, RZ, R8 ; IMAD.MOV.U32 R37, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, -R22, R52 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x7cc0 ; DADD R38, R26, -R38 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R39|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R26, R38, R6 ; DFMA R10, -R8, R26, R38 ; DFMA R26, R6, R10, R26 ; FFMA R6, RZ, R9, R27 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7cb0 ; IMAD.MOV.U32 R10, RZ, RZ, R38 ; MOV R6, 0x7c90 ; IMAD.MOV.U32 R7, RZ, RZ, R39 ; CALL.REL.NOINC 0x135e0 ; MOV R26, R8 ; IMAD.MOV.U32 R27, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, R32, -R16 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x7e40 ; DADD R12, -R14, R20 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R20, R12, R6 ; DFMA R10, -R8, R20, R12 ; DFMA R20, R6, R10, R20 ; FFMA R6, RZ, R9, R21 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7e30 ; IMAD.MOV.U32 R10, RZ, RZ, R12 ; MOV R6, 0x7e10 ; IMAD.MOV.U32 R7, RZ, RZ, R13 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R20, RZ, RZ, R8 ; IMAD.MOV.U32 R21, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R31 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R34, R14 ; BSSY B3, 0x7fc0 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R30, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R30, 1 ; DFMA R6, R8, R6, R8 ; DMUL R56, R10, R6 ; DFMA R8, R56, -R30, R10 ; DFMA R56, R6, R8, R56 ; FFMA R6, RZ, R31, R57 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7fb0 ; MOV R7, R11 ; IMAD.MOV.U32 R8, RZ, RZ, R30 ; MOV R6, 0x7f90 ; IMAD.MOV.U32 R9, RZ, RZ, R31 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R56, RZ, RZ, R8 ; IMAD.MOV.U32 R57, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, R16, R18 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x8140 ; DADD R12, -R28, R34 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R54, R12, R6 ; DFMA R10, -R8, R54, R12 ; DFMA R54, R6, R10, R54 ; FFMA R6, RZ, R9, R55 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x8130 ; IMAD.MOV.U32 R10, RZ, RZ, R12 ; MOV R6, 0x8110 ; IMAD.MOV.U32 R7, RZ, RZ, R13 ; CALL.REL.NOINC 0x135e0 ; MOV R54, R8 ; IMAD.MOV.U32 R55, RZ, RZ, R7 ; BSYNC B3 ; DADD R14, RZ, -R52 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x82d0 ; DADD R10, -R36, R28 ; MUFU.RCP64H R7, R15 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R14, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R14, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R38, R10, R6 ; DFMA R8, -R14, R38, R10 ; DFMA R38, R6, R8, R38 ; FFMA R6, RZ, R15, R39 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x82c0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x82a0 ; IMAD.MOV.U32 R8, RZ, RZ, R14 ; IMAD.MOV.U32 R9, RZ, RZ, R15 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R38, RZ, RZ, R8 ; IMAD.MOV.U32 R39, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, -R22, -R18 ; MOV R6, 0x1 ; BSSY B3, 0x8450 ; DADD R36, -R26, R36 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R37|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R26, R36, R6 ; DFMA R10, -R8, R26, R36 ; DFMA R26, R6, R10, R26 ; FFMA R6, RZ, R9, R27 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x8440 ; IMAD.MOV.U32 R10, RZ, RZ, R36 ; MOV R6, 0x8420 ; IMAD.MOV.U32 R7, RZ, RZ, R37 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R26, RZ, RZ, R8 ; IMAD.MOV.U32 R27, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R33 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R56, R20 ; BSSY B3, 0x85d0 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R32, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R32, 1 ; DFMA R6, R8, R6, R8 ; DMUL R20, R10, R6 ; DFMA R8, R20, -R32, R10 ; DFMA R20, R6, R8, R20 ; FFMA R6, RZ, R33, R21 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x85c0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R9, R33 ; IMAD.MOV.U32 R8, RZ, RZ, R32 ; MOV R6, 0x85a0 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R20, RZ, RZ, R8 ; IMAD.MOV.U32 R21, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, R30, R18 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x8750 ; DADD R12, -R54, R56 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R18, R12, R6 ; DFMA R10, -R8, R18, R12 ; DFMA R18, R6, R10, R18 ; FFMA R6, RZ, R9, R19 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x8740 ; IMAD.MOV.U32 R10, RZ, RZ, R12 ; MOV R6, 0x8720 ; IMAD.MOV.U32 R7, RZ, RZ, R13 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R18, RZ, RZ, R8 ; IMAD.MOV.U32 R19, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, -R52, R16 ; MOV R6, 0x1 ; BSSY B3, 0x88d0 ; DADD R12, -R38, R54 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R32, R12, R6 ; DFMA R10, -R8, R32, R12 ; DFMA R32, R6, R10, R32 ; FFMA R6, RZ, R9, R33 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x88c0 ; IMAD.MOV.U32 R10, RZ, RZ, R12 ; MOV R6, 0x88a0 ; IMAD.MOV.U32 R7, RZ, RZ, R13 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R32, RZ, RZ, R8 ; IMAD.MOV.U32 R33, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, RZ, -R22 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0x8a40 ; DADD R26, -R26, R38 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R27|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R10, R26, R6 ; DFMA R12, -R8, R10, R26 ; DFMA R6, R6, R12, R10 ; FFMA R10, RZ, R9, R7 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x8a30 ; IMAD.MOV.U32 R10, RZ, RZ, R26 ; MOV R6, 0x8a20 ; IMAD.MOV.U32 R7, RZ, RZ, R27 ; CALL.REL.NOINC 0x135e0 ; MOV R6, R8 ; BSYNC B3 ; DMUL R8, R38, R54 ; DSETP.GEU.AND P0, PT, |R32|, |R6|, PT ; DSETP.GEU.AND P4, PT, R8, RZ, PT ; FSEL R8, R32, R6, !P0 ; FSEL R9, R33, R7, !P0 ; DMUL R10, R54, R56 ; DMUL R6, R24, R14 ; DADD R16, RZ, -R16 ; DSETP.GEU.AND P0, PT, |R32|, |R18|, PT ; DADD R30, RZ, -R30 ; DSETP.GEU.AND P2, PT, |R18|, |R20|, PT ; DSETP.GEU.AND P5, PT, R10, RZ, PT ; FSEL R10, R32, R18, !P0 ; DMUL R6, R6, R8 ; FSEL R11, R33, R19, !P0 ; FSEL R12, R18, R20, !P2 ; DSETP.GEU.AND P1, PT, |R38|, |R54|, PT ; FSEL R13, R19, R21, !P2 ; DSETP.GEU.AND P3, PT, |R54|, |R56|, PT ; FSEL R18, R38, R54, !P1 ; DMUL R8, R24, R16 ; FSEL R38, R39, R55, !P1 ; FSEL R14, R54, R56, !P3 ; DMUL R30, R16, R30 ; FSEL R54, R55, R57, !P3 ; FSEL R18, R18, RZ, P4 ; DMUL R8, R8, R10 ; FSEL R19, R38, RZ, P4 ; FSEL R14, R14, RZ, P5 ; DMUL R30, R30, R12 ; FSEL R15, R54, RZ, P5 ; DFMA R18, R24, R18, R28 ; FSEL R6, R6, R8, !P1 ; FSEL R7, R7, R9, !P1 ; DFMA R14, R16, R14, R34 ; FSEL R8, R8, R30, !P3 ; FSEL R9, R9, R31, !P3 ; DADD R18, R18, R6 ; DADD R14, R14, R8 ; BRA 0xcdd0 ; MUFU.RCP64H R7, c[0x0][0x20c] ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x208] ; BSSY B3, 0x8e60 ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x20c] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R8, R6, -R10, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R10, 1 ; DADD R10, R28, -R38 ; DFMA R6, R8, R6, R8 ; DMUL R14, R10, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R14, -c[0x0][0x208], R10 ; DFMA R14, R6, R8, R14 ; FFMA R6, RZ, c[0x0][0x20c], R15 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x8e50 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x8e30 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x208] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x20c] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R14, RZ, RZ, R8 ; MOV R15, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x20c] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x208] ; BSSY B3, 0x9000 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x20c] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, -R28, R26 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R38, R8, R10 ; DFMA R6, R38, -c[0x0][0x208], R10 ; DFMA R38, R8, R6, R38 ; FFMA R6, RZ, c[0x0][0x20c], R39 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x8ff0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x8fd0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x208] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x20c] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R38, RZ, RZ, R8 ; MOV R39, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x20c] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x208] ; BSSY B3, 0x91a0 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x20c] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, R48, -R26 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R36, R8, R10 ; DFMA R6, R36, -c[0x0][0x208], R10 ; DFMA R36, R8, R6, R36 ; FFMA R6, RZ, c[0x0][0x20c], R37 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x9190 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x9170 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x208] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x20c] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R36, RZ, RZ, R8 ; MOV R37, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x20c] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x208] ; BSSY B3, 0x9340 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x20c] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, -R48, R24 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R34, R8, R10 ; DFMA R6, R34, -c[0x0][0x208], R10 ; DFMA R34, R8, R6, R34 ; FFMA R6, RZ, c[0x0][0x20c], R35 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x9330 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x9310 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x208] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x20c] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R34, RZ, RZ, R8 ; MOV R35, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x20c] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x208] ; BSSY B3, 0x94e0 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x20c] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, -R24, R20 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R32, R8, R10 ; DFMA R6, R32, -c[0x0][0x208], R10 ; DFMA R32, R8, R6, R32 ; FFMA R6, RZ, c[0x0][0x20c], R33 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x94d0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x94b0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x208] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x20c] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R32, RZ, RZ, R8 ; MOV R33, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x20c] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x208] ; BSSY B3, 0x9680 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x20c] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, R22, -R20 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R30, R8, R10 ; DFMA R6, R30, -c[0x0][0x208], R10 ; DFMA R30, R8, R6, R30 ; FFMA R6, RZ, c[0x0][0x20c], R31 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x9670 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x9650 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x208] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x20c] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; MOV R31, R7 ; BSYNC B3 ; DADD R8, R38.reuse, R38 ; BSSY B1, 0x97c0 ; MOV R10, 0x97b0 ; DMUL R28, R38, c[0x2][0x20] ; DADD R8, -R8, R14 ; DMUL R6, R38, c[0x2][0x8] ; DADD R16, R8, R36 ; DMUL R24, R34, c[0x2][0x28] ; DADD R8, -RZ, |R16| ; DFMA R18, R36, c[0x2][0x28], -R28 ; DFMA R6, R14, c[0x2][0x10], R6 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; DMUL R26, R34, c[0x2][0x10] ; DFMA R22, R36, c[0x2][0x10], R24 ; DFMA R18, R34, c[0x2][0x10], R18 ; DFMA R20, R36, c[0x2][0x18], R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R16.reuse, 2 ; BSSY B1, 0x9900 ; IMAD.MOV.U32 R56, RZ, RZ, R6 ; DSETP.NEU.AND P0, PT, R16, RZ, PT ; IMAD.MOV.U32 R57, RZ, RZ, R7 ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R56, SRZ ; @P1 BRA 0x98f0 ; DSETP.GTU.AND P0, PT, |R16|, +INF , PT ; @P0 BRA 0x98e0 ; ISETP.NE.AND P0, PT, R16, RZ, PT ; LOP3.LUT R6, R17, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R6, 0x7ff00000, P0 ; @P0 BRA 0x98f0 ; IMAD.MOV.U32 R56, RZ, RZ, 0x0 ; IMAD.MOV.U32 R57, RZ, RZ, 0x7ff00000 ; BRA 0x98f0 ; DADD R56, R16, 2 ; BSYNC B1 ; DFMA R54, R38, -4, R14 ; BSSY B1, 0x99b0 ; MOV R6, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DMUL R52, R36, 3 ; MOV R10, 0x99a0 ; DADD R54, R54, R52 ; DADD R8, -RZ, |R54| ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R54.reuse, 2 ; BSSY B1, 0x9b10 ; DSETP.NEU.AND P1, PT, R54, RZ, PT ; DMUL R10, R56, c[0x2][0x30] ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; DSETP.NEU.AND P0, PT, R16, 1, PT ; ISETP.NE.AND P2, PT, R8, 0x7ff00000, PT ; FSEL R56, R10, 1.46601546874880000000e+13, P0 ; @!P1 CS2R R6, SRZ ; FSEL R57, R11, 1.8854166269302368164, P0 ; @P2 BRA 0x9b00 ; DSETP.GTU.AND P0, PT, |R54|, +INF , PT ; @P0 BRA 0x9af0 ; ISETP.NE.AND P0, PT, R54, RZ, PT ; LOP3.LUT R8, R55, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x9b00 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x9b00 ; DADD R6, R54, 2 ; BSYNC B1 ; DADD R16, R36, R36 ; BSSY B1, 0x9c10 ; MOV R10, 0x9c00 ; DMUL R6, R6, 0.25 ; DADD R14, -R16, R38 ; DSETP.NEU.AND P0, PT, R54, 1, PT ; DADD R14, R14, R34 ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R8, -RZ, |R14| ; DADD R56, R56, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R14.reuse, 2 ; BSSY B1, 0x9d30 ; DSETP.NEU.AND P0, PT, R14, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x9d20 ; DSETP.GTU.AND P0, PT, |R14|, +INF , PT ; @P0 BRA 0x9d10 ; ISETP.NE.AND P0, PT, R14, RZ, PT ; LOP3.LUT R8, R15, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x9d20 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x9d20 ; DADD R6, R14, 2 ; BSYNC B1 ; DADD R54, -R34, R38 ; BSSY B1, 0x9e00 ; MOV R10, 0x9df0 ; DMUL R6, R6, c[0x2][0x30] ; DADD R8, -RZ, |R54| ; DSETP.NEU.AND P0, PT, R14, 1, PT ; FSEL R76, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; FSEL R77, R7, 1.8854166269302368164, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R54.reuse, 2 ; BSSY B1, 0x9f20 ; DSETP.NEU.AND P0, PT, R54, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x9f10 ; DSETP.GTU.AND P0, PT, |R54|, +INF , PT ; @P0 BRA 0x9f00 ; ISETP.NE.AND P0, PT, R54, RZ, PT ; LOP3.LUT R8, R55, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x9f10 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x9f10 ; DADD R6, R54, 2 ; BSYNC B1 ; DADD R14, R34, R34 ; BSSY B1, 0xa020 ; MOV R10, 0xa010 ; DMUL R6, R6, 0.25 ; DADD R74, -R14, R36 ; DSETP.NEU.AND P0, PT, R54, 1, PT ; DADD R74, R74, R32 ; FSEL R54, R6, RZ, P0 ; FSEL R55, R7, 1.625, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R8, -RZ, |R74| ; MOV R6, RZ ; DADD R54, R76, R54 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R74.reuse, 2 ; BSSY B1, 0xa140 ; DSETP.NEU.AND P0, PT, R74, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xa130 ; DSETP.GTU.AND P0, PT, |R74|, +INF , PT ; @P0 BRA 0xa120 ; ISETP.NE.AND P0, PT, R74, RZ, PT ; LOP3.LUT R8, R75, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xa130 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xa130 ; DADD R6, R74, 2 ; BSYNC B1 ; DFMA R52, R34, -4, R52 ; BSSY B1, 0xa220 ; MOV R10, 0xa210 ; DMUL R6, R6, c[0x2][0x30] ; DADD R52, R52, R32 ; DSETP.NEU.AND P0, PT, R74, 1, PT ; DADD R8, -RZ, |R52| ; FSEL R74, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R75, R7, 1.8854166269302368164, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R52.reuse, 2 ; BSSY B1, 0xa340 ; DSETP.NEU.AND P0, PT, R52, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xa330 ; DSETP.GTU.AND P0, PT, |R52|, +INF , PT ; @P0 BRA 0xa320 ; ISETP.NE.AND P0, PT, R52, RZ, PT ; LOP3.LUT R8, R53, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xa330 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; MOV R7, 0x7ff00000 ; BRA 0xa330 ; DADD R6, R52, 2 ; BSYNC B1 ; DMUL R6, R6, 0.25 ; BSSY B1, 0xa420 ; MOV R10, 0xa410 ; DADD R56, R56, c[0x2][0x0] ; DSETP.NEU.AND P0, PT, R52, 1, PT ; DADD R8, -RZ, |R56| ; FSEL R52, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R53, R7, 1.625, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R52, R74, R52 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R56.reuse, 2 ; BSSY B1, 0xa540 ; DSETP.NEU.AND P0, PT, R56, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xa530 ; DSETP.GTU.AND P0, PT, |R56|, +INF , PT ; @P0 BRA 0xa520 ; ISETP.NE.AND P0, PT, R56, RZ, PT ; LOP3.LUT R8, R57, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xa530 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xa530 ; DADD R6, R56, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0xa6a0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x38] ; DFMA R12, R10, -R6, c[0x2][0x38] ; DFMA R8, R8, R12, R10 ; FFMA R10, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA 0xa690 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R9, R7 ; IMAD.MOV.U32 R10, RZ, RZ, -0x66666666 ; MOV R6, 0xa680 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fb99999 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DADD R54, R54, c[0x2][0x0] ; BSSY B1, 0xa760 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R56, 1, PT ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R54| ; FSEL R56, R8, -1.5881868392106855534e-23, P0 ; FSEL R57, R9, 1.4499999284744262695, P0 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MOV R10, 0xa750 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R54.reuse, 2 ; BSSY B1, 0xa880 ; DSETP.NEU.AND P0, PT, R54, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xa870 ; DSETP.GTU.AND P0, PT, |R54|, +INF , PT ; @P0 BRA 0xa860 ; ISETP.NE.AND P0, PT, R54, RZ, PT ; LOP3.LUT R8, R55, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xa870 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; MOV R7, 0x7ff00000 ; BRA 0xa870 ; DADD R6, R54, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0xa9e0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x40] ; DFMA R12, R10, -R6, c[0x2][0x40] ; DFMA R8, R8, R12, R10 ; FFMA R10, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA 0xa9d0 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0xa9c0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fe33333 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DADD R52, R52, c[0x2][0x0] ; BSSY B1, 0xaaa0 ; MOV R6, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DSETP.NEU.AND P0, PT, R54, 1, PT ; DADD R10, -RZ, |R52| ; FSEL R54, R8, 4.172325063223070174e-08, P0 ; FSEL R55, R9, 1.7749999761581420898, P0 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MOV R10, 0xaa90 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R52.reuse, 2 ; BSSY B1, 0xabc0 ; DSETP.NEU.AND P0, PT, R52, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xabb0 ; DSETP.GTU.AND P0, PT, |R52|, +INF , PT ; @P0 BRA 0xaba0 ; ISETP.NE.AND P0, PT, R52, RZ, PT ; LOP3.LUT R8, R53, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xabb0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xabb0 ; DADD R6, R52, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0xad20 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x48] ; DFMA R12, R10, -R6, c[0x2][0x48] ; DFMA R8, R8, R12, R10 ; FFMA R10, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA 0xad10 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0xad00 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; MOV R7, 0x3fd33333 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DSETP.NEU.AND P0, PT, R52, 1, PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R57|, 6.5827683646048100446e-37, PT ; BSSY B3, 0xaef0 ; DADD R52, R56, R54 ; FSEL R72, R8, 4.172325063223070174e-08, P0 ; FSEL R73, R9, 1.6499999761581420898, P0 ; DADD R52, R52, R72 ; MUFU.RCP64H R7, R53 ; DFMA R8, -R52, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R52, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R74, R6, R56 ; DFMA R8, -R52, R74, R56 ; DFMA R74, R6, R8, R74 ; FFMA R6, RZ, R53, R75 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xaee0 ; IMAD.MOV.U32 R10, RZ, RZ, R56 ; MOV R6, 0xaec0 ; IMAD.MOV.U32 R7, RZ, RZ, R57 ; IMAD.MOV.U32 R8, RZ, RZ, R52 ; IMAD.MOV.U32 R9, RZ, RZ, R53 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R74, RZ, RZ, R8 ; MOV R75, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R53 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R55|, 6.5827683646048100446e-37, PT ; BSSY B3, 0xb090 ; DFMA R8, -R52, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R52, R8, 1 ; DFMA R8, R8, R6, R8 ; IMAD.MOV.U32 R6, RZ, RZ, R54 ; IMAD.MOV.U32 R7, RZ, RZ, R55 ; DMUL R56, R8, R6 ; DFMA R6, -R52, R56, R6 ; DFMA R56, R8, R6, R56 ; FFMA R6, RZ, R53, R57 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xb080 ; IMAD.MOV.U32 R10, RZ, RZ, R54 ; MOV R6, 0xb060 ; IMAD.MOV.U32 R7, RZ, RZ, R55 ; IMAD.MOV.U32 R8, RZ, RZ, R52 ; IMAD.MOV.U32 R9, RZ, RZ, R53 ; CALL.REL.NOINC 0x135e0 ; MOV R56, R8 ; IMAD.MOV.U32 R57, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R53 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R73|, 6.5827683646048100446e-37, PT ; BSSY B3, 0xb220 ; DFMA R8, -R52, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R52, R8, 1 ; DFMA R10, R8, R6, R8 ; IMAD.MOV.U32 R8, RZ, RZ, R72 ; IMAD.MOV.U32 R9, RZ, RZ, R73 ; DMUL R6, R10, R8 ; DFMA R8, -R52, R6, R8 ; DFMA R6, R10, R8, R6 ; FFMA R8, RZ, R53, R7 ; FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xb210 ; IMAD.MOV.U32 R8, RZ, RZ, R52 ; MOV R7, R73 ; IMAD.MOV.U32 R9, RZ, RZ, R53 ; MOV R6, 0xb200 ; IMAD.MOV.U32 R10, RZ, RZ, R72 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; BSYNC B3 ; DADD R8, R32, R32 ; BSSY B1, 0xb380 ; DFMA R26, R36, c[0x2][0x28], R26 ; DADD R8, -R8, R30 ; DADD R28, -R28, R26 ; DADD R26, R8, R34 ; DMUL R18, R18, R56 ; DMUL R8, R32, c[0x2][0x8] ; DADD R10, -RZ, |R26| ; DFMA R18, R20, R74, R18 ; DFMA R22, R32, c[0x2][0x50], R22 ; DFMA R20, R32, c[0x2][0x50], R24 ; DFMA R8, R30, c[0x2][0x10], R8 ; DFMA R18, R22, R6, R18 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DFMA R20, R36, c[0x2][0x10], R20 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DFMA R22, R34, c[0x2][0x18], R8 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MOV R10, 0xb370 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R26.reuse, 2 ; BSSY B1, 0xb4a0 ; DSETP.NEU.AND P0, PT, R26, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xb490 ; DSETP.GTU.AND P0, PT, |R26|, +INF , PT ; @P0 BRA 0xb480 ; ISETP.NE.AND P0, PT, R26, RZ, PT ; LOP3.LUT R8, R27, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xb490 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xb490 ; DADD R6, R26, 2 ; BSYNC B1 ; DFMA R30, R32, -4, R30 ; BSSY B1, 0xb590 ; MOV R10, 0xb580 ; DMUL R24, R34, 3 ; DMUL R6, R6, c[0x2][0x30] ; DADD R30, R30, R24 ; DSETP.NEU.AND P0, PT, R26, 1, PT ; DADD R8, -RZ, |R30| ; FSEL R26, R6, 1.46601546874880000000e+13, P0 ; FSEL R27, R7, 1.8854166269302368164, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; MOV R6, RZ ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R30.reuse, 2 ; BSSY B1, 0xb6b0 ; DSETP.NEU.AND P0, PT, R30, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xb6a0 ; DSETP.GTU.AND P0, PT, |R30|, +INF , PT ; @P0 BRA 0xb690 ; ISETP.NE.AND P0, PT, R30, RZ, PT ; LOP3.LUT R8, R31, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xb6a0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xb6a0 ; DADD R6, R30, 2 ; BSYNC B1 ; DADD R14, -R14, R32 ; BSSY B1, 0xb7a0 ; MOV R10, 0xb790 ; DMUL R6, R6, 0.25 ; DADD R14, R14, R36 ; DSETP.NEU.AND P0, PT, R30, 1, PT ; DADD R8, -RZ, |R14| ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R26, R26, R6 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R14.reuse, 2 ; BSSY B1, 0xb8c0 ; DSETP.NEU.AND P0, PT, R14, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xb8b0 ; DSETP.GTU.AND P0, PT, |R14|, +INF , PT ; @P0 BRA 0xb8a0 ; ISETP.NE.AND P0, PT, R14, RZ, PT ; LOP3.LUT R8, R15, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xb8b0 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xb8b0 ; DADD R6, R14, 2 ; BSYNC B1 ; DADD R32, R32, -R36 ; BSSY B1, 0xb990 ; MOV R10, 0xb980 ; DMUL R6, R6, c[0x2][0x30] ; DADD R8, -RZ, |R32| ; DSETP.NEU.AND P0, PT, R14, 1, PT ; FSEL R14, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; FSEL R15, R7, 1.8854166269302368164, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R32.reuse, 2 ; BSSY B1, 0xbab0 ; DSETP.NEU.AND P0, PT, R32, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xbaa0 ; DSETP.GTU.AND P0, PT, |R32|, +INF , PT ; @P0 BRA 0xba90 ; ISETP.NE.AND P0, PT, R32, RZ, PT ; LOP3.LUT R8, R33, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xbaa0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xbaa0 ; DADD R6, R32, 2 ; BSYNC B1 ; DADD R16, -R16, R34 ; BSSY B1, 0xbba0 ; MOV R10, 0xbb90 ; DMUL R6, R6, 0.25 ; DADD R16, R16, R38 ; DSETP.NEU.AND P0, PT, R32, 1, PT ; DADD R8, -RZ, |R16| ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R14, R14, R6 ; MOV R11, R9 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R16.reuse, 2 ; BSSY B1, 0xbcc0 ; DSETP.NEU.AND P0, PT, R16, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xbcb0 ; DSETP.GTU.AND P0, PT, |R16|, +INF , PT ; @P0 BRA 0xbca0 ; ISETP.NE.AND P0, PT, R16, RZ, PT ; LOP3.LUT R8, R17, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xbcb0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xbcb0 ; DADD R6, R16, 2 ; BSYNC B1 ; DFMA R24, R36, -4, R24 ; BSSY B1, 0xbda0 ; MOV R10, 0xbd90 ; DMUL R6, R6, c[0x2][0x30] ; DADD R38, R24, R38 ; DSETP.NEU.AND P0, PT, R16, 1, PT ; DADD R8, -RZ, |R38| ; FSEL R24, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R25, R7, 1.8854166269302368164, P0 ; MOV R7, 0x40000000 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R38.reuse, 2 ; BSSY B1, 0xbec0 ; DSETP.NEU.AND P0, PT, R38, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xbeb0 ; DSETP.GTU.AND P0, PT, |R38|, +INF , PT ; @P0 BRA 0xbea0 ; ISETP.NE.AND P0, PT, R38, RZ, PT ; LOP3.LUT R8, R39, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xbeb0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xbeb0 ; DADD R6, R38, 2 ; BSYNC B1 ; DMUL R6, R6, 0.25 ; BSSY B1, 0xbfa0 ; MOV R10, 0xbf90 ; DADD R16, R26, c[0x2][0x0] ; DSETP.NEU.AND P0, PT, R38, 1, PT ; DADD R8, -RZ, |R16| ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R24, R24, R6 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R16.reuse, 2 ; BSSY B1, 0xc0c0 ; DSETP.NEU.AND P0, PT, R16, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xc0b0 ; DSETP.GTU.AND P0, PT, |R16|, +INF , PT ; @P0 BRA 0xc0a0 ; ISETP.NE.AND P0, PT, R16, RZ, PT ; LOP3.LUT R8, R17, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xc0b0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; MOV R7, 0x7ff00000 ; BRA 0xc0b0 ; DADD R6, R16, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0xc220 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x38] ; DFMA R12, R10, -R6, c[0x2][0x38] ; DFMA R8, R8, R12, R10 ; FFMA R10, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA 0xc210 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0xc200 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, -0x66666666 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fb99999 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DADD R14, R14, c[0x2][0x0] ; BSSY B1, 0xc2e0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R16, 1, PT ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R14| ; FSEL R16, R8, -1.5881868392106855534e-23, P0 ; FSEL R17, R9, 1.4499999284744262695, P0 ; MOV R8, R10 ; MOV R10, 0xc2d0 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R14.reuse, 2 ; BSSY B1, 0xc400 ; DSETP.NEU.AND P0, PT, R14, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xc3f0 ; DSETP.GTU.AND P0, PT, |R14|, +INF , PT ; @P0 BRA 0xc3e0 ; ISETP.NE.AND P0, PT, R14, RZ, PT ; LOP3.LUT R8, R15, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xc3f0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xc3f0 ; DADD R6, R14, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0xc560 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x40] ; DFMA R12, R10, -R6, c[0x2][0x40] ; DFMA R8, R8, R12, R10 ; FFMA R10, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA 0xc550 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R9, R7 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; MOV R6, 0xc540 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fe33333 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DADD R24, R24, c[0x2][0x0] ; BSSY B1, 0xc620 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R14, 1, PT ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R24| ; FSEL R14, R8, 4.172325063223070174e-08, P0 ; FSEL R15, R9, 1.7749999761581420898, P0 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MOV R10, 0xc610 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R24.reuse, 2 ; BSSY B1, 0xc740 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xc730 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0xc720 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0xc730 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xc730 ; DADD R6, R24, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0xc8a0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x48] ; DFMA R12, R10, -R6, c[0x2][0x48] ; DFMA R8, R8, R12, R10 ; FFMA R10, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; @P0 BRA 0xc890 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0xc880 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fd33333 ; CALL.REL.NOINC 0x135e0 ; MOV R9, R7 ; BSYNC B3 ; DSETP.NEU.AND P0, PT, R24, 1, PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R17|, 6.5827683646048100446e-37, PT ; BSSY B3, 0xca70 ; DADD R24, R16, R14 ; FSEL R26, R8, 4.172325063223070174e-08, P0 ; FSEL R27, R9, 1.6499999761581420898, P0 ; DADD R24, R24, R26 ; MUFU.RCP64H R7, R25 ; DFMA R8, -R24, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R24, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R30, R6, R16 ; DFMA R8, -R24, R30, R16 ; DFMA R30, R6, R8, R30 ; FFMA R6, RZ, R25, R31 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xca60 ; IMAD.MOV.U32 R10, RZ, RZ, R16 ; MOV R6, 0xca40 ; IMAD.MOV.U32 R7, RZ, RZ, R17 ; IMAD.MOV.U32 R8, RZ, RZ, R24 ; IMAD.MOV.U32 R9, RZ, RZ, R25 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; MOV R31, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R25 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; BSSY B3, 0xcc10 ; DFMA R8, -R24, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R24, R8, 1 ; DFMA R8, R8, R6, R8 ; IMAD.MOV.U32 R6, RZ, RZ, R14 ; IMAD.MOV.U32 R7, RZ, RZ, R15 ; DMUL R16, R8, R6 ; DFMA R6, -R24, R16, R6 ; DFMA R16, R8, R6, R16 ; FFMA R6, RZ, R25, R17 ; FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xcc00 ; IMAD.MOV.U32 R10, RZ, RZ, R14 ; MOV R9, R25 ; IMAD.MOV.U32 R7, RZ, RZ, R15 ; MOV R6, 0xcbe0 ; IMAD.MOV.U32 R8, RZ, RZ, R24 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R16, RZ, RZ, R8 ; IMAD.MOV.U32 R17, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R25 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R27|, 6.5827683646048100446e-37, PT ; BSSY B3, 0xcda0 ; DFMA R8, -R24, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R24, R8, 1 ; DFMA R10, R8, R6, R8 ; IMAD.MOV.U32 R8, RZ, RZ, R26 ; IMAD.MOV.U32 R9, RZ, RZ, R27 ; DMUL R6, R10, R8 ; DFMA R8, -R24, R6, R8 ; DFMA R6, R10, R8, R6 ; FFMA R8, RZ, R25, R7 ; FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xcd90 ; IMAD.MOV.U32 R8, RZ, RZ, R24 ; MOV R9, R25 ; IMAD.MOV.U32 R10, RZ, RZ, R26 ; MOV R6, 0xcd80 ; IMAD.MOV.U32 R7, RZ, RZ, R27 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; BSYNC B3 ; DMUL R20, R20, R16 ; DFMA R20, R22, R30, R20 ; DFMA R14, R28, R6, R20 ; BSYNC B2 ; S2R R6, SR_TID.Z ; ULDC UR4, c[0x0][0x1f8] ; UIADD3 UR4, UR4, -0x1, URZ ; S2R R7, SR_CTAID.Z ; IMAD R20, R7, c[0x0][0x8], R6 ; IADD3 R6, R20.reuse, 0x1, RZ ; IADD3 R8, R20.reuse, 0x2, RZ ; IADD3 R10, R20.reuse, 0x3, RZ ; I2F.F64 R6, R6 ; IADD3 R12, R20.reuse, -0x1, RZ ; IADD3 R16, R20.reuse, -0x2, RZ ; IADD3 R20, R20, -0x3, RZ ; I2F.F64 R8, R8 ; I2F.F64 R10, R10 ; DSETP.MAX.AND P0, P3, RZ, R6, PT ; IMAD.MOV.U32 R17, RZ, RZ, R6 ; IMAD.MOV.U32 R21, RZ, RZ, R7 ; I2F.F64 R12, R12 ; DSETP.MAX.AND P5, P6, RZ, R8, PT ; IMAD.MOV.U32 R23, RZ, RZ, R8 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; I2F.F64 R6, UR4 ; DSETP.MAX.AND P2, P4, RZ, R10, PT ; MOV R25, R10 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; IMAD.MOV.U32 R24, RZ, RZ, R11 ; FSEL R11, R8, R21, P0 ; SEL R10, R10, R17, P0 ; DSETP.MAX.AND P1, P0, RZ, R12, PT ; @P3 LOP3.LUT R11, R21, 0x80000, RZ, 0xfc, !PT ; I2F.F64 R16, R16 ; IMAD.MOV.U32 R29, RZ, RZ, R13 ; FSEL R13, R8.reuse, R9, P5 ; IMAD.MOV.U32 R27, RZ, RZ, R12 ; @P6 LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P3, PT, R10, R6, PT ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; MOV R9, RZ ; I2F.F64 R20, R20 ; SEL R8, R8, R25, P2 ; FSEL R22, R6, R10, P3 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; FSEL R9, R9, R24, P2 ; SEL R12, R12, R23, P5 ; IMAD.MOV.U32 R25, RZ, RZ, R16 ; @P4 LOP3.LUT R9, R24, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R31, RZ, RZ, R17 ; FSEL R23, R7, R11, P3 ; DSETP.MAX.AND P2, P3, RZ, R16, PT ; FSEL R11, R10.reuse, R29, P1 ; IMAD.MOV.U32 R16, RZ, RZ, RZ ; @P0 LOP3.LUT R11, R29, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P5, PT, R12, R6.reuse, PT ; SEL R10, R10, R27, P1 ; F2I.F64.TRUNC R22, R22 ; IMAD.MOV.U32 R24, RZ, RZ, R21 ; DSETP.GT.AND P0, PT, R8, R6.reuse, PT ; IMAD.MOV.U32 R33, RZ, RZ, R20 ; FSEL R12, R6, R12, P5 ; IMAD.MOV.U32 R27, RZ, RZ, 0x8 ; FSEL R13, R7.reuse, R13, P5 ; DSETP.GT.AND P1, PT, R10, R6, PT ; FSEL R17, R7, R9, P0 ; FSEL R23, R16, R31, P2 ; DSETP.MAX.AND P4, P5, RZ, R20, PT ; FSEL R16, R6.reuse, R8, P0 ; F2I.F64.TRUNC R12, R12 ; CS2R R8, SRZ ; @P3 LOP3.LUT R23, R31, 0x80000, RZ, 0xfc, !PT ; FSEL R21, R7, R11, P1 ; FSEL R20, R6, R10, P1 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; FSEL R11, R9, R24, P4 ; F2I.F64.TRUNC R16, R16 ; SEL R8, R8, R25, P2 ; MOV R9, R23 ; SEL R10, R10, R33, P4 ; @P5 LOP3.LUT R11, R24, 0x80000, RZ, 0xfc, !PT ; F2I.F64.TRUNC R20, R20 ; DSETP.GT.AND P0, PT, R8, R6, PT ; IMAD R13, R12, c[0x0][0x1f4], R5 ; IMAD R13, R13, c[0x0][0x1f0], R4.reuse ; FSEL R8, R6, R8, P0 ; IMAD R17, R16, c[0x0][0x1f4], R5.reuse ; FSEL R9, R7, R9, P0 ; DSETP.GT.AND P0, PT, R10, R6, PT ; IMAD.WIDE R24, R13, R27, c[0x0][0x170] ; F2I.F64.TRUNC R8, R8 ; IMAD R26, R17, c[0x0][0x1f0], R4.reuse ; FSEL R6, R6, R10, P0 ; IMAD R21, R20, c[0x0][0x1f4], R5.reuse ; FSEL R7, R7, R11, P0 ; IMAD R11, R22, c[0x0][0x1f4], R5 ; LDG.E.64 R24, [R24.64] ; IMAD R16, R21, c[0x0][0x1f0], R4.reuse ; F2I.F64.TRUNC R6, R6 ; IMAD R11, R11, c[0x0][0x1f0], R4 ; IMAD.WIDE R16, R16, R27, c[0x0][0x170] ; IMAD R23, R8, c[0x0][0x1f4], R5.reuse ; IMAD.WIDE R28, R11, R27.reuse, c[0x0][0x170] ; LDG.E.64 R16, [R16.64] ; IMAD R20, R23, c[0x0][0x1f0], R4 ; LDG.E.64 R28, [R28.64] ; IMAD R5, R6, c[0x0][0x1f4], R5 ; IMAD.WIDE R20, R20, R27, c[0x0][0x170] ; IMAD R5, R5, c[0x0][0x1f0], R4 ; LDG.E.64 R20, [R20.64] ; IMAD.WIDE R36, R5, R27, c[0x0][0x170] ; IMAD.WIDE R26, R26, R27, c[0x0][0x170] ; LDG.E.64 R36, [R36.64] ; LDG.E.64 R26, [R26.64] ; DSETP.GEU.AND P0, PT, R50, c[0x0][0x210], PT ; DSETP.GEU.AND P1, PT, R46, c[0x0][0x210], PT ; BSSY B2, 0x13230 ; @P0 BRA P1, 0xf110 ; IADD3 R32, P1, R2, c[0x0][0x1e0], RZ ; IADD3.X R33, R0, c[0x0][0x1e4], RZ, P1, !PT ; LDG.E.64 R32, [R32.64] ; IADD3 R34, P1, R2, c[0x0][0x1e8], RZ ; IADD3.X R35, R0, c[0x0][0x1ec], RZ, P1, !PT ; LDG.E.64 R34, [R34.64] ; DSETP.GEU.AND P1, PT, R46, c[0x0][0x210], PT ; IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x210] ; BSSY B3, 0xd8f0 ; IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x214] ; IMAD.MOV.U32 R22, RZ, RZ, c[0x0][0x210] ; IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x214] ; DADD R30, R12, c[0x0][0x210] ; @!P0 IMAD.MOV.U32 R44, RZ, RZ, R50 ; @!P0 IMAD.MOV.U32 R45, RZ, RZ, R51 ; DMUL R38, R12.reuse, -2 ; @!P0 IMAD.MOV.U32 R36, RZ, RZ, R20 ; @P1 MOV R46, c[0x0][0x210] ; @!P0 IMAD.MOV.U32 R37, RZ, RZ, R21 ; @P1 DMUL R6, R12, 3 ; @P1 IMAD.MOV.U32 R47, RZ, RZ, c[0x0][0x214] ; @P1 MOV R22, R30 ; @P1 IMAD.MOV.U32 R23, RZ, RZ, R31 ; @P1 IMAD.MOV.U32 R30, RZ, RZ, R6 ; @P1 IMAD.MOV.U32 R31, RZ, RZ, R7 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R8, -R22, R30 ; MUFU.RCP64H R7, R9 ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; @P1 IMAD.MOV.U32 R32, RZ, RZ, R28 ; @P1 MOV R28, R24 ; @P1 IMAD.MOV.U32 R33, RZ, RZ, R29 ; @P1 IMAD.MOV.U32 R29, RZ, RZ, R25 ; @P1 IMAD.MOV.U32 R24, RZ, RZ, R26 ; @P1 IMAD.MOV.U32 R25, RZ, RZ, R27 ; @P0 DMUL R26, R12, -3 ; @P0 IMAD.MOV.U32 R34, RZ, RZ, R16 ; @P0 IMAD.MOV.U32 R35, RZ, RZ, R17 ; DADD R52, R24, -R28 ; @!P0 IMAD.MOV.U32 R26, RZ, RZ, R38 ; @!P0 MOV R27, R39 ; @P0 IMAD.MOV.U32 R16, RZ, RZ, R20 ; @!P0 DADD R38, -RZ, -c[0x0][0x210] ; @P0 IMAD.MOV.U32 R17, RZ, RZ, R21 ; DMUL R24, R52, R6 ; FSETP.GEU.AND P3, PT, |R53|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R24, R52 ; DFMA R24, R6, R10, R24 ; FFMA R5, RZ, R9, R25 ; FSETP.GT.AND P2, PT, |R5|, 1.469367938527859385e-39, PT ; @P2 BRA P3, 0xd8e0 ; IMAD.MOV.U32 R10, RZ, RZ, R52 ; MOV R6, 0xd8c0 ; IMAD.MOV.U32 R7, RZ, RZ, R53 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R24, RZ, RZ, R8 ; IMAD.MOV.U32 R25, RZ, RZ, R7 ; BSYNC B3 ; DADD R12, R22, -R46 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0xda80 ; DADD R10, -R32, R28 ; MUFU.RCP64H R7, R13 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R12, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R12, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R20, R10, R6 ; DFMA R8, -R12, R20, R10 ; DFMA R20, R6, R8, R20 ; FFMA R5, RZ, R13, R21 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xda70 ; MOV R7, R11 ; IMAD.MOV.U32 R8, RZ, RZ, R12 ; MOV R6, 0xda50 ; IMAD.MOV.U32 R9, RZ, RZ, R13 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R20, RZ, RZ, R8 ; IMAD.MOV.U32 R21, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R47 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R48, R32 ; BSSY B3, 0xdc00 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R46, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R46, 1 ; DFMA R6, R8, R6, R8 ; DMUL R32, R10, R6 ; DFMA R8, R32, -R46, R10 ; DFMA R32, R6, R8, R32 ; FFMA R5, RZ, R47, R33 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xdbf0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R8, R46 ; IMAD.MOV.U32 R9, RZ, RZ, R47 ; MOV R6, 0xdbd0 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R32, RZ, RZ, R8 ; IMAD.MOV.U32 R33, RZ, RZ, R7 ; BSYNC B3 ; DADD R28, RZ, R44 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0xdd90 ; DADD R10, R48, -R34 ; MUFU.RCP64H R7, R29 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R28, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R28, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R48, R10, R6 ; DFMA R8, -R28, R48, R10 ; DFMA R48, R6, R8, R48 ; FFMA R5, RZ, R29, R49 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xdd80 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R9, R29 ; IMAD.MOV.U32 R8, RZ, RZ, R28 ; MOV R6, 0xdd60 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R48, RZ, RZ, R8 ; IMAD.MOV.U32 R49, RZ, RZ, R7 ; BSYNC B3 ; DADD R12, -R38, -R44 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0xdf20 ; DADD R10, R34, -R16 ; MUFU.RCP64H R7, R13 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R12, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R12, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R34, R10, R6 ; DFMA R8, -R12, R34, R10 ; DFMA R34, R6, R8, R34 ; FFMA R5, RZ, R13, R35 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xdf10 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xdef0 ; IMAD.MOV.U32 R8, RZ, RZ, R12 ; IMAD.MOV.U32 R9, RZ, RZ, R13 ; CALL.REL.NOINC 0x135e0 ; MOV R34, R8 ; IMAD.MOV.U32 R35, RZ, RZ, R7 ; BSYNC B3 ; DADD R12, -R26, R38 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0xe0b0 ; DADD R10, R16, -R36 ; MUFU.RCP64H R7, R13 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R12, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R12, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R16, R10, R6 ; DFMA R8, -R12, R16, R10 ; DFMA R16, R6, R8, R16 ; FFMA R5, RZ, R13, R17 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xe0a0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xe080 ; IMAD.MOV.U32 R8, RZ, RZ, R12 ; IMAD.MOV.U32 R9, RZ, RZ, R13 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R16, RZ, RZ, R8 ; MOV R17, R7 ; BSYNC B3 ; DADD R12, R30, -R46 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0xe240 ; DADD R10, -R20, R24 ; MUFU.RCP64H R7, R13 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R12, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R12, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R24, R10, R6 ; DFMA R8, -R12, R24, R10 ; DFMA R24, R6, R8, R24 ; FFMA R5, RZ, R13, R25 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xe230 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xe210 ; IMAD.MOV.U32 R8, RZ, RZ, R12 ; IMAD.MOV.U32 R9, RZ, RZ, R13 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R24, RZ, RZ, R8 ; IMAD.MOV.U32 R25, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R23 ; MOV R6, 0x1 ; DADD R10, -R32, R20 ; BSSY B3, 0xe3c0 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R22, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R22, 1 ; DFMA R6, R8, R6, R8 ; DMUL R52, R10, R6 ; DFMA R8, R52, -R22, R10 ; DFMA R52, R6, R8, R52 ; FFMA R5, RZ, R23, R53 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xe3b0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xe390 ; IMAD.MOV.U32 R8, RZ, RZ, R22 ; IMAD.MOV.U32 R9, RZ, RZ, R23 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R52, RZ, RZ, R8 ; IMAD.MOV.U32 R53, RZ, RZ, R7 ; BSYNC B3 ; DADD R12, R46, R44 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0xe550 ; DADD R10, -R48, R32 ; MUFU.RCP64H R7, R13 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R12, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R12, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R50, R10, R6 ; DFMA R8, -R12, R50, R10 ; DFMA R50, R6, R8, R50 ; FFMA R5, RZ, R13, R51 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xe540 ; MOV R7, R11 ; IMAD.MOV.U32 R8, RZ, RZ, R12 ; MOV R6, 0xe520 ; IMAD.MOV.U32 R9, RZ, RZ, R13 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R50, RZ, RZ, R8 ; IMAD.MOV.U32 R51, RZ, RZ, R7 ; BSYNC B3 ; DADD R20, RZ, -R38 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0xe6e0 ; DADD R10, -R34, R48 ; MUFU.RCP64H R7, R21 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R20, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R20, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R36, R10, R6 ; DFMA R8, -R20, R36, R10 ; DFMA R36, R6, R8, R36 ; FFMA R5, RZ, R21, R37 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xe6d0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R8, R20 ; IMAD.MOV.U32 R9, RZ, RZ, R21 ; MOV R6, 0xe6b0 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R36, RZ, RZ, R8 ; IMAD.MOV.U32 R37, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, -R26, -R44 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0xe860 ; DADD R34, -R16, R34 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R35|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R16, R34, R6 ; DFMA R10, -R8, R16, R34 ; DFMA R16, R6, R10, R16 ; FFMA R5, RZ, R9, R17 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xe850 ; IMAD.MOV.U32 R10, RZ, RZ, R34 ; MOV R6, 0xe830 ; IMAD.MOV.U32 R7, RZ, RZ, R35 ; CALL.REL.NOINC 0x135e0 ; MOV R16, R8 ; IMAD.MOV.U32 R17, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R31 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R52, R24 ; BSSY B3, 0xe9e0 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R30, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R30, 1 ; DFMA R6, R8, R6, R8 ; DMUL R24, R10, R6 ; DFMA R8, R24, -R30, R10 ; DFMA R24, R6, R8, R24 ; FFMA R5, RZ, R31, R25 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xe9d0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xe9b0 ; IMAD.MOV.U32 R8, RZ, RZ, R30 ; IMAD.MOV.U32 R9, RZ, RZ, R31 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R24, RZ, RZ, R8 ; MOV R25, R7 ; BSYNC B3 ; DADD R44, R22, R44 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0xeb70 ; DADD R10, -R50, R52 ; MUFU.RCP64H R7, R45 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R44, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R44, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R30, R10, R6 ; DFMA R8, -R44, R30, R10 ; DFMA R30, R6, R8, R30 ; FFMA R5, RZ, R45, R31 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xeb60 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xeb40 ; IMAD.MOV.U32 R8, RZ, RZ, R44 ; IMAD.MOV.U32 R9, RZ, RZ, R45 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; IMAD.MOV.U32 R31, RZ, RZ, R7 ; BSYNC B3 ; DADD R38, -R38, R46 ; MOV R6, 0x1 ; BSSY B3, 0xed00 ; DADD R10, -R36, R50 ; MUFU.RCP64H R7, R39 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R38, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R38, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R34, R10, R6 ; DFMA R8, -R38, R34, R10 ; DFMA R34, R6, R8, R34 ; FFMA R5, RZ, R39, R35 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xecf0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xecd0 ; IMAD.MOV.U32 R8, RZ, RZ, R38 ; IMAD.MOV.U32 R9, RZ, RZ, R39 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R34, RZ, RZ, R8 ; IMAD.MOV.U32 R35, RZ, RZ, R7 ; BSYNC B3 ; DADD R26, RZ, -R26 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0xee90 ; DADD R16, -R16, R36 ; MUFU.RCP64H R7, R27 ; FSETP.GEU.AND P1, PT, |R17|, 6.5827683646048100446e-37, PT ; DFMA R8, -R26, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R26, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R8, R16, R6 ; DFMA R10, -R26, R8, R16 ; DFMA R6, R6, R10, R8 ; FFMA R5, RZ, R27, R7 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xee80 ; MOV R10, R16 ; IMAD.MOV.U32 R7, RZ, RZ, R17 ; MOV R6, 0xee70 ; IMAD.MOV.U32 R8, RZ, RZ, R26 ; IMAD.MOV.U32 R9, RZ, RZ, R27 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; BSYNC B3 ; DSETP.GEU.AND P0, PT, |R34|, |R6|, PT ; DMUL R10, R50, R52 ; FSEL R6, R34, R6, !P0 ; DADD R46, RZ, -R46 ; FSEL R7, R35, R7, !P0 ; DADD R22, RZ, -R22 ; DSETP.GEU.AND P2, PT, |R30|, |R24|, PT ; DMUL R8, R36, R50 ; DMUL R20, R28, R20 ; DSETP.GEU.AND P0, PT, |R34|, |R30|, PT ; DSETP.GEU.AND P5, PT, R10, RZ, PT ; FSEL R10, R30, R24, !P2 ; DMUL R22, R46, R22 ; FSEL R11, R31, R25, !P2 ; DSETP.GEU.AND P4, PT, R8, RZ, PT ; FSEL R8, R34, R30, !P0 ; DMUL R20, R20, R6 ; FSEL R9, R35, R31, !P0 ; DSETP.GEU.AND P1, PT, |R36|, |R50|, PT ; DSETP.GEU.AND P3, PT, |R50|, |R52|, PT ; FSEL R5, R36, R50, !P1 ; DMUL R6, R28, R46 ; FSEL R36, R37, R51, !P1 ; DMUL R22, R22, R10 ; FSEL R10, R50, R52, !P3 ; FSEL R50, R51, R53, !P3 ; DMUL R6, R6, R8 ; FSEL R10, R10, RZ, P5 ; FSEL R8, R5, RZ, P4 ; FSEL R9, R36, RZ, P4 ; FSEL R11, R50, RZ, P5 ; FSEL R30, R20, R6, !P1 ; DFMA R28, R28, R8, R48 ; FSEL R31, R21, R7, !P1 ; FSEL R38, R6, R22, !P3 ; DFMA R32, R46, R10, R32 ; FSEL R39, R7, R23, !P3 ; DADD R30, R28, R30 ; DADD R38, R32, R38 ; BRA 0x13220 ; MUFU.RCP64H R7, c[0x0][0x214] ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x210] ; MOV R6, 0x1 ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x214] ; BSSY B3, 0xf2b0 ; DFMA R8, R6, -R10, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R10, 1 ; DADD R10, R20, -R36 ; DFMA R6, R8, R6, R8 ; DMUL R22, R10, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R22, -c[0x0][0x210], R10 ; DFMA R22, R6, R8, R22 ; FFMA R5, RZ, c[0x0][0x214], R23 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xf2a0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xf280 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x210] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x214] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R22, RZ, RZ, R8 ; IMAD.MOV.U32 R23, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x214] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x210] ; MOV R9, c[0x0][0x214] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B3, 0xf450 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, -R20, R16 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R20, R8, R10 ; DFMA R6, R20, -c[0x0][0x210], R10 ; DFMA R20, R8, R6, R20 ; FFMA R5, RZ, c[0x0][0x214], R21 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xf440 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xf420 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x210] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x214] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R20, RZ, RZ, R8 ; IMAD.MOV.U32 R21, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x214] ; MOV R8, c[0x0][0x210] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x214] ; BSSY B3, 0xf5f0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, R48, -R16 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R16, R8, R10 ; DFMA R6, R16, -c[0x0][0x210], R10 ; DFMA R16, R8, R6, R16 ; FFMA R5, RZ, c[0x0][0x214], R17 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xf5e0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xf5c0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x210] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x214] ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R16, RZ, RZ, R8 ; MOV R17, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x214] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x210] ; BSSY B3, 0xf790 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x214] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, -R48, R28 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R52, R8, R10 ; DFMA R6, R52, -c[0x0][0x210], R10 ; DFMA R52, R8, R6, R52 ; FFMA R5, RZ, c[0x0][0x214], R53 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xf780 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xf760 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x210] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x214] ; CALL.REL.NOINC 0x135e0 ; MOV R52, R8 ; IMAD.MOV.U32 R53, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x214] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x210] ; BSSY B3, 0xf930 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x214] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, -R28, R24 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R50, R8, R10 ; DFMA R6, R50, -c[0x0][0x210], R10 ; DFMA R50, R8, R6, R50 ; FFMA R5, RZ, c[0x0][0x214], R51 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xf920 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R9, c[0x0][0x214] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x210] ; MOV R6, 0xf900 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R50, RZ, RZ, R8 ; IMAD.MOV.U32 R51, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, c[0x0][0x214] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x210] ; BSSY B3, 0xfad0 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x214] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, R26, -R24 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R48, R8, R10 ; DFMA R6, R48, -c[0x0][0x210], R10 ; DFMA R48, R8, R6, R48 ; FFMA R5, RZ, c[0x0][0x214], R49 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xfac0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R8, c[0x0][0x210] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x214] ; MOV R6, 0xfaa0 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R48, RZ, RZ, R8 ; IMAD.MOV.U32 R49, RZ, RZ, R7 ; BSYNC B3 ; DADD R8, R20.reuse, R20 ; BSSY B1, 0xfc10 ; MOV R10, 0xfc00 ; DMUL R38, R20, c[0x2][0x20] ; DADD R8, -R8, R22 ; DMUL R6, R20, c[0x2][0x8] ; DADD R28, R8, R16 ; DMUL R32, R52, c[0x2][0x28] ; DADD R8, -RZ, |R28| ; DFMA R34, R16, c[0x2][0x28], -R38 ; DFMA R6, R22, c[0x2][0x10], R6 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; DMUL R36, R52, c[0x2][0x10] ; DFMA R30, R16, c[0x2][0x10], R32 ; DFMA R34, R52, c[0x2][0x10], R34 ; DFMA R44, R16, c[0x2][0x18], R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R28.reuse, 2 ; BSSY B1, 0xfd50 ; MOV R46, R6 ; IMAD.MOV.U32 R47, RZ, RZ, R7 ; DSETP.NEU.AND P0, PT, R28, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R46, SRZ ; @P1 BRA 0xfd40 ; DSETP.GTU.AND P0, PT, |R28|, +INF , PT ; @P0 BRA 0xfd30 ; ISETP.NE.AND P0, PT, R28, RZ, PT ; LOP3.LUT R5, R29, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xfd40 ; IMAD.MOV.U32 R46, RZ, RZ, 0x0 ; IMAD.MOV.U32 R47, RZ, RZ, 0x7ff00000 ; BRA 0xfd40 ; DADD R46, R28, 2 ; BSYNC B1 ; DFMA R24, R20, -4, R22 ; BSSY B1, 0xfe00 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R10, 0xfdf0 ; DMUL R26, R16, 3 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R24, R24, R26 ; DADD R8, -RZ, |R24| ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R24.reuse, 2 ; BSSY B1, 0xff60 ; DSETP.NEU.AND P1, PT, R24, RZ, PT ; DMUL R10, R46, c[0x2][0x30] ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; DSETP.NEU.AND P0, PT, R28, 1, PT ; ISETP.NE.AND P2, PT, R8, 0x7ff00000, PT ; FSEL R46, R10, 1.46601546874880000000e+13, P0 ; @!P1 CS2R R6, SRZ ; FSEL R47, R11, 1.8854166269302368164, P0 ; @P2 BRA 0xff50 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0xff40 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R5, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xff50 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xff50 ; DADD R6, R24, 2 ; BSYNC B1 ; DADD R28, R16, R16 ; BSSY B1, 0x10060 ; MOV R10, 0x10050 ; DMUL R6, R6, 0.25 ; DADD R22, -R28, R20 ; DSETP.NEU.AND P0, PT, R24, 1, PT ; DADD R22, R22, R52 ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R8, -RZ, |R22| ; DADD R46, R46, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R22.reuse, 2 ; BSSY B1, 0x10180 ; DSETP.NEU.AND P0, PT, R22, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x10170 ; DSETP.GTU.AND P0, PT, |R22|, +INF , PT ; @P0 BRA 0x10160 ; ISETP.NE.AND P0, PT, R22, RZ, PT ; LOP3.LUT R5, R23, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x10170 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x10170 ; DADD R6, R22, 2 ; BSYNC B1 ; DADD R24, -R52, R20 ; BSSY B1, 0x10250 ; MOV R10, 0x10240 ; DMUL R6, R6, c[0x2][0x30] ; DADD R8, -RZ, |R24| ; DSETP.NEU.AND P0, PT, R22, 1, PT ; FSEL R56, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R57, R7, 1.8854166269302368164, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; MOV R11, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R24.reuse, 2 ; BSSY B1, 0x10370 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x10360 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x10350 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R5, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x10360 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x10360 ; DADD R6, R24, 2 ; BSYNC B1 ; DADD R22, R52, R52 ; BSSY B1, 0x10470 ; MOV R10, 0x10460 ; DMUL R6, R6, 0.25 ; DADD R54, -R22, R16 ; DSETP.NEU.AND P0, PT, R24, 1, PT ; DADD R54, R54, R50 ; FSEL R24, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R25, R7, 1.625, P0 ; DADD R8, -RZ, |R54| ; MOV R7, 0x40000000 ; DADD R24, R56, R24 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R54.reuse, 2 ; BSSY B1, 0x10590 ; DSETP.NEU.AND P0, PT, R54, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x10580 ; DSETP.GTU.AND P0, PT, |R54|, +INF , PT ; @P0 BRA 0x10570 ; ISETP.NE.AND P0, PT, R54, RZ, PT ; LOP3.LUT R5, R55, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x10580 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x10580 ; DADD R6, R54, 2 ; BSYNC B1 ; DFMA R26, R52, -4, R26 ; BSSY B1, 0x10670 ; MOV R10, 0x10660 ; DMUL R6, R6, c[0x2][0x30] ; DADD R26, R26, R50 ; DSETP.NEU.AND P0, PT, R54, 1, PT ; DADD R8, -RZ, |R26| ; FSEL R54, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R55, R7, 1.8854166269302368164, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R26.reuse, 2 ; BSSY B1, 0x10790 ; DSETP.NEU.AND P0, PT, R26, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x10780 ; DSETP.GTU.AND P0, PT, |R26|, +INF , PT ; @P0 BRA 0x10770 ; ISETP.NE.AND P0, PT, R26, RZ, PT ; LOP3.LUT R5, R27, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x10780 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; MOV R7, 0x7ff00000 ; BRA 0x10780 ; DADD R6, R26, 2 ; BSYNC B1 ; DMUL R6, R6, 0.25 ; BSSY B1, 0x10870 ; MOV R10, 0x10860 ; DADD R46, R46, c[0x2][0x0] ; DSETP.NEU.AND P0, PT, R26, 1, PT ; DADD R8, -RZ, |R46| ; FSEL R26, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R27, R7, 1.625, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R26, R54, R26 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R46.reuse, 2 ; BSSY B1, 0x10990 ; DSETP.NEU.AND P0, PT, R46, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x10980 ; DSETP.GTU.AND P0, PT, |R46|, +INF , PT ; @P0 BRA 0x10970 ; ISETP.NE.AND P0, PT, R46, RZ, PT ; LOP3.LUT R5, R47, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x10980 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x10980 ; DADD R6, R46, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0x10af0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x38] ; DFMA R12, R10, -R6, c[0x2][0x38] ; DFMA R8, R8, R12, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0x10ae0 ; MOV R8, R6 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; MOV R6, 0x10ad0 ; IMAD.MOV.U32 R10, RZ, RZ, -0x66666666 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fb99999 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DADD R24, R24, c[0x2][0x0] ; BSSY B1, 0x10bb0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R7, 0x40000000 ; DSETP.NEU.AND P0, PT, R46, 1, PT ; DADD R10, -RZ, |R24| ; FSEL R46, R8, -1.5881868392106855534e-23, P0 ; FSEL R47, R9, 1.4499999284744262695, P0 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MOV R10, 0x10ba0 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R24.reuse, 2 ; BSSY B1, 0x10cd0 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x10cc0 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x10cb0 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R5, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x10cc0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x10cc0 ; DADD R6, R24, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0x10e30 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x40] ; DFMA R12, R10, -R6, c[0x2][0x40] ; DFMA R8, R8, R12, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0x10e20 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x10e10 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; MOV R7, 0x3fe33333 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DADD R26, R26, c[0x2][0x0] ; BSSY B1, 0x10ef0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R24, 1, PT ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R26| ; FSEL R24, R8, 4.172325063223070174e-08, P0 ; FSEL R25, R9, 1.7749999761581420898, P0 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MOV R10, 0x10ee0 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R26.reuse, 2 ; BSSY B1, 0x11010 ; DSETP.NEU.AND P0, PT, R26, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x11000 ; DSETP.GTU.AND P0, PT, |R26|, +INF , PT ; @P0 BRA 0x10ff0 ; ISETP.NE.AND P0, PT, R26, RZ, PT ; LOP3.LUT R5, R27, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x11000 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x11000 ; DADD R6, R26, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; MOV R8, 0x1 ; BSSY B3, 0x11170 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x48] ; DFMA R12, R10, -R6, c[0x2][0x48] ; DFMA R8, R8, R12, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0x11160 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x11150 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fd33333 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DSETP.NEU.AND P0, PT, R26, 1, PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R47|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x11340 ; DADD R26, R46, R24 ; FSEL R54, R8, 4.172325063223070174e-08, P0 ; FSEL R55, R9, 1.6499999761581420898, P0 ; DADD R26, R26, R54 ; MUFU.RCP64H R7, R27 ; DFMA R8, -R26, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R26, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R56, R6, R46 ; DFMA R8, -R26, R56, R46 ; DFMA R56, R6, R8, R56 ; FFMA R5, RZ, R27, R57 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x11330 ; MOV R10, R46 ; IMAD.MOV.U32 R7, RZ, RZ, R47 ; MOV R6, 0x11310 ; IMAD.MOV.U32 R8, RZ, RZ, R26 ; IMAD.MOV.U32 R9, RZ, RZ, R27 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R56, RZ, RZ, R8 ; IMAD.MOV.U32 R57, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R27 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R25|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x114e0 ; DFMA R8, -R26, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R26, R8, 1 ; DFMA R8, R8, R6, R8 ; MOV R6, R24 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; DMUL R46, R8, R6 ; DFMA R6, -R26, R46, R6 ; DFMA R46, R8, R6, R46 ; FFMA R5, RZ, R27, R47 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x114d0 ; IMAD.MOV.U32 R10, RZ, RZ, R24 ; MOV R6, 0x114b0 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; IMAD.MOV.U32 R8, RZ, RZ, R26 ; IMAD.MOV.U32 R9, RZ, RZ, R27 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R46, RZ, RZ, R8 ; MOV R47, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R27 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R55|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x11670 ; DFMA R8, -R26, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R26, R8, 1 ; DFMA R10, R8, R6, R8 ; IMAD.MOV.U32 R8, RZ, RZ, R54 ; IMAD.MOV.U32 R9, RZ, RZ, R55 ; DMUL R6, R10, R8 ; DFMA R8, -R26, R6, R8 ; DFMA R6, R10, R8, R6 ; FFMA R5, RZ, R27, R7 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x11660 ; IMAD.MOV.U32 R8, RZ, RZ, R26 ; MOV R7, R55 ; IMAD.MOV.U32 R9, RZ, RZ, R27 ; MOV R6, 0x11650 ; IMAD.MOV.U32 R10, RZ, RZ, R54 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; BSYNC B3 ; DADD R8, R50, R50 ; BSSY B1, 0x117d0 ; DMUL R34, R34, R46 ; DADD R8, -R8, R48 ; DFMA R44, R44, R56, R34 ; DADD R34, R8, R52 ; DMUL R8, R50, c[0x2][0x8] ; DADD R10, -RZ, |R34| ; DFMA R36, R16, c[0x2][0x28], R36 ; DFMA R24, R50, c[0x2][0x50], R32 ; DFMA R8, R48, c[0x2][0x10], R8 ; DFMA R30, R50, c[0x2][0x50], R30 ; DADD R38, -R38, R36 ; DFMA R24, R16, c[0x2][0x10], R24 ; DFMA R26, R52, c[0x2][0x18], R8 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MOV R10, 0x117c0 ; DFMA R30, R30, R6, R44 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R34.reuse, 2 ; BSSY B1, 0x118f0 ; DSETP.NEU.AND P0, PT, R34, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x118e0 ; DSETP.GTU.AND P0, PT, |R34|, +INF , PT ; @P0 BRA 0x118d0 ; ISETP.NE.AND P0, PT, R34, RZ, PT ; LOP3.LUT R5, R35, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x118e0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x118e0 ; DADD R6, R34, 2 ; BSYNC B1 ; DFMA R36, R50, -4, R48 ; BSSY B1, 0x119e0 ; MOV R10, 0x119d0 ; DMUL R32, R52, 3 ; DMUL R6, R6, c[0x2][0x30] ; DADD R36, R36, R32 ; DSETP.NEU.AND P0, PT, R34, 1, PT ; DADD R8, -RZ, |R36| ; FSEL R34, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R35, R7, 1.8854166269302368164, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; MOV R11, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R36.reuse, 2 ; BSSY B1, 0x11b00 ; DSETP.NEU.AND P0, PT, R36, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x11af0 ; DSETP.GTU.AND P0, PT, |R36|, +INF , PT ; @P0 BRA 0x11ae0 ; ISETP.NE.AND P0, PT, R36, RZ, PT ; LOP3.LUT R5, R37, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x11af0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x11af0 ; DADD R6, R36, 2 ; BSYNC B1 ; DADD R22, -R22, R50 ; BSSY B1, 0x11bf0 ; MOV R10, 0x11be0 ; DMUL R6, R6, 0.25 ; DADD R22, R22, R16 ; DSETP.NEU.AND P0, PT, R36, 1, PT ; DADD R8, -RZ, |R22| ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R34, R34, R6 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; MOV R7, 0x40000000 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R22.reuse, 2 ; BSSY B1, 0x11d10 ; DSETP.NEU.AND P0, PT, R22, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x11d00 ; DSETP.GTU.AND P0, PT, |R22|, +INF , PT ; @P0 BRA 0x11cf0 ; ISETP.NE.AND P0, PT, R22, RZ, PT ; LOP3.LUT R5, R23, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x11d00 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x11d00 ; DADD R6, R22, 2 ; BSYNC B1 ; DADD R50, R50, -R16 ; BSSY B1, 0x11de0 ; MOV R10, 0x11dd0 ; DMUL R6, R6, c[0x2][0x30] ; DADD R8, -RZ, |R50| ; DSETP.NEU.AND P0, PT, R22, 1, PT ; FSEL R22, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; FSEL R23, R7, 1.8854166269302368164, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R50.reuse, 2 ; BSSY B1, 0x11f00 ; DSETP.NEU.AND P0, PT, R50, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x11ef0 ; DSETP.GTU.AND P0, PT, |R50|, +INF , PT ; @P0 BRA 0x11ee0 ; ISETP.NE.AND P0, PT, R50, RZ, PT ; LOP3.LUT R5, R51, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x11ef0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; MOV R7, 0x7ff00000 ; BRA 0x11ef0 ; DADD R6, R50, 2 ; BSYNC B1 ; DADD R28, -R28, R52 ; BSSY B1, 0x11ff0 ; MOV R10, 0x11fe0 ; DMUL R6, R6, 0.25 ; DADD R28, R28, R20 ; DSETP.NEU.AND P0, PT, R50, 1, PT ; DADD R8, -RZ, |R28| ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R22, R22, R6 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R28.reuse, 2 ; BSSY B1, 0x12110 ; DSETP.NEU.AND P0, PT, R28, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x12100 ; DSETP.GTU.AND P0, PT, |R28|, +INF , PT ; @P0 BRA 0x120f0 ; ISETP.NE.AND P0, PT, R28, RZ, PT ; LOP3.LUT R5, R29, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x12100 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x12100 ; DADD R6, R28, 2 ; BSYNC B1 ; DFMA R16, R16, -4, R32 ; BSSY B1, 0x121f0 ; MOV R10, 0x121e0 ; DMUL R6, R6, c[0x2][0x30] ; DADD R20, R16, R20 ; DSETP.NEU.AND P0, PT, R28, 1, PT ; DADD R8, -RZ, |R20| ; FSEL R28, R6, 1.46601546874880000000e+13, P0 ; FSEL R29, R7, 1.8854166269302368164, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; MOV R6, RZ ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R20.reuse, 2 ; BSSY B1, 0x12310 ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x12300 ; DSETP.GTU.AND P0, PT, |R20|, +INF , PT ; @P0 BRA 0x122f0 ; ISETP.NE.AND P0, PT, R20, RZ, PT ; LOP3.LUT R5, R21, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x12300 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x12300 ; DADD R6, R20, 2 ; BSYNC B1 ; DMUL R6, R6, 0.25 ; BSSY B1, 0x123f0 ; MOV R10, 0x123e0 ; DADD R16, R34, c[0x2][0x0] ; DSETP.NEU.AND P0, PT, R20, 1, PT ; DADD R8, -RZ, |R16| ; FSEL R20, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R21, R7, 1.625, P0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R20, R28, R20 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R16.reuse, 2 ; BSSY B1, 0x12510 ; DSETP.NEU.AND P0, PT, R16, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x12500 ; DSETP.GTU.AND P0, PT, |R16|, +INF , PT ; @P0 BRA 0x124f0 ; ISETP.NE.AND P0, PT, R16, RZ, PT ; LOP3.LUT R5, R17, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x12500 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x12500 ; DADD R6, R16, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0x12670 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x38] ; DFMA R12, R10, -R6, c[0x2][0x38] ; DFMA R8, R8, R12, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0x12660 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x12650 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, -0x66666666 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fb99999 ; CALL.REL.NOINC 0x135e0 ; MOV R9, R7 ; BSYNC B3 ; DADD R22, R22, c[0x2][0x0] ; BSSY B1, 0x12730 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R16, 1, PT ; IMAD.MOV.U32 R7, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R22| ; FSEL R16, R8, -1.5881868392106855534e-23, P0 ; FSEL R17, R9, 1.4499999284744262695, P0 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MOV R10, 0x12720 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R22.reuse, 2 ; BSSY B1, 0x12850 ; DSETP.NEU.AND P0, PT, R22, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x12840 ; DSETP.GTU.AND P0, PT, |R22|, +INF , PT ; @P0 BRA 0x12830 ; ISETP.NE.AND P0, PT, R22, RZ, PT ; LOP3.LUT R5, R23, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x12840 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x12840 ; DADD R6, R22, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0x129b0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x40] ; DFMA R12, R10, -R6, c[0x2][0x40] ; DFMA R8, R8, R12, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0x129a0 ; MOV R8, R6 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; MOV R6, 0x12990 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fe33333 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DADD R20, R20, c[0x2][0x0] ; BSSY B1, 0x12a70 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R7, 0x40000000 ; DSETP.NEU.AND P0, PT, R22, 1, PT ; DADD R10, -RZ, |R20| ; FSEL R22, R8, 4.172325063223070174e-08, P0 ; FSEL R23, R9, 1.7749999761581420898, P0 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; MOV R10, 0x12a60 ; CALL.REL.NOINC 0x13c50 ; BSYNC B1 ; DADD R8, R20.reuse, 2 ; BSSY B1, 0x12b90 ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x12b80 ; DSETP.GTU.AND P0, PT, |R20|, +INF , PT ; @P0 BRA 0x12b70 ; ISETP.NE.AND P0, PT, R20, RZ, PT ; LOP3.LUT R5, R21, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x12b80 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x12b80 ; DADD R6, R20, 2 ; BSYNC B1 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B3, 0x12cf0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x48] ; DFMA R12, R10, -R6, c[0x2][0x48] ; DFMA R8, R8, R12, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0x12ce0 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x12cd0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; MOV R7, 0x3fd33333 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; BSYNC B3 ; DSETP.NEU.AND P0, PT, R20, 1, PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R17|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x12ec0 ; DADD R20, R16, R22 ; FSEL R28, R8, 4.172325063223070174e-08, P0 ; FSEL R29, R9, 1.6499999761581420898, P0 ; DADD R20, R20, R28 ; MUFU.RCP64H R7, R21 ; DFMA R8, -R20, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R20, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R32, R6, R16 ; DFMA R8, -R20, R32, R16 ; DFMA R32, R6, R8, R32 ; FFMA R5, RZ, R21, R33 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x12eb0 ; IMAD.MOV.U32 R10, RZ, RZ, R16 ; MOV R6, 0x12e90 ; IMAD.MOV.U32 R7, RZ, RZ, R17 ; IMAD.MOV.U32 R8, RZ, RZ, R20 ; IMAD.MOV.U32 R9, RZ, RZ, R21 ; CALL.REL.NOINC 0x135e0 ; MOV R32, R8 ; IMAD.MOV.U32 R33, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R21 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x13060 ; DFMA R8, -R20, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R20, R8, 1 ; DFMA R8, R8, R6, R8 ; IMAD.MOV.U32 R6, RZ, RZ, R22 ; IMAD.MOV.U32 R7, RZ, RZ, R23 ; DMUL R16, R8, R6 ; DFMA R6, -R20, R16, R6 ; DFMA R16, R8, R6, R16 ; FFMA R5, RZ, R21, R17 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x13050 ; IMAD.MOV.U32 R10, RZ, RZ, R22 ; MOV R8, R20 ; IMAD.MOV.U32 R7, RZ, RZ, R23 ; MOV R6, 0x13030 ; IMAD.MOV.U32 R9, RZ, RZ, R21 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R16, RZ, RZ, R8 ; IMAD.MOV.U32 R17, RZ, RZ, R7 ; BSYNC B3 ; MUFU.RCP64H R7, R21 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R29|, 6.5827683646048100446e-37, PT ; BSSY B3, 0x131f0 ; DFMA R8, -R20, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R20, R8, 1 ; DFMA R10, R8, R6, R8 ; IMAD.MOV.U32 R8, RZ, RZ, R28 ; IMAD.MOV.U32 R9, RZ, RZ, R29 ; DMUL R6, R10, R8 ; DFMA R8, -R20, R6, R8 ; DFMA R6, R10, R8, R6 ; FFMA R5, RZ, R21, R7 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x131e0 ; MOV R8, R20 ; IMAD.MOV.U32 R9, RZ, RZ, R21 ; MOV R6, 0x131d0 ; IMAD.MOV.U32 R10, RZ, RZ, R28 ; IMAD.MOV.U32 R7, RZ, RZ, R29 ; CALL.REL.NOINC 0x135e0 ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; BSYNC B3 ; DMUL R24, R24, R16 ; DFMA R24, R26, R32, R24 ; DFMA R38, R38, R6, R24 ; BSYNC B2 ; IADD3 R8, P0, R2, c[0x0][0x178], RZ ; IADD3.X R9, R0, c[0x0][0x17c], RZ, P0, !PT ; LDG.E.64 R8, [R8.64] ; IADD3 R12, P0, R2, c[0x0][0x180], RZ ; IADD3.X R13, R0, c[0x0][0x184], RZ, P0, !PT ; LDG.E.64 R12, [R12.64] ; IADD3 R16, P0, R2, c[0x0][0x188], RZ ; IADD3.X R17, R0, c[0x0][0x18c], RZ, P0, !PT ; LDG.E.64 R16, [R16.64] ; IADD3 R6, P0, R2, c[0x0][0x168], RZ ; IADD3.X R7, R0, c[0x0][0x16c], RZ, P0, !PT ; LDG.E.64 R6, [R6.64] ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; MOV R10, RZ ; IMAD.MOV.U32 R2, RZ, RZ, 0x8 ; IMAD R3, R3, c[0x0][0x1f0], R4 ; IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; DSETP.MAX.AND P0, P1, RZ, R8, PT ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; IMAD.MOV.U32 R5, RZ, RZ, R8 ; FSEL R21, R0, R11, P0 ; SEL R10, R10, R5, P0 ; DSETP.GT.AND P0, PT, R8, RZ, PT ; IMAD.MOV.U32 R5, RZ, RZ, R12 ; @P1 LOP3.LUT R21, R11, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P1, PT, R12, RZ, PT ; FSEL R8, R8, RZ, !P0 ; FSEL R9, R9, RZ, !P0 ; IMAD.MOV.U32 R11, RZ, RZ, R21 ; DSETP.MAX.AND P0, P2, RZ, R12, PT ; DMUL R42, R10, R42 ; FSEL R11, R0, R13, P0 ; DFMA R40, R40, R8, R42 ; FSEL R8, R12, RZ, !P1 ; FSEL R9, R13.reuse, RZ, !P1 ; @P2 LOP3.LUT R11, R13, 0x80000, RZ, 0xfc, !PT ; DSETP.MAX.AND P1, P2, RZ, R16, PT ; DFMA R14, R14, R8, R40 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; IMAD.MOV.U32 R9, RZ, RZ, R11 ; SEL R8, R8, R5, P0 ; DSETP.GT.AND P0, PT, R16, RZ, PT ; IMAD.MOV.U32 R5, RZ, RZ, R17 ; DFMA R14, R8, R18, R14 ; FSEL R10, R16, RZ, !P0 ; FSEL R11, R17, RZ, !P0 ; MOV R8, RZ ; FSEL R9, R0, R5, P1 ; SEL R8, R8, R16, P1 ; DFMA R14, R38, R10, R14 ; @P2 LOP3.LUT R9, R5, 0x80000, RZ, 0xfc, !PT ; DFMA R14, R8, R30, R14 ; DMUL R6, R14, R6 ; STG.E.64 [R2.64], R6 ; EXIT ; BSYNC B0 ; IMAD.WIDE R10, R13, R10, c[0x0][0x160] ; STG.E.64 [R10.64], RZ ; EXIT ; FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R65, RZ, RZ, R7 ; LOP3.LUT R11, R9, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R58, RZ, RZ, R8.reuse ; BSSY B1, 0x13c00 ; IMAD.MOV.U32 R59, RZ, RZ, R9 ; FSETP.GEU.AND P2, PT, |R65|, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R60, RZ, RZ, R8 ; LOP3.LUT R61, R11, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R64, RZ, RZ, R10 ; LOP3.LUT R7, R65, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; LOP3.LUT R10, R9, 0x7ff00000, RZ, 0xc0, !PT ; @!P0 DMUL R60, R58, 8.98846567431157953865e+307 ; IMAD.MOV.U32 R62, RZ, RZ, R64 ; ISETP.GE.U32.AND P1, PT, R7, R10, PT ; MUFU.RCP64H R13, R61 ; @!P2 LOP3.LUT R8, R59, 0x7ff00000, RZ, 0xc0, !PT ; @!P2 IMAD.MOV.U32 R68, RZ, RZ, RZ ; @!P0 LOP3.LUT R10, R61, 0x7ff00000, RZ, 0xc0, !PT ; @!P2 ISETP.GE.U32.AND P3, PT, R7, R8, PT ; MOV R8, 0x1ca00000 ; @!P2 SEL R11, R8.reuse, 0x63400000, !P3 ; SEL R9, R8, 0x63400000, !P1 ; @!P2 LOP3.LUT R11, R11, 0x80000000, R65.reuse, 0xf8, !PT ; DFMA R66, R12, -R60, 1 ; LOP3.LUT R63, R9, 0x800fffff, R65, 0xf8, !PT ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; @!P2 LOP3.LUT R69, R11, 0x100000, RZ, 0xfc, !PT ; DFMA R66, R66, R66, R66 ; @!P2 DFMA R62, R62, 2, -R68 ; DFMA R66, R12, R66, R12 ; @!P2 LOP3.LUT R9, R63, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R12, R66, -R60, 1 ; IADD3 R11, R9, -0x1, RZ ; DFMA R66, R66, R12, R66 ; ISETP.GT.U32.AND P0, PT, R11, 0x7feffffe, PT ; IADD3 R12, R10, -0x1, RZ ; DMUL R68, R66, R62 ; ISETP.GT.U32.OR P0, PT, R12, 0x7feffffe, P0 ; DFMA R70, R68, -R60, R62 ; DFMA R12, R66, R70, R68 ; @P0 BRA 0x13a70 ; LOP3.LUT R10, R59, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R7.reuse, R10, PT ; IMAD.IADD R9, R7, 0x1, -R10 ; SEL R7, R8, 0x63400000, !P0 ; IMNMX R9, R9, -0x46a00000, !PT ; IMNMX R8, R9, 0x46a00000, PT ; IMAD.IADD R7, R8, 0x1, -R7 ; MOV R8, RZ ; IADD3 R9, R7, 0x7fe00000, RZ ; DMUL R66, R12, R8 ; FSETP.GTU.AND P0, PT, |R67|, 1.469367938527859385e-39, PT ; @P0 BRA 0x13bf0 ; DFMA R60, R12, -R60, R62 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R61.reuse, RZ, PT ; LOP3.LUT R8, R61, 0x80000000, R59, 0x48, !PT ; LOP3.LUT R11, R8, R9, RZ, 0xfc, !PT ; @!P0 BRA 0x13bf0 ; IMAD.MOV R59, RZ, RZ, -R7 ; DMUL.RP R10, R12, R10 ; IMAD.MOV.U32 R58, RZ, RZ, RZ ; IADD3 R7, -R7, -0x43300000, RZ ; DFMA R58, R66, -R58, R12 ; LOP3.LUT R8, R11, R8, RZ, 0x3c, !PT ; FSETP.NEU.AND P0, PT, |R59|, R7, PT ; FSEL R10, R10, R66, !P0 ; FSEL R11, R8, R67, !P0 ; IMAD.MOV.U32 R66, RZ, RZ, R10 ; IMAD.MOV.U32 R67, RZ, RZ, R11 ; BRA 0x13bf0 ; DSETP.NAN.AND P0, PT, R64, R64, PT ; @P0 BRA 0x13bc0 ; DSETP.NAN.AND P0, PT, R58, R58, PT ; @P0 BRA 0x13b80 ; ISETP.NE.AND P0, PT, R9, R10, PT ; IMAD.MOV.U32 R66, RZ, RZ, 0x0 ; MOV R67, 0xfff80000 ; @!P0 BRA 0x13bf0 ; ISETP.NE.AND P0, PT, R9, 0x7ff00000, PT ; LOP3.LUT R7, R65, 0x80000000, R59, 0x48, !PT ; ISETP.EQ.OR P0, PT, R10, RZ, !P0 ; @P0 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R66, RZ, RZ, RZ ; @!P0 IMAD.MOV.U32 R67, RZ, RZ, R7 ; @P0 IMAD.MOV.U32 R66, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R67, RZ, RZ, R8 ; BRA 0x13bf0 ; LOP3.LUT R7, R59, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R66, RZ, RZ, R58 ; IMAD.MOV.U32 R67, RZ, RZ, R7 ; BRA 0x13bf0 ; LOP3.LUT R7, R65, 0x80000, RZ, 0xfc, !PT ; MOV R66, R64 ; IMAD.MOV.U32 R67, RZ, RZ, R7 ; BSYNC B1 ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; IMAD.MOV.U32 R8, RZ, RZ, R66 ; IMAD.MOV.U32 R7, RZ, RZ, R67 ; RET.REL.NODEC R10 0x0 ; SHF.R.U32.HI R9, RZ, 0x14, R11 ; IMAD.MOV.U32 R12, RZ, RZ, R8 ; MOV R13, R11 ; IMAD.MOV.U32 R58, RZ, RZ, RZ ; ISETP.NE.AND P0, PT, R9, RZ, PT ; @!P0 DMUL R12, R12, 1.80143985094819840000e+16 ; @!P0 IMAD.MOV.U32 R11, RZ, RZ, R13 ; @!P0 LEA.HI R9, R13, 0xffffffca, RZ, 0xc ; @!P0 IMAD.MOV.U32 R8, RZ, RZ, R12 ; LOP3.LUT R11, R11, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R66, RZ, RZ, R8 ; LOP3.LUT R11, R11, 0x3ff00000, RZ, 0xfc, !PT ; ISETP.GE.U32.AND P1, PT, R11, 0x3ff6a09f, PT ; IMAD.MOV.U32 R67, RZ, RZ, R11 ; @P1 IADD3 R8, R67, -0x100000, RZ ; @P1 IMAD.MOV.U32 R67, RZ, RZ, R8 ; IADD3 R8, R9.reuse, -0x3ff, RZ ; @P1 IADD3 R8, R9, -0x3fe, RZ ; IMAD.MOV.U32 R9, RZ, RZ, 0x43300000 ; DADD R60, R66, 1 ; LOP3.LUT R8, R8, 0x80000000, RZ, 0x3c, !PT ; DADD R66, R66, -1 ; MUFU.RCP64H R59, R61 ; DADD R12, R8, c[0x2][0x98] ; DFMA R64, -R60, R58, 1 ; DFMA R64, R64, R64, R64 ; DFMA R64, R58, R64, R58 ; MOV R58, 0x7d2cafe2 ; IMAD.MOV.U32 R59, RZ, RZ, 0x3eb0f5ff ; DMUL R72, R64, R66 ; DFMA R72, R64, R66, R72 ; DMUL R62, R72, R72 ; DFMA R58, R62, R58, c[0x2][0x58] ; DFMA R60, R62, R58, c[0x2][0x60] ; DADD R58, R66, -R72 ; DFMA R60, R62, R60, c[0x2][0x68] ; DADD R58, R58, R58 ; DFMA R60, R62, R60, c[0x2][0x70] ; DFMA R58, R66, -R72, R58 ; DFMA R60, R62, R60, c[0x2][0x78] ; DMUL R58, R64, R58 ; DFMA R60, R62, R60, c[0x2][0x80] ; DMUL R66, R72, R72 ; IADD3 R65, R59, 0x100000, RZ ; IMAD.MOV.U32 R64, RZ, RZ, R58 ; DFMA R70, R62, R60, c[0x2][0x88] ; DADD R68, -R70, c[0x2][0x88] ; DFMA R68, R62, R60, R68 ; DFMA R60, R72, R72, -R66 ; DMUL R62, R72, R66 ; DFMA R64, R72, R64, R60 ; DFMA R60, R72, R66, -R62 ; DFMA R60, R58, R66, R60 ; DADD R66, RZ, R68 ; DFMA R64, R72, R64, R60 ; DADD R66, R66, c[0x2][0x90] ; DADD R60, R70, R66 ; DADD R70, R70, -R60 ; DMUL R68, R60, R62 ; DADD R70, R66, R70 ; DFMA R66, R60, R62, -R68 ; DFMA R64, R60, R64, R66 ; DFMA R70, R70, R62, R64 ; DADD R62, R68, R70 ; DADD R60, R72, R62 ; DADD R68, R68, -R62 ; DADD R72, R72, -R60 ; DADD R68, R70, R68 ; DADD R72, R62, R72 ; DADD R62, R68, R72 ; DADD R62, R58, R62 ; DADD R58, R60, R62 ; DFMA R8, R12, c[0x2][0xa0], R58 ; DADD R64, R60, -R58 ; DFMA R60, -R12, c[0x2][0xa0], R8 ; DADD R64, R62, R64 ; DADD R60, -R58, R60 ; IMAD.MOV.U32 R59, RZ, RZ, R7 ; IMAD.MOV.U32 R58, RZ, RZ, R6 ; DADD R64, R64, -R60 ; IMAD.SHL.U32 R6, R59.reuse, 0x2, RZ ; LOP3.LUT R7, R59, 0xff0fffff, RZ, 0xc0, !PT ; DFMA R64, R12, c[0x2][0xa8], R64 ; ISETP.GT.U32.AND P0, PT, R6, -0x2000001, PT ; MOV R6, R58 ; SEL R7, R7, R59, P0 ; DADD R12, R8, R64 ; DADD R8, R8, -R12 ; DMUL R58, R12, R6 ; DADD R8, R64, R8 ; IMAD.MOV.U32 R64, RZ, RZ, 0x652b82fe ; DFMA R12, R12, R6, -R58 ; IMAD.MOV.U32 R65, RZ, RZ, 0x3ff71547 ; DFMA R12, R8, R6, R12 ; IMAD.MOV.U32 R6, RZ, RZ, 0x69ce2bdf ; IMAD.MOV.U32 R7, RZ, RZ, 0x3e5ade15 ; DADD R8, R58, R12 ; DFMA R64, R8, R64, 6.75539944105574400000e+15 ; FSETP.GEU.AND P0, PT, |R9|, 4.1917929649353027344, PT ; DADD R62, R64, -6.75539944105574400000e+15 ; DFMA R60, R62, c[0x2][0xb0], R8 ; DFMA R60, R62, c[0x2][0xb8], R60 ; DFMA R6, R60, R6, c[0x2][0xc0] ; DFMA R62, R60, R6, c[0x2][0xc8] ; DFMA R62, R60, R62, c[0x2][0xd0] ; DFMA R62, R60, R62, c[0x2][0xd8] ; DFMA R62, R60, R62, c[0x2][0xe0] ; DFMA R62, R60, R62, c[0x2][0xe8] ; DFMA R62, R60, R62, c[0x2][0xf0] ; DFMA R62, R60, R62, c[0x2][0xf8] ; DFMA R62, R60, R62, c[0x2][0x100] ; DFMA R62, R60, R62, 1 ; DFMA R62, R60, R62, 1 ; IMAD R61, R64, 0x100000, R63 ; IMAD.MOV.U32 R60, RZ, RZ, R62 ; @!P0 BRA 0x14450 ; FSETP.GEU.AND P1, PT, |R9|, 4.2275390625, PT ; DADD R60, R8, +INF ; DSETP.GEU.AND P0, PT, R8, RZ, PT ; FSEL R60, R60, RZ, P0 ; @!P1 LEA.HI R6, R64, R64, RZ, 0x1 ; FSEL R61, R61, RZ, P0 ; @!P1 SHF.R.S32.HI R6, RZ, 0x1, R6 ; @!P1 LEA R63, R6, R63, 0x14 ; @!P1 IMAD.IADD R6, R64, 0x1, -R6 ; @!P1 LEA R7, R6, 0x3ff00000, 0x14 ; @!P1 IMAD.MOV.U32 R6, RZ, RZ, RZ ; @!P1 DMUL R60, R62, R6 ; LOP3.LUT R6, R61, 0x7fffffff, RZ, 0xc0, !PT ; DADD R8, R58, -R8 ; IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; ISETP.NE.AND P0, PT, R6, 0x7ff00000, PT ; DADD R8, R12, R8 ; ISETP.EQ.AND P0, PT, R60, RZ, !P0 ; @!P0 DFMA R60, R8, R60, R60 ; IMAD.MOV.U32 R6, RZ, RZ, R60 ; IMAD.MOV.U32 R7, RZ, RZ, R61 ; RET.REL.NODEC R10 0x0 ; BRA 0x144f0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.Y ; S2R R5, SR_TID.Y ; S2R R2, SR_CTAID.X ; S2R R3, SR_TID.X ; S2R R8, SR_CTAID.Z ; S2R R7, SR_TID.Z ; IMAD R0, R0, c[0x0][0x4], R5 ; ISETP.GE.AND P0, PT, R0, c[0x0][0x1cc], PT ; IMAD R2, R2, c[0x0][0x0], R3 ; ISETP.GE.OR P0, PT, R2, c[0x0][0x1c8], P0 ; IMAD R8, R8, c[0x0][0x8], R7 ; ISETP.GE.OR P0, PT, R8, c[0x0][0x1d0], P0 ; @P0 EXIT ; I2F.F64 R2, R2 ; ULDC.64 UR6, c[0x0][0x1c8] ; IADD3 R6, R0.reuse, 0x1, RZ ; ULDC UR5, c[0x0][0x1d0] ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; UIADD3 UR4, UR6, -0x1, URZ ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; UIADD3 UR5, UR5, -0x1, URZ ; I2F.F64 R8, R8 ; IADD3 R14, R0.reuse, 0x2, RZ ; IADD3 R16, R0, -0x1, RZ ; I2F.F64 R4, R0 ; DSETP.MAX.AND P1, P2, RZ, R2, PT ; IMAD.MOV.U32 R13, RZ, RZ, R2 ; IMAD.MOV.U32 R11, RZ, RZ, R3 ; SEL R12, R12, R13, P1 ; DSETP.MAX.AND P4, P3, RZ, R8, PT ; I2F.F64 R2, UR4 ; IMAD.MOV.U32 R17, RZ, RZ, R8 ; UIADD3 UR4, UR7, -0x1, URZ ; IMAD.MOV.U32 R18, RZ, RZ, R9 ; ULDC.64 UR6, c[0x0][0x118] ; SEL R10, R10, R17, P4 ; DSETP.MAX.AND P5, P0, RZ, R4, PT ; IMAD.MOV.U32 R15, RZ, RZ, R4 ; I2F.F64 R8, UR5 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; FSEL R13, R4.reuse, R11, P1 ; I2F.F64 R6, R6 ; @P2 LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R11, RZ, RZ, RZ ; SEL R4, R4, R15, P5 ; FSEL R11, R11, R18, P4 ; I2F.F64 R14, R14 ; @P3 LOP3.LUT R11, R18, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P3, PT, R12, R2, PT ; IADD3 R18, R0, -0x2, RZ ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; DSETP.GT.AND P6, PT, R10, R8, PT ; IMAD.MOV.U32 R21, RZ, RZ, R6 ; FSEL R3, R3, R13, P3 ; IMAD.MOV.U32 R23, RZ, RZ, R7 ; DSETP.MAX.AND P1, P2, RZ, R6, PT ; I2F.F64 R18, R18 ; FSEL R13, R9, R11, P6 ; FSEL R9, R0, R5, P5 ; IMAD.MOV.U32 R27, RZ, RZ, R15 ; @P0 LOP3.LUT R9, R5, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R25, RZ, RZ, R14 ; FSEL R2, R2, R12, P3 ; I2F.F64 R6, UR4 ; DSETP.MAX.AND P3, P4, RZ, R14, PT ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; FSEL R15, R0, R23, P1 ; @P2 LOP3.LUT R15, R23, 0x80000, RZ, 0xfc, !PT ; FSEL R12, R8, R10, P6 ; I2F.F64 R16, R16 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; IMAD.MOV.U32 R23, RZ, RZ, R19 ; IMAD.MOV.U32 R9, RZ, RZ, R15 ; SEL R8, R8, R21, P1 ; DSETP.MAX.AND P0, P1, RZ, R18, PT ; F2I.F64.TRUNC R2, R2 ; FSEL R19, R0, R27, P3 ; IMAD.MOV.U32 R21, RZ, RZ, R18 ; DSETP.GT.AND P2, PT, R4, R6, PT ; @P4 LOP3.LUT R19, R27, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R27, RZ, RZ, 0x8 ; DSETP.MAX.AND P5, P6, RZ, R16, PT ; FSEL R10, R6, R4, P2 ; IMAD.MOV.U32 R14, RZ, RZ, R17 ; FSEL R11, R7, R5, P2 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; F2I.F64.TRUNC R17, R12 ; IMAD.MOV.U32 R5, RZ, RZ, R19 ; DSETP.GT.AND P2, PT, R8, R6, PT ; IMAD.MOV.U32 R3, RZ, RZ, RZ ; SEL R4, R4, R25, P3 ; IMAD.MOV.U32 R29, RZ, RZ, R16 ; F2I.F64.TRUNC R0, R10 ; FSEL R3, R3, R14, P5 ; DSETP.GT.AND P3, PT, R4, R6, PT ; @P6 LOP3.LUT R3, R14, 0x80000, RZ, 0xfc, !PT ; FSEL R12, R6.reuse, R8, P2 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; FSEL R13, R7.reuse, R9, P2 ; IMAD.MOV.U32 R9, RZ, RZ, R3 ; FSEL R14, R6, R4, P3 ; IMAD.MOV.U32 R4, RZ, RZ, RZ ; FSEL R15, R7, R5, P3 ; F2I.F64.TRUNC R12, R12 ; SEL R8, R8, R29, P5 ; FSEL R5, R4.reuse, R23, P0 ; IMAD R33, R17, c[0x0][0x1cc], R0 ; @P1 LOP3.LUT R5, R23, 0x80000, RZ, 0xfc, !PT ; SEL R4, R4, R21, P0 ; IMAD R32, R33, c[0x0][0x1c8], R2 ; DSETP.GT.AND P2, PT, R8, R6.reuse, PT ; F2I.F64.TRUNC R14, R14 ; IMAD.WIDE R22, R32, R27, c[0x0][0x190] ; DSETP.GT.AND P0, PT, R4, R6, PT ; FSEL R8, R6.reuse, R8, P2 ; IMAD R3, R17, c[0x0][0x1cc], R12 ; FSEL R9, R7, R9, P2 ; LDG.E.64 R22, [R22.64] ; FSEL R4, R6, R4, P0 ; IMAD R3, R3, c[0x0][0x1c8], R2 ; FSEL R5, R7, R5, P0 ; F2I.F64.TRUNC R8, R8 ; IMAD.WIDE R18, R32, R27, c[0x0][0x198] ; IMAD R7, R17, c[0x0][0x1cc], R14 ; IMAD.WIDE R20, R32, R27, c[0x0][0x1c0] ; F2I.F64.TRUNC R4, R4 ; LDG.E.64 R18, [R18.64] ; IMAD R7, R7, c[0x0][0x1c8], R2 ; IMAD R11, R17, c[0x0][0x1cc], R8 ; IMAD R11, R11, c[0x0][0x1c8], R2 ; IMAD R17, R17, c[0x0][0x1cc], R4 ; IMAD R14, R17, c[0x0][0x1c8], R2 ; IMAD.WIDE R12, R11, R27.reuse, c[0x0][0x1c0] ; LDG.E.64 R16, [R20.64] ; IMAD.WIDE R14, R14, R27.reuse, c[0x0][0x1c0] ; LDG.E.64 R12, [R12.64] ; IMAD.WIDE R10, R3, R27, c[0x0][0x1c0] ; LDG.E.64 R14, [R14.64] ; IMAD.WIDE R30, R7, R27.reuse, c[0x0][0x1c0] ; LDG.E.64 R10, [R10.64] ; IMAD.WIDE R24, R32.reuse, R27.reuse, c[0x0][0x160] ; LDG.E.64 R30, [R30.64] ; IMAD.WIDE R26, R32, R27, c[0x0][0x168] ; STG.E.64 [R24.64], RZ ; STG.E.64 [R26.64], RZ ; BSSY B1, 0x1730 ; SHF.R.S32.HI R35, RZ, 0x1f, R32 ; DSETP.GEU.AND P0, PT, R22, c[0x0][0x1d8], PT ; @P0 BRA 0x1720 ; DADD R8, -RZ, |c[0x0][0x1d8]| ; BSSY B0, 0x9d0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R4, 0x9c0 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1d8] ; MOV R9, c[0x0][0x1dc] ; DSETP.NEU.AND P0, PT, RZ, c[0x0][0x1d8], PT ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R4, R8, 2 ; @!P0 CS2R R6, SRZ ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R4, 0x7ff00000, PT ; @P1 BRA 0xb10 ; DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; @P0 BRA 0xb00 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1dc] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1d8], PT ; LOP3.LUT R3, R3, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0xb10 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xb10 ; DADD R6, R8, 2 ; DSETP.NEU.AND P0, PT, R8, 1, PT ; IMAD.MOV.U32 R36, RZ, RZ, 0x1 ; BSSY B2, 0xd10 ; ISETP.LE.AND P4, PT, RZ, c[0x0][0x1dc], PT ; DADD R4, -R12, R16 ; FSEL R7, R7, 1.875, P0 ; FSEL R6, R6, RZ, P0 ; MUFU.RCP64H R37, R7 ; DMUL R28, R4, -2.5 ; DADD R4, -R12, R30 ; DFMA R8, -R6, R36, 1 ; DFMA R38, R8, R8, R8 ; DADD R8, -R12, R10 ; DFMA R38, R36, R38, R36 ; DFMA R8, R8, 2, R28 ; DFMA R28, -R6, R38, 1 ; DFMA R4, R4, -0.5, R8 ; DFMA R28, R38, R28, R38 ; DMUL R8, R4, R28 ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; DFMA R36, -R6, R8, R4 ; DFMA R28, R28, R36, R8 ; FFMA R3, RZ, R7, R29 ; FSETP.GT.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xd00 ; IMAD.MOV.U32 R8, RZ, RZ, R4 ; MOV R4, 0xce0 ; IMAD.MOV.U32 R3, RZ, RZ, R7 ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R28, RZ, RZ, R6 ; IMAD.MOV.U32 R29, RZ, RZ, R3 ; BSYNC B2 ; DADD R8, -RZ, |c[0x0][0x1d8]| ; BSSY B0, 0xd80 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R4, 0xd70 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40080000 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; IMAD.MOV.U32 R40, RZ, RZ, c[0x0][0x1d8] ; DADD R4, -R12, R10 ; IMAD.MOV.U32 R41, RZ, RZ, c[0x0][0x1dc] ; DSETP.NEU.AND P1, PT, RZ, c[0x0][0x1d8], PT ; DADD R36, R40, 3 ; DADD R8, -R12, R16 ; DMUL R38, R4, 0.5 ; LOP3.LUT R7, R37, 0x7ff00000, RZ, 0xc0, !PT ; @!P1 IMAD.MOV.U32 R6, RZ, RZ, RZ ; DADD R50, -R12, R30 ; ISETP.NE.AND P0, PT, R7, 0x7ff00000, PT ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; DFMA R36, R8, 0.5, -R38 ; @!P4 LOP3.LUT R3, R7, 0x80000000, RZ, 0x3c, !PT ; DFMA R36, R50, c[0x2][0x0], R36 ; @!P4 IMAD.MOV.U32 R7, RZ, RZ, R3 ; @!P1 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x1dc] ; @P0 BRA 0xf60 ; DSETP.GTU.AND P0, PT, |R40|, +INF , PT ; @P0 BRA 0xf50 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1dc] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1d8], PT ; LOP3.LUT R3, R3, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0xf60 ; IMAD.MOV.U32 R7, RZ, RZ, -0x100000 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; SEL R7, R7, 0x7ff00000, !P4 ; BRA 0xf60 ; DADD R6, R40, 3 ; DSETP.NEU.AND P0, PT, R40, 1, PT ; IMAD.MOV.U32 R30, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R37|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x1130 ; DMUL R4, R4, -1.5 ; FSEL R7, R7, 1.875, P0 ; FSEL R6, R6, RZ, P0 ; MUFU.RCP64H R31, R7 ; DFMA R4, R8, 3, R4 ; DFMA R50, R50, c[0x2][0x8], R4 ; DFMA R38, -R6, R30, 1 ; DFMA R38, R38, R38, R38 ; DFMA R38, R30, R38, R30 ; DFMA R30, -R6, R38, 1 ; DFMA R30, R38, R30, R38 ; DMUL R38, R30, R36 ; DFMA R40, -R6, R38, R36 ; DFMA R30, R30, R40, R38 ; FFMA R3, RZ, R7, R31 ; FSETP.GT.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1120 ; IMAD.MOV.U32 R8, RZ, RZ, R36 ; MOV R4, 0x1100 ; IMAD.MOV.U32 R5, RZ, RZ, R37 ; IMAD.MOV.U32 R3, RZ, RZ, R7 ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R30, RZ, RZ, R6 ; IMAD.MOV.U32 R31, RZ, RZ, R3 ; BSYNC B2 ; MUFU.RCP64H R5, c[0x0][0x1dc] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1d8] ; FSETP.GEU.AND P1, PT, |R51|, 6.5827683646048100446e-37, PT ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1dc] ; BSSY B2, 0x12d0 ; IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; DADD R52, R22, c[0x0][0x1d8] ; DFMA R6, R4, -R8, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R4, R6, R4 ; DFMA R4, R6, -R8, 1 ; DFMA R4, R6, R4, R6 ; DMUL R6, R4, R50 ; DFMA R8, R6, -c[0x0][0x1d8], R50 ; DFMA R6, R4, R8, R6 ; FFMA R3, RZ, c[0x0][0x1dc], R7 ; FSETP.GT.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x12c0 ; MOV R8, R50 ; IMAD.MOV.U32 R5, RZ, RZ, R51 ; MOV R4, 0x12b0 ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x1d8] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1dc] ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; BSYNC B2 ; DADD R8, -RZ, |R52| ; BSSY B0, 0x1350 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40000000 ; MOV R4, 0x1340 ; DFMA R50, R52, R6, R12 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; DADD R36, R22, c[0x0][0x1d8] ; BSSY B0, 0x1490 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R4, R36, 2 ; DSETP.NEU.AND P0, PT, R36, RZ, PT ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R4, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x1480 ; DSETP.GTU.AND P0, PT, |R36|, +INF , PT ; @P0 BRA 0x1470 ; ISETP.NE.AND P0, PT, R36, RZ, PT ; LOP3.LUT R3, R37, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0x1480 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x1480 ; DADD R6, R36, 2 ; BSYNC B0 ; DSETP.NEU.AND P0, PT, R36, 1, PT ; BSSY B0, 0x1550 ; ISETP.GE.AND P2, PT, R37, RZ, PT ; IMAD.MOV.U32 R3, RZ, RZ, 0x40080000 ; DADD R8, -RZ, |R36| ; FSEL R4, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R5, R7, 1.875, P0 ; DFMA R50, R28, R4, R50 ; MOV R4, 0x1540 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; DADD R22, R22, c[0x0][0x1d8] ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; BSSY B0, 0x16d0 ; DADD R4, R22, 3 ; @!P2 LOP3.LUT R3, R7, 0x80000000, RZ, 0x3c, !PT ; DSETP.NEU.AND P1, PT, R22, RZ, PT ; @!P2 IMAD.MOV.U32 R7, RZ, RZ, R3 ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @!P1 IMAD.MOV.U32 R6, RZ, RZ, RZ ; @!P1 IMAD.MOV.U32 R7, RZ, RZ, R23 ; @P0 BRA 0x16c0 ; DSETP.GTU.AND P0, PT, |R22|, +INF , PT ; @P0 BRA 0x16b0 ; ISETP.NE.AND P0, PT, R22, RZ, PT ; LOP3.LUT R3, R23, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0x16c0 ; IMAD.MOV.U32 R7, RZ, RZ, -0x100000 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; SEL R7, R7, 0x7ff00000, !P2 ; BRA 0x16c0 ; DADD R6, R22, 3 ; BSYNC B0 ; DSETP.NEU.AND P0, PT, R22, 1, PT ; FSEL R4, R6, RZ, P0 ; FSEL R5, R7, 1.875, P0 ; DFMA R50, R30, R4, R50 ; STG.E.64 [R24.64], R50 ; BSYNC B1 ; DSETP.GEU.AND P0, PT, R18, c[0x0][0x1d8], PT ; BSSY B1, 0x24d0 ; @P0 BRA 0x24c0 ; DADD R8, -RZ, |c[0x0][0x1d8]| ; BSSY B0, 0x1800 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R4, 0x17f0 ; DADD R28, -R14, R12 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40000000 ; DADD R24, -R14, R16 ; DADD R22, -R14, R10 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1d8] ; DSETP.NEU.AND P6, PT, RZ, c[0x0][0x1d8], PT ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1dc] ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R4, R8, 2 ; @!P6 CS2R R6, SRZ ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @P0 BRA 0x1940 ; DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; @P0 BRA 0x1930 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1dc] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1d8], PT ; LOP3.LUT R3, R3, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0x1940 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x1940 ; DADD R6, R8, 2 ; DSETP.NEU.AND P4, PT, R8, 1, PT ; IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; BSSY B2, 0x1b10 ; ISETP.LE.AND P5, PT, RZ, c[0x0][0x1dc], PT ; DMUL R28, R28, -2.5 ; FSEL R7, R7, 1.875, P4 ; FSEL R6, R6, RZ, P4 ; MUFU.RCP64H R5, R7 ; DFMA R24, R24, 2, R28 ; DFMA R8, -R6, R4, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R4, R8, R4 ; DFMA R4, R22, -0.5, R24 ; DFMA R28, -R6, R8, 1 ; DFMA R28, R8, R28, R8 ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; DMUL R22, R4, R28 ; DFMA R8, -R6, R22, R4 ; DFMA R22, R28, R8, R22 ; FFMA R3, RZ, R7, R23 ; FSETP.GT.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1b00 ; IMAD.MOV.U32 R8, RZ, RZ, R4 ; MOV R4, 0x1ae0 ; IMAD.MOV.U32 R3, RZ, RZ, R7 ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R22, RZ, RZ, R6 ; MOV R23, R3 ; BSYNC B2 ; DADD R8, -RZ, |c[0x0][0x1d8]| ; BSSY B0, 0x1b80 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R4, 0x1b70 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40080000 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x1d8] ; DADD R16, -R14.reuse, R16 ; IMAD.MOV.U32 R25, RZ, RZ, c[0x0][0x1dc] ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R12, -R14, R12 ; @!P6 IMAD.MOV.U32 R6, RZ, RZ, RZ ; DADD R28, R24, 3 ; @!P5 LOP3.LUT R3, R7, 0x80000000, RZ, 0x3c, !PT ; DMUL R4, R16, 0.5 ; @!P5 IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R8, -R14, R10 ; @!P6 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x1dc] ; LOP3.LUT R28, R29, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R4, R12, 0.5, -R4 ; ISETP.NE.AND P0, PT, R28, 0x7ff00000, PT ; DFMA R4, R8, c[0x2][0x0], R4 ; @P0 BRA 0x1d50 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x1d40 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1dc] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1d8], PT ; LOP3.LUT R3, R3, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0x1d50 ; IMAD.MOV.U32 R3, RZ, RZ, -0x100000 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; SEL R7, R3, 0x7ff00000, !P5 ; BRA 0x1d50 ; DADD R6, R24, 3 ; FSEL R7, R7, 1.875, P4 ; IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; FSEL R6, R6, RZ, P4 ; DMUL R16, R16, -1.5 ; MUFU.RCP64H R11, R7 ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x1f00 ; DFMA R12, R12, 3, R16 ; DFMA R12, R8, c[0x2][0x8], R12 ; DFMA R24, -R6, R10, 1 ; DFMA R24, R24, R24, R24 ; DFMA R24, R10, R24, R10 ; DFMA R10, -R6, R24, 1 ; DFMA R10, R24, R10, R24 ; DMUL R24, R10, R4 ; DFMA R28, -R6, R24, R4 ; DFMA R10, R10, R28, R24 ; FFMA R3, RZ, R7, R11 ; FSETP.GT.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1ef0 ; IMAD.MOV.U32 R8, RZ, RZ, R4 ; MOV R4, 0x1ed0 ; IMAD.MOV.U32 R3, RZ, RZ, R7 ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; IMAD.MOV.U32 R11, RZ, RZ, R3 ; BSYNC B2 ; MUFU.RCP64H R5, c[0x0][0x1dc] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1d8] ; FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1dc] ; BSSY B2, 0x20b0 ; IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; DFMA R6, R4, -R8, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R4, R6, R4 ; DFMA R4, R6, -R8, 1 ; DFMA R16, R6, R4, R6 ; DMUL R4, R16, R12 ; DFMA R6, R4, -c[0x0][0x1d8], R12 ; DFMA R6, R16, R6, R4 ; DADD R4, R8, c[0x0][0x1d8] ; FFMA R3, RZ, c[0x0][0x1dc], R7 ; DADD R18, -R18, R4 ; FSETP.GT.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x20a0 ; IMAD.MOV.U32 R8, RZ, RZ, R12 ; MOV R4, 0x2090 ; IMAD.MOV.U32 R5, RZ, RZ, R13 ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x1d8] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1dc] ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; BSYNC B2 ; DADD R8, -RZ, |R18| ; BSSY B0, 0x2130 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40000000 ; MOV R4, 0x2120 ; DFMA R14, R18, R6, R14 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; DADD R4, R18.reuse, 2 ; BSSY B0, 0x2270 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; ISETP.GE.AND P3, PT, R19, RZ, PT ; DSETP.NEU.AND P2, PT, R18, RZ, PT ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @!P2 CS2R R6, SRZ ; @P0 BRA 0x2260 ; DSETP.GTU.AND P0, PT, |R18|, +INF , PT ; @P0 BRA 0x2250 ; ISETP.NE.AND P0, PT, R18, RZ, PT ; LOP3.LUT R3, R19, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0x2260 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x2260 ; DADD R6, R18, 2 ; BSYNC B0 ; DSETP.NEU.AND P4, PT, R18, 1, PT ; BSSY B0, 0x2320 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40080000 ; DADD R8, -RZ, |R18| ; FSEL R4, R6, RZ, P4 ; FSEL R5, R7, 1.875, P4 ; MOV R6, RZ ; DFMA R14, R22, R4, R14 ; MOV R4, 0x2310 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; DADD R4, R18, 3 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; BSSY B0, 0x2480 ; @!P2 IMAD.MOV.U32 R6, RZ, RZ, RZ ; @!P3 LOP3.LUT R3, R7, 0x80000000, RZ, 0x3c, !PT ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; @!P3 IMAD.MOV.U32 R7, RZ, RZ, R3 ; @!P2 IMAD.MOV.U32 R7, RZ, RZ, R19 ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @P0 BRA 0x2470 ; DSETP.GTU.AND P0, PT, |R18|, +INF , PT ; @P0 BRA 0x2460 ; ISETP.NE.AND P0, PT, R18, RZ, PT ; LOP3.LUT R18, R19, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R18, 0x7ff00000, P0 ; @P0 BRA 0x2470 ; IMAD.MOV.U32 R7, RZ, RZ, -0x100000 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; SEL R7, R7, 0x7ff00000, !P3 ; BRA 0x2470 ; DADD R6, R18, 3 ; BSYNC B0 ; FSEL R4, R6, RZ, P4 ; FSEL R5, R7, 1.875, P4 ; DFMA R14, R10, R4, R14 ; STG.E.64 [R26.64], R14 ; BSYNC B1 ; S2R R3, SR_TID.X ; ULDC UR4, c[0x0][0x1c8] ; IMAD.SHL.U32 R28, R32.reuse, 0x8, RZ ; UIADD3 UR4, UR4, -0x1, URZ ; S2R R4, SR_CTAID.X ; SHF.L.U64.HI R35, R32, 0x3, R35 ; IMAD.MOV.U32 R27, RZ, RZ, 0x8 ; IMAD R3, R4, c[0x0][0x0], R3 ; IADD3 R4, R3.reuse, 0x1, RZ ; IADD3 R6, R3.reuse, 0x2, RZ ; IADD3 R8, R3.reuse, -0x1, RZ ; I2F.F64 R4, R4 ; IADD3 R10, R3, -0x2, RZ ; IMAD.MOV.U32 R3, RZ, RZ, RZ ; I2F.F64 R6, R6 ; I2F.F64 R8, R8 ; DSETP.MAX.AND P3, P4, RZ, R4, PT ; IMAD.MOV.U32 R13, RZ, RZ, R4 ; IMAD.MOV.U32 R12, RZ, RZ, R5 ; I2F.F64 R10, R10 ; DSETP.MAX.AND P5, P2, RZ, R6, PT ; IMAD.MOV.U32 R15, RZ, RZ, R6 ; IMAD.MOV.U32 R14, RZ, RZ, R7 ; FSEL R7, R3, R12, P3 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; @P4 LOP3.LUT R7, R12, 0x80000, RZ, 0xfc, !PT ; I2F.F64 R4, UR4 ; DSETP.MAX.AND P0, P1, RZ, R8, PT ; IMAD.MOV.U32 R17, RZ, RZ, R8 ; SEL R6, R6, R13, P3 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; IMAD.MOV.U32 R16, RZ, RZ, R9 ; FSEL R9, R3.reuse, R14, P5 ; SEL R8, R8, R15, P5 ; DSETP.MAX.AND P4, P5, RZ, R10, PT ; @P2 LOP3.LUT R9, R14, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R15, RZ, RZ, R10 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; DSETP.GT.AND P2, PT, R6, R4, PT ; FSEL R19, R3, R11, P4 ; SEL R10, R10, R15, P4 ; DSETP.GT.AND P3, PT, R8, R4, PT ; FSEL R12, R4, R6, P2 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; @P5 LOP3.LUT R19, R11, 0x80000, RZ, 0xfc, !PT ; FSEL R13, R5, R7, P2 ; FSEL R7, R3, R16, P0 ; IMAD.MOV.U32 R11, RZ, RZ, R19 ; SEL R6, R6, R17, P0 ; F2I.F64.TRUNC R12, R12 ; @P1 LOP3.LUT R7, R16, 0x80000, RZ, 0xfc, !PT ; FSEL R8, R4, R8, P3 ; DSETP.GT.AND P2, PT, R10, R4, PT ; FSEL R9, R5, R9, P3 ; DSETP.GT.AND P0, PT, R6, R4, PT ; F2I.F64.TRUNC R14, R8 ; FSEL R10, R4.reuse, R10, P2 ; FSEL R11, R5.reuse, R11, P2 ; FSEL R4, R4, R6, P0 ; FSEL R5, R5, R7, P0 ; F2I.F64.TRUNC R18, R10 ; IADD3 R6, P0, R28.reuse, c[0x0][0x1a0], RZ ; IMAD R16, R33, c[0x0][0x1c8], R12 ; IADD3 R8, P1, R28, c[0x0][0x1a8], RZ ; LDG.E.64 R12, [R20.64] ; IADD3.X R7, R35, c[0x0][0x1a4], RZ, P0, !PT ; F2I.F64.TRUNC R4, R4 ; IMAD R26, R33, c[0x0][0x1c8], R14 ; LDG.E.64 R10, [R6.64] ; IADD3.X R9, R35, c[0x0][0x1ac], RZ, P1, !PT ; IMAD R18, R33, c[0x0][0x1c8], R18 ; IADD3 R22, P1, R28, c[0x0][0x178], RZ ; IMAD.WIDE R16, R16, R27, c[0x0][0x1c0] ; IMAD.WIDE R30, R18, R27.reuse, c[0x0][0x1c0] ; IADD3 R18, P0, R28, c[0x0][0x170], RZ ; LDG.E.64 R16, [R16.64] ; IMAD R4, R33, c[0x0][0x1c8], R4 ; IADD3.X R19, R35.reuse, c[0x0][0x174], RZ, P0, !PT ; LDG.E.64 R32, [R8.64] ; IMAD.WIDE R14, R4, R27.reuse, c[0x0][0x1c0] ; IADD3.X R23, R35, c[0x0][0x17c], RZ, P1, !PT ; LDG.E.64 R30, [R30.64] ; IMAD.WIDE R26, R26, R27, c[0x0][0x1c0] ; LDG.E.64 R14, [R14.64] ; LDG.E.64 R26, [R26.64] ; STG.E.64 [R18.64], RZ ; STG.E.64 [R22.64], RZ ; BSSY B1, 0x3800 ; DSETP.GEU.AND P0, PT, R10, c[0x0][0x1e0], PT ; @P0 BRA 0x37f0 ; DADD R8, -RZ, |c[0x0][0x1e0]| ; BSSY B0, 0x2b10 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R4, 0x2b00 ; DADD R52, -R14, R12 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40000000 ; DADD R50, -R14, R16 ; DADD R24, -R14, R26 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1e0] ; DSETP.NEU.AND P6, PT, RZ, c[0x0][0x1e0], PT ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1e4] ; ISETP.LE.AND P5, PT, RZ, c[0x0][0x1e4], PT ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R4, R8, 2 ; @!P6 CS2R R6, SRZ ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @P0 BRA 0x2c60 ; DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; @P0 BRA 0x2c50 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1e4] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1e0], PT ; LOP3.LUT R3, R3, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0x2c60 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; MOV R7, 0x7ff00000 ; BRA 0x2c60 ; DADD R6, R8, 2 ; DSETP.NEU.AND P4, PT, R8, 1, PT ; IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; BSSY B2, 0x2e20 ; DMUL R52, R52, -2.5 ; FSEL R7, R7, 1.875, P4 ; FSEL R6, R6, RZ, P4 ; MUFU.RCP64H R5, R7 ; DFMA R50, R50, 2, R52 ; DFMA R8, -R6, R4, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R4, R8, R4 ; DFMA R4, R24, -0.5, R50 ; DFMA R36, -R6, R8, 1 ; DFMA R36, R8, R36, R8 ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; DMUL R24, R4, R36 ; DFMA R8, -R6, R24, R4 ; DFMA R24, R36, R8, R24 ; FFMA R3, RZ, R7, R25 ; FSETP.GT.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2e10 ; IMAD.MOV.U32 R8, RZ, RZ, R4 ; MOV R4, 0x2df0 ; IMAD.MOV.U32 R3, RZ, RZ, R7 ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R24, RZ, RZ, R6 ; IMAD.MOV.U32 R25, RZ, RZ, R3 ; BSYNC B2 ; DADD R8, -RZ, |c[0x0][0x1e0]| ; BSSY B0, 0x2e90 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R4, 0x2e80 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40080000 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; IMAD.MOV.U32 R36, RZ, RZ, c[0x0][0x1e0] ; DADD R4, -R14, R16 ; IMAD.MOV.U32 R37, RZ, RZ, c[0x0][0x1e4] ; DADD R8, -R14, R12 ; DADD R38, R36, 3 ; DMUL R40, R4, 0.5 ; DADD R50, -R14, R26 ; LOP3.LUT R38, R39, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R27, RZ, RZ, R3 ; DFMA R40, R8, 0.5, -R40 ; IMAD.MOV.U32 R26, RZ, RZ, R6 ; ISETP.NE.AND P0, PT, R38, 0x7ff00000, PT ; @!P6 IMAD.MOV.U32 R26, RZ, RZ, RZ ; @!P5 LOP3.LUT R3, R27, 0x80000000, RZ, 0x3c, !PT ; DFMA R6, R50, c[0x2][0x0], R40 ; @!P5 IMAD.MOV.U32 R27, RZ, RZ, R3 ; @!P6 IMAD.MOV.U32 R27, RZ, RZ, c[0x0][0x1e4] ; @P0 BRA 0x3070 ; DSETP.GTU.AND P0, PT, |R36|, +INF , PT ; @P0 BRA 0x3060 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1e4] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1e0], PT ; LOP3.LUT R3, R3, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0x3070 ; IMAD.MOV.U32 R27, RZ, RZ, -0x100000 ; IMAD.MOV.U32 R26, RZ, RZ, RZ ; SEL R27, R27, 0x7ff00000, !P5 ; BRA 0x3070 ; DADD R26, R36, 3 ; FSEL R37, R27, 1.875, P4 ; DMUL R4, R4, -1.5 ; FSEL R36, R26, RZ, P4 ; IMAD.MOV.U32 R26, RZ, RZ, 0x1 ; MUFU.RCP64H R27, R37 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x3240 ; DFMA R4, R8, 3, R4 ; DFMA R50, R50, c[0x2][0x8], R4 ; DFMA R38, -R36, R26, 1 ; DFMA R38, R38, R38, R38 ; DFMA R38, R26, R38, R26 ; DFMA R26, -R36, R38, 1 ; DFMA R26, R38, R26, R38 ; DMUL R38, R26, R6 ; DFMA R40, -R36, R38, R6 ; DFMA R26, R26, R40, R38 ; FFMA R3, RZ, R37, R27 ; FSETP.GT.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x3230 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R4, 0x3210 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; IMAD.MOV.U32 R6, RZ, RZ, R36 ; IMAD.MOV.U32 R3, RZ, RZ, R37 ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R26, RZ, RZ, R6 ; IMAD.MOV.U32 R27, RZ, RZ, R3 ; BSYNC B2 ; MUFU.RCP64H R5, c[0x0][0x1e4] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1e0] ; FSETP.GEU.AND P1, PT, |R51|, 6.5827683646048100446e-37, PT ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1e4] ; BSSY B2, 0x33e0 ; IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; DADD R10, R10, c[0x0][0x1e0] ; DFMA R6, R4, -R8, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R4, R6, R4 ; DFMA R4, R6, -R8, 1 ; DFMA R4, R6, R4, R6 ; DMUL R6, R4, R50 ; DFMA R8, R6, -c[0x0][0x1e0], R50 ; DFMA R6, R4, R8, R6 ; FFMA R3, RZ, c[0x0][0x1e4], R7 ; FSETP.GT.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x33d0 ; IMAD.MOV.U32 R8, RZ, RZ, R50 ; MOV R6, c[0x0][0x1e0] ; IMAD.MOV.U32 R5, RZ, RZ, R51 ; MOV R4, 0x33c0 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1e4] ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; BSYNC B2 ; DADD R8, -RZ, |R10| ; BSSY B0, 0x3460 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40000000 ; MOV R4, 0x3450 ; DFMA R50, R10, R6, R14 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; DADD R4, R10.reuse, 2 ; BSSY B0, 0x35a0 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; ISETP.GE.AND P3, PT, R11, RZ, PT ; DSETP.NEU.AND P2, PT, R10, RZ, PT ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @!P2 CS2R R6, SRZ ; @P0 BRA 0x3590 ; DSETP.GTU.AND P0, PT, |R10|, +INF , PT ; @P0 BRA 0x3580 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; LOP3.LUT R3, R11, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0x3590 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x3590 ; DADD R6, R10, 2 ; BSYNC B0 ; DSETP.NEU.AND P4, PT, R10, 1, PT ; BSSY B0, 0x3650 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40080000 ; DADD R8, -RZ, |R10| ; FSEL R4, R6, RZ, P4 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R5, R7, 1.875, P4 ; DFMA R50, R24, R4, R50 ; MOV R4, 0x3640 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; DADD R4, R10, 3 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; BSSY B0, 0x37b0 ; @!P2 IMAD.MOV.U32 R6, RZ, RZ, RZ ; @!P3 LOP3.LUT R3, R7, 0x80000000, RZ, 0x3c, !PT ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; @!P3 IMAD.MOV.U32 R7, RZ, RZ, R3 ; @!P2 IMAD.MOV.U32 R7, RZ, RZ, R11 ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @P0 BRA 0x37a0 ; DSETP.GTU.AND P0, PT, |R10|, +INF , PT ; @P0 BRA 0x3790 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; LOP3.LUT R10, R11, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R10, 0x7ff00000, P0 ; @P0 BRA 0x37a0 ; IMAD.MOV.U32 R7, RZ, RZ, -0x100000 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; SEL R7, R7, 0x7ff00000, !P3 ; BRA 0x37a0 ; DADD R6, R10, 3 ; BSYNC B0 ; FSEL R4, R6, RZ, P4 ; FSEL R5, R7, 1.875, P4 ; DFMA R50, R26, R4, R50 ; STG.E.64 [R18.64], R50 ; BSYNC B1 ; DSETP.GEU.AND P0, PT, R32, c[0x0][0x1e0], PT ; BSSY B1, 0x45a0 ; @P0 BRA 0x4590 ; DADD R8, -RZ, |c[0x0][0x1e0]| ; BSSY B0, 0x38d0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R4, 0x38c0 ; DADD R24, -R30, R14 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40000000 ; DADD R18, -R30, R12 ; DADD R10, -R30, R16 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1e0] ; DSETP.NEU.AND P6, PT, RZ, c[0x0][0x1e0], PT ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1e4] ; ISETP.LE.AND P5, PT, RZ, c[0x0][0x1e4], PT ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R4, R8, 2 ; @!P6 CS2R R6, SRZ ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @P0 BRA 0x3a20 ; DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; @P0 BRA 0x3a10 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1e4] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1e0], PT ; LOP3.LUT R3, R3, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0x3a20 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x3a20 ; DADD R6, R8, 2 ; DSETP.NEU.AND P4, PT, R8, 1, PT ; IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; BSSY B2, 0x3be0 ; DMUL R24, R24, -2.5 ; FSEL R7, R7, 1.875, P4 ; FSEL R6, R6, RZ, P4 ; MUFU.RCP64H R5, R7 ; DFMA R18, R18, 2, R24 ; DFMA R8, -R6, R4, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R4, R8, R4 ; DFMA R4, R10, -0.5, R18 ; DFMA R24, -R6, R8, 1 ; DFMA R24, R8, R24, R8 ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; DMUL R10, R4, R24 ; DFMA R8, -R6, R10, R4 ; DFMA R10, R24, R8, R10 ; FFMA R3, RZ, R7, R11 ; FSETP.GT.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x3bd0 ; IMAD.MOV.U32 R8, RZ, RZ, R4 ; MOV R4, 0x3bb0 ; IMAD.MOV.U32 R3, RZ, RZ, R7 ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; IMAD.MOV.U32 R11, RZ, RZ, R3 ; BSYNC B2 ; DADD R8, -RZ, |c[0x0][0x1e0]| ; BSSY B0, 0x3c50 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R3, 0x40080000 ; MOV R4, 0x3c40 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x1e0] ; DADD R4, -R30, R12 ; IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x1e4] ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R14, -R30, R14 ; @!P6 IMAD.MOV.U32 R6, RZ, RZ, RZ ; DADD R12, R18, 3 ; @!P5 LOP3.LUT R3, R7, 0x80000000, RZ, 0x3c, !PT ; DMUL R8, R4, 0.5 ; @!P5 IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R16, -R30, R16 ; @!P6 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x1e4] ; LOP3.LUT R12, R13, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R8, R14, 0.5, -R8 ; ISETP.NE.AND P0, PT, R12, 0x7ff00000, PT ; DFMA R8, R16, c[0x2][0x0], R8 ; @P0 BRA 0x3e20 ; DSETP.GTU.AND P0, PT, |R18|, +INF , PT ; @P0 BRA 0x3e10 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1e4] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1e0], PT ; LOP3.LUT R3, R3, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0x3e20 ; IMAD.MOV.U32 R3, RZ, RZ, -0x100000 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; SEL R7, R3, 0x7ff00000, !P5 ; BRA 0x3e20 ; DADD R6, R18, 3 ; FSEL R7, R7, 1.875, P4 ; IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; FSEL R6, R6, RZ, P4 ; DMUL R4, R4, -1.5 ; MUFU.RCP64H R13, R7 ; FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x3fd0 ; DFMA R14, R14, 3, R4 ; DFMA R14, R16, c[0x2][0x8], R14 ; DFMA R18, -R6, R12, 1 ; DFMA R18, R18, R18, R18 ; DFMA R18, R12, R18, R12 ; DFMA R12, -R6, R18, 1 ; DFMA R12, R18, R12, R18 ; DMUL R18, R12, R8 ; DFMA R24, -R6, R18, R8 ; DFMA R12, R12, R24, R18 ; FFMA R3, RZ, R7, R13 ; FSETP.GT.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x3fc0 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; MOV R4, 0x3fa0 ; IMAD.MOV.U32 R3, RZ, RZ, R7 ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R12, RZ, RZ, R6 ; IMAD.MOV.U32 R13, RZ, RZ, R3 ; BSYNC B2 ; MUFU.RCP64H R5, c[0x0][0x1e4] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1e0] ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1e4] ; BSSY B2, 0x4180 ; IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; DFMA R6, R4, -R8, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R4, R6, R4 ; DFMA R4, R6, -R8, 1 ; DFMA R16, R6, R4, R6 ; DMUL R4, R16, R14 ; DFMA R6, R4, -c[0x0][0x1e0], R14 ; DFMA R6, R16, R6, R4 ; DADD R4, R8, c[0x0][0x1e0] ; FFMA R3, RZ, c[0x0][0x1e4], R7 ; DADD R32, -R32, R4 ; FSETP.GT.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x4170 ; IMAD.MOV.U32 R8, RZ, RZ, R14 ; MOV R4, 0x4160 ; IMAD.MOV.U32 R5, RZ, RZ, R15 ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x1e0] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1e4] ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; BSYNC B2 ; DADD R8, -RZ, |R32| ; BSSY B0, 0x4200 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40000000 ; MOV R4, 0x41f0 ; DFMA R30, R32, R6, R30 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; DADD R4, R32.reuse, 2 ; BSSY B0, 0x4340 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; ISETP.GE.AND P3, PT, R33, RZ, PT ; DSETP.NEU.AND P2, PT, R32, RZ, PT ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @!P2 CS2R R6, SRZ ; @P0 BRA 0x4330 ; DSETP.GTU.AND P0, PT, |R32|, +INF , PT ; @P0 BRA 0x4320 ; ISETP.NE.AND P0, PT, R32, RZ, PT ; LOP3.LUT R3, R33, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R3, 0x7ff00000, P0 ; @P0 BRA 0x4330 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x4330 ; DADD R6, R32, 2 ; BSYNC B0 ; DSETP.NEU.AND P4, PT, R32, 1, PT ; BSSY B0, 0x43f0 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40080000 ; DADD R8, -RZ, |R32| ; FSEL R4, R6, RZ, P4 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R5, R7, 1.875, P4 ; DFMA R30, R10, R4, R30 ; MOV R4, 0x43e0 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; DADD R4, R32, 3 ; MOV R7, R3 ; BSSY B0, 0x4550 ; @!P2 IMAD.MOV.U32 R6, RZ, RZ, RZ ; @!P3 LOP3.LUT R3, R7, 0x80000000, RZ, 0x3c, !PT ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; @!P3 IMAD.MOV.U32 R7, RZ, RZ, R3 ; @!P2 IMAD.MOV.U32 R7, RZ, RZ, R33 ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @P0 BRA 0x4540 ; DSETP.GTU.AND P0, PT, |R32|, +INF , PT ; @P0 BRA 0x4530 ; ISETP.NE.AND P0, PT, R32, RZ, PT ; LOP3.LUT R32, R33, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R32, 0x7ff00000, P0 ; @P0 BRA 0x4540 ; IMAD.MOV.U32 R7, RZ, RZ, -0x100000 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; SEL R7, R7, 0x7ff00000, !P3 ; BRA 0x4540 ; DADD R6, R32, 3 ; BSYNC B0 ; FSEL R4, R6, RZ, P4 ; FSEL R5, R7, 1.875, P4 ; DFMA R30, R12, R4, R30 ; STG.E.64 [R22.64], R30 ; BSYNC B1 ; S2R R3, SR_TID.Z ; ULDC UR4, c[0x0][0x1d0] ; UIADD3 UR4, UR4, -0x1, URZ ; S2R R4, SR_CTAID.Z ; LDG.E.64 R20, [R20.64] ; IMAD R3, R4, c[0x0][0x8], R3 ; IADD3 R4, R3.reuse, 0x1, RZ ; IADD3 R6, R3.reuse, 0x2, RZ ; IADD3 R8, R3.reuse, -0x1, RZ ; I2F.F64 R4, R4 ; IADD3 R10, R3, -0x2, RZ ; IMAD.MOV.U32 R3, RZ, RZ, RZ ; I2F.F64 R6, R6 ; I2F.F64 R8, R8 ; DSETP.MAX.AND P0, P1, RZ, R4, PT ; IMAD.MOV.U32 R13, RZ, RZ, R4 ; IMAD.MOV.U32 R12, RZ, RZ, R5 ; DSETP.MAX.AND P5, P4, RZ, R6, PT ; I2F.F64 R4, UR4 ; IMAD.MOV.U32 R15, RZ, RZ, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IMAD.MOV.U32 R14, RZ, RZ, R7 ; FSEL R7, R3.reuse, R12, P0 ; DSETP.MAX.AND P2, P3, RZ, R8, PT ; I2F.F64 R10, R10 ; IMAD.MOV.U32 R17, RZ, RZ, R8 ; SEL R6, R6, R13, P0 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; @P1 LOP3.LUT R7, R12, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R16, RZ, RZ, R9 ; FSEL R9, R3, R14, P5 ; SEL R8, R8, R15, P5 ; @P4 LOP3.LUT R9, R14, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P4, PT, R6, R4, PT ; FSEL R15, R3, R16, P2 ; @P3 LOP3.LUT R15, R16, 0x80000, RZ, 0xfc, !PT ; DSETP.MAX.AND P1, P0, RZ, R10, PT ; IMAD.MOV.U32 R19, RZ, RZ, R10 ; FSEL R10, R4, R6, P4 ; IMAD.MOV.U32 R14, RZ, RZ, R11 ; DSETP.GT.AND P5, PT, R8, R4, PT ; FSEL R11, R5, R7, P4 ; CS2R R6, SRZ ; F2I.F64.TRUNC R3, R10 ; FSEL R12, R4, R8, P5 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; FSEL R13, R5, R9, P5 ; FSEL R9, R7, R14, P1 ; IMAD.MOV.U32 R7, RZ, RZ, R15 ; SEL R6, R6, R17, P2 ; SEL R8, R8, R19, P1 ; F2I.F64.TRUNC R13, R12 ; @P0 LOP3.LUT R9, R14, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R14, RZ, RZ, 0x8 ; DSETP.GT.AND P2, PT, R6, R4, PT ; IADD3 R24, P1, R28, c[0x0][0x1b8], RZ ; IMAD R3, R3, c[0x0][0x1cc], R0 ; DSETP.GT.AND P0, PT, R8, R4, PT ; IADD3.X R25, R35, c[0x0][0x1bc], RZ, P1, !PT ; FSEL R6, R4.reuse, R6, P2 ; FSEL R7, R5, R7, P2 ; FSEL R4, R4, R8, P0 ; IMAD R13, R13, c[0x0][0x1cc], R0 ; FSEL R5, R5, R9, P0 ; F2I.F64.TRUNC R7, R6 ; IADD3 R10, P0, R28, c[0x0][0x1b0], RZ ; IMAD R3, R3, c[0x0][0x1c8], R2 ; LDG.E.64 R24, [R24.64] ; IADD3.X R11, R35, c[0x0][0x1b4], RZ, P0, !PT ; F2I.F64.TRUNC R5, R4 ; LDG.E.64 R10, [R10.64] ; IMAD R9, R7, c[0x0][0x1cc], R0 ; IMAD R13, R13, c[0x0][0x1c8], R2.reuse ; IMAD R9, R9, c[0x0][0x1c8], R2 ; IMAD R15, R5, c[0x0][0x1cc], R0 ; IADD3 R12, P0, R28, c[0x0][0x180], RZ ; IMAD R15, R15, c[0x0][0x1c8], R2 ; IADD3 R28, P1, R28, c[0x0][0x188], RZ ; IMAD.WIDE R18, R9, R14, c[0x0][0x1c0] ; IMAD.WIDE R22, R15, R14, c[0x0][0x1c0] ; IMAD.WIDE R16, R3, R14.reuse, c[0x0][0x1c0] ; IADD3.X R29, R35, c[0x0][0x18c], RZ, P1, !PT ; LDG.E.64 R22, [R22.64] ; IMAD.WIDE R14, R13, R14, c[0x0][0x1c0] ; IADD3.X R13, R35, c[0x0][0x184], RZ, P0, !PT ; LDG.E.64 R18, [R18.64] ; LDG.E.64 R16, [R16.64] ; LDG.E.64 R14, [R14.64] ; STG.E.64 [R12.64], RZ ; STG.E.64 [R28.64], RZ ; BSSY B1, 0x58e0 ; DSETP.GEU.AND P0, PT, R10, c[0x0][0x1e8], PT ; @P0 BRA 0x58d0 ; DADD R8, -RZ, |c[0x0][0x1e8]| ; BSSY B0, 0x4c10 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R4, 0x4c00 ; DADD R32, -R18, R20 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40000000 ; DADD R30, -R18, R16 ; DADD R26, -R18, R14 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1e8] ; DSETP.NEU.AND P6, PT, RZ, c[0x0][0x1e8], PT ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1ec] ; ISETP.LE.AND P5, PT, RZ, c[0x0][0x1ec], PT ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R4, R8, 2 ; @!P6 CS2R R6, SRZ ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @P0 BRA 0x4d60 ; DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; @P0 BRA 0x4d50 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1ec] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1e8], PT ; LOP3.LUT R0, R0, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x4d60 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x4d60 ; DADD R6, R8, 2 ; DSETP.NEU.AND P4, PT, R8, 1, PT ; IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; BSSY B2, 0x4f20 ; DMUL R32, R32, -2.5 ; FSEL R3, R7, 1.875, P4 ; FSEL R2, R6, RZ, P4 ; MUFU.RCP64H R5, R3 ; DFMA R30, R30, 2, R32 ; DFMA R6, -R2, R4, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R4, R6, R4 ; DFMA R4, R26, -0.5, R30 ; DFMA R8, -R2, R6, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; DMUL R26, R4, R8 ; DFMA R6, -R2, R26, R4 ; DFMA R26, R8, R6, R26 ; FFMA R0, RZ, R3, R27 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x4f10 ; IMAD.MOV.U32 R8, RZ, RZ, R4 ; MOV R6, R2 ; MOV R4, 0x4ef0 ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R26, RZ, RZ, R6 ; IMAD.MOV.U32 R27, RZ, RZ, R3 ; BSYNC B2 ; DADD R8, -RZ, |c[0x0][0x1e8]| ; BSSY B0, 0x4f90 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R4, 0x4f80 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40080000 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; IMAD.MOV.U32 R36, RZ, RZ, c[0x0][0x1e8] ; DADD R4, -R18, R16 ; IMAD.MOV.U32 R37, RZ, RZ, c[0x0][0x1ec] ; IMAD.MOV.U32 R2, RZ, RZ, R6 ; DADD R8, -R18, R20 ; @!P6 IMAD.MOV.U32 R2, RZ, RZ, RZ ; DADD R32, R36, 3 ; DMUL R34, R4, 0.5 ; DADD R30, -R18, R14 ; LOP3.LUT R32, R33, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R34, R8, 0.5, -R34 ; @!P5 LOP3.LUT R15, R3, 0x80000000, RZ, 0x3c, !PT ; ISETP.NE.AND P0, PT, R32, 0x7ff00000, PT ; DFMA R6, R30, c[0x2][0x0], R34 ; @!P5 IMAD.MOV.U32 R3, RZ, RZ, R15 ; @!P6 IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1ec] ; @P0 BRA 0x5160 ; DSETP.GTU.AND P0, PT, |R36|, +INF , PT ; @P0 BRA 0x5150 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1ec] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1e8], PT ; LOP3.LUT R0, R0, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x5160 ; IMAD.MOV.U32 R3, RZ, RZ, -0x100000 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; SEL R3, R3, 0x7ff00000, !P5 ; BRA 0x5160 ; DADD R2, R36, 3 ; FSEL R3, R3, 1.875, P4 ; IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; FSEL R2, R2, RZ, P4 ; DMUL R4, R4, -1.5 ; MUFU.RCP64H R15, R3 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x5320 ; DFMA R4, R8, 3, R4 ; DFMA R30, R30, c[0x2][0x8], R4 ; DFMA R32, -R2, R14, 1 ; DFMA R32, R32, R32, R32 ; DFMA R32, R14, R32, R14 ; DFMA R14, -R2, R32, 1 ; DFMA R14, R32, R14, R32 ; DMUL R32, R14, R6 ; DFMA R34, -R2, R32, R6 ; DFMA R14, R14, R34, R32 ; FFMA R0, RZ, R3, R15 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x5310 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R4, 0x52f0 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; IMAD.MOV.U32 R6, RZ, RZ, R2 ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R14, RZ, RZ, R6 ; IMAD.MOV.U32 R15, RZ, RZ, R3 ; BSYNC B2 ; MUFU.RCP64H R3, c[0x0][0x1ec] ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x1e8] ; FSETP.GEU.AND P1, PT, |R31|, 6.5827683646048100446e-37, PT ; IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x1ec] ; BSSY B2, 0x54c0 ; IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; DADD R10, R10, c[0x0][0x1e8] ; DFMA R4, R2, -R6, 1 ; DFMA R4, R4, R4, R4 ; DFMA R4, R2, R4, R2 ; DFMA R2, R4, -R6, 1 ; DFMA R2, R4, R2, R4 ; DMUL R4, R2, R30 ; DFMA R6, R4, -c[0x0][0x1e8], R30 ; DFMA R2, R2, R6, R4 ; FFMA R0, RZ, c[0x0][0x1ec], R3 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x54b0 ; IMAD.MOV.U32 R8, RZ, RZ, R30 ; MOV R4, 0x54a0 ; IMAD.MOV.U32 R5, RZ, RZ, R31 ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x1e8] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1ec] ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R2, RZ, RZ, R6 ; BSYNC B2 ; DADD R8, -RZ, |R10| ; BSSY B0, 0x5540 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R4, 0x5530 ; DFMA R30, R10, R2, R18 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40000000 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; DADD R4, R10.reuse, 2 ; BSSY B0, 0x5680 ; MOV R7, R3 ; DSETP.NEU.AND P2, PT, R10, RZ, PT ; ISETP.GE.AND P3, PT, R11, RZ, PT ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @!P2 CS2R R6, SRZ ; @P0 BRA 0x5670 ; DSETP.GTU.AND P0, PT, |R10|, +INF , PT ; @P0 BRA 0x5660 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; LOP3.LUT R0, R11, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x5670 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x5670 ; DADD R6, R10, 2 ; BSYNC B0 ; DSETP.NEU.AND P4, PT, R10, 1, PT ; BSSY B0, 0x5730 ; MOV R4, 0x5720 ; DADD R8, -RZ, |R10| ; FSEL R2, R6, RZ, P4 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R3, R7, 1.875, P4 ; DFMA R30, R26, R2, R30 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40080000 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; DADD R4, R10, 3 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; BSSY B0, 0x5890 ; @!P2 IMAD.MOV.U32 R6, RZ, RZ, RZ ; @!P3 LOP3.LUT R3, R7, 0x80000000, RZ, 0x3c, !PT ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; @!P3 IMAD.MOV.U32 R7, RZ, RZ, R3 ; @!P2 IMAD.MOV.U32 R7, RZ, RZ, R11 ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @P0 BRA 0x5880 ; DSETP.GTU.AND P0, PT, |R10|, +INF , PT ; @P0 BRA 0x5870 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; LOP3.LUT R10, R11, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R10, 0x7ff00000, P0 ; @P0 BRA 0x5880 ; IMAD.MOV.U32 R7, RZ, RZ, -0x100000 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; SEL R7, R7, 0x7ff00000, !P3 ; BRA 0x5880 ; DADD R6, R10, 3 ; BSYNC B0 ; FSEL R2, R6, RZ, P4 ; FSEL R3, R7, 1.875, P4 ; DFMA R30, R14, R2, R30 ; STG.E.64 [R12.64], R30 ; BSYNC B1 ; DSETP.GEU.AND P0, PT, R24, c[0x0][0x1e8], PT ; @P0 EXIT ; DADD R8, -RZ, |c[0x0][0x1e8]| ; BSSY B0, 0x59a0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R4, 0x5990 ; DADD R14, -R22, R18 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40000000 ; DADD R12, -R22, R20 ; DADD R10, -R22, R16 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1e8] ; DSETP.NEU.AND P6, PT, RZ, c[0x0][0x1e8], PT ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1ec] ; ISETP.LE.AND P5, PT, RZ, c[0x0][0x1ec], PT ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R4, R8, 2 ; @!P6 CS2R R6, SRZ ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @P0 BRA 0x5af0 ; DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; @P0 BRA 0x5ae0 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1ec] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1e8], PT ; LOP3.LUT R0, R0, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x5af0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x5af0 ; DADD R6, R8, 2 ; DSETP.NEU.AND P4, PT, R8, 1, PT ; IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; BSSY B1, 0x5cb0 ; DMUL R14, R14, -2.5 ; FSEL R3, R7, 1.875, P4 ; FSEL R2, R6, RZ, P4 ; MUFU.RCP64H R5, R3 ; DFMA R12, R12, 2, R14 ; DFMA R6, -R2, R4, 1 ; DFMA R6, R6, R6, R6 ; DFMA R6, R4, R6, R4 ; DFMA R4, R10, -0.5, R12 ; DFMA R8, -R2, R6, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; DMUL R10, R4, R8 ; DFMA R6, -R2, R10, R4 ; DFMA R10, R8, R6, R10 ; FFMA R0, RZ, R3, R11 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x5ca0 ; IMAD.MOV.U32 R8, RZ, RZ, R4 ; MOV R4, 0x5c80 ; IMAD.MOV.U32 R6, RZ, RZ, R2 ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; IMAD.MOV.U32 R11, RZ, RZ, R3 ; BSYNC B1 ; DADD R8, -RZ, |c[0x0][0x1e8]| ; BSSY B0, 0x5d20 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R4, 0x5d10 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40080000 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1e8] ; DADD R20, -R22.reuse, R20 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1ec] ; @!P6 MOV R6, RZ ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R18, -R22, R18 ; DADD R12, R8, 3 ; @!P5 LOP3.LUT R3, R7, 0x80000000, RZ, 0x3c, !PT ; DMUL R4, R20, 0.5 ; @!P5 IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R14, -R22, R16 ; @!P6 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x1ec] ; LOP3.LUT R12, R13, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R4, R18, 0.5, -R4 ; ISETP.NE.AND P0, PT, R12, 0x7ff00000, PT ; DFMA R4, R14, c[0x2][0x0], R4 ; @P0 BRA 0x5ef0 ; DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; @P0 BRA 0x5ee0 ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x1ec] ; ISETP.NE.AND P0, PT, RZ, c[0x0][0x1e8], PT ; LOP3.LUT R0, R0, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x5ef0 ; IMAD.MOV.U32 R0, RZ, RZ, -0x100000 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; SEL R7, R0, 0x7ff00000, !P5 ; BRA 0x5ef0 ; DADD R6, R8, 3 ; FSEL R3, R7, 1.875, P4 ; DMUL R20, R20, -1.5 ; FSEL R2, R6, RZ, P4 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; MUFU.RCP64H R7, R3 ; FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; BSSY B1, 0x60a0 ; DFMA R20, R18, 3, R20 ; DFMA R14, R14, c[0x2][0x8], R20 ; DFMA R8, -R2, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R2, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R12, R6, R4 ; DFMA R8, -R2, R12, R4 ; DFMA R12, R6, R8, R12 ; FFMA R0, RZ, R3, R13 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x6090 ; IMAD.MOV.U32 R8, RZ, RZ, R4 ; MOV R4, 0x6070 ; IMAD.MOV.U32 R6, RZ, RZ, R2 ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R12, RZ, RZ, R6 ; IMAD.MOV.U32 R13, RZ, RZ, R3 ; BSYNC B1 ; MUFU.RCP64H R3, c[0x0][0x1ec] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1e8] ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1ec] ; BSSY B1, 0x6250 ; IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; DFMA R4, R2, -R8, 1 ; DFMA R4, R4, R4, R4 ; DFMA R4, R2, R4, R2 ; DFMA R2, R4, -R8, 1 ; DFMA R6, R4, R2, R4 ; DMUL R2, R6, R14 ; DFMA R4, R2, -c[0x0][0x1e8], R14 ; DFMA R6, R6, R4, R2 ; DADD R2, R8, c[0x0][0x1e8] ; FFMA R0, RZ, c[0x0][0x1ec], R7 ; DADD R24, -R24, R2 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x6240 ; IMAD.MOV.U32 R8, RZ, RZ, R14 ; MOV R4, 0x6230 ; IMAD.MOV.U32 R5, RZ, RZ, R15 ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x1e8] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1ec] ; CALL.REL.NOINC 0x6670 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; BSYNC B1 ; DADD R8, -RZ, |R24| ; BSSY B0, 0x62d0 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40000000 ; MOV R4, 0x62c0 ; DFMA R22, R24, R6, R22 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; DADD R4, R24.reuse, 2 ; BSSY B0, 0x6410 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; ISETP.GE.AND P3, PT, R25, RZ, PT ; DSETP.NEU.AND P2, PT, R24, RZ, PT ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @!P2 CS2R R6, SRZ ; @P0 BRA 0x6400 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x63f0 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R0, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x6400 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x6400 ; DADD R6, R24, 2 ; BSYNC B0 ; DSETP.NEU.AND P4, PT, R24, 1, PT ; BSSY B0, 0x64c0 ; MOV R4, 0x64b0 ; DADD R8, -RZ, |R24| ; FSEL R2, R6, RZ, P4 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R3, R7, 1.875, P4 ; DFMA R22, R10, R2, R22 ; IMAD.MOV.U32 R3, RZ, RZ, 0x40080000 ; CALL.REL.NOINC 0x6cd0 ; BSYNC B0 ; DADD R4, R24, 3 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; BSSY B0, 0x6620 ; @!P2 IMAD.MOV.U32 R6, RZ, RZ, RZ ; @!P3 LOP3.LUT R3, R7, 0x80000000, RZ, 0x3c, !PT ; LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; @!P3 IMAD.MOV.U32 R7, RZ, RZ, R3 ; @!P2 IMAD.MOV.U32 R7, RZ, RZ, R25 ; ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; @P0 BRA 0x6610 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x6600 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R24, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R24, 0x7ff00000, P0 ; @P0 BRA 0x6610 ; MOV R7, 0xfff00000 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; SEL R7, R7, 0x7ff00000, !P3 ; BRA 0x6610 ; DADD R6, R24, 3 ; BSYNC B0 ; FSEL R2, R6, RZ, P4 ; FSEL R3, R7, 1.875, P4 ; DFMA R22, R12, R2, R22 ; STG.E.64 [R28.64], R22 ; EXIT ; FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R43, RZ, RZ, R5 ; LOP3.LUT R7, R3, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R36, RZ, RZ, R6.reuse ; BSSY B0, 0x6c90 ; IMAD.MOV.U32 R37, RZ, RZ, R3 ; FSETP.GEU.AND P1, PT, |R43|, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R38, RZ, RZ, R6 ; LOP3.LUT R39, R7, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R42, RZ, RZ, R8 ; LOP3.LUT R5, R43, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R44, RZ, RZ, 0x1 ; LOP3.LUT R6, R3, 0x7ff00000, RZ, 0xc0, !PT ; @!P0 DMUL R38, R36, 8.98846567431157953865e+307 ; IMAD.MOV.U32 R3, RZ, RZ, 0x1ca00000 ; ISETP.GE.U32.AND P3, PT, R5, R6, PT ; IMAD.MOV.U32 R40, RZ, RZ, R42 ; MUFU.RCP64H R45, R39 ; @!P1 LOP3.LUT R8, R37, 0x7ff00000, RZ, 0xc0, !PT ; SEL R7, R3, 0x63400000, !P3 ; @!P1 ISETP.GE.U32.AND P2, PT, R5, R8, PT ; LOP3.LUT R41, R7, 0x800fffff, R43, 0xf8, !PT ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; @!P1 SEL R8, R3, 0x63400000, !P2 ; @!P0 LOP3.LUT R6, R39, 0x7ff00000, RZ, 0xc0, !PT ; @!P1 LOP3.LUT R8, R8, 0x80000000, R43, 0xf8, !PT ; DFMA R46, R44, -R38, 1 ; @!P1 LOP3.LUT R9, R8, 0x100000, RZ, 0xfc, !PT ; @!P1 IMAD.MOV.U32 R8, RZ, RZ, RZ ; DFMA R46, R46, R46, R46 ; @!P1 DFMA R40, R40, 2, -R8 ; DFMA R44, R44, R46, R44 ; DFMA R8, R44, -R38, 1 ; @!P1 LOP3.LUT R7, R41, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R44, R44, R8, R44 ; IADD3 R8, R7, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R8, 0x7feffffe, PT ; DMUL R46, R44, R40 ; IADD3 R8, R6, -0x1, RZ ; ISETP.GT.U32.OR P0, PT, R8, 0x7feffffe, P0 ; DFMA R48, R46, -R38, R40 ; DFMA R8, R44, R48, R46 ; @P0 BRA 0x6b00 ; LOP3.LUT R6, R37, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.GE.U32.AND P0, PT, R5.reuse, R6, PT ; IMAD.IADD R7, R5, 0x1, -R6 ; SEL R3, R3, 0x63400000, !P0 ; IMNMX R7, R7, -0x46a00000, !PT ; IMNMX R6, R7, 0x46a00000, PT ; IMAD.IADD R3, R6, 0x1, -R3 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; IADD3 R7, R3, 0x7fe00000, RZ ; DMUL R44, R8, R6 ; FSETP.GTU.AND P0, PT, |R45|, 1.469367938527859385e-39, PT ; @P0 BRA 0x6c80 ; DFMA R38, R8, -R38, R40 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R39.reuse, RZ, PT ; LOP3.LUT R5, R39, 0x80000000, R37, 0x48, !PT ; LOP3.LUT R7, R5, R7, RZ, 0xfc, !PT ; @!P0 BRA 0x6c80 ; IMAD.MOV R37, RZ, RZ, -R3 ; DMUL.RP R6, R8, R6 ; IMAD.MOV.U32 R36, RZ, RZ, RZ ; IADD3 R3, -R3, -0x43300000, RZ ; DFMA R36, R44, -R36, R8 ; FSETP.NEU.AND P0, PT, |R37|, R3, PT ; LOP3.LUT R3, R7, R5, RZ, 0x3c, !PT ; FSEL R6, R6, R44, !P0 ; FSEL R7, R3, R45, !P0 ; IMAD.MOV.U32 R44, RZ, RZ, R6 ; IMAD.MOV.U32 R45, RZ, RZ, R7 ; BRA 0x6c80 ; DSETP.NAN.AND P0, PT, R42, R42, PT ; @P0 BRA 0x6c50 ; DSETP.NAN.AND P0, PT, R36, R36, PT ; @P0 BRA 0x6c10 ; ISETP.NE.AND P0, PT, R7, R6, PT ; IMAD.MOV.U32 R44, RZ, RZ, 0x0 ; IMAD.MOV.U32 R45, RZ, RZ, -0x80000 ; @!P0 BRA 0x6c80 ; ISETP.NE.AND P0, PT, R7, 0x7ff00000, PT ; LOP3.LUT R3, R43, 0x80000000, R37, 0x48, !PT ; ISETP.EQ.OR P0, PT, R6, RZ, !P0 ; @P0 LOP3.LUT R5, R3, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R44, RZ, RZ, RZ ; @!P0 IMAD.MOV.U32 R45, RZ, RZ, R3 ; @P0 IMAD.MOV.U32 R44, RZ, RZ, RZ ; @P0 IMAD.MOV.U32 R45, RZ, RZ, R5 ; BRA 0x6c80 ; LOP3.LUT R3, R37, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R44, RZ, RZ, R36 ; IMAD.MOV.U32 R45, RZ, RZ, R3 ; BRA 0x6c80 ; LOP3.LUT R3, R43, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R44, RZ, RZ, R42 ; MOV R45, R3 ; BSYNC B0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; IMAD.MOV.U32 R6, RZ, RZ, R44 ; IMAD.MOV.U32 R3, RZ, RZ, R45 ; RET.REL.NODEC R4 0x0 ; SHF.R.U32.HI R5, RZ, 0x14, R9 ; ISETP.NE.AND P0, PT, R5, RZ, PT ; @!P0 DMUL R36, R8, 1.80143985094819840000e+16 ; @!P0 IMAD.MOV.U32 R9, RZ, RZ, R37 ; @!P0 LEA.HI R5, R37, 0xffffffca, RZ, 0xc ; @!P0 IMAD.MOV.U32 R8, RZ, RZ, R36 ; LOP3.LUT R7, R9, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R42, RZ, RZ, R8 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; LOP3.LUT R7, R7, 0x3ff00000, RZ, 0xfc, !PT ; ISETP.GE.U32.AND P1, PT, R7, 0x3ff6a09f, PT ; IMAD.MOV.U32 R43, RZ, RZ, R7 ; @P1 IADD3 R7, R43, -0x100000, RZ ; @P1 IMAD.MOV.U32 R43, RZ, RZ, R7 ; IADD3 R7, R5.reuse, -0x3ff, RZ ; @P1 IADD3 R7, R5, -0x3fe, RZ ; DADD R40, R42, 1 ; DADD R42, R42, -1 ; MUFU.RCP64H R9, R41 ; DFMA R38, -R40, R8, 1 ; DFMA R38, R38, R38, R38 ; DFMA R38, R8, R38, R8 ; IMAD.MOV.U32 R8, RZ, RZ, 0x7d2cafe2 ; IMAD.MOV.U32 R9, RZ, RZ, 0x3eb0f5ff ; DMUL R46, R38, R42 ; DFMA R46, R38, R42, R46 ; DMUL R48, R46, R46 ; DFMA R8, R48, R8, c[0x2][0x10] ; DFMA R40, R48, R8, c[0x2][0x18] ; DADD R8, R42, -R46 ; DFMA R40, R48, R40, c[0x2][0x20] ; DADD R8, R8, R8 ; DFMA R40, R48, R40, c[0x2][0x28] ; DFMA R8, R42, -R46, R8 ; DFMA R40, R48, R40, c[0x2][0x30] ; DMUL R8, R38, R8 ; DFMA R40, R48, R40, c[0x2][0x38] ; DFMA R44, R48, R40, c[0x2][0x40] ; IADD3 R39, R9, 0x100000, RZ ; IMAD.MOV.U32 R38, RZ, RZ, R8 ; DADD R42, -R44, c[0x2][0x40] ; DFMA R42, R48, R40, R42 ; DMUL R40, R46, R46 ; DFMA R48, R46, R46, -R40 ; DFMA R38, R46, R38, R48 ; DMUL R48, R46, R40 ; DFMA R36, R46, R40, -R48 ; DFMA R36, R8, R40, R36 ; DADD R40, RZ, R42 ; DFMA R36, R46, R38, R36 ; DADD R40, R40, c[0x2][0x48] ; DADD R38, R44, R40 ; DADD R44, R44, -R38 ; DMUL R42, R38, R48 ; DADD R44, R40, R44 ; DFMA R40, R38, R48, -R42 ; DFMA R36, R38, R36, R40 ; DFMA R44, R44, R48, R36 ; DADD R38, R42, R44 ; DADD R36, R46, R38 ; DADD R42, R42, -R38 ; DADD R46, R46, -R36 ; DADD R42, R44, R42 ; DADD R46, R38, R46 ; LOP3.LUT R38, R7, 0x80000000, RZ, 0x3c, !PT ; IMAD.MOV.U32 R39, RZ, RZ, 0x43300000 ; IMAD.MOV.U32 R7, RZ, RZ, R3 ; DADD R42, R42, R46 ; IMAD.SHL.U32 R5, R7.reuse, 0x2, RZ ; DADD R38, R38, c[0x2][0x50] ; LOP3.LUT R3, R7, 0xff0fffff, RZ, 0xc0, !PT ; DADD R42, R8, R42 ; ISETP.GT.U32.AND P0, PT, R5, -0x2000001, PT ; SEL R7, R3, R7, P0 ; DADD R40, R36, R42 ; DFMA R8, R38, c[0x2][0x58], R40 ; DADD R44, R36, -R40 ; DFMA R36, -R38, c[0x2][0x58], R8 ; DADD R44, R42, R44 ; IMAD.MOV.U32 R42, RZ, RZ, 0x652b82fe ; DADD R36, -R40, R36 ; IMAD.MOV.U32 R43, RZ, RZ, 0x3ff71547 ; DADD R44, R44, -R36 ; DFMA R44, R38, c[0x2][0x60], R44 ; DADD R38, R8, R44 ; DADD R8, R8, -R38 ; DMUL R36, R38, R6 ; DADD R8, R44, R8 ; DFMA R38, R38, R6, -R36 ; DFMA R8, R8, R6, R38 ; IMAD.MOV.U32 R38, RZ, RZ, 0x69ce2bdf ; IMAD.MOV.U32 R39, RZ, RZ, 0x3e5ade15 ; DADD R6, R36, R8 ; DFMA R42, R6, R42, 6.75539944105574400000e+15 ; FSETP.GEU.AND P0, PT, |R7|, 4.1917929649353027344, PT ; DADD R44, R42, -6.75539944105574400000e+15 ; DFMA R40, R44, c[0x2][0x68], R6 ; DFMA R40, R44, c[0x2][0x70], R40 ; DFMA R38, R40, R38, c[0x2][0x78] ; DFMA R38, R40, R38, c[0x2][0x80] ; DFMA R38, R40, R38, c[0x2][0x88] ; DFMA R38, R40, R38, c[0x2][0x90] ; DFMA R38, R40, R38, c[0x2][0x98] ; DFMA R38, R40, R38, c[0x2][0xa0] ; DFMA R38, R40, R38, c[0x2][0xa8] ; DFMA R38, R40, R38, c[0x2][0xb0] ; DFMA R38, R40, R38, c[0x2][0xb8] ; DFMA R38, R40, R38, 1 ; DFMA R40, R40, R38, 1 ; IMAD R39, R42, 0x100000, R41 ; IMAD.MOV.U32 R38, RZ, RZ, R40 ; @!P0 BRA 0x7490 ; FSETP.GEU.AND P0, PT, |R7|, 4.2275390625, PT ; DADD R38, R6, +INF ; DSETP.GEU.AND P1, PT, R6, RZ, PT ; FSEL R38, R38, RZ, P1 ; @!P0 LEA.HI R3, R42, R42, RZ, 0x1 ; FSEL R39, R39, RZ, P1 ; @!P0 SHF.R.S32.HI R3, RZ, 0x1, R3 ; @!P0 IMAD R41, R3, 0x100000, R41 ; @!P0 IMAD.IADD R3, R42, 0x1, -R3 ; @!P0 IMAD.MOV.U32 R42, RZ, RZ, RZ ; @!P0 LEA R43, R3, 0x3ff00000, 0x14 ; @!P0 DMUL R38, R40, R42 ; LOP3.LUT R3, R39, 0x7fffffff, RZ, 0xc0, !PT ; DADD R6, R36, -R6 ; IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; ISETP.NE.AND P0, PT, R3, 0x7ff00000, PT ; DADD R6, R8, R6 ; ISETP.EQ.AND P0, PT, R38, RZ, !P0 ; @!P0 DFMA R38, R6, R38, R38 ; IMAD.MOV.U32 R6, RZ, RZ, R38 ; IMAD.MOV.U32 R3, RZ, RZ, R39 ; RET.REL.NODEC R4 0x0 ; BRA 0x7530; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R4, SR_CTAID.Y ; S2R R5, SR_TID.Y ; S2R R16, SR_CTAID.X ; S2R R3, SR_TID.X ; S2R R2, SR_CTAID.Z ; S2R R7, SR_TID.Z ; IMAD R4, R4, c[0x0][0x4], R5 ; ISETP.GE.AND P0, PT, R4, c[0x0][0x1b4], PT ; IMAD R16, R16, c[0x0][0x0], R3 ; ISETP.GE.OR P0, PT, R16, c[0x0][0x1b0], P0 ; IMAD R2, R2, c[0x0][0x8], R7 ; ISETP.GE.OR P0, PT, R2, c[0x0][0x1b8], P0 ; @P0 EXIT ; I2F.F64 R2, R2 ; ULDC UR4, c[0x0][0x1b8] ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; UIADD3 UR4, UR4, -0x1, URZ ; IADD3 R12, R4, 0x1, RZ ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; ULDC.64 UR6, c[0x0][0x1b0] ; I2F.F64 R6, R4 ; DSETP.MAX.AND P0, P1, RZ, R2, PT ; IMAD.MOV.U32 R5, RZ, RZ, R3 ; I2F.F64 R8, UR4 ; IMAD.MOV.U32 R11, RZ, RZ, R2 ; UIADD3 UR4, UR7, -0x1, URZ ; FSEL R15, R0, R5, P0 ; SEL R10, R10, R11, P0 ; I2F.F64 R12, R12 ; @P1 LOP3.LUT R15, R5, 0x80000, RZ, 0xfc, !PT ; DSETP.MAX.AND P1, P2, RZ, R6, PT ; MOV R5, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; I2F.F64 R2, UR4 ; IMAD.MOV.U32 R11, RZ, RZ, R15 ; UIADD3 UR4, UR6, -0x1, URZ ; FSEL R15, R0, R7, P1 ; SEL R6, R6, R5, P1 ; ULDC.64 UR6, c[0x0][0x118] ; DSETP.GT.AND P0, PT, R10, R8, PT ; IMAD.MOV.U32 R17, RZ, RZ, R12 ; DSETP.MAX.AND P3, P4, RZ, R12, PT ; @P2 LOP3.LUT R15, R7, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R7, RZ, RZ, RZ ; FSEL R8, R8, R10, P0 ; FSEL R9, R9, R11, P0 ; IADD3 R10, R4.reuse, 0x2, RZ ; F2I.F64.TRUNC R5, R8 ; IADD3 R12, R4, 0x3, RZ ; I2F.F64 R10, R10 ; FSEL R9, R7, R13, P3 ; IMAD.MOV.U32 R7, RZ, RZ, R15 ; SEL R8, R0, R17, P3 ; @P4 LOP3.LUT R9, R13, 0x80000, RZ, 0xfc, !PT ; I2F.F64 R12, R12 ; DSETP.GT.AND P0, PT, R6, R2, PT ; FSEL R14, R2, R6, P0 ; IMAD.MOV.U32 R17, RZ, RZ, R10 ; FSEL R15, R3, R7, P0 ; DSETP.GT.AND P0, PT, R8, R2, PT ; F2I.F64.TRUNC R0, R14 ; FSEL R6, R2, R8, P0 ; DSETP.MAX.AND P2, P3, RZ, R12, PT ; FSEL R7, R3, R9, P0 ; IMAD.MOV.U32 R19, RZ, RZ, R12 ; MOV R18, R13 ; DSETP.MAX.AND P0, P1, RZ, R10, PT ; F2I.F64.TRUNC R6, R6 ; IADD3 R14, R4, -0x1, RZ ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; CS2R R12, SRZ ; SEL R10, R10, R17, P0 ; I2F.F64 R14, R14 ; FSEL R13, R13, R18, P2 ; IMAD.MOV.U32 R7, RZ, RZ, RZ ; SEL R12, R12, R19, P2 ; @P3 LOP3.LUT R13, R18, 0x80000, RZ, 0xfc, !PT ; FSEL R7, R7, R11, P0 ; I2F.F64 R8, R16 ; @P1 LOP3.LUT R7, R11, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P3, PT, R12, R2, PT ; IMAD.MOV.U32 R11, RZ, RZ, R7 ; IADD3 R16, R4.reuse, -0x2, RZ ; IMAD.MOV.U32 R7, RZ, RZ, RZ ; IADD3 R4, R4, -0x3, RZ ; DSETP.GT.AND P2, PT, R10, R2, PT ; MOV R22, R15 ; I2F.F64 R16, R16 ; DSETP.MAX.AND P0, P1, RZ, R8, PT ; IMAD.MOV.U32 R21, RZ, RZ, R8 ; FSEL R18, R2.reuse, R10, P2 ; IMAD.MOV.U32 R20, RZ, RZ, R9 ; FSEL R19, R3.reuse, R11, P2 ; DSETP.MAX.AND P2, P6, RZ, R14, PT ; I2F.F64 R8, R4 ; IMAD.MOV.U32 R11, RZ, RZ, R14 ; FSEL R15, R3, R13, P3 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; FSEL R14, R2, R12, P3 ; FSEL R7, R7, R22, P2 ; DSETP.MAX.AND P4, P5, RZ, R16, PT ; SEL R10, R10, R11, P2 ; IMAD.MOV.U32 R11, RZ, RZ, RZ ; F2I.F64.TRUNC R18, R18 ; IMAD.MOV.U32 R13, RZ, RZ, R16 ; @P6 LOP3.LUT R7, R22, 0x80000, RZ, 0xfc, !PT ; MOV R12, RZ ; DSETP.MAX.AND P3, P2, RZ, R8, PT ; IMAD.MOV.U32 R23, RZ, RZ, R8 ; SEL R12, R12, R13, P4 ; IMAD.MOV.U32 R22, RZ, RZ, R9 ; FSEL R19, R11, R17, P4 ; IMAD.MOV.U32 R11, RZ, RZ, R7 ; I2F.F64 R8, UR4 ; IMAD.MOV.U32 R7, RZ, RZ, RZ ; @P5 LOP3.LUT R19, R17, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P4, PT, R10, R2.reuse, PT ; IMAD.MOV.U32 R13, RZ, RZ, R19 ; F2I.F64.TRUNC R4, R14 ; FSEL R16, R2, R10, P4 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; FSEL R17, R3, R11, P4 ; DSETP.GT.AND P5, PT, R12, R2, PT ; FSEL R11, R7, R20, P0 ; SEL R10, R10, R21, P0 ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; FSEL R15, R7, R22, P3 ; F2I.F64.TRUNC R16, R16 ; @P2 LOP3.LUT R15, R22, 0x80000, RZ, 0xfc, !PT ; IMAD R7, R5, c[0x0][0x1b4], R6 ; SEL R14, R14, R23, P3 ; @P1 LOP3.LUT R11, R20, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R20, RZ, RZ, 0x8 ; FSEL R12, R2, R12, P5 ; DSETP.GT.AND P2, PT, R14, R2, PT ; FSEL R13, R3, R13, P5 ; IMAD R17, R5, c[0x0][0x1b4], R0 ; DSETP.GT.AND P0, PT, R10, R8, PT ; F2I.F64.TRUNC R12, R12 ; FSEL R14, R2, R14, P2 ; FSEL R15, R3, R15, P2 ; FSEL R2, R8, R10, P0 ; FSEL R3, R9, R11, P0 ; F2I.F64.TRUNC R14, R14 ; IMAD R11, R5.reuse, c[0x0][0x1b4], R4 ; IMAD R9, R5.reuse, c[0x0][0x1b4], R18 ; IMAD R13, R5, c[0x0][0x1b4], R16 ; F2I.F64.TRUNC R2, R2 ; IMAD R19, R5.reuse, c[0x0][0x1b4], R12 ; IMAD R5, R5, c[0x0][0x1b4], R14 ; IMAD R4, R17, c[0x0][0x1b0], R2.reuse ; IMAD R36, R7, c[0x0][0x1b0], R2 ; IMAD.WIDE R64, R4, R20, c[0x0][0x180] ; IMAD.WIDE R6, R4, R20, c[0x0][0x188] ; LDG.E.64 R64, [R64.64] ; IMAD R19, R19, c[0x0][0x1b0], R2.reuse ; LDG.E.64 R6, [R6.64] ; IMAD R9, R9, c[0x0][0x1b0], R2.reuse ; IMAD R5, R5, c[0x0][0x1b0], R2.reuse ; IMAD R13, R13, c[0x0][0x1b0], R2 ; IMAD R11, R11, c[0x0][0x1b0], R2 ; IMAD.WIDE R22, R19, R20, c[0x0][0x178] ; IMAD.WIDE R44, R4, R20.reuse, c[0x0][0x178] ; LDG.E.64 R22, [R22.64] ; IMAD.WIDE R24, R5, R20.reuse, c[0x0][0x178] ; LDG.E.64 R44, [R44.64] ; IMAD.WIDE R38, R13, R20.reuse, c[0x0][0x178] ; LDG.E.64 R24, [R24.64] ; IMAD.WIDE R36, R36, R20, c[0x0][0x178] ; LDG.E.64 R38, [R38.64] ; IMAD.WIDE R18, R9, R20.reuse, c[0x0][0x178] ; LDG.E.64 R36, [R36.64] ; IMAD.WIDE R20, R11, R20, c[0x0][0x178] ; LDG.E.64 R18, [R18.64] ; LDG.E.64 R20, [R20.64] ; BSSY B1, 0x6940 ; MOV R66, c[0x0][0x1c0] ; IMAD.MOV.U32 R67, RZ, RZ, c[0x0][0x1c4] ; SHF.R.S32.HI R3, RZ, 0x1f, R4 ; IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x1c8] ; IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x1cc] ; IMAD.MOV.U32 R42, RZ, RZ, c[0x0][0x1d0] ; IMAD.MOV.U32 R43, RZ, RZ, c[0x0][0x1d4] ; DSETP.GEU.AND P1, PT, R64, c[0x0][0x1c0], PT ; DSETP.GEU.AND P0, PT, R6, c[0x0][0x1c0], PT ; @P0 BRA P1, 0x27a0 ; DSETP.GEU.AND P1, PT, R64, c[0x0][0x1c0], PT ; IMAD.MOV.U32 R40, RZ, RZ, c[0x0][0x1c0] ; MOV R41, c[0x0][0x1c4] ; IMAD.MOV.U32 R48, RZ, RZ, c[0x0][0x1c0] ; MOV R10, 0x1 ; IMAD.MOV.U32 R49, RZ, RZ, c[0x0][0x1c4] ; BSSY B2, 0xf70 ; @!P0 IMAD.MOV.U32 R24, RZ, RZ, R22 ; DADD R50, R40.reuse, c[0x0][0x1c0] ; @!P0 IMAD.MOV.U32 R25, RZ, RZ, R23 ; @!P0 MOV R66, R6 ; @!P0 IMAD.MOV.U32 R67, RZ, RZ, R7 ; DMUL R46, R40, -2 ; @!P0 IMAD.MOV.U32 R22, RZ, RZ, R38 ; @P1 IMAD.MOV.U32 R64, RZ, RZ, c[0x0][0x1c0] ; @P1 DMUL R8, R40.reuse, 3 ; @P1 IMAD.MOV.U32 R65, RZ, RZ, c[0x0][0x1c4] ; @P1 IMAD.MOV.U32 R48, RZ, RZ, R50 ; @P0 DMUL R40, R40, -3 ; @P1 IMAD.MOV.U32 R49, RZ, RZ, R51 ; @!P0 IMAD.MOV.U32 R23, RZ, RZ, R39 ; @P1 IMAD.MOV.U32 R50, RZ, RZ, R8 ; @P1 IMAD.MOV.U32 R51, RZ, RZ, R9 ; @!P0 IMAD.MOV.U32 R40, RZ, RZ, R46 ; @!P0 IMAD.MOV.U32 R41, RZ, RZ, R47 ; @!P0 DADD R46, -RZ, -c[0x0][0x1c0] ; DADD R8, -R48, R50 ; MUFU.RCP64H R11, R9 ; DFMA R14, -R8, R10, 1 ; DFMA R26, R14, R14, R14 ; IMAD.MOV.U32 R14, RZ, RZ, R36 ; IMAD.MOV.U32 R15, RZ, RZ, R37 ; DFMA R26, R10, R26, R10 ; @P1 IMAD.MOV.U32 R14, RZ, RZ, R18 ; @P1 IMAD.MOV.U32 R15, RZ, RZ, R19 ; @P1 IMAD.MOV.U32 R18, RZ, RZ, R20 ; @P1 IMAD.MOV.U32 R19, RZ, RZ, R21 ; DFMA R20, -R8, R26, 1 ; DADD R10, -R14, R18 ; DFMA R20, R26, R20, R26 ; DMUL R18, R10, R20 ; FSETP.GEU.AND P3, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R26, -R8, R18, R10 ; DFMA R20, R20, R26, R18 ; CS2R R18, SRZ ; @P0 IMAD.MOV.U32 R26, RZ, RZ, R38 ; @P0 MOV R27, R39 ; @P1 IMAD.MOV.U32 R18, RZ, RZ, R36 ; @!P0 CS2R R26, SRZ ; @P1 IMAD.MOV.U32 R19, RZ, RZ, R37 ; FFMA R5, RZ, R9, R21 ; FSETP.GT.AND P2, PT, |R5|, 1.469367938527859385e-39, PT ; @P2 BRA P3, 0xf60 ; MOV R7, R11 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; MOV R6, 0xf40 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R20, RZ, RZ, R8 ; IMAD.MOV.U32 R21, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, R48, -R64 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x1100 ; DADD R28, R14, -R18 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R29|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R14, R28, R6 ; DFMA R10, -R8, R14, R28 ; DFMA R14, R6, R10, R14 ; FFMA R5, RZ, R9, R15 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x10f0 ; IMAD.MOV.U32 R10, RZ, RZ, R28 ; MOV R5, R9 ; IMAD.MOV.U32 R7, RZ, RZ, R29 ; MOV R6, 0x10d0 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R14, RZ, RZ, R8 ; IMAD.MOV.U32 R15, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R65 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R44, R18 ; BSSY B2, 0x1280 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R64, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R64, 1 ; DFMA R6, R8, R6, R8 ; DMUL R34, R10, R6 ; DFMA R8, R34, -R64, R10 ; DFMA R34, R6, R8, R34 ; FFMA R5, RZ, R65, R35 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1270 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x1250 ; IMAD.MOV.U32 R8, RZ, RZ, R64 ; IMAD.MOV.U32 R5, RZ, RZ, R65 ; CALL.REL.NOINC 0x13360 ; MOV R34, R8 ; IMAD.MOV.U32 R35, RZ, RZ, R5 ; BSYNC B2 ; DADD R18, RZ, R66 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x1410 ; DADD R10, R44, -R26 ; MUFU.RCP64H R7, R19 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R18, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R18, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R32, R10, R6 ; DFMA R8, -R18, R32, R10 ; DFMA R32, R6, R8, R32 ; FFMA R5, RZ, R19, R33 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1400 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x13e0 ; IMAD.MOV.U32 R8, RZ, RZ, R18 ; IMAD.MOV.U32 R5, RZ, RZ, R19 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R32, RZ, RZ, R8 ; MOV R33, R5 ; BSYNC B2 ; DADD R8, -R46, -R66 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x15a0 ; DADD R26, -R22, R26 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R27|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R30, R26, R6 ; DFMA R10, -R8, R30, R26 ; DFMA R30, R6, R10, R30 ; FFMA R5, RZ, R9, R31 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1590 ; IMAD.MOV.U32 R10, RZ, RZ, R26 ; MOV R6, 0x1570 ; IMAD.MOV.U32 R7, RZ, RZ, R27 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; IMAD.MOV.U32 R31, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, -R40, R46 ; MOV R6, 0x1 ; BSSY B2, 0x1730 ; DADD R22, R22, -R24 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R28, R22, R6 ; DFMA R10, -R8, R28, R22 ; DFMA R28, R6, R10, R28 ; FFMA R5, RZ, R9, R29 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1720 ; IMAD.MOV.U32 R10, RZ, RZ, R22 ; MOV R6, 0x1700 ; IMAD.MOV.U32 R7, RZ, RZ, R23 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R28, RZ, RZ, R8 ; IMAD.MOV.U32 R29, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, R50, -R64 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x18c0 ; DADD R20, -R14, R20 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R26, R20, R6 ; DFMA R10, -R8, R26, R20 ; DFMA R26, R6, R10, R26 ; FFMA R5, RZ, R9, R27 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x18b0 ; MOV R10, R20 ; IMAD.MOV.U32 R7, RZ, RZ, R21 ; MOV R6, 0x1890 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R26, RZ, RZ, R8 ; IMAD.MOV.U32 R27, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R49 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R34, R14 ; BSSY B2, 0x1a40 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R48, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R48, 1 ; DFMA R6, R8, R6, R8 ; DMUL R24, R10, R6 ; DFMA R8, R24, -R48, R10 ; DFMA R24, R6, R8, R24 ; FFMA R5, RZ, R49, R25 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1a30 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R8, R48 ; IMAD.MOV.U32 R5, RZ, RZ, R49 ; MOV R6, 0x1a10 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R24, RZ, RZ, R8 ; IMAD.MOV.U32 R25, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, R64, R66 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x1bd0 ; DADD R14, -R32, R34 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R22, R14, R6 ; DFMA R10, -R8, R22, R14 ; DFMA R22, R6, R10, R22 ; FFMA R5, RZ, R9, R23 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1bc0 ; IMAD.MOV.U32 R10, RZ, RZ, R14 ; MOV R5, R9 ; IMAD.MOV.U32 R7, RZ, RZ, R15 ; MOV R6, 0x1ba0 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R22, RZ, RZ, R8 ; IMAD.MOV.U32 R23, RZ, RZ, R5 ; BSYNC B2 ; DADD R14, RZ, -R46 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x1d60 ; DADD R10, -R30, R32 ; MUFU.RCP64H R7, R15 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R14, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R14, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R20, R10, R6 ; DFMA R8, -R14, R20, R10 ; DFMA R20, R6, R8, R20 ; FFMA R5, RZ, R15, R21 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1d50 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x1d30 ; IMAD.MOV.U32 R8, RZ, RZ, R14 ; IMAD.MOV.U32 R5, RZ, RZ, R15 ; CALL.REL.NOINC 0x13360 ; MOV R20, R8 ; IMAD.MOV.U32 R21, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, -R40, -R66 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x1ef0 ; DADD R30, -R28, R30 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R31|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R28, R30, R6 ; DFMA R10, -R8, R28, R30 ; DFMA R28, R6, R10, R28 ; FFMA R5, RZ, R9, R29 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x1ee0 ; IMAD.MOV.U32 R10, RZ, RZ, R30 ; MOV R6, 0x1ec0 ; IMAD.MOV.U32 R7, RZ, RZ, R31 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R28, RZ, RZ, R8 ; MOV R29, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R51 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R24, R26 ; BSSY B2, 0x2070 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R50, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R50, 1 ; DFMA R6, R8, R6, R8 ; DMUL R26, R10, R6 ; DFMA R8, R26, -R50, R10 ; DFMA R26, R6, R8, R26 ; FFMA R5, RZ, R51, R27 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2060 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x2040 ; IMAD.MOV.U32 R8, RZ, RZ, R50 ; IMAD.MOV.U32 R5, RZ, RZ, R51 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R26, RZ, RZ, R8 ; IMAD.MOV.U32 R27, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, R48, R66 ; MOV R6, 0x1 ; BSSY B2, 0x2200 ; DADD R50, -R22, R24 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R51|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R30, R50, R6 ; DFMA R10, -R8, R30, R50 ; DFMA R30, R6, R10, R30 ; FFMA R5, RZ, R9, R31 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x21f0 ; IMAD.MOV.U32 R10, RZ, RZ, R50 ; MOV R6, 0x21d0 ; IMAD.MOV.U32 R7, RZ, RZ, R51 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; IMAD.MOV.U32 R31, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, -R46, R64 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x2390 ; DADD R50, -R20, R22 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R51|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R46, R50, R6 ; DFMA R10, -R8, R46, R50 ; DFMA R46, R6, R10, R46 ; FFMA R5, RZ, R9, R47 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2380 ; MOV R10, R50 ; IMAD.MOV.U32 R7, RZ, RZ, R51 ; MOV R6, 0x2360 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R46, RZ, RZ, R8 ; IMAD.MOV.U32 R47, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, RZ, -R40 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x2520 ; DADD R40, -R28, R20 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R41|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R10, R40, R6 ; DFMA R28, -R8, R10, R40 ; DFMA R6, R6, R28, R10 ; FFMA R5, RZ, R9, R7 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2510 ; IMAD.MOV.U32 R10, RZ, RZ, R40 ; MOV R7, R41 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; MOV R6, 0x24f0 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R6, RZ, RZ, R8 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; BSYNC B2 ; DMUL R8, R20, R22 ; DSETP.GEU.AND P0, PT, |R46|, |R6|, PT ; DSETP.GEU.AND P4, PT, R8, RZ, PT ; FSEL R8, R46, R6, !P0 ; FSEL R9, R47, R7, !P0 ; DMUL R10, R22, R24 ; DMUL R6, R18, R14 ; DADD R64, RZ, -R64 ; DSETP.GEU.AND P0, PT, |R46|, |R30|, PT ; DADD R48, RZ, -R48 ; DSETP.GEU.AND P2, PT, |R30|, |R26|, PT ; DSETP.GEU.AND P5, PT, R10, RZ, PT ; FSEL R10, R46, R30, !P0 ; DMUL R6, R6, R8 ; FSEL R11, R47, R31, !P0 ; FSEL R14, R30, R26, !P2 ; DSETP.GEU.AND P1, PT, |R20|, |R22|, PT ; FSEL R15, R31, R27, !P2 ; DSETP.GEU.AND P3, PT, |R22|, |R24|, PT ; FSEL R16, R20, R22, !P1 ; DMUL R8, R18, R64 ; FSEL R20, R21, R23, !P1 ; FSEL R5, R22, R24, !P3 ; DMUL R48, R64, R48 ; FSEL R22, R23, R25, !P3 ; DMUL R8, R8, R10 ; FSEL R10, R5, RZ, P5 ; DMUL R48, R48, R14 ; FSEL R11, R22, RZ, P5 ; FSEL R14, R16, RZ, P4 ; FSEL R15, R20, RZ, P4 ; FSEL R6, R6, R8, !P1 ; FSEL R7, R7, R9, !P1 ; DFMA R14, R18, R14, R32 ; FSEL R8, R8, R48, !P3 ; FSEL R9, R9, R49, !P3 ; DFMA R18, R64, R10, R34 ; DADD R14, R14, R6 ; DADD R18, R18, R8 ; BRA 0x6930 ; MUFU.RCP64H R7, c[0x0][0x1c4] ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x1c0] ; BSSY B2, 0x2940 ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x1c4] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R8, R6, -R10, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R10, 1 ; DADD R10, R22, -R24 ; DFMA R6, R8, R6, R8 ; DMUL R14, R10, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R14, -c[0x0][0x1c0], R10 ; DFMA R14, R6, R8, R14 ; FFMA R5, RZ, c[0x0][0x1c4], R15 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2930 ; MOV R7, R11 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c0] ; MOV R6, 0x2910 ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1c4] ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R14, RZ, RZ, R8 ; IMAD.MOV.U32 R15, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1c4] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c0] ; MOV R6, 0x1 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1c4] ; BSSY B2, 0x2ae0 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DADD R6, -R22, R38 ; DFMA R8, R10, -R8, 1 ; DFMA R10, R10, R8, R10 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; DMUL R34, R10, R6 ; DFMA R8, R34, -c[0x0][0x1c0], R6 ; DFMA R34, R10, R8, R34 ; FFMA R5, RZ, c[0x0][0x1c4], R35 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2ad0 ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; MOV R6, 0x2ab0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c0] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1c4] ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R34, RZ, RZ, R8 ; IMAD.MOV.U32 R35, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1c4] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c0] ; MOV R9, c[0x0][0x1c4] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x2c80 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DADD R6, R44, -R38 ; DFMA R8, R10, -R8, 1 ; DFMA R10, R10, R8, R10 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; DMUL R32, R10, R6 ; DFMA R8, R32, -c[0x0][0x1c0], R6 ; DFMA R32, R10, R8, R32 ; FFMA R5, RZ, c[0x0][0x1c4], R33 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2c70 ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; MOV R6, 0x2c50 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c0] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1c4] ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R32, RZ, RZ, R8 ; IMAD.MOV.U32 R33, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1c4] ; MOV R8, c[0x0][0x1c0] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1c4] ; BSSY B2, 0x2e20 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DADD R6, -R44, R36 ; DFMA R8, R10, -R8, 1 ; DFMA R10, R10, R8, R10 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; DMUL R30, R10, R6 ; DFMA R8, R30, -c[0x0][0x1c0], R6 ; DFMA R30, R10, R8, R30 ; FFMA R5, RZ, c[0x0][0x1c4], R31 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2e10 ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; MOV R6, 0x2df0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c0] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1c4] ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; MOV R31, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1c4] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c0] ; BSSY B2, 0x2fc0 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1c4] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, -R36, R18 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R28, R8, R10 ; DFMA R6, R28, -c[0x0][0x1c0], R10 ; DFMA R28, R8, R6, R28 ; FFMA R5, RZ, c[0x0][0x1c4], R29 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x2fb0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x2f90 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c0] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1c4] ; CALL.REL.NOINC 0x13360 ; MOV R28, R8 ; IMAD.MOV.U32 R29, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1c4] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c0] ; BSSY B2, 0x3160 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1c4] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, R20, -R18 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R26, R8, R10 ; DFMA R6, R26, -c[0x0][0x1c0], R10 ; DFMA R26, R8, R6, R26 ; FFMA R5, RZ, c[0x0][0x1c4], R27 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x3150 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R5, c[0x0][0x1c4] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c0] ; MOV R6, 0x3130 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R26, RZ, RZ, R8 ; IMAD.MOV.U32 R27, RZ, RZ, R5 ; BSYNC B2 ; DADD R6, R34.reuse, R34 ; BSSY B0, 0x3260 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DMUL R8, R34, c[0x2][0x18] ; DADD R24, -R6, R14 ; DMUL R6, R34, c[0x2][0x0] ; DADD R24, R24, R32 ; DFMA R6, R14, c[0x2][0x8], R6 ; DFMA R8, R32, c[0x2][0x20], -R8 ; DADD R10, -RZ, |R24| ; DFMA R22, R32, c[0x2][0x10], R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DFMA R20, R30, c[0x2][0x8], R8 ; MOV R8, 0x3250 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R24.reuse, 2 ; BSSY B0, 0x33a0 ; IMAD.MOV.U32 R18, RZ, RZ, R6 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; IMAD.MOV.U32 R19, RZ, RZ, R5 ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R18, SRZ ; @P1 BRA 0x3390 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x3380 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R24, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R24, 0x7ff00000, P0 ; @P0 BRA 0x3390 ; MOV R18, 0x0 ; IMAD.MOV.U32 R19, RZ, RZ, 0x7ff00000 ; BRA 0x3390 ; DADD R18, R24, 2 ; BSYNC B0 ; DFMA R24, R34, -4, R14 ; BSSY B0, 0x3430 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R8, 0x3420 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DFMA R24, R32, 3, R24 ; DADD R10, -RZ, |R24| ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R34, R34 ; BSSY B0, 0x35d0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P1, PT, R24, RZ, PT ; DADD R14, -R8, R14 ; DADD R8, R24, 2 ; DADD R14, R14, R32 ; @!P1 CS2R R6, SRZ ; DMUL R10, R18, c[0x2][0x28] ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; DSETP.NEU.AND P0, PT, R14, 1, PT ; ISETP.NE.AND P2, PT, R8, 0x7ff00000, PT ; FSEL R10, R10, 1.46601546874880000000e+13, P0 ; FSEL R11, R11, 1.8854166269302368164, P0 ; @P2 BRA 0x35c0 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x35b0 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R5, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x35c0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x35c0 ; DADD R6, R24, 2 ; BSYNC B0 ; DADD R8, R32, R32 ; BSSY B0, 0x36e0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DMUL R6, R6, 0.25 ; DADD R8, -R8, R34 ; DSETP.NEU.AND P0, PT, R24, 1, PT ; DADD R18, R8, R30 ; FSEL R24, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R25, R7, 1.625, P0 ; DADD R8, -RZ, |R18| ; DADD R24, R10, R24 ; MOV R10, R8 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; MOV R8, 0x36d0 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R18.reuse, 2 ; BSSY B0, 0x3810 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R18, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x3800 ; DSETP.GTU.AND P0, PT, |R18|, +INF , PT ; @P0 BRA 0x37f0 ; ISETP.NE.AND P0, PT, R18, RZ, PT ; LOP3.LUT R5, R19, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x3800 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x3800 ; DADD R6, R18, 2 ; BSYNC B0 ; DMUL R6, R6, c[0x2][0x28] ; BSSY B0, 0x38d0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x38c0 ; DADD R14, -R30, R34 ; DSETP.NEU.AND P0, PT, R18, 1, PT ; DADD R10, -RZ, |R14| ; FSEL R18, R6, 1.46601546874880000000e+13, P0 ; FSEL R19, R7, 1.8854166269302368164, P0 ; MOV R6, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R14.reuse, 2 ; BSSY B0, 0x3a10 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R14, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x3a00 ; DADD R8, -R30, R34 ; DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; @P0 BRA 0x39f0 ; ISETP.NE.AND P0, PT, R8, RZ, PT ; LOP3.LUT R8, R9, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; @P0 BRA 0x3a00 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x3a00 ; DADD R6, R14, 2 ; BSYNC B0 ; DADD R8, R30, R30 ; BSSY B0, 0x3b00 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DMUL R6, R6, 0.25 ; DADD R8, -R8, R32 ; DSETP.NEU.AND P0, PT, R14, 1, PT ; DADD R40, R8, R28 ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R10, -RZ, |R40| ; MOV R8, 0x3af0 ; DADD R18, R18, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R40.reuse, 2 ; BSSY B0, 0x3c30 ; MOV R7, R5 ; DSETP.NEU.AND P0, PT, R40, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x3c20 ; DSETP.GTU.AND P0, PT, |R40|, +INF , PT ; @P0 BRA 0x3c10 ; ISETP.NE.AND P0, PT, R40, RZ, PT ; LOP3.LUT R5, R41, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x3c20 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x3c20 ; DADD R6, R40, 2 ; BSYNC B0 ; DMUL R8, R32, 3 ; BSSY B0, 0x3d10 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DMUL R6, R6, c[0x2][0x28] ; DFMA R8, R30, -4, R8 ; DSETP.NEU.AND P0, PT, R40, 1, PT ; DADD R14, R8, R28 ; FSEL R40, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R41, R7, 1.8854166269302368164, P0 ; DADD R10, -RZ, |R14| ; MOV R8, 0x3d00 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R14.reuse, 2 ; BSSY B0, 0x3e40 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R14, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x3e30 ; DSETP.GTU.AND P0, PT, |R14|, +INF , PT ; @P0 BRA 0x3e20 ; ISETP.NE.AND P0, PT, R14, RZ, PT ; LOP3.LUT R5, R15, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x3e30 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; MOV R7, 0x7ff00000 ; BRA 0x3e30 ; DADD R6, R14, 2 ; BSYNC B0 ; DMUL R6, R6, 0.25 ; BSSY B0, 0x3f10 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x3f00 ; DSETP.NEU.AND P0, PT, R14, 1, PT ; DADD R24, R24, c[0x2][0x30] ; FSEL R14, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R15, R7, 1.625, P0 ; DADD R10, -RZ, |R24| ; DADD R14, R40, R14 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R24.reuse, 2 ; BSSY B0, 0x4040 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x4030 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x4020 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R5, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x4030 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x4030 ; DADD R6, R24, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0x41a0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x38] ; DFMA R40, R10, -R6, c[0x2][0x38] ; DFMA R8, R8, R40, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0x4190 ; MOV R8, R6 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; MOV R6, 0x4180 ; IMAD.MOV.U32 R10, RZ, RZ, -0x66666666 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fb99999 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DADD R18, R18, c[0x2][0x30] ; BSSY B0, 0x4250 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R24, 1, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R18| ; FSEL R24, R8, -1.5881868392106855534e-23, P0 ; FSEL R25, R9, 1.4499999284744262695, P0 ; MOV R8, 0x4240 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R18.reuse, 2 ; BSSY B0, 0x4380 ; MOV R7, R5 ; DSETP.NEU.AND P0, PT, R18, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x4370 ; DSETP.GTU.AND P0, PT, |R18|, +INF , PT ; @P0 BRA 0x4360 ; ISETP.NE.AND P0, PT, R18, RZ, PT ; LOP3.LUT R5, R19, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x4370 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x4370 ; DADD R6, R18, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0x44e0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x40] ; DFMA R40, R10, -R6, c[0x2][0x40] ; DFMA R8, R8, R40, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0x44d0 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x44c0 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; MOV R7, 0x3fe33333 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DADD R14, R14, c[0x2][0x30] ; BSSY B0, 0x4590 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R18, 1, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R14| ; FSEL R18, R8, 4.172325063223070174e-08, P0 ; FSEL R19, R9, 1.7749999761581420898, P0 ; MOV R8, 0x4580 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R14.reuse, 2 ; BSSY B0, 0x46c0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R14, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x46b0 ; DSETP.GTU.AND P0, PT, |R14|, +INF , PT ; @P0 BRA 0x46a0 ; ISETP.NE.AND P0, PT, R14, RZ, PT ; LOP3.LUT R5, R15, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x46b0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x46b0 ; DADD R6, R14, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; MOV R8, 0x1 ; DMUL R46, R30, c[0x2][0x20] ; BSSY B2, 0x4860 ; DMUL R48, R28, c[0x2][0x18] ; DFMA R46, R32, c[0x2][0x8], R46 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x48] ; DFMA R40, R10, -R6, c[0x2][0x48] ; DFMA R8, R8, R40, R10 ; DMUL R40, R30, c[0x2][0x8] ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0x4850 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x4840 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fd33333 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DSETP.NEU.AND P0, PT, R14, 1, PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R25|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x4a30 ; DADD R14, R24, R18 ; FSEL R50, R8, 4.172325063223070174e-08, P0 ; FSEL R51, R9, 1.6499999761581420898, P0 ; DADD R14, R14, R50 ; MUFU.RCP64H R7, R15 ; DFMA R8, -R14, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R14, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R64, R6, R24 ; DFMA R8, -R14, R64, R24 ; DFMA R64, R6, R8, R64 ; FFMA R5, RZ, R15, R65 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x4a20 ; MOV R10, R24 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; MOV R6, 0x4a00 ; IMAD.MOV.U32 R8, RZ, RZ, R14 ; IMAD.MOV.U32 R5, RZ, RZ, R15 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R64, RZ, RZ, R8 ; IMAD.MOV.U32 R65, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R15 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R19|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x4bd0 ; DFMA R8, -R14, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R14, R8, 1 ; DFMA R8, R8, R6, R8 ; MOV R6, R18 ; IMAD.MOV.U32 R7, RZ, RZ, R19 ; DMUL R24, R8, R6 ; DFMA R6, -R14, R24, R6 ; DFMA R24, R8, R6, R24 ; FFMA R5, RZ, R15, R25 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x4bc0 ; IMAD.MOV.U32 R10, RZ, RZ, R18 ; MOV R6, 0x4ba0 ; IMAD.MOV.U32 R7, RZ, RZ, R19 ; IMAD.MOV.U32 R8, RZ, RZ, R14 ; IMAD.MOV.U32 R5, RZ, RZ, R15 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R24, RZ, RZ, R8 ; MOV R25, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R15 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R51|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x4d60 ; DFMA R8, -R14, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R14, R8, 1 ; DFMA R10, R8, R6, R8 ; IMAD.MOV.U32 R8, RZ, RZ, R50 ; IMAD.MOV.U32 R9, RZ, RZ, R51 ; DMUL R6, R10, R8 ; DFMA R8, -R14, R6, R8 ; DFMA R8, R10, R8, R6 ; FFMA R5, RZ, R15, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x4d50 ; IMAD.MOV.U32 R8, RZ, RZ, R14 ; MOV R7, R51 ; IMAD.MOV.U32 R5, RZ, RZ, R15 ; MOV R6, 0x4d40 ; IMAD.MOV.U32 R10, RZ, RZ, R50 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DADD R6, R28, R28 ; BSSY B0, 0x4eb0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DMUL R20, R20, R24 ; DADD R6, -R6, R26 ; DADD R46, -R48, R46 ; DADD R24, R6, R30 ; DMUL R6, R28, c[0x2][0x0] ; DFMA R20, R22, R64, R20 ; DFMA R48, R30, c[0x2][0x20], -R48 ; DFMA R18, R32, c[0x2][0x20], R40 ; DFMA R6, R26, c[0x2][0x8], R6 ; DFMA R14, R46, R8, R20 ; MOV R8, 0x4ea0 ; DADD R10, -RZ, |R24| ; DFMA R20, R32, c[0x2][0x8], R48 ; DFMA R18, R34, c[0x2][0x50], R18 ; DFMA R22, R30, c[0x2][0x10], R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R24.reuse, 2 ; BSSY B0, 0x4fe0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x4fd0 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x4fc0 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R5, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x4fd0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x4fd0 ; DADD R6, R24, 2 ; BSYNC B0 ; DFMA R26, R28, -4, R26 ; BSSY B0, 0x50c0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x50b0 ; DMUL R40, R30, 3 ; DMUL R6, R6, c[0x2][0x28] ; DADD R26, R26, R40 ; DSETP.NEU.AND P0, PT, R24, 1, PT ; DADD R10, -RZ, |R26| ; FSEL R46, R6, 1.46601546874880000000e+13, P0 ; FSEL R47, R7, 1.8854166269302368164, P0 ; MOV R6, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R26.reuse, 2 ; BSSY B0, 0x51f0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R26, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x51e0 ; DSETP.GTU.AND P0, PT, |R26|, +INF , PT ; @P0 BRA 0x51d0 ; ISETP.NE.AND P0, PT, R26, RZ, PT ; LOP3.LUT R5, R27, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x51e0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x51e0 ; DADD R6, R26, 2 ; BSYNC B0 ; DADD R24, R30, R30 ; BSSY B0, 0x52e0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x52d0 ; DMUL R6, R6, 0.25 ; DADD R24, -R24, R28 ; DSETP.NEU.AND P0, PT, R26, 1, PT ; DADD R24, R24, R32 ; FSEL R26, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R27, R7, 1.625, P0 ; DADD R10, -RZ, |R24| ; DADD R26, R46, R26 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R24.reuse, 2 ; BSSY B0, 0x5410 ; MOV R7, R5 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x5400 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x53f0 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R5, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x5400 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x5400 ; DADD R6, R24, 2 ; BSYNC B0 ; DMUL R6, R6, c[0x2][0x28] ; BSSY B0, 0x54d0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x54c0 ; DADD R28, R28, -R32 ; DSETP.NEU.AND P0, PT, R24, 1, PT ; DADD R10, -RZ, |R28| ; FSEL R24, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R25, R7, 1.8854166269302368164, P0 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R28.reuse, 2 ; BSSY B0, 0x5600 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R28, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x55f0 ; DSETP.GTU.AND P0, PT, |R28|, +INF , PT ; @P0 BRA 0x55e0 ; ISETP.NE.AND P0, PT, R28, RZ, PT ; LOP3.LUT R5, R29, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x55f0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; MOV R7, 0x7ff00000 ; BRA 0x55f0 ; DADD R6, R28, 2 ; BSYNC B0 ; DADD R8, R32, R32 ; BSSY B0, 0x56f0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DMUL R6, R6, 0.25 ; DADD R30, -R8, R30 ; MOV R8, 0x56e0 ; DSETP.NEU.AND P0, PT, R28, 1, PT ; DADD R30, R30, R34 ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R10, -RZ, |R30| ; DADD R24, R24, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R30.reuse, 2 ; BSSY B0, 0x5820 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R30, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x5810 ; DSETP.GTU.AND P0, PT, |R30|, +INF , PT ; @P0 BRA 0x5800 ; ISETP.NE.AND P0, PT, R30, RZ, PT ; LOP3.LUT R5, R31, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x5810 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x5810 ; DADD R6, R30, 2 ; BSYNC B0 ; DFMA R32, R32, -4, R40 ; BSSY B0, 0x58f0 ; MOV R5, 0x40000000 ; DMUL R6, R6, c[0x2][0x28] ; MOV R8, 0x58e0 ; DADD R34, R32, R34 ; DSETP.NEU.AND P0, PT, R30, 1, PT ; DADD R10, -RZ, |R34| ; FSEL R28, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R29, R7, 1.8854166269302368164, P0 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R34.reuse, 2 ; BSSY B0, 0x5a20 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R34, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x5a10 ; DSETP.GTU.AND P0, PT, |R34|, +INF , PT ; @P0 BRA 0x5a00 ; ISETP.NE.AND P0, PT, R34, RZ, PT ; LOP3.LUT R5, R35, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x5a10 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x5a10 ; DADD R6, R34, 2 ; BSYNC B0 ; DMUL R6, R6, 0.25 ; BSSY B0, 0x5af0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x5ae0 ; DSETP.NEU.AND P0, PT, R34, 1, PT ; DADD R26, R26, c[0x2][0x30] ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R10, -RZ, |R26| ; DADD R28, R28, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R26.reuse, 2 ; BSSY B0, 0x5c20 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R26, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x5c10 ; DSETP.GTU.AND P0, PT, |R26|, +INF , PT ; @P0 BRA 0x5c00 ; ISETP.NE.AND P0, PT, R26, RZ, PT ; LOP3.LUT R5, R27, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x5c10 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x5c10 ; DADD R6, R26, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0x5d80 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x38] ; DFMA R30, R10, -R6, c[0x2][0x38] ; DFMA R8, R8, R30, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0x5d70 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x5d60 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, -0x66666666 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fb99999 ; CALL.REL.NOINC 0x13360 ; MOV R9, R5 ; BSYNC B2 ; DADD R24, R24, c[0x2][0x30] ; BSSY B0, 0x5e30 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R26, 1, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R24| ; FSEL R26, R8, -1.5881868392106855534e-23, P0 ; FSEL R27, R9, 1.4499999284744262695, P0 ; MOV R8, 0x5e20 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R24.reuse, 2 ; BSSY B0, 0x5f60 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x5f50 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x5f40 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R5, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x5f50 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x5f50 ; DADD R6, R24, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0x60c0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x40] ; DFMA R30, R10, -R6, c[0x2][0x40] ; DFMA R8, R8, R30, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0x60b0 ; MOV R8, R6 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; MOV R6, 0x60a0 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fe33333 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DADD R28, R28, c[0x2][0x30] ; BSSY B0, 0x6170 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R24, 1, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R28| ; FSEL R24, R8, 4.172325063223070174e-08, P0 ; FSEL R25, R9, 1.7749999761581420898, P0 ; MOV R8, 0x6160 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R28.reuse, 2 ; BSSY B0, 0x62a0 ; MOV R7, R5 ; DSETP.NEU.AND P0, PT, R28, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x6290 ; DSETP.GTU.AND P0, PT, |R28|, +INF , PT ; @P0 BRA 0x6280 ; ISETP.NE.AND P0, PT, R28, RZ, PT ; LOP3.LUT R5, R29, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x6290 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x6290 ; DADD R6, R28, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0x6400 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x48] ; DFMA R30, R10, -R6, c[0x2][0x48] ; DFMA R8, R8, R30, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0x63f0 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x63e0 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; MOV R7, 0x3fd33333 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DSETP.NEU.AND P0, PT, R28, 1, PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R27|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x65d0 ; DADD R28, R26, R24 ; FSEL R30, R8, 4.172325063223070174e-08, P0 ; FSEL R31, R9, 1.6499999761581420898, P0 ; DADD R28, R28, R30 ; MUFU.RCP64H R7, R29 ; DFMA R8, -R28, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R28, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R32, R6, R26 ; DFMA R8, -R28, R32, R26 ; DFMA R32, R6, R8, R32 ; FFMA R5, RZ, R29, R33 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x65c0 ; IMAD.MOV.U32 R10, RZ, RZ, R26 ; MOV R6, 0x65a0 ; IMAD.MOV.U32 R7, RZ, RZ, R27 ; IMAD.MOV.U32 R8, RZ, RZ, R28 ; IMAD.MOV.U32 R5, RZ, RZ, R29 ; CALL.REL.NOINC 0x13360 ; MOV R32, R8 ; IMAD.MOV.U32 R33, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R29 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R25|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x6770 ; DFMA R8, -R28, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R28, R8, 1 ; DFMA R8, R8, R6, R8 ; IMAD.MOV.U32 R6, RZ, RZ, R24 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; DMUL R26, R8, R6 ; DFMA R6, -R28, R26, R6 ; DFMA R26, R8, R6, R26 ; FFMA R5, RZ, R29, R27 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x6760 ; IMAD.MOV.U32 R10, RZ, RZ, R24 ; MOV R8, R28 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; MOV R6, 0x6740 ; IMAD.MOV.U32 R5, RZ, RZ, R29 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R26, RZ, RZ, R8 ; IMAD.MOV.U32 R27, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R29 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R31|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x6900 ; DFMA R8, -R28, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R28, R8, 1 ; DFMA R10, R8, R6, R8 ; IMAD.MOV.U32 R8, RZ, RZ, R30 ; IMAD.MOV.U32 R9, RZ, RZ, R31 ; DMUL R6, R10, R8 ; DFMA R8, -R28, R6, R8 ; DFMA R8, R10, R8, R6 ; FFMA R5, RZ, R29, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x68f0 ; MOV R8, R28 ; IMAD.MOV.U32 R5, RZ, RZ, R29 ; MOV R6, 0x68e0 ; IMAD.MOV.U32 R10, RZ, RZ, R30 ; IMAD.MOV.U32 R7, RZ, RZ, R31 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DMUL R20, R20, R26 ; DFMA R20, R22, R32, R20 ; DFMA R18, R18, R8, R20 ; BSYNC B1 ; S2R R5, SR_TID.X ; ULDC UR4, c[0x0][0x1b0] ; MOV R28, RZ ; UIADD3 UR4, UR4, -0x1, URZ ; S2R R6, SR_CTAID.X ; SHF.L.U64.HI R3, R4.reuse, 0x3, R3 ; IMAD.SHL.U32 R4, R4, 0x8, RZ ; IMAD R26, R6, c[0x0][0x0], R5 ; I2F.F64 R6, UR4 ; IADD3 R8, R26.reuse, 0x1, RZ ; IADD3 R20, R26.reuse, 0x3, RZ ; IADD3 R10, R26, 0x2, RZ ; I2F.F64 R8, R8 ; IADD3 R16, R26.reuse, -0x1, RZ ; IADD3 R22, R26.reuse, -0x2, RZ ; IADD3 R26, R26, -0x3, RZ ; I2F.F64 R20, R20 ; I2F.F64 R10, R10 ; DSETP.MAX.AND P2, P5, RZ, R8, PT ; IMAD.MOV.U32 R23, RZ, RZ, R8 ; IMAD.MOV.U32 R25, RZ, RZ, R9 ; DSETP.MAX.AND P1, P0, RZ, R20, PT ; IMAD.MOV.U32 R29, RZ, RZ, R20 ; I2F.F64 R8, R16 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; IMAD.MOV.U32 R5, RZ, RZ, R21 ; DSETP.MAX.AND P4, P3, RZ, R10, PT ; MOV R27, R10 ; IMAD.MOV.U32 R24, RZ, RZ, R11 ; SEL R20, R20, R23, P2 ; CS2R R10, SRZ ; I2F.F64 R22, R22 ; FSEL R21, R10, R25, P2 ; SEL R10, R10, R27, P4 ; I2F.F64 R26, R26 ; @P5 LOP3.LUT R21, R25, 0x80000, RZ, 0xfc, !PT ; DSETP.MAX.AND P5, P2, RZ, R8, PT ; FSEL R11, R11, R24, P4 ; IMAD.MOV.U32 R25, RZ, RZ, R8 ; @P3 LOP3.LUT R11, R24, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; DSETP.MAX.AND P3, P4, RZ, R22, PT ; IMAD.MOV.U32 R31, RZ, RZ, R22 ; MOV R16, R23 ; IMAD.MOV.U32 R22, RZ, RZ, RZ ; DSETP.GT.AND P6, PT, R20, R6, PT ; FSEL R23, R8, R9, P5 ; SEL R8, R8, R29, P1 ; SEL R22, R22, R25, P5 ; IMAD.MOV.U32 R33, RZ, RZ, R26 ; FSEL R24, R6, R20, P6 ; IMAD.MOV.U32 R20, RZ, RZ, RZ ; FSEL R25, R7, R21, P6 ; DSETP.MAX.AND P6, P5, RZ, R26, PT ; @P2 LOP3.LUT R23, R9, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R9, RZ, RZ, RZ ; SEL R20, R20, R31, P3 ; IMAD.MOV.U32 R30, RZ, RZ, R27 ; DSETP.GT.AND P2, PT, R10, R6, PT ; CS2R R26, SRZ ; FSEL R21, R9, R16, P3 ; @P4 LOP3.LUT R21, R16, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P3, PT, R22, R6.reuse, PT ; FSEL R9, R28, R5, P1 ; F2I.F64.TRUNC R16, R24 ; FSEL R27, R27, R30, P6 ; DSETP.GT.AND P1, PT, R20, R6, PT ; SEL R26, R26, R33, P6 ; @P0 LOP3.LUT R9, R5, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; @P5 LOP3.LUT R27, R30, 0x80000, RZ, 0xfc, !PT ; FSEL R24, R6.reuse, R20, P1 ; FSEL R25, R7.reuse, R21, P1 ; DSETP.GT.AND P0, PT, R8, R6.reuse, PT ; FSEL R10, R6.reuse, R10, P2 ; FSEL R11, R7.reuse, R11, P2 ; DSETP.GT.AND P1, PT, R26, R6, PT ; FSEL R22, R6.reuse, R22, P3 ; F2I.F64.TRUNC R24, R24 ; FSEL R20, R6, R8, P0 ; DSETP.GEU.AND P2, PT, |R36|, |R38|, PT ; FSEL R21, R7, R9, P0 ; FSEL R26, R6, R26, P1 ; FSEL R27, R7, R27, P1 ; F2I.F64.TRUNC R28, R10 ; FSEL R8, R18, R14, !P2 ; FSEL R9, R19, R15, !P2 ; FSEL R23, R7, R23, P3 ; IADD3 R14, P1, R4.reuse, c[0x0][0x190], RZ ; F2I.F64.TRUNC R26, R26 ; IADD3 R6, P2, R4, c[0x0][0x198], RZ ; IADD3 R10, P0, R4, c[0x0][0x160], RZ ; IADD3.X R15, R3.reuse, c[0x0][0x194], RZ, P1, !PT ; IADD3.X R11, R3.reuse, c[0x0][0x164], RZ, P0, !PT ; F2I.F64.TRUNC R22, R22 ; IADD3.X R7, R3, c[0x0][0x19c], RZ, P2, !PT ; STG.E.64 [R10.64], R8 ; F2I.F64.TRUNC R20, R20 ; LDG.E.64 R14, [R14.64] ; LDG.E.64 R6, [R6.64] ; IMAD R16, R17, c[0x0][0x1b0], R16 ; IMAD R18, R17.reuse, c[0x0][0x1b0], R28 ; IMAD R25, R17.reuse, c[0x0][0x1b0], R26 ; IMAD R23, R17.reuse, c[0x0][0x1b0], R24 ; IMAD R40, R17.reuse, c[0x0][0x1b0], R22 ; IMAD R20, R17, c[0x0][0x1b0], R20 ; IMAD.WIDE R24, R25, R5, c[0x0][0x178] ; IMAD.WIDE R22, R23, R5.reuse, c[0x0][0x178] ; LDG.E.64 R24, [R24.64] ; IMAD.WIDE R40, R40, R5.reuse, c[0x0][0x178] ; LDG.E.64 R22, [R22.64] ; IMAD.WIDE R38, R16, R5.reuse, c[0x0][0x178] ; LDG.E.64 R40, [R40.64] ; IMAD.WIDE R18, R18, R5, c[0x0][0x178] ; LDG.E.64 R38, [R38.64] ; IMAD.WIDE R20, R20, R5, c[0x0][0x178] ; LDG.E.64 R18, [R18.64] ; LDG.E.64 R20, [R20.64] ; BSSY B1, 0xcdf0 ; DSETP.GEU.AND P1, PT, R14, c[0x0][0x1c8], PT ; DSETP.GEU.AND P0, PT, R6, c[0x0][0x1c8], PT ; @P0 BRA P1, 0x8ce0 ; DSETP.GEU.AND P1, PT, R14, c[0x0][0x1c8], PT ; IMAD.MOV.U32 R36, RZ, RZ, c[0x0][0x1c8] ; BSSY B2, 0x74b0 ; IMAD.MOV.U32 R37, RZ, RZ, c[0x0][0x1cc] ; IMAD.MOV.U32 R48, RZ, RZ, c[0x0][0x1c8] ; IMAD.MOV.U32 R49, RZ, RZ, c[0x0][0x1cc] ; DADD R50, R36, c[0x0][0x1c8] ; IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; @!P0 IMAD.MOV.U32 R24, RZ, RZ, R22 ; DMUL R46, R36.reuse, -2 ; @!P0 IMAD.MOV.U32 R25, RZ, RZ, R23 ; @!P0 IMAD.MOV.U32 R12, RZ, RZ, R6 ; @P1 DMUL R8, R36.reuse, 3 ; @!P0 IMAD.MOV.U32 R13, RZ, RZ, R7 ; @P1 MOV R48, R50 ; @P1 IMAD.MOV.U32 R49, RZ, RZ, R51 ; @P0 DMUL R36, R36, -3 ; @P1 IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x1c8] ; @P1 IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x1cc] ; @!P0 IMAD.MOV.U32 R22, RZ, RZ, R40 ; @!P0 MOV R37, R47 ; @P1 IMAD.MOV.U32 R50, RZ, RZ, R8 ; @P1 IMAD.MOV.U32 R51, RZ, RZ, R9 ; @!P0 IMAD.MOV.U32 R36, RZ, RZ, R46 ; @!P0 DADD R46, -RZ, -c[0x0][0x1c8] ; @!P0 IMAD.MOV.U32 R23, RZ, RZ, R41 ; DADD R8, -R48, R50 ; MUFU.RCP64H R11, R9 ; DFMA R16, -R8, R10, 1 ; DFMA R26, R16, R16, R16 ; IMAD.MOV.U32 R16, RZ, RZ, R38 ; @P1 MOV R16, R18 ; IMAD.MOV.U32 R17, RZ, RZ, R39 ; DFMA R26, R10, R26, R10 ; @P1 IMAD.MOV.U32 R17, RZ, RZ, R19 ; @P1 IMAD.MOV.U32 R18, RZ, RZ, R20 ; @P1 IMAD.MOV.U32 R19, RZ, RZ, R21 ; DFMA R10, -R8, R26, 1 ; DADD R28, -R16, R18 ; DFMA R10, R26, R10, R26 ; @P0 IMAD.MOV.U32 R26, RZ, RZ, R40 ; @P0 IMAD.MOV.U32 R27, RZ, RZ, R41 ; @!P0 CS2R R26, SRZ ; DMUL R20, R28, R10 ; FSETP.GEU.AND P3, PT, |R29|, 6.5827683646048100446e-37, PT ; DFMA R18, -R8, R20, R28 ; DFMA R20, R10, R18, R20 ; CS2R R18, SRZ ; @P1 MOV R18, R38 ; @P1 IMAD.MOV.U32 R19, RZ, RZ, R39 ; FFMA R5, RZ, R9, R21 ; FSETP.GT.AND P2, PT, |R5|, 1.469367938527859385e-39, PT ; @P2 BRA P3, 0x74a0 ; IMAD.MOV.U32 R10, RZ, RZ, R28 ; MOV R6, 0x7480 ; IMAD.MOV.U32 R7, RZ, RZ, R29 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; CALL.REL.NOINC 0x13360 ; MOV R20, R8 ; IMAD.MOV.U32 R21, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, R48, -R14 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x7640 ; DADD R28, R16, -R18 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R29|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R16, R28, R6 ; DFMA R10, -R8, R16, R28 ; DFMA R16, R6, R10, R16 ; FFMA R5, RZ, R9, R17 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7630 ; IMAD.MOV.U32 R10, RZ, RZ, R28 ; MOV R6, 0x7610 ; IMAD.MOV.U32 R7, RZ, RZ, R29 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R16, RZ, RZ, R8 ; MOV R17, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R15 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R44, R18 ; BSSY B2, 0x77c0 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R14, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R14, 1 ; DFMA R6, R8, R6, R8 ; DMUL R34, R10, R6 ; DFMA R8, R34, -R14, R10 ; DFMA R34, R6, R8, R34 ; FFMA R5, RZ, R15, R35 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x77b0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x7790 ; IMAD.MOV.U32 R8, RZ, RZ, R14 ; IMAD.MOV.U32 R5, RZ, RZ, R15 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R34, RZ, RZ, R8 ; IMAD.MOV.U32 R35, RZ, RZ, R5 ; BSYNC B2 ; DADD R18, RZ, R12 ; MOV R6, 0x1 ; BSSY B2, 0x7950 ; DADD R10, R44, -R26 ; MUFU.RCP64H R7, R19 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R18, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R18, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R32, R10, R6 ; DFMA R8, -R18, R32, R10 ; DFMA R32, R6, R8, R32 ; FFMA R5, RZ, R19, R33 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7940 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x7920 ; IMAD.MOV.U32 R8, RZ, RZ, R18 ; IMAD.MOV.U32 R5, RZ, RZ, R19 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R32, RZ, RZ, R8 ; IMAD.MOV.U32 R33, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, -R46, -R12 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x7ae0 ; DADD R26, -R22, R26 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R27|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R30, R26, R6 ; DFMA R10, -R8, R30, R26 ; DFMA R30, R6, R10, R30 ; FFMA R5, RZ, R9, R31 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7ad0 ; MOV R10, R26 ; IMAD.MOV.U32 R7, RZ, RZ, R27 ; MOV R6, 0x7ab0 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; IMAD.MOV.U32 R31, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, -R36, R46 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x7c70 ; DADD R22, R22, -R24 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R28, R22, R6 ; DFMA R10, -R8, R28, R22 ; DFMA R28, R6, R10, R28 ; FFMA R5, RZ, R9, R29 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7c60 ; IMAD.MOV.U32 R10, RZ, RZ, R22 ; MOV R7, R23 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; MOV R6, 0x7c40 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R28, RZ, RZ, R8 ; IMAD.MOV.U32 R29, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, R50, -R14 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x7e00 ; DADD R20, -R16, R20 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R26, R20, R6 ; DFMA R10, -R8, R26, R20 ; DFMA R26, R6, R10, R26 ; FFMA R5, RZ, R9, R27 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7df0 ; IMAD.MOV.U32 R10, RZ, RZ, R20 ; MOV R5, R9 ; IMAD.MOV.U32 R7, RZ, RZ, R21 ; MOV R6, 0x7dd0 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R26, RZ, RZ, R8 ; IMAD.MOV.U32 R27, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R49 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R34, R16 ; BSSY B2, 0x7f80 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R48, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R48, 1 ; DFMA R6, R8, R6, R8 ; DMUL R24, R10, R6 ; DFMA R8, R24, -R48, R10 ; DFMA R24, R6, R8, R24 ; FFMA R5, RZ, R49, R25 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x7f70 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x7f50 ; IMAD.MOV.U32 R8, RZ, RZ, R48 ; IMAD.MOV.U32 R5, RZ, RZ, R49 ; CALL.REL.NOINC 0x13360 ; MOV R24, R8 ; IMAD.MOV.U32 R25, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, R14, R12 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x8110 ; DADD R16, -R32, R34 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R17|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R22, R16, R6 ; DFMA R10, -R8, R22, R16 ; DFMA R22, R6, R10, R22 ; FFMA R5, RZ, R9, R23 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x8100 ; IMAD.MOV.U32 R10, RZ, RZ, R16 ; MOV R6, 0x80e0 ; IMAD.MOV.U32 R7, RZ, RZ, R17 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R22, RZ, RZ, R8 ; MOV R23, R5 ; BSYNC B2 ; DADD R16, RZ, -R46 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x82a0 ; DADD R10, -R30, R32 ; MUFU.RCP64H R7, R17 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R16, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R16, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R20, R10, R6 ; DFMA R8, -R16, R20, R10 ; DFMA R20, R6, R8, R20 ; FFMA R5, RZ, R17, R21 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x8290 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x8270 ; IMAD.MOV.U32 R8, RZ, RZ, R16 ; IMAD.MOV.U32 R5, RZ, RZ, R17 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R20, RZ, RZ, R8 ; IMAD.MOV.U32 R21, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, -R36, -R12 ; MOV R6, 0x1 ; BSSY B2, 0x8430 ; DADD R30, -R28, R30 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R31|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R28, R30, R6 ; DFMA R10, -R8, R28, R30 ; DFMA R28, R6, R10, R28 ; FFMA R5, RZ, R9, R29 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x8420 ; IMAD.MOV.U32 R10, RZ, RZ, R30 ; MOV R6, 0x8400 ; IMAD.MOV.U32 R7, RZ, RZ, R31 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R28, RZ, RZ, R8 ; IMAD.MOV.U32 R29, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R51 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R24, R26 ; BSSY B2, 0x85b0 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R50, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R50, 1 ; DFMA R6, R8, R6, R8 ; DMUL R26, R10, R6 ; DFMA R8, R26, -R50, R10 ; DFMA R26, R6, R8, R26 ; FFMA R5, RZ, R51, R27 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x85a0 ; MOV R7, R11 ; IMAD.MOV.U32 R8, RZ, RZ, R50 ; MOV R6, 0x8580 ; IMAD.MOV.U32 R5, RZ, RZ, R51 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R26, RZ, RZ, R8 ; IMAD.MOV.U32 R27, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, R48, R12 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x8740 ; DADD R30, -R22, R24 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R31|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R12, R30, R6 ; DFMA R10, -R8, R12, R30 ; DFMA R12, R6, R10, R12 ; FFMA R5, RZ, R9, R13 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x8730 ; IMAD.MOV.U32 R10, RZ, RZ, R30 ; MOV R7, R31 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; MOV R6, 0x8710 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R12, RZ, RZ, R8 ; IMAD.MOV.U32 R13, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, -R46, R14 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x88d0 ; DADD R46, -R20, R22 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R47|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R30, R46, R6 ; DFMA R10, -R8, R30, R46 ; DFMA R30, R6, R10, R30 ; FFMA R5, RZ, R9, R31 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x88c0 ; IMAD.MOV.U32 R10, RZ, RZ, R46 ; MOV R5, R9 ; IMAD.MOV.U32 R7, RZ, RZ, R47 ; MOV R6, 0x88a0 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; IMAD.MOV.U32 R31, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, RZ, -R36 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x8a60 ; DADD R36, -R28, R20 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R37|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R10, R36, R6 ; DFMA R28, -R8, R10, R36 ; DFMA R6, R6, R28, R10 ; FFMA R5, RZ, R9, R7 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x8a50 ; IMAD.MOV.U32 R10, RZ, RZ, R36 ; MOV R6, 0x8a30 ; IMAD.MOV.U32 R7, RZ, RZ, R37 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; CALL.REL.NOINC 0x13360 ; MOV R6, R8 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; BSYNC B2 ; DMUL R8, R20, R22 ; DSETP.GEU.AND P0, PT, |R30|, |R6|, PT ; DSETP.GEU.AND P4, PT, R8, RZ, PT ; FSEL R8, R30, R6, !P0 ; FSEL R9, R31, R7, !P0 ; DMUL R10, R22, R24 ; DMUL R6, R18, R16 ; DADD R14, RZ, -R14 ; DSETP.GEU.AND P0, PT, |R30|, |R12|, PT ; DADD R48, RZ, -R48 ; DSETP.GEU.AND P2, PT, |R12|, |R26|, PT ; DSETP.GEU.AND P5, PT, R10, RZ, PT ; FSEL R16, R12, R26, !P2 ; DMUL R6, R6, R8 ; FSEL R17, R13, R27, !P2 ; FSEL R10, R30, R12, !P0 ; DSETP.GEU.AND P1, PT, |R20|, |R22|, PT ; FSEL R11, R31, R13, !P0 ; DSETP.GEU.AND P3, PT, |R22|, |R24|, PT ; FSEL R5, R20, R22, !P1 ; DMUL R48, R14, R48 ; FSEL R20, R21, R23, !P1 ; FSEL R12, R22, R24, !P3 ; DMUL R8, R18, R14 ; FSEL R22, R23, R25, !P3 ; FSEL R12, R12, RZ, P5 ; DMUL R48, R48, R16 ; FSEL R13, R22, RZ, P5 ; DMUL R8, R8, R10 ; FSEL R10, R5, RZ, P4 ; FSEL R11, R20, RZ, P4 ; DFMA R14, R14, R12, R34 ; DFMA R18, R18, R10, R32 ; FSEL R20, R6, R8, !P1 ; FSEL R21, R7, R9, !P1 ; FSEL R26, R8, R48, !P3 ; FSEL R27, R9, R49, !P3 ; DADD R20, R18, R20 ; DADD R26, R14, R26 ; BRA 0xcde0 ; MUFU.RCP64H R7, c[0x0][0x1cc] ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x1c8] ; BSSY B2, 0x8e80 ; IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x1cc] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R8, R6, -R10, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R10, 1 ; DADD R10, R22, -R24 ; DFMA R6, R8, R6, R8 ; DMUL R12, R10, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R12, -c[0x0][0x1c8], R10 ; DFMA R12, R6, R8, R12 ; FFMA R5, RZ, c[0x0][0x1cc], R13 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x8e70 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R5, c[0x0][0x1cc] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c8] ; MOV R6, 0x8e50 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R12, RZ, RZ, R8 ; IMAD.MOV.U32 R13, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1cc] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c8] ; BSSY B2, 0x9020 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1cc] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DADD R6, -R22, R40 ; DFMA R8, R10, -R8, 1 ; DFMA R10, R10, R8, R10 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; DMUL R36, R10, R6 ; DFMA R8, R36, -c[0x0][0x1c8], R6 ; DFMA R36, R10, R8, R36 ; FFMA R5, RZ, c[0x0][0x1cc], R37 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x9010 ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; MOV R8, c[0x0][0x1c8] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1cc] ; MOV R6, 0x8ff0 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R36, RZ, RZ, R8 ; IMAD.MOV.U32 R37, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1cc] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c8] ; BSSY B2, 0x91c0 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1cc] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DADD R6, R44, -R40 ; DFMA R8, R10, -R8, 1 ; DFMA R10, R10, R8, R10 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; DMUL R34, R10, R6 ; DFMA R8, R34, -c[0x0][0x1c8], R6 ; DFMA R34, R10, R8, R34 ; FFMA R5, RZ, c[0x0][0x1cc], R35 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x91b0 ; MOV R10, R6 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c8] ; MOV R6, 0x9190 ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1cc] ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R34, RZ, RZ, R8 ; IMAD.MOV.U32 R35, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1cc] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c8] ; MOV R6, 0x1 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1cc] ; BSSY B2, 0x9360 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DADD R6, -R44, R38 ; DFMA R8, R10, -R8, 1 ; DFMA R10, R10, R8, R10 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; DMUL R32, R10, R6 ; DFMA R8, R32, -c[0x0][0x1c8], R6 ; DFMA R32, R10, R8, R32 ; FFMA R5, RZ, c[0x0][0x1cc], R33 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x9350 ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; MOV R6, 0x9330 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c8] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1cc] ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R32, RZ, RZ, R8 ; IMAD.MOV.U32 R33, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1cc] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c8] ; MOV R9, c[0x0][0x1cc] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0x9500 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, -R38, R18 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R30, R8, R10 ; DFMA R6, R30, -c[0x0][0x1c8], R10 ; DFMA R30, R8, R6, R30 ; FFMA R5, RZ, c[0x0][0x1cc], R31 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x94f0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x94d0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c8] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1cc] ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; IMAD.MOV.U32 R31, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1cc] ; MOV R8, c[0x0][0x1c8] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1cc] ; BSSY B2, 0x96a0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, R20, -R18 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R28, R8, R10 ; DFMA R6, R28, -c[0x0][0x1c8], R10 ; DFMA R28, R8, R6, R28 ; FFMA R5, RZ, c[0x0][0x1cc], R29 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x9690 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0x9670 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1c8] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1cc] ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R28, RZ, RZ, R8 ; MOV R29, R5 ; BSYNC B2 ; DADD R8, R36.reuse, R36 ; BSSY B0, 0x97d0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DMUL R26, R36, c[0x2][0x18] ; DADD R8, -R8, R12 ; DMUL R6, R36, c[0x2][0x0] ; DADD R14, R8, R34 ; MOV R8, 0x97c0 ; DMUL R22, R32, c[0x2][0x20] ; DFMA R16, R34, c[0x2][0x20], -R26 ; DFMA R6, R12, c[0x2][0x8], R6 ; DMUL R24, R32, c[0x2][0x8] ; DADD R10, -RZ, |R14| ; DFMA R20, R34, c[0x2][0x8], R22 ; DFMA R16, R32, c[0x2][0x8], R16 ; DFMA R18, R34, c[0x2][0x10], R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R14.reuse, 2 ; BSSY B0, 0x9910 ; IMAD.MOV.U32 R50, RZ, RZ, R6 ; DSETP.NEU.AND P0, PT, R14, RZ, PT ; IMAD.MOV.U32 R51, RZ, RZ, R5 ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R50, SRZ ; @P1 BRA 0x9900 ; DSETP.GTU.AND P0, PT, |R14|, +INF , PT ; @P0 BRA 0x98f0 ; ISETP.NE.AND P0, PT, R14, RZ, PT ; LOP3.LUT R5, R15, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x9900 ; IMAD.MOV.U32 R50, RZ, RZ, 0x0 ; IMAD.MOV.U32 R51, RZ, RZ, 0x7ff00000 ; BRA 0x9900 ; DADD R50, R14, 2 ; BSYNC B0 ; DFMA R48, R36, -4, R12 ; BSSY B0, 0x99b0 ; MOV R6, RZ ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DMUL R46, R34, 3 ; MOV R8, 0x99a0 ; DADD R48, R48, R46 ; DADD R10, -RZ, |R48| ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R48.reuse, 2 ; BSSY B0, 0x9b20 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P1, PT, R48, RZ, PT ; DMUL R10, R50, c[0x2][0x28] ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; DSETP.NEU.AND P0, PT, R14, 1, PT ; ISETP.NE.AND P2, PT, R8, 0x7ff00000, PT ; FSEL R50, R10, 1.46601546874880000000e+13, P0 ; @!P1 CS2R R6, SRZ ; FSEL R51, R11, 1.8854166269302368164, P0 ; @P2 BRA 0x9b10 ; DSETP.GTU.AND P0, PT, |R48|, +INF , PT ; @P0 BRA 0x9b00 ; ISETP.NE.AND P0, PT, R48, RZ, PT ; LOP3.LUT R5, R49, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x9b10 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x9b10 ; DADD R6, R48, 2 ; BSYNC B0 ; DADD R14, R34, R34 ; BSSY B0, 0x9c10 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x9c00 ; DMUL R6, R6, 0.25 ; DADD R12, -R14, R36 ; DSETP.NEU.AND P0, PT, R48, 1, PT ; DADD R12, R12, R32 ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R10, -RZ, |R12| ; DADD R50, R50, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R12.reuse, 2 ; BSSY B0, 0x9d40 ; MOV R7, R5 ; DSETP.NEU.AND P0, PT, R12, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x9d30 ; DSETP.GTU.AND P0, PT, |R12|, +INF , PT ; @P0 BRA 0x9d20 ; ISETP.NE.AND P0, PT, R12, RZ, PT ; LOP3.LUT R5, R13, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x9d30 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x9d30 ; DADD R6, R12, 2 ; BSYNC B0 ; DMUL R6, R6, c[0x2][0x28] ; BSSY B0, 0x9e00 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x9df0 ; DADD R48, -R32, R36 ; DSETP.NEU.AND P0, PT, R12, 1, PT ; DADD R10, -RZ, |R48| ; FSEL R68, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R69, R7, 1.8854166269302368164, P0 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R48.reuse, 2 ; BSSY B0, 0x9f30 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R48, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x9f20 ; DSETP.GTU.AND P0, PT, |R48|, +INF , PT ; @P0 BRA 0x9f10 ; ISETP.NE.AND P0, PT, R48, RZ, PT ; LOP3.LUT R5, R49, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0x9f20 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; MOV R7, 0x7ff00000 ; BRA 0x9f20 ; DADD R6, R48, 2 ; BSYNC B0 ; DADD R12, R32, R32 ; BSSY B0, 0xa020 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0xa010 ; DMUL R6, R6, 0.25 ; DADD R66, -R12, R34 ; DSETP.NEU.AND P0, PT, R48, 1, PT ; DADD R66, R66, R30 ; FSEL R48, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R49, R7, 1.625, P0 ; DADD R10, -RZ, |R66| ; DADD R48, R68, R48 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R66.reuse, 2 ; BSSY B0, 0xa150 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R66, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xa140 ; DSETP.GTU.AND P0, PT, |R66|, +INF , PT ; @P0 BRA 0xa130 ; ISETP.NE.AND P0, PT, R66, RZ, PT ; LOP3.LUT R5, R67, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xa140 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xa140 ; DADD R6, R66, 2 ; BSYNC B0 ; DFMA R46, R32, -4, R46 ; BSSY B0, 0xa220 ; MOV R5, 0x40000000 ; DMUL R6, R6, c[0x2][0x28] ; MOV R8, 0xa210 ; DADD R46, R46, R30 ; DSETP.NEU.AND P0, PT, R66, 1, PT ; DADD R10, -RZ, |R46| ; FSEL R66, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R67, R7, 1.8854166269302368164, P0 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R46.reuse, 2 ; BSSY B0, 0xa350 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R46, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xa340 ; DSETP.GTU.AND P0, PT, |R46|, +INF , PT ; @P0 BRA 0xa330 ; ISETP.NE.AND P0, PT, R46, RZ, PT ; LOP3.LUT R5, R47, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xa340 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xa340 ; DADD R6, R46, 2 ; BSYNC B0 ; DMUL R6, R6, 0.25 ; BSSY B0, 0xa420 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0xa410 ; DSETP.NEU.AND P0, PT, R46, 1, PT ; DADD R50, R50, c[0x2][0x30] ; FSEL R46, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R47, R7, 1.625, P0 ; DADD R10, -RZ, |R50| ; DADD R46, R66, R46 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R50.reuse, 2 ; BSSY B0, 0xa550 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R50, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xa540 ; DSETP.GTU.AND P0, PT, |R50|, +INF , PT ; @P0 BRA 0xa530 ; ISETP.NE.AND P0, PT, R50, RZ, PT ; LOP3.LUT R5, R51, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xa540 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xa540 ; DADD R6, R50, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0xa6b0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x38] ; DFMA R52, R10, -R6, c[0x2][0x38] ; DFMA R8, R8, R52, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0xa6a0 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0xa690 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, -0x66666666 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fb99999 ; CALL.REL.NOINC 0x13360 ; MOV R9, R5 ; BSYNC B2 ; DADD R48, R48, c[0x2][0x30] ; BSSY B0, 0xa760 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R50, 1, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R48| ; FSEL R50, R8, -1.5881868392106855534e-23, P0 ; FSEL R51, R9, 1.4499999284744262695, P0 ; MOV R8, 0xa750 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R48.reuse, 2 ; BSSY B0, 0xa890 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R48, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xa880 ; DSETP.GTU.AND P0, PT, |R48|, +INF , PT ; @P0 BRA 0xa870 ; ISETP.NE.AND P0, PT, R48, RZ, PT ; LOP3.LUT R5, R49, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xa880 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xa880 ; DADD R6, R48, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0xa9f0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x40] ; DFMA R52, R10, -R6, c[0x2][0x40] ; DFMA R8, R8, R52, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0xa9e0 ; MOV R8, R6 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; MOV R6, 0xa9d0 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fe33333 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DADD R46, R46, c[0x2][0x30] ; BSSY B0, 0xaaa0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R48, 1, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R46| ; FSEL R48, R8, 4.172325063223070174e-08, P0 ; FSEL R49, R9, 1.7749999761581420898, P0 ; MOV R8, 0xaa90 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R46.reuse, 2 ; BSSY B0, 0xabd0 ; MOV R7, R5 ; DSETP.NEU.AND P0, PT, R46, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xabc0 ; DSETP.GTU.AND P0, PT, |R46|, +INF , PT ; @P0 BRA 0xabb0 ; ISETP.NE.AND P0, PT, R46, RZ, PT ; LOP3.LUT R5, R47, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xabc0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xabc0 ; DADD R6, R46, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0xad30 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x48] ; DFMA R52, R10, -R6, c[0x2][0x48] ; DFMA R8, R8, R52, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0xad20 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0xad10 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; MOV R7, 0x3fd33333 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DSETP.NEU.AND P0, PT, R46, 1, PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R51|, 6.5827683646048100446e-37, PT ; BSSY B2, 0xaf00 ; DADD R46, R50, R48 ; FSEL R64, R8, 4.172325063223070174e-08, P0 ; FSEL R65, R9, 1.6499999761581420898, P0 ; DADD R46, R46, R64 ; MUFU.RCP64H R7, R47 ; DFMA R8, -R46, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R46, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R66, R6, R50 ; DFMA R8, -R46, R66, R50 ; DFMA R66, R6, R8, R66 ; FFMA R5, RZ, R47, R67 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xaef0 ; IMAD.MOV.U32 R10, RZ, RZ, R50 ; MOV R6, 0xaed0 ; IMAD.MOV.U32 R7, RZ, RZ, R51 ; IMAD.MOV.U32 R8, RZ, RZ, R46 ; IMAD.MOV.U32 R5, RZ, RZ, R47 ; CALL.REL.NOINC 0x13360 ; MOV R66, R8 ; IMAD.MOV.U32 R67, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R47 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R49|, 6.5827683646048100446e-37, PT ; BSSY B2, 0xb0a0 ; DFMA R8, -R46, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R46, R8, 1 ; DFMA R8, R8, R6, R8 ; IMAD.MOV.U32 R6, RZ, RZ, R48 ; IMAD.MOV.U32 R7, RZ, RZ, R49 ; DMUL R50, R8, R6 ; DFMA R6, -R46, R50, R6 ; DFMA R50, R8, R6, R50 ; FFMA R5, RZ, R47, R51 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xb090 ; IMAD.MOV.U32 R10, RZ, RZ, R48 ; MOV R8, R46 ; IMAD.MOV.U32 R7, RZ, RZ, R49 ; MOV R6, 0xb070 ; IMAD.MOV.U32 R5, RZ, RZ, R47 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R50, RZ, RZ, R8 ; IMAD.MOV.U32 R51, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R47 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R65|, 6.5827683646048100446e-37, PT ; BSSY B2, 0xb230 ; DFMA R8, -R46, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R46, R8, 1 ; DFMA R10, R8, R6, R8 ; IMAD.MOV.U32 R6, RZ, RZ, R64 ; IMAD.MOV.U32 R7, RZ, RZ, R65 ; DMUL R8, R10, R6 ; DFMA R6, -R46, R8, R6 ; DFMA R8, R10, R6, R8 ; FFMA R5, RZ, R47, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xb220 ; MOV R8, R46 ; IMAD.MOV.U32 R5, RZ, RZ, R47 ; MOV R6, 0xb210 ; IMAD.MOV.U32 R10, RZ, RZ, R64 ; IMAD.MOV.U32 R7, RZ, RZ, R65 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DADD R6, R30, R30 ; BSSY B0, 0xb380 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DFMA R24, R34, c[0x2][0x20], R24 ; DADD R6, -R6, R28 ; DMUL R16, R16, R50 ; DADD R26, -R26, R24 ; DADD R24, R6, R32 ; DMUL R6, R30, c[0x2][0x0] ; DFMA R16, R18, R66, R16 ; DFMA R20, R30, c[0x2][0x50], R20 ; DFMA R22, R30, c[0x2][0x50], R22 ; DFMA R6, R28, c[0x2][0x8], R6 ; DFMA R20, R20, R8, R16 ; MOV R8, 0xb370 ; DADD R10, -RZ, |R24| ; DFMA R16, R34, c[0x2][0x8], R22 ; DFMA R18, R32, c[0x2][0x10], R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R24.reuse, 2 ; BSSY B0, 0xb4b0 ; MOV R7, R5 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xb4a0 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0xb490 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R5, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xb4a0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xb4a0 ; DADD R6, R24, 2 ; BSYNC B0 ; DFMA R28, R30, -4, R28 ; BSSY B0, 0xb590 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0xb580 ; DMUL R22, R32, 3 ; DMUL R6, R6, c[0x2][0x28] ; DADD R28, R28, R22 ; DSETP.NEU.AND P0, PT, R24, 1, PT ; DADD R10, -RZ, |R28| ; FSEL R24, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R25, R7, 1.8854166269302368164, P0 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R28.reuse, 2 ; BSSY B0, 0xb6c0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R28, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xb6b0 ; DSETP.GTU.AND P0, PT, |R28|, +INF , PT ; @P0 BRA 0xb6a0 ; ISETP.NE.AND P0, PT, R28, RZ, PT ; LOP3.LUT R5, R29, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xb6b0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; MOV R7, 0x7ff00000 ; BRA 0xb6b0 ; DADD R6, R28, 2 ; BSYNC B0 ; DMUL R6, R6, 0.25 ; BSSY B0, 0xb7a0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0xb790 ; DADD R12, -R12, R30 ; DSETP.NEU.AND P0, PT, R28, 1, PT ; DADD R12, R12, R34 ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R10, -RZ, |R12| ; DADD R24, R24, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R12.reuse, 2 ; BSSY B0, 0xb8d0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R12, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xb8c0 ; DSETP.GTU.AND P0, PT, |R12|, +INF , PT ; @P0 BRA 0xb8b0 ; ISETP.NE.AND P0, PT, R12, RZ, PT ; LOP3.LUT R5, R13, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xb8c0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xb8c0 ; DADD R6, R12, 2 ; BSYNC B0 ; DMUL R6, R6, c[0x2][0x28] ; BSSY B0, 0xb990 ; MOV R5, 0x40000000 ; DADD R30, R30, -R34 ; MOV R8, 0xb980 ; DSETP.NEU.AND P0, PT, R12, 1, PT ; DADD R10, -RZ, |R30| ; FSEL R12, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R13, R7, 1.8854166269302368164, P0 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R30.reuse, 2 ; BSSY B0, 0xbac0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R30, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xbab0 ; DSETP.GTU.AND P0, PT, |R30|, +INF , PT ; @P0 BRA 0xbaa0 ; ISETP.NE.AND P0, PT, R30, RZ, PT ; LOP3.LUT R5, R31, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xbab0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xbab0 ; DADD R6, R30, 2 ; BSYNC B0 ; DMUL R6, R6, 0.25 ; BSSY B0, 0xbba0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0xbb90 ; DADD R14, -R14, R32 ; DSETP.NEU.AND P0, PT, R30, 1, PT ; DADD R14, R14, R36 ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R10, -RZ, |R14| ; DADD R12, R12, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R14.reuse, 2 ; BSSY B0, 0xbcd0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R14, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xbcc0 ; DSETP.GTU.AND P0, PT, |R14|, +INF , PT ; @P0 BRA 0xbcb0 ; ISETP.NE.AND P0, PT, R14, RZ, PT ; LOP3.LUT R5, R15, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xbcc0 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xbcc0 ; DADD R6, R14, 2 ; BSYNC B0 ; DFMA R22, R34, -4, R22 ; BSSY B0, 0xbda0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0xbd90 ; DMUL R6, R6, c[0x2][0x28] ; DADD R36, R22, R36 ; DSETP.NEU.AND P0, PT, R14, 1, PT ; DADD R10, -RZ, |R36| ; FSEL R22, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R23, R7, 1.8854166269302368164, P0 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R36.reuse, 2 ; BSSY B0, 0xbed0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R36, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xbec0 ; DSETP.GTU.AND P0, PT, |R36|, +INF , PT ; @P0 BRA 0xbeb0 ; ISETP.NE.AND P0, PT, R36, RZ, PT ; LOP3.LUT R5, R37, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xbec0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xbec0 ; DADD R6, R36, 2 ; BSYNC B0 ; DMUL R6, R6, 0.25 ; BSSY B0, 0xbfa0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0xbf90 ; DSETP.NEU.AND P0, PT, R36, 1, PT ; DADD R14, R24, c[0x2][0x30] ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R10, -RZ, |R14| ; DADD R22, R22, R6 ; MOV R6, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R14.reuse, 2 ; BSSY B0, 0xc0d0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R14, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xc0c0 ; DSETP.GTU.AND P0, PT, |R14|, +INF , PT ; @P0 BRA 0xc0b0 ; ISETP.NE.AND P0, PT, R14, RZ, PT ; LOP3.LUT R5, R15, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xc0c0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xc0c0 ; DADD R6, R14, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0xc230 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x38] ; DFMA R24, R10, -R6, c[0x2][0x38] ; DFMA R8, R8, R24, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0xc220 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R5, R7 ; IMAD.MOV.U32 R10, RZ, RZ, -0x66666666 ; MOV R6, 0xc210 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fb99999 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DADD R12, R12, c[0x2][0x30] ; BSSY B0, 0xc2e0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R14, 1, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R12| ; FSEL R14, R8, -1.5881868392106855534e-23, P0 ; FSEL R15, R9, 1.4499999284744262695, P0 ; MOV R8, 0xc2d0 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R12.reuse, 2 ; BSSY B0, 0xc410 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R12, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xc400 ; DSETP.GTU.AND P0, PT, |R12|, +INF , PT ; @P0 BRA 0xc3f0 ; ISETP.NE.AND P0, PT, R12, RZ, PT ; LOP3.LUT R5, R13, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xc400 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xc400 ; DADD R6, R12, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0xc570 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x40] ; DFMA R24, R10, -R6, c[0x2][0x40] ; DFMA R8, R8, R24, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0xc560 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0xc550 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fe33333 ; CALL.REL.NOINC 0x13360 ; MOV R9, R5 ; BSYNC B2 ; DADD R22, R22, c[0x2][0x30] ; BSSY B0, 0xc620 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R12, 1, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R22| ; FSEL R12, R8, 4.172325063223070174e-08, P0 ; FSEL R13, R9, 1.7749999761581420898, P0 ; MOV R8, 0xc610 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R22.reuse, 2 ; BSSY B0, 0xc750 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R22, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0xc740 ; DSETP.GTU.AND P0, PT, |R22|, +INF , PT ; @P0 BRA 0xc730 ; ISETP.NE.AND P0, PT, R22, RZ, PT ; LOP3.LUT R5, R23, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R5, 0x7ff00000, P0 ; @P0 BRA 0xc740 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0xc740 ; DADD R6, R22, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0xc8b0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x48] ; DFMA R24, R10, -R6, c[0x2][0x48] ; DFMA R8, R8, R24, R10 ; FFMA R5, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA 0xc8a0 ; MOV R8, R6 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; MOV R6, 0xc890 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fd33333 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DSETP.NEU.AND P0, PT, R22, 1, PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; BSSY B2, 0xca80 ; DADD R22, R14, R12 ; FSEL R24, R8, 4.172325063223070174e-08, P0 ; FSEL R25, R9, 1.6499999761581420898, P0 ; DADD R22, R22, R24 ; MUFU.RCP64H R7, R23 ; DFMA R8, -R22, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R22, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R28, R6, R14 ; DFMA R8, -R22, R28, R14 ; DFMA R28, R6, R8, R28 ; FFMA R5, RZ, R23, R29 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xca70 ; IMAD.MOV.U32 R10, RZ, RZ, R14 ; MOV R7, R15 ; IMAD.MOV.U32 R8, RZ, RZ, R22 ; MOV R6, 0xca50 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R28, RZ, RZ, R8 ; IMAD.MOV.U32 R29, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R23 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; BSSY B2, 0xcc20 ; DFMA R8, -R22, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R22, R8, 1 ; DFMA R8, R8, R6, R8 ; IMAD.MOV.U32 R6, RZ, RZ, R12 ; MOV R7, R13 ; DMUL R14, R8, R6 ; DFMA R6, -R22, R14, R6 ; DFMA R14, R8, R6, R14 ; FFMA R5, RZ, R23, R15 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xcc10 ; IMAD.MOV.U32 R10, RZ, RZ, R12 ; MOV R6, 0xcbf0 ; IMAD.MOV.U32 R7, RZ, RZ, R13 ; IMAD.MOV.U32 R8, RZ, RZ, R22 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R14, RZ, RZ, R8 ; IMAD.MOV.U32 R15, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R23 ; MOV R6, 0x1 ; BSSY B2, 0xcdb0 ; FSETP.GEU.AND P1, PT, |R25|, 6.5827683646048100446e-37, PT ; DFMA R8, -R22, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R22, R8, 1 ; DFMA R10, R8, R6, R8 ; IMAD.MOV.U32 R8, RZ, RZ, R24 ; IMAD.MOV.U32 R9, RZ, RZ, R25 ; DMUL R6, R10, R8 ; DFMA R8, -R22, R6, R8 ; DFMA R8, R10, R8, R6 ; FFMA R5, RZ, R23, R9 ; FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xcda0 ; IMAD.MOV.U32 R8, RZ, RZ, R22 ; MOV R6, 0xcd90 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; IMAD.MOV.U32 R10, RZ, RZ, R24 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; CALL.REL.NOINC 0x13360 ; MOV R9, R5 ; BSYNC B2 ; DMUL R16, R16, R14 ; DFMA R16, R18, R28, R16 ; DFMA R26, R26, R8, R16 ; BSYNC B1 ; S2R R5, SR_TID.Z ; ULDC UR4, c[0x0][0x1b8] ; UIADD3 UR4, UR4, -0x1, URZ ; S2R R6, SR_CTAID.Z ; IMAD R5, R6, c[0x0][0x8], R5 ; IADD3 R6, R5.reuse, 0x1, RZ ; IADD3 R10, R5.reuse, 0x3, RZ ; IADD3 R8, R5.reuse, 0x2, RZ ; I2F.F64 R6, R6 ; IADD3 R12, R5.reuse, -0x1, RZ ; IADD3 R14, R5.reuse, -0x2, RZ ; IADD3 R16, R5, -0x3, RZ ; IMAD.MOV.U32 R5, RZ, RZ, RZ ; I2F.F64 R10, R10 ; I2F.F64 R8, R8 ; DSETP.MAX.AND P0, P3, RZ, R6, PT ; IMAD.MOV.U32 R15, RZ, RZ, R6 ; IMAD.MOV.U32 R17, RZ, RZ, R7 ; I2F.F64 R12, R12 ; DSETP.MAX.AND P2, P4, RZ, R10, PT ; IMAD.MOV.U32 R23, RZ, RZ, R10 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; IMAD.MOV.U32 R22, RZ, RZ, R11 ; I2F.F64 R6, UR4 ; DSETP.MAX.AND P5, P6, RZ, R8, PT ; IMAD.MOV.U32 R19, RZ, RZ, R8 ; MOV R8, RZ ; SEL R10, R10, R15, P0 ; FSEL R11, R8.reuse, R17, P0 ; I2F.F64 R14, R14 ; @P3 LOP3.LUT R11, R17, 0x80000, RZ, 0xfc, !PT ; DSETP.MAX.AND P1, P0, RZ, R12, PT ; IMAD.MOV.U32 R25, RZ, RZ, R12 ; IMAD.MOV.U32 R12, RZ, RZ, RZ ; IMAD.MOV.U32 R29, RZ, RZ, R13 ; DSETP.GT.AND P3, PT, R10, R6, PT ; FSEL R13, R8, R9, P5 ; I2F.F64 R16, R16 ; @P6 LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; SEL R12, R12, R19, P5 ; FSEL R18, R6, R10, P3 ; IMAD.MOV.U32 R31, RZ, RZ, R14 ; FSEL R9, R5, R22, P2 ; IMAD.MOV.U32 R33, RZ, RZ, R15 ; SEL R8, R8, R23, P2 ; DSETP.GT.AND P5, PT, R12, R6, PT ; FSEL R19, R7, R11, P3 ; @P4 LOP3.LUT R9, R22, 0x80000, RZ, 0xfc, !PT ; DSETP.MAX.AND P2, P3, RZ, R14, PT ; MOV R10, RZ ; IMAD.MOV.U32 R14, RZ, RZ, RZ ; F2I.F64.TRUNC R5, R18 ; FSEL R12, R6, R12, P5 ; IMAD.MOV.U32 R22, RZ, RZ, R17 ; FSEL R11, R10.reuse, R29, P1 ; IMAD.MOV.U32 R35, RZ, RZ, R16 ; @P0 LOP3.LUT R11, R29, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P0, PT, R8, R6, PT ; SEL R10, R10, R25, P1 ; FSEL R13, R7.reuse, R13, P5 ; DSETP.MAX.AND P4, P5, RZ, R16, PT ; FSEL R19, R14, R33, P2 ; FSEL R14, R6, R8, P0 ; DSETP.GT.AND P1, PT, R10, R6, PT ; FSEL R15, R7, R9, P0 ; F2I.F64.TRUNC R23, R12 ; CS2R R8, SRZ ; @P3 LOP3.LUT R19, R33, 0x80000, RZ, 0xfc, !PT ; IMAD R5, R5, c[0x0][0x1b4], R0 ; FSEL R17, R7, R11, P1 ; FSEL R16, R6, R10, P1 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; FSEL R11, R9, R22, P4 ; IMAD.MOV.U32 R9, RZ, RZ, R19 ; SEL R8, R8, R31, P2 ; F2I.F64.TRUNC R25, R16 ; SEL R10, R10, R35, P4 ; @P5 LOP3.LUT R11, R22, 0x80000, RZ, 0xfc, !PT ; DSETP.GT.AND P0, PT, R8, R6, PT ; IMAD R23, R23, c[0x0][0x1b4], R0 ; F2I.F64.TRUNC R15, R14 ; FSEL R12, R6, R8, P0 ; FSEL R13, R7, R9, P0 ; DSETP.GT.AND P0, PT, R10, R6, PT ; IADD3 R8, P1, R4, c[0x0][0x168], RZ ; IMAD R25, R25, c[0x0][0x1b4], R0 ; F2I.F64.TRUNC R13, R12 ; FSEL R10, R6, R10, P0 ; FSEL R11, R7, R11, P0 ; DSETP.GEU.AND P0, PT, |R38|, |R40|, PT ; IADD3.X R9, R3, c[0x0][0x16c], RZ, P1, !PT ; IMAD R15, R15, c[0x0][0x1b4], R0 ; IADD3 R18, P1, R4, c[0x0][0x1a8], RZ ; F2I.F64.TRUNC R11, R10 ; FSEL R6, R26, R20, !P0 ; FSEL R7, R27, R21, !P0 ; IADD3 R16, P0, R4, c[0x0][0x1a0], RZ ; IADD3.X R19, R3.reuse, c[0x0][0x1ac], RZ, P1, !PT ; STG.E.64 [R8.64], R6 ; IADD3.X R17, R3, c[0x0][0x1a4], RZ, P0, !PT ; IMAD R13, R13, c[0x0][0x1b4], R0 ; LDG.E.64 R16, [R16.64] ; IMAD R11, R11, c[0x0][0x1b4], R0 ; IMAD.MOV.U32 R0, RZ, RZ, 0x8 ; LDG.E.64 R6, [R18.64] ; IMAD R13, R13, c[0x0][0x1b0], R2.reuse ; IMAD R5, R5, c[0x0][0x1b0], R2.reuse ; IMAD R23, R23, c[0x0][0x1b0], R2.reuse ; IMAD R11, R11, c[0x0][0x1b0], R2 ; IMAD R14, R25, c[0x0][0x1b0], R2.reuse ; IMAD R24, R15, c[0x0][0x1b0], R2 ; IMAD.WIDE R34, R13, R0, c[0x0][0x178] ; IMAD.WIDE R36, R11, R0.reuse, c[0x0][0x178] ; LDG.E.64 R34, [R34.64] ; IMAD.WIDE R14, R14, R0.reuse, c[0x0][0x178] ; LDG.E.64 R36, [R36.64] ; IMAD.WIDE R12, R5, R0.reuse, c[0x0][0x178] ; LDG.E.64 R14, [R14.64] ; IMAD.WIDE R22, R23, R0, c[0x0][0x178] ; LDG.E.64 R12, [R12.64] ; IMAD.WIDE R24, R24, R0, c[0x0][0x178] ; LDG.E.64 R22, [R22.64] ; LDG.E.64 R24, [R24.64] ; BSSY B1, 0x132f0 ; DSETP.GEU.AND P1, PT, R16, c[0x0][0x1d0], PT ; DSETP.GEU.AND P0, PT, R6, c[0x0][0x1d0], PT ; @P0 BRA P1, 0xf1e0 ; DSETP.GEU.AND P1, PT, R16, c[0x0][0x1d0], PT ; MOV R30, c[0x0][0x1d0] ; IMAD.MOV.U32 R31, RZ, RZ, c[0x0][0x1d4] ; BSSY B2, 0xd9b0 ; IMAD.MOV.U32 R26, RZ, RZ, c[0x0][0x1d0] ; @P0 MOV R38, R14 ; IMAD.MOV.U32 R27, RZ, RZ, c[0x0][0x1d4] ; DADD R28, R30, c[0x0][0x1d0] ; IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; IMAD.MOV.U32 R20, RZ, RZ, R12 ; IMAD.MOV.U32 R21, RZ, RZ, R13 ; @P1 DMUL R8, R30.reuse, 3 ; @P1 IMAD.MOV.U32 R20, RZ, RZ, R22 ; @P1 IMAD.MOV.U32 R21, RZ, RZ, R23 ; @P1 MOV R23, R25 ; @P1 IMAD.MOV.U32 R26, RZ, RZ, R28 ; @P1 IMAD.MOV.U32 R27, RZ, RZ, R29 ; @P1 IMAD.MOV.U32 R22, RZ, RZ, R24 ; @P1 MOV R29, R9 ; @P1 IMAD.MOV.U32 R28, RZ, RZ, R8 ; DMUL R24, R30, -2 ; @!P0 IMAD.MOV.U32 R36, RZ, RZ, R34 ; @!P0 IMAD.MOV.U32 R37, RZ, RZ, R35 ; DADD R40, -R20, R22 ; @P0 IMAD.MOV.U32 R39, RZ, RZ, R15 ; @!P0 CS2R R38, SRZ ; @!P0 IMAD.MOV.U32 R42, RZ, RZ, R6 ; DADD R8, -R26, R28 ; @!P0 IMAD.MOV.U32 R43, RZ, RZ, R7 ; @!P0 MOV R35, R15 ; @P1 IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x1d0] ; @P0 DMUL R22, R30, -3 ; @P1 IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x1d4] ; MUFU.RCP64H R11, R9 ; FSETP.GEU.AND P3, PT, |R41|, 6.5827683646048100446e-37, PT ; @!P0 IMAD.MOV.U32 R34, RZ, RZ, R14 ; @!P0 IMAD.MOV.U32 R22, RZ, RZ, R24 ; @!P0 IMAD.MOV.U32 R23, RZ, RZ, R25 ; @!P0 DADD R24, -RZ, -c[0x0][0x1d0] ; DFMA R18, -R8, R10, 1 ; DFMA R18, R18, R18, R18 ; DFMA R18, R10, R18, R10 ; DFMA R10, -R8, R18, 1 ; DFMA R10, R18, R10, R18 ; DMUL R32, R40, R10 ; DFMA R18, -R8, R32, R40 ; DFMA R32, R10, R18, R32 ; CS2R R18, SRZ ; @P1 IMAD.MOV.U32 R18, RZ, RZ, R12 ; @P1 IMAD.MOV.U32 R19, RZ, RZ, R13 ; FFMA R0, RZ, R9, R33 ; FSETP.GT.AND P2, PT, |R0|, 1.469367938527859385e-39, PT ; @P2 BRA P3, 0xd9a0 ; IMAD.MOV.U32 R10, RZ, RZ, R40 ; MOV R6, 0xd980 ; IMAD.MOV.U32 R7, RZ, RZ, R41 ; IMAD.MOV.U32 R5, RZ, RZ, R9 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R32, RZ, RZ, R8 ; IMAD.MOV.U32 R33, RZ, RZ, R5 ; BSYNC B2 ; DADD R40, R26, -R16 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0xdb40 ; DADD R10, R20, -R18 ; MUFU.RCP64H R7, R41 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R40, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R40, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R30, R10, R6 ; DFMA R8, -R40, R30, R10 ; DFMA R30, R6, R8, R30 ; FFMA R0, RZ, R41, R31 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xdb30 ; MOV R7, R11 ; IMAD.MOV.U32 R8, RZ, RZ, R40 ; MOV R6, 0xdb10 ; IMAD.MOV.U32 R5, RZ, RZ, R41 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; IMAD.MOV.U32 R31, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R17 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R44, R18 ; BSSY B2, 0xdcc0 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R16, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R16, 1 ; DFMA R6, R8, R6, R8 ; DMUL R20, R10, R6 ; DFMA R8, R20, -R16, R10 ; DFMA R20, R6, R8, R20 ; FFMA R0, RZ, R17, R21 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xdcb0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R8, R16 ; IMAD.MOV.U32 R5, RZ, RZ, R17 ; MOV R6, 0xdc90 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R20, RZ, RZ, R8 ; IMAD.MOV.U32 R21, RZ, RZ, R5 ; BSYNC B2 ; DADD R18, RZ, R42 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0xde50 ; DADD R10, R44, -R38 ; MUFU.RCP64H R7, R19 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R18, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R18, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R46, R10, R6 ; DFMA R8, -R18, R46, R10 ; DFMA R46, R6, R8, R46 ; FFMA R0, RZ, R19, R47 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xde40 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R5, R19 ; IMAD.MOV.U32 R8, RZ, RZ, R18 ; MOV R6, 0xde20 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R46, RZ, RZ, R8 ; IMAD.MOV.U32 R47, RZ, RZ, R5 ; BSYNC B2 ; DADD R40, -R24, -R42 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0xdfe0 ; DADD R10, -R34, R38 ; MUFU.RCP64H R7, R41 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R40, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R40, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R44, R10, R6 ; DFMA R8, -R40, R44, R10 ; DFMA R44, R6, R8, R44 ; FFMA R0, RZ, R41, R45 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xdfd0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xdfb0 ; IMAD.MOV.U32 R8, RZ, RZ, R40 ; IMAD.MOV.U32 R5, RZ, RZ, R41 ; CALL.REL.NOINC 0x13360 ; MOV R44, R8 ; IMAD.MOV.U32 R45, RZ, RZ, R5 ; BSYNC B2 ; DADD R38, -R22, R24 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0xe170 ; DADD R10, R34, -R36 ; MUFU.RCP64H R7, R39 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R38, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R38, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R40, R10, R6 ; DFMA R8, -R38, R40, R10 ; DFMA R40, R6, R8, R40 ; FFMA R0, RZ, R39, R41 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xe160 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xe140 ; IMAD.MOV.U32 R8, RZ, RZ, R38 ; IMAD.MOV.U32 R5, RZ, RZ, R39 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R40, RZ, RZ, R8 ; MOV R41, R5 ; BSYNC B2 ; DADD R34, R28, -R16 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0xe300 ; DADD R10, -R30, R32 ; MUFU.RCP64H R7, R35 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R34, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R34, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R38, R10, R6 ; DFMA R8, -R34, R38, R10 ; DFMA R38, R6, R8, R38 ; FFMA R0, RZ, R35, R39 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xe2f0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xe2d0 ; IMAD.MOV.U32 R8, RZ, RZ, R34 ; IMAD.MOV.U32 R5, RZ, RZ, R35 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R38, RZ, RZ, R8 ; IMAD.MOV.U32 R39, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R27 ; MOV R6, 0x1 ; DADD R10, -R20, R30 ; BSSY B2, 0xe480 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R26, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R26, 1 ; DFMA R6, R8, R6, R8 ; DMUL R36, R10, R6 ; DFMA R8, R36, -R26, R10 ; DFMA R36, R6, R8, R36 ; FFMA R0, RZ, R27, R37 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xe470 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xe450 ; IMAD.MOV.U32 R8, RZ, RZ, R26 ; IMAD.MOV.U32 R5, RZ, RZ, R27 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R36, RZ, RZ, R8 ; IMAD.MOV.U32 R37, RZ, RZ, R5 ; BSYNC B2 ; DADD R30, R16, R42 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0xe610 ; DADD R10, -R46, R20 ; MUFU.RCP64H R7, R31 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R30, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R30, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R34, R10, R6 ; DFMA R8, -R30, R34, R10 ; DFMA R34, R6, R8, R34 ; FFMA R0, RZ, R31, R35 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xe600 ; MOV R7, R11 ; IMAD.MOV.U32 R8, RZ, RZ, R30 ; MOV R6, 0xe5e0 ; IMAD.MOV.U32 R5, RZ, RZ, R31 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R34, RZ, RZ, R8 ; IMAD.MOV.U32 R35, RZ, RZ, R5 ; BSYNC B2 ; DADD R30, RZ, -R24 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0xe7a0 ; DADD R10, -R44, R46 ; MUFU.RCP64H R7, R31 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R30, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R30, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R32, R10, R6 ; DFMA R8, -R30, R32, R10 ; DFMA R32, R6, R8, R32 ; FFMA R0, RZ, R31, R33 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xe790 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R8, R30 ; IMAD.MOV.U32 R5, RZ, RZ, R31 ; MOV R6, 0xe770 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R32, RZ, RZ, R8 ; IMAD.MOV.U32 R33, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, -R22, -R42 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0xe930 ; DADD R44, -R40, R44 ; MUFU.RCP64H R7, R9 ; FSETP.GEU.AND P1, PT, |R45|, 6.5827683646048100446e-37, PT ; DFMA R10, -R8, R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DFMA R6, -R8, R10, 1 ; DFMA R6, R10, R6, R10 ; DMUL R40, R44, R6 ; DFMA R10, -R8, R40, R44 ; DFMA R40, R6, R10, R40 ; FFMA R0, RZ, R9, R41 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xe920 ; IMAD.MOV.U32 R10, RZ, RZ, R44 ; MOV R5, R9 ; IMAD.MOV.U32 R7, RZ, RZ, R45 ; MOV R6, 0xe900 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R40, RZ, RZ, R8 ; IMAD.MOV.U32 R41, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R29 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DADD R10, -R36, R38 ; BSSY B2, 0xeab0 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R6, -R28, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R28, 1 ; DFMA R6, R8, R6, R8 ; DMUL R38, R10, R6 ; DFMA R8, R38, -R28, R10 ; DFMA R38, R6, R8, R38 ; FFMA R0, RZ, R29, R39 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xeaa0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xea80 ; IMAD.MOV.U32 R8, RZ, RZ, R28 ; IMAD.MOV.U32 R5, RZ, RZ, R29 ; CALL.REL.NOINC 0x13360 ; MOV R38, R8 ; IMAD.MOV.U32 R39, RZ, RZ, R5 ; BSYNC B2 ; DADD R42, R26, R42 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0xec40 ; DADD R10, -R34, R36 ; MUFU.RCP64H R7, R43 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R42, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R42, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R28, R10, R6 ; DFMA R8, -R42, R28, R10 ; DFMA R28, R6, R8, R28 ; FFMA R0, RZ, R43, R29 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xec30 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xec10 ; IMAD.MOV.U32 R8, RZ, RZ, R42 ; IMAD.MOV.U32 R5, RZ, RZ, R43 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R28, RZ, RZ, R8 ; MOV R29, R5 ; BSYNC B2 ; DADD R42, -R24, R16 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0xedd0 ; DADD R10, -R32, R34 ; MUFU.RCP64H R7, R43 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, -R42, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R42, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R24, R10, R6 ; DFMA R8, -R42, R24, R10 ; DFMA R24, R6, R8, R24 ; FFMA R0, RZ, R43, R25 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xedc0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xeda0 ; IMAD.MOV.U32 R8, RZ, RZ, R42 ; IMAD.MOV.U32 R5, RZ, RZ, R43 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R24, RZ, RZ, R8 ; IMAD.MOV.U32 R25, RZ, RZ, R5 ; BSYNC B2 ; DADD R22, RZ, -R22 ; MOV R6, 0x1 ; BSSY B2, 0xef60 ; DADD R40, -R40, R32 ; MUFU.RCP64H R7, R23 ; FSETP.GEU.AND P1, PT, |R41|, 6.5827683646048100446e-37, PT ; DFMA R8, -R22, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R22, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R8, R40, R6 ; DFMA R10, -R22, R8, R40 ; DFMA R8, R6, R10, R8 ; FFMA R0, RZ, R23, R9 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xef50 ; IMAD.MOV.U32 R10, RZ, RZ, R40 ; MOV R6, 0xef40 ; IMAD.MOV.U32 R7, RZ, RZ, R41 ; IMAD.MOV.U32 R8, RZ, RZ, R22 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DMUL R6, R32, R34 ; DSETP.GEU.AND P0, PT, |R24|, |R8|, PT ; DMUL R10, R34, R36 ; DSETP.GEU.AND P4, PT, R6, RZ, PT ; FSEL R6, R24, R8, !P0 ; FSEL R7, R25, R9, !P0 ; DMUL R30, R18, R30 ; DADD R16, RZ, -R16 ; DADD R26, RZ, -R26 ; DSETP.GEU.AND P2, PT, |R28|, |R38|, PT ; DSETP.GEU.AND P0, PT, |R24|, |R28|, PT ; DSETP.GEU.AND P5, PT, R10, RZ, PT ; FSEL R10, R28, R38, !P2 ; DMUL R30, R30, R6 ; FSEL R11, R29, R39, !P2 ; FSEL R8, R24, R28, !P0 ; DMUL R26, R16, R26 ; FSEL R9, R25, R29, !P0 ; DSETP.GEU.AND P1, PT, |R32|, |R34|, PT ; DSETP.GEU.AND P3, PT, |R34|, |R36|, PT ; FSEL R0, R32, R34, !P1 ; DMUL R6, R18, R16 ; FSEL R32, R33, R35, !P1 ; DMUL R26, R26, R10 ; FSEL R10, R34, R36, !P3 ; DMUL R6, R6, R8 ; FSEL R34, R35, R37, !P3 ; FSEL R8, R0, RZ, P4 ; FSEL R9, R32, RZ, P4 ; FSEL R10, R10, RZ, P5 ; FSEL R11, R34, RZ, P5 ; FSEL R28, R30, R6, !P1 ; DFMA R18, R18, R8, R46 ; FSEL R29, R31, R7, !P1 ; FSEL R6, R6, R26, !P3 ; DFMA R16, R16, R10, R20 ; FSEL R7, R7, R27, !P3 ; DADD R28, R18, R28 ; DADD R16, R16, R6 ; BRA 0x132e0 ; MUFU.RCP64H R7, c[0x0][0x1d4] ; IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x1d0] ; MOV R11, c[0x0][0x1d4] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; BSSY B2, 0xf380 ; DFMA R8, R6, -R10, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, R8, -R10, 1 ; DADD R10, R34, -R36 ; DFMA R6, R8, R6, R8 ; DMUL R20, R10, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DFMA R8, R20, -c[0x0][0x1d0], R10 ; DFMA R20, R6, R8, R20 ; FFMA R0, RZ, c[0x0][0x1d4], R21 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xf370 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R6, 0xf350 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1d0] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1d4] ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R20, RZ, RZ, R8 ; IMAD.MOV.U32 R21, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1d4] ; MOV R8, c[0x0][0x1d0] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1d4] ; BSSY B2, 0xf520 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DADD R6, -R34, R14 ; DFMA R8, R10, -R8, 1 ; DFMA R10, R10, R8, R10 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; DMUL R18, R10, R6 ; DFMA R8, R18, -c[0x0][0x1d0], R6 ; DFMA R18, R10, R8, R18 ; FFMA R0, RZ, c[0x0][0x1d4], R19 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xf510 ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; MOV R6, 0xf4f0 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1d0] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1d4] ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R18, RZ, RZ, R8 ; MOV R19, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1d4] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1d0] ; BSSY B2, 0xf6c0 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1d4] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DADD R6, R44, -R14 ; DFMA R8, R10, -R8, 1 ; DFMA R10, R10, R8, R10 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; DMUL R16, R10, R6 ; DFMA R8, R16, -c[0x0][0x1d0], R6 ; DFMA R16, R10, R8, R16 ; FFMA R0, RZ, c[0x0][0x1d4], R17 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xf6b0 ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; MOV R6, 0xf690 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1d0] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1d4] ; CALL.REL.NOINC 0x13360 ; MOV R16, R8 ; IMAD.MOV.U32 R17, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1d4] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1d0] ; BSSY B2, 0xf860 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1d4] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R6, R10, R6 ; DADD R6, -R44, R12 ; DFMA R8, R10, -R8, 1 ; DFMA R10, R10, R8, R10 ; FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; DMUL R46, R10, R6 ; DFMA R8, R46, -c[0x0][0x1d0], R6 ; DFMA R46, R10, R8, R46 ; FFMA R0, RZ, c[0x0][0x1d4], R47 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xf850 ; IMAD.MOV.U32 R10, RZ, RZ, R6 ; MOV R5, c[0x0][0x1d4] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1d0] ; MOV R6, 0xf830 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R46, RZ, RZ, R8 ; IMAD.MOV.U32 R47, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1d4] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1d0] ; BSSY B2, 0xfa00 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1d4] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, -R12, R22 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R44, R8, R10 ; DFMA R6, R44, -c[0x0][0x1d0], R10 ; DFMA R44, R8, R6, R44 ; FFMA R0, RZ, c[0x0][0x1d4], R45 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xf9f0 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; MOV R8, c[0x0][0x1d0] ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1d4] ; MOV R6, 0xf9d0 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R44, RZ, RZ, R8 ; IMAD.MOV.U32 R45, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, c[0x0][0x1d4] ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1d0] ; BSSY B2, 0xfba0 ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x1d4] ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; DFMA R10, R6, -R8, 1 ; DFMA R10, R10, R10, R10 ; DFMA R6, R6, R10, R6 ; DADD R10, R24, -R22 ; DFMA R8, R6, -R8, 1 ; DFMA R8, R6, R8, R6 ; FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; DMUL R42, R8, R10 ; DFMA R6, R42, -c[0x0][0x1d0], R10 ; DFMA R42, R8, R6, R42 ; FFMA R0, RZ, c[0x0][0x1d4], R43 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0xfb90 ; MOV R7, R11 ; IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x1d0] ; MOV R6, 0xfb70 ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x1d4] ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R42, RZ, RZ, R8 ; IMAD.MOV.U32 R43, RZ, RZ, R5 ; BSYNC B2 ; DADD R8, R18.reuse, R18 ; BSSY B0, 0xfcd0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DMUL R36, R18, c[0x2][0x18] ; DADD R8, -R8, R20 ; DMUL R6, R18, c[0x2][0x0] ; DADD R24, R8, R16 ; MOV R8, 0xfcc0 ; DMUL R30, R46, c[0x2][0x20] ; DFMA R32, R16, c[0x2][0x20], -R36 ; DFMA R6, R20, c[0x2][0x8], R6 ; DMUL R34, R46, c[0x2][0x8] ; DADD R10, -RZ, |R24| ; DFMA R28, R16, c[0x2][0x8], R30 ; DFMA R32, R46, c[0x2][0x8], R32 ; DFMA R38, R16, c[0x2][0x10], R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R24.reuse, 2 ; BSSY B0, 0xfe10 ; MOV R26, R6 ; IMAD.MOV.U32 R27, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R26, SRZ ; @P1 BRA 0xfe00 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0xfdf0 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R0, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0xfe00 ; IMAD.MOV.U32 R26, RZ, RZ, 0x0 ; IMAD.MOV.U32 R27, RZ, RZ, 0x7ff00000 ; BRA 0xfe00 ; DADD R26, R24, 2 ; BSYNC B0 ; DFMA R20, R18, -4, R20 ; BSSY B0, 0xfeb0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; MOV R8, 0xfea0 ; DMUL R22, R16, 3 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DADD R20, R20, R22 ; DADD R10, -RZ, |R20| ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R20.reuse, 2 ; BSSY B0, 0x10020 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P1, PT, R20, RZ, PT ; DMUL R10, R26, c[0x2][0x28] ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; DSETP.NEU.AND P0, PT, R24, 1, PT ; ISETP.NE.AND P2, PT, R8, 0x7ff00000, PT ; FSEL R40, R10, 1.46601546874880000000e+13, P0 ; @!P1 CS2R R6, SRZ ; FSEL R41, R11, 1.8854166269302368164, P0 ; @P2 BRA 0x10010 ; DSETP.GTU.AND P0, PT, |R20|, +INF , PT ; @P0 BRA 0x10000 ; ISETP.NE.AND P0, PT, R20, RZ, PT ; LOP3.LUT R0, R21, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x10010 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x10010 ; DADD R6, R20, 2 ; BSYNC B0 ; DADD R26, R16, R16 ; BSSY B0, 0x10110 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x10100 ; DMUL R6, R6, 0.25 ; DADD R24, -R26, R18 ; DSETP.NEU.AND P0, PT, R20, 1, PT ; DADD R24, R24, R46 ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R10, -RZ, |R24| ; DADD R40, R40, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R24.reuse, 2 ; BSSY B0, 0x10240 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x10230 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x10220 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R0, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x10230 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x10230 ; DADD R6, R24, 2 ; BSYNC B0 ; DMUL R6, R6, c[0x2][0x28] ; BSSY B0, 0x10300 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x102f0 ; DADD R20, -R46, R18 ; DSETP.NEU.AND P0, PT, R24, 1, PT ; DADD R10, -RZ, |R20| ; FSEL R50, R6, 1.46601546874880000000e+13, P0 ; FSEL R51, R7, 1.8854166269302368164, P0 ; MOV R6, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R20.reuse, 2 ; BSSY B0, 0x10430 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x10420 ; DSETP.GTU.AND P0, PT, |R20|, +INF , PT ; @P0 BRA 0x10410 ; ISETP.NE.AND P0, PT, R20, RZ, PT ; LOP3.LUT R0, R21, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x10420 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x10420 ; DADD R6, R20, 2 ; BSYNC B0 ; DADD R24, R46, R46 ; BSSY B0, 0x10520 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x10510 ; DMUL R6, R6, 0.25 ; DADD R48, -R24, R16 ; DSETP.NEU.AND P0, PT, R20, 1, PT ; DADD R48, R48, R44 ; FSEL R20, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R21, R7, 1.625, P0 ; DADD R10, -RZ, |R48| ; DADD R20, R50, R20 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R48.reuse, 2 ; BSSY B0, 0x10650 ; MOV R7, R5 ; DSETP.NEU.AND P0, PT, R48, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x10640 ; DSETP.GTU.AND P0, PT, |R48|, +INF , PT ; @P0 BRA 0x10630 ; ISETP.NE.AND P0, PT, R48, RZ, PT ; LOP3.LUT R0, R49, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x10640 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x10640 ; DADD R6, R48, 2 ; BSYNC B0 ; DFMA R22, R46, -4, R22 ; BSSY B0, 0x10720 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x10710 ; DMUL R6, R6, c[0x2][0x28] ; DADD R22, R22, R44 ; DSETP.NEU.AND P0, PT, R48, 1, PT ; DADD R10, -RZ, |R22| ; FSEL R48, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R49, R7, 1.8854166269302368164, P0 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R22.reuse, 2 ; BSSY B0, 0x10850 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R22, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x10840 ; DSETP.GTU.AND P0, PT, |R22|, +INF , PT ; @P0 BRA 0x10830 ; ISETP.NE.AND P0, PT, R22, RZ, PT ; LOP3.LUT R0, R23, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x10840 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x10840 ; DADD R6, R22, 2 ; BSYNC B0 ; DMUL R6, R6, 0.25 ; BSSY B0, 0x10920 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x10910 ; DSETP.NEU.AND P0, PT, R22, 1, PT ; DADD R40, R40, c[0x2][0x30] ; FSEL R22, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R23, R7, 1.625, P0 ; DADD R10, -RZ, |R40| ; DADD R22, R48, R22 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R40.reuse, 2 ; BSSY B0, 0x10a50 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R40, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x10a40 ; DSETP.GTU.AND P0, PT, |R40|, +INF , PT ; @P0 BRA 0x10a30 ; ISETP.NE.AND P0, PT, R40, RZ, PT ; LOP3.LUT R0, R41, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x10a40 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; MOV R7, 0x7ff00000 ; BRA 0x10a40 ; DADD R6, R40, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0x10bb0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x38] ; DFMA R48, R10, -R6, c[0x2][0x38] ; DFMA R8, R8, R48, R10 ; FFMA R0, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA 0x10ba0 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x10b90 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, -0x66666666 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fb99999 ; CALL.REL.NOINC 0x13360 ; MOV R9, R5 ; BSYNC B2 ; DADD R20, R20, c[0x2][0x30] ; BSSY B0, 0x10c60 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R40, 1, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R20| ; FSEL R40, R8, -1.5881868392106855534e-23, P0 ; FSEL R41, R9, 1.4499999284744262695, P0 ; MOV R8, 0x10c50 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R20.reuse, 2 ; BSSY B0, 0x10d90 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R20, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x10d80 ; DSETP.GTU.AND P0, PT, |R20|, +INF , PT ; @P0 BRA 0x10d70 ; ISETP.NE.AND P0, PT, R20, RZ, PT ; LOP3.LUT R0, R21, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x10d80 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x10d80 ; DADD R6, R20, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; MOV R8, 0x1 ; BSSY B2, 0x10ef0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x40] ; DFMA R48, R10, -R6, c[0x2][0x40] ; DFMA R8, R8, R48, R10 ; FFMA R0, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA 0x10ee0 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x10ed0 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fe33333 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DADD R22, R22, c[0x2][0x30] ; BSSY B0, 0x10fa0 ; MOV R6, RZ ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DSETP.NEU.AND P0, PT, R20, 1, PT ; DADD R10, -RZ, |R22| ; FSEL R20, R8, 4.172325063223070174e-08, P0 ; FSEL R21, R9, 1.7749999761581420898, P0 ; MOV R8, 0x10f90 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R22.reuse, 2 ; BSSY B0, 0x110d0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R22, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x110c0 ; DSETP.GTU.AND P0, PT, |R22|, +INF , PT ; @P0 BRA 0x110b0 ; ISETP.NE.AND P0, PT, R22, RZ, PT ; LOP3.LUT R0, R23, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x110c0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x110c0 ; DADD R6, R22, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0x11230 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x48] ; DFMA R48, R10, -R6, c[0x2][0x48] ; DFMA R8, R8, R48, R10 ; FFMA R0, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA 0x11220 ; MOV R8, R6 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; MOV R6, 0x11210 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fd33333 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DSETP.NEU.AND P0, PT, R22, 1, PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R41|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x11400 ; DADD R22, R40, R20 ; FSEL R48, R8, 4.172325063223070174e-08, P0 ; FSEL R49, R9, 1.6499999761581420898, P0 ; DADD R22, R22, R48 ; MUFU.RCP64H R7, R23 ; DFMA R8, -R22, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R22, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R50, R6, R40 ; DFMA R8, -R22, R50, R40 ; DFMA R50, R6, R8, R50 ; FFMA R0, RZ, R23, R51 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x113f0 ; MOV R10, R40 ; IMAD.MOV.U32 R7, RZ, RZ, R41 ; MOV R6, 0x113d0 ; IMAD.MOV.U32 R8, RZ, RZ, R22 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R50, RZ, RZ, R8 ; IMAD.MOV.U32 R51, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R23 ; MOV R6, 0x1 ; BSSY B2, 0x115a0 ; FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; DFMA R8, -R22, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R22, R8, 1 ; DFMA R8, R8, R6, R8 ; IMAD.MOV.U32 R6, RZ, RZ, R20 ; IMAD.MOV.U32 R7, RZ, RZ, R21 ; DMUL R40, R8, R6 ; DFMA R6, -R22, R40, R6 ; DFMA R40, R8, R6, R40 ; FFMA R0, RZ, R23, R41 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x11590 ; IMAD.MOV.U32 R10, RZ, RZ, R20 ; MOV R5, R23 ; IMAD.MOV.U32 R7, RZ, RZ, R21 ; MOV R6, 0x11570 ; IMAD.MOV.U32 R8, RZ, RZ, R22 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R40, RZ, RZ, R8 ; IMAD.MOV.U32 R41, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R23 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R49|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x11730 ; DFMA R8, -R22, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R22, R8, 1 ; DFMA R10, R8, R6, R8 ; IMAD.MOV.U32 R6, RZ, RZ, R48 ; IMAD.MOV.U32 R7, RZ, RZ, R49 ; DMUL R8, R10, R6 ; DFMA R6, -R22, R8, R6 ; DFMA R8, R10, R6, R8 ; FFMA R0, RZ, R23, R9 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x11720 ; MOV R8, R22 ; IMAD.MOV.U32 R5, RZ, RZ, R23 ; MOV R6, 0x11710 ; IMAD.MOV.U32 R10, RZ, RZ, R48 ; IMAD.MOV.U32 R7, RZ, RZ, R49 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DADD R6, R44, R44 ; BSSY B0, 0x11880 ; MOV R5, 0x40000000 ; DMUL R32, R32, R40 ; DADD R6, -R6, R42 ; DFMA R38, R38, R50, R32 ; DADD R32, R6, R46 ; DMUL R6, R44, c[0x2][0x0] ; DFMA R34, R16, c[0x2][0x20], R34 ; DFMA R20, R44, c[0x2][0x50], R30 ; DFMA R28, R44, c[0x2][0x50], R28 ; DFMA R6, R42, c[0x2][0x8], R6 ; DADD R36, -R36, R34 ; DADD R10, -RZ, |R32| ; DFMA R20, R16, c[0x2][0x8], R20 ; DFMA R28, R28, R8, R38 ; MOV R8, 0x11870 ; DFMA R22, R46, c[0x2][0x10], R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R32.reuse, 2 ; BSSY B0, 0x119b0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R32, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x119a0 ; DSETP.GTU.AND P0, PT, |R32|, +INF , PT ; @P0 BRA 0x11990 ; ISETP.NE.AND P0, PT, R32, RZ, PT ; LOP3.LUT R0, R33, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x119a0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x119a0 ; DADD R6, R32, 2 ; BSYNC B0 ; DFMA R34, R44, -4, R42 ; BSSY B0, 0x11a90 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x11a80 ; DMUL R30, R46, 3 ; DMUL R6, R6, c[0x2][0x28] ; DADD R34, R34, R30 ; DSETP.NEU.AND P0, PT, R32, 1, PT ; DADD R10, -RZ, |R34| ; FSEL R32, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R33, R7, 1.8854166269302368164, P0 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R34.reuse, 2 ; BSSY B0, 0x11bc0 ; MOV R7, R5 ; DSETP.NEU.AND P0, PT, R34, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x11bb0 ; DSETP.GTU.AND P0, PT, |R34|, +INF , PT ; @P0 BRA 0x11ba0 ; ISETP.NE.AND P0, PT, R34, RZ, PT ; LOP3.LUT R0, R35, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x11bb0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x11bb0 ; DADD R6, R34, 2 ; BSYNC B0 ; DMUL R6, R6, 0.25 ; BSSY B0, 0x11ca0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x11c90 ; DADD R24, -R24, R44 ; DSETP.NEU.AND P0, PT, R34, 1, PT ; DADD R24, R24, R16 ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R10, -RZ, |R24| ; DADD R32, R32, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R24.reuse, 2 ; BSSY B0, 0x11dd0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x11dc0 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x11db0 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R0, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x11dc0 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x11dc0 ; DADD R6, R24, 2 ; BSYNC B0 ; DMUL R6, R6, c[0x2][0x28] ; BSSY B0, 0x11e90 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x11e80 ; DADD R44, R44, -R16 ; DSETP.NEU.AND P0, PT, R24, 1, PT ; DADD R10, -RZ, |R44| ; FSEL R24, R6, 1.46601546874880000000e+13, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R25, R7, 1.8854166269302368164, P0 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R44.reuse, 2 ; BSSY B0, 0x11fc0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R44, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x11fb0 ; DSETP.GTU.AND P0, PT, |R44|, +INF , PT ; @P0 BRA 0x11fa0 ; ISETP.NE.AND P0, PT, R44, RZ, PT ; LOP3.LUT R0, R45, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x11fb0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; MOV R7, 0x7ff00000 ; BRA 0x11fb0 ; DADD R6, R44, 2 ; BSYNC B0 ; DMUL R6, R6, 0.25 ; BSSY B0, 0x120a0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x12090 ; DADD R26, -R26, R46 ; DSETP.NEU.AND P0, PT, R44, 1, PT ; DADD R26, R26, R18 ; FSEL R6, R6, RZ, P0 ; FSEL R7, R7, 1.625, P0 ; DADD R10, -RZ, |R26| ; DADD R24, R24, R6 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R26.reuse, 2 ; BSSY B0, 0x121d0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R26, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x121c0 ; DSETP.GTU.AND P0, PT, |R26|, +INF , PT ; @P0 BRA 0x121b0 ; ISETP.NE.AND P0, PT, R26, RZ, PT ; LOP3.LUT R0, R27, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x121c0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x121c0 ; DADD R6, R26, 2 ; BSYNC B0 ; DFMA R16, R16, -4, R30 ; BSSY B0, 0x122a0 ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; MOV R8, 0x12290 ; DMUL R6, R6, c[0x2][0x28] ; DADD R18, R16, R18 ; DSETP.NEU.AND P0, PT, R26, 1, PT ; DADD R10, -RZ, |R18| ; FSEL R26, R6, 1.46601546874880000000e+13, P0 ; FSEL R27, R7, 1.8854166269302368164, P0 ; MOV R6, RZ ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R18.reuse, 2 ; BSSY B0, 0x123d0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R18, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x123c0 ; DSETP.GTU.AND P0, PT, |R18|, +INF , PT ; @P0 BRA 0x123b0 ; ISETP.NE.AND P0, PT, R18, RZ, PT ; LOP3.LUT R0, R19, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x123c0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x123c0 ; DADD R6, R18, 2 ; BSYNC B0 ; DMUL R6, R6, 0.25 ; BSSY B0, 0x124a0 ; MOV R5, 0x40000000 ; DSETP.NEU.AND P0, PT, R18, 1, PT ; MOV R8, 0x12490 ; DADD R16, R32, c[0x2][0x30] ; FSEL R18, R6, RZ, P0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; FSEL R19, R7, 1.625, P0 ; DADD R10, -RZ, |R16| ; DADD R18, R26, R18 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R16.reuse, 2 ; BSSY B0, 0x125d0 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R16, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x125c0 ; DSETP.GTU.AND P0, PT, |R16|, +INF , PT ; @P0 BRA 0x125b0 ; ISETP.NE.AND P0, PT, R16, RZ, PT ; LOP3.LUT R0, R17, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x125c0 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x125c0 ; DADD R6, R16, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0x12730 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x38] ; DFMA R26, R10, -R6, c[0x2][0x38] ; DFMA R8, R8, R26, R10 ; FFMA R0, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA 0x12720 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R5, R7 ; IMAD.MOV.U32 R10, RZ, RZ, -0x66666666 ; MOV R6, 0x12710 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fb99999 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DADD R24, R24, c[0x2][0x30] ; BSSY B0, 0x127e0 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R16, 1, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R24| ; FSEL R16, R8, -1.5881868392106855534e-23, P0 ; FSEL R17, R9, 1.4499999284744262695, P0 ; MOV R8, 0x127d0 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R24.reuse, 2 ; BSSY B0, 0x12910 ; MOV R7, R5 ; DSETP.NEU.AND P0, PT, R24, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x12900 ; DSETP.GTU.AND P0, PT, |R24|, +INF , PT ; @P0 BRA 0x128f0 ; ISETP.NE.AND P0, PT, R24, RZ, PT ; LOP3.LUT R0, R25, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x12900 ; IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x12900 ; DADD R6, R24, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0x12a70 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x40] ; DFMA R26, R10, -R6, c[0x2][0x40] ; DFMA R8, R8, R26, R10 ; FFMA R0, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA 0x12a60 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R10, 0x33333333 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; MOV R6, 0x12a50 ; IMAD.MOV.U32 R7, RZ, RZ, 0x3fe33333 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DADD R18, R18, c[0x2][0x30] ; BSSY B0, 0x12b20 ; IMAD.MOV.U32 R6, RZ, RZ, RZ ; DSETP.NEU.AND P0, PT, R24, 1, PT ; IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; DADD R10, -RZ, |R18| ; FSEL R24, R8, 4.172325063223070174e-08, P0 ; FSEL R25, R9, 1.7749999761581420898, P0 ; MOV R8, 0x12b10 ; CALL.REL.NOINC 0x139c0 ; BSYNC B0 ; DADD R8, R18.reuse, 2 ; BSSY B0, 0x12c50 ; IMAD.MOV.U32 R7, RZ, RZ, R5 ; DSETP.NEU.AND P0, PT, R18, RZ, PT ; LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; @!P0 CS2R R6, SRZ ; @P1 BRA 0x12c40 ; DSETP.GTU.AND P0, PT, |R18|, +INF , PT ; @P0 BRA 0x12c30 ; ISETP.NE.AND P0, PT, R18, RZ, PT ; LOP3.LUT R0, R19, 0x7fffffff, RZ, 0xc0, !PT ; ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; @P0 BRA 0x12c40 ; MOV R6, 0x0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; BRA 0x12c40 ; DADD R6, R18, 2 ; BSYNC B0 ; MUFU.RCP64H R9, R7 ; IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; BSSY B2, 0x12db0 ; DFMA R10, R8, -R6, 1 ; DFMA R10, R10, R10, R10 ; DFMA R10, R8, R10, R8 ; DFMA R8, R10, -R6, 1 ; DFMA R8, R10, R8, R10 ; DMUL R10, R8, c[0x2][0x48] ; DFMA R26, R10, -R6, c[0x2][0x48] ; DFMA R8, R8, R26, R10 ; FFMA R0, RZ, R7, R9 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA 0x12da0 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; MOV R6, 0x12d90 ; IMAD.MOV.U32 R5, RZ, RZ, R7 ; MOV R7, 0x3fd33333 ; IMAD.MOV.U32 R10, RZ, RZ, 0x33333333 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DSETP.NEU.AND P0, PT, R18, 1, PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R17|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x12f80 ; DADD R18, R16, R24 ; FSEL R26, R8, 4.172325063223070174e-08, P0 ; FSEL R27, R9, 1.6499999761581420898, P0 ; DADD R18, R18, R26 ; MUFU.RCP64H R7, R19 ; DFMA R8, -R18, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R18, R8, 1 ; DFMA R6, R8, R6, R8 ; DMUL R30, R6, R16 ; DFMA R8, -R18, R30, R16 ; DFMA R30, R6, R8, R30 ; FFMA R0, RZ, R19, R31 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x12f70 ; IMAD.MOV.U32 R10, RZ, RZ, R16 ; MOV R5, R19 ; IMAD.MOV.U32 R7, RZ, RZ, R17 ; MOV R6, 0x12f50 ; IMAD.MOV.U32 R8, RZ, RZ, R18 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R30, RZ, RZ, R8 ; IMAD.MOV.U32 R31, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R19 ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; FSETP.GEU.AND P1, PT, |R25|, 6.5827683646048100446e-37, PT ; BSSY B2, 0x13120 ; DFMA R8, -R18, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R18, R8, 1 ; DFMA R8, R8, R6, R8 ; IMAD.MOV.U32 R6, RZ, RZ, R24 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; DMUL R16, R8, R6 ; DFMA R6, -R18, R16, R6 ; DFMA R16, R8, R6, R16 ; FFMA R0, RZ, R19, R17 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x13110 ; MOV R10, R24 ; IMAD.MOV.U32 R7, RZ, RZ, R25 ; MOV R6, 0x130f0 ; IMAD.MOV.U32 R8, RZ, RZ, R18 ; IMAD.MOV.U32 R5, RZ, RZ, R19 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R16, RZ, RZ, R8 ; IMAD.MOV.U32 R17, RZ, RZ, R5 ; BSYNC B2 ; MUFU.RCP64H R7, R19 ; MOV R6, 0x1 ; BSSY B2, 0x132b0 ; FSETP.GEU.AND P1, PT, |R27|, 6.5827683646048100446e-37, PT ; DFMA R8, -R18, R6, 1 ; DFMA R8, R8, R8, R8 ; DFMA R8, R6, R8, R6 ; DFMA R6, -R18, R8, 1 ; DFMA R10, R8, R6, R8 ; IMAD.MOV.U32 R8, RZ, RZ, R26 ; IMAD.MOV.U32 R9, RZ, RZ, R27 ; DMUL R6, R10, R8 ; DFMA R8, -R18, R6, R8 ; DFMA R8, R10, R8, R6 ; FFMA R0, RZ, R19, R9 ; FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; @P0 BRA P1, 0x132a0 ; IMAD.MOV.U32 R8, RZ, RZ, R18 ; MOV R7, R27 ; IMAD.MOV.U32 R5, RZ, RZ, R19 ; MOV R6, 0x13290 ; IMAD.MOV.U32 R10, RZ, RZ, R26 ; CALL.REL.NOINC 0x13360 ; IMAD.MOV.U32 R9, RZ, RZ, R5 ; BSYNC B2 ; DMUL R20, R20, R16 ; DFMA R20, R22, R30, R20 ; DFMA R16, R36, R8, R20 ; BSYNC B1 ; DSETP.GEU.AND P0, PT, |R12|, |R14|, PT ; IADD3 R2, P1, R4, c[0x0][0x170], RZ ; IADD3.X R3, R3, c[0x0][0x174], RZ, P1, !PT ; FSEL R4, R16, R28, !P0 ; FSEL R5, R17, R29, !P0 ; STG.E.64 [R2.64], R4 ; EXIT ; FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R52, RZ, RZ, R8.reuse ; LOP3.LUT R9, R5, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R53, RZ, RZ, R5 ; MOV R61, R7 ; IMAD.MOV.U32 R54, RZ, RZ, R8 ; LOP3.LUT R55, R9, 0x3ff00000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R60, RZ, RZ, R10 ; FSETP.GEU.AND P2, PT, |R61|.reuse, 1.469367938527859385e-39, PT ; IMAD.MOV.U32 R56, RZ, RZ, 0x1 ; LOP3.LUT R7, R61, 0x7ff00000, RZ, 0xc0, !PT ; IMAD.MOV.U32 R58, RZ, RZ, R60 ; LOP3.LUT R8, R5, 0x7ff00000, RZ, 0xc0, !PT ; @!P0 DMUL R54, R52, 8.98846567431157953865e+307 ; IMAD.MOV.U32 R5, RZ, RZ, 0x1ca00000 ; BSSY B0, 0x13980 ; ISETP.GE.U32.AND P1, PT, R7, R8, PT ; MUFU.RCP64H R57, R55 ; @!P2 LOP3.LUT R10, R53, 0x7ff00000, RZ, 0xc0, !PT ; @!P0 LOP3.LUT R8, R55, 0x7ff00000, RZ, 0xc0, !PT ; @!P2 ISETP.GE.U32.AND P3, PT, R7, R10, PT ; SEL R10, R5.reuse, 0x63400000, !P1 ; @!P2 SEL R9, R5, 0x63400000, !P3 ; LOP3.LUT R59, R10, 0x800fffff, R61.reuse, 0xf8, !PT ; @!P2 IMAD.MOV.U32 R10, RZ, RZ, RZ ; @!P2 LOP3.LUT R9, R9, 0x80000000, R61, 0xf8, !PT ; DFMA R62, R56, -R54, 1 ; @!P2 LOP3.LUT R11, R9, 0x100000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; DFMA R62, R62, R62, R62 ; @!P2 DFMA R58, R58, 2, -R10 ; DFMA R62, R56, R62, R56 ; DFMA R10, R62, -R54, 1 ; @!P2 LOP3.LUT R9, R59, 0x7ff00000, RZ, 0xc0, !PT ; DFMA R62, R62, R10, R62 ; DMUL R10, R62, R58 ; DFMA R56, R10, -R54, R58 ; DFMA R56, R62, R56, R10 ; IADD3 R10, R9, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R10, 0x7feffffe, PT ; IADD3 R10, R8, -0x1, RZ ; ISETP.GT.U32.OR P0, PT, R10, 0x7feffffe, P0 ; @P0 BRA 0x137f0 ; LOP3.LUT R8, R53, 0x7ff00000, RZ, 0xc0, !PT ; IADD3 R9, R7.reuse, -R8.reuse, RZ ; ISETP.GE.U32.AND P0, PT, R7, R8, PT ; IMNMX R9, R9, -0x46a00000, !PT ; SEL R5, R5, 0x63400000, !P0 ; IMNMX R8, R9, 0x46a00000, PT ; IMAD.IADD R7, R8, 0x1, -R5 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; IADD3 R9, R7, 0x7fe00000, RZ ; DMUL R10, R56, R8 ; FSETP.GTU.AND P0, PT, |R11|, 1.469367938527859385e-39, PT ; @P0 BRA 0x13970 ; DFMA R54, R56, -R54, R58 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; FSETP.NEU.AND P0, PT, R55.reuse, RZ, PT ; LOP3.LUT R5, R55, 0x80000000, R53, 0x48, !PT ; LOP3.LUT R9, R5, R9, RZ, 0xfc, !PT ; @!P0 BRA 0x13970 ; IMAD.MOV R53, RZ, RZ, -R7 ; DMUL.RP R8, R56, R8 ; IMAD.MOV.U32 R52, RZ, RZ, RZ ; IADD3 R7, -R7, -0x43300000, RZ ; DFMA R52, R10, -R52, R56 ; LOP3.LUT R5, R9, R5, RZ, 0x3c, !PT ; FSETP.NEU.AND P0, PT, |R53|, R7, PT ; FSEL R9, R5, R11, !P0 ; FSEL R8, R8, R10, !P0 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; MOV R10, R8 ; BRA 0x13970 ; DSETP.NAN.AND P0, PT, R60, R60, PT ; @P0 BRA 0x13940 ; DSETP.NAN.AND P0, PT, R52, R52, PT ; @P0 BRA 0x13900 ; ISETP.NE.AND P0, PT, R9, R8, PT ; IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; IMAD.MOV.U32 R11, RZ, RZ, -0x80000 ; @!P0 BRA 0x13970 ; ISETP.NE.AND P0, PT, R9, 0x7ff00000, PT ; LOP3.LUT R5, R61, 0x80000000, R53, 0x48, !PT ; ISETP.EQ.OR P0, PT, R8, RZ, !P0 ; @P0 LOP3.LUT R7, R5, 0x7ff00000, RZ, 0xfc, !PT ; @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; @P0 MOV R10, RZ ; @!P0 IMAD.MOV.U32 R11, RZ, RZ, R5 ; @P0 IMAD.MOV.U32 R11, RZ, RZ, R7 ; BRA 0x13970 ; LOP3.LUT R5, R53, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R10, RZ, RZ, R52 ; IMAD.MOV.U32 R11, RZ, RZ, R5 ; BRA 0x13970 ; LOP3.LUT R5, R61, 0x80000, RZ, 0xfc, !PT ; IMAD.MOV.U32 R10, RZ, RZ, R60 ; IMAD.MOV.U32 R11, RZ, RZ, R5 ; BSYNC B0 ; IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; MOV R8, R10 ; IMAD.MOV.U32 R5, RZ, RZ, R11 ; RET.REL.NODEC R6 0x0 ; SHF.R.U32.HI R7, RZ, 0x14, R11 ; ISETP.NE.AND P0, PT, R7, RZ, PT ; @!P0 DMUL R52, R10, 1.80143985094819840000e+16 ; @!P0 IMAD.MOV.U32 R11, RZ, RZ, R53 ; @!P0 LEA.HI R7, R53, 0xffffffca, RZ, 0xc ; @!P0 IMAD.MOV.U32 R10, RZ, RZ, R52 ; LOP3.LUT R11, R11, 0x800fffff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R56, RZ, RZ, R10 ; IMAD.MOV.U32 R10, RZ, RZ, RZ ; LOP3.LUT R11, R11, 0x3ff00000, RZ, 0xfc, !PT ; ISETP.GE.U32.AND P1, PT, R11, 0x3ff6a09f, PT ; MOV R57, R11 ; @P1 IADD3 R9, R57, -0x100000, RZ ; @P1 IMAD.MOV.U32 R57, RZ, RZ, R9 ; IADD3 R9, R7.reuse, -0x3ff, RZ ; @P1 IADD3 R9, R7, -0x3fe, RZ ; DADD R58, R56, 1 ; DADD R56, R56, -1 ; MUFU.RCP64H R11, R59 ; DFMA R54, -R58, R10, 1 ; DFMA R54, R54, R54, R54 ; DFMA R54, R10, R54, R10 ; DMUL R62, R54, R56 ; DFMA R62, R54, R56, R62 ; DADD R10, R56, -R62 ; DMUL R64, R62, R62 ; DADD R10, R10, R10 ; DFMA R10, R56, -R62, R10 ; IMAD.MOV.U32 R56, RZ, RZ, 0x7d2cafe2 ; IMAD.MOV.U32 R57, RZ, RZ, 0x3eb0f5ff ; DMUL R10, R54, R10 ; DFMA R56, R64, R56, c[0x2][0x58] ; DFMA R56, R64, R56, c[0x2][0x60] ; IADD3 R55, R11, 0x100000, RZ ; IMAD.MOV.U32 R54, RZ, RZ, R10 ; DFMA R56, R64, R56, c[0x2][0x68] ; DFMA R56, R64, R56, c[0x2][0x70] ; DFMA R56, R64, R56, c[0x2][0x78] ; DFMA R56, R64, R56, c[0x2][0x80] ; DFMA R60, R64, R56, c[0x2][0x88] ; DADD R58, -R60, c[0x2][0x88] ; DFMA R58, R64, R56, R58 ; DMUL R56, R62, R62 ; DFMA R64, R62, R62, -R56 ; DFMA R54, R62, R54, R64 ; DMUL R64, R62, R56 ; DFMA R52, R62, R56, -R64 ; DFMA R52, R10, R56, R52 ; DADD R56, RZ, R58 ; DFMA R54, R62, R54, R52 ; DADD R56, R56, c[0x2][0x90] ; DADD R52, R60, R56 ; DADD R60, R60, -R52 ; DMUL R58, R52, R64 ; DADD R60, R56, R60 ; DFMA R56, R52, R64, -R58 ; DFMA R54, R52, R54, R56 ; DFMA R60, R60, R64, R54 ; DADD R54, R58, R60 ; DADD R52, R62, R54 ; DADD R58, R58, -R54 ; DADD R62, R62, -R52 ; DADD R58, R60, R58 ; DADD R62, R54, R62 ; LOP3.LUT R54, R9, 0x80000000, RZ, 0x3c, !PT ; MOV R55, 0x43300000 ; DADD R58, R58, R62 ; DADD R54, R54, c[0x2][0x98] ; DADD R58, R10, R58 ; DADD R56, R52, R58 ; DFMA R10, R54, c[0x2][0xa0], R56 ; DADD R60, R52, -R56 ; DFMA R52, -R54, c[0x2][0xa0], R10 ; DADD R60, R58, R60 ; IMAD.MOV.U32 R58, RZ, RZ, 0x652b82fe ; MOV R59, 0x3ff71547 ; DADD R52, -R56, R52 ; DADD R60, R60, -R52 ; IMAD.MOV.U32 R53, RZ, RZ, R5 ; IMAD.MOV.U32 R52, RZ, RZ, R6 ; IMAD.SHL.U32 R5, R53.reuse, 0x2, RZ ; DFMA R60, R54, c[0x2][0xa8], R60 ; LOP3.LUT R6, R53, 0xff0fffff, RZ, 0xc0, !PT ; ISETP.GT.U32.AND P0, PT, R5, -0x2000001, PT ; DADD R54, R10, R60 ; SEL R7, R6, R53, P0 ; IMAD.MOV.U32 R6, RZ, RZ, R52 ; DADD R10, R10, -R54 ; DMUL R52, R54, R6 ; DADD R10, R60, R10 ; DFMA R54, R54, R6, -R52 ; DFMA R10, R10, R6, R54 ; IMAD.MOV.U32 R54, RZ, RZ, 0x69ce2bdf ; IMAD.MOV.U32 R55, RZ, RZ, 0x3e5ade15 ; DADD R6, R52, R10 ; DFMA R58, R6, R58, 6.75539944105574400000e+15 ; FSETP.GEU.AND P0, PT, |R7|, 4.1917929649353027344, PT ; DADD R60, R58, -6.75539944105574400000e+15 ; DFMA R56, R60, c[0x2][0xb0], R6 ; DFMA R56, R60, c[0x2][0xb8], R56 ; DFMA R54, R56, R54, c[0x2][0xc0] ; DFMA R54, R56, R54, c[0x2][0xc8] ; DFMA R54, R56, R54, c[0x2][0xd0] ; DFMA R54, R56, R54, c[0x2][0xd8] ; DFMA R54, R56, R54, c[0x2][0xe0] ; DFMA R54, R56, R54, c[0x2][0xe8] ; DFMA R54, R56, R54, c[0x2][0xf0] ; DFMA R54, R56, R54, c[0x2][0xf8] ; DFMA R54, R56, R54, c[0x2][0x100] ; DFMA R54, R56, R54, 1 ; DFMA R56, R56, R54, 1 ; IMAD R55, R58, 0x100000, R57 ; IMAD.MOV.U32 R54, RZ, RZ, R56 ; @!P0 BRA 0x141a0 ; FSETP.GEU.AND P1, PT, |R7|, 4.2275390625, PT ; DADD R54, R6, +INF ; DSETP.GEU.AND P0, PT, R6, RZ, PT ; FSEL R54, R54, RZ, P0 ; @!P1 LEA.HI R5, R58, R58, RZ, 0x1 ; FSEL R55, R55, RZ, P0 ; @!P1 SHF.R.S32.HI R5, RZ, 0x1, R5 ; @!P1 IMAD R57, R5, 0x100000, R57 ; @!P1 IADD3 R5, R58, -R5, RZ ; @!P1 IMAD.MOV.U32 R58, RZ, RZ, RZ ; @!P1 LEA R59, R5, 0x3ff00000, 0x14 ; @!P1 DMUL R54, R56, R58 ; LOP3.LUT R5, R55, 0x7fffffff, RZ, 0xc0, !PT ; DADD R6, R52, -R6 ; IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; ISETP.NE.AND P0, PT, R5, 0x7ff00000, PT ; DADD R6, R10, R6 ; ISETP.EQ.AND P0, PT, R54, RZ, !P0 ; @!P0 DFMA R54, R6, R54, R54 ; IMAD.MOV.U32 R6, RZ, RZ, R54 ; IMAD.MOV.U32 R5, RZ, RZ, R55 ; RET.REL.NODEC R8 0x0 ; BRA 0x14240; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000330fa_00000000-6_a9b385d32004ebe5994000f0a44fc78149530394.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2042: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2042: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z65__device_stub__Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .type _Z65__device_stub__Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, @function _Z65__device_stub__Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: .LFB2064: .cfi_startproc endbr64 subq $328, %rsp .cfi_def_cfa_offset 336 movq %rdi, 104(%rsp) movq %rsi, 96(%rsp) movq %rdx, 88(%rsp) movq %rcx, 80(%rsp) movq %r8, 72(%rsp) movq %r9, 64(%rsp) movsd %xmm0, 24(%rsp) movsd %xmm1, 16(%rsp) movsd %xmm2, 8(%rsp) movq 336(%rsp), %rax movq %rax, 56(%rsp) movq 344(%rsp), %rax movq %rax, 48(%rsp) movq 352(%rsp), %rax movq %rax, 40(%rsp) movq 360(%rsp), %rax movq %rax, 32(%rsp) movq %fs:40, %rax movq %rax, 312(%rsp) xorl %eax, %eax leaq 104(%rsp), %rax movq %rax, 176(%rsp) leaq 96(%rsp), %rax movq %rax, 184(%rsp) leaq 88(%rsp), %rax movq %rax, 192(%rsp) leaq 80(%rsp), %rax movq %rax, 200(%rsp) leaq 72(%rsp), %rax movq %rax, 208(%rsp) leaq 64(%rsp), %rax movq %rax, 216(%rsp) leaq 56(%rsp), %rax movq %rax, 224(%rsp) leaq 48(%rsp), %rax movq %rax, 232(%rsp) leaq 40(%rsp), %rax movq %rax, 240(%rsp) leaq 32(%rsp), %rax movq %rax, 248(%rsp) leaq 368(%rsp), %rax movq %rax, 256(%rsp) leaq 376(%rsp), %rax movq %rax, 264(%rsp) leaq 384(%rsp), %rax movq %rax, 272(%rsp) leaq 24(%rsp), %rax movq %rax, 280(%rsp) leaq 16(%rsp), %rax movq %rax, 288(%rsp) leaq 8(%rsp), %rax movq %rax, 296(%rsp) leaq 392(%rsp), %rax movq %rax, 304(%rsp) movl $1, 128(%rsp) movl $1, 132(%rsp) movl $1, 136(%rsp) movl $1, 140(%rsp) movl $1, 144(%rsp) movl $1, 148(%rsp) leaq 120(%rsp), %rcx leaq 112(%rsp), %rdx leaq 140(%rsp), %rsi leaq 128(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 312(%rsp), %rax subq %fs:40, %rax jne .L8 addq $328, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 120(%rsp) .cfi_def_cfa_offset 344 pushq 120(%rsp) .cfi_def_cfa_offset 352 leaq 192(%rsp), %r9 movq 156(%rsp), %rcx movl 164(%rsp), %r8d movq 144(%rsp), %rsi movl 152(%rsp), %edx leaq _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 336 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2064: .size _Z65__device_stub__Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .-_Z65__device_stub__Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .globl _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .type _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, @function _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: .LFB2065: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 72(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 72(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 72(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 72(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 pushq 72(%rsp) .cfi_def_cfa_offset 56 pushq 72(%rsp) .cfi_def_cfa_offset 64 pushq 72(%rsp) .cfi_def_cfa_offset 72 pushq 72(%rsp) .cfi_def_cfa_offset 80 call _Z65__device_stub__Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi addq $72, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2065: .size _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .-_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .globl _Z78__device_stub__Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .type _Z78__device_stub__Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, @function _Z78__device_stub__Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: .LFB2066: .cfi_startproc endbr64 subq $376, %rsp .cfi_def_cfa_offset 384 movq %rdi, 120(%rsp) movq %rsi, 112(%rsp) movq %rdx, 104(%rsp) movq %rcx, 96(%rsp) movq %r8, 88(%rsp) movq %r9, 80(%rsp) movsd %xmm0, 16(%rsp) movsd %xmm1, 8(%rsp) movsd %xmm2, (%rsp) movq 384(%rsp), %rax movq %rax, 72(%rsp) movq 392(%rsp), %rax movq %rax, 64(%rsp) movq 400(%rsp), %rax movq %rax, 56(%rsp) movq 408(%rsp), %rax movq %rax, 48(%rsp) movq 416(%rsp), %rax movq %rax, 40(%rsp) movq 424(%rsp), %rax movq %rax, 32(%rsp) movq 432(%rsp), %rax movq %rax, 24(%rsp) movq %fs:40, %rax movq %rax, 360(%rsp) xorl %eax, %eax leaq 120(%rsp), %rax movq %rax, 192(%rsp) leaq 112(%rsp), %rax movq %rax, 200(%rsp) leaq 104(%rsp), %rax movq %rax, 208(%rsp) leaq 96(%rsp), %rax movq %rax, 216(%rsp) leaq 88(%rsp), %rax movq %rax, 224(%rsp) leaq 80(%rsp), %rax movq %rax, 232(%rsp) leaq 72(%rsp), %rax movq %rax, 240(%rsp) leaq 64(%rsp), %rax movq %rax, 248(%rsp) leaq 56(%rsp), %rax movq %rax, 256(%rsp) leaq 48(%rsp), %rax movq %rax, 264(%rsp) leaq 40(%rsp), %rax movq %rax, 272(%rsp) leaq 32(%rsp), %rax movq %rax, 280(%rsp) leaq 24(%rsp), %rax movq %rax, 288(%rsp) leaq 440(%rsp), %rax movq %rax, 296(%rsp) leaq 448(%rsp), %rax movq %rax, 304(%rsp) leaq 456(%rsp), %rax movq %rax, 312(%rsp) leaq 16(%rsp), %rax movq %rax, 320(%rsp) leaq 8(%rsp), %rax movq %rax, 328(%rsp) movq %rsp, %rax movq %rax, 336(%rsp) leaq 464(%rsp), %rax movq %rax, 344(%rsp) movl $1, 144(%rsp) movl $1, 148(%rsp) movl $1, 152(%rsp) movl $1, 156(%rsp) movl $1, 160(%rsp) movl $1, 164(%rsp) leaq 136(%rsp), %rcx leaq 128(%rsp), %rdx leaq 156(%rsp), %rsi leaq 144(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 360(%rsp), %rax subq %fs:40, %rax jne .L16 addq $376, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 136(%rsp) .cfi_def_cfa_offset 392 pushq 136(%rsp) .cfi_def_cfa_offset 400 leaq 208(%rsp), %r9 movq 172(%rsp), %rcx movl 180(%rsp), %r8d movq 160(%rsp), %rsi movl 168(%rsp), %edx leaq _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 384 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2066: .size _Z78__device_stub__Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .-_Z78__device_stub__Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .globl _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .type _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, @function _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: .LFB2067: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 movl 104(%rsp), %eax pushq %rax .cfi_def_cfa_offset 56 pushq 104(%rsp) .cfi_def_cfa_offset 64 pushq 104(%rsp) .cfi_def_cfa_offset 72 pushq 104(%rsp) .cfi_def_cfa_offset 80 pushq 104(%rsp) .cfi_def_cfa_offset 88 pushq 104(%rsp) .cfi_def_cfa_offset 96 pushq 104(%rsp) .cfi_def_cfa_offset 104 pushq 104(%rsp) .cfi_def_cfa_offset 112 call _Z78__device_stub__Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi addq $104, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2067: .size _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .-_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .globl _Z89__device_stub__Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .type _Z89__device_stub__Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function _Z89__device_stub__Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi: .LFB2068: .cfi_startproc endbr64 subq $456, %rsp .cfi_def_cfa_offset 464 movq %rdi, 168(%rsp) movq %rsi, 160(%rsp) movq %rdx, 152(%rsp) movq %rcx, 144(%rsp) movq %r8, 136(%rsp) movq %r9, 128(%rsp) movsd %xmm0, 24(%rsp) movsd %xmm1, 16(%rsp) movsd %xmm2, 8(%rsp) movq 464(%rsp), %rax movq %rax, 120(%rsp) movq 472(%rsp), %rax movq %rax, 112(%rsp) movq 480(%rsp), %rax movq %rax, 104(%rsp) movq 488(%rsp), %rax movq %rax, 96(%rsp) movq 496(%rsp), %rax movq %rax, 88(%rsp) movq 504(%rsp), %rax movq %rax, 80(%rsp) movq 512(%rsp), %rax movq %rax, 72(%rsp) movq 520(%rsp), %rax movq %rax, 64(%rsp) movq 528(%rsp), %rax movq %rax, 56(%rsp) movq 536(%rsp), %rax movq %rax, 48(%rsp) movq 544(%rsp), %rax movq %rax, 40(%rsp) movq 552(%rsp), %rax movq %rax, 32(%rsp) movq %fs:40, %rax movq %rax, 440(%rsp) xorl %eax, %eax leaq 168(%rsp), %rax movq %rax, 240(%rsp) leaq 160(%rsp), %rax movq %rax, 248(%rsp) leaq 152(%rsp), %rax movq %rax, 256(%rsp) leaq 144(%rsp), %rax movq %rax, 264(%rsp) leaq 136(%rsp), %rax movq %rax, 272(%rsp) leaq 128(%rsp), %rax movq %rax, 280(%rsp) leaq 120(%rsp), %rax movq %rax, 288(%rsp) leaq 112(%rsp), %rax movq %rax, 296(%rsp) leaq 104(%rsp), %rax movq %rax, 304(%rsp) leaq 96(%rsp), %rax movq %rax, 312(%rsp) leaq 88(%rsp), %rax movq %rax, 320(%rsp) leaq 80(%rsp), %rax movq %rax, 328(%rsp) leaq 72(%rsp), %rax movq %rax, 336(%rsp) leaq 64(%rsp), %rax movq %rax, 344(%rsp) leaq 56(%rsp), %rax movq %rax, 352(%rsp) leaq 48(%rsp), %rax movq %rax, 360(%rsp) leaq 40(%rsp), %rax movq %rax, 368(%rsp) leaq 32(%rsp), %rax movq %rax, 376(%rsp) leaq 560(%rsp), %rax movq %rax, 384(%rsp) leaq 568(%rsp), %rax movq %rax, 392(%rsp) leaq 576(%rsp), %rax movq %rax, 400(%rsp) leaq 24(%rsp), %rax movq %rax, 408(%rsp) leaq 16(%rsp), %rax movq %rax, 416(%rsp) leaq 8(%rsp), %rax movq %rax, 424(%rsp) leaq 584(%rsp), %rax movq %rax, 432(%rsp) movl $1, 192(%rsp) movl $1, 196(%rsp) movl $1, 200(%rsp) movl $1, 204(%rsp) movl $1, 208(%rsp) movl $1, 212(%rsp) leaq 184(%rsp), %rcx leaq 176(%rsp), %rdx leaq 204(%rsp), %rsi leaq 192(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L23 .L19: movq 440(%rsp), %rax subq %fs:40, %rax jne .L24 addq $456, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state pushq 184(%rsp) .cfi_def_cfa_offset 472 pushq 184(%rsp) .cfi_def_cfa_offset 480 leaq 256(%rsp), %r9 movq 220(%rsp), %rcx movl 228(%rsp), %r8d movq 208(%rsp), %rsi movl 216(%rsp), %edx leaq _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 464 jmp .L19 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE2068: .size _Z89__device_stub__Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z89__device_stub__Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .globl _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .type _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi: .LFB2069: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 136(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 136(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 136(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 136(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 pushq 136(%rsp) .cfi_def_cfa_offset 56 pushq 136(%rsp) .cfi_def_cfa_offset 64 pushq 136(%rsp) .cfi_def_cfa_offset 72 pushq 136(%rsp) .cfi_def_cfa_offset 80 pushq 136(%rsp) .cfi_def_cfa_offset 88 pushq 136(%rsp) .cfi_def_cfa_offset 96 pushq 136(%rsp) .cfi_def_cfa_offset 104 pushq 136(%rsp) .cfi_def_cfa_offset 112 pushq 136(%rsp) .cfi_def_cfa_offset 120 pushq 136(%rsp) .cfi_def_cfa_offset 128 pushq 136(%rsp) .cfi_def_cfa_offset 136 pushq 136(%rsp) .cfi_def_cfa_offset 144 call _Z89__device_stub__Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi addq $136, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2069: .size _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi" .align 8 .LC1: .string "_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi" .align 8 .LC2: .string "_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2071: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2071: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .p2align 2 ; -- Begin function _Z24weno_onesided_derivativeddddd .type _Z24weno_onesided_derivativeddddd,@function _Z24weno_onesided_derivativeddddd: ; @_Z24weno_onesided_derivativeddddd ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) s_or_saveexec_b32 s0, -1 scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill s_mov_b32 exec_lo, s0 v_writelane_b32 v40, s34, 0 v_writelane_b32 v40, s35, 1 v_writelane_b32 v40, s36, 2 v_writelane_b32 v40, s37, 3 v_writelane_b32 v40, s38, 4 v_writelane_b32 v40, s39, 5 v_writelane_b32 v40, s40, 6 v_writelane_b32 v40, s41, 7 v_writelane_b32 v40, s42, 8 v_writelane_b32 v40, s43, 9 v_writelane_b32 v40, s44, 10 v_writelane_b32 v40, s45, 11 v_writelane_b32 v40, s46, 12 v_writelane_b32 v40, s47, 13 v_writelane_b32 v40, s48, 14 v_writelane_b32 v40, s49, 15 v_writelane_b32 v40, s50, 16 v_writelane_b32 v40, s51, 17 v_writelane_b32 v40, s52, 18 v_writelane_b32 v40, s53, 19 v_writelane_b32 v40, s54, 20 v_writelane_b32 v40, s55, 21 v_writelane_b32 v40, s56, 22 v_writelane_b32 v40, s57, 23 v_writelane_b32 v40, s58, 24 v_writelane_b32 v40, s59, 25 v_writelane_b32 v40, s60, 26 v_writelane_b32 v40, s61, 27 v_writelane_b32 v40, s30, 28 v_writelane_b32 v40, s31, 29 s_mov_b32 s1, 0xbff2aaaa s_mov_b32 s0, 0xaaaaaaab s_mov_b32 s29, 0x3fd55555 v_mul_f64 v[10:11], v[2:3], s[0:1] s_mov_b32 s28, 0x55555555 s_mov_b32 s3, 0x3ffd5555 s_mov_b32 s2, s28 v_fma_f64 v[16:17], v[2:3], -2.0, v[0:1] s_mov_b32 s1, 0x3feaaaaa s_mov_b32 s49, 0x3fba6564 s_mov_b32 s48, 0x968915a9 s_mov_b32 s57, 0x3fbdee67 s_mov_b32 s56, 0x4222de17 s_mov_b32 s51, 0x3fbe25e4 s_mov_b32 s50, 0x3abe935a s_mov_b32 s39, 0x3fe62e42 s_mov_b32 s38, 0xfefa39ef s_mov_b32 s53, 0x3fc110ef s_mov_b32 s52, 0x47e6c9c2 s_mov_b32 s55, 0x3fc3b13b s_mov_b32 s54, 0xcfa74449 s_mov_b32 s43, 0x3c7abc9e s_mov_b32 s42, 0x3b39803f s_mov_b32 s47, 0x3fc745d1 s_mov_b32 s46, 0x71bf3c30 s_mov_b32 s45, 0x3fcc71c7 s_mov_b32 s44, 0x1c7792ce s_mov_b32 s41, 0x3fd24924 s_mov_b32 s40, 0x924920da s_mov_b32 s37, 0x3fd99999 s_mov_b32 s36, 0x9999999c s_mov_b32 s35, 0xbfe55555 s_mov_b32 s34, s28 s_mov_b32 s31, 0x3c8543b0 s_mov_b32 s30, 0xd5df274d s_mov_b32 s25, 0x3ff71547 s_mov_b32 s24, 0x652b82fe s_mov_b32 s17, 0xbfe62e42 s_mov_b32 s16, s38 s_mov_b32 s19, 0xbc7abc9e s_mov_b32 s18, s42 v_fma_f64 v[10:11], v[0:1], s[28:29], v[10:11] s_mov_b32 s21, 0x3e928af3 s_mov_b32 s20, 0xfca7ab0c s_mov_b32 s27, 0x3e5ade15 v_add_f64 v[16:17], v[16:17], v[4:5] s_mov_b32 s26, 0x6a5dcb37 s_mov_b32 s23, 0x3ec71dee s_mov_b32 s22, 0x623fde64 s_mov_b32 s15, 0x3efa0199 s_mov_b32 s14, 0x7c89e6b0 s_mov_b32 s13, 0x3f2a01a0 s_mov_b32 s12, 0x14761f6e s_mov_b32 s11, 0x3f56c16c s_mov_b32 s10, 0x1852b7b0 s_mov_b32 s9, 0x3f811111 s_mov_b32 s8, 0x11122322 s_mov_b32 s5, 0x3fc55555 s_mov_b32 s4, 0x55555511 s_mov_b32 s7, 0x3fe00000 s_mov_b32 s6, 11 v_fma_f64 v[0:1], v[2:3], -4.0, v[0:1] s_mov_b32 s59, 0x3ff15555 s_mov_b32 s58, s28 s_mov_b32 s61, 0x3eb0c6f7 s_mov_b32 s60, 0xa0b5ed8d s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[10:11], v[4:5], s[2:3], v[10:11] s_mov_b32 s3, 0xbfc55555 v_mul_f64 v[12:13], v[2:3], s[2:3] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_frexp_mant_f64_e64 v[18:19], |v[16:17]| v_fma_f64 v[0:1], v[4:5], 0x40080000, v[0:1] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], v[4:5], s[0:1], v[12:13] v_fma_f64 v[14:15], v[6:7], s[28:29], v[12:13] v_mul_f64 v[12:13], v[6:7], s[0:1] s_mov_b32 s1, 0x3fb99999 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[12:13], v[4:5], s[28:29], v[12:13] s_mov_b32 s29, 0x3fe55555 v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_fma_f64 v[12:13], v[8:9], s[2:3], v[12:13] s_mov_b32 s3, 0x3fa55555 s_mov_b32 s2, 0x555502a1 v_cndmask_b32_e64 v20, 0, 1, vcc_lo v_ldexp_f64 v[18:19], v[18:19], v20 v_frexp_exp_i32_f64_e32 v20, v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[18:19], 1.0 v_subrev_co_ci_u32_e32 v32, vcc_lo, 0, v20, vcc_lo v_add_f64 v[20:21], v[18:19], -1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[22:23], -1.0 v_add_f64 v[18:19], v[18:19], -v[24:25] v_rcp_f64_e32 v[24:25], v[22:23] s_waitcnt_depctr 0xfff v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25] v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25] v_mul_f64 v[26:27], v[20:21], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[28:29], v[22:23], v[26:27] v_fma_f64 v[22:23], v[26:27], v[22:23], -v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[26:27], v[18:19], v[22:23] v_add_f64 v[22:23], v[28:29], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[30:31], v[20:21], -v[22:23] v_add_f64 v[28:29], v[22:23], -v[28:29] v_add_f64 v[20:21], v[20:21], -v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[18:19], v[28:29], -v[18:19] v_cvt_f64_i32_e32 v[28:29], v32 v_add_f64 v[20:21], v[20:21], -v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[18:19], v[20:21] v_add_f64 v[18:19], v[30:31], v[18:19] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[30:31], v[28:29], s[38:39] v_mul_f64 v[18:19], v[24:25], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[32:33], v[28:29], s[38:39], -v[30:31] v_add_f64 v[20:21], v[26:27], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[28:29], v[28:29], s[42:43], v[32:33] v_add_f64 v[22:23], v[20:21], -v[26:27] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[32:33], v[30:31], v[28:29] v_add_f64 v[18:19], v[18:19], -v[22:23] v_mul_f64 v[22:23], v[20:21], v[20:21] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[30:31], v[32:33], -v[30:31] v_add_f64 v[26:27], v[18:19], v[18:19] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_fma_f64 v[24:25], v[20:21], v[20:21], -v[22:23] v_ldexp_f64 v[34:35], v[18:19], 1 v_add_f64 v[28:29], v[28:29], -v[30:31] v_ldexp_f64 v[30:31], v[20:21], 1 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[20:21], v[26:27], v[24:25] v_add_f64 v[26:27], v[22:23], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[26:27], -v[22:23] v_mul_f64 v[36:37], v[20:21], v[26:27] v_add_f64 v[22:23], v[24:25], -v[22:23] v_fma_f64 v[24:25], v[26:27], s[56:57], s[48:49] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[38:39], v[26:27], v[20:21], -v[36:37] v_fma_f64 v[24:25], v[26:27], v[24:25], s[50:51] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[18:19], v[26:27], v[18:19], v[38:39] v_fma_f64 v[24:25], v[26:27], v[24:25], s[52:53] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[18:19], v[22:23], v[20:21], v[18:19] v_fma_f64 v[24:25], v[26:27], v[24:25], s[54:55] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[36:37], v[18:19] v_fma_f64 v[24:25], v[26:27], v[24:25], s[46:47] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[36:37], v[20:21], -v[36:37] v_fma_f64 v[24:25], v[26:27], v[24:25], s[44:45] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[18:19], -v[36:37] v_fma_f64 v[24:25], v[26:27], v[24:25], s[40:41] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[26:27], v[24:25], s[36:37] v_mul_f64 v[36:37], v[26:27], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[26:27], v[24:25], -v[36:37] v_fma_f64 v[22:23], v[22:23], v[24:25], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[36:37], v[22:23] v_add_f64 v[26:27], v[24:25], -v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[22:23], -v[26:27] v_add_f64 v[26:27], v[24:25], s[28:29] v_add_f64 v[22:23], v[22:23], s[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[36:37], v[26:27], s[34:35] v_add_f64 v[24:25], v[24:25], -v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[22:23], v[24:25] v_add_f64 v[24:25], v[26:27], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[26:27], -v[24:25] v_add_f64 v[22:23], v[22:23], v[26:27] v_mul_f64 v[26:27], v[20:21], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[36:37], v[20:21], v[24:25], -v[26:27] v_fma_f64 v[20:21], v[20:21], v[22:23], v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[18:19], v[24:25], v[20:21] v_add_f64 v[20:21], v[26:27], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[20:21], -v[26:27] v_add_f64 v[18:19], v[18:19], -v[22:23] v_add_f64 v[22:23], v[30:31], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[34:35], v[18:19] v_add_f64 v[24:25], v[22:23], -v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], -v[24:25] v_add_f64 v[18:19], v[18:19], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[22:23], v[18:19] v_add_f64 v[22:23], v[20:21], -v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[18:19], -v[22:23] v_add_f64 v[22:23], v[32:33], v[20:21] v_add_f64 v[24:25], v[22:23], -v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_f64 v[26:27], v[22:23], -v[24:25] v_add_f64 v[20:21], v[20:21], -v[24:25] v_add_f64 v[24:25], v[28:29], v[18:19] v_add_f64 v[26:27], v[32:33], -v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[20:21], v[20:21], v[26:27] v_add_f64 v[26:27], v[24:25], -v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[24:25], v[20:21] v_add_f64 v[30:31], v[24:25], -v[26:27] v_add_f64 v[18:19], v[18:19], -v[26:27] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[24:25], v[22:23], v[20:21] v_add_f64 v[28:29], v[28:29], -v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[24:25], -v[22:23] v_add_f64 v[18:19], v[18:19], v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], -v[22:23] v_add_f64 v[18:19], v[18:19], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[24:25], v[18:19] v_add_f64 v[22:23], v[20:21], -v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[18:19], -v[22:23] v_add_f64 v[22:23], v[20:21], v[20:21] v_fma_f64 v[20:21], v[20:21], 2.0, -v[22:23] v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[18:19], 2.0, v[20:21] v_add_f64 v[20:21], v[22:23], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[20:21], -v[22:23] v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22 v_mul_f64 v[22:23], v[20:21], s[24:25] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[20:21]| v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[20:21] v_add_f64 v[18:19], v[18:19], -v[24:25] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_rndne_f64_e32 v[22:23], v[22:23] v_dual_cndmask_b32 v19, 0, v19 :: v_dual_cndmask_b32 v18, 0, v18 v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[20:21] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[22:23], s[16:17], v[20:21] v_fma_f64 v[24:25], v[22:23], s[18:19], v[24:25] v_cvt_i32_f64_e32 v22, v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[24:25], s[26:27], s[20:21] v_fma_f64 v[26:27], v[24:25], v[26:27], s[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[24:25], v[26:27], s[14:15] v_fma_f64 v[26:27], v[24:25], v[26:27], s[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[24:25], v[26:27], s[10:11] v_fma_f64 v[26:27], v[24:25], v[26:27], s[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[24:25], v[26:27], s[2:3] v_fma_f64 v[26:27], v[24:25], v[26:27], s[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[24:25], v[26:27], s[6:7] v_fma_f64 v[26:27], v[24:25], v[26:27], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[24:25], v[26:27], 1.0 v_ldexp_f64 v[22:23], v[24:25], v22 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v23, 0x7ff00000, v23, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo v_cndmask_b32_e64 v21, 0, v23, s0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v20, 0, v22, vcc_lo v_cmp_neq_f64_e64 s0, 0, v[16:17] v_fma_f64 v[18:19], v[20:21], v[18:19], v[20:21] v_cmp_class_f64_e64 vcc_lo, v[20:21], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_dual_cndmask_b32 v19, v19, v21 :: v_dual_cndmask_b32 v18, v18, v20 v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[16:17]| v_frexp_mant_f64_e64 v[20:21], |v[0:1]| v_mul_f64 v[16:17], v[4:5], 0x40080000 v_mul_f64 v[18:19], |v[18:19]|, s[58:59] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v19, 0x7ff00000, v19, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo v_cndmask_b32_e32 v18, 0, v18, vcc_lo v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[20:21] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v19, 0, v19, s0 v_cndmask_b32_e64 v22, 0, 1, vcc_lo v_ldexp_f64 v[20:21], v[20:21], v22 v_frexp_exp_i32_f64_e32 v22, v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[24:25], v[20:21], 1.0 v_subrev_co_ci_u32_e32 v34, vcc_lo, 0, v22, vcc_lo v_add_f64 v[22:23], v[20:21], -1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[24:25], -1.0 v_add_f64 v[20:21], v[20:21], -v[26:27] v_rcp_f64_e32 v[26:27], v[24:25] s_waitcnt_depctr 0xfff v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27] v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27] v_mul_f64 v[28:29], v[22:23], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[30:31], v[24:25], v[28:29] v_fma_f64 v[24:25], v[28:29], v[24:25], -v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[28:29], v[20:21], v[24:25] v_add_f64 v[24:25], v[30:31], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[32:33], v[22:23], -v[24:25] v_add_f64 v[30:31], v[24:25], -v[30:31] v_add_f64 v[22:23], v[22:23], -v[32:33] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[20:21], v[30:31], -v[20:21] v_cvt_f64_i32_e32 v[30:31], v34 v_add_f64 v[22:23], v[22:23], -v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], v[22:23] v_add_f64 v[20:21], v[32:33], v[20:21] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[32:33], v[30:31], s[38:39] v_mul_f64 v[20:21], v[26:27], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[34:35], v[30:31], s[38:39], -v[32:33] v_add_f64 v[22:23], v[28:29], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[30:31], v[30:31], s[42:43], v[34:35] v_add_f64 v[24:25], v[22:23], -v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[34:35], v[32:33], v[30:31] v_add_f64 v[20:21], v[20:21], -v[24:25] v_mul_f64 v[24:25], v[22:23], v[22:23] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[32:33], v[34:35], -v[32:33] v_add_f64 v[28:29], v[20:21], v[20:21] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_fma_f64 v[26:27], v[22:23], v[22:23], -v[24:25] v_ldexp_f64 v[36:37], v[20:21], 1 v_add_f64 v[30:31], v[30:31], -v[32:33] v_ldexp_f64 v[32:33], v[22:23], 1 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[22:23], v[28:29], v[26:27] v_add_f64 v[28:29], v[24:25], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[24:25], v[28:29], -v[24:25] v_mul_f64 v[38:39], v[22:23], v[28:29] v_add_f64 v[24:25], v[26:27], -v[24:25] v_fma_f64 v[26:27], v[28:29], s[56:57], s[48:49] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[48:49], v[28:29], v[22:23], -v[38:39] v_fma_f64 v[26:27], v[28:29], v[26:27], s[50:51] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[20:21], v[28:29], v[20:21], v[48:49] v_fma_f64 v[26:27], v[28:29], v[26:27], s[52:53] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[20:21], v[24:25], v[22:23], v[20:21] v_fma_f64 v[26:27], v[28:29], v[26:27], s[54:55] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[38:39], v[20:21] v_fma_f64 v[26:27], v[28:29], v[26:27], s[46:47] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[38:39], v[22:23], -v[38:39] v_fma_f64 v[26:27], v[28:29], v[26:27], s[44:45] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[20:21], -v[38:39] v_fma_f64 v[26:27], v[28:29], v[26:27], s[40:41] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[28:29], v[26:27], s[36:37] v_mul_f64 v[38:39], v[28:29], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[28:29], v[26:27], -v[38:39] v_fma_f64 v[24:25], v[24:25], v[26:27], v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[38:39], v[24:25] v_add_f64 v[28:29], v[26:27], -v[38:39] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[24:25], v[24:25], -v[28:29] v_add_f64 v[28:29], v[26:27], s[28:29] v_add_f64 v[24:25], v[24:25], s[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[38:39], v[28:29], s[34:35] v_add_f64 v[26:27], v[26:27], -v[38:39] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[24:25], v[26:27] v_add_f64 v[26:27], v[28:29], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[28:29], v[28:29], -v[26:27] v_add_f64 v[24:25], v[24:25], v[28:29] v_mul_f64 v[28:29], v[22:23], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[38:39], v[22:23], v[26:27], -v[28:29] v_fma_f64 v[22:23], v[22:23], v[24:25], v[38:39] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[20:21], v[26:27], v[22:23] v_add_f64 v[22:23], v[28:29], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[22:23], -v[28:29] v_add_f64 v[20:21], v[20:21], -v[24:25] v_add_f64 v[24:25], v[32:33], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[36:37], v[20:21] v_add_f64 v[26:27], v[24:25], -v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[22:23], -v[26:27] v_add_f64 v[20:21], v[20:21], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[24:25], v[20:21] v_add_f64 v[24:25], v[22:23], -v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], -v[24:25] v_add_f64 v[24:25], v[34:35], v[22:23] v_add_f64 v[26:27], v[24:25], -v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_f64 v[28:29], v[24:25], -v[26:27] v_add_f64 v[22:23], v[22:23], -v[26:27] v_add_f64 v[26:27], v[30:31], v[20:21] v_add_f64 v[28:29], v[34:35], -v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[22:23], v[22:23], v[28:29] v_add_f64 v[28:29], v[26:27], -v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[26:27], v[22:23] v_add_f64 v[32:33], v[26:27], -v[28:29] v_add_f64 v[20:21], v[20:21], -v[28:29] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[26:27], v[24:25], v[22:23] v_add_f64 v[30:31], v[30:31], -v[32:33] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[24:25], v[26:27], -v[24:25] v_add_f64 v[20:21], v[20:21], v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[22:23], -v[24:25] v_add_f64 v[20:21], v[20:21], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[26:27], v[20:21] v_add_f64 v[24:25], v[22:23], -v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], -v[24:25] v_add_f64 v[24:25], v[22:23], v[22:23] v_fma_f64 v[22:23], v[22:23], 2.0, -v[24:25] v_cmp_class_f64_e64 vcc_lo, v[24:25], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[20:21], 2.0, v[22:23] v_add_f64 v[22:23], v[24:25], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[22:23], -v[24:25] v_dual_cndmask_b32 v23, v23, v25 :: v_dual_cndmask_b32 v22, v22, v24 v_mul_f64 v[24:25], v[22:23], s[24:25] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]| v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[22:23] v_add_f64 v[20:21], v[20:21], -v[26:27] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_rndne_f64_e32 v[24:25], v[24:25] v_dual_cndmask_b32 v21, 0, v21 :: v_dual_cndmask_b32 v20, 0, v20 v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[22:23] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[24:25], s[16:17], v[22:23] v_fma_f64 v[26:27], v[24:25], s[18:19], v[26:27] v_cvt_i32_f64_e32 v24, v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], s[26:27], s[20:21] v_fma_f64 v[28:29], v[26:27], v[28:29], s[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], s[14:15] v_fma_f64 v[28:29], v[26:27], v[28:29], s[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], s[10:11] v_fma_f64 v[28:29], v[26:27], v[28:29], s[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], s[2:3] v_fma_f64 v[28:29], v[26:27], v[28:29], s[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], s[6:7] v_fma_f64 v[28:29], v[26:27], v[28:29], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[26:27], v[28:29], 1.0 v_ldexp_f64 v[24:25], v[26:27], v24 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v25, 0x7ff00000, v25, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo v_cndmask_b32_e32 v22, 0, v24, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v23, 0, v25, s0 v_cmp_neq_f64_e64 s0, 0, v[0:1] v_fma_f64 v[20:21], v[22:23], v[20:21], v[22:23] v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22 v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]| v_ldexp_f64 v[20:21], |v[20:21]|, -2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v21, 0x7ff00000, v21, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v0, 0, v20, vcc_lo v_cndmask_b32_e64 v1, 0, v21, s0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_add_f64 v[0:1], v[18:19], v[0:1] v_fma_f64 v[18:19], v[4:5], -2.0, v[2:3] v_add_f64 v[2:3], v[2:3], -v[6:7] v_fma_f64 v[4:5], v[6:7], -2.0, v[4:5] v_add_f64 v[0:1], v[0:1], s[60:61] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[18:19], v[18:19], v[6:7] v_fma_f64 v[6:7], v[6:7], -4.0, v[16:17] v_add_f64 v[4:5], v[4:5], v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_frexp_mant_f64_e64 v[20:21], |v[18:19]| v_add_f64 v[6:7], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[20:21] v_frexp_mant_f64_e64 v[8:9], |v[6:7]| v_cndmask_b32_e64 v22, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[20:21], v[20:21], v22 v_frexp_exp_i32_f64_e32 v22, v[18:19] v_add_f64 v[24:25], v[20:21], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_subrev_co_ci_u32_e32 v34, vcc_lo, 0, v22, vcc_lo v_add_f64 v[22:23], v[20:21], -1.0 v_add_f64 v[26:27], v[24:25], -1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], -v[26:27] v_rcp_f64_e32 v[26:27], v[24:25] s_waitcnt_depctr 0xfff v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0 v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0 v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[28:29], v[22:23], v[26:27] v_mul_f64 v[30:31], v[24:25], v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[28:29], v[24:25], -v[30:31] v_fma_f64 v[20:21], v[28:29], v[20:21], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[30:31], v[20:21] v_add_f64 v[32:33], v[22:23], -v[24:25] v_add_f64 v[30:31], v[24:25], -v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[22:23], -v[32:33] v_add_f64 v[20:21], v[30:31], -v[20:21] v_cvt_f64_i32_e32 v[30:31], v34 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[22:23], -v[24:25] v_add_f64 v[20:21], v[20:21], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[20:21], v[32:33], v[20:21] v_mul_f64 v[32:33], v[30:31], s[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[20:21], v[26:27], v[20:21] v_fma_f64 v[34:35], v[30:31], s[38:39], -v[32:33] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[28:29], v[20:21] v_fma_f64 v[30:31], v[30:31], s[42:43], v[34:35] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[24:25], v[22:23], -v[28:29] v_add_f64 v[34:35], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[20:21], v[20:21], -v[24:25] v_mul_f64 v[24:25], v[22:23], v[22:23] v_add_f64 v[32:33], v[34:35], -v[32:33] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[28:29], v[20:21], v[20:21] v_fma_f64 v[26:27], v[22:23], v[22:23], -v[24:25] v_ldexp_f64 v[36:37], v[20:21], 1 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[30:31], v[30:31], -v[32:33] v_ldexp_f64 v[32:33], v[22:23], 1 v_fma_f64 v[26:27], v[22:23], v[28:29], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[28:29], v[24:25], v[26:27] v_add_f64 v[24:25], v[28:29], -v[24:25] v_mul_f64 v[38:39], v[22:23], v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[24:25], v[26:27], -v[24:25] v_fma_f64 v[26:27], v[28:29], s[56:57], s[48:49] v_fma_f64 v[48:49], v[28:29], v[22:23], -v[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[28:29], v[26:27], s[50:51] v_fma_f64 v[20:21], v[28:29], v[20:21], v[48:49] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[28:29], v[26:27], s[52:53] v_fma_f64 v[20:21], v[24:25], v[22:23], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[28:29], v[26:27], s[54:55] v_add_f64 v[22:23], v[38:39], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[28:29], v[26:27], s[46:47] v_add_f64 v[38:39], v[22:23], -v[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[28:29], v[26:27], s[44:45] v_add_f64 v[20:21], v[20:21], -v[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[28:29], v[26:27], s[40:41] v_fma_f64 v[26:27], v[28:29], v[26:27], s[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[38:39], v[28:29], v[26:27] v_fma_f64 v[28:29], v[28:29], v[26:27], -v[38:39] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[24:25], v[26:27], v[28:29] v_add_f64 v[26:27], v[38:39], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[28:29], v[26:27], -v[38:39] v_add_f64 v[24:25], v[24:25], -v[28:29] v_add_f64 v[28:29], v[26:27], s[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[24:25], v[24:25], s[30:31] v_add_f64 v[38:39], v[28:29], s[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[26:27], -v[38:39] v_add_f64 v[24:25], v[24:25], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[28:29], v[24:25] v_add_f64 v[28:29], v[28:29], -v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[24:25], v[28:29] v_mul_f64 v[28:29], v[22:23], v[26:27] v_fma_f64 v[38:39], v[22:23], v[26:27], -v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], v[22:23], v[24:25], v[38:39] v_fma_f64 v[20:21], v[20:21], v[26:27], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[28:29], v[20:21] v_add_f64 v[24:25], v[22:23], -v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[20:21], -v[24:25] v_add_f64 v[24:25], v[32:33], v[22:23] v_add_f64 v[20:21], v[36:37], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[24:25], -v[32:33] v_add_f64 v[22:23], v[22:23], -v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], v[22:23] v_add_f64 v[22:23], v[24:25], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[22:23], -v[24:25] v_add_f64 v[20:21], v[20:21], -v[24:25] v_add_f64 v[24:25], v[34:35], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[24:25], -v[34:35] v_add_f64 v[28:29], v[24:25], -v[26:27] v_add_f64 v[22:23], v[22:23], -v[26:27] v_add_f64 v[26:27], v[30:31], v[20:21] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[28:29], v[34:35], -v[28:29] v_add_f64 v[22:23], v[22:23], v[28:29] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[28:29], v[26:27], -v[30:31] v_add_f64 v[22:23], v[26:27], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[32:33], v[26:27], -v[28:29] v_add_f64 v[20:21], v[20:21], -v[28:29] v_add_f64 v[26:27], v[24:25], v[22:23] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[30:31], v[30:31], -v[32:33] v_add_f64 v[24:25], v[26:27], -v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[20:21], v[30:31] v_add_f64 v[22:23], v[22:23], -v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], v[22:23] v_add_f64 v[22:23], v[26:27], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[22:23], -v[26:27] v_add_f64 v[20:21], v[20:21], -v[24:25] v_add_f64 v[24:25], v[22:23], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[22:23], v[22:23], 2.0, -v[24:25] v_cmp_class_f64_e64 vcc_lo, v[24:25], 0x204 v_fma_f64 v[20:21], v[20:21], 2.0, v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[24:25], v[20:21] v_add_f64 v[26:27], v[22:23], -v[24:25] v_dual_cndmask_b32 v23, v23, v25 :: v_dual_cndmask_b32 v22, v22, v24 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_mul_f64 v[24:25], v[22:23], s[24:25] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]| v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[22:23] v_add_f64 v[20:21], v[20:21], -v[26:27] v_rndne_f64_e32 v[24:25], v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v21, 0, v21 :: v_dual_cndmask_b32 v20, 0, v20 v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[22:23] v_fma_f64 v[26:27], v[24:25], s[16:17], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[24:25], s[18:19], v[26:27] v_cvt_i32_f64_e32 v24, v[24:25] v_fma_f64 v[28:29], v[26:27], s[26:27], s[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], s[22:23] v_fma_f64 v[28:29], v[26:27], v[28:29], s[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], s[12:13] v_fma_f64 v[28:29], v[26:27], v[28:29], s[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], s[8:9] v_fma_f64 v[28:29], v[26:27], v[28:29], s[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], s[4:5] v_fma_f64 v[28:29], v[26:27], v[28:29], s[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], 1.0 v_fma_f64 v[26:27], v[26:27], v[28:29], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[24:25], v[26:27], v24 v_cndmask_b32_e32 v25, 0x7ff00000, v25, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v22, 0, v24, vcc_lo v_cndmask_b32_e64 v23, 0, v25, s0 v_cmp_neq_f64_e64 s0, 0, v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[20:21], v[22:23], v[20:21], v[22:23] v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204 v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22 v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[18:19]| s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[20:21], |v[20:21]|, s[58:59] v_cndmask_b32_e32 v21, 0x7ff00000, v21, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) s_and_b32 vcc_lo, s0, vcc_lo v_cndmask_b32_e32 v18, 0, v20, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v19, 0, v21, s0 v_frexp_mant_f64_e64 v[20:21], |v[2:3]| v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[20:21] v_cndmask_b32_e64 v22, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[20:21], v[20:21], v22 v_frexp_exp_i32_f64_e32 v22, v[2:3] v_add_f64 v[24:25], v[20:21], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_subrev_co_ci_u32_e32 v34, vcc_lo, 0, v22, vcc_lo v_add_f64 v[22:23], v[20:21], -1.0 v_add_f64 v[26:27], v[24:25], -1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], -v[26:27] v_rcp_f64_e32 v[26:27], v[24:25] s_waitcnt_depctr 0xfff v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0 v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0 v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[28:29], v[22:23], v[26:27] v_mul_f64 v[30:31], v[24:25], v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[28:29], v[24:25], -v[30:31] v_fma_f64 v[20:21], v[28:29], v[20:21], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[30:31], v[20:21] v_add_f64 v[32:33], v[22:23], -v[24:25] v_add_f64 v[30:31], v[24:25], -v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[22:23], -v[32:33] v_add_f64 v[20:21], v[30:31], -v[20:21] v_cvt_f64_i32_e32 v[30:31], v34 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[22:23], -v[24:25] v_add_f64 v[20:21], v[20:21], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[20:21], v[32:33], v[20:21] v_mul_f64 v[32:33], v[30:31], s[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[20:21], v[26:27], v[20:21] v_fma_f64 v[34:35], v[30:31], s[38:39], -v[32:33] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[28:29], v[20:21] v_fma_f64 v[30:31], v[30:31], s[42:43], v[34:35] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[24:25], v[22:23], -v[28:29] v_add_f64 v[34:35], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[20:21], v[20:21], -v[24:25] v_mul_f64 v[24:25], v[22:23], v[22:23] v_add_f64 v[32:33], v[34:35], -v[32:33] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[28:29], v[20:21], v[20:21] v_fma_f64 v[26:27], v[22:23], v[22:23], -v[24:25] v_ldexp_f64 v[36:37], v[20:21], 1 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[30:31], v[30:31], -v[32:33] v_ldexp_f64 v[32:33], v[22:23], 1 v_fma_f64 v[26:27], v[22:23], v[28:29], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[28:29], v[24:25], v[26:27] v_add_f64 v[24:25], v[28:29], -v[24:25] v_mul_f64 v[38:39], v[22:23], v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[24:25], v[26:27], -v[24:25] v_fma_f64 v[26:27], v[28:29], s[56:57], s[48:49] v_fma_f64 v[48:49], v[28:29], v[22:23], -v[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[28:29], v[26:27], s[50:51] v_fma_f64 v[20:21], v[28:29], v[20:21], v[48:49] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[28:29], v[26:27], s[52:53] v_fma_f64 v[20:21], v[24:25], v[22:23], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[28:29], v[26:27], s[54:55] v_add_f64 v[22:23], v[38:39], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[28:29], v[26:27], s[46:47] v_add_f64 v[38:39], v[22:23], -v[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[28:29], v[26:27], s[44:45] v_add_f64 v[20:21], v[20:21], -v[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[28:29], v[26:27], s[40:41] v_fma_f64 v[26:27], v[28:29], v[26:27], s[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[38:39], v[28:29], v[26:27] v_fma_f64 v[28:29], v[28:29], v[26:27], -v[38:39] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[24:25], v[26:27], v[28:29] v_add_f64 v[26:27], v[38:39], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[28:29], v[26:27], -v[38:39] v_add_f64 v[24:25], v[24:25], -v[28:29] v_add_f64 v[28:29], v[26:27], s[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[24:25], v[24:25], s[30:31] v_add_f64 v[38:39], v[28:29], s[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[26:27], -v[38:39] v_add_f64 v[24:25], v[24:25], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[28:29], v[24:25] v_add_f64 v[28:29], v[28:29], -v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[24:25], v[28:29] v_mul_f64 v[28:29], v[22:23], v[26:27] v_fma_f64 v[38:39], v[22:23], v[26:27], -v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], v[22:23], v[24:25], v[38:39] v_fma_f64 v[20:21], v[20:21], v[26:27], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[28:29], v[20:21] v_add_f64 v[24:25], v[22:23], -v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[20:21], -v[24:25] v_add_f64 v[24:25], v[32:33], v[22:23] v_add_f64 v[20:21], v[36:37], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[24:25], -v[32:33] v_add_f64 v[22:23], v[22:23], -v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], v[22:23] v_add_f64 v[22:23], v[24:25], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[22:23], -v[24:25] v_add_f64 v[20:21], v[20:21], -v[24:25] v_add_f64 v[24:25], v[34:35], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[24:25], -v[34:35] v_add_f64 v[28:29], v[24:25], -v[26:27] v_add_f64 v[22:23], v[22:23], -v[26:27] v_add_f64 v[26:27], v[30:31], v[20:21] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[28:29], v[34:35], -v[28:29] v_add_f64 v[22:23], v[22:23], v[28:29] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[28:29], v[26:27], -v[30:31] v_add_f64 v[22:23], v[26:27], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[32:33], v[26:27], -v[28:29] v_add_f64 v[20:21], v[20:21], -v[28:29] v_add_f64 v[26:27], v[24:25], v[22:23] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[30:31], v[30:31], -v[32:33] v_add_f64 v[24:25], v[26:27], -v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[20:21], v[30:31] v_add_f64 v[22:23], v[22:23], -v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], v[22:23] v_add_f64 v[22:23], v[26:27], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[22:23], -v[26:27] v_add_f64 v[20:21], v[20:21], -v[24:25] v_add_f64 v[24:25], v[22:23], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[22:23], v[22:23], 2.0, -v[24:25] v_cmp_class_f64_e64 vcc_lo, v[24:25], 0x204 v_fma_f64 v[20:21], v[20:21], 2.0, v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[24:25], v[20:21] v_add_f64 v[26:27], v[22:23], -v[24:25] v_dual_cndmask_b32 v23, v23, v25 :: v_dual_cndmask_b32 v22, v22, v24 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_mul_f64 v[24:25], v[22:23], s[24:25] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]| v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[22:23] v_add_f64 v[20:21], v[20:21], -v[26:27] v_rndne_f64_e32 v[24:25], v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v21, 0, v21 :: v_dual_cndmask_b32 v20, 0, v20 v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[22:23] v_fma_f64 v[26:27], v[24:25], s[16:17], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[24:25], s[18:19], v[26:27] v_cvt_i32_f64_e32 v24, v[24:25] v_fma_f64 v[28:29], v[26:27], s[26:27], s[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], s[22:23] v_fma_f64 v[28:29], v[26:27], v[28:29], s[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], s[12:13] v_fma_f64 v[28:29], v[26:27], v[28:29], s[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], s[8:9] v_fma_f64 v[28:29], v[26:27], v[28:29], s[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], s[4:5] v_fma_f64 v[28:29], v[26:27], v[28:29], s[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[26:27], v[28:29], 1.0 v_fma_f64 v[26:27], v[26:27], v[28:29], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[24:25], v[26:27], v24 v_cndmask_b32_e32 v25, 0x7ff00000, v25, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v22, 0, v24, vcc_lo v_cndmask_b32_e64 v23, 0, v25, s0 v_cmp_neq_f64_e64 s0, 0, v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[20:21], v[22:23], v[20:21], v[22:23] v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204 v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22 v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]| s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[20:21], |v[20:21]|, -2 v_cndmask_b32_e32 v21, 0x7ff00000, v21, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) s_and_b32 vcc_lo, s0, vcc_lo v_cndmask_b32_e32 v2, 0, v20, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v3, 0, v21, s0 v_add_f64 v[2:3], v[2:3], v[18:19] v_frexp_mant_f64_e64 v[18:19], |v[4:5]| s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[2:3], v[2:3], s[60:61] v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[18:19] v_cndmask_b32_e64 v20, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[18:19], v[18:19], v20 v_frexp_exp_i32_f64_e32 v20, v[4:5] v_add_f64 v[22:23], v[18:19], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_subrev_co_ci_u32_e32 v32, vcc_lo, 0, v20, vcc_lo v_add_f64 v[20:21], v[18:19], -1.0 v_add_f64 v[24:25], v[22:23], -1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[18:19], -v[24:25] v_rcp_f64_e32 v[24:25], v[22:23] s_waitcnt_depctr 0xfff v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0 v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0 v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[26:27], v[20:21], v[24:25] v_mul_f64 v[28:29], v[22:23], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], v[26:27], v[22:23], -v[28:29] v_fma_f64 v[18:19], v[26:27], v[18:19], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[28:29], v[18:19] v_add_f64 v[30:31], v[20:21], -v[22:23] v_add_f64 v[28:29], v[22:23], -v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[20:21], -v[30:31] v_add_f64 v[18:19], v[28:29], -v[18:19] v_cvt_f64_i32_e32 v[28:29], v32 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], -v[22:23] v_add_f64 v[18:19], v[18:19], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[18:19], v[30:31], v[18:19] v_mul_f64 v[30:31], v[28:29], s[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[18:19], v[24:25], v[18:19] v_fma_f64 v[32:33], v[28:29], s[38:39], -v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[26:27], v[18:19] v_fma_f64 v[28:29], v[28:29], s[42:43], v[32:33] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[20:21], -v[26:27] v_add_f64 v[32:33], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[18:19], v[18:19], -v[22:23] v_mul_f64 v[22:23], v[20:21], v[20:21] v_add_f64 v[30:31], v[32:33], -v[30:31] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[26:27], v[18:19], v[18:19] v_fma_f64 v[24:25], v[20:21], v[20:21], -v[22:23] v_ldexp_f64 v[34:35], v[18:19], 1 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[28:29], v[28:29], -v[30:31] v_ldexp_f64 v[30:31], v[20:21], 1 v_fma_f64 v[24:25], v[20:21], v[26:27], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[22:23], v[24:25] v_add_f64 v[22:23], v[26:27], -v[22:23] v_mul_f64 v[36:37], v[20:21], v[26:27] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[22:23], v[24:25], -v[22:23] v_fma_f64 v[24:25], v[26:27], s[56:57], s[48:49] v_fma_f64 v[38:39], v[26:27], v[20:21], -v[36:37] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[24:25], v[26:27], v[24:25], s[50:51] v_fma_f64 v[18:19], v[26:27], v[18:19], v[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[24:25], v[26:27], v[24:25], s[52:53] v_fma_f64 v[18:19], v[22:23], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[24:25], v[26:27], v[24:25], s[54:55] v_add_f64 v[20:21], v[36:37], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[24:25], v[26:27], v[24:25], s[46:47] v_add_f64 v[36:37], v[20:21], -v[36:37] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[24:25], v[26:27], v[24:25], s[44:45] v_add_f64 v[18:19], v[18:19], -v[36:37] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[26:27], v[24:25], s[40:41] v_fma_f64 v[24:25], v[26:27], v[24:25], s[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[36:37], v[26:27], v[24:25] v_fma_f64 v[26:27], v[26:27], v[24:25], -v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], v[22:23], v[24:25], v[26:27] v_add_f64 v[24:25], v[36:37], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[24:25], -v[36:37] v_add_f64 v[22:23], v[22:23], -v[26:27] v_add_f64 v[26:27], v[24:25], s[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[22:23], s[30:31] v_add_f64 v[36:37], v[26:27], s[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[24:25], -v[36:37] v_add_f64 v[22:23], v[22:23], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[26:27], v[22:23] v_add_f64 v[26:27], v[26:27], -v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[22:23], v[26:27] v_mul_f64 v[26:27], v[20:21], v[24:25] v_fma_f64 v[36:37], v[20:21], v[24:25], -v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[20:21], v[22:23], v[36:37] v_fma_f64 v[18:19], v[18:19], v[24:25], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[26:27], v[18:19] v_add_f64 v[22:23], v[20:21], -v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[18:19], -v[22:23] v_add_f64 v[22:23], v[30:31], v[20:21] v_add_f64 v[18:19], v[34:35], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[22:23], -v[30:31] v_add_f64 v[20:21], v[20:21], -v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[18:19], v[20:21] v_add_f64 v[20:21], v[22:23], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[20:21], -v[22:23] v_add_f64 v[18:19], v[18:19], -v[22:23] v_add_f64 v[22:23], v[32:33], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[24:25], v[22:23], -v[32:33] v_add_f64 v[26:27], v[22:23], -v[24:25] v_add_f64 v[20:21], v[20:21], -v[24:25] v_add_f64 v[24:25], v[28:29], v[18:19] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[26:27], v[32:33], -v[26:27] v_add_f64 v[20:21], v[20:21], v[26:27] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[26:27], v[24:25], -v[28:29] v_add_f64 v[20:21], v[24:25], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[30:31], v[24:25], -v[26:27] v_add_f64 v[18:19], v[18:19], -v[26:27] v_add_f64 v[24:25], v[22:23], v[20:21] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[28:29], v[28:29], -v[30:31] v_add_f64 v[22:23], v[24:25], -v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[18:19], v[28:29] v_add_f64 v[20:21], v[20:21], -v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[18:19], v[20:21] v_add_f64 v[20:21], v[24:25], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[20:21], -v[24:25] v_add_f64 v[18:19], v[18:19], -v[22:23] v_add_f64 v[22:23], v[20:21], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[20:21], v[20:21], 2.0, -v[22:23] v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204 v_fma_f64 v[18:19], v[18:19], 2.0, v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[22:23], v[18:19] v_add_f64 v[24:25], v[20:21], -v[22:23] v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_mul_f64 v[22:23], v[20:21], s[24:25] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[20:21]| v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[20:21] v_add_f64 v[18:19], v[18:19], -v[24:25] v_rndne_f64_e32 v[22:23], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v19, 0, v19 :: v_dual_cndmask_b32 v18, 0, v18 v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[20:21] v_fma_f64 v[24:25], v[22:23], s[16:17], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[24:25], v[22:23], s[18:19], v[24:25] v_cvt_i32_f64_e32 v22, v[22:23] v_fma_f64 v[26:27], v[24:25], s[26:27], s[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[24:25], v[26:27], s[22:23] v_fma_f64 v[26:27], v[24:25], v[26:27], s[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[24:25], v[26:27], s[12:13] v_fma_f64 v[26:27], v[24:25], v[26:27], s[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[24:25], v[26:27], s[8:9] v_fma_f64 v[26:27], v[24:25], v[26:27], s[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[24:25], v[26:27], s[4:5] v_fma_f64 v[26:27], v[24:25], v[26:27], s[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[24:25], v[26:27], 1.0 v_fma_f64 v[24:25], v[24:25], v[26:27], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[22:23], v[24:25], v22 v_cndmask_b32_e32 v23, 0x7ff00000, v23, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v20, 0, v22, vcc_lo v_cndmask_b32_e64 v21, 0, v23, s0 v_cmp_neq_f64_e64 s0, 0, v[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[18:19], v[20:21], v[18:19], v[20:21] v_cmp_class_f64_e64 vcc_lo, v[20:21], 0x204 v_dual_cndmask_b32 v19, v19, v21 :: v_dual_cndmask_b32 v18, v18, v20 v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[4:5]| s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mul_f64 v[18:19], |v[18:19]|, s[58:59] s_mov_b32 s59, 0x3fe33333 s_mov_b32 s58, 0x33333333 v_cndmask_b32_e32 v19, 0x7ff00000, v19, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) s_and_b32 vcc_lo, s0, vcc_lo v_cndmask_b32_e32 v4, 0, v18, vcc_lo v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v5, 0, v19, s0 v_cndmask_b32_e64 v16, 0, 1, vcc_lo v_ldexp_f64 v[8:9], v[8:9], v16 v_frexp_exp_i32_f64_e32 v16, v[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[8:9], 1.0 v_subrev_co_ci_u32_e32 v28, vcc_lo, 0, v16, vcc_lo v_add_f64 v[16:17], v[8:9], -1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[18:19], -1.0 v_add_f64 v[8:9], v[8:9], -v[20:21] v_rcp_f64_e32 v[20:21], v[18:19] s_waitcnt_depctr 0xfff v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[22:23], v[20:21], v[20:21] v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[22:23], v[20:21], v[20:21] v_mul_f64 v[22:23], v[16:17], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[24:25], v[18:19], v[22:23] v_fma_f64 v[18:19], v[22:23], v[18:19], -v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], v[22:23], v[8:9], v[18:19] v_add_f64 v[18:19], v[24:25], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[26:27], v[16:17], -v[18:19] v_add_f64 v[24:25], v[18:19], -v[24:25] v_add_f64 v[16:17], v[16:17], -v[26:27] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[8:9], v[24:25], -v[8:9] v_cvt_f64_i32_e32 v[24:25], v28 v_add_f64 v[16:17], v[16:17], -v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[8:9], v[16:17] v_add_f64 v[8:9], v[26:27], v[8:9] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[26:27], v[24:25], s[38:39] v_mul_f64 v[8:9], v[20:21], v[8:9] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[28:29], v[24:25], s[38:39], -v[26:27] v_add_f64 v[16:17], v[22:23], v[8:9] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[24:25], v[24:25], s[42:43], v[28:29] v_add_f64 v[18:19], v[16:17], -v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[28:29], v[26:27], v[24:25] v_add_f64 v[8:9], v[8:9], -v[18:19] v_mul_f64 v[18:19], v[16:17], v[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[26:27], v[28:29], -v[26:27] v_add_f64 v[22:23], v[8:9], v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_fma_f64 v[20:21], v[16:17], v[16:17], -v[18:19] v_ldexp_f64 v[30:31], v[8:9], 1 v_add_f64 v[24:25], v[24:25], -v[26:27] v_ldexp_f64 v[26:27], v[16:17], 1 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[16:17], v[22:23], v[20:21] v_add_f64 v[22:23], v[18:19], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[22:23], -v[18:19] v_mul_f64 v[32:33], v[16:17], v[22:23] v_add_f64 v[18:19], v[20:21], -v[18:19] v_fma_f64 v[20:21], v[22:23], s[56:57], s[48:49] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[34:35], v[22:23], v[16:17], -v[32:33] v_fma_f64 v[20:21], v[22:23], v[20:21], s[50:51] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[8:9], v[22:23], v[8:9], v[34:35] v_fma_f64 v[20:21], v[22:23], v[20:21], s[52:53] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[8:9], v[18:19], v[16:17], v[8:9] v_fma_f64 v[20:21], v[22:23], v[20:21], s[54:55] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[32:33], v[8:9] v_fma_f64 v[20:21], v[22:23], v[20:21], s[46:47] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[32:33], v[16:17], -v[32:33] v_fma_f64 v[20:21], v[22:23], v[20:21], s[44:45] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[8:9], v[8:9], -v[32:33] v_fma_f64 v[20:21], v[22:23], v[20:21], s[40:41] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[22:23], v[20:21], s[36:37] v_mul_f64 v[32:33], v[22:23], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], v[22:23], v[20:21], -v[32:33] v_fma_f64 v[18:19], v[18:19], v[20:21], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[32:33], v[18:19] v_add_f64 v[22:23], v[20:21], -v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[18:19], -v[22:23] v_add_f64 v[22:23], v[20:21], s[28:29] v_add_f64 v[18:19], v[18:19], s[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[32:33], v[22:23], s[34:35] v_add_f64 v[20:21], v[20:21], -v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[18:19], v[20:21] v_add_f64 v[20:21], v[22:23], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[22:23], v[22:23], -v[20:21] v_add_f64 v[18:19], v[18:19], v[22:23] v_mul_f64 v[22:23], v[16:17], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[16:17], v[20:21], -v[22:23] v_fma_f64 v[16:17], v[16:17], v[18:19], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], v[8:9], v[20:21], v[16:17] v_add_f64 v[16:17], v[22:23], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[16:17], -v[22:23] v_add_f64 v[8:9], v[8:9], -v[18:19] v_add_f64 v[18:19], v[26:27], v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[8:9], v[30:31], v[8:9] v_add_f64 v[20:21], v[18:19], -v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[16:17], v[16:17], -v[20:21] v_add_f64 v[8:9], v[8:9], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[16:17], v[18:19], v[8:9] v_add_f64 v[18:19], v[16:17], -v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[8:9], -v[18:19] v_add_f64 v[18:19], v[28:29], v[16:17] v_add_f64 v[20:21], v[18:19], -v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_f64 v[22:23], v[18:19], -v[20:21] v_add_f64 v[16:17], v[16:17], -v[20:21] v_add_f64 v[20:21], v[24:25], v[8:9] v_add_f64 v[22:23], v[28:29], -v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[16:17], v[16:17], v[22:23] v_add_f64 v[22:23], v[20:21], -v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[20:21], v[16:17] v_add_f64 v[26:27], v[20:21], -v[22:23] v_add_f64 v[8:9], v[8:9], -v[22:23] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[20:21], v[18:19], v[16:17] v_add_f64 v[24:25], v[24:25], -v[26:27] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[20:21], -v[18:19] v_add_f64 v[8:9], v[8:9], v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[16:17], v[16:17], -v[18:19] v_add_f64 v[8:9], v[8:9], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[16:17], v[20:21], v[8:9] v_add_f64 v[18:19], v[16:17], -v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[8:9], -v[18:19] v_add_f64 v[18:19], v[16:17], v[16:17] v_fma_f64 v[16:17], v[16:17], 2.0, -v[18:19] v_cmp_class_f64_e64 vcc_lo, v[18:19], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], v[8:9], 2.0, v[16:17] v_add_f64 v[16:17], v[18:19], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[16:17], -v[18:19] v_dual_cndmask_b32 v17, v17, v19 :: v_dual_cndmask_b32 v16, v16, v18 v_mul_f64 v[18:19], v[16:17], s[24:25] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[16:17]| v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[16:17] v_add_f64 v[8:9], v[8:9], -v[20:21] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_rndne_f64_e32 v[18:19], v[18:19] v_dual_cndmask_b32 v9, 0, v9 :: v_dual_cndmask_b32 v8, 0, v8 v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], s[16:17], v[16:17] v_fma_f64 v[20:21], v[18:19], s[18:19], v[20:21] v_cvt_i32_f64_e32 v18, v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], v[20:21], s[26:27], s[20:21] v_fma_f64 v[22:23], v[20:21], v[22:23], s[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], v[20:21], v[22:23], s[14:15] v_fma_f64 v[22:23], v[20:21], v[22:23], s[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], v[20:21], v[22:23], s[10:11] v_fma_f64 v[22:23], v[20:21], v[22:23], s[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], v[20:21], v[22:23], s[2:3] v_fma_f64 v[22:23], v[20:21], v[22:23], s[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], v[20:21], v[22:23], s[6:7] v_fma_f64 v[22:23], v[20:21], v[22:23], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[20:21], v[22:23], 1.0 v_ldexp_f64 v[18:19], v[20:21], v18 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v19, 0x7ff00000, v19, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo v_cndmask_b32_e32 v16, 0, v18, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v17, 0, v19, s0 v_cmp_neq_f64_e64 s0, 0, v[6:7] v_fma_f64 v[8:9], v[16:17], v[8:9], v[16:17] v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16 v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[6:7]| v_ldexp_f64 v[8:9], |v[8:9]|, -2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v9, 0x7ff00000, v9, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v6, 0, v8, vcc_lo v_cndmask_b32_e64 v7, 0, v9, s0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[4:5], v[4:5], v[6:7] v_frexp_mant_f64_e32 v[6:7], v[0:1] v_add_f64 v[4:5], v[4:5], s[60:61] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[6:7] v_readlane_b32 s61, v40, 27 v_readlane_b32 s60, v40, 26 v_cndmask_b32_e64 v8, 0, 1, vcc_lo v_ldexp_f64 v[6:7], v[6:7], v8 v_frexp_exp_i32_f64_e32 v8, v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[6:7], 1.0 v_subrev_co_ci_u32_e32 v26, vcc_lo, 0, v8, vcc_lo v_add_f64 v[8:9], v[6:7], -1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[16:17], -1.0 v_add_f64 v[6:7], v[6:7], -v[18:19] v_rcp_f64_e32 v[18:19], v[16:17] s_waitcnt_depctr 0xfff v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19] v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19] v_mul_f64 v[20:21], v[8:9], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[22:23], v[16:17], v[20:21] v_fma_f64 v[16:17], v[20:21], v[16:17], -v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], v[20:21], v[6:7], v[16:17] v_add_f64 v[16:17], v[22:23], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[24:25], v[8:9], -v[16:17] v_add_f64 v[22:23], v[16:17], -v[22:23] v_add_f64 v[8:9], v[8:9], -v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[6:7], v[22:23], -v[6:7] v_cvt_f64_i32_e32 v[22:23], v26 v_add_f64 v[8:9], v[8:9], -v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[6:7], v[8:9] v_add_f64 v[6:7], v[24:25], v[6:7] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[24:25], v[22:23], s[38:39] v_mul_f64 v[6:7], v[18:19], v[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[22:23], s[38:39], -v[24:25] v_add_f64 v[8:9], v[20:21], v[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[22:23], v[22:23], s[42:43], v[26:27] v_add_f64 v[16:17], v[8:9], -v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[26:27], v[24:25], v[22:23] v_add_f64 v[6:7], v[6:7], -v[16:17] v_mul_f64 v[16:17], v[8:9], v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[24:25], v[26:27], -v[24:25] v_add_f64 v[20:21], v[6:7], v[6:7] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_fma_f64 v[18:19], v[8:9], v[8:9], -v[16:17] v_ldexp_f64 v[28:29], v[6:7], 1 v_add_f64 v[22:23], v[22:23], -v[24:25] v_ldexp_f64 v[24:25], v[8:9], 1 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[8:9], v[20:21], v[18:19] v_add_f64 v[20:21], v[16:17], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[20:21], -v[16:17] v_mul_f64 v[30:31], v[8:9], v[20:21] v_add_f64 v[16:17], v[18:19], -v[16:17] v_fma_f64 v[18:19], v[20:21], s[56:57], s[48:49] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[32:33], v[20:21], v[8:9], -v[30:31] v_fma_f64 v[18:19], v[20:21], v[18:19], s[50:51] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[6:7], v[20:21], v[6:7], v[32:33] v_fma_f64 v[18:19], v[20:21], v[18:19], s[52:53] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[6:7], v[16:17], v[8:9], v[6:7] v_fma_f64 v[18:19], v[20:21], v[18:19], s[54:55] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[8:9], v[30:31], v[6:7] v_fma_f64 v[18:19], v[20:21], v[18:19], s[46:47] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[30:31], v[8:9], -v[30:31] v_fma_f64 v[18:19], v[20:21], v[18:19], s[44:45] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[6:7], v[6:7], -v[30:31] v_fma_f64 v[18:19], v[20:21], v[18:19], s[40:41] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[20:21], v[18:19], s[36:37] v_mul_f64 v[30:31], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[20:21], v[18:19], -v[30:31] v_fma_f64 v[16:17], v[16:17], v[18:19], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[30:31], v[16:17] v_add_f64 v[20:21], v[18:19], -v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[16:17], -v[20:21] v_add_f64 v[20:21], v[18:19], s[28:29] v_add_f64 v[16:17], v[16:17], s[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[30:31], v[20:21], s[34:35] v_add_f64 v[18:19], v[18:19], -v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[16:17], v[16:17], v[18:19] v_add_f64 v[18:19], v[20:21], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], -v[18:19] v_add_f64 v[16:17], v[16:17], v[20:21] v_mul_f64 v[20:21], v[8:9], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[8:9], v[18:19], -v[20:21] v_fma_f64 v[8:9], v[8:9], v[16:17], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], v[6:7], v[18:19], v[8:9] v_add_f64 v[8:9], v[20:21], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[16:17], v[8:9], -v[20:21] v_add_f64 v[6:7], v[6:7], -v[16:17] v_add_f64 v[16:17], v[24:25], v[8:9] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[6:7], v[28:29], v[6:7] v_add_f64 v[18:19], v[16:17], -v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[8:9], -v[18:19] v_add_f64 v[6:7], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[16:17], v[6:7] v_add_f64 v[16:17], v[8:9], -v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[6:7], -v[16:17] v_add_f64 v[16:17], v[26:27], v[8:9] v_add_f64 v[18:19], v[16:17], -v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_f64 v[20:21], v[16:17], -v[18:19] v_add_f64 v[8:9], v[8:9], -v[18:19] v_add_f64 v[18:19], v[22:23], v[6:7] v_add_f64 v[20:21], v[26:27], -v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[8:9], v[8:9], v[20:21] v_add_f64 v[20:21], v[18:19], -v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[8:9], v[18:19], v[8:9] v_add_f64 v[24:25], v[18:19], -v[20:21] v_add_f64 v[6:7], v[6:7], -v[20:21] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[18:19], v[16:17], v[8:9] v_add_f64 v[22:23], v[22:23], -v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[18:19], -v[16:17] v_add_f64 v[6:7], v[6:7], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[8:9], -v[16:17] v_add_f64 v[6:7], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[18:19], v[6:7] v_add_f64 v[16:17], v[8:9], -v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[6:7], -v[16:17] v_add_f64 v[16:17], v[8:9], v[8:9] v_fma_f64 v[8:9], v[8:9], 2.0, -v[16:17] v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], v[6:7], 2.0, v[8:9] v_add_f64 v[8:9], v[16:17], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[8:9], -v[16:17] v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16 v_mul_f64 v[16:17], v[8:9], s[24:25] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[8:9]| v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[8:9] v_add_f64 v[6:7], v[6:7], -v[18:19] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_rndne_f64_e32 v[16:17], v[16:17] v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6 v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[16:17], s[16:17], v[8:9] v_fma_f64 v[18:19], v[16:17], s[18:19], v[18:19] v_cvt_i32_f64_e32 v16, v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], s[26:27], s[20:21] v_fma_f64 v[20:21], v[18:19], v[20:21], s[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], v[20:21], s[14:15] v_fma_f64 v[20:21], v[18:19], v[20:21], s[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], v[20:21], s[10:11] v_fma_f64 v[20:21], v[18:19], v[20:21], s[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3] v_fma_f64 v[20:21], v[18:19], v[20:21], s[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], v[20:21], s[6:7] v_fma_f64 v[20:21], v[18:19], v[20:21], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[18:19], v[20:21], 1.0 v_ldexp_f64 v[16:17], v[18:19], v16 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v17, 0x7ff00000, v17, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo v_cndmask_b32_e32 v8, 0, v16, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v9, 0, v17, s0 s_mov_b32 s0, 0x9999999a v_fma_f64 v[6:7], v[8:9], v[6:7], v[8:9] v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8 v_dual_mov_b32 v8, v6 :: v_dual_and_b32 v9, 0x7fffffff, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f64 v[16:17], null, v[8:9], v[8:9], s[0:1] v_div_scale_f64 v[8:9], vcc_lo, s[0:1], v[8:9], s[0:1] v_rcp_f64_e32 v[18:19], v[16:17] s_waitcnt_depctr 0xfff v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] v_mul_f64 v[20:21], v[8:9], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[16:17], v[20:21], v[8:9] v_div_fmas_f64 v[8:9], v[8:9], v[18:19], v[20:21] v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[6:7], v[8:9], |v[6:7]|, s[0:1] v_cmp_neq_f64_e64 s0, 0, v[0:1] v_cndmask_b32_e32 v7, 0, v7, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) s_and_b32 vcc_lo, s0, vcc_lo v_cndmask_b32_e32 v0, 0, v6, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v1, 0x7ff00000, v7, s0 v_frexp_mant_f64_e32 v[6:7], v[2:3] v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[6:7] v_cndmask_b32_e64 v8, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[6:7], v[6:7], v8 v_frexp_exp_i32_f64_e32 v8, v[2:3] v_add_f64 v[16:17], v[6:7], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_subrev_co_ci_u32_e32 v26, vcc_lo, 0, v8, vcc_lo v_add_f64 v[8:9], v[6:7], -1.0 v_add_f64 v[18:19], v[16:17], -1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[6:7], -v[18:19] v_rcp_f64_e32 v[18:19], v[16:17] s_waitcnt_depctr 0xfff v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[20:21], v[8:9], v[18:19] v_mul_f64 v[22:23], v[16:17], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], v[20:21], v[16:17], -v[22:23] v_fma_f64 v[6:7], v[20:21], v[6:7], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[16:17], v[22:23], v[6:7] v_add_f64 v[24:25], v[8:9], -v[16:17] v_add_f64 v[22:23], v[16:17], -v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[8:9], v[8:9], -v[24:25] v_add_f64 v[6:7], v[22:23], -v[6:7] v_cvt_f64_i32_e32 v[22:23], v26 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[8:9], -v[16:17] v_add_f64 v[6:7], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[6:7], v[24:25], v[6:7] v_mul_f64 v[24:25], v[22:23], s[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[6:7], v[18:19], v[6:7] v_fma_f64 v[26:27], v[22:23], s[38:39], -v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[8:9], v[20:21], v[6:7] v_fma_f64 v[22:23], v[22:23], s[42:43], v[26:27] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[8:9], -v[20:21] v_add_f64 v[26:27], v[24:25], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[6:7], v[6:7], -v[16:17] v_mul_f64 v[16:17], v[8:9], v[8:9] v_add_f64 v[24:25], v[26:27], -v[24:25] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[20:21], v[6:7], v[6:7] v_fma_f64 v[18:19], v[8:9], v[8:9], -v[16:17] v_ldexp_f64 v[28:29], v[6:7], 1 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[22:23], v[22:23], -v[24:25] v_ldexp_f64 v[24:25], v[8:9], 1 v_fma_f64 v[18:19], v[8:9], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[16:17], v[18:19] v_add_f64 v[16:17], v[20:21], -v[16:17] v_mul_f64 v[30:31], v[8:9], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[16:17], v[18:19], -v[16:17] v_fma_f64 v[18:19], v[20:21], s[56:57], s[48:49] v_fma_f64 v[32:33], v[20:21], v[8:9], -v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[18:19], v[20:21], v[18:19], s[50:51] v_fma_f64 v[6:7], v[20:21], v[6:7], v[32:33] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[18:19], v[20:21], v[18:19], s[52:53] v_fma_f64 v[6:7], v[16:17], v[8:9], v[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[18:19], v[20:21], v[18:19], s[54:55] v_add_f64 v[8:9], v[30:31], v[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[18:19], v[20:21], v[18:19], s[46:47] v_add_f64 v[30:31], v[8:9], -v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[18:19], v[20:21], v[18:19], s[44:45] v_add_f64 v[6:7], v[6:7], -v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[20:21], v[18:19], s[40:41] v_fma_f64 v[18:19], v[20:21], v[18:19], s[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[30:31], v[20:21], v[18:19] v_fma_f64 v[20:21], v[20:21], v[18:19], -v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], v[16:17], v[18:19], v[20:21] v_add_f64 v[18:19], v[30:31], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[18:19], -v[30:31] v_add_f64 v[16:17], v[16:17], -v[20:21] v_add_f64 v[20:21], v[18:19], s[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[16:17], s[30:31] v_add_f64 v[30:31], v[20:21], s[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[18:19], -v[30:31] v_add_f64 v[16:17], v[16:17], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[20:21], v[16:17] v_add_f64 v[20:21], v[20:21], -v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[16:17], v[16:17], v[20:21] v_mul_f64 v[20:21], v[8:9], v[18:19] v_fma_f64 v[30:31], v[8:9], v[18:19], -v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], v[8:9], v[16:17], v[30:31] v_fma_f64 v[6:7], v[6:7], v[18:19], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[20:21], v[6:7] v_add_f64 v[16:17], v[8:9], -v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[6:7], v[6:7], -v[16:17] v_add_f64 v[16:17], v[24:25], v[8:9] v_add_f64 v[6:7], v[28:29], v[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[16:17], -v[24:25] v_add_f64 v[8:9], v[8:9], -v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[6:7], v[8:9] v_add_f64 v[8:9], v[16:17], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[16:17], v[8:9], -v[16:17] v_add_f64 v[6:7], v[6:7], -v[16:17] v_add_f64 v[16:17], v[26:27], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[16:17], -v[26:27] v_add_f64 v[20:21], v[16:17], -v[18:19] v_add_f64 v[8:9], v[8:9], -v[18:19] v_add_f64 v[18:19], v[22:23], v[6:7] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[26:27], -v[20:21] v_add_f64 v[8:9], v[8:9], v[20:21] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[18:19], -v[22:23] v_add_f64 v[8:9], v[18:19], v[8:9] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[24:25], v[18:19], -v[20:21] v_add_f64 v[6:7], v[6:7], -v[20:21] v_add_f64 v[18:19], v[16:17], v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[22:23], -v[24:25] v_add_f64 v[16:17], v[18:19], -v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[6:7], v[6:7], v[22:23] v_add_f64 v[8:9], v[8:9], -v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[6:7], v[8:9] v_add_f64 v[8:9], v[18:19], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[16:17], v[8:9], -v[18:19] v_add_f64 v[6:7], v[6:7], -v[16:17] v_add_f64 v[16:17], v[8:9], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[8:9], v[8:9], 2.0, -v[16:17] v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204 v_fma_f64 v[6:7], v[6:7], 2.0, v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[16:17], v[6:7] v_add_f64 v[18:19], v[8:9], -v[16:17] v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_mul_f64 v[16:17], v[8:9], s[24:25] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[8:9]| v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[8:9] v_add_f64 v[6:7], v[6:7], -v[18:19] v_rndne_f64_e32 v[16:17], v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6 v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[8:9] v_fma_f64 v[18:19], v[16:17], s[16:17], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[18:19], v[16:17], s[18:19], v[18:19] v_cvt_i32_f64_e32 v16, v[16:17] v_fma_f64 v[20:21], v[18:19], s[26:27], s[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], v[20:21], s[22:23] v_fma_f64 v[20:21], v[18:19], v[20:21], s[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], v[20:21], s[12:13] v_fma_f64 v[20:21], v[18:19], v[20:21], s[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], v[20:21], s[8:9] v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], v[20:21], s[4:5] v_fma_f64 v[20:21], v[18:19], v[20:21], s[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], v[20:21], 1.0 v_fma_f64 v[18:19], v[18:19], v[20:21], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[16:17], v[18:19], v16 v_cndmask_b32_e32 v17, 0x7ff00000, v17, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v8, 0, v16, vcc_lo v_cndmask_b32_e64 v9, 0, v17, s0 v_cmp_neq_f64_e64 s0, 0, v[2:3] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[6:7], v[8:9], v[6:7], v[8:9] v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x204 v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v8, v6 :: v_dual_and_b32 v9, 0x7fffffff, v7 v_div_scale_f64 v[16:17], null, v[8:9], v[8:9], s[58:59] v_div_scale_f64 v[8:9], vcc_lo, s[58:59], v[8:9], s[58:59] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[18:19], v[16:17] s_waitcnt_depctr 0xfff v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[20:21], v[8:9], v[18:19] v_fma_f64 v[8:9], -v[16:17], v[20:21], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fmas_f64 v[8:9], v[8:9], v[18:19], v[20:21] v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[2:3] v_div_fixup_f64 v[6:7], v[8:9], |v[6:7]|, s[58:59] s_mov_b32 s59, 0x3fd33333 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v7, 0, v7, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo v_cndmask_b32_e32 v2, 0, v6, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v3, 0x7ff00000, v7, s0 v_frexp_mant_f64_e32 v[6:7], v[4:5] v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[6:7] v_cndmask_b32_e64 v8, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ldexp_f64 v[6:7], v[6:7], v8 v_frexp_exp_i32_f64_e32 v8, v[4:5] v_add_f64 v[16:17], v[6:7], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_subrev_co_ci_u32_e32 v26, vcc_lo, 0, v8, vcc_lo v_add_f64 v[8:9], v[6:7], -1.0 v_add_f64 v[18:19], v[16:17], -1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[6:7], -v[18:19] v_rcp_f64_e32 v[18:19], v[16:17] s_waitcnt_depctr 0xfff v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[20:21], v[8:9], v[18:19] v_mul_f64 v[22:23], v[16:17], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], v[20:21], v[16:17], -v[22:23] v_fma_f64 v[6:7], v[20:21], v[6:7], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[16:17], v[22:23], v[6:7] v_add_f64 v[24:25], v[8:9], -v[16:17] v_add_f64 v[22:23], v[16:17], -v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[8:9], v[8:9], -v[24:25] v_add_f64 v[6:7], v[22:23], -v[6:7] v_cvt_f64_i32_e32 v[22:23], v26 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[8:9], -v[16:17] v_add_f64 v[6:7], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[6:7], v[24:25], v[6:7] v_mul_f64 v[24:25], v[22:23], s[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[6:7], v[18:19], v[6:7] v_fma_f64 v[26:27], v[22:23], s[38:39], -v[24:25] v_readlane_b32 s39, v40, 5 v_readlane_b32 s38, v40, 4 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[8:9], v[20:21], v[6:7] v_fma_f64 v[22:23], v[22:23], s[42:43], v[26:27] v_readlane_b32 s43, v40, 9 v_readlane_b32 s42, v40, 8 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[16:17], v[8:9], -v[20:21] v_add_f64 v[26:27], v[24:25], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[6:7], v[6:7], -v[16:17] v_mul_f64 v[16:17], v[8:9], v[8:9] v_add_f64 v[24:25], v[26:27], -v[24:25] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[20:21], v[6:7], v[6:7] v_fma_f64 v[18:19], v[8:9], v[8:9], -v[16:17] v_ldexp_f64 v[28:29], v[6:7], 1 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[22:23], v[22:23], -v[24:25] v_ldexp_f64 v[24:25], v[8:9], 1 v_fma_f64 v[18:19], v[8:9], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[16:17], v[18:19] v_add_f64 v[16:17], v[20:21], -v[16:17] v_mul_f64 v[30:31], v[8:9], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[16:17], v[18:19], -v[16:17] v_fma_f64 v[18:19], v[20:21], s[56:57], s[48:49] v_fma_f64 v[32:33], v[20:21], v[8:9], -v[30:31] v_readlane_b32 s57, v40, 23 v_readlane_b32 s56, v40, 22 v_readlane_b32 s49, v40, 15 v_readlane_b32 s48, v40, 14 v_fma_f64 v[18:19], v[20:21], v[18:19], s[50:51] v_fma_f64 v[6:7], v[20:21], v[6:7], v[32:33] v_readlane_b32 s51, v40, 17 v_readlane_b32 s50, v40, 16 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[18:19], v[20:21], v[18:19], s[52:53] v_fma_f64 v[6:7], v[16:17], v[8:9], v[6:7] v_readlane_b32 s53, v40, 19 v_readlane_b32 s52, v40, 18 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[18:19], v[20:21], v[18:19], s[54:55] v_add_f64 v[8:9], v[30:31], v[6:7] v_readlane_b32 s55, v40, 21 v_readlane_b32 s54, v40, 20 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[18:19], v[20:21], v[18:19], s[46:47] v_add_f64 v[30:31], v[8:9], -v[30:31] v_readlane_b32 s47, v40, 13 v_readlane_b32 s46, v40, 12 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[18:19], v[20:21], v[18:19], s[44:45] v_add_f64 v[6:7], v[6:7], -v[30:31] v_readlane_b32 s45, v40, 11 v_readlane_b32 s44, v40, 10 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[18:19], v[20:21], v[18:19], s[40:41] v_readlane_b32 s41, v40, 7 v_readlane_b32 s40, v40, 6 v_fma_f64 v[18:19], v[20:21], v[18:19], s[36:37] v_readlane_b32 s37, v40, 3 v_readlane_b32 s36, v40, 2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[30:31], v[20:21], v[18:19] v_fma_f64 v[20:21], v[20:21], v[18:19], -v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[16:17], v[16:17], v[18:19], v[20:21] v_add_f64 v[18:19], v[30:31], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[18:19], -v[30:31] v_add_f64 v[16:17], v[16:17], -v[20:21] v_add_f64 v[20:21], v[18:19], s[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[16:17], s[30:31] v_add_f64 v[30:31], v[20:21], s[34:35] v_readlane_b32 s30, v40, 28 v_readlane_b32 s31, v40, 29 v_readlane_b32 s35, v40, 1 v_readlane_b32 s34, v40, 0 v_add_f64 v[18:19], v[18:19], -v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[16:17], v[16:17], v[18:19] v_add_f64 v[18:19], v[20:21], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[20:21], v[20:21], -v[18:19] v_add_f64 v[16:17], v[16:17], v[20:21] v_mul_f64 v[20:21], v[8:9], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[8:9], v[18:19], -v[20:21] v_fma_f64 v[8:9], v[8:9], v[16:17], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], v[6:7], v[18:19], v[8:9] v_add_f64 v[8:9], v[20:21], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[16:17], v[8:9], -v[20:21] v_add_f64 v[6:7], v[6:7], -v[16:17] v_add_f64 v[16:17], v[24:25], v[8:9] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[6:7], v[28:29], v[6:7] v_add_f64 v[18:19], v[16:17], -v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[8:9], -v[18:19] v_add_f64 v[6:7], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[16:17], v[6:7] v_add_f64 v[16:17], v[8:9], -v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[6:7], -v[16:17] v_add_f64 v[16:17], v[26:27], v[8:9] v_add_f64 v[18:19], v[16:17], -v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_f64 v[20:21], v[16:17], -v[18:19] v_add_f64 v[8:9], v[8:9], -v[18:19] v_add_f64 v[18:19], v[22:23], v[6:7] v_add_f64 v[20:21], v[26:27], -v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[8:9], v[8:9], v[20:21] v_add_f64 v[20:21], v[18:19], -v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[8:9], v[18:19], v[8:9] v_add_f64 v[24:25], v[18:19], -v[20:21] v_add_f64 v[6:7], v[6:7], -v[20:21] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[18:19], v[16:17], v[8:9] v_add_f64 v[22:23], v[22:23], -v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[18:19], -v[16:17] v_add_f64 v[6:7], v[6:7], v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[8:9], -v[16:17] v_add_f64 v[6:7], v[6:7], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[8:9], v[18:19], v[6:7] v_add_f64 v[16:17], v[8:9], -v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[6:7], -v[16:17] v_add_f64 v[16:17], v[8:9], v[8:9] v_fma_f64 v[8:9], v[8:9], 2.0, -v[16:17] v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], v[6:7], 2.0, v[8:9] v_add_f64 v[8:9], v[16:17], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[18:19], v[8:9], -v[16:17] v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16 v_mul_f64 v[16:17], v[8:9], s[24:25] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[8:9]| v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[8:9] v_add_f64 v[6:7], v[6:7], -v[18:19] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_rndne_f64_e32 v[16:17], v[16:17] v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6 v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[16:17], s[16:17], v[8:9] v_fma_f64 v[18:19], v[16:17], s[18:19], v[18:19] v_cvt_i32_f64_e32 v16, v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], s[26:27], s[20:21] v_fma_f64 v[20:21], v[18:19], v[20:21], s[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], v[20:21], s[14:15] v_fma_f64 v[20:21], v[18:19], v[20:21], s[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], v[20:21], s[10:11] v_fma_f64 v[20:21], v[18:19], v[20:21], s[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3] v_fma_f64 v[20:21], v[18:19], v[20:21], s[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[18:19], v[20:21], s[6:7] v_fma_f64 v[20:21], v[18:19], v[20:21], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[18:19], v[20:21], 1.0 v_ldexp_f64 v[16:17], v[18:19], v16 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v17, 0x7ff00000, v17, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo v_cndmask_b32_e32 v8, 0, v16, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v9, 0, v17, s0 v_cmp_neq_f64_e64 s0, 0, v[4:5] v_fma_f64 v[6:7], v[8:9], v[6:7], v[8:9] v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x204 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8 v_dual_mov_b32 v8, v6 :: v_dual_and_b32 v9, 0x7fffffff, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_scale_f64 v[16:17], null, v[8:9], v[8:9], s[58:59] v_div_scale_f64 v[8:9], vcc_lo, s[58:59], v[8:9], s[58:59] v_rcp_f64_e32 v[18:19], v[16:17] s_waitcnt_depctr 0xfff v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19] v_mul_f64 v[20:21], v[8:9], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[16:17], v[20:21], v[8:9] v_div_fmas_f64 v[8:9], v[8:9], v[18:19], v[20:21] v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_div_fixup_f64 v[6:7], v[8:9], |v[6:7]|, s[58:59] v_readlane_b32 s59, v40, 25 v_readlane_b32 s58, v40, 24 v_cndmask_b32_e32 v7, 0, v7, vcc_lo s_and_b32 vcc_lo, s0, vcc_lo s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v4, 0, v6, vcc_lo v_cndmask_b32_e64 v5, 0x7ff00000, v7, s0 v_add_f64 v[6:7], v[0:1], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64 v[6:7], v[6:7], v[4:5] v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[16:17], v[8:9] s_waitcnt_depctr 0xfff v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] v_div_scale_f64 v[18:19], vcc_lo, v[0:1], v[6:7], v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[20:21], v[18:19], v[16:17] v_fma_f64 v[8:9], -v[8:9], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[8:9], v[8:9], v[16:17], v[20:21] v_div_fixup_f64 v[0:1], v[8:9], v[6:7], v[0:1] v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[16:17], v[8:9] s_waitcnt_depctr 0xfff v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] v_div_scale_f64 v[18:19], vcc_lo, v[2:3], v[6:7], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[20:21], v[18:19], v[16:17] v_fma_f64 v[8:9], -v[8:9], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[8:9], v[8:9], v[16:17], v[20:21] v_div_fixup_f64 v[2:3], v[8:9], v[6:7], v[2:3] v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[2:3], v[14:15], v[2:3] v_rcp_f64_e32 v[16:17], v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_fma_f64 v[0:1], v[10:11], v[0:1], v[2:3] s_waitcnt_depctr 0xfff v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0 v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17] v_div_scale_f64 v[18:19], vcc_lo, v[4:5], v[6:7], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[20:21], v[18:19], v[16:17] v_fma_f64 v[8:9], -v[8:9], v[20:21], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[8:9], v[8:9], v[16:17], v[20:21] v_div_fixup_f64 v[4:5], v[8:9], v[6:7], v[4:5] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[0:1], v[12:13], v[4:5], v[0:1] s_or_saveexec_b32 s0, -1 scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload s_mov_b32 exec_lo, s0 s_waitcnt vmcnt(0) s_setpc_b64 s[30:31] .Lfunc_end0: .size _Z24weno_onesided_derivativeddddd, .Lfunc_end0-_Z24weno_onesided_derivativeddddd ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 15080 ; NumSgprs: 64 ; NumVgprs: 50 ; ScratchSize: 8 ; MemoryBound: 0 .text .protected _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi ; -- Begin function _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .globl _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .p2align 8 .type _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi,@function _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: ; @_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi ; %bb.0: s_mov_b64 s[62:63], s[0:1] s_load_b64 s[0:1], s[0:1], 0x8c s_clause 0x1 s_load_b64 s[66:67], s[62:63], 0x50 s_load_b32 s2, s[62:63], 0x58 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v2, v0, 10, 10 v_bfe_u32 v3, v0, 20, 10 s_mov_b32 s32, 0 s_waitcnt lgkmcnt(0) s_and_b32 s3, s0, 0xffff s_lshr_b32 s0, s0, 16 s_and_b32 s1, s1, 0xffff v_mad_u64_u32 v[65:66], null, s13, s3, v[1:2] v_mad_u64_u32 v[0:1], null, s14, s0, v[2:3] v_mad_u64_u32 v[60:61], null, s15, s1, v[3:4] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_gt_i32_e32 vcc_lo, s66, v65 v_cmp_gt_i32_e64 s0, s67, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e64 s1, s2, v60 s_and_b32 s0, vcc_lo, s0 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_b32 s0, s0, s1 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB1_32 ; %bb.1: v_cvt_f64_i32_e32 v[1:2], v60 s_add_i32 s2, s2, -1 v_cvt_f64_i32_e32 v[3:4], v0 v_add_nc_u32_e32 v7, 2, v0 v_add_nc_u32_e32 v9, 3, v0 v_add_nc_u32_e32 v11, -1, v0 v_add_nc_u32_e32 v13, -2, v0 v_cvt_f64_i32_e32 v[63:64], s2 v_add_nc_u32_e32 v5, 1, v0 v_add_nc_u32_e32 v0, -3, v0 v_cvt_f64_i32_e32 v[7:8], v7 v_cvt_f64_i32_e32 v[9:10], v9 v_cvt_f64_i32_e32 v[11:12], v11 v_cvt_f64_i32_e32 v[13:14], v13 v_cvt_f64_i32_e32 v[15:16], v0 v_cvt_f64_i32_e32 v[17:18], v65 s_add_i32 s0, s67, -1 ; implicit-def: $vgpr41_vgpr42 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cvt_f64_i32_e32 v[19:20], s0 s_add_i32 s0, s66, -1 v_cvt_f64_i32_e32 v[66:67], s0 v_max_f64 v[0:1], v[1:2], 0 v_max_f64 v[2:3], v[3:4], 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[63:64] v_cmp_gt_f64_e64 s0, v[2:3], v[19:20] v_cndmask_b32_e32 v0, v0, v63, vcc_lo v_cvt_f64_i32_e32 v[5:6], v5 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v3, v3, v20, s0 v_cndmask_b32_e64 v2, v2, v19, s0 v_cvt_i32_f64_e32 v61, v[2:3] s_delay_alu instid0(VALU_DEP_4) v_max_f64 v[4:5], v[5:6], 0 v_max_f64 v[6:7], v[7:8], 0 v_max_f64 v[8:9], v[9:10], 0 v_max_f64 v[10:11], v[11:12], 0 v_max_f64 v[12:13], v[13:14], 0 v_max_f64 v[14:15], v[15:16], 0 v_max_f64 v[16:17], v[17:18], 0 v_cmp_gt_f64_e64 s1, v[4:5], v[19:20] v_cmp_gt_f64_e64 s2, v[6:7], v[19:20] v_cmp_gt_f64_e64 s3, v[8:9], v[19:20] v_cmp_gt_f64_e64 s4, v[10:11], v[19:20] v_cmp_gt_f64_e64 s5, v[12:13], v[19:20] v_cmp_gt_f64_e64 s6, v[14:15], v[19:20] v_cmp_gt_f64_e64 s7, v[16:17], v[66:67] v_cndmask_b32_e64 v5, v5, v20, s1 v_cndmask_b32_e64 v4, v4, v19, s1 v_cndmask_b32_e64 v7, v7, v20, s2 v_cndmask_b32_e64 v9, v9, v20, s3 v_cndmask_b32_e64 v6, v6, v19, s2 v_cndmask_b32_e64 v8, v8, v19, s3 v_cvt_i32_f64_e32 v2, v[4:5] v_cndmask_b32_e32 v1, v1, v64, vcc_lo v_cndmask_b32_e64 v17, v17, v67, s7 v_cndmask_b32_e64 v16, v16, v66, s7 v_cvt_i32_f64_e32 v3, v[6:7] v_cvt_i32_f64_e32 v4, v[8:9] v_cvt_i32_f64_e32 v18, v[0:1] v_cndmask_b32_e64 v1, v11, v20, s4 v_cndmask_b32_e64 v11, v13, v20, s5 v_cndmask_b32_e64 v13, v15, v20, s6 v_cndmask_b32_e64 v0, v10, v19, s4 v_cndmask_b32_e64 v10, v12, v19, s5 v_cndmask_b32_e64 v12, v14, v19, s6 v_cvt_i32_f64_e32 v62, v[16:17] s_clause 0x1 s_load_b128 s[68:71], s[62:63], 0x18 s_load_b64 s[0:1], s[62:63], 0x28 v_cvt_i32_f64_e32 v0, v[0:1] v_cvt_i32_f64_e32 v1, v[10:11] v_cvt_i32_f64_e32 v5, v[12:13] v_mul_lo_u32 v6, v18, s67 s_delay_alu instid0(VALU_DEP_1) v_add_nc_u32_e32 v2, v6, v2 v_add_nc_u32_e32 v7, v6, v61 v_add_nc_u32_e32 v10, v6, v3 v_add_nc_u32_e32 v12, v6, v4 v_add_nc_u32_e32 v3, v6, v0 v_add_nc_u32_e32 v8, v6, v1 v_mul_lo_u32 v47, v7, s66 v_add_nc_u32_e32 v6, v6, v5 v_mad_u64_u32 v[0:1], null, v2, s66, v[62:63] v_mad_u64_u32 v[4:5], null, v3, s66, v[62:63] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_mad_u64_u32 v[2:3], null, v6, s66, v[62:63] v_add_nc_u32_e32 v56, v47, v62 v_mad_u64_u32 v[6:7], null, v8, s66, v[62:63] v_mad_u64_u32 v[8:9], null, v10, s66, v[62:63] v_ashrrev_i32_e32 v57, 31, v56 v_mad_u64_u32 v[10:11], null, v12, s66, v[62:63] v_ashrrev_i32_e32 v3, 31, v2 v_ashrrev_i32_e32 v7, 31, v6 s_delay_alu instid0(VALU_DEP_4) v_lshlrev_b64 v[12:13], 3, v[56:57] v_ashrrev_i32_e32 v1, 31, v0 v_ashrrev_i32_e32 v9, 31, v8 v_lshlrev_b64 v[18:19], 3, v[2:3] v_lshlrev_b64 v[6:7], 3, v[6:7] v_ashrrev_i32_e32 v11, 31, v10 s_waitcnt lgkmcnt(0) v_add_co_u32 v14, vcc_lo, s70, v12 v_add_co_ci_u32_e32 v15, vcc_lo, s71, v13, vcc_lo v_add_co_u32 v16, vcc_lo, s0, v12 v_add_co_ci_u32_e32 v17, vcc_lo, s1, v13, vcc_lo global_load_b64 v[2:3], v[14:15], off global_load_b64 v[20:21], v[16:17], off v_lshlrev_b64 v[0:1], 3, v[0:1] v_add_co_u32 v14, vcc_lo, s68, v18 v_add_co_ci_u32_e32 v15, vcc_lo, s69, v19, vcc_lo v_lshlrev_b64 v[8:9], 3, v[8:9] v_add_co_u32 v6, vcc_lo, s68, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s69, v7, vcc_lo v_lshlrev_b64 v[10:11], 3, v[10:11] v_add_co_u32 v0, vcc_lo, s68, v0 v_ashrrev_i32_e32 v5, 31, v4 v_add_co_ci_u32_e32 v1, vcc_lo, s69, v1, vcc_lo v_add_co_u32 v8, vcc_lo, s68, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s69, v9, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_lshlrev_b64 v[4:5], 3, v[4:5] v_add_co_u32 v10, vcc_lo, s68, v10 v_add_co_ci_u32_e32 v11, vcc_lo, s69, v11, vcc_lo v_add_co_u32 v12, vcc_lo, s68, v12 v_add_co_ci_u32_e32 v13, vcc_lo, s69, v13, vcc_lo v_add_co_u32 v16, vcc_lo, s68, v4 v_add_co_ci_u32_e32 v17, vcc_lo, s69, v5, vcc_lo s_clause 0x6 global_load_b64 v[68:69], v[0:1], off global_load_b64 v[4:5], v[8:9], off global_load_b64 v[10:11], v[10:11], off global_load_b64 v[58:59], v[12:13], off global_load_b64 v[18:19], v[14:15], off global_load_b64 v[6:7], v[6:7], off global_load_b64 v[70:71], v[16:17], off s_load_b64 s[70:71], s[62:63], 0x60 ; implicit-def: $vgpr0_vgpr1 s_waitcnt vmcnt(8) lgkmcnt(0) v_cmp_ngt_f64_e64 s64, s[70:71], v[2:3] s_waitcnt vmcnt(7) v_cmp_ngt_f64_e64 s33, s[70:71], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s0, s64, s33 s_and_saveexec_b32 s1, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s65, exec_lo, s1 s_cbranch_execz .LBB1_3 ; %bb.2: s_waitcnt vmcnt(1) v_add_f64 v[0:1], v[6:7], -v[18:19] s_waitcnt vmcnt(0) v_add_f64 v[2:3], v[70:71], -v[6:7] v_add_f64 v[6:7], v[58:59], -v[70:71] v_add_f64 v[8:9], v[68:69], -v[58:59] v_add_f64 v[12:13], v[4:5], -v[68:69] v_add_f64 v[4:5], v[10:11], -v[4:5] s_getpc_b64 s[72:73] s_add_u32 s72, s72, _Z24weno_onesided_derivativeddddd@rel32@lo+4 s_addc_u32 s73, s73, _Z24weno_onesided_derivativeddddd@rel32@hi+12 v_div_scale_f64 v[10:11], null, s[70:71], s[70:71], v[0:1] v_div_scale_f64 v[14:15], null, s[70:71], s[70:71], v[2:3] v_div_scale_f64 v[16:17], null, s[70:71], s[70:71], v[6:7] v_div_scale_f64 v[18:19], null, s[70:71], s[70:71], v[8:9] v_div_scale_f64 v[20:21], null, s[70:71], s[70:71], v[12:13] v_div_scale_f64 v[22:23], null, s[70:71], s[70:71], v[4:5] v_div_scale_f64 v[50:51], vcc_lo, v[0:1], s[70:71], v[0:1] v_rcp_f64_e32 v[24:25], v[10:11] v_rcp_f64_e32 v[26:27], v[14:15] v_rcp_f64_e32 v[28:29], v[16:17] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_rcp_f64_e32 v[30:31], v[18:19] v_rcp_f64_e32 v[32:33], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3) v_rcp_f64_e32 v[34:35], v[22:23] v_fma_f64 v[36:37], -v[10:11], v[24:25], 1.0 v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0 v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0 v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0 v_fma_f64 v[48:49], -v[22:23], v[34:35], 1.0 v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25] v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27] v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29] v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31] v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33] v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35] v_fma_f64 v[36:37], -v[10:11], v[24:25], 1.0 v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0 v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0 v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0 v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0 v_fma_f64 v[48:49], -v[22:23], v[34:35], 1.0 v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25] v_div_scale_f64 v[36:37], s0, v[2:3], s[70:71], v[2:3] v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27] v_div_scale_f64 v[38:39], s1, v[6:7], s[70:71], v[6:7] v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29] v_div_scale_f64 v[40:41], s2, v[8:9], s[70:71], v[8:9] v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31] v_div_scale_f64 v[42:43], s3, v[12:13], s[70:71], v[12:13] v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33] v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35] v_div_scale_f64 v[44:45], s4, v[4:5], s[70:71], v[4:5] v_mul_f64 v[48:49], v[50:51], v[24:25] v_mul_f64 v[52:53], v[36:37], v[26:27] v_mul_f64 v[54:55], v[38:39], v[28:29] v_mul_f64 v[72:73], v[40:41], v[30:31] v_mul_f64 v[74:75], v[42:43], v[32:33] v_mul_f64 v[76:77], v[44:45], v[34:35] v_fma_f64 v[10:11], -v[10:11], v[48:49], v[50:51] v_fma_f64 v[14:15], -v[14:15], v[52:53], v[36:37] v_fma_f64 v[16:17], -v[16:17], v[54:55], v[38:39] v_fma_f64 v[18:19], -v[18:19], v[72:73], v[40:41] v_fma_f64 v[20:21], -v[20:21], v[74:75], v[42:43] v_fma_f64 v[22:23], -v[22:23], v[76:77], v[44:45] v_div_fmas_f64 v[10:11], v[10:11], v[24:25], v[48:49] s_mov_b32 vcc_lo, s0 v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[52:53] s_mov_b32 vcc_lo, s1 v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[54:55] s_mov_b32 vcc_lo, s2 v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[72:73] s_mov_b32 vcc_lo, s3 v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[74:75] s_mov_b32 vcc_lo, s4 v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[76:77] v_div_fixup_f64 v[0:1], v[10:11], s[70:71], v[0:1] v_div_fixup_f64 v[43:44], v[14:15], s[70:71], v[2:3] v_div_fixup_f64 v[45:46], v[16:17], s[70:71], v[6:7] v_div_fixup_f64 v[50:51], v[18:19], s[70:71], v[8:9] v_div_fixup_f64 v[52:53], v[20:21], s[70:71], v[12:13] v_div_fixup_f64 v[54:55], v[22:23], s[70:71], v[4:5] v_dual_mov_b32 v2, v43 :: v_dual_mov_b32 v3, v44 v_dual_mov_b32 v4, v45 :: v_dual_mov_b32 v5, v46 v_dual_mov_b32 v6, v50 :: v_dual_mov_b32 v7, v51 v_dual_mov_b32 v8, v52 :: v_dual_mov_b32 v9, v53 s_swappc_b64 s[30:31], s[72:73] v_dual_mov_b32 v41, v0 :: v_dual_mov_b32 v42, v1 v_dual_mov_b32 v0, v54 :: v_dual_mov_b32 v1, v55 v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v3, v53 v_dual_mov_b32 v4, v50 :: v_dual_mov_b32 v5, v51 v_dual_mov_b32 v6, v45 :: v_dual_mov_b32 v7, v46 v_dual_mov_b32 v8, v43 :: v_dual_mov_b32 v9, v44 s_swappc_b64 s[30:31], s[72:73] ; implicit-def: $vgpr6_vgpr7 ; implicit-def: $vgpr18_vgpr19 ; implicit-def: $vgpr20_vgpr21 ; implicit-def: $vgpr2_vgpr3 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $vgpr10_vgpr11 .LBB1_3: ; %Flow376 s_and_not1_saveexec_b32 s4, s65 s_cbranch_execz .LBB1_11 ; %bb.4: v_add_f64 v[8:9], s[70:71], s[70:71] v_mov_b32_e32 v14, 0 s_waitcnt vmcnt(6) v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v26, v68 v_dual_mov_b32 v0, s70 :: v_dual_mov_b32 v1, s71 v_mov_b32_e32 v27, v69 s_and_saveexec_b32 s0, s64 s_cbranch_execz .LBB1_6 ; %bb.5: v_mul_f64 v[12:13], s[70:71], 0x40080000 v_dual_mov_b32 v2, s70 :: v_dual_mov_b32 v3, s71 v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9 v_dual_mov_b32 v14, v68 :: v_dual_mov_b32 v15, v69 s_waitcnt vmcnt(5) v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4 s_waitcnt vmcnt(4) v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11 v_dual_mov_b32 v8, v12 :: v_dual_mov_b32 v9, v13 .LBB1_6: s_or_b32 exec_lo, exec_lo, s0 ; implicit-def: $vgpr10_vgpr11 ; implicit-def: $sgpr0_sgpr1 ; implicit-def: $sgpr2_sgpr3 s_and_saveexec_b32 s5, s33 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s5, exec_lo, s5 s_cbranch_execz .LBB1_8 ; %bb.7: s_mov_b32 s2, 0 s_waitcnt vmcnt(4) v_mul_f64 v[10:11], s[70:71], -2.0 s_mov_b32 s3, 0xc0080000 s_xor_b32 s1, s71, 0x80000000 s_mov_b32 s0, s70 ; implicit-def: $vgpr20_vgpr21 .LBB1_8: ; %Flow373 s_or_saveexec_b32 s5, s5 v_dual_mov_b32 v13, s3 :: v_dual_mov_b32 v12, s2 v_dual_mov_b32 v17, s1 :: v_dual_mov_b32 v16, s0 s_waitcnt vmcnt(0) v_dual_mov_b32 v24, v70 :: v_dual_mov_b32 v25, v71 v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6 s_xor_b32 exec_lo, exec_lo, s5 ; %bb.9: v_xor_b32_e32 v21, 0x80000000, v21 s_xor_b32 s1, s71, 0x80000000 s_mov_b32 s0, s70 v_mov_b32_e32 v24, 0 v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v11, s1 v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v16, v20 v_dual_mov_b32 v13, -2.0 :: v_dual_mov_b32 v10, s0 v_dual_mov_b32 v17, v21 :: v_dual_mov_b32 v22, v70 v_mov_b32_e32 v23, v71 v_dual_mov_b32 v19, v7 :: v_dual_mov_b32 v18, v6 ; %bb.10: ; %_Z14select_stencilRdS_S_S_S_S_S_S_S_S_S_S_S_S_dddddddddddddddd.exit.i.i s_or_b32 exec_lo, exec_lo, s5 v_add_f64 v[4:5], v[4:5], -v[26:27] v_add_f64 v[6:7], v[8:9], -v[0:1] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[22:23], -v[18:19] v_div_scale_f64 v[20:21], null, v[6:7], v[6:7], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[28:29], v[20:21] s_waitcnt_depctr 0xfff v_fma_f64 v[30:31], -v[20:21], v[28:29], 1.0 v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], -v[20:21], v[28:29], 1.0 v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] v_div_scale_f64 v[30:31], vcc_lo, v[4:5], v[6:7], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[32:33], v[30:31], v[28:29] v_fma_f64 v[20:21], -v[20:21], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[20:21], v[20:21], v[28:29], v[32:33] v_div_fixup_f64 v[20:21], v[20:21], v[6:7], v[4:5] v_add_f64 v[4:5], v[26:27], -v[14:15] v_add_f64 v[6:7], v[0:1], -v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[26:27], null, v[6:7], v[6:7], v[4:5] v_rcp_f64_e32 v[28:29], v[26:27] s_waitcnt_depctr 0xfff v_fma_f64 v[30:31], -v[26:27], v[28:29], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] v_fma_f64 v[30:31], -v[26:27], v[28:29], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] v_div_scale_f64 v[30:31], vcc_lo, v[4:5], v[6:7], v[4:5] v_mul_f64 v[32:33], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], -v[26:27], v[32:33], v[30:31] v_div_fmas_f64 v[26:27], v[26:27], v[28:29], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[26:27], v[26:27], v[6:7], v[4:5] v_add_f64 v[4:5], v[14:15], -v[58:59] v_add_f64 v[20:21], v[20:21], -v[26:27] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], v[4:5] v_rcp_f64_e32 v[14:15], v[6:7] s_waitcnt_depctr 0xfff v_fma_f64 v[28:29], -v[6:7], v[14:15], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], v[14:15], v[28:29], v[14:15] v_fma_f64 v[28:29], -v[6:7], v[14:15], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], v[14:15], v[28:29], v[14:15] v_div_scale_f64 v[28:29], vcc_lo, v[4:5], v[2:3], v[4:5] v_mul_f64 v[30:31], v[28:29], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], -v[6:7], v[30:31], v[28:29] v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[30:31] v_add_f64 v[14:15], v[58:59], -v[24:25] v_add_f64 v[24:25], v[24:25], -v[22:23] v_fma_f64 v[22:23], -v[12:13], s[70:71], v[10:11] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[4:5], v[6:7], v[2:3], v[4:5] v_add_f64 v[6:7], -v[16:17], 0 v_div_scale_f64 v[28:29], null, v[6:7], v[6:7], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[30:31], v[28:29] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[14:15], v[6:7], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[34:35], v[32:33], v[30:31] v_fma_f64 v[28:29], -v[28:29], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[28:29], v[28:29], v[30:31], v[34:35] v_div_fixup_f64 v[14:15], v[28:29], v[6:7], v[14:15] v_add_f64 v[28:29], v[16:17], -v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[30:31], null, v[28:29], v[28:29], v[24:25] v_rcp_f64_e32 v[32:33], v[30:31] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[24:25], v[28:29], v[24:25] v_mul_f64 v[36:37], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], -v[30:31], v[36:37], v[34:35] v_div_fmas_f64 v[30:31], v[30:31], v[32:33], v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[24:25], v[30:31], v[28:29], v[24:25] v_div_scale_f64 v[28:29], null, v[22:23], v[22:23], v[18:19] v_rcp_f64_e32 v[30:31], v[28:29] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[18:19], v[22:23], v[18:19] v_mul_f64 v[34:35], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], -v[28:29], v[34:35], v[32:33] v_div_fmas_f64 v[28:29], v[28:29], v[30:31], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[18:19], v[28:29], v[22:23], v[18:19] v_add_f64 v[22:23], v[8:9], -v[2:3] v_add_f64 v[18:19], v[24:25], -v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[28:29], null, v[22:23], v[22:23], v[20:21] v_rcp_f64_e32 v[30:31], v[28:29] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[20:21], v[22:23], v[20:21] v_mul_f64 v[34:35], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], -v[28:29], v[34:35], v[32:33] v_div_fmas_f64 v[28:29], v[28:29], v[30:31], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[20:21], v[28:29], v[22:23], v[20:21] v_add_f64 v[22:23], v[26:27], -v[4:5] v_div_scale_f64 v[26:27], null, v[0:1], v[0:1], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[28:29], v[26:27] s_waitcnt_depctr 0xfff v_fma_f64 v[30:31], -v[26:27], v[28:29], 1.0 v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], -v[26:27], v[28:29], 1.0 v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] v_div_scale_f64 v[30:31], vcc_lo, v[22:23], v[0:1], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[32:33], v[30:31], v[28:29] v_fma_f64 v[26:27], -v[26:27], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fmas_f64 v[26:27], v[26:27], v[28:29], v[32:33] v_add_f64 v[28:29], v[2:3], -v[16:17] v_div_fixup_f64 v[22:23], v[26:27], v[0:1], v[22:23] v_add_f64 v[26:27], v[4:5], -v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[20:21], -v[22:23] v_div_scale_f64 v[30:31], null, v[28:29], v[28:29], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[32:33], v[30:31] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[26:27], v[28:29], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[36:37], v[34:35], v[32:33] v_fma_f64 v[30:31], -v[30:31], v[36:37], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[30:31], v[30:31], v[32:33], v[36:37] v_div_fixup_f64 v[26:27], v[30:31], v[28:29], v[26:27] v_add_f64 v[28:29], v[14:15], -v[24:25] v_add_f64 v[30:31], -v[10:11], 0 v_fma_f64 v[24:25], -v[12:13], s[70:71], v[16:17] v_add_f64 v[16:17], v[0:1], -v[16:17] v_add_f64 v[10:11], v[2:3], -v[10:11] v_fma_f64 v[12:13], -v[12:13], s[70:71], 0 v_add_f64 v[2:3], -v[2:3], 0 v_add_f64 v[0:1], -v[0:1], 0 v_div_scale_f64 v[32:33], null, v[30:31], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[0:1], v[2:3], v[0:1] v_rcp_f64_e32 v[34:35], v[32:33] s_waitcnt_depctr 0xfff v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35] v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35] v_div_scale_f64 v[36:37], vcc_lo, v[28:29], v[30:31], v[28:29] v_mul_f64 v[38:39], v[36:37], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], -v[32:33], v[38:39], v[36:37] v_div_fmas_f64 v[32:33], v[32:33], v[34:35], v[38:39] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[28:29], v[32:33], v[30:31], v[28:29] v_div_scale_f64 v[32:33], null, v[24:25], v[24:25], v[18:19] v_rcp_f64_e32 v[34:35], v[32:33] s_waitcnt_depctr 0xfff v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35] v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35] v_div_scale_f64 v[36:37], vcc_lo, v[18:19], v[24:25], v[18:19] v_mul_f64 v[38:39], v[36:37], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], -v[32:33], v[38:39], v[36:37] v_div_fmas_f64 v[32:33], v[32:33], v[34:35], v[38:39] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[18:19], v[32:33], v[24:25], v[18:19] v_div_scale_f64 v[24:25], null, v[8:9], v[8:9], v[20:21] v_add_f64 v[18:19], v[28:29], -v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[32:33], v[24:25] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[24:25], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], -v[24:25], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[20:21], v[8:9], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[36:37], v[34:35], v[32:33] v_fma_f64 v[24:25], -v[24:25], v[36:37], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[24:25], v[24:25], v[32:33], v[36:37] v_div_fixup_f64 v[8:9], v[24:25], v[8:9], v[20:21] v_add_f64 v[20:21], v[22:23], -v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[24:25], null, v[16:17], v[16:17], v[20:21] v_rcp_f64_e32 v[32:33], v[24:25] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[24:25], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_fma_f64 v[34:35], -v[24:25], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[20:21], v[16:17], v[20:21] v_mul_f64 v[36:37], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], -v[24:25], v[36:37], v[34:35] v_div_fmas_f64 v[24:25], v[24:25], v[32:33], v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[16:17], v[24:25], v[16:17], v[20:21] v_add_f64 v[20:21], v[26:27], -v[28:29] v_cmp_lt_f64_e64 s0, |v[16:17]|, |v[8:9]| s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_scale_f64 v[24:25], null, v[10:11], v[10:11], v[20:21] v_cndmask_b32_e64 v9, v9, v17, s0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_rcp_f64_e32 v[32:33], v[24:25] v_cndmask_b32_e64 v8, v8, v16, s0 v_cmp_lt_f64_e64 s0, |v[26:27]|, |v[22:23]| v_mul_f64 v[0:1], v[0:1], v[8:9] v_mul_f64 v[8:9], v[26:27], v[28:29] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[24:25], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_fma_f64 v[34:35], -v[24:25], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[20:21], v[10:11], v[20:21] v_mul_f64 v[36:37], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], -v[24:25], v[36:37], v[34:35] v_div_fmas_f64 v[24:25], v[24:25], v[32:33], v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[10:11], v[24:25], v[10:11], v[20:21] v_div_scale_f64 v[20:21], null, v[12:13], v[12:13], v[18:19] v_rcp_f64_e32 v[24:25], v[20:21] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[20:21], v[24:25], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[24:25], v[32:33], v[24:25] v_fma_f64 v[32:33], -v[20:21], v[24:25], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[24:25], v[32:33], v[24:25] v_div_scale_f64 v[32:33], vcc_lo, v[18:19], v[12:13], v[18:19] v_mul_f64 v[34:35], v[32:33], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[20:21], v[34:35], v[32:33] v_div_fmas_f64 v[20:21], v[20:21], v[24:25], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[12:13], v[20:21], v[12:13], v[18:19] v_mul_f64 v[18:19], v[6:7], v[30:31] v_cmp_lt_f64_e64 vcc_lo, |v[10:11]|, |v[12:13]| v_dual_cndmask_b32 v13, v13, v11 :: v_dual_cndmask_b32 v12, v12, v10 v_cmp_lt_f64_e64 vcc_lo, |v[10:11]|, |v[16:17]| s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_mul_f64 v[12:13], v[18:19], v[12:13] v_mul_f64 v[18:19], v[2:3], v[6:7] v_dual_cndmask_b32 v11, v17, v11 :: v_dual_cndmask_b32 v10, v16, v10 v_cmp_lt_f64_e64 vcc_lo, |v[28:29]|, |v[26:27]| v_mul_f64 v[10:11], v[18:19], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v13, v11, v13 :: v_dual_cndmask_b32 v12, v10, v12 v_cndmask_b32_e64 v1, v1, v11, s0 v_cndmask_b32_e64 v0, v0, v10, s0 v_dual_cndmask_b32 v10, v26, v28 :: v_dual_cndmask_b32 v11, v27, v29 v_cmp_ngt_f64_e32 vcc_lo, 0, v[8:9] v_dual_cndmask_b32 v9, 0, v11 :: v_dual_cndmask_b32 v8, 0, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[6:7], v[6:7], v[8:9], v[14:15] v_cndmask_b32_e64 v8, v22, v26, s0 v_cndmask_b32_e64 v9, v23, v27, s0 v_add_f64 v[41:42], v[6:7], v[12:13] v_mul_f64 v[6:7], v[22:23], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_ngt_f64_e32 vcc_lo, 0, v[6:7] v_dual_cndmask_b32 v7, 0, v9 :: v_dual_cndmask_b32 v6, 0, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[2:3], v[2:3], v[6:7], v[4:5] v_add_f64 v[0:1], v[2:3], v[0:1] .LBB1_11: ; %Flow377 s_or_b32 exec_lo, exec_lo, s4 s_waitcnt vmcnt(1) v_add_nc_u32_e32 v6, -3, v65 v_add_nc_u32_e32 v8, -2, v65 v_add_nc_u32_e32 v10, -1, v65 v_add_nc_u32_e32 v2, 1, v65 v_add_nc_u32_e32 v4, 2, v65 v_cvt_f64_i32_e32 v[6:7], v6 v_cvt_f64_i32_e32 v[8:9], v8 v_cvt_f64_i32_e32 v[10:11], v10 v_cvt_f64_i32_e32 v[2:3], v2 v_add_nc_u32_e32 v12, 3, v65 v_cvt_f64_i32_e32 v[4:5], v4 s_waitcnt vmcnt(0) v_cmp_lt_f64_e64 s5, |v[68:69]|, |v[70:71]| s_clause 0x2 s_load_b64 s[6:7], s[62:63], 0x0 s_load_b128 s[8:11], s[62:63], 0x30 s_load_b64 s[70:71], s[62:63], 0x68 v_cvt_f64_i32_e32 v[12:13], v12 v_max_f64 v[6:7], v[6:7], 0 v_max_f64 v[8:9], v[8:9], 0 v_max_f64 v[10:11], v[10:11], 0 v_max_f64 v[2:3], v[2:3], 0 v_max_f64 v[4:5], v[4:5], 0 v_cndmask_b32_e64 v1, v42, v1, s5 v_cndmask_b32_e64 v0, v41, v0, s5 ; implicit-def: $vgpr41_vgpr42 v_max_f64 v[12:13], v[12:13], 0 v_cmp_gt_f64_e64 s1, v[6:7], v[66:67] v_cmp_gt_f64_e64 s2, v[8:9], v[66:67] v_cmp_gt_f64_e64 s3, v[10:11], v[66:67] v_cmp_gt_f64_e32 vcc_lo, v[2:3], v[66:67] v_cmp_gt_f64_e64 s0, v[4:5], v[66:67] v_cmp_gt_f64_e64 s4, v[12:13], v[66:67] v_cndmask_b32_e64 v7, v7, v67, s1 v_cndmask_b32_e64 v6, v6, v66, s1 v_cndmask_b32_e64 v9, v9, v67, s2 v_cndmask_b32_e32 v3, v3, v67, vcc_lo v_cndmask_b32_e64 v8, v8, v66, s2 v_cndmask_b32_e64 v11, v11, v67, s3 v_cvt_i32_f64_e32 v17, v[6:7] v_cndmask_b32_e64 v10, v10, v66, s3 v_cndmask_b32_e32 v2, v2, v66, vcc_lo v_cvt_i32_f64_e32 v18, v[8:9] v_cndmask_b32_e64 v5, v5, v67, s0 v_cndmask_b32_e64 v4, v4, v66, s0 v_cvt_i32_f64_e32 v10, v[10:11] v_cvt_i32_f64_e32 v16, v[2:3] v_cndmask_b32_e64 v13, v13, v67, s4 v_cndmask_b32_e64 v12, v12, v66, s4 v_cvt_i32_f64_e32 v11, v[4:5] v_lshlrev_b64 v[2:3], 3, v[56:57] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cvt_i32_f64_e32 v12, v[12:13] s_waitcnt lgkmcnt(0) v_add_co_u32 v4, vcc_lo, s6, v2 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo v_add_co_u32 v6, vcc_lo, s8, v2 v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo v_add_co_u32 v8, vcc_lo, s10, v2 v_add_co_ci_u32_e32 v9, vcc_lo, s11, v3, vcc_lo global_store_b64 v[4:5], v[0:1], off global_load_b64 v[2:3], v[6:7], off global_load_b64 v[14:15], v[8:9], off v_add_nc_u32_e32 v4, v47, v17 v_add_nc_u32_e32 v6, v47, v18 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_ashrrev_i32_e32 v5, 31, v4 v_add_nc_u32_e32 v8, v47, v10 v_add_nc_u32_e32 v0, v47, v16 v_ashrrev_i32_e32 v7, 31, v6 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[4:5], 3, v[4:5] v_ashrrev_i32_e32 v9, 31, v8 v_add_nc_u32_e32 v10, v47, v11 s_delay_alu instid0(VALU_DEP_4) v_lshlrev_b64 v[6:7], 3, v[6:7] v_ashrrev_i32_e32 v1, 31, v0 v_add_nc_u32_e32 v12, v47, v12 v_lshlrev_b64 v[8:9], 3, v[8:9] v_add_co_u32 v4, vcc_lo, s68, v4 v_ashrrev_i32_e32 v11, 31, v10 v_add_co_ci_u32_e32 v5, vcc_lo, s69, v5, vcc_lo v_lshlrev_b64 v[0:1], 3, v[0:1] v_add_co_u32 v6, vcc_lo, s68, v6 v_ashrrev_i32_e32 v13, 31, v12 v_add_co_ci_u32_e32 v7, vcc_lo, s69, v7, vcc_lo v_lshlrev_b64 v[10:11], 3, v[10:11] v_add_co_u32 v8, vcc_lo, s68, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s69, v9, vcc_lo v_lshlrev_b64 v[12:13], 3, v[12:13] v_add_co_u32 v0, vcc_lo, s68, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s69, v1, vcc_lo v_add_co_u32 v10, vcc_lo, s68, v10 v_add_co_ci_u32_e32 v11, vcc_lo, s69, v11, vcc_lo v_add_co_u32 v12, vcc_lo, s68, v12 v_add_co_ci_u32_e32 v13, vcc_lo, s69, v13, vcc_lo s_clause 0x5 global_load_b64 v[18:19], v[4:5], off global_load_b64 v[6:7], v[6:7], off global_load_b64 v[65:66], v[8:9], off global_load_b64 v[67:68], v[0:1], off global_load_b64 v[4:5], v[10:11], off global_load_b64 v[10:11], v[12:13], off ; implicit-def: $vgpr0_vgpr1 s_waitcnt vmcnt(7) v_cmp_ngt_f64_e64 s64, s[70:71], v[2:3] s_waitcnt vmcnt(6) v_cmp_ngt_f64_e64 s33, s[70:71], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s0, s64, s33 s_and_saveexec_b32 s1, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s65, exec_lo, s1 s_cbranch_execz .LBB1_13 ; %bb.12: s_waitcnt vmcnt(4) v_add_f64 v[0:1], v[6:7], -v[18:19] s_waitcnt vmcnt(3) v_add_f64 v[2:3], v[65:66], -v[6:7] v_add_f64 v[6:7], v[58:59], -v[65:66] s_waitcnt vmcnt(2) v_add_f64 v[8:9], v[67:68], -v[58:59] s_waitcnt vmcnt(1) v_add_f64 v[12:13], v[4:5], -v[67:68] s_waitcnt vmcnt(0) v_add_f64 v[4:5], v[10:11], -v[4:5] s_getpc_b64 s[72:73] s_add_u32 s72, s72, _Z24weno_onesided_derivativeddddd@rel32@lo+4 s_addc_u32 s73, s73, _Z24weno_onesided_derivativeddddd@rel32@hi+12 v_div_scale_f64 v[10:11], null, s[70:71], s[70:71], v[0:1] v_div_scale_f64 v[14:15], null, s[70:71], s[70:71], v[2:3] v_div_scale_f64 v[16:17], null, s[70:71], s[70:71], v[6:7] v_div_scale_f64 v[18:19], null, s[70:71], s[70:71], v[8:9] v_div_scale_f64 v[20:21], null, s[70:71], s[70:71], v[12:13] v_div_scale_f64 v[22:23], null, s[70:71], s[70:71], v[4:5] v_div_scale_f64 v[48:49], vcc_lo, v[0:1], s[70:71], v[0:1] v_rcp_f64_e32 v[24:25], v[10:11] v_rcp_f64_e32 v[26:27], v[14:15] v_rcp_f64_e32 v[28:29], v[16:17] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_rcp_f64_e32 v[30:31], v[18:19] v_rcp_f64_e32 v[32:33], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3) v_rcp_f64_e32 v[34:35], v[22:23] v_fma_f64 v[36:37], -v[10:11], v[24:25], 1.0 v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0 v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0 v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0 v_fma_f64 v[46:47], -v[22:23], v[34:35], 1.0 v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25] v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27] v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29] v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31] v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33] v_fma_f64 v[34:35], v[34:35], v[46:47], v[34:35] v_fma_f64 v[36:37], -v[10:11], v[24:25], 1.0 v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0 v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0 v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0 v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0 v_fma_f64 v[46:47], -v[22:23], v[34:35], 1.0 v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25] v_div_scale_f64 v[36:37], s0, v[2:3], s[70:71], v[2:3] v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27] v_div_scale_f64 v[38:39], s1, v[6:7], s[70:71], v[6:7] v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29] v_div_scale_f64 v[40:41], s2, v[8:9], s[70:71], v[8:9] v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31] v_div_scale_f64 v[42:43], s3, v[12:13], s[70:71], v[12:13] v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33] v_fma_f64 v[34:35], v[34:35], v[46:47], v[34:35] v_div_scale_f64 v[44:45], s4, v[4:5], s[70:71], v[4:5] v_mul_f64 v[46:47], v[48:49], v[24:25] v_mul_f64 v[50:51], v[36:37], v[26:27] v_mul_f64 v[52:53], v[38:39], v[28:29] v_mul_f64 v[54:55], v[40:41], v[30:31] v_mul_f64 v[69:70], v[42:43], v[32:33] v_mul_f64 v[71:72], v[44:45], v[34:35] v_fma_f64 v[10:11], -v[10:11], v[46:47], v[48:49] v_fma_f64 v[14:15], -v[14:15], v[50:51], v[36:37] v_fma_f64 v[16:17], -v[16:17], v[52:53], v[38:39] v_fma_f64 v[18:19], -v[18:19], v[54:55], v[40:41] v_fma_f64 v[20:21], -v[20:21], v[69:70], v[42:43] v_fma_f64 v[22:23], -v[22:23], v[71:72], v[44:45] v_div_fmas_f64 v[10:11], v[10:11], v[24:25], v[46:47] s_mov_b32 vcc_lo, s0 v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[50:51] s_mov_b32 vcc_lo, s1 v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[52:53] s_mov_b32 vcc_lo, s2 v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[54:55] s_mov_b32 vcc_lo, s3 v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[69:70] s_mov_b32 vcc_lo, s4 v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[71:72] v_div_fixup_f64 v[0:1], v[10:11], s[70:71], v[0:1] v_div_fixup_f64 v[43:44], v[14:15], s[70:71], v[2:3] v_div_fixup_f64 v[45:46], v[16:17], s[70:71], v[6:7] v_div_fixup_f64 v[50:51], v[18:19], s[70:71], v[8:9] v_div_fixup_f64 v[52:53], v[20:21], s[70:71], v[12:13] v_div_fixup_f64 v[54:55], v[22:23], s[70:71], v[4:5] v_dual_mov_b32 v2, v43 :: v_dual_mov_b32 v3, v44 v_dual_mov_b32 v4, v45 :: v_dual_mov_b32 v5, v46 v_dual_mov_b32 v6, v50 :: v_dual_mov_b32 v7, v51 v_dual_mov_b32 v8, v52 :: v_dual_mov_b32 v9, v53 s_swappc_b64 s[30:31], s[72:73] v_dual_mov_b32 v41, v0 :: v_dual_mov_b32 v42, v1 v_dual_mov_b32 v0, v54 :: v_dual_mov_b32 v1, v55 v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v3, v53 v_dual_mov_b32 v4, v50 :: v_dual_mov_b32 v5, v51 v_dual_mov_b32 v6, v45 :: v_dual_mov_b32 v7, v46 v_dual_mov_b32 v8, v43 :: v_dual_mov_b32 v9, v44 s_swappc_b64 s[30:31], s[72:73] ; implicit-def: $vgpr6_vgpr7 ; implicit-def: $vgpr18_vgpr19 ; implicit-def: $vgpr14_vgpr15 ; implicit-def: $vgpr2_vgpr3 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $vgpr10_vgpr11 .LBB1_13: ; %Flow370 s_and_not1_saveexec_b32 s4, s65 s_cbranch_execz .LBB1_21 ; %bb.14: v_add_f64 v[8:9], s[70:71], s[70:71] v_mov_b32_e32 v20, 0 s_waitcnt vmcnt(2) v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v26, v67 v_dual_mov_b32 v0, s70 :: v_dual_mov_b32 v1, s71 v_mov_b32_e32 v27, v68 s_and_saveexec_b32 s0, s64 s_cbranch_execz .LBB1_16 ; %bb.15: v_mul_f64 v[12:13], s[70:71], 0x40080000 v_dual_mov_b32 v2, s70 :: v_dual_mov_b32 v3, s71 v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9 v_dual_mov_b32 v20, v67 :: v_dual_mov_b32 v21, v68 s_waitcnt vmcnt(1) v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4 s_waitcnt vmcnt(0) v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11 v_dual_mov_b32 v8, v12 :: v_dual_mov_b32 v9, v13 .LBB1_16: s_or_b32 exec_lo, exec_lo, s0 ; implicit-def: $vgpr10_vgpr11 ; implicit-def: $sgpr0_sgpr1 ; implicit-def: $sgpr2_sgpr3 s_and_saveexec_b32 s5, s33 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s5, exec_lo, s5 s_cbranch_execz .LBB1_18 ; %bb.17: s_mov_b32 s2, 0 s_waitcnt vmcnt(0) v_mul_f64 v[10:11], s[70:71], -2.0 s_mov_b32 s3, 0xc0080000 s_xor_b32 s1, s71, 0x80000000 s_mov_b32 s0, s70 ; implicit-def: $vgpr14_vgpr15 .LBB1_18: ; %Flow367 s_or_saveexec_b32 s5, s5 v_dual_mov_b32 v13, s3 :: v_dual_mov_b32 v12, s2 v_dual_mov_b32 v17, s1 :: v_dual_mov_b32 v16, s0 v_dual_mov_b32 v24, v65 :: v_dual_mov_b32 v25, v66 v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6 s_xor_b32 exec_lo, exec_lo, s5 s_cbranch_execz .LBB1_20 ; %bb.19: v_xor_b32_e32 v15, 0x80000000, v15 s_xor_b32 s1, s71, 0x80000000 s_mov_b32 s0, s70 s_waitcnt vmcnt(0) v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v11, s1 v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v17, v15 v_dual_mov_b32 v13, -2.0 :: v_dual_mov_b32 v10, s0 v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v16, v14 v_dual_mov_b32 v22, v65 :: v_dual_mov_b32 v23, v66 v_dual_mov_b32 v19, v7 :: v_dual_mov_b32 v18, v6 .LBB1_20: ; %_Z14select_stencilRdS_S_S_S_S_S_S_S_S_S_S_S_S_dddddddddddddddd.exit.i.i293 s_or_b32 exec_lo, exec_lo, s5 s_waitcnt vmcnt(1) v_add_f64 v[4:5], v[4:5], -v[26:27] v_add_f64 v[6:7], v[8:9], -v[0:1] v_add_f64 v[18:19], v[22:23], -v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[14:15], null, v[6:7], v[6:7], v[4:5] v_rcp_f64_e32 v[28:29], v[14:15] s_waitcnt_depctr 0xfff v_fma_f64 v[30:31], -v[14:15], v[28:29], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] v_fma_f64 v[30:31], -v[14:15], v[28:29], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] v_div_scale_f64 v[30:31], vcc_lo, v[4:5], v[6:7], v[4:5] v_mul_f64 v[32:33], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], -v[14:15], v[32:33], v[30:31] v_div_fmas_f64 v[14:15], v[14:15], v[28:29], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_div_fixup_f64 v[28:29], v[14:15], v[6:7], v[4:5] v_add_f64 v[4:5], v[26:27], -v[20:21] v_add_f64 v[6:7], v[0:1], -v[2:3] v_div_scale_f64 v[14:15], null, v[6:7], v[6:7], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[26:27], v[14:15] s_waitcnt_depctr 0xfff v_fma_f64 v[30:31], -v[14:15], v[26:27], 1.0 v_fma_f64 v[26:27], v[26:27], v[30:31], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], -v[14:15], v[26:27], 1.0 v_fma_f64 v[26:27], v[26:27], v[30:31], v[26:27] v_div_scale_f64 v[30:31], vcc_lo, v[4:5], v[6:7], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[32:33], v[30:31], v[26:27] v_fma_f64 v[14:15], -v[14:15], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[32:33] v_div_fixup_f64 v[26:27], v[14:15], v[6:7], v[4:5] v_add_f64 v[4:5], v[20:21], -v[58:59] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], v[4:5] v_rcp_f64_e32 v[14:15], v[6:7] s_waitcnt_depctr 0xfff v_fma_f64 v[20:21], -v[6:7], v[14:15], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15] v_fma_f64 v[20:21], -v[6:7], v[14:15], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15] v_div_scale_f64 v[20:21], vcc_lo, v[4:5], v[2:3], v[4:5] v_mul_f64 v[30:31], v[20:21], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], -v[6:7], v[30:31], v[20:21] v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[30:31] v_add_f64 v[14:15], v[58:59], -v[24:25] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[4:5], v[6:7], v[2:3], v[4:5] v_add_f64 v[6:7], -v[16:17], 0 v_div_scale_f64 v[20:21], null, v[6:7], v[6:7], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[30:31], v[20:21] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[20:21], v[30:31], 1.0 v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], -v[20:21], v[30:31], 1.0 v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[14:15], v[6:7], v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[34:35], v[32:33], v[30:31] v_fma_f64 v[20:21], -v[20:21], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[20:21], v[20:21], v[30:31], v[34:35] v_div_fixup_f64 v[14:15], v[20:21], v[6:7], v[14:15] v_add_f64 v[20:21], v[24:25], -v[22:23] s_waitcnt vmcnt(0) v_add_f64 v[24:25], v[16:17], -v[10:11] v_fma_f64 v[22:23], -v[12:13], s[70:71], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[30:31], null, v[24:25], v[24:25], v[20:21] v_rcp_f64_e32 v[32:33], v[30:31] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[20:21], v[24:25], v[20:21] v_mul_f64 v[36:37], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], -v[30:31], v[36:37], v[34:35] v_div_fmas_f64 v[30:31], v[30:31], v[32:33], v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[20:21], v[30:31], v[24:25], v[20:21] v_div_scale_f64 v[24:25], null, v[22:23], v[22:23], v[18:19] v_rcp_f64_e32 v[30:31], v[24:25] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[24:25], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_fma_f64 v[32:33], -v[24:25], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[18:19], v[22:23], v[18:19] v_mul_f64 v[34:35], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], -v[24:25], v[34:35], v[32:33] v_div_fmas_f64 v[24:25], v[24:25], v[30:31], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_div_fixup_f64 v[18:19], v[24:25], v[22:23], v[18:19] v_add_f64 v[22:23], v[28:29], -v[26:27] v_add_f64 v[24:25], v[8:9], -v[2:3] v_add_f64 v[18:19], v[20:21], -v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[28:29], null, v[24:25], v[24:25], v[22:23] v_rcp_f64_e32 v[30:31], v[28:29] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[22:23], v[24:25], v[22:23] v_mul_f64 v[34:35], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], -v[28:29], v[34:35], v[32:33] v_div_fmas_f64 v[28:29], v[28:29], v[30:31], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[22:23], v[28:29], v[24:25], v[22:23] v_add_f64 v[24:25], v[26:27], -v[4:5] v_div_scale_f64 v[26:27], null, v[0:1], v[0:1], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[28:29], v[26:27] s_waitcnt_depctr 0xfff v_fma_f64 v[30:31], -v[26:27], v[28:29], 1.0 v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], -v[26:27], v[28:29], 1.0 v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] v_div_scale_f64 v[30:31], vcc_lo, v[24:25], v[0:1], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[32:33], v[30:31], v[28:29] v_fma_f64 v[26:27], -v[26:27], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fmas_f64 v[26:27], v[26:27], v[28:29], v[32:33] v_add_f64 v[28:29], v[2:3], -v[16:17] v_div_fixup_f64 v[24:25], v[26:27], v[0:1], v[24:25] v_add_f64 v[26:27], v[4:5], -v[14:15] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[30:31], null, v[28:29], v[28:29], v[26:27] v_rcp_f64_e32 v[32:33], v[30:31] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[26:27], v[28:29], v[26:27] v_mul_f64 v[36:37], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], -v[30:31], v[36:37], v[34:35] v_div_fmas_f64 v[30:31], v[30:31], v[32:33], v[36:37] s_delay_alu instid0(VALU_DEP_1) v_div_fixup_f64 v[26:27], v[30:31], v[28:29], v[26:27] v_add_f64 v[28:29], v[14:15], -v[20:21] v_add_f64 v[30:31], -v[10:11], 0 v_fma_f64 v[20:21], -v[12:13], s[70:71], v[16:17] v_add_f64 v[16:17], v[0:1], -v[16:17] v_add_f64 v[10:11], v[2:3], -v[10:11] v_fma_f64 v[12:13], -v[12:13], s[70:71], 0 v_add_f64 v[2:3], -v[2:3], 0 v_add_f64 v[0:1], -v[0:1], 0 v_div_scale_f64 v[32:33], null, v[30:31], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[0:1], v[2:3], v[0:1] v_rcp_f64_e32 v[34:35], v[32:33] s_waitcnt_depctr 0xfff v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35] v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35] v_div_scale_f64 v[36:37], vcc_lo, v[28:29], v[30:31], v[28:29] v_mul_f64 v[38:39], v[36:37], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], -v[32:33], v[38:39], v[36:37] v_div_fmas_f64 v[32:33], v[32:33], v[34:35], v[38:39] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[28:29], v[32:33], v[30:31], v[28:29] v_div_scale_f64 v[32:33], null, v[20:21], v[20:21], v[18:19] v_rcp_f64_e32 v[34:35], v[32:33] s_waitcnt_depctr 0xfff v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35] v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35] v_div_scale_f64 v[36:37], vcc_lo, v[18:19], v[20:21], v[18:19] v_mul_f64 v[38:39], v[36:37], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], -v[32:33], v[38:39], v[36:37] v_div_fmas_f64 v[32:33], v[32:33], v[34:35], v[38:39] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[18:19], v[32:33], v[20:21], v[18:19] v_add_f64 v[20:21], v[22:23], -v[24:25] v_add_f64 v[18:19], v[28:29], -v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[22:23], null, v[8:9], v[8:9], v[20:21] v_rcp_f64_e32 v[32:33], v[22:23] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[22:23], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_fma_f64 v[34:35], -v[22:23], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[20:21], v[8:9], v[20:21] v_mul_f64 v[36:37], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], -v[22:23], v[36:37], v[34:35] v_div_fmas_f64 v[22:23], v[22:23], v[32:33], v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[8:9], v[22:23], v[8:9], v[20:21] v_add_f64 v[20:21], v[24:25], -v[26:27] v_div_scale_f64 v[22:23], null, v[16:17], v[16:17], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[32:33], v[22:23] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[22:23], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], -v[22:23], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[20:21], v[16:17], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[36:37], v[34:35], v[32:33] v_fma_f64 v[22:23], -v[22:23], v[36:37], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[22:23], v[22:23], v[32:33], v[36:37] v_div_fixup_f64 v[16:17], v[22:23], v[16:17], v[20:21] v_add_f64 v[20:21], v[26:27], -v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_lt_f64_e64 s0, |v[16:17]|, |v[8:9]| v_div_scale_f64 v[22:23], null, v[10:11], v[10:11], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v9, v9, v17, s0 v_rcp_f64_e32 v[32:33], v[22:23] v_cndmask_b32_e64 v8, v8, v16, s0 v_cmp_lt_f64_e64 s0, |v[26:27]|, |v[24:25]| s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_mul_f64 v[0:1], v[0:1], v[8:9] v_mul_f64 v[8:9], v[26:27], v[28:29] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[22:23], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], -v[22:23], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[20:21], v[10:11], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[36:37], v[34:35], v[32:33] v_fma_f64 v[22:23], -v[22:23], v[36:37], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[22:23], v[22:23], v[32:33], v[36:37] v_div_fixup_f64 v[10:11], v[22:23], v[10:11], v[20:21] v_div_scale_f64 v[20:21], null, v[12:13], v[12:13], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[22:23], v[20:21] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[20:21], v[22:23], 1.0 v_fma_f64 v[22:23], v[22:23], v[32:33], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], -v[20:21], v[22:23], 1.0 v_fma_f64 v[22:23], v[22:23], v[32:33], v[22:23] v_div_scale_f64 v[32:33], vcc_lo, v[18:19], v[12:13], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[34:35], v[32:33], v[22:23] v_fma_f64 v[20:21], -v[20:21], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[20:21], v[20:21], v[22:23], v[34:35] v_div_fixup_f64 v[12:13], v[20:21], v[12:13], v[18:19] v_mul_f64 v[18:19], v[6:7], v[30:31] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cmp_lt_f64_e64 vcc_lo, |v[10:11]|, |v[12:13]| v_dual_cndmask_b32 v13, v13, v11 :: v_dual_cndmask_b32 v12, v12, v10 v_cmp_lt_f64_e64 vcc_lo, |v[10:11]|, |v[16:17]| v_mul_f64 v[12:13], v[18:19], v[12:13] v_mul_f64 v[18:19], v[2:3], v[6:7] v_dual_cndmask_b32 v11, v17, v11 :: v_dual_cndmask_b32 v10, v16, v10 v_cmp_lt_f64_e64 vcc_lo, |v[28:29]|, |v[26:27]| s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[10:11], v[18:19], v[10:11] v_dual_cndmask_b32 v13, v11, v13 :: v_dual_cndmask_b32 v12, v10, v12 v_cndmask_b32_e64 v1, v1, v11, s0 v_cndmask_b32_e64 v0, v0, v10, s0 v_dual_cndmask_b32 v10, v26, v28 :: v_dual_cndmask_b32 v11, v27, v29 v_cmp_ngt_f64_e32 vcc_lo, 0, v[8:9] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v9, 0, v11 :: v_dual_cndmask_b32 v8, 0, v10 v_fma_f64 v[6:7], v[6:7], v[8:9], v[14:15] v_cndmask_b32_e64 v8, v24, v26, s0 v_cndmask_b32_e64 v9, v25, v27, s0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_f64 v[41:42], v[6:7], v[12:13] v_mul_f64 v[6:7], v[24:25], v[26:27] v_cmp_ngt_f64_e32 vcc_lo, 0, v[6:7] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v7, 0, v9 :: v_dual_cndmask_b32 v6, 0, v8 v_fma_f64 v[2:3], v[2:3], v[6:7], v[4:5] s_delay_alu instid0(VALU_DEP_1) v_add_f64 v[0:1], v[2:3], v[0:1] .LBB1_21: ; %Flow371 s_or_b32 exec_lo, exec_lo, s4 v_add_nc_u32_e32 v2, 1, v60 s_waitcnt vmcnt(1) v_add_nc_u32_e32 v4, 2, v60 v_add_nc_u32_e32 v6, 3, v60 v_add_nc_u32_e32 v8, -1, v60 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v10, -3, v60 v_cvt_f64_i32_e32 v[2:3], v2 v_cvt_f64_i32_e32 v[4:5], v4 v_cvt_f64_i32_e32 v[6:7], v6 v_add_nc_u32_e32 v12, -2, v60 v_cvt_f64_i32_e32 v[8:9], v8 v_cvt_f64_i32_e32 v[10:11], v10 v_cmp_lt_f64_e64 s5, |v[67:68]|, |v[65:66]| s_load_b64 s[6:7], s[62:63], 0x8 v_cvt_f64_i32_e32 v[12:13], v12 v_max_f64 v[2:3], v[2:3], 0 v_max_f64 v[4:5], v[4:5], 0 v_max_f64 v[6:7], v[6:7], 0 v_max_f64 v[8:9], v[8:9], 0 v_max_f64 v[10:11], v[10:11], 0 v_cndmask_b32_e64 v1, v42, v1, s5 v_cndmask_b32_e64 v0, v41, v0, s5 v_max_f64 v[12:13], v[12:13], 0 ; implicit-def: $vgpr41_vgpr42 v_cmp_gt_f64_e32 vcc_lo, v[2:3], v[63:64] v_cmp_gt_f64_e64 s0, v[4:5], v[63:64] v_cmp_gt_f64_e64 s1, v[6:7], v[63:64] v_cmp_gt_f64_e64 s2, v[8:9], v[63:64] v_cmp_gt_f64_e64 s3, v[10:11], v[63:64] v_cmp_gt_f64_e64 s4, v[12:13], v[63:64] v_dual_cndmask_b32 v3, v3, v64 :: v_dual_cndmask_b32 v2, v2, v63 v_cndmask_b32_e64 v5, v5, v64, s0 v_cndmask_b32_e64 v4, v4, v63, s0 v_cndmask_b32_e64 v7, v7, v64, s1 v_cndmask_b32_e64 v6, v6, v63, s1 v_cndmask_b32_e64 v9, v9, v64, s2 v_cndmask_b32_e64 v8, v8, v63, s2 v_cndmask_b32_e64 v11, v11, v64, s3 v_cndmask_b32_e64 v10, v10, v63, s3 v_cvt_i32_f64_e32 v14, v[2:3] v_cvt_i32_f64_e32 v15, v[4:5] v_cndmask_b32_e64 v13, v13, v64, s4 v_cvt_i32_f64_e32 v16, v[6:7] v_cndmask_b32_e64 v12, v12, v63, s4 v_cvt_i32_f64_e32 v17, v[8:9] v_cvt_i32_f64_e32 v10, v[10:11] s_load_b128 s[0:3], s[62:63], 0x40 v_lshlrev_b64 v[2:3], 3, v[56:57] v_cvt_i32_f64_e32 v12, v[12:13] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, s6, v2 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo global_store_b64 v[4:5], v[0:1], off v_add_co_u32 v6, vcc_lo, s0, v2 v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo v_add_co_u32 v8, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v9, vcc_lo, s3, v3, vcc_lo v_mad_u64_u32 v[0:1], null, v14, s67, v[61:62] v_mad_u64_u32 v[1:2], null, v15, s67, v[61:62] v_mad_u64_u32 v[2:3], null, v16, s67, v[61:62] v_mad_u64_u32 v[3:4], null, v17, s67, v[61:62] v_mad_u64_u32 v[4:5], null, v10, s67, v[61:62] v_mad_u64_u32 v[10:11], null, v12, s67, v[61:62] v_mad_u64_u32 v[11:12], null, v0, s66, v[62:63] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_mad_u64_u32 v[13:14], null, v3, s66, v[62:63] v_mad_u64_u32 v[15:16], null, v4, s66, v[62:63] v_mad_u64_u32 v[20:21], null, v1, s66, v[62:63] v_mad_u64_u32 v[0:1], null, v2, s66, v[62:63] global_load_b64 v[2:3], v[6:7], off global_load_b64 v[18:19], v[8:9], off v_mad_u64_u32 v[4:5], null, v10, s66, v[62:63] v_ashrrev_i32_e32 v16, 31, v15 v_ashrrev_i32_e32 v14, 31, v13 v_ashrrev_i32_e32 v12, 31, v11 v_ashrrev_i32_e32 v21, 31, v20 v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[6:7], 3, v[15:16] v_ashrrev_i32_e32 v5, 31, v4 v_lshlrev_b64 v[8:9], 3, v[13:14] v_lshlrev_b64 v[10:11], 3, v[11:12] v_lshlrev_b64 v[12:13], 3, v[20:21] v_lshlrev_b64 v[0:1], 3, v[0:1] v_lshlrev_b64 v[4:5], 3, v[4:5] v_add_co_u32 v6, vcc_lo, s68, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s69, v7, vcc_lo s_load_b64 s[66:67], s[62:63], 0x70 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v4, vcc_lo, s68, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s69, v5, vcc_lo v_add_co_u32 v8, vcc_lo, s68, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s69, v9, vcc_lo v_add_co_u32 v10, vcc_lo, s68, v10 v_add_co_ci_u32_e32 v11, vcc_lo, s69, v11, vcc_lo v_add_co_u32 v12, vcc_lo, s68, v12 v_add_co_ci_u32_e32 v13, vcc_lo, s69, v13, vcc_lo v_add_co_u32 v0, vcc_lo, s68, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s69, v1, vcc_lo s_clause 0x5 global_load_b64 v[14:15], v[6:7], off global_load_b64 v[16:17], v[4:5], off global_load_b64 v[60:61], v[8:9], off global_load_b64 v[62:63], v[10:11], off global_load_b64 v[6:7], v[12:13], off global_load_b64 v[8:9], v[0:1], off ; implicit-def: $vgpr0_vgpr1 s_waitcnt vmcnt(7) lgkmcnt(0) v_cmp_ngt_f64_e64 s64, s[66:67], v[2:3] s_waitcnt vmcnt(6) v_cmp_ngt_f64_e64 s33, s[66:67], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s0, s64, s33 s_and_saveexec_b32 s1, s0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s65, exec_lo, s1 s_cbranch_execz .LBB1_23 ; %bb.22: s_waitcnt vmcnt(4) v_add_f64 v[0:1], v[16:17], -v[14:15] s_waitcnt vmcnt(3) v_add_f64 v[2:3], v[60:61], -v[16:17] v_add_f64 v[4:5], v[58:59], -v[60:61] s_waitcnt vmcnt(2) v_add_f64 v[10:11], v[62:63], -v[58:59] s_waitcnt vmcnt(1) v_add_f64 v[12:13], v[6:7], -v[62:63] s_waitcnt vmcnt(0) v_add_f64 v[6:7], v[8:9], -v[6:7] s_getpc_b64 s[68:69] s_add_u32 s68, s68, _Z24weno_onesided_derivativeddddd@rel32@lo+4 s_addc_u32 s69, s69, _Z24weno_onesided_derivativeddddd@rel32@hi+12 v_div_scale_f64 v[8:9], null, s[66:67], s[66:67], v[0:1] v_div_scale_f64 v[14:15], null, s[66:67], s[66:67], v[2:3] v_div_scale_f64 v[16:17], null, s[66:67], s[66:67], v[4:5] v_div_scale_f64 v[18:19], null, s[66:67], s[66:67], v[10:11] v_div_scale_f64 v[20:21], null, s[66:67], s[66:67], v[12:13] v_div_scale_f64 v[22:23], null, s[66:67], s[66:67], v[6:7] v_div_scale_f64 v[48:49], vcc_lo, v[0:1], s[66:67], v[0:1] v_rcp_f64_e32 v[24:25], v[8:9] v_rcp_f64_e32 v[26:27], v[14:15] v_rcp_f64_e32 v[28:29], v[16:17] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_rcp_f64_e32 v[30:31], v[18:19] v_rcp_f64_e32 v[32:33], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3) v_rcp_f64_e32 v[34:35], v[22:23] v_fma_f64 v[36:37], -v[8:9], v[24:25], 1.0 v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0 v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0 v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0 v_fma_f64 v[46:47], -v[22:23], v[34:35], 1.0 v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25] v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27] v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29] v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31] v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33] v_fma_f64 v[34:35], v[34:35], v[46:47], v[34:35] v_fma_f64 v[36:37], -v[8:9], v[24:25], 1.0 v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0 v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0 v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0 v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0 v_fma_f64 v[46:47], -v[22:23], v[34:35], 1.0 v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25] v_div_scale_f64 v[36:37], s0, v[2:3], s[66:67], v[2:3] v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27] v_div_scale_f64 v[38:39], s1, v[4:5], s[66:67], v[4:5] v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29] v_div_scale_f64 v[40:41], s2, v[10:11], s[66:67], v[10:11] v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31] v_div_scale_f64 v[42:43], s3, v[12:13], s[66:67], v[12:13] v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33] v_fma_f64 v[34:35], v[34:35], v[46:47], v[34:35] v_div_scale_f64 v[44:45], s4, v[6:7], s[66:67], v[6:7] v_mul_f64 v[46:47], v[48:49], v[24:25] v_mul_f64 v[50:51], v[36:37], v[26:27] v_mul_f64 v[52:53], v[38:39], v[28:29] v_mul_f64 v[54:55], v[40:41], v[30:31] v_mul_f64 v[58:59], v[42:43], v[32:33] v_mul_f64 v[64:65], v[44:45], v[34:35] v_fma_f64 v[8:9], -v[8:9], v[46:47], v[48:49] v_fma_f64 v[14:15], -v[14:15], v[50:51], v[36:37] v_fma_f64 v[16:17], -v[16:17], v[52:53], v[38:39] v_fma_f64 v[18:19], -v[18:19], v[54:55], v[40:41] v_fma_f64 v[20:21], -v[20:21], v[58:59], v[42:43] v_fma_f64 v[22:23], -v[22:23], v[64:65], v[44:45] v_div_fmas_f64 v[8:9], v[8:9], v[24:25], v[46:47] s_mov_b32 vcc_lo, s0 v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[50:51] s_mov_b32 vcc_lo, s1 v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[52:53] s_mov_b32 vcc_lo, s2 v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[54:55] s_mov_b32 vcc_lo, s3 v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[58:59] s_mov_b32 vcc_lo, s4 v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[64:65] v_div_fixup_f64 v[0:1], v[8:9], s[66:67], v[0:1] v_div_fixup_f64 v[43:44], v[14:15], s[66:67], v[2:3] v_div_fixup_f64 v[45:46], v[16:17], s[66:67], v[4:5] v_div_fixup_f64 v[50:51], v[18:19], s[66:67], v[10:11] v_div_fixup_f64 v[52:53], v[20:21], s[66:67], v[12:13] v_div_fixup_f64 v[54:55], v[22:23], s[66:67], v[6:7] v_dual_mov_b32 v2, v43 :: v_dual_mov_b32 v3, v44 v_dual_mov_b32 v4, v45 :: v_dual_mov_b32 v5, v46 v_dual_mov_b32 v6, v50 :: v_dual_mov_b32 v7, v51 v_dual_mov_b32 v8, v52 :: v_dual_mov_b32 v9, v53 s_swappc_b64 s[30:31], s[68:69] v_dual_mov_b32 v41, v0 :: v_dual_mov_b32 v42, v1 v_dual_mov_b32 v0, v54 :: v_dual_mov_b32 v1, v55 v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v3, v53 v_dual_mov_b32 v4, v50 :: v_dual_mov_b32 v5, v51 v_dual_mov_b32 v6, v45 :: v_dual_mov_b32 v7, v46 v_dual_mov_b32 v8, v43 :: v_dual_mov_b32 v9, v44 s_swappc_b64 s[30:31], s[68:69] ; implicit-def: $vgpr16_vgpr17 ; implicit-def: $vgpr58_vgpr59 ; implicit-def: $vgpr14_vgpr15 ; implicit-def: $vgpr18_vgpr19 ; implicit-def: $vgpr2_vgpr3 ; implicit-def: $vgpr6_vgpr7 ; implicit-def: $vgpr8_vgpr9 .LBB1_23: ; %Flow364 s_and_not1_saveexec_b32 s5, s65 s_cbranch_execz .LBB1_31 ; %bb.24: v_add_f64 v[4:5], s[66:67], s[66:67] v_mov_b32_e32 v20, 0 s_waitcnt vmcnt(2) v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v22, v62 v_dual_mov_b32 v0, s66 :: v_dual_mov_b32 v1, s67 v_mov_b32_e32 v23, v63 s_and_saveexec_b32 s0, s64 s_cbranch_execz .LBB1_26 ; %bb.25: v_mul_f64 v[10:11], s[66:67], 0x40080000 v_dual_mov_b32 v2, s66 :: v_dual_mov_b32 v3, s67 v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5 v_dual_mov_b32 v20, v62 :: v_dual_mov_b32 v21, v63 s_waitcnt vmcnt(1) v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6 s_waitcnt vmcnt(0) v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9 v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11 .LBB1_26: s_or_b32 exec_lo, exec_lo, s0 ; implicit-def: $vgpr8_vgpr9 ; implicit-def: $sgpr0_sgpr1 ; implicit-def: $sgpr2_sgpr3 s_and_saveexec_b32 s4, s33 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s4, exec_lo, s4 s_cbranch_execz .LBB1_28 ; %bb.27: s_mov_b32 s2, 0 s_waitcnt vmcnt(0) v_mul_f64 v[8:9], s[66:67], -2.0 s_mov_b32 s3, 0xc0080000 s_xor_b32 s1, s67, 0x80000000 s_mov_b32 s0, s66 ; implicit-def: $vgpr18_vgpr19 .LBB1_28: ; %Flow s_or_saveexec_b32 s4, s4 v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2 v_dual_mov_b32 v13, s1 :: v_dual_mov_b32 v12, s0 v_dual_mov_b32 v26, v60 :: v_dual_mov_b32 v27, v61 v_dual_mov_b32 v25, v17 :: v_dual_mov_b32 v24, v16 s_xor_b32 exec_lo, exec_lo, s4 s_cbranch_execz .LBB1_30 ; %bb.29: v_xor_b32_e32 v19, 0x80000000, v19 s_xor_b32 s1, s67, 0x80000000 s_mov_b32 s0, s66 v_mov_b32_e32 v26, 0 s_waitcnt vmcnt(0) v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, s1 v_dual_mov_b32 v27, 0 :: v_dual_mov_b32 v12, v18 v_dual_mov_b32 v11, -2.0 :: v_dual_mov_b32 v8, s0 v_dual_mov_b32 v13, v19 :: v_dual_mov_b32 v24, v60 v_dual_mov_b32 v25, v61 :: v_dual_mov_b32 v14, v16 v_mov_b32_e32 v15, v17 .LBB1_30: ; %_Z14select_stencilRdS_S_S_S_S_S_S_S_S_S_S_S_S_dddddddddddddddd.exit.i.i321 s_or_b32 exec_lo, exec_lo, s4 s_waitcnt vmcnt(1) v_add_f64 v[16:17], v[6:7], -v[22:23] v_add_f64 v[18:19], v[4:5], -v[0:1] v_add_f64 v[22:23], v[22:23], -v[20:21] v_add_f64 v[28:29], v[0:1], -v[2:3] v_add_f64 v[20:21], v[20:21], -v[58:59] v_add_f64 v[30:31], v[58:59], -v[26:27] v_add_f64 v[6:7], -v[12:13], 0 v_add_f64 v[26:27], v[26:27], -v[24:25] s_waitcnt vmcnt(0) v_add_f64 v[32:33], v[12:13], -v[8:9] v_add_f64 v[14:15], v[24:25], -v[14:15] v_fma_f64 v[24:25], -v[10:11], s[66:67], v[8:9] v_div_scale_f64 v[34:35], null, v[18:19], v[18:19], v[16:17] v_div_scale_f64 v[36:37], null, v[28:29], v[28:29], v[22:23] v_div_scale_f64 v[38:39], null, v[2:3], v[2:3], v[20:21] v_div_scale_f64 v[40:41], null, v[6:7], v[6:7], v[30:31] v_div_scale_f64 v[42:43], null, v[32:33], v[32:33], v[26:27] v_div_scale_f64 v[44:45], null, v[24:25], v[24:25], v[14:15] v_div_scale_f64 v[76:77], vcc_lo, v[16:17], v[18:19], v[16:17] v_rcp_f64_e32 v[46:47], v[34:35] v_rcp_f64_e32 v[48:49], v[36:37] v_rcp_f64_e32 v[50:51], v[38:39] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_rcp_f64_e32 v[52:53], v[40:41] v_rcp_f64_e32 v[54:55], v[42:43] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3) v_rcp_f64_e32 v[58:59], v[44:45] v_fma_f64 v[64:65], -v[34:35], v[46:47], 1.0 v_fma_f64 v[66:67], -v[36:37], v[48:49], 1.0 v_fma_f64 v[68:69], -v[38:39], v[50:51], 1.0 v_fma_f64 v[70:71], -v[40:41], v[52:53], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[72:73], -v[42:43], v[54:55], 1.0 v_fma_f64 v[74:75], -v[44:45], v[58:59], 1.0 v_fma_f64 v[46:47], v[46:47], v[64:65], v[46:47] v_fma_f64 v[48:49], v[48:49], v[66:67], v[48:49] v_fma_f64 v[50:51], v[50:51], v[68:69], v[50:51] v_fma_f64 v[52:53], v[52:53], v[70:71], v[52:53] v_fma_f64 v[54:55], v[54:55], v[72:73], v[54:55] v_fma_f64 v[58:59], v[58:59], v[74:75], v[58:59] v_fma_f64 v[64:65], -v[34:35], v[46:47], 1.0 v_fma_f64 v[66:67], -v[36:37], v[48:49], 1.0 v_fma_f64 v[68:69], -v[38:39], v[50:51], 1.0 v_fma_f64 v[70:71], -v[40:41], v[52:53], 1.0 v_fma_f64 v[72:73], -v[42:43], v[54:55], 1.0 v_fma_f64 v[74:75], -v[44:45], v[58:59], 1.0 v_fma_f64 v[46:47], v[46:47], v[64:65], v[46:47] v_div_scale_f64 v[64:65], s0, v[22:23], v[28:29], v[22:23] v_fma_f64 v[48:49], v[48:49], v[66:67], v[48:49] v_div_scale_f64 v[66:67], s1, v[20:21], v[2:3], v[20:21] v_fma_f64 v[50:51], v[50:51], v[68:69], v[50:51] v_div_scale_f64 v[68:69], s2, v[30:31], v[6:7], v[30:31] v_fma_f64 v[52:53], v[52:53], v[70:71], v[52:53] v_div_scale_f64 v[70:71], s3, v[26:27], v[32:33], v[26:27] v_fma_f64 v[54:55], v[54:55], v[72:73], v[54:55] v_div_scale_f64 v[72:73], s4, v[14:15], v[24:25], v[14:15] v_fma_f64 v[58:59], v[58:59], v[74:75], v[58:59] v_mul_f64 v[74:75], v[76:77], v[46:47] v_mul_f64 v[78:79], v[64:65], v[48:49] v_mul_f64 v[80:81], v[66:67], v[50:51] v_mul_f64 v[82:83], v[68:69], v[52:53] v_mul_f64 v[84:85], v[70:71], v[54:55] v_mul_f64 v[86:87], v[72:73], v[58:59] v_fma_f64 v[34:35], -v[34:35], v[74:75], v[76:77] v_fma_f64 v[36:37], -v[36:37], v[78:79], v[64:65] v_fma_f64 v[38:39], -v[38:39], v[80:81], v[66:67] v_fma_f64 v[40:41], -v[40:41], v[82:83], v[68:69] v_fma_f64 v[42:43], -v[42:43], v[84:85], v[70:71] v_fma_f64 v[44:45], -v[44:45], v[86:87], v[72:73] v_div_fmas_f64 v[34:35], v[34:35], v[46:47], v[74:75] s_mov_b32 vcc_lo, s0 v_div_fmas_f64 v[36:37], v[36:37], v[48:49], v[78:79] s_mov_b32 vcc_lo, s1 v_div_fmas_f64 v[38:39], v[38:39], v[50:51], v[80:81] s_mov_b32 vcc_lo, s2 v_div_fmas_f64 v[40:41], v[40:41], v[52:53], v[82:83] s_mov_b32 vcc_lo, s3 v_div_fmas_f64 v[42:43], v[42:43], v[54:55], v[84:85] s_mov_b32 vcc_lo, s4 v_div_fmas_f64 v[44:45], v[44:45], v[58:59], v[86:87] v_div_fixup_f64 v[16:17], v[34:35], v[18:19], v[16:17] v_div_fixup_f64 v[18:19], v[36:37], v[28:29], v[22:23] v_add_f64 v[28:29], v[2:3], -v[12:13] v_fma_f64 v[36:37], -v[10:11], s[66:67], v[12:13] v_div_fixup_f64 v[20:21], v[38:39], v[2:3], v[20:21] v_add_f64 v[12:13], v[0:1], -v[12:13] v_fma_f64 v[10:11], -v[10:11], s[66:67], 0 v_div_fixup_f64 v[22:23], v[40:41], v[6:7], v[30:31] v_div_fixup_f64 v[26:27], v[42:43], v[32:33], v[26:27] v_add_f64 v[32:33], -v[8:9], 0 v_add_f64 v[8:9], v[2:3], -v[8:9] v_div_fixup_f64 v[14:15], v[44:45], v[24:25], v[14:15] v_add_f64 v[24:25], v[4:5], -v[2:3] v_add_f64 v[2:3], -v[2:3], 0 v_add_f64 v[16:17], v[16:17], -v[18:19] v_add_f64 v[18:19], v[18:19], -v[20:21] v_add_f64 v[30:31], v[20:21], -v[22:23] v_add_f64 v[34:35], v[22:23], -v[26:27] v_add_f64 v[14:15], v[26:27], -v[14:15] v_div_scale_f64 v[26:27], null, v[24:25], v[24:25], v[16:17] v_div_scale_f64 v[72:73], vcc_lo, v[16:17], v[24:25], v[16:17] v_div_scale_f64 v[38:39], null, v[0:1], v[0:1], v[18:19] v_div_scale_f64 v[40:41], null, v[28:29], v[28:29], v[30:31] v_div_scale_f64 v[42:43], null, v[32:33], v[32:33], v[34:35] v_div_scale_f64 v[44:45], null, v[36:37], v[36:37], v[14:15] v_rcp_f64_e32 v[46:47], v[26:27] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_rcp_f64_e32 v[48:49], v[38:39] v_rcp_f64_e32 v[50:51], v[40:41] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[52:53], v[42:43] v_rcp_f64_e32 v[54:55], v[44:45] v_fma_f64 v[58:59], -v[26:27], v[46:47], 1.0 v_fma_f64 v[64:65], -v[38:39], v[48:49], 1.0 s_delay_alu instid0(TRANS32_DEP_3) v_fma_f64 v[66:67], -v[40:41], v[50:51], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[68:69], -v[42:43], v[52:53], 1.0 v_fma_f64 v[70:71], -v[44:45], v[54:55], 1.0 v_fma_f64 v[46:47], v[46:47], v[58:59], v[46:47] v_fma_f64 v[48:49], v[48:49], v[64:65], v[48:49] v_fma_f64 v[50:51], v[50:51], v[66:67], v[50:51] v_fma_f64 v[52:53], v[52:53], v[68:69], v[52:53] v_fma_f64 v[54:55], v[54:55], v[70:71], v[54:55] v_fma_f64 v[58:59], -v[26:27], v[46:47], 1.0 v_fma_f64 v[64:65], -v[38:39], v[48:49], 1.0 v_fma_f64 v[66:67], -v[40:41], v[50:51], 1.0 v_fma_f64 v[68:69], -v[42:43], v[52:53], 1.0 v_fma_f64 v[70:71], -v[44:45], v[54:55], 1.0 v_fma_f64 v[46:47], v[46:47], v[58:59], v[46:47] v_div_scale_f64 v[58:59], s0, v[18:19], v[0:1], v[18:19] v_fma_f64 v[48:49], v[48:49], v[64:65], v[48:49] v_div_scale_f64 v[64:65], s1, v[30:31], v[28:29], v[30:31] v_fma_f64 v[50:51], v[50:51], v[66:67], v[50:51] v_div_scale_f64 v[66:67], s2, v[34:35], v[32:33], v[34:35] v_fma_f64 v[52:53], v[52:53], v[68:69], v[52:53] v_div_scale_f64 v[68:69], s3, v[14:15], v[36:37], v[14:15] v_fma_f64 v[54:55], v[54:55], v[70:71], v[54:55] v_mul_f64 v[70:71], v[72:73], v[46:47] v_mul_f64 v[74:75], v[58:59], v[48:49] v_mul_f64 v[76:77], v[64:65], v[50:51] v_mul_f64 v[78:79], v[66:67], v[52:53] v_mul_f64 v[80:81], v[68:69], v[54:55] v_fma_f64 v[26:27], -v[26:27], v[70:71], v[72:73] v_fma_f64 v[38:39], -v[38:39], v[74:75], v[58:59] v_fma_f64 v[40:41], -v[40:41], v[76:77], v[64:65] v_fma_f64 v[42:43], -v[42:43], v[78:79], v[66:67] v_fma_f64 v[44:45], -v[44:45], v[80:81], v[68:69] v_div_fmas_f64 v[26:27], v[26:27], v[46:47], v[70:71] s_mov_b32 vcc_lo, s0 v_div_fmas_f64 v[38:39], v[38:39], v[48:49], v[74:75] s_mov_b32 vcc_lo, s1 v_div_fmas_f64 v[40:41], v[40:41], v[50:51], v[76:77] s_mov_b32 vcc_lo, s2 v_div_fmas_f64 v[42:43], v[42:43], v[52:53], v[78:79] s_mov_b32 vcc_lo, s3 v_div_fmas_f64 v[44:45], v[44:45], v[54:55], v[80:81] v_div_fixup_f64 v[16:17], v[26:27], v[24:25], v[16:17] v_div_fixup_f64 v[18:19], v[38:39], v[0:1], v[18:19] v_add_f64 v[0:1], -v[0:1], 0 v_div_fixup_f64 v[24:25], v[40:41], v[28:29], v[30:31] v_div_fixup_f64 v[26:27], v[42:43], v[32:33], v[34:35] v_div_fixup_f64 v[14:15], v[44:45], v[36:37], v[14:15] v_add_f64 v[16:17], v[16:17], -v[18:19] v_mul_f64 v[0:1], v[2:3], v[0:1] v_add_f64 v[28:29], v[18:19], -v[24:25] v_add_f64 v[30:31], v[24:25], -v[26:27] v_add_f64 v[14:15], v[26:27], -v[14:15] v_div_scale_f64 v[34:35], null, v[4:5], v[4:5], v[16:17] v_div_scale_f64 v[64:65], vcc_lo, v[16:17], v[4:5], v[16:17] v_div_scale_f64 v[36:37], null, v[12:13], v[12:13], v[28:29] v_div_scale_f64 v[38:39], null, v[8:9], v[8:9], v[30:31] v_div_scale_f64 v[40:41], null, v[10:11], v[10:11], v[14:15] v_rcp_f64_e32 v[42:43], v[34:35] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_rcp_f64_e32 v[44:45], v[36:37] v_rcp_f64_e32 v[46:47], v[38:39] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3) v_rcp_f64_e32 v[48:49], v[40:41] v_fma_f64 v[50:51], -v[34:35], v[42:43], 1.0 v_fma_f64 v[52:53], -v[36:37], v[44:45], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[54:55], -v[38:39], v[46:47], 1.0 v_fma_f64 v[58:59], -v[40:41], v[48:49], 1.0 v_fma_f64 v[42:43], v[42:43], v[50:51], v[42:43] v_fma_f64 v[44:45], v[44:45], v[52:53], v[44:45] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[46:47], v[46:47], v[54:55], v[46:47] v_fma_f64 v[48:49], v[48:49], v[58:59], v[48:49] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[50:51], -v[34:35], v[42:43], 1.0 v_fma_f64 v[52:53], -v[36:37], v[44:45], 1.0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[54:55], -v[38:39], v[46:47], 1.0 v_fma_f64 v[58:59], -v[40:41], v[48:49], 1.0 s_delay_alu instid0(VALU_DEP_4) v_fma_f64 v[42:43], v[42:43], v[50:51], v[42:43] v_div_scale_f64 v[50:51], s0, v[28:29], v[12:13], v[28:29] v_fma_f64 v[44:45], v[44:45], v[52:53], v[44:45] v_div_scale_f64 v[52:53], s1, v[30:31], v[8:9], v[30:31] v_fma_f64 v[46:47], v[46:47], v[54:55], v[46:47] v_div_scale_f64 v[54:55], s2, v[14:15], v[10:11], v[14:15] v_fma_f64 v[48:49], v[48:49], v[58:59], v[48:49] v_mul_f64 v[58:59], v[64:65], v[42:43] v_mul_f64 v[66:67], v[50:51], v[44:45] v_mul_f64 v[68:69], v[52:53], v[46:47] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_mul_f64 v[70:71], v[54:55], v[48:49] v_fma_f64 v[34:35], -v[34:35], v[58:59], v[64:65] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[36:37], -v[36:37], v[66:67], v[50:51] v_fma_f64 v[38:39], -v[38:39], v[68:69], v[52:53] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[40:41], -v[40:41], v[70:71], v[54:55] v_div_fmas_f64 v[34:35], v[34:35], v[42:43], v[58:59] s_mov_b32 vcc_lo, s0 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_div_fmas_f64 v[36:37], v[36:37], v[44:45], v[66:67] s_mov_b32 vcc_lo, s1 v_div_fmas_f64 v[38:39], v[38:39], v[46:47], v[68:69] s_mov_b32 vcc_lo, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_div_fmas_f64 v[40:41], v[40:41], v[48:49], v[70:71] v_div_fixup_f64 v[4:5], v[34:35], v[4:5], v[16:17] v_mul_f64 v[16:17], v[6:7], v[32:33] v_div_fixup_f64 v[12:13], v[36:37], v[12:13], v[28:29] v_div_fixup_f64 v[8:9], v[38:39], v[8:9], v[30:31] v_div_fixup_f64 v[10:11], v[40:41], v[10:11], v[14:15] v_mul_f64 v[14:15], v[2:3], v[6:7] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_lt_f64_e64 vcc_lo, |v[12:13]|, |v[4:5]| v_cmp_lt_f64_e64 s0, |v[8:9]|, |v[12:13]| s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_cmp_lt_f64_e64 s1, |v[8:9]|, |v[10:11]| v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12 v_cmp_lt_f64_e64 vcc_lo, |v[24:25]|, |v[18:19]| v_cndmask_b32_e64 v13, v13, v9, s0 v_cndmask_b32_e64 v12, v12, v8, s0 v_cmp_lt_f64_e64 s0, |v[26:27]|, |v[24:25]| v_cndmask_b32_e64 v9, v11, v9, s1 v_cndmask_b32_e64 v8, v10, v8, s1 v_mul_f64 v[0:1], v[0:1], v[4:5] v_mul_f64 v[4:5], v[14:15], v[12:13] v_mul_f64 v[10:11], v[24:25], v[26:27] v_mul_f64 v[12:13], v[18:19], v[24:25] v_mul_f64 v[8:9], v[16:17], v[8:9] v_dual_cndmask_b32 v14, v19, v25 :: v_dual_cndmask_b32 v15, v18, v24 v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4 v_cmp_ngt_f64_e64 s1, 0, v[10:11] v_cmp_ngt_f64_e64 s2, 0, v[12:13] v_cndmask_b32_e64 v9, v5, v9, s0 v_cndmask_b32_e64 v5, v25, v27, s0 v_cndmask_b32_e64 v10, v24, v26, s0 v_cndmask_b32_e64 v8, v4, v8, s0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v13, 0, v5, s1 v_cndmask_b32_e64 v11, 0, v14, s2 v_cndmask_b32_e64 v12, 0, v10, s1 v_cndmask_b32_e64 v10, 0, v15, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[5:6], v[6:7], v[12:13], v[22:23] v_fma_f64 v[2:3], v[2:3], v[10:11], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[41:42], v[5:6], v[8:9] v_add_f64 v[0:1], v[2:3], v[0:1] .LBB1_31: ; %Flow365 s_or_b32 exec_lo, exec_lo, s5 s_waitcnt vmcnt(2) v_cmp_lt_f64_e64 vcc_lo, |v[62:63]|, |v[60:61]| s_load_b64 s[0:1], s[62:63], 0x10 v_lshlrev_b64 v[2:3], 3, v[56:57] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v1, v42, v1 :: v_dual_cndmask_b32 v0, v41, v0 s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s0, v2 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo global_store_b64 v[2:3], v[0:1], off .LBB1_32: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 8 .amdhsa_kernarg_size 384 .amdhsa_user_sgpr_count 13 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 1 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 1 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 88 .amdhsa_next_free_sgpr 74 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end1-_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 11636 ; NumSgprs: 76 ; NumVgprs: 88 ; ScratchSize: 8 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 9 ; VGPRBlocks: 10 ; NumSGPRsForWavesPerEU: 76 ; NumVGPRsForWavesPerEU: 88 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1 ; COMPUTE_PGM_RSRC2:USER_SGPR: 13 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2 .text .p2align 2 ; -- Begin function _Z12cubic_interpRdS_dddddddd .type _Z12cubic_interpRdS_dddddddd,@function _Z12cubic_interpRdS_dddddddd: ; @_Z12cubic_interpRdS_dddddddd ; %bb.0: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) s_or_saveexec_b32 s0, -1 scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill s_mov_b32 exec_lo, s0 v_writelane_b32 v40, s30, 0 v_writelane_b32 v40, s31, 1 v_frexp_mant_f64_e64 v[20:21], |v[8:9]| v_frexp_exp_i32_f64_e32 v28, v[8:9] s_mov_b32 s0, 0 s_mov_b32 s26, exec_lo s_mov_b32 s1, s0 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v23, s1 :: v_dual_mov_b32 v22, s0 flat_store_b64 v[0:1], v[22:23] flat_store_b64 v[2:3], v[22:23] v_cmpx_lt_f64_e32 v[4:5], v[8:9] s_cbranch_execz .LBB2_2 ; %bb.1: v_add_f64 v[26:27], v[16:17], -v[12:13] v_add_f64 v[24:25], v[14:15], -v[12:13] v_add_f64 v[22:23], v[18:19], -v[12:13] s_mov_b32 s5, 0x3fd55555 s_mov_b32 s4, 0x55555555 v_add_f64 v[4:5], v[4:5], v[8:9] s_mov_b32 s3, 0x3fba6564 s_mov_b32 s2, 0x968915a9 s_mov_b32 s7, 0x3fbdee67 s_mov_b32 s6, 0x4222de17 s_mov_b32 s9, 0x3fbe25e4 s_mov_b32 s8, 0x3abe935a s_mov_b32 s11, 0x3fc110ef s_mov_b32 s10, 0x47e6c9c2 s_mov_b32 s13, 0x3fc3b13b s_mov_b32 s12, 0xcfa74449 s_mov_b32 s15, 0x3fc745d1 s_mov_b32 s14, 0x71bf3c30 s_mov_b32 s17, 0x3fcc71c7 s_mov_b32 s16, 0x1c7792ce s_mov_b32 s19, 0x3fd24924 s_mov_b32 s18, 0x924920da s_mov_b32 s21, 0x3fd99999 s_mov_b32 s20, 0x9999999c s_mov_b32 s29, 0x3f2a01a0 s_mov_b32 s28, 0x14761f6e s_mov_b32 s23, 0x3fa55555 s_mov_b32 s22, 0x555502a1 s_mov_b32 s25, 0x3fc55555 s_mov_b32 s24, 0x55555511 s_mov_b32 s31, 0x3fe00000 s_mov_b32 s30, 11 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[29:30], v[26:27], 0xbff80000 v_frexp_mant_f64_e64 v[52:53], |v[4:5]| s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[24:25], 0x40080000, v[29:30] v_fma_f64 v[18:19], v[22:23], s[4:5], v[18:19] s_mov_b32 s5, 0x3fe55555 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[20:21] v_cmp_gt_f64_e64 s0, s[4:5], v[52:53] v_cndmask_b32_e64 v29, 0, 1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v39, 0, 1, s0 v_ldexp_f64 v[29:30], v[20:21], v29 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f64 v[31:32], v[29:30], 1.0 v_add_f64 v[37:38], v[29:30], -1.0 v_rcp_f64_e32 v[33:34], v[31:32] v_add_f64 v[48:49], v[31:32], -1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) v_add_f64 v[29:30], v[29:30], -v[48:49] s_waitcnt_depctr 0xfff v_fma_f64 v[35:36], -v[31:32], v[33:34], 1.0 v_ldexp_f64 v[48:49], v[52:53], v39 v_subrev_co_ci_u32_e32 v39, vcc_lo, 0, v28, vcc_lo v_fma_f64 v[33:34], v[35:36], v[33:34], v[33:34] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[35:36], -v[31:32], v[33:34], 1.0 v_fma_f64 v[33:34], v[35:36], v[33:34], v[33:34] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[35:36], v[37:38], v[33:34] v_mul_f64 v[50:51], v[31:32], v[35:36] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[31:32], v[35:36], v[31:32], -v[50:51] v_fma_f64 v[29:30], v[35:36], v[29:30], v[31:32] v_add_f64 v[31:32], v[48:49], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[52:53], v[50:51], v[29:30] v_rcp_f64_e32 v[54:55], v[31:32] s_delay_alu instid0(VALU_DEP_1) v_add_f64 v[64:65], v[37:38], -v[52:53] v_add_f64 v[50:51], v[52:53], -v[50:51] s_waitcnt_depctr 0xfff v_fma_f64 v[66:67], -v[31:32], v[54:55], 1.0 v_add_f64 v[37:38], v[37:38], -v[64:65] v_add_f64 v[29:30], v[50:51], -v[29:30] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[54:55], v[66:67], v[54:55], v[54:55] v_add_f64 v[37:38], v[37:38], -v[52:53] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[50:51], -v[31:32], v[54:55], 1.0 v_add_f64 v[29:30], v[29:30], v[37:38] v_add_f64 v[37:38], v[48:49], -1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[50:51], v[50:51], v[54:55], v[54:55] v_add_f64 v[29:30], v[64:65], v[29:30] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[52:53], v[37:38], v[50:51] v_mul_f64 v[29:30], v[33:34], v[29:30] v_add_f64 v[33:34], v[31:32], -1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f64 v[54:55], v[31:32], v[52:53] v_add_f64 v[64:65], v[35:36], v[29:30] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[33:34], v[48:49], -v[33:34] v_fma_f64 v[31:32], v[52:53], v[31:32], -v[54:55] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[35:36], v[64:65], -v[35:36] v_fma_f64 v[31:32], v[52:53], v[33:34], v[31:32] v_mul_f64 v[33:34], v[64:65], v[64:65] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[29:30], v[29:30], -v[35:36] v_add_f64 v[35:36], v[54:55], v[31:32] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[48:49], v[64:65], v[64:65], -v[33:34] v_add_f64 v[66:67], v[29:30], v[29:30] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[68:69], v[37:38], -v[35:36] v_add_f64 v[54:55], v[35:36], -v[54:55] v_fma_f64 v[48:49], v[64:65], v[66:67], v[48:49] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[37:38], v[37:38], -v[68:69] v_add_f64 v[31:32], v[54:55], -v[31:32] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[66:67], v[33:34], v[48:49] v_add_f64 v[35:36], v[37:38], -v[35:36] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_fma_f64 v[37:38], v[66:67], s[6:7], s[2:3] v_add_f64 v[33:34], v[66:67], -v[33:34] v_mul_f64 v[82:83], v[64:65], v[66:67] v_add_f64 v[31:32], v[31:32], v[35:36] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[35:36], v[66:67], v[37:38], s[8:9] v_add_f64 v[33:34], v[48:49], -v[33:34] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[31:32], v[68:69], v[31:32] v_fma_f64 v[35:36], v[66:67], v[35:36], s[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[31:32], v[50:51], v[31:32] v_fma_f64 v[35:36], v[66:67], v[35:36], s[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[37:38], v[52:53], v[31:32] v_fma_f64 v[35:36], v[66:67], v[35:36], s[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[50:51], v[37:38], -v[52:53] v_mul_f64 v[52:53], v[37:38], v[37:38] v_fma_f64 v[35:36], v[66:67], v[35:36], s[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[31:32], v[31:32], -v[50:51] v_fma_f64 v[50:51], v[37:38], v[37:38], -v[52:53] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[35:36], v[66:67], v[35:36], s[18:19] v_add_f64 v[54:55], v[31:32], v[31:32] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[35:36], v[66:67], v[35:36], s[20:21] v_fma_f64 v[50:51], v[37:38], v[54:55], v[50:51] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[54:55], v[66:67], v[35:36] v_add_f64 v[68:69], v[52:53], v[50:51] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[48:49], v[66:67], v[35:36], -v[54:55] v_fma_f64 v[70:71], v[68:69], s[6:7], s[2:3] s_mov_b32 s3, 0xbfe55555 s_mov_b32 s2, s4 s_mov_b32 s7, 0x3c8543b0 s_mov_b32 s6, 0xd5df274d v_add_f64 v[52:53], v[68:69], -v[52:53] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[35:36], v[33:34], v[35:36], v[48:49] v_fma_f64 v[48:49], v[68:69], v[70:71], s[8:9] s_mov_b32 s9, 0x3ec71dee s_mov_b32 s8, 0x623fde64 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[50:51], v[50:51], -v[52:53] v_add_f64 v[70:71], v[54:55], v[35:36] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_fma_f64 v[48:49], v[68:69], v[48:49], s[10:11] s_mov_b32 s11, 0x3fe62e42 s_mov_b32 s10, 0xfefa39ef v_add_f64 v[80:81], v[70:71], s[4:5] v_add_f64 v[54:55], v[70:71], -v[54:55] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[48:49], v[68:69], v[48:49], s[12:13] s_mov_b32 s13, 0x3e928af3 s_mov_b32 s12, 0xfca7ab0c v_add_f64 v[84:85], v[80:81], s[2:3] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[35:36], v[35:36], -v[54:55] v_fma_f64 v[54:55], v[66:67], v[64:65], -v[82:83] v_fma_f64 v[48:49], v[68:69], v[48:49], s[14:15] s_mov_b32 s15, 0x3c7abc9e s_mov_b32 s14, 0x3b39803f s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[70:71], v[70:71], -v[84:85] v_add_f64 v[35:36], v[35:36], s[6:7] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[54:55], v[66:67], v[29:30], v[54:55] v_fma_f64 v[48:49], v[68:69], v[48:49], s[16:17] v_ldexp_f64 v[29:30], v[29:30], 1 s_mov_b32 s17, 0x3e5ade15 s_mov_b32 s16, 0x6a5dcb37 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[35:36], v[35:36], v[70:71] v_fma_f64 v[33:34], v[33:34], v[64:65], v[54:55] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[48:49], v[68:69], v[48:49], s[18:19] s_mov_b32 s19, 0x3f811111 s_mov_b32 s18, 0x11122322 v_add_f64 v[54:55], v[80:81], v[35:36] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[66:67], v[82:83], v[33:34] v_fma_f64 v[48:49], v[68:69], v[48:49], s[20:21] s_mov_b32 s21, 0x3f56c16c s_mov_b32 s20, 0x1852b7b0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[70:71], v[80:81], -v[54:55] v_mul_f64 v[80:81], v[66:67], v[54:55] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_mul_f64 v[84:85], v[68:69], v[48:49] v_add_f64 v[82:83], v[66:67], -v[82:83] v_add_f64 v[35:36], v[35:36], v[70:71] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[70:71], v[66:67], v[54:55], -v[80:81] v_fma_f64 v[52:53], v[68:69], v[48:49], -v[84:85] s_delay_alu instid0(VALU_DEP_4) v_add_f64 v[33:34], v[33:34], -v[82:83] v_cvt_f64_i32_e32 v[82:83], v39 v_frexp_exp_i32_f64_e32 v39, v[4:5] v_fma_f64 v[35:36], v[66:67], v[35:36], v[70:71] v_fma_f64 v[48:49], v[50:51], v[48:49], v[52:53] v_ldexp_f64 v[52:53], v[64:65], 1 v_mul_f64 v[70:71], v[37:38], v[68:69] v_mul_f64 v[96:97], v[82:83], s[10:11] v_subrev_co_ci_u32_e64 v39, vcc_lo, 0, v39, s0 v_fma_f64 v[33:34], v[33:34], v[54:55], v[35:36] v_add_f64 v[35:36], v[84:85], v[48:49] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[54:55], v[80:81], v[33:34] v_add_f64 v[64:65], v[35:36], s[4:5] v_add_f64 v[66:67], v[35:36], -v[84:85] v_cmp_class_f64_e64 s5, v[8:9], 0x204 s_delay_alu instid0(VALU_DEP_4) v_add_f64 v[84:85], v[52:53], v[54:55] v_add_f64 v[80:81], v[54:55], -v[80:81] v_add_f64 v[86:87], v[64:65], s[2:3] v_add_f64 v[48:49], v[48:49], -v[66:67] v_fma_f64 v[66:67], v[68:69], v[37:38], -v[70:71] s_mov_b32 s3, 0x3ff71547 s_mov_b32 s2, 0x652b82fe v_add_f64 v[52:53], v[84:85], -v[52:53] v_add_f64 v[33:34], v[33:34], -v[80:81] v_add_f64 v[35:36], v[35:36], -v[86:87] v_add_f64 v[48:49], v[48:49], s[6:7] v_fma_f64 v[66:67], v[68:69], v[31:32], v[66:67] v_fma_f64 v[68:69], v[82:83], s[10:11], -v[96:97] v_ldexp_f64 v[31:32], v[31:32], 1 s_mov_b32 s7, 0x3efa0199 s_mov_b32 s6, 0x7c89e6b0 v_add_f64 v[52:53], v[54:55], -v[52:53] v_add_f64 v[29:30], v[29:30], v[33:34] v_add_f64 v[33:34], v[48:49], v[35:36] v_fma_f64 v[35:36], v[50:51], v[37:38], v[66:67] v_fma_f64 v[48:49], v[82:83], s[14:15], v[68:69] v_ldexp_f64 v[37:38], v[37:38], 1 v_add_f64 v[29:30], v[29:30], v[52:53] v_add_f64 v[50:51], v[64:65], v[33:34] v_add_f64 v[52:53], v[70:71], v[35:36] v_add_f64 v[54:55], v[96:97], v[48:49] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[66:67], v[84:85], v[29:30] v_add_f64 v[64:65], v[64:65], -v[50:51] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_mul_f64 v[68:69], v[52:53], v[50:51] v_add_f64 v[70:71], v[52:53], -v[70:71] v_add_f64 v[80:81], v[54:55], v[66:67] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[33:34], v[33:34], v[64:65] v_fma_f64 v[64:65], v[52:53], v[50:51], -v[68:69] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[35:36], v[35:36], -v[70:71] v_add_f64 v[82:83], v[80:81], -v[54:55] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_fma_f64 v[33:34], v[52:53], v[33:34], v[64:65] v_add_f64 v[52:53], v[54:55], -v[96:97] v_add_f64 v[64:65], v[66:67], -v[84:85] v_add_f64 v[70:71], v[80:81], -v[82:83] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[33:34], v[35:36], v[50:51], v[33:34] v_add_f64 v[35:36], v[48:49], -v[52:53] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_add_f64 v[29:30], v[29:30], -v[64:65] v_add_f64 v[48:49], v[66:67], -v[82:83] v_add_f64 v[50:51], v[54:55], -v[70:71] v_add_f64 v[52:53], v[68:69], v[33:34] v_add_f64 v[54:55], v[35:36], v[29:30] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[48:49], v[48:49], v[50:51] v_cvt_f64_i32_e32 v[50:51], v39 v_add_f64 v[64:65], v[37:38], v[52:53] v_add_f64 v[66:67], v[52:53], -v[68:69] v_add_f64 v[68:69], v[54:55], -v[35:36] v_add_f64 v[48:49], v[54:55], v[48:49] v_mul_f64 v[70:71], v[50:51], s[10:11] v_add_f64 v[37:38], v[64:65], -v[37:38] v_add_f64 v[33:34], v[33:34], -v[66:67] v_add_f64 v[54:55], v[54:55], -v[68:69] v_add_f64 v[29:30], v[29:30], -v[68:69] v_add_f64 v[66:67], v[80:81], v[48:49] v_fma_f64 v[82:83], v[50:51], s[10:11], -v[70:71] s_mov_b32 s11, 0xbfe62e42 v_add_f64 v[37:38], v[52:53], -v[37:38] v_add_f64 v[31:32], v[31:32], v[33:34] v_add_f64 v[33:34], v[35:36], -v[54:55] v_add_f64 v[35:36], v[66:67], -v[80:81] v_fma_f64 v[50:51], v[50:51], s[14:15], v[82:83] s_mov_b32 s15, 0xbc7abc9e s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[31:32], v[31:32], v[37:38] v_add_f64 v[29:30], v[29:30], v[33:34] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[33:34], v[48:49], -v[35:36] v_add_f64 v[35:36], v[70:71], v[50:51] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[37:38], v[64:65], v[31:32] v_add_f64 v[29:30], v[29:30], v[33:34] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[68:69], v[35:36], -v[70:71] v_add_f64 v[33:34], v[35:36], v[37:38] v_add_f64 v[64:65], v[37:38], -v[64:65] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[48:49], v[66:67], v[29:30] v_add_f64 v[50:51], v[50:51], -v[68:69] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[52:53], v[33:34], -v[35:36] v_add_f64 v[31:32], v[31:32], -v[64:65] s_delay_alu instid0(VALU_DEP_4) v_add_f64 v[54:55], v[48:49], -v[66:67] v_add_f64 v[66:67], v[48:49], v[48:49] v_mul_f64 v[80:81], v[48:49], 0x40080000 v_add_f64 v[70:71], v[33:34], -v[52:53] v_add_f64 v[37:38], v[37:38], -v[52:53] v_add_f64 v[29:30], v[29:30], -v[54:55] v_fma_f64 v[54:55], v[48:49], 2.0, -v[66:67] v_fma_f64 v[48:49], v[48:49], 0x40080000, -v[80:81] v_cmp_class_f64_e64 vcc_lo, v[66:67], 0x204 v_add_f64 v[35:36], v[35:36], -v[70:71] v_cmp_class_f64_e64 s0, v[80:81], 0x204 v_fma_f64 v[52:53], v[29:30], 2.0, v[54:55] v_fma_f64 v[29:30], v[29:30], 0x40080000, v[48:49] v_add_f64 v[54:55], v[50:51], v[31:32] v_add_f64 v[35:36], v[37:38], v[35:36] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[37:38], v[66:67], v[52:53] v_add_f64 v[64:65], v[80:81], v[29:30] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[48:49], v[54:55], -v[50:51] v_add_f64 v[35:36], v[54:55], v[35:36] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_dual_cndmask_b32 v69, v38, v67 :: v_dual_cndmask_b32 v68, v37, v66 v_cndmask_b32_e64 v83, v65, v81, s0 v_cndmask_b32_e64 v82, v64, v80, s0 v_add_f64 v[54:55], v[54:55], -v[48:49] v_add_f64 v[84:85], v[33:34], v[35:36] v_mul_f64 v[70:71], v[68:69], s[2:3] v_add_f64 v[31:32], v[31:32], -v[48:49] v_mul_f64 v[86:87], v[82:83], s[2:3] v_add_f64 v[37:38], v[37:38], -v[66:67] v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[68:69] v_add_f64 v[64:65], v[64:65], -v[80:81] v_add_f64 v[48:49], v[50:51], -v[54:55] v_add_f64 v[33:34], v[84:85], -v[33:34] v_rndne_f64_e32 v[70:71], v[70:71] v_rndne_f64_e32 v[50:51], v[86:87] v_add_f64 v[37:38], v[52:53], -v[37:38] v_add_f64 v[29:30], v[29:30], -v[64:65] v_add_f64 v[31:32], v[31:32], v[48:49] v_add_f64 v[33:34], v[35:36], -v[33:34] v_fma_f64 v[54:55], v[70:71], s[10:11], v[68:69] v_cvt_i32_f64_e32 v39, v[70:71] v_fma_f64 v[35:36], v[50:51], s[10:11], v[82:83] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[31:32], v[31:32], v[33:34] v_fma_f64 v[48:49], v[70:71], s[14:15], v[54:55] v_cvt_i32_f64_e32 v70, v[50:51] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_fma_f64 v[33:34], v[50:51], s[14:15], v[35:36] v_mul_f64 v[50:51], v[24:25], 0xc0040000 v_add_f64 v[54:55], v[84:85], v[31:32] v_fma_f64 v[35:36], v[48:49], s[16:17], s[12:13] v_fma_f64 v[86:87], v[33:34], s[16:17], s[12:13] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[84:85], v[54:55], -v[84:85] v_fma_f64 v[35:36], v[48:49], v[35:36], s[8:9] v_add_f64 v[96:97], v[54:55], v[54:55] s_delay_alu instid0(VALU_DEP_4) v_fma_f64 v[86:87], v[33:34], v[86:87], s[8:9] v_mul_f64 v[98:99], v[54:55], 0x40080000 v_add_f64 v[31:32], v[31:32], -v[84:85] v_fma_f64 v[35:36], v[48:49], v[35:36], s[6:7] v_fma_f64 v[84:85], v[54:55], 2.0, -v[96:97] v_fma_f64 v[86:87], v[33:34], v[86:87], s[6:7] v_fma_f64 v[54:55], v[54:55], 0x40080000, -v[98:99] v_cmp_class_f64_e64 vcc_lo, v[96:97], 0x204 v_cmp_class_f64_e64 s0, v[98:99], 0x204 v_fma_f64 v[35:36], v[48:49], v[35:36], s[28:29] v_fma_f64 v[84:85], v[31:32], 2.0, v[84:85] v_fma_f64 v[86:87], v[33:34], v[86:87], s[28:29] v_fma_f64 v[31:32], v[31:32], 0x40080000, v[54:55] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[35:36], v[48:49], v[35:36], s[20:21] v_add_f64 v[54:55], v[96:97], v[84:85] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[86:87], v[33:34], v[86:87], s[20:21] v_add_f64 v[100:101], v[98:99], v[31:32] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[35:36], v[48:49], v[35:36], s[18:19] v_dual_cndmask_b32 v103, v55, v97 :: v_dual_cndmask_b32 v102, v54, v96 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[86:87], v[33:34], v[86:87], s[18:19] v_cndmask_b32_e64 v115, v101, v99, s0 v_cndmask_b32_e64 v114, v100, v98, s0 v_cmp_nlt_f64_e64 s0, 0x40900000, v[68:69] v_mul_f64 v[112:113], v[102:103], s[2:3] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[68:69]| v_add_f64 v[54:55], v[54:55], -v[96:97] v_mul_f64 v[116:117], v[114:115], s[2:3] v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[82:83] v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[82:83]| v_fma_f64 v[35:36], v[48:49], v[35:36], s[22:23] v_fma_f64 v[86:87], v[33:34], v[86:87], s[22:23] v_rndne_f64_e32 v[112:113], v[112:113] v_dual_cndmask_b32 v38, 0, v38 :: v_dual_cndmask_b32 v37, 0, v37 v_rndne_f64_e32 v[116:117], v[116:117] v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[82:83] v_cndmask_b32_e64 v30, 0, v30, s2 v_cndmask_b32_e64 v29, 0, v29, s2 v_add_f64 v[54:55], v[84:85], -v[54:55] v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[102:103]| v_fma_f64 v[35:36], v[48:49], v[35:36], s[24:25] v_fma_f64 v[86:87], v[33:34], v[86:87], s[24:25] v_fma_f64 v[118:119], v[112:113], s[10:11], v[102:103] v_fma_f64 v[128:129], v[116:117], s[10:11], v[114:115] v_cvt_i32_f64_e32 v96, v[116:117] v_fma_f64 v[35:36], v[48:49], v[35:36], s[30:31] v_fma_f64 v[86:87], v[33:34], v[86:87], s[30:31] v_fma_f64 v[118:119], v[112:113], s[14:15], v[118:119] v_fma_f64 v[128:129], v[116:117], s[14:15], v[128:129] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[35:36], v[48:49], v[35:36], 1.0 v_fma_f64 v[86:87], v[33:34], v[86:87], 1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[66:67], v[128:129], s[16:17], s[12:13] v_fma_f64 v[35:36], v[48:49], v[35:36], 1.0 v_fma_f64 v[48:49], v[118:119], s[16:17], s[12:13] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[33:34], v[33:34], v[86:87], 1.0 v_fma_f64 v[52:53], v[128:129], v[66:67], s[8:9] v_mul_f64 v[66:67], v[26:27], -0.5 v_fma_f64 v[26:27], v[26:27], 2.0, v[50:51] v_ldexp_f64 v[35:36], v[35:36], v39 v_fma_f64 v[48:49], v[118:119], v[48:49], s[8:9] v_ldexp_f64 v[33:34], v[33:34], v70 v_fma_f64 v[50:51], v[128:129], v[52:53], s[6:7] v_fma_f64 v[24:25], v[24:25], 0.5, v[66:67] v_fma_f64 v[26:27], v[22:23], -0.5, v[26:27] v_div_scale_f64 v[52:53], null, v[8:9], v[8:9], v[18:19] v_cndmask_b32_e64 v36, 0x7ff00000, v36, s0 s_and_b32 s0, s1, s0 v_fma_f64 v[48:49], v[118:119], v[48:49], s[6:7] v_cndmask_b32_e64 v35, 0, v35, s0 v_cndmask_b32_e32 v34, 0x7ff00000, v34, vcc_lo v_cndmask_b32_e64 v36, 0, v36, s1 v_cmp_eq_f64_e64 s1, 0, v[8:9] s_and_b32 vcc_lo, s3, vcc_lo v_cmp_class_f64_e64 s6, v[4:5], 0x204 v_cndmask_b32_e64 v34, 0, v34, s3 v_fma_f64 v[37:38], v[35:36], v[37:38], v[35:36] v_cmp_class_f64_e64 s0, v[35:36], 0x204 v_fma_f64 v[50:51], v[128:129], v[50:51], s[28:29] v_cmp_nlt_f64_e64 s3, 0x40900000, v[102:103] v_fma_f64 v[48:49], v[118:119], v[48:49], s[28:29] v_cndmask_b32_e64 v39, 0x7ff00000, 0, s1 v_cndmask_b32_e64 v36, v38, v36, s0 v_cndmask_b32_e32 v33, 0, v33, vcc_lo v_cndmask_b32_e64 v35, v37, v35, s0 s_or_b32 s0, s1, s5 s_mov_b32 s5, s25 v_and_b32_e32 v36, 0x7fffffff, v36 v_fma_f64 v[29:30], v[33:34], v[29:30], v[33:34] v_cmp_class_f64_e64 vcc_lo, v[33:34], 0x204 v_cndmask_b32_e64 v35, v35, 0, s0 v_fma_f64 v[22:23], v[22:23], s[4:5], v[24:25] v_cndmask_b32_e64 v36, v36, v39, s0 v_rcp_f64_e32 v[37:38], v[52:53] v_fma_f64 v[50:51], v[128:129], v[50:51], s[20:21] v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[102:103] v_cmp_ngt_f64_e64 s5, 0xc090cc00, v[114:115] v_div_scale_f64 v[24:25], null, v[35:36], v[35:36], v[26:27] v_fma_f64 v[48:49], v[118:119], v[48:49], s[20:21] v_dual_cndmask_b32 v29, v29, v33 :: v_dual_cndmask_b32 v30, v30, v34 v_bfi_b32 v33, 0x7fffffff, v39, v9 v_div_scale_f64 v[80:81], vcc_lo, v[18:19], v[8:9], v[18:19] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v29, v29, 0, s0 v_bfi_b32 v30, 0x7fffffff, v30, v9 s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_fma_f64 v[66:67], -v[52:53], v[37:38], 1.0 v_rcp_f64_e32 v[64:65], v[24:25] v_fma_f64 v[50:51], v[128:129], v[50:51], s[18:19] v_cvt_i32_f64_e32 v39, v[112:113] v_cndmask_b32_e64 v30, v30, v33, s0 v_div_scale_f64 v[33:34], null, v[29:30], v[29:30], v[22:23] v_div_scale_f64 v[86:87], s1, v[22:23], v[29:30], v[22:23] v_fma_f64 v[48:49], v[118:119], v[48:49], s[18:19] v_fma_f64 v[37:38], v[37:38], v[66:67], v[37:38] v_fma_f64 v[50:51], v[128:129], v[50:51], s[22:23] s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_fma_f64 v[70:71], -v[24:25], v[64:65], 1.0 v_rcp_f64_e32 v[68:69], v[33:34] v_fma_f64 v[48:49], v[118:119], v[48:49], s[22:23] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[50:51], v[128:129], v[50:51], s[24:25] v_fma_f64 v[64:65], v[64:65], v[70:71], v[64:65] v_fma_f64 v[70:71], -v[52:53], v[37:38], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[66:67], -v[33:34], v[68:69], 1.0 v_fma_f64 v[48:49], v[118:119], v[48:49], s[24:25] v_fma_f64 v[50:51], v[128:129], v[50:51], s[30:31] v_fma_f64 v[37:38], v[37:38], v[70:71], v[37:38] v_div_scale_f64 v[70:71], s0, v[26:27], v[35:36], v[26:27] v_fma_f64 v[66:67], v[68:69], v[66:67], v[68:69] v_fma_f64 v[68:69], -v[24:25], v[64:65], 1.0 v_fma_f64 v[48:49], v[118:119], v[48:49], s[30:31] v_fma_f64 v[50:51], v[128:129], v[50:51], 1.0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[82:83], -v[33:34], v[66:67], 1.0 v_fma_f64 v[64:65], v[64:65], v[68:69], v[64:65] v_mul_f64 v[68:69], v[80:81], v[37:38] v_fma_f64 v[48:49], v[118:119], v[48:49], 1.0 v_fma_f64 v[50:51], v[128:129], v[50:51], 1.0 v_fma_f64 v[66:67], v[66:67], v[82:83], v[66:67] v_mul_f64 v[82:83], v[70:71], v[64:65] v_fma_f64 v[52:53], -v[52:53], v[68:69], v[80:81] v_fma_f64 v[48:49], v[118:119], v[48:49], 1.0 v_ldexp_f64 v[50:51], v[50:51], v96 v_mul_f64 v[80:81], v[86:87], v[66:67] v_fma_f64 v[24:25], -v[24:25], v[82:83], v[70:71] v_div_fmas_f64 v[37:38], v[52:53], v[37:38], v[68:69] v_add_f64 v[52:53], v[100:101], -v[98:99] v_ldexp_f64 v[48:49], v[48:49], v39 s_mov_b32 vcc_lo, s0 v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[114:115]| v_fma_f64 v[33:34], -v[33:34], v[80:81], v[86:87] v_div_fmas_f64 v[24:25], v[24:25], v[64:65], v[82:83] v_div_fixup_f64 v[18:19], v[37:38], v[8:9], v[18:19] v_cndmask_b32_e64 v38, 0, v55, s2 v_cndmask_b32_e64 v37, 0, v54, s2 v_cmp_nlt_f64_e64 s2, 0x40900000, v[114:115] v_add_f64 v[31:32], v[31:32], -v[52:53] v_cndmask_b32_e64 v39, 0x7ff00000, v49, s3 s_and_b32 vcc_lo, s4, s3 v_cndmask_b32_e32 v48, 0, v48, vcc_lo s_mov_b32 vcc_lo, s1 s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e64 v49, 0, v39, s4 v_cmp_eq_f64_e64 s4, 0, v[4:5] v_div_fmas_f64 v[33:34], v[33:34], v[66:67], v[80:81] v_div_fixup_f64 v[24:25], v[24:25], v[35:36], v[26:27] v_fma_f64 v[18:19], v[4:5], v[18:19], v[12:13] s_and_b32 vcc_lo, s5, s2 v_cndmask_b32_e64 v26, 0, v31, s0 v_cndmask_b32_e32 v31, 0, v50, vcc_lo v_fma_f64 v[37:38], v[48:49], v[37:38], v[48:49] v_cmp_class_f64_e64 s3, v[48:49], 0x204 v_cndmask_b32_e64 v51, 0x7ff00000, v51, s2 v_cndmask_b32_e64 v27, 0, v32, s0 s_or_b32 s0, s4, s6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v32, 0, v51, s5 v_fma_f64 v[26:27], v[31:32], v[26:27], v[31:32] v_cmp_class_f64_e64 vcc_lo, v[31:32], 0x204 v_div_fixup_f64 v[22:23], v[33:34], v[29:30], v[22:23] v_cndmask_b32_e64 v4, v38, v49, s3 v_cndmask_b32_e64 v38, 0x7ff00000, 0, s4 v_cndmask_b32_e64 v35, v37, v48, s3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v4, 0x7fffffff, v4 v_cndmask_b32_e64 v35, v35, 0, s0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v36, v4, v38, s0 v_cndmask_b32_e32 v4, v26, v31, vcc_lo v_fma_f64 v[18:19], v[24:25], v[35:36], v[18:19] v_cndmask_b32_e32 v24, v27, v32, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v4, v4, 0, s0 v_bfi_b32 v24, 0x7fffffff, v24, v5 v_bfi_b32 v5, 0x7fffffff, v38, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v5, v24, v5, s0 v_fma_f64 v[4:5], v[22:23], v[4:5], v[18:19] flat_store_b64 v[0:1], v[4:5] .LBB2_2: s_or_b32 exec_lo, exec_lo, s26 s_delay_alu instid0(SALU_CYCLE_1) s_mov_b32 s26, exec_lo v_cmpx_lt_f64_e32 v[6:7], v[8:9] s_cbranch_execz .LBB2_4 ; %bb.3: v_add_f64 v[14:15], v[14:15], -v[10:11] v_add_f64 v[12:13], v[12:13], -v[10:11] v_add_f64 v[4:5], v[16:17], -v[10:11] s_mov_b32 s5, 0x3fd55555 s_mov_b32 s4, 0x55555555 v_fma_f64 v[6:7], v[8:9], 2.0, -v[6:7] s_mov_b32 s3, 0x3fba6564 s_mov_b32 s2, 0x968915a9 s_mov_b32 s7, 0x3fbdee67 s_mov_b32 s6, 0x4222de17 s_mov_b32 s9, 0x3fbe25e4 s_mov_b32 s8, 0x3abe935a s_mov_b32 s11, 0x3fc110ef s_mov_b32 s10, 0x47e6c9c2 s_mov_b32 s13, 0x3fc3b13b s_mov_b32 s12, 0xcfa74449 s_mov_b32 s15, 0x3fc745d1 s_mov_b32 s14, 0x71bf3c30 s_mov_b32 s17, 0x3fcc71c7 s_mov_b32 s16, 0x1c7792ce s_mov_b32 s19, 0x3fd24924 s_mov_b32 s18, 0x924920da s_mov_b32 s21, 0x3fd99999 s_mov_b32 s20, 0x9999999c s_mov_b32 s29, 0x3f2a01a0 s_mov_b32 s28, 0x14761f6e s_mov_b32 s23, 0x3fa55555 s_mov_b32 s22, 0x555502a1 s_mov_b32 s25, 0x3fc55555 s_mov_b32 s24, 0x55555511 s_mov_b32 s31, 0x3fe00000 s_mov_b32 s30, 11 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[0:1], v[14:15], 0xbff80000 v_frexp_mant_f64_e64 v[31:32], |v[6:7]| s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[0:1], v[12:13], 0x40080000, v[0:1] v_fma_f64 v[0:1], v[4:5], s[4:5], v[0:1] s_mov_b32 s5, 0x3fe55555 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[20:21] v_cmp_gt_f64_e64 s0, s[4:5], v[31:32] v_cndmask_b32_e64 v16, 0, 1, vcc_lo v_subrev_co_ci_u32_e32 v28, vcc_lo, 0, v28, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[16:17], v[20:21], v16 v_add_f64 v[18:19], v[16:17], 1.0 v_add_f64 v[24:25], v[16:17], -1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[20:21], v[18:19] v_add_f64 v[26:27], v[18:19], -1.0 v_add_f64 v[16:17], v[16:17], -v[26:27] s_waitcnt_depctr 0xfff v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0 v_cndmask_b32_e64 v26, 0, 1, s0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_ldexp_f64 v[26:27], v[31:32], v26 v_fma_f64 v[20:21], v[22:23], v[20:21], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0 v_fma_f64 v[20:21], v[22:23], v[20:21], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[22:23], v[24:25], v[20:21] v_mul_f64 v[29:30], v[18:19], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], v[22:23], v[18:19], -v[29:30] v_fma_f64 v[16:17], v[22:23], v[16:17], v[18:19] v_add_f64 v[18:19], v[26:27], 1.0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[31:32], v[29:30], v[16:17] v_rcp_f64_e32 v[33:34], v[18:19] s_delay_alu instid0(VALU_DEP_1) v_add_f64 v[35:36], v[24:25], -v[31:32] v_add_f64 v[29:30], v[31:32], -v[29:30] s_waitcnt_depctr 0xfff v_fma_f64 v[37:38], -v[18:19], v[33:34], 1.0 v_add_f64 v[24:25], v[24:25], -v[35:36] v_add_f64 v[16:17], v[29:30], -v[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[33:34], v[37:38], v[33:34], v[33:34] v_add_f64 v[24:25], v[24:25], -v[31:32] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[29:30], -v[18:19], v[33:34], 1.0 v_add_f64 v[16:17], v[16:17], v[24:25] v_add_f64 v[24:25], v[26:27], -1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[29:30], v[29:30], v[33:34], v[33:34] v_add_f64 v[16:17], v[35:36], v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[31:32], v[24:25], v[29:30] v_mul_f64 v[16:17], v[20:21], v[16:17] v_add_f64 v[20:21], v[18:19], -1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f64 v[33:34], v[18:19], v[31:32] v_add_f64 v[35:36], v[22:23], v[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[20:21], v[26:27], -v[20:21] v_fma_f64 v[18:19], v[31:32], v[18:19], -v[33:34] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[35:36], -v[22:23] v_fma_f64 v[18:19], v[31:32], v[20:21], v[18:19] v_mul_f64 v[20:21], v[35:36], v[35:36] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[16:17], v[16:17], -v[22:23] v_add_f64 v[22:23], v[33:34], v[18:19] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[26:27], v[35:36], v[35:36], -v[20:21] v_add_f64 v[37:38], v[16:17], v[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[48:49], v[24:25], -v[22:23] v_add_f64 v[33:34], v[22:23], -v[33:34] v_fma_f64 v[26:27], v[35:36], v[37:38], v[26:27] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[24:25], v[24:25], -v[48:49] v_add_f64 v[18:19], v[33:34], -v[18:19] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[37:38], v[20:21], v[26:27] v_add_f64 v[22:23], v[24:25], -v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_fma_f64 v[24:25], v[37:38], s[6:7], s[2:3] v_add_f64 v[20:21], v[37:38], -v[20:21] v_mul_f64 v[54:55], v[35:36], v[37:38] v_add_f64 v[18:19], v[18:19], v[22:23] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[22:23], v[37:38], v[24:25], s[8:9] v_add_f64 v[20:21], v[26:27], -v[20:21] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[18:19], v[48:49], v[18:19] v_fma_f64 v[22:23], v[37:38], v[22:23], s[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[18:19], v[29:30], v[18:19] v_fma_f64 v[22:23], v[37:38], v[22:23], s[12:13] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[24:25], v[31:32], v[18:19] v_fma_f64 v[22:23], v[37:38], v[22:23], s[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_f64 v[29:30], v[24:25], -v[31:32] v_mul_f64 v[31:32], v[24:25], v[24:25] v_fma_f64 v[22:23], v[37:38], v[22:23], s[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[18:19], v[18:19], -v[29:30] v_fma_f64 v[29:30], v[24:25], v[24:25], -v[31:32] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[22:23], v[37:38], v[22:23], s[18:19] v_add_f64 v[33:34], v[18:19], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[22:23], v[37:38], v[22:23], s[20:21] v_fma_f64 v[29:30], v[24:25], v[33:34], v[29:30] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[33:34], v[37:38], v[22:23] v_add_f64 v[48:49], v[31:32], v[29:30] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[37:38], v[22:23], -v[33:34] v_fma_f64 v[50:51], v[48:49], s[6:7], s[2:3] s_mov_b32 s3, 0xbfe55555 s_mov_b32 s2, s4 s_mov_b32 s7, 0x3c8543b0 s_mov_b32 s6, 0xd5df274d v_add_f64 v[31:32], v[48:49], -v[31:32] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[22:23], v[20:21], v[22:23], v[26:27] v_fma_f64 v[26:27], v[48:49], v[50:51], s[8:9] s_mov_b32 s9, 0x3ec71dee s_mov_b32 s8, 0x623fde64 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[29:30], v[29:30], -v[31:32] v_add_f64 v[50:51], v[33:34], v[22:23] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_fma_f64 v[26:27], v[48:49], v[26:27], s[10:11] s_mov_b32 s11, 0x3fe62e42 s_mov_b32 s10, 0xfefa39ef v_add_f64 v[52:53], v[50:51], s[4:5] v_add_f64 v[33:34], v[50:51], -v[33:34] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[26:27], v[48:49], v[26:27], s[12:13] s_mov_b32 s13, 0x3e928af3 s_mov_b32 s12, 0xfca7ab0c v_add_f64 v[64:65], v[52:53], s[2:3] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[22:23], v[22:23], -v[33:34] v_fma_f64 v[33:34], v[37:38], v[35:36], -v[54:55] v_fma_f64 v[26:27], v[48:49], v[26:27], s[14:15] s_mov_b32 s15, 0x3c7abc9e s_mov_b32 s14, 0x3b39803f s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[50:51], v[50:51], -v[64:65] v_add_f64 v[22:23], v[22:23], s[6:7] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[33:34], v[37:38], v[16:17], v[33:34] v_fma_f64 v[26:27], v[48:49], v[26:27], s[16:17] v_ldexp_f64 v[16:17], v[16:17], 1 s_mov_b32 s17, 0x3e5ade15 s_mov_b32 s16, 0x6a5dcb37 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[22:23], v[22:23], v[50:51] v_fma_f64 v[20:21], v[20:21], v[35:36], v[33:34] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[26:27], v[48:49], v[26:27], s[18:19] s_mov_b32 s19, 0x3f811111 s_mov_b32 s18, 0x11122322 v_add_f64 v[33:34], v[52:53], v[22:23] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[37:38], v[54:55], v[20:21] v_fma_f64 v[26:27], v[48:49], v[26:27], s[20:21] s_mov_b32 s21, 0x3f56c16c s_mov_b32 s20, 0x1852b7b0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[50:51], v[52:53], -v[33:34] v_mul_f64 v[52:53], v[37:38], v[33:34] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_mul_f64 v[64:65], v[48:49], v[26:27] v_add_f64 v[54:55], v[37:38], -v[54:55] v_add_f64 v[22:23], v[22:23], v[50:51] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[50:51], v[37:38], v[33:34], -v[52:53] v_fma_f64 v[31:32], v[48:49], v[26:27], -v[64:65] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[20:21], v[20:21], -v[54:55] v_cvt_f64_i32_e32 v[54:55], v28 v_fma_f64 v[22:23], v[37:38], v[22:23], v[50:51] s_delay_alu instid0(VALU_DEP_4) v_fma_f64 v[26:27], v[29:30], v[26:27], v[31:32] v_ldexp_f64 v[31:32], v[35:36], 1 v_mul_f64 v[50:51], v[24:25], v[48:49] v_mul_f64 v[68:69], v[54:55], s[10:11] v_fma_f64 v[20:21], v[20:21], v[33:34], v[22:23] v_add_f64 v[22:23], v[64:65], v[26:27] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[33:34], v[52:53], v[20:21] v_add_f64 v[35:36], v[22:23], s[4:5] v_add_f64 v[37:38], v[22:23], -v[64:65] v_cmp_class_f64_e64 s5, v[8:9], 0x204 s_delay_alu instid0(VALU_DEP_4) v_add_f64 v[64:65], v[31:32], v[33:34] v_add_f64 v[52:53], v[33:34], -v[52:53] v_add_f64 v[66:67], v[35:36], s[2:3] v_add_f64 v[26:27], v[26:27], -v[37:38] v_fma_f64 v[37:38], v[48:49], v[24:25], -v[50:51] s_mov_b32 s3, 0x3ff71547 s_mov_b32 s2, 0x652b82fe v_add_f64 v[31:32], v[64:65], -v[31:32] v_add_f64 v[20:21], v[20:21], -v[52:53] v_add_f64 v[22:23], v[22:23], -v[66:67] v_add_f64 v[26:27], v[26:27], s[6:7] v_fma_f64 v[37:38], v[48:49], v[18:19], v[37:38] v_fma_f64 v[48:49], v[54:55], s[10:11], -v[68:69] v_ldexp_f64 v[18:19], v[18:19], 1 s_mov_b32 s7, 0x3efa0199 s_mov_b32 s6, 0x7c89e6b0 v_add_f64 v[31:32], v[33:34], -v[31:32] v_add_f64 v[16:17], v[16:17], v[20:21] v_add_f64 v[20:21], v[26:27], v[22:23] v_fma_f64 v[22:23], v[29:30], v[24:25], v[37:38] v_fma_f64 v[26:27], v[54:55], s[14:15], v[48:49] v_ldexp_f64 v[24:25], v[24:25], 1 v_add_f64 v[16:17], v[16:17], v[31:32] v_add_f64 v[28:29], v[35:36], v[20:21] v_add_f64 v[30:31], v[50:51], v[22:23] v_add_f64 v[32:33], v[68:69], v[26:27] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[37:38], v[64:65], v[16:17] v_add_f64 v[34:35], v[35:36], -v[28:29] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_mul_f64 v[48:49], v[30:31], v[28:29] v_add_f64 v[50:51], v[30:31], -v[50:51] v_add_f64 v[52:53], v[32:33], v[37:38] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[20:21], v[20:21], v[34:35] v_fma_f64 v[34:35], v[30:31], v[28:29], -v[48:49] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[22:23], v[22:23], -v[50:51] v_add_f64 v[54:55], v[52:53], -v[32:33] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) v_fma_f64 v[20:21], v[30:31], v[20:21], v[34:35] v_add_f64 v[30:31], v[32:33], -v[68:69] v_add_f64 v[34:35], v[37:38], -v[64:65] v_add_f64 v[50:51], v[52:53], -v[54:55] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[20:21], v[22:23], v[28:29], v[20:21] v_add_f64 v[22:23], v[26:27], -v[30:31] s_delay_alu instid0(VALU_DEP_4) v_add_f64 v[16:17], v[16:17], -v[34:35] v_add_f64 v[26:27], v[37:38], -v[54:55] v_frexp_exp_i32_f64_e32 v34, v[6:7] v_add_f64 v[28:29], v[32:33], -v[50:51] v_add_f64 v[30:31], v[48:49], v[20:21] v_add_f64 v[32:33], v[22:23], v[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[26:27], v[26:27], v[28:29] v_subrev_co_ci_u32_e64 v28, vcc_lo, 0, v34, s0 v_add_f64 v[34:35], v[24:25], v[30:31] v_add_f64 v[36:37], v[30:31], -v[48:49] v_add_f64 v[38:39], v[32:33], -v[22:23] s_delay_alu instid0(VALU_DEP_4) v_cvt_f64_i32_e32 v[28:29], v28 v_add_f64 v[26:27], v[32:33], v[26:27] v_add_f64 v[24:25], v[34:35], -v[24:25] v_add_f64 v[20:21], v[20:21], -v[36:37] v_add_f64 v[32:33], v[32:33], -v[38:39] v_mul_f64 v[48:49], v[28:29], s[10:11] v_add_f64 v[16:17], v[16:17], -v[38:39] v_add_f64 v[36:37], v[52:53], v[26:27] v_add_f64 v[24:25], v[30:31], -v[24:25] v_add_f64 v[18:19], v[18:19], v[20:21] v_add_f64 v[20:21], v[22:23], -v[32:33] v_fma_f64 v[50:51], v[28:29], s[10:11], -v[48:49] s_mov_b32 s11, 0xbfe62e42 v_add_f64 v[22:23], v[36:37], -v[52:53] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[18:19], v[18:19], v[24:25] v_add_f64 v[16:17], v[16:17], v[20:21] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_fma_f64 v[28:29], v[28:29], s[14:15], v[50:51] s_mov_b32 s15, 0xbc7abc9e v_add_f64 v[20:21], v[26:27], -v[22:23] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[24:25], v[34:35], v[18:19] v_add_f64 v[22:23], v[48:49], v[28:29] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[16:17], v[16:17], v[20:21] v_add_f64 v[34:35], v[24:25], -v[34:35] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_add_f64 v[20:21], v[22:23], v[24:25] v_add_f64 v[38:39], v[22:23], -v[48:49] v_add_f64 v[26:27], v[36:37], v[16:17] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[18:19], v[18:19], -v[34:35] v_add_f64 v[30:31], v[20:21], -v[22:23] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[28:29], v[28:29], -v[38:39] v_add_f64 v[32:33], v[26:27], -v[36:37] v_add_f64 v[36:37], v[26:27], v[26:27] v_mul_f64 v[50:51], v[26:27], 0x40080000 v_add_f64 v[48:49], v[20:21], -v[30:31] v_add_f64 v[24:25], v[24:25], -v[30:31] v_add_f64 v[16:17], v[16:17], -v[32:33] v_fma_f64 v[32:33], v[26:27], 2.0, -v[36:37] v_fma_f64 v[26:27], v[26:27], 0x40080000, -v[50:51] v_cmp_class_f64_e64 vcc_lo, v[36:37], 0x204 v_cmp_class_f64_e64 s0, v[50:51], 0x204 v_add_f64 v[22:23], v[22:23], -v[48:49] v_fma_f64 v[30:31], v[16:17], 2.0, v[32:33] v_fma_f64 v[16:17], v[16:17], 0x40080000, v[26:27] v_add_f64 v[32:33], v[28:29], v[18:19] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[22:23], v[24:25], v[22:23] v_add_f64 v[24:25], v[36:37], v[30:31] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[34:35], v[50:51], v[16:17] v_add_f64 v[26:27], v[32:33], -v[28:29] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[22:23], v[32:33], v[22:23] v_dual_cndmask_b32 v39, v25, v37 :: v_dual_cndmask_b32 v38, v24, v36 s_delay_alu instid0(VALU_DEP_4) v_cndmask_b32_e64 v53, v35, v51, s0 v_cndmask_b32_e64 v52, v34, v50, s0 v_add_f64 v[32:33], v[32:33], -v[26:27] v_add_f64 v[54:55], v[20:21], v[22:23] v_mul_f64 v[48:49], v[38:39], s[2:3] v_add_f64 v[18:19], v[18:19], -v[26:27] v_mul_f64 v[64:65], v[52:53], s[2:3] v_add_f64 v[24:25], v[24:25], -v[36:37] v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[38:39] v_add_f64 v[34:35], v[34:35], -v[50:51] v_add_f64 v[26:27], v[28:29], -v[32:33] v_add_f64 v[20:21], v[54:55], -v[20:21] v_rndne_f64_e32 v[48:49], v[48:49] v_rndne_f64_e32 v[28:29], v[64:65] v_add_f64 v[24:25], v[30:31], -v[24:25] v_add_f64 v[16:17], v[16:17], -v[34:35] v_add_f64 v[18:19], v[18:19], v[26:27] v_add_f64 v[20:21], v[22:23], -v[20:21] v_fma_f64 v[32:33], v[48:49], s[10:11], v[38:39] v_fma_f64 v[22:23], v[28:29], s[10:11], v[52:53] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[18:19], v[18:19], v[20:21] v_fma_f64 v[26:27], v[48:49], s[14:15], v[32:33] v_cvt_i32_f64_e32 v48, v[48:49] s_delay_alu instid0(VALU_DEP_4) v_fma_f64 v[20:21], v[28:29], s[14:15], v[22:23] v_cvt_i32_f64_e32 v49, v[28:29] v_mul_f64 v[28:29], v[12:13], 0xc0040000 v_add_f64 v[32:33], v[54:55], v[18:19] v_fma_f64 v[22:23], v[26:27], s[16:17], s[12:13] v_fma_f64 v[64:65], v[20:21], s[16:17], s[12:13] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64 v[54:55], v[32:33], -v[54:55] v_fma_f64 v[22:23], v[26:27], v[22:23], s[8:9] v_add_f64 v[66:67], v[32:33], v[32:33] s_delay_alu instid0(VALU_DEP_4) v_fma_f64 v[64:65], v[20:21], v[64:65], s[8:9] v_mul_f64 v[68:69], v[32:33], 0x40080000 v_add_f64 v[18:19], v[18:19], -v[54:55] v_fma_f64 v[22:23], v[26:27], v[22:23], s[6:7] v_fma_f64 v[54:55], v[32:33], 2.0, -v[66:67] v_fma_f64 v[64:65], v[20:21], v[64:65], s[6:7] v_fma_f64 v[32:33], v[32:33], 0x40080000, -v[68:69] v_cmp_class_f64_e64 vcc_lo, v[66:67], 0x204 v_cmp_class_f64_e64 s0, v[68:69], 0x204 v_fma_f64 v[22:23], v[26:27], v[22:23], s[28:29] v_fma_f64 v[54:55], v[18:19], 2.0, v[54:55] v_fma_f64 v[64:65], v[20:21], v[64:65], s[28:29] v_fma_f64 v[18:19], v[18:19], 0x40080000, v[32:33] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[22:23], v[26:27], v[22:23], s[20:21] v_add_f64 v[32:33], v[66:67], v[54:55] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[64:65], v[20:21], v[64:65], s[20:21] v_add_f64 v[70:71], v[68:69], v[18:19] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[22:23], v[26:27], v[22:23], s[18:19] v_dual_cndmask_b32 v81, v33, v67 :: v_dual_cndmask_b32 v80, v32, v66 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[64:65], v[20:21], v[64:65], s[18:19] v_cndmask_b32_e64 v85, v71, v69, s0 v_cndmask_b32_e64 v84, v70, v68, s0 v_cmp_nlt_f64_e64 s0, 0x40900000, v[38:39] v_mul_f64 v[82:83], v[80:81], s[2:3] v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[38:39]| v_add_f64 v[32:33], v[32:33], -v[66:67] v_mul_f64 v[86:87], v[84:85], s[2:3] v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[52:53] v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[52:53]| v_fma_f64 v[22:23], v[26:27], v[22:23], s[22:23] v_fma_f64 v[64:65], v[20:21], v[64:65], s[22:23] v_rndne_f64_e32 v[82:83], v[82:83] v_dual_cndmask_b32 v25, 0, v25 :: v_dual_cndmask_b32 v24, 0, v24 v_rndne_f64_e32 v[86:87], v[86:87] v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[52:53] v_cndmask_b32_e64 v17, 0, v17, s2 v_cndmask_b32_e64 v16, 0, v16, s2 v_add_f64 v[32:33], v[54:55], -v[32:33] v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[80:81]| v_fma_f64 v[22:23], v[26:27], v[22:23], s[24:25] v_fma_f64 v[64:65], v[20:21], v[64:65], s[24:25] v_fma_f64 v[96:97], v[82:83], s[10:11], v[80:81] v_fma_f64 v[98:99], v[86:87], s[10:11], v[84:85] v_cvt_i32_f64_e32 v66, v[86:87] v_fma_f64 v[22:23], v[26:27], v[22:23], s[30:31] v_fma_f64 v[64:65], v[20:21], v[64:65], s[30:31] v_fma_f64 v[96:97], v[82:83], s[14:15], v[96:97] v_cvt_i32_f64_e32 v82, v[82:83] v_fma_f64 v[98:99], v[86:87], s[14:15], v[98:99] v_fma_f64 v[22:23], v[26:27], v[22:23], 1.0 v_fma_f64 v[64:65], v[20:21], v[64:65], 1.0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[36:37], v[98:99], s[16:17], s[12:13] v_fma_f64 v[22:23], v[26:27], v[22:23], 1.0 v_fma_f64 v[26:27], v[96:97], s[16:17], s[12:13] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[20:21], v[20:21], v[64:65], 1.0 v_fma_f64 v[30:31], v[98:99], v[36:37], s[8:9] v_mul_f64 v[36:37], v[14:15], -0.5 v_fma_f64 v[14:15], v[14:15], 2.0, v[28:29] v_ldexp_f64 v[22:23], v[22:23], v48 v_fma_f64 v[26:27], v[96:97], v[26:27], s[8:9] v_ldexp_f64 v[20:21], v[20:21], v49 v_fma_f64 v[28:29], v[98:99], v[30:31], s[6:7] v_fma_f64 v[12:13], v[12:13], 0.5, v[36:37] v_fma_f64 v[14:15], v[4:5], -0.5, v[14:15] v_div_scale_f64 v[30:31], null, v[8:9], v[8:9], v[0:1] v_cndmask_b32_e64 v23, 0x7ff00000, v23, s0 s_and_b32 s0, s1, s0 v_fma_f64 v[26:27], v[96:97], v[26:27], s[6:7] v_cndmask_b32_e64 v22, 0, v22, s0 v_cndmask_b32_e32 v21, 0x7ff00000, v21, vcc_lo v_cndmask_b32_e64 v23, 0, v23, s1 v_cmp_eq_f64_e64 s1, 0, v[8:9] s_and_b32 vcc_lo, s3, vcc_lo v_cmp_class_f64_e64 s6, v[6:7], 0x204 v_cndmask_b32_e64 v21, 0, v21, s3 v_fma_f64 v[24:25], v[22:23], v[24:25], v[22:23] v_cmp_class_f64_e64 s0, v[22:23], 0x204 v_fma_f64 v[28:29], v[98:99], v[28:29], s[28:29] v_cmp_nlt_f64_e64 s3, 0x40900000, v[80:81] v_fma_f64 v[26:27], v[96:97], v[26:27], s[28:29] v_cndmask_b32_e64 v34, 0x7ff00000, 0, s1 v_cndmask_b32_e64 v23, v25, v23, s0 v_cndmask_b32_e32 v20, 0, v20, vcc_lo v_cndmask_b32_e64 v22, v24, v22, s0 s_or_b32 s0, s1, s5 s_mov_b32 s5, s25 v_and_b32_e32 v23, 0x7fffffff, v23 v_fma_f64 v[16:17], v[20:21], v[16:17], v[20:21] v_cmp_class_f64_e64 vcc_lo, v[20:21], 0x204 v_cndmask_b32_e64 v22, v22, 0, s0 v_fma_f64 v[4:5], v[4:5], s[4:5], v[12:13] v_cndmask_b32_e64 v23, v23, v34, s0 v_rcp_f64_e32 v[24:25], v[30:31] v_fma_f64 v[28:29], v[98:99], v[28:29], s[20:21] v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[80:81] v_cmp_ngt_f64_e64 s5, 0xc090cc00, v[84:85] v_div_scale_f64 v[12:13], null, v[22:23], v[22:23], v[14:15] v_fma_f64 v[26:27], v[96:97], v[26:27], s[20:21] v_dual_cndmask_b32 v16, v16, v20 :: v_dual_cndmask_b32 v17, v17, v21 v_bfi_b32 v20, 0x7fffffff, v34, v9 v_div_scale_f64 v[50:51], vcc_lo, v[0:1], v[8:9], v[0:1] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v16, v16, 0, s0 v_bfi_b32 v17, 0x7fffffff, v17, v9 s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[36:37], -v[30:31], v[24:25], 1.0 v_rcp_f64_e32 v[34:35], v[12:13] v_fma_f64 v[28:29], v[98:99], v[28:29], s[18:19] v_cndmask_b32_e64 v17, v17, v20, s0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(TRANS32_DEP_1) v_div_scale_f64 v[20:21], null, v[16:17], v[16:17], v[4:5] v_div_scale_f64 v[64:65], s1, v[4:5], v[16:17], v[4:5] v_fma_f64 v[26:27], v[96:97], v[26:27], s[18:19] v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25] v_fma_f64 v[28:29], v[98:99], v[28:29], s[22:23] v_fma_f64 v[48:49], -v[12:13], v[34:35], 1.0 v_rcp_f64_e32 v[38:39], v[20:21] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f64 v[26:27], v[96:97], v[26:27], s[22:23] v_fma_f64 v[28:29], v[98:99], v[28:29], s[24:25] s_delay_alu instid0(VALU_DEP_3) v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35] v_fma_f64 v[48:49], -v[30:31], v[24:25], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[36:37], -v[20:21], v[38:39], 1.0 v_fma_f64 v[26:27], v[96:97], v[26:27], s[24:25] v_fma_f64 v[28:29], v[98:99], v[28:29], s[30:31] v_fma_f64 v[24:25], v[24:25], v[48:49], v[24:25] v_div_scale_f64 v[48:49], s0, v[14:15], v[22:23], v[14:15] v_fma_f64 v[36:37], v[38:39], v[36:37], v[38:39] v_fma_f64 v[38:39], -v[12:13], v[34:35], 1.0 v_fma_f64 v[26:27], v[96:97], v[26:27], s[30:31] v_fma_f64 v[28:29], v[98:99], v[28:29], 1.0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[52:53], -v[20:21], v[36:37], 1.0 v_fma_f64 v[34:35], v[34:35], v[38:39], v[34:35] v_mul_f64 v[38:39], v[50:51], v[24:25] v_fma_f64 v[26:27], v[96:97], v[26:27], 1.0 v_fma_f64 v[28:29], v[98:99], v[28:29], 1.0 v_fma_f64 v[36:37], v[36:37], v[52:53], v[36:37] v_mul_f64 v[52:53], v[48:49], v[34:35] v_fma_f64 v[30:31], -v[30:31], v[38:39], v[50:51] v_fma_f64 v[26:27], v[96:97], v[26:27], 1.0 v_ldexp_f64 v[28:29], v[28:29], v66 v_mul_f64 v[50:51], v[64:65], v[36:37] v_fma_f64 v[12:13], -v[12:13], v[52:53], v[48:49] v_div_fmas_f64 v[24:25], v[30:31], v[24:25], v[38:39] v_add_f64 v[30:31], v[70:71], -v[68:69] v_ldexp_f64 v[26:27], v[26:27], v82 s_mov_b32 vcc_lo, s0 v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[84:85]| v_fma_f64 v[20:21], -v[20:21], v[50:51], v[64:65] v_div_fmas_f64 v[12:13], v[12:13], v[34:35], v[52:53] v_div_fixup_f64 v[0:1], v[24:25], v[8:9], v[0:1] v_add_f64 v[8:9], v[18:19], -v[30:31] v_cndmask_b32_e64 v27, 0x7ff00000, v27, s3 v_cndmask_b32_e64 v19, 0, v33, s2 v_cndmask_b32_e64 v18, 0, v32, s2 v_cmp_nlt_f64_e64 s2, 0x40900000, v[84:85] s_and_b32 vcc_lo, s4, s3 v_cndmask_b32_e64 v25, 0, v27, s4 v_cndmask_b32_e32 v24, 0, v26, vcc_lo v_cmp_eq_f64_e64 s4, 0, v[6:7] s_mov_b32 vcc_lo, s1 s_delay_alu instid0(VALU_DEP_2) v_fma_f64 v[18:19], v[24:25], v[18:19], v[24:25] v_cmp_class_f64_e64 s3, v[24:25], 0x204 v_div_fmas_f64 v[20:21], v[20:21], v[36:37], v[50:51] v_div_fixup_f64 v[12:13], v[12:13], v[22:23], v[14:15] v_fma_f64 v[0:1], v[6:7], v[0:1], v[10:11] v_cndmask_b32_e64 v9, 0, v9, s0 v_cndmask_b32_e64 v8, 0, v8, s0 v_cndmask_b32_e64 v29, 0x7ff00000, v29, s2 s_and_b32 vcc_lo, s5, s2 v_cndmask_b32_e32 v10, 0, v28, vcc_lo s_or_b32 s0, s4, s6 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v11, 0, v29, s5 v_cndmask_b32_e64 v6, v19, v25, s3 v_fma_f64 v[8:9], v[10:11], v[8:9], v[10:11] v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x204 v_cndmask_b32_e64 v19, 0x7ff00000, 0, s4 v_cndmask_b32_e64 v14, v18, v24, s3 v_and_b32_e32 v6, 0x7fffffff, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v14, v14, 0, s0 v_cndmask_b32_e64 v15, v6, v19, s0 v_div_fixup_f64 v[4:5], v[20:21], v[16:17], v[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_fma_f64 v[0:1], v[12:13], v[14:15], v[0:1] v_cndmask_b32_e32 v6, v8, v10, vcc_lo v_cndmask_b32_e32 v8, v9, v11, vcc_lo v_cndmask_b32_e64 v6, v6, 0, s0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_bfi_b32 v8, 0x7fffffff, v8, v7 v_bfi_b32 v7, 0x7fffffff, v19, v7 v_cndmask_b32_e64 v7, v8, v7, s0 s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[0:1], v[4:5], v[6:7], v[0:1] flat_store_b64 v[2:3], v[0:1] .LBB2_4: s_or_b32 exec_lo, exec_lo, s26 v_readlane_b32 s30, v40, 0 v_readlane_b32 s31, v40, 1 s_or_saveexec_b32 s0, -1 scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload s_mov_b32 exec_lo, s0 s_waitcnt vmcnt(0) lgkmcnt(0) s_setpc_b64 s[30:31] .Lfunc_end2: .size _Z12cubic_interpRdS_dddddddd, .Lfunc_end2-_Z12cubic_interpRdS_dddddddd ; -- End function .section .AMDGPU.csdata,"",@progbits ; Function info: ; codeLenInByte = 8956 ; NumSgprs: 35 ; NumVgprs: 130 ; ScratchSize: 8 ; MemoryBound: 0 .text .protected _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi ; -- Begin function _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .globl _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .p2align 8 .type _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi,@function _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: ; @_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi ; %bb.0: s_clause 0x2 s_load_b64 s[2:3], s[0:1], 0xa4 s_load_b64 s[34:35], s[0:1], 0x68 s_load_b32 s4, s[0:1], 0x70 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v2, v0, 10, 10 v_bfe_u32 v3, v0, 20, 10 s_mov_b32 s32, 0 s_waitcnt lgkmcnt(0) s_and_b32 s5, s2, 0xffff s_lshr_b32 s2, s2, 16 s_and_b32 s3, s3, 0xffff v_mad_u64_u32 v[58:59], null, s13, s5, v[1:2] v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3] v_mad_u64_u32 v[41:42], null, s15, s3, v[3:4] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_gt_i32_e32 vcc_lo, s34, v58 v_cmp_gt_i32_e64 s2, s35, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e64 s3, s4, v41 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_b32 s2, s2, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB3_2 ; %bb.1: v_cvt_f64_i32_e32 v[1:2], v41 s_add_i32 s4, s4, -1 v_add_nc_u32_e32 v9, 2, v0 v_add_nc_u32_e32 v11, -1, v0 v_add_nc_u32_e32 v13, -2, v0 v_cvt_f64_i32_e32 v[5:6], v0 v_cvt_f64_i32_e32 v[42:43], s4 v_add_nc_u32_e32 v7, 1, v0 v_cvt_f64_i32_e32 v[3:4], v58 v_cvt_f64_i32_e32 v[9:10], v9 v_cvt_f64_i32_e32 v[11:12], v11 v_cvt_f64_i32_e32 v[13:14], v13 s_add_i32 s3, s35, -1 s_add_i32 s2, s34, -1 v_cvt_f64_i32_e32 v[15:16], s3 v_cvt_f64_i32_e32 v[59:60], s2 s_load_b64 s[56:57], s[0:1], 0x60 s_getpc_b64 s[58:59] s_add_u32 s58, s58, _Z12cubic_interpRdS_dddddddd@rel32@lo+4 s_addc_u32 s59, s59, _Z12cubic_interpRdS_dddddddd@rel32@hi+12 v_max_f64 v[0:1], v[1:2], 0 v_max_f64 v[2:3], v[3:4], 0 v_max_f64 v[4:5], v[5:6], 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[42:43] v_cmp_gt_f64_e64 s2, v[2:3], v[59:60] s_delay_alu instid0(VALU_DEP_3) v_cmp_gt_f64_e64 s3, v[4:5], v[15:16] v_cndmask_b32_e32 v0, v0, v42, vcc_lo v_cvt_f64_i32_e32 v[7:8], v7 v_cndmask_b32_e32 v1, v1, v43, vcc_lo v_cndmask_b32_e64 v3, v3, v60, s2 v_cndmask_b32_e64 v5, v5, v16, s3 v_cndmask_b32_e64 v4, v4, v15, s3 v_cndmask_b32_e64 v2, v2, v59, s2 s_clause 0x1 s_load_b256 s[36:43], s[0:1], 0x20 s_load_b64 s[2:3], s[0:1], 0x78 v_cvt_i32_f64_e32 v44, v[4:5] v_cvt_i32_f64_e32 v45, v[2:3] v_max_f64 v[6:7], v[7:8], 0 v_max_f64 v[8:9], v[9:10], 0 v_max_f64 v[10:11], v[11:12], 0 v_max_f64 v[12:13], v[13:14], 0 v_cvt_i32_f64_e32 v14, v[0:1] v_cmp_gt_f64_e64 s4, v[6:7], v[15:16] v_cmp_gt_f64_e64 s5, v[8:9], v[15:16] v_cmp_gt_f64_e64 s6, v[10:11], v[15:16] v_cmp_gt_f64_e64 s7, v[12:13], v[15:16] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v7, v7, v16, s4 v_cndmask_b32_e64 v6, v6, v15, s4 v_cndmask_b32_e64 v11, v11, v16, s6 s_delay_alu instid0(VALU_DEP_4) v_cndmask_b32_e64 v1, v13, v16, s7 v_cndmask_b32_e64 v0, v12, v15, s7 v_cndmask_b32_e64 v10, v10, v15, s6 v_cndmask_b32_e64 v9, v9, v16, s5 v_cndmask_b32_e64 v8, v8, v15, s5 v_cvt_i32_f64_e32 v4, v[6:7] v_cvt_i32_f64_e32 v0, v[0:1] v_cvt_i32_f64_e32 v6, v[10:11] v_mul_lo_u32 v1, v14, s35 v_cvt_i32_f64_e32 v5, v[8:9] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, v1, v44 v_mul_lo_u32 v61, v2, s34 v_add_nc_u32_e32 v3, v1, v4 v_add_nc_u32_e32 v4, v1, v0 v_add_nc_u32_e32 v6, v1, v6 v_add_nc_u32_e32 v8, v1, v5 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_mad_u64_u32 v[0:1], null, v3, s34, v[45:46] v_mad_u64_u32 v[2:3], null, v4, s34, v[45:46] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_mad_u64_u32 v[4:5], null, v6, s34, v[45:46] v_mad_u64_u32 v[6:7], null, v8, s34, v[45:46] v_add_nc_u32_e32 v8, v61, v45 v_ashrrev_i32_e32 v1, 31, v0 v_ashrrev_i32_e32 v3, 31, v2 v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_ashrrev_i32_e32 v9, 31, v8 v_ashrrev_i32_e32 v7, 31, v6 v_lshlrev_b64 v[2:3], 3, v[2:3] v_lshlrev_b64 v[0:1], 3, v[0:1] v_lshlrev_b64 v[4:5], 3, v[4:5] v_lshlrev_b64 v[46:47], 3, v[8:9] v_lshlrev_b64 v[6:7], 3, v[6:7] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s56, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s57, v3, vcc_lo v_add_co_u32 v4, vcc_lo, s56, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s57, v5, vcc_lo v_add_co_u32 v6, vcc_lo, s56, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s57, v7, vcc_lo v_add_co_u32 v8, vcc_lo, s40, v46 v_add_co_ci_u32_e32 v9, vcc_lo, s41, v47, vcc_lo v_add_co_u32 v14, vcc_lo, s42, v46 v_add_co_ci_u32_e32 v15, vcc_lo, s43, v47, vcc_lo v_add_co_u32 v56, vcc_lo, s56, v46 v_add_co_ci_u32_e32 v57, vcc_lo, s57, v47, vcc_lo v_add_co_u32 v0, vcc_lo, s56, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s57, v1, vcc_lo s_clause 0x2 global_load_b64 v[10:11], v[2:3], off global_load_b64 v[12:13], v[4:5], off global_load_b64 v[18:19], v[6:7], off global_load_b64 v[4:5], v[8:9], off v_mov_b32_e32 v9, s3 global_load_b64 v[6:7], v[14:15], off s_clause 0x1 global_load_b64 v[14:15], v[56:57], off global_load_b64 v[16:17], v[0:1], off s_clause 0x1 s_load_b256 s[48:55], s[0:1], 0x0 s_load_b256 s[40:47], s[0:1], 0x40 v_mov_b32_e32 v8, s2 s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s48, v46 v_add_co_ci_u32_e32 v1, vcc_lo, s49, v47, vcc_lo v_add_co_u32 v2, vcc_lo, s50, v46 v_add_co_ci_u32_e32 v3, vcc_lo, s51, v47, vcc_lo s_mov_b64 s[48:49], s[0:1] s_swappc_b64 s[30:31], s[58:59] v_add_nc_u32_e32 v0, -2, v58 v_add_nc_u32_e32 v2, -1, v58 v_add_nc_u32_e32 v4, 1, v58 v_add_nc_u32_e32 v6, 2, v58 global_load_b64 v[14:15], v[56:57], off v_cvt_f64_i32_e32 v[0:1], v0 v_cvt_f64_i32_e32 v[2:3], v2 v_cvt_f64_i32_e32 v[4:5], v4 v_cvt_f64_i32_e32 v[6:7], v6 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_max_f64 v[0:1], v[0:1], 0 v_max_f64 v[2:3], v[2:3], 0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_max_f64 v[4:5], v[4:5], 0 v_max_f64 v[6:7], v[6:7], 0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[59:60] v_cmp_gt_f64_e64 s0, v[2:3], v[59:60] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_gt_f64_e64 s1, v[4:5], v[59:60] v_cmp_gt_f64_e64 s2, v[6:7], v[59:60] v_dual_cndmask_b32 v1, v1, v60 :: v_dual_cndmask_b32 v0, v0, v59 s_delay_alu instid0(VALU_DEP_4) v_cndmask_b32_e64 v3, v3, v60, s0 v_cndmask_b32_e64 v2, v2, v59, s0 v_cndmask_b32_e64 v5, v5, v60, s1 v_cndmask_b32_e64 v4, v4, v59, s1 v_cvt_i32_f64_e32 v8, v[0:1] v_cndmask_b32_e64 v7, v7, v60, s2 v_cvt_i32_f64_e32 v9, v[2:3] v_cndmask_b32_e64 v6, v6, v59, s2 v_cvt_i32_f64_e32 v4, v[4:5] v_add_co_u32 v0, vcc_lo, s40, v46 v_add_co_ci_u32_e32 v1, vcc_lo, s41, v47, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_cvt_i32_f64_e32 v5, v[6:7] v_add_co_u32 v2, vcc_lo, s42, v46 v_add_co_ci_u32_e32 v3, vcc_lo, s43, v47, vcc_lo s_load_b64 s[0:1], s[48:49], 0x80 v_add_nc_u32_e32 v6, v61, v8 v_add_nc_u32_e32 v8, v61, v9 v_add_nc_u32_e32 v10, v61, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_ashrrev_i32_e32 v7, 31, v6 v_ashrrev_i32_e32 v9, 31, v8 v_add_nc_u32_e32 v12, v61, v5 global_load_b64 v[4:5], v[0:1], off v_lshlrev_b64 v[0:1], 3, v[6:7] v_ashrrev_i32_e32 v11, 31, v10 global_load_b64 v[6:7], v[2:3], off v_lshlrev_b64 v[2:3], 3, v[8:9] v_ashrrev_i32_e32 v13, 31, v12 v_lshlrev_b64 v[8:9], 3, v[10:11] v_add_co_u32 v0, vcc_lo, s56, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s57, v1, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_lshlrev_b64 v[12:13], 3, v[12:13] v_add_co_u32 v2, vcc_lo, s56, v2 global_load_b64 v[10:11], v[0:1], off v_add_co_ci_u32_e32 v3, vcc_lo, s57, v3, vcc_lo v_add_co_u32 v8, vcc_lo, s56, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s57, v9, vcc_lo v_add_co_u32 v0, vcc_lo, s56, v12 v_add_co_ci_u32_e32 v1, vcc_lo, s57, v13, vcc_lo s_clause 0x2 global_load_b64 v[12:13], v[2:3], off global_load_b64 v[16:17], v[8:9], off global_load_b64 v[18:19], v[0:1], off v_add_co_u32 v0, vcc_lo, s52, v46 v_add_co_ci_u32_e32 v1, vcc_lo, s53, v47, vcc_lo v_add_co_u32 v2, vcc_lo, s54, v46 v_add_co_ci_u32_e32 v3, vcc_lo, s55, v47, vcc_lo s_waitcnt lgkmcnt(0) v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v9, s1 s_swappc_b64 s[30:31], s[58:59] v_add_nc_u32_e32 v0, 1, v41 v_add_nc_u32_e32 v2, 2, v41 v_add_nc_u32_e32 v4, -2, v41 v_add_nc_u32_e32 v6, -1, v41 global_load_b64 v[14:15], v[56:57], off v_cvt_f64_i32_e32 v[0:1], v0 v_cvt_f64_i32_e32 v[2:3], v2 v_cvt_f64_i32_e32 v[4:5], v4 v_cvt_f64_i32_e32 v[6:7], v6 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_max_f64 v[0:1], v[0:1], 0 v_max_f64 v[2:3], v[2:3], 0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_max_f64 v[4:5], v[4:5], 0 v_max_f64 v[6:7], v[6:7], 0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[42:43] v_cmp_gt_f64_e64 s0, v[2:3], v[42:43] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_gt_f64_e64 s1, v[4:5], v[42:43] v_cmp_gt_f64_e64 s2, v[6:7], v[42:43] v_dual_cndmask_b32 v1, v1, v43 :: v_dual_cndmask_b32 v0, v0, v42 s_delay_alu instid0(VALU_DEP_4) v_cndmask_b32_e64 v3, v3, v43, s0 v_cndmask_b32_e64 v2, v2, v42, s0 v_cndmask_b32_e64 v5, v5, v43, s1 v_cndmask_b32_e64 v4, v4, v42, s1 v_cndmask_b32_e64 v7, v7, v43, s2 v_cvt_i32_f64_e32 v8, v[0:1] v_cndmask_b32_e64 v6, v6, v42, s2 v_cvt_i32_f64_e32 v9, v[2:3] v_cvt_i32_f64_e32 v10, v[4:5] v_add_co_u32 v0, vcc_lo, s44, v46 s_delay_alu instid0(VALU_DEP_4) v_cvt_i32_f64_e32 v7, v[6:7] v_add_co_ci_u32_e32 v1, vcc_lo, s45, v47, vcc_lo s_load_b64 s[0:1], s[48:49], 0x88 v_mad_u64_u32 v[2:3], null, v8, s35, v[44:45] v_mad_u64_u32 v[3:4], null, v9, s35, v[44:45] v_mad_u64_u32 v[4:5], null, v10, s35, v[44:45] v_mad_u64_u32 v[5:6], null, v7, s35, v[44:45] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_mad_u64_u32 v[8:9], null, v2, s34, v[45:46] v_mad_u64_u32 v[10:11], null, v3, s34, v[45:46] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_mad_u64_u32 v[2:3], null, v4, s34, v[45:46] v_mad_u64_u32 v[12:13], null, v5, s34, v[45:46] global_load_b64 v[4:5], v[0:1], off v_ashrrev_i32_e32 v9, 31, v8 v_add_co_u32 v6, vcc_lo, s46, v46 v_ashrrev_i32_e32 v3, 31, v2 v_ashrrev_i32_e32 v11, 31, v10 v_ashrrev_i32_e32 v13, 31, v12 v_add_co_ci_u32_e32 v7, vcc_lo, s47, v47, vcc_lo s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_lshlrev_b64 v[0:1], 3, v[2:3] v_lshlrev_b64 v[8:9], 3, v[8:9] v_lshlrev_b64 v[2:3], 3, v[12:13] v_lshlrev_b64 v[12:13], 3, v[10:11] global_load_b64 v[6:7], v[6:7], off v_add_co_u32 v0, vcc_lo, s56, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s57, v1, vcc_lo v_add_co_u32 v2, vcc_lo, s56, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s57, v3, vcc_lo v_add_co_u32 v8, vcc_lo, s56, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s57, v9, vcc_lo global_load_b64 v[10:11], v[0:1], off v_add_co_u32 v0, vcc_lo, s56, v12 v_add_co_ci_u32_e32 v1, vcc_lo, s57, v13, vcc_lo s_clause 0x2 global_load_b64 v[12:13], v[2:3], off global_load_b64 v[16:17], v[8:9], off global_load_b64 v[18:19], v[0:1], off s_waitcnt lgkmcnt(0) v_mov_b32_e32 v9, s1 v_add_co_u32 v0, vcc_lo, s36, v46 v_add_co_ci_u32_e32 v1, vcc_lo, s37, v47, vcc_lo v_add_co_u32 v2, vcc_lo, s38, v46 v_add_co_ci_u32_e32 v3, vcc_lo, s39, v47, vcc_lo v_mov_b32_e32 v8, s0 s_swappc_b64 s[30:31], s[58:59] .LBB3_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 8 .amdhsa_kernarg_size 408 .amdhsa_user_sgpr_count 13 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 1 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 1 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 130 .amdhsa_next_free_sgpr 60 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end3: .size _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end3-_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1828 ; NumSgprs: 62 ; NumVgprs: 130 ; ScratchSize: 8 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 7 ; VGPRBlocks: 16 ; NumSGPRsForWavesPerEU: 62 ; NumVGPRsForWavesPerEU: 130 ; Occupancy: 10 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1 ; COMPUTE_PGM_RSRC2:USER_SGPR: 13 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2 .text .protected _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi ; -- Begin function _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .globl _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .p2align 8 .type _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@function _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi: ; @_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi ; %bb.0: s_clause 0x2 s_load_b64 s[2:3], s[0:1], 0xcc s_load_b64 s[64:65], s[0:1], 0x90 s_load_b32 s4, s[0:1], 0x98 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v4, v0, 10, 10 v_bfe_u32 v0, v0, 20, 10 s_mov_b32 s32, 0 s_waitcnt lgkmcnt(0) s_and_b32 s5, s2, 0xffff s_lshr_b32 s2, s2, 16 s_and_b32 s3, s3, 0xffff v_mad_u64_u32 v[75:76], null, s13, s5, v[1:2] v_mad_u64_u32 v[2:3], null, s14, s2, v[4:5] v_mad_u64_u32 v[70:71], null, s15, s3, v[0:1] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_gt_i32_e32 vcc_lo, s64, v75 v_cmp_gt_i32_e64 s2, s65, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e64 s3, s4, v70 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_b32 s2, s2, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB4_44 ; %bb.1: v_cvt_f64_i32_e32 v[0:1], v70 v_cvt_f64_i32_e32 v[3:4], v2 v_cvt_f64_i32_e32 v[8:9], v75 s_add_i32 s4, s4, -1 s_add_i32 s2, s65, -1 v_cvt_f64_i32_e32 v[71:72], s4 v_cvt_f64_i32_e32 v[6:7], s2 s_add_i32 s2, s64, -1 v_mov_b32_e32 v10, 0 v_cvt_f64_i32_e32 v[76:77], s2 s_mov_b32 s63, exec_lo s_load_b64 s[70:71], s[0:1], 0xa0 v_mov_b32_e32 v11, 0 v_max_f64 v[0:1], v[0:1], 0 v_max_f64 v[3:4], v[3:4], 0 v_max_f64 v[8:9], v[8:9], 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[71:72] v_cmp_gt_f64_e64 s2, v[3:4], v[6:7] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f64_e64 s3, v[8:9], v[76:77] v_dual_cndmask_b32 v1, v1, v72 :: v_dual_cndmask_b32 v0, v0, v71 v_cvt_i32_f64_e32 v5, v[0:1] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cndmask_b32_e64 v1, v4, v7, s2 v_cndmask_b32_e64 v0, v3, v6, s2 v_cvt_i32_f64_e32 v74, v[0:1] v_cndmask_b32_e64 v1, v9, v77, s3 v_cndmask_b32_e64 v0, v8, v76, s3 s_load_b64 s[2:3], s[0:1], 0x30 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cvt_i32_f64_e32 v73, v[0:1] v_mul_lo_u32 v3, v5, s65 v_add_nc_u32_e32 v0, v3, v74 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v47, v0, s64 v_add_nc_u32_e32 v66, v47, v73 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v67, 31, v66 v_lshlrev_b64 v[64:65], 3, v[66:67] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s2, v64 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v65, vcc_lo s_mov_b32 s3, 0x3eb0c6f7 s_mov_b32 s2, 0xa0b5ed8d global_load_b64 v[0:1], v[0:1], off v_mul_f64 v[8:9], s[70:71], s[2:3] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_cmpx_nlt_f64_e32 v[0:1], v[8:9] s_cbranch_execz .LBB4_43 ; %bb.2: s_load_b64 s[2:3], s[0:1], 0x38 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_mov_b32 s72, exec_lo s_waitcnt lgkmcnt(0) v_add_co_u32 v4, vcc_lo, s2, v64 v_add_co_ci_u32_e32 v5, vcc_lo, s3, v65, vcc_lo global_load_b64 v[4:5], v[4:5], off s_waitcnt vmcnt(0) v_cmpx_nlt_f64_e32 v[4:5], v[8:9] s_cbranch_execz .LBB4_42 ; %bb.3: s_load_b64 s[2:3], s[0:1], 0x40 v_lshlrev_b64 v[12:13], 3, v[66:67] s_mov_b32 s73, exec_lo s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, s2, v12 v_add_co_ci_u32_e32 v11, vcc_lo, s3, v13, vcc_lo global_load_b64 v[56:57], v[10:11], off v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_waitcnt vmcnt(0) v_cmpx_nlt_f64_e32 v[56:57], v[8:9] s_cbranch_execz .LBB4_41 ; %bb.4: s_load_b64 s[2:3], s[0:1], 0x48 s_mov_b32 s74, exec_lo s_waitcnt lgkmcnt(0) v_add_co_u32 v10, vcc_lo, s2, v12 v_add_co_ci_u32_e32 v11, vcc_lo, s3, v13, vcc_lo global_load_b64 v[58:59], v[10:11], off v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_waitcnt vmcnt(0) v_cmpx_nlt_f64_e32 v[58:59], v[8:9] s_cbranch_execz .LBB4_40 ; %bb.5: s_load_b64 s[2:3], s[0:1], 0x50 v_lshlrev_b64 v[12:13], 3, v[66:67] s_mov_b32 s75, exec_lo s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v10, vcc_lo, s2, v12 v_add_co_ci_u32_e32 v11, vcc_lo, s3, v13, vcc_lo global_load_b64 v[60:61], v[10:11], off v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_waitcnt vmcnt(0) v_cmpx_nlt_f64_e32 v[60:61], v[8:9] s_cbranch_execz .LBB4_39 ; %bb.6: s_load_b64 s[2:3], s[0:1], 0x58 s_mov_b32 s76, exec_lo s_waitcnt lgkmcnt(0) v_add_co_u32 v10, vcc_lo, s2, v12 v_add_co_ci_u32_e32 v11, vcc_lo, s3, v13, vcc_lo global_load_b64 v[62:63], v[10:11], off v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_waitcnt vmcnt(0) v_cmpx_nlt_f64_e32 v[62:63], v[8:9] s_cbranch_execz .LBB4_38 ; %bb.7: v_add_nc_u32_e32 v8, 1, v2 v_add_nc_u32_e32 v10, 2, v2 v_add_nc_u32_e32 v12, 3, v2 v_add_nc_u32_e32 v14, -1, v2 v_add_nc_u32_e32 v16, -2, v2 v_add_nc_u32_e32 v2, -3, v2 v_cvt_f64_i32_e32 v[8:9], v8 v_cvt_f64_i32_e32 v[10:11], v10 v_cvt_f64_i32_e32 v[12:13], v12 v_cvt_f64_i32_e32 v[14:15], v14 v_cvt_f64_i32_e32 v[16:17], v16 v_cvt_f64_i32_e32 v[18:19], v2 s_load_b64 s[68:69], s[0:1], 0x10 v_cmp_ngt_f64_e64 s62, s[70:71], v[0:1] v_cmp_ngt_f64_e64 s33, s[70:71], v[4:5] ; implicit-def: $vgpr43_vgpr44 ; implicit-def: $vgpr41_vgpr42 v_max_f64 v[8:9], v[8:9], 0 v_max_f64 v[10:11], v[10:11], 0 v_max_f64 v[12:13], v[12:13], 0 v_max_f64 v[14:15], v[14:15], 0 v_max_f64 v[16:17], v[16:17], 0 v_max_f64 v[18:19], v[18:19], 0 v_cmp_gt_f64_e32 vcc_lo, v[8:9], v[6:7] v_cmp_gt_f64_e64 s2, v[10:11], v[6:7] v_cmp_gt_f64_e64 s3, v[12:13], v[6:7] v_cmp_gt_f64_e64 s4, v[14:15], v[6:7] v_cmp_gt_f64_e64 s5, v[16:17], v[6:7] v_cmp_gt_f64_e64 s6, v[18:19], v[6:7] v_cndmask_b32_e32 v9, v9, v7, vcc_lo v_cndmask_b32_e64 v11, v11, v7, s2 v_cndmask_b32_e64 v13, v13, v7, s3 v_cndmask_b32_e64 v15, v15, v7, s4 v_cndmask_b32_e64 v17, v17, v7, s5 v_cndmask_b32_e64 v7, v19, v7, s6 v_cndmask_b32_e32 v8, v8, v6, vcc_lo v_cndmask_b32_e64 v10, v10, v6, s2 v_cndmask_b32_e64 v12, v12, v6, s3 v_cndmask_b32_e64 v14, v14, v6, s4 v_cndmask_b32_e64 v16, v16, v6, s5 v_cndmask_b32_e64 v6, v18, v6, s6 v_cvt_i32_f64_e32 v2, v[8:9] v_cvt_i32_f64_e32 v9, v[12:13] v_cvt_i32_f64_e32 v8, v[10:11] v_cvt_i32_f64_e32 v10, v[14:15] v_cvt_i32_f64_e32 v12, v[6:7] v_cvt_i32_f64_e32 v11, v[16:17] v_lshlrev_b64 v[6:7], 3, v[66:67] s_and_b32 s2, s62, s33 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, s68, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s69, v7, vcc_lo v_add_nc_u32_e32 v13, v3, v2 v_add_nc_u32_e32 v18, v3, v9 v_add_nc_u32_e32 v14, v3, v8 v_add_nc_u32_e32 v15, v3, v10 v_add_nc_u32_e32 v17, v3, v12 v_add_nc_u32_e32 v16, v3, v11 v_mad_u64_u32 v[2:3], null, v13, s64, v[73:74] v_mad_u64_u32 v[8:9], null, v14, s64, v[73:74] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_mad_u64_u32 v[12:13], null, v17, s64, v[73:74] v_mad_u64_u32 v[10:11], null, v15, s64, v[73:74] v_mad_u64_u32 v[14:15], null, v16, s64, v[73:74] v_mad_u64_u32 v[16:17], null, v18, s64, v[73:74] v_ashrrev_i32_e32 v13, 31, v12 v_ashrrev_i32_e32 v3, 31, v2 v_ashrrev_i32_e32 v11, 31, v10 v_ashrrev_i32_e32 v9, 31, v8 v_ashrrev_i32_e32 v15, 31, v14 v_lshlrev_b64 v[12:13], 3, v[12:13] v_lshlrev_b64 v[2:3], 3, v[2:3] v_lshlrev_b64 v[10:11], 3, v[10:11] v_ashrrev_i32_e32 v17, 31, v16 v_lshlrev_b64 v[14:15], 3, v[14:15] v_lshlrev_b64 v[8:9], 3, v[8:9] v_add_co_u32 v12, vcc_lo, s68, v12 v_add_co_ci_u32_e32 v13, vcc_lo, s69, v13, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v14, vcc_lo, s68, v14 v_add_co_ci_u32_e32 v15, vcc_lo, s69, v15, vcc_lo v_add_co_u32 v10, vcc_lo, s68, v10 v_add_co_ci_u32_e32 v11, vcc_lo, s69, v11, vcc_lo v_lshlrev_b64 v[16:17], 3, v[16:17] v_add_co_u32 v2, vcc_lo, s68, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s69, v3, vcc_lo v_add_co_u32 v8, vcc_lo, s68, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s69, v9, vcc_lo v_add_co_u32 v16, vcc_lo, s68, v16 v_add_co_ci_u32_e32 v17, vcc_lo, s69, v17, vcc_lo s_clause 0x6 global_load_b64 v[68:69], v[6:7], off global_load_b64 v[18:19], v[12:13], off global_load_b64 v[22:23], v[14:15], off global_load_b64 v[20:21], v[10:11], off global_load_b64 v[6:7], v[2:3], off global_load_b64 v[12:13], v[8:9], off global_load_b64 v[10:11], v[16:17], off s_and_saveexec_b32 s3, s2 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s77, exec_lo, s3 s_mov_b64 s[66:67], s[0:1] s_cbranch_execz .LBB4_9 ; %bb.8: s_waitcnt vmcnt(4) v_add_f64 v[0:1], v[22:23], -v[18:19] s_waitcnt vmcnt(3) v_add_f64 v[2:3], v[20:21], -v[22:23] v_add_f64 v[4:5], v[68:69], -v[20:21] s_waitcnt vmcnt(2) v_add_f64 v[8:9], v[6:7], -v[68:69] s_waitcnt vmcnt(1) v_add_f64 v[6:7], v[12:13], -v[6:7] s_waitcnt vmcnt(0) v_add_f64 v[10:11], v[10:11], -v[12:13] s_getpc_b64 s[78:79] s_add_u32 s78, s78, _Z24weno_onesided_derivativeddddd@rel32@lo+4 s_addc_u32 s79, s79, _Z24weno_onesided_derivativeddddd@rel32@hi+12 v_div_scale_f64 v[12:13], null, s[70:71], s[70:71], v[0:1] v_div_scale_f64 v[14:15], null, s[70:71], s[70:71], v[2:3] v_div_scale_f64 v[16:17], null, s[70:71], s[70:71], v[4:5] v_div_scale_f64 v[18:19], null, s[70:71], s[70:71], v[8:9] v_div_scale_f64 v[20:21], null, s[70:71], s[70:71], v[6:7] v_div_scale_f64 v[22:23], null, s[70:71], s[70:71], v[10:11] v_div_scale_f64 v[50:51], vcc_lo, v[0:1], s[70:71], v[0:1] v_rcp_f64_e32 v[24:25], v[12:13] v_rcp_f64_e32 v[26:27], v[14:15] v_rcp_f64_e32 v[28:29], v[16:17] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_rcp_f64_e32 v[30:31], v[18:19] v_rcp_f64_e32 v[32:33], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3) v_rcp_f64_e32 v[34:35], v[22:23] v_fma_f64 v[36:37], -v[12:13], v[24:25], 1.0 v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0 v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0 v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0 v_fma_f64 v[48:49], -v[22:23], v[34:35], 1.0 v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25] v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27] v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29] v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31] v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33] v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35] v_fma_f64 v[36:37], -v[12:13], v[24:25], 1.0 v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0 v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0 v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0 v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0 v_fma_f64 v[48:49], -v[22:23], v[34:35], 1.0 v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25] v_div_scale_f64 v[36:37], s0, v[2:3], s[70:71], v[2:3] v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27] v_div_scale_f64 v[38:39], s1, v[4:5], s[70:71], v[4:5] v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29] v_div_scale_f64 v[40:41], s2, v[8:9], s[70:71], v[8:9] v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31] v_div_scale_f64 v[42:43], s3, v[6:7], s[70:71], v[6:7] v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33] v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35] v_div_scale_f64 v[44:45], s4, v[10:11], s[70:71], v[10:11] v_mul_f64 v[48:49], v[50:51], v[24:25] v_mul_f64 v[52:53], v[36:37], v[26:27] v_mul_f64 v[54:55], v[38:39], v[28:29] v_mul_f64 v[78:79], v[40:41], v[30:31] v_mul_f64 v[80:81], v[42:43], v[32:33] v_mul_f64 v[82:83], v[44:45], v[34:35] v_fma_f64 v[12:13], -v[12:13], v[48:49], v[50:51] v_fma_f64 v[14:15], -v[14:15], v[52:53], v[36:37] v_fma_f64 v[16:17], -v[16:17], v[54:55], v[38:39] v_fma_f64 v[18:19], -v[18:19], v[78:79], v[40:41] v_fma_f64 v[20:21], -v[20:21], v[80:81], v[42:43] v_fma_f64 v[22:23], -v[22:23], v[82:83], v[44:45] v_div_fmas_f64 v[12:13], v[12:13], v[24:25], v[48:49] s_mov_b32 vcc_lo, s0 v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[52:53] s_mov_b32 vcc_lo, s1 v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[54:55] s_mov_b32 vcc_lo, s2 v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[78:79] s_mov_b32 vcc_lo, s3 v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[80:81] s_mov_b32 vcc_lo, s4 v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[82:83] v_div_fixup_f64 v[0:1], v[12:13], s[70:71], v[0:1] v_div_fixup_f64 v[43:44], v[14:15], s[70:71], v[2:3] v_div_fixup_f64 v[45:46], v[16:17], s[70:71], v[4:5] v_div_fixup_f64 v[50:51], v[18:19], s[70:71], v[8:9] v_div_fixup_f64 v[52:53], v[20:21], s[70:71], v[6:7] v_div_fixup_f64 v[54:55], v[22:23], s[70:71], v[10:11] v_dual_mov_b32 v2, v43 :: v_dual_mov_b32 v3, v44 v_dual_mov_b32 v4, v45 :: v_dual_mov_b32 v5, v46 v_dual_mov_b32 v6, v50 :: v_dual_mov_b32 v7, v51 v_dual_mov_b32 v8, v52 :: v_dual_mov_b32 v9, v53 s_swappc_b64 s[30:31], s[78:79] v_dual_mov_b32 v41, v0 :: v_dual_mov_b32 v42, v1 v_dual_mov_b32 v0, v54 :: v_dual_mov_b32 v1, v55 v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v3, v53 v_dual_mov_b32 v4, v50 :: v_dual_mov_b32 v5, v51 v_dual_mov_b32 v6, v45 :: v_dual_mov_b32 v7, v46 v_dual_mov_b32 v8, v43 :: v_dual_mov_b32 v9, v44 s_swappc_b64 s[30:31], s[78:79] v_dual_mov_b32 v43, v0 :: v_dual_mov_b32 v44, v1 s_mov_b64 s[0:1], s[66:67] ; implicit-def: $vgpr20_vgpr21 ; implicit-def: $vgpr22_vgpr23 ; implicit-def: $vgpr18_vgpr19 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $vgpr0_vgpr1 ; implicit-def: $vgpr6_vgpr7 ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $vgpr10_vgpr11 .LBB4_9: ; %Flow457 s_and_not1_saveexec_b32 s6, s77 s_cbranch_execz .LBB4_17 ; %bb.10: s_load_b128 s[8:11], s[0:1], 0x60 v_lshlrev_b64 v[2:3], 3, v[66:67] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v8, vcc_lo, s10, v2 v_add_co_ci_u32_e32 v9, vcc_lo, s11, v3, vcc_lo v_add_co_u32 v2, vcc_lo, s8, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo global_load_b64 v[30:31], v[8:9], off global_load_b64 v[24:25], v[2:3], off v_add_f64 v[8:9], s[70:71], s[70:71] v_dual_mov_b32 v2, s70 :: v_dual_mov_b32 v3, s71 s_and_saveexec_b32 s2, s62 s_cbranch_execz .LBB4_12 ; %bb.11: v_mul_f64 v[14:15], s[70:71], 0x40080000 v_dual_mov_b32 v0, s70 :: v_dual_mov_b32 v1, s71 s_delay_alu instid0(VALU_DEP_4) v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9 s_waitcnt vmcnt(0) v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 v_dual_mov_b32 v6, v12 :: v_dual_mov_b32 v7, v13 v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10 v_dual_mov_b32 v8, v14 :: v_dual_mov_b32 v9, v15 .LBB4_12: s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $vgpr10_vgpr11 ; implicit-def: $sgpr2_sgpr3 ; implicit-def: $sgpr4_sgpr5 s_and_saveexec_b32 s7, s33 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s7, exec_lo, s7 s_cbranch_execz .LBB4_14 ; %bb.13: s_mov_b32 s4, 0 s_waitcnt vmcnt(2) v_mul_f64 v[10:11], s[70:71], -2.0 s_mov_b32 s5, 0xc0080000 s_xor_b32 s3, s71, 0x80000000 s_mov_b32 s2, s70 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $vgpr30_vgpr31 .LBB4_14: ; %Flow454 s_or_saveexec_b32 s7, s7 v_dual_mov_b32 v15, s5 :: v_dual_mov_b32 v14, s4 v_dual_mov_b32 v17, s3 :: v_dual_mov_b32 v16, s2 s_waitcnt vmcnt(5) v_dual_mov_b32 v29, v21 :: v_dual_mov_b32 v28, v20 v_dual_mov_b32 v27, v23 :: v_dual_mov_b32 v26, v22 s_xor_b32 exec_lo, exec_lo, s7 s_cbranch_execz .LBB4_16 ; %bb.15: v_xor_b32_e32 v5, 0x80000000, v5 s_xor_b32 s3, s71, 0x80000000 s_mov_b32 s2, s70 s_waitcnt vmcnt(2) v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v11, s3 v_dual_mov_b32 v15, -2.0 :: v_dual_mov_b32 v10, s2 v_dual_mov_b32 v17, v5 :: v_dual_mov_b32 v16, v4 s_waitcnt vmcnt(1) v_dual_mov_b32 v28, v30 :: v_dual_mov_b32 v29, v31 v_dual_mov_b32 v27, v21 :: v_dual_mov_b32 v26, v20 v_dual_mov_b32 v18, v22 :: v_dual_mov_b32 v19, v23 .LBB4_16: ; %_Z14select_stencilRdS_S_S_S_S_S_S_S_S_S_S_S_S_dddddddddddddddd.exit.i s_or_b32 exec_lo, exec_lo, s7 s_waitcnt vmcnt(3) v_add_f64 v[4:5], v[12:13], -v[6:7] v_add_f64 v[12:13], v[8:9], -v[2:3] v_add_f64 v[18:19], v[26:27], -v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[20:21], null, v[12:13], v[12:13], v[4:5] v_rcp_f64_e32 v[22:23], v[20:21] s_waitcnt vmcnt(1) s_waitcnt_depctr 0xfff v_fma_f64 v[30:31], -v[20:21], v[22:23], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], v[22:23], v[30:31], v[22:23] v_fma_f64 v[30:31], -v[20:21], v[22:23], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[22:23], v[22:23], v[30:31], v[22:23] v_div_scale_f64 v[30:31], vcc_lo, v[4:5], v[12:13], v[4:5] v_mul_f64 v[32:33], v[30:31], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[20:21], v[32:33], v[30:31] v_div_fmas_f64 v[20:21], v[20:21], v[22:23], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_div_fixup_f64 v[20:21], v[20:21], v[12:13], v[4:5] s_waitcnt vmcnt(0) v_add_f64 v[4:5], v[6:7], -v[24:25] v_add_f64 v[6:7], v[2:3], -v[0:1] v_div_scale_f64 v[12:13], null, v[6:7], v[6:7], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[22:23], v[12:13] s_waitcnt_depctr 0xfff v_fma_f64 v[30:31], -v[12:13], v[22:23], 1.0 v_fma_f64 v[22:23], v[22:23], v[30:31], v[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], -v[12:13], v[22:23], 1.0 v_fma_f64 v[22:23], v[22:23], v[30:31], v[22:23] v_div_scale_f64 v[30:31], vcc_lo, v[4:5], v[6:7], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[32:33], v[30:31], v[22:23] v_fma_f64 v[12:13], -v[12:13], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[12:13], v[12:13], v[22:23], v[32:33] v_div_fixup_f64 v[22:23], v[12:13], v[6:7], v[4:5] v_add_f64 v[4:5], v[24:25], -v[68:69] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[20:21], v[20:21], -v[22:23] v_div_scale_f64 v[6:7], null, v[0:1], v[0:1], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[12:13], v[6:7] s_waitcnt_depctr 0xfff v_fma_f64 v[24:25], -v[6:7], v[12:13], 1.0 v_fma_f64 v[12:13], v[12:13], v[24:25], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], -v[6:7], v[12:13], 1.0 v_fma_f64 v[12:13], v[12:13], v[24:25], v[12:13] v_div_scale_f64 v[24:25], vcc_lo, v[4:5], v[0:1], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[30:31], v[24:25], v[12:13] v_fma_f64 v[6:7], -v[6:7], v[30:31], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fmas_f64 v[6:7], v[6:7], v[12:13], v[30:31] v_add_f64 v[12:13], v[68:69], -v[28:29] v_div_fixup_f64 v[4:5], v[6:7], v[0:1], v[4:5] v_add_f64 v[6:7], -v[16:17], 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[22:23], v[22:23], -v[4:5] v_div_scale_f64 v[24:25], null, v[6:7], v[6:7], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[30:31], v[24:25] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[24:25], v[30:31], 1.0 v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], -v[24:25], v[30:31], 1.0 v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[12:13], v[6:7], v[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[34:35], v[32:33], v[30:31] v_fma_f64 v[24:25], -v[24:25], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[24:25], v[24:25], v[30:31], v[34:35] v_div_fixup_f64 v[12:13], v[24:25], v[6:7], v[12:13] v_add_f64 v[24:25], v[28:29], -v[26:27] v_add_f64 v[28:29], v[16:17], -v[10:11] v_fma_f64 v[26:27], -v[14:15], s[70:71], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[30:31], null, v[28:29], v[28:29], v[24:25] v_rcp_f64_e32 v[32:33], v[30:31] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[24:25], v[28:29], v[24:25] v_mul_f64 v[36:37], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], -v[30:31], v[36:37], v[34:35] v_div_fmas_f64 v[30:31], v[30:31], v[32:33], v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[24:25], v[30:31], v[28:29], v[24:25] v_div_scale_f64 v[28:29], null, v[26:27], v[26:27], v[18:19] v_rcp_f64_e32 v[30:31], v[28:29] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[18:19], v[26:27], v[18:19] v_mul_f64 v[34:35], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], -v[28:29], v[34:35], v[32:33] v_div_fmas_f64 v[28:29], v[28:29], v[30:31], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[18:19], v[28:29], v[26:27], v[18:19] v_add_f64 v[26:27], v[8:9], -v[0:1] v_add_f64 v[18:19], v[24:25], -v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[28:29], null, v[26:27], v[26:27], v[20:21] v_rcp_f64_e32 v[30:31], v[28:29] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[20:21], v[26:27], v[20:21] v_mul_f64 v[34:35], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], -v[28:29], v[34:35], v[32:33] v_div_fmas_f64 v[28:29], v[28:29], v[30:31], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[20:21], v[28:29], v[26:27], v[20:21] v_div_scale_f64 v[26:27], null, v[2:3], v[2:3], v[22:23] v_rcp_f64_e32 v[28:29], v[26:27] s_waitcnt_depctr 0xfff v_fma_f64 v[30:31], -v[26:27], v[28:29], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] v_fma_f64 v[30:31], -v[26:27], v[28:29], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] v_div_scale_f64 v[30:31], vcc_lo, v[22:23], v[2:3], v[22:23] v_mul_f64 v[32:33], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], -v[26:27], v[32:33], v[30:31] v_div_fmas_f64 v[26:27], v[26:27], v[28:29], v[32:33] v_add_f64 v[28:29], v[0:1], -v[16:17] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[22:23], v[26:27], v[2:3], v[22:23] v_add_f64 v[26:27], v[4:5], -v[12:13] v_add_f64 v[20:21], v[20:21], -v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[30:31], null, v[28:29], v[28:29], v[26:27] v_rcp_f64_e32 v[32:33], v[30:31] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[26:27], v[28:29], v[26:27] v_mul_f64 v[36:37], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], -v[30:31], v[36:37], v[34:35] v_div_fmas_f64 v[30:31], v[30:31], v[32:33], v[36:37] s_delay_alu instid0(VALU_DEP_1) v_div_fixup_f64 v[26:27], v[30:31], v[28:29], v[26:27] v_add_f64 v[28:29], v[12:13], -v[24:25] v_add_f64 v[30:31], -v[10:11], 0 v_fma_f64 v[24:25], -v[14:15], s[70:71], v[16:17] v_add_f64 v[16:17], v[2:3], -v[16:17] v_add_f64 v[10:11], v[0:1], -v[10:11] v_fma_f64 v[14:15], -v[14:15], s[70:71], 0 v_add_f64 v[0:1], -v[0:1], 0 v_add_f64 v[2:3], -v[2:3], 0 v_div_scale_f64 v[32:33], null, v[30:31], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[2:3], v[0:1], v[2:3] v_rcp_f64_e32 v[34:35], v[32:33] s_waitcnt_depctr 0xfff v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35] v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35] v_div_scale_f64 v[36:37], vcc_lo, v[28:29], v[30:31], v[28:29] v_mul_f64 v[38:39], v[36:37], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], -v[32:33], v[38:39], v[36:37] v_div_fmas_f64 v[32:33], v[32:33], v[34:35], v[38:39] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[28:29], v[32:33], v[30:31], v[28:29] v_div_scale_f64 v[32:33], null, v[24:25], v[24:25], v[18:19] v_rcp_f64_e32 v[34:35], v[32:33] s_waitcnt_depctr 0xfff v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35] v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35] v_div_scale_f64 v[36:37], vcc_lo, v[18:19], v[24:25], v[18:19] v_mul_f64 v[38:39], v[36:37], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], -v[32:33], v[38:39], v[36:37] v_div_fmas_f64 v[32:33], v[32:33], v[34:35], v[38:39] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[18:19], v[32:33], v[24:25], v[18:19] v_div_scale_f64 v[24:25], null, v[8:9], v[8:9], v[20:21] v_add_f64 v[18:19], v[28:29], -v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[32:33], v[24:25] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[24:25], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], -v[24:25], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[20:21], v[8:9], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[36:37], v[34:35], v[32:33] v_fma_f64 v[24:25], -v[24:25], v[36:37], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[24:25], v[24:25], v[32:33], v[36:37] v_div_fixup_f64 v[8:9], v[24:25], v[8:9], v[20:21] v_add_f64 v[20:21], v[22:23], -v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[24:25], null, v[16:17], v[16:17], v[20:21] v_rcp_f64_e32 v[32:33], v[24:25] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[24:25], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_fma_f64 v[34:35], -v[24:25], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[20:21], v[16:17], v[20:21] v_mul_f64 v[36:37], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], -v[24:25], v[36:37], v[34:35] v_div_fmas_f64 v[24:25], v[24:25], v[32:33], v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[16:17], v[24:25], v[16:17], v[20:21] v_add_f64 v[20:21], v[26:27], -v[28:29] v_cmp_lt_f64_e64 s2, |v[16:17]|, |v[8:9]| s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_div_scale_f64 v[24:25], null, v[10:11], v[10:11], v[20:21] v_cndmask_b32_e64 v9, v9, v17, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_rcp_f64_e32 v[32:33], v[24:25] v_cndmask_b32_e64 v8, v8, v16, s2 v_cmp_lt_f64_e64 s2, |v[26:27]|, |v[22:23]| v_mul_f64 v[2:3], v[2:3], v[8:9] v_mul_f64 v[8:9], v[26:27], v[28:29] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[24:25], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_fma_f64 v[34:35], -v[24:25], v[32:33], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[20:21], v[10:11], v[20:21] v_mul_f64 v[36:37], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], -v[24:25], v[36:37], v[34:35] v_div_fmas_f64 v[24:25], v[24:25], v[32:33], v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[10:11], v[24:25], v[10:11], v[20:21] v_div_scale_f64 v[20:21], null, v[14:15], v[14:15], v[18:19] v_rcp_f64_e32 v[24:25], v[20:21] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[20:21], v[24:25], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[24:25], v[32:33], v[24:25] v_fma_f64 v[32:33], -v[20:21], v[24:25], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], v[24:25], v[32:33], v[24:25] v_div_scale_f64 v[32:33], vcc_lo, v[18:19], v[14:15], v[18:19] v_mul_f64 v[34:35], v[32:33], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[20:21], v[34:35], v[32:33] v_div_fmas_f64 v[20:21], v[20:21], v[24:25], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[14:15], v[20:21], v[14:15], v[18:19] v_mul_f64 v[18:19], v[6:7], v[30:31] v_cmp_lt_f64_e64 vcc_lo, |v[10:11]|, |v[14:15]| v_dual_cndmask_b32 v15, v15, v11 :: v_dual_cndmask_b32 v14, v14, v10 v_cmp_lt_f64_e64 vcc_lo, |v[10:11]|, |v[16:17]| s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_mul_f64 v[14:15], v[18:19], v[14:15] v_mul_f64 v[18:19], v[0:1], v[6:7] v_dual_cndmask_b32 v11, v17, v11 :: v_dual_cndmask_b32 v10, v16, v10 v_cmp_lt_f64_e64 vcc_lo, |v[28:29]|, |v[26:27]| v_mul_f64 v[10:11], v[18:19], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_dual_cndmask_b32 v15, v11, v15 :: v_dual_cndmask_b32 v14, v10, v14 v_cndmask_b32_e64 v3, v3, v11, s2 v_cndmask_b32_e64 v2, v2, v10, s2 v_dual_cndmask_b32 v10, v26, v28 :: v_dual_cndmask_b32 v11, v27, v29 v_cmp_ngt_f64_e32 vcc_lo, 0, v[8:9] v_dual_cndmask_b32 v9, 0, v11 :: v_dual_cndmask_b32 v8, 0, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[6:7], v[6:7], v[8:9], v[12:13] v_cndmask_b32_e64 v8, v22, v26, s2 v_cndmask_b32_e64 v9, v23, v27, s2 v_add_f64 v[41:42], v[6:7], v[14:15] v_mul_f64 v[6:7], v[22:23], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_ngt_f64_e32 vcc_lo, 0, v[6:7] v_dual_cndmask_b32 v7, 0, v9 :: v_dual_cndmask_b32 v6, 0, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[0:1], v[0:1], v[6:7], v[4:5] v_add_f64 v[43:44], v[0:1], v[2:3] .LBB4_17: ; %Flow458 s_or_b32 exec_lo, exec_lo, s6 v_add_nc_u32_e32 v0, 1, v75 v_add_nc_u32_e32 v4, -3, v75 s_waitcnt vmcnt(2) v_add_nc_u32_e32 v6, -2, v75 v_add_nc_u32_e32 v2, 2, v75 v_add_nc_u32_e32 v8, -1, v75 v_cvt_f64_i32_e32 v[0:1], v0 v_cvt_f64_i32_e32 v[4:5], v4 v_cvt_f64_i32_e32 v[6:7], v6 v_cvt_f64_i32_e32 v[2:3], v2 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v10, 3, v75 v_cvt_f64_i32_e32 v[8:9], v8 s_load_b64 s[70:71], s[0:1], 0xa8 ; implicit-def: $vgpr50_vgpr51 ; implicit-def: $vgpr45_vgpr46 s_delay_alu instid0(VALU_DEP_2) v_cvt_f64_i32_e32 v[10:11], v10 s_waitcnt lgkmcnt(0) v_cmp_ngt_f64_e64 s62, s[70:71], v[56:57] v_cmp_ngt_f64_e64 s33, s[70:71], v[58:59] v_max_f64 v[0:1], v[0:1], 0 v_max_f64 v[4:5], v[4:5], 0 v_max_f64 v[6:7], v[6:7], 0 v_max_f64 v[2:3], v[2:3], 0 v_max_f64 v[8:9], v[8:9], 0 v_max_f64 v[10:11], v[10:11], 0 v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[76:77] v_cmp_gt_f64_e64 s3, v[4:5], v[76:77] v_cmp_gt_f64_e64 s4, v[6:7], v[76:77] v_cmp_gt_f64_e64 s2, v[2:3], v[76:77] v_cmp_gt_f64_e64 s5, v[8:9], v[76:77] v_cmp_gt_f64_e64 s6, v[10:11], v[76:77] v_cndmask_b32_e32 v1, v1, v77, vcc_lo v_cndmask_b32_e64 v5, v5, v77, s3 v_cndmask_b32_e32 v0, v0, v76, vcc_lo v_cndmask_b32_e64 v4, v4, v76, s3 v_cndmask_b32_e64 v7, v7, v77, s4 v_cndmask_b32_e64 v6, v6, v76, s4 v_cndmask_b32_e64 v3, v3, v77, s2 v_cndmask_b32_e64 v2, v2, v76, s2 v_cvt_i32_f64_e32 v0, v[0:1] v_cvt_i32_f64_e32 v1, v[4:5] v_cndmask_b32_e64 v9, v9, v77, s5 v_cndmask_b32_e64 v8, v8, v76, s5 v_cvt_i32_f64_e32 v4, v[6:7] v_cvt_i32_f64_e32 v3, v[2:3] v_cndmask_b32_e64 v11, v11, v77, s6 v_cndmask_b32_e64 v10, v10, v76, s6 v_cvt_i32_f64_e32 v5, v[8:9] s_and_b32 s2, s62, s33 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) v_cvt_i32_f64_e32 v7, v[10:11] v_add_nc_u32_e32 v0, v47, v0 v_add_nc_u32_e32 v2, v47, v1 v_add_nc_u32_e32 v4, v47, v4 v_add_nc_u32_e32 v8, v47, v3 v_ashrrev_i32_e32 v3, 31, v2 v_ashrrev_i32_e32 v1, 31, v0 v_add_nc_u32_e32 v6, v47, v5 v_ashrrev_i32_e32 v5, 31, v4 v_ashrrev_i32_e32 v9, 31, v8 v_lshlrev_b64 v[2:3], 3, v[2:3] v_add_nc_u32_e32 v10, v47, v7 v_ashrrev_i32_e32 v7, 31, v6 v_lshlrev_b64 v[4:5], 3, v[4:5] v_lshlrev_b64 v[0:1], 3, v[0:1] v_lshlrev_b64 v[8:9], 3, v[8:9] v_add_co_u32 v2, vcc_lo, s68, v2 v_lshlrev_b64 v[6:7], 3, v[6:7] v_add_co_ci_u32_e32 v3, vcc_lo, s69, v3, vcc_lo v_add_co_u32 v4, vcc_lo, s68, v4 v_ashrrev_i32_e32 v11, 31, v10 v_add_co_ci_u32_e32 v5, vcc_lo, s69, v5, vcc_lo v_add_co_u32 v6, vcc_lo, s68, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s69, v7, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_lshlrev_b64 v[10:11], 3, v[10:11] v_add_co_u32 v0, vcc_lo, s68, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s69, v1, vcc_lo v_add_co_u32 v8, vcc_lo, s68, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s69, v9, vcc_lo v_add_co_u32 v12, vcc_lo, s68, v10 v_add_co_ci_u32_e32 v13, vcc_lo, s69, v11, vcc_lo s_clause 0x5 global_load_b64 v[16:17], v[2:3], off global_load_b64 v[18:19], v[4:5], off global_load_b64 v[10:11], v[6:7], off global_load_b64 v[2:3], v[0:1], off global_load_b64 v[4:5], v[8:9], off global_load_b64 v[8:9], v[12:13], off s_and_saveexec_b32 s3, s2 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s77, exec_lo, s3 s_cbranch_execz .LBB4_19 ; %bb.18: s_waitcnt vmcnt(4) v_add_f64 v[0:1], v[18:19], -v[16:17] s_waitcnt vmcnt(3) v_add_f64 v[6:7], v[10:11], -v[18:19] v_add_f64 v[10:11], v[68:69], -v[10:11] s_waitcnt vmcnt(2) v_add_f64 v[12:13], v[2:3], -v[68:69] s_waitcnt vmcnt(1) v_add_f64 v[2:3], v[4:5], -v[2:3] s_waitcnt vmcnt(0) v_add_f64 v[4:5], v[8:9], -v[4:5] s_getpc_b64 s[78:79] s_add_u32 s78, s78, _Z24weno_onesided_derivativeddddd@rel32@lo+4 s_addc_u32 s79, s79, _Z24weno_onesided_derivativeddddd@rel32@hi+12 v_div_scale_f64 v[8:9], null, s[70:71], s[70:71], v[0:1] v_div_scale_f64 v[14:15], null, s[70:71], s[70:71], v[6:7] v_div_scale_f64 v[16:17], null, s[70:71], s[70:71], v[10:11] v_div_scale_f64 v[18:19], null, s[70:71], s[70:71], v[12:13] v_div_scale_f64 v[20:21], null, s[70:71], s[70:71], v[2:3] v_div_scale_f64 v[22:23], null, s[70:71], s[70:71], v[4:5] v_div_scale_f64 v[53:54], vcc_lo, v[0:1], s[70:71], v[0:1] v_rcp_f64_e32 v[24:25], v[8:9] v_rcp_f64_e32 v[26:27], v[14:15] v_rcp_f64_e32 v[28:29], v[16:17] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_rcp_f64_e32 v[30:31], v[18:19] v_rcp_f64_e32 v[32:33], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3) v_rcp_f64_e32 v[34:35], v[22:23] v_fma_f64 v[36:37], -v[8:9], v[24:25], 1.0 v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0 v_fma_f64 v[45:46], -v[16:17], v[28:29], 1.0 v_fma_f64 v[47:48], -v[18:19], v[30:31], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[49:50], -v[20:21], v[32:33], 1.0 v_fma_f64 v[51:52], -v[22:23], v[34:35], 1.0 v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25] v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27] v_fma_f64 v[28:29], v[28:29], v[45:46], v[28:29] v_fma_f64 v[30:31], v[30:31], v[47:48], v[30:31] v_fma_f64 v[32:33], v[32:33], v[49:50], v[32:33] v_fma_f64 v[34:35], v[34:35], v[51:52], v[34:35] v_fma_f64 v[36:37], -v[8:9], v[24:25], 1.0 v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0 v_fma_f64 v[45:46], -v[16:17], v[28:29], 1.0 v_fma_f64 v[47:48], -v[18:19], v[30:31], 1.0 v_fma_f64 v[49:50], -v[20:21], v[32:33], 1.0 v_fma_f64 v[51:52], -v[22:23], v[34:35], 1.0 v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25] v_div_scale_f64 v[36:37], s0, v[6:7], s[70:71], v[6:7] v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27] v_div_scale_f64 v[38:39], s1, v[10:11], s[70:71], v[10:11] v_fma_f64 v[28:29], v[28:29], v[45:46], v[28:29] v_div_scale_f64 v[45:46], s2, v[12:13], s[70:71], v[12:13] v_fma_f64 v[30:31], v[30:31], v[47:48], v[30:31] v_div_scale_f64 v[47:48], s3, v[2:3], s[70:71], v[2:3] v_fma_f64 v[32:33], v[32:33], v[49:50], v[32:33] v_fma_f64 v[34:35], v[34:35], v[51:52], v[34:35] v_div_scale_f64 v[49:50], s4, v[4:5], s[70:71], v[4:5] v_mul_f64 v[51:52], v[53:54], v[24:25] v_mul_f64 v[55:56], v[36:37], v[26:27] v_mul_f64 v[57:58], v[38:39], v[28:29] v_mul_f64 v[75:76], v[45:46], v[30:31] v_mul_f64 v[77:78], v[47:48], v[32:33] v_mul_f64 v[79:80], v[49:50], v[34:35] v_fma_f64 v[8:9], -v[8:9], v[51:52], v[53:54] v_fma_f64 v[14:15], -v[14:15], v[55:56], v[36:37] v_fma_f64 v[16:17], -v[16:17], v[57:58], v[38:39] v_fma_f64 v[18:19], -v[18:19], v[75:76], v[45:46] v_fma_f64 v[20:21], -v[20:21], v[77:78], v[47:48] v_fma_f64 v[22:23], -v[22:23], v[79:80], v[49:50] v_div_fmas_f64 v[8:9], v[8:9], v[24:25], v[51:52] s_mov_b32 vcc_lo, s0 v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[55:56] s_mov_b32 vcc_lo, s1 v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[57:58] s_mov_b32 vcc_lo, s2 v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[75:76] s_mov_b32 vcc_lo, s3 v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[77:78] s_mov_b32 vcc_lo, s4 v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[79:80] v_div_fixup_f64 v[0:1], v[8:9], s[70:71], v[0:1] v_div_fixup_f64 v[50:51], v[14:15], s[70:71], v[6:7] v_div_fixup_f64 v[52:53], v[16:17], s[70:71], v[10:11] v_div_fixup_f64 v[54:55], v[18:19], s[70:71], v[12:13] v_div_fixup_f64 v[56:57], v[20:21], s[70:71], v[2:3] v_div_fixup_f64 v[58:59], v[22:23], s[70:71], v[4:5] v_dual_mov_b32 v2, v50 :: v_dual_mov_b32 v3, v51 v_dual_mov_b32 v4, v52 :: v_dual_mov_b32 v5, v53 v_dual_mov_b32 v6, v54 :: v_dual_mov_b32 v7, v55 v_dual_mov_b32 v8, v56 :: v_dual_mov_b32 v9, v57 s_swappc_b64 s[30:31], s[78:79] v_dual_mov_b32 v45, v0 :: v_dual_mov_b32 v46, v1 v_dual_mov_b32 v0, v58 :: v_dual_mov_b32 v1, v59 v_dual_mov_b32 v2, v56 :: v_dual_mov_b32 v3, v57 v_dual_mov_b32 v4, v54 :: v_dual_mov_b32 v5, v55 v_dual_mov_b32 v6, v52 :: v_dual_mov_b32 v7, v53 v_dual_mov_b32 v8, v50 :: v_dual_mov_b32 v9, v51 s_swappc_b64 s[30:31], s[78:79] v_dual_mov_b32 v50, v0 :: v_dual_mov_b32 v51, v1 s_mov_b64 s[0:1], s[66:67] ; implicit-def: $vgpr10_vgpr11 ; implicit-def: $vgpr18_vgpr19 ; implicit-def: $vgpr16_vgpr17 ; implicit-def: $vgpr58_vgpr59 ; implicit-def: $vgpr56_vgpr57 ; implicit-def: $vgpr2_vgpr3 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $vgpr8_vgpr9 .LBB4_19: ; %Flow451 s_and_not1_saveexec_b32 s6, s77 s_cbranch_execz .LBB4_27 ; %bb.20: s_load_b128 s[8:11], s[0:1], 0x70 v_lshlrev_b64 v[0:1], 3, v[66:67] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v6, vcc_lo, s10, v0 v_add_co_ci_u32_e32 v7, vcc_lo, s11, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s8, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo global_load_b64 v[26:27], v[6:7], off global_load_b64 v[20:21], v[0:1], off v_add_f64 v[6:7], s[70:71], s[70:71] v_dual_mov_b32 v0, s70 :: v_dual_mov_b32 v1, s71 s_and_saveexec_b32 s2, s62 s_cbranch_execz .LBB4_22 ; %bb.21: v_mul_f64 v[12:13], s[70:71], 0x40080000 v_dual_mov_b32 v56, s70 :: v_dual_mov_b32 v57, s71 s_delay_alu instid0(VALU_DEP_4) v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7 s_waitcnt vmcnt(0) v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5 v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9 v_dual_mov_b32 v6, v12 :: v_dual_mov_b32 v7, v13 .LBB4_22: s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $vgpr8_vgpr9 ; implicit-def: $sgpr2_sgpr3 ; implicit-def: $sgpr4_sgpr5 s_and_saveexec_b32 s7, s33 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s7, exec_lo, s7 s_cbranch_execz .LBB4_24 ; %bb.23: s_mov_b32 s4, 0 s_waitcnt vmcnt(2) v_mul_f64 v[8:9], s[70:71], -2.0 s_mov_b32 s5, 0xc0080000 s_xor_b32 s3, s71, 0x80000000 s_mov_b32 s2, s70 ; implicit-def: $vgpr58_vgpr59 ; implicit-def: $vgpr26_vgpr27 .LBB4_24: ; %Flow448 s_or_saveexec_b32 s7, s7 v_dual_mov_b32 v13, s5 :: v_dual_mov_b32 v12, s4 v_dual_mov_b32 v15, s3 :: v_dual_mov_b32 v14, s2 s_waitcnt vmcnt(5) v_dual_mov_b32 v25, v11 :: v_dual_mov_b32 v24, v10 v_dual_mov_b32 v23, v19 :: v_dual_mov_b32 v22, v18 s_xor_b32 exec_lo, exec_lo, s7 s_cbranch_execz .LBB4_26 ; %bb.25: v_xor_b32_e32 v59, 0x80000000, v59 s_xor_b32 s3, s71, 0x80000000 s_mov_b32 s2, s70 s_waitcnt vmcnt(2) v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v9, s3 v_dual_mov_b32 v13, -2.0 :: v_dual_mov_b32 v8, s2 v_dual_mov_b32 v14, v58 :: v_dual_mov_b32 v15, v59 s_waitcnt vmcnt(1) v_dual_mov_b32 v24, v26 :: v_dual_mov_b32 v25, v27 v_dual_mov_b32 v23, v11 :: v_dual_mov_b32 v22, v10 v_dual_mov_b32 v16, v18 :: v_dual_mov_b32 v17, v19 .LBB4_26: ; %_Z14select_stencilRdS_S_S_S_S_S_S_S_S_S_S_S_S_dddddddddddddddd.exit.i350 s_or_b32 exec_lo, exec_lo, s7 s_waitcnt vmcnt(3) v_add_f64 v[4:5], v[4:5], -v[2:3] v_add_f64 v[10:11], v[6:7], -v[0:1] s_waitcnt vmcnt(0) v_add_f64 v[2:3], v[2:3], -v[20:21] v_add_f64 v[16:17], v[22:23], -v[16:17] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[18:19], null, v[10:11], v[10:11], v[4:5] v_rcp_f64_e32 v[26:27], v[18:19] s_waitcnt_depctr 0xfff v_fma_f64 v[28:29], -v[18:19], v[26:27], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[26:27], v[28:29], v[26:27] v_fma_f64 v[28:29], -v[18:19], v[26:27], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[26:27], v[28:29], v[26:27] v_div_scale_f64 v[28:29], vcc_lo, v[4:5], v[10:11], v[4:5] v_mul_f64 v[30:31], v[28:29], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[18:19], v[30:31], v[28:29] v_div_fmas_f64 v[18:19], v[18:19], v[26:27], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[18:19], v[18:19], v[10:11], v[4:5] v_add_f64 v[4:5], v[0:1], -v[56:57] v_div_scale_f64 v[10:11], null, v[4:5], v[4:5], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[26:27], v[10:11] s_waitcnt_depctr 0xfff v_fma_f64 v[28:29], -v[10:11], v[26:27], 1.0 v_fma_f64 v[26:27], v[26:27], v[28:29], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], -v[10:11], v[26:27], 1.0 v_fma_f64 v[26:27], v[26:27], v[28:29], v[26:27] v_div_scale_f64 v[28:29], vcc_lo, v[2:3], v[4:5], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[30:31], v[28:29], v[26:27] v_fma_f64 v[10:11], -v[10:11], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[10:11], v[10:11], v[26:27], v[30:31] v_div_fixup_f64 v[26:27], v[10:11], v[4:5], v[2:3] v_add_f64 v[2:3], v[20:21], -v[68:69] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[18:19], v[18:19], -v[26:27] v_div_scale_f64 v[4:5], null, v[56:57], v[56:57], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[10:11], v[4:5] s_waitcnt_depctr 0xfff v_fma_f64 v[20:21], -v[4:5], v[10:11], 1.0 v_fma_f64 v[10:11], v[10:11], v[20:21], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[4:5], v[10:11], 1.0 v_fma_f64 v[10:11], v[10:11], v[20:21], v[10:11] v_div_scale_f64 v[20:21], vcc_lo, v[2:3], v[56:57], v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[28:29], v[20:21], v[10:11] v_fma_f64 v[4:5], -v[4:5], v[28:29], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fmas_f64 v[4:5], v[4:5], v[10:11], v[28:29] v_add_f64 v[10:11], v[68:69], -v[24:25] v_div_fixup_f64 v[2:3], v[4:5], v[56:57], v[2:3] v_add_f64 v[4:5], -v[14:15], 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[20:21], null, v[4:5], v[4:5], v[10:11] v_rcp_f64_e32 v[28:29], v[20:21] s_waitcnt_depctr 0xfff v_fma_f64 v[30:31], -v[20:21], v[28:29], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] v_fma_f64 v[30:31], -v[20:21], v[28:29], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] v_div_scale_f64 v[30:31], vcc_lo, v[10:11], v[4:5], v[10:11] v_mul_f64 v[32:33], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[20:21], v[32:33], v[30:31] v_div_fmas_f64 v[20:21], v[20:21], v[28:29], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_div_fixup_f64 v[10:11], v[20:21], v[4:5], v[10:11] v_add_f64 v[20:21], v[24:25], -v[22:23] v_add_f64 v[24:25], v[14:15], -v[8:9] v_fma_f64 v[22:23], -v[12:13], s[70:71], v[8:9] v_div_scale_f64 v[28:29], null, v[24:25], v[24:25], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[30:31], v[28:29] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[20:21], v[24:25], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[34:35], v[32:33], v[30:31] v_fma_f64 v[28:29], -v[28:29], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[28:29], v[28:29], v[30:31], v[34:35] v_div_fixup_f64 v[20:21], v[28:29], v[24:25], v[20:21] v_div_scale_f64 v[24:25], null, v[22:23], v[22:23], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[28:29], v[24:25] s_waitcnt_depctr 0xfff v_fma_f64 v[30:31], -v[24:25], v[28:29], 1.0 v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], -v[24:25], v[28:29], 1.0 v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] v_div_scale_f64 v[30:31], vcc_lo, v[16:17], v[22:23], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[32:33], v[30:31], v[28:29] v_fma_f64 v[24:25], -v[24:25], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[24:25], v[24:25], v[28:29], v[32:33] v_div_fixup_f64 v[16:17], v[24:25], v[22:23], v[16:17] v_add_f64 v[22:23], v[6:7], -v[56:57] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[20:21], -v[16:17] v_div_scale_f64 v[24:25], null, v[22:23], v[22:23], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[28:29], v[24:25] s_waitcnt_depctr 0xfff v_fma_f64 v[30:31], -v[24:25], v[28:29], 1.0 v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], -v[24:25], v[28:29], 1.0 v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29] v_div_scale_f64 v[30:31], vcc_lo, v[18:19], v[22:23], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[32:33], v[30:31], v[28:29] v_fma_f64 v[24:25], -v[24:25], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[24:25], v[24:25], v[28:29], v[32:33] v_div_fixup_f64 v[18:19], v[24:25], v[22:23], v[18:19] v_add_f64 v[22:23], v[26:27], -v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[24:25], null, v[0:1], v[0:1], v[22:23] v_rcp_f64_e32 v[26:27], v[24:25] s_waitcnt_depctr 0xfff v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[26:27], v[28:29], v[26:27] v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[26:27], v[26:27], v[28:29], v[26:27] v_div_scale_f64 v[28:29], vcc_lo, v[22:23], v[0:1], v[22:23] v_mul_f64 v[30:31], v[28:29], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[24:25], -v[24:25], v[30:31], v[28:29] v_div_fmas_f64 v[24:25], v[24:25], v[26:27], v[30:31] v_add_f64 v[26:27], v[56:57], -v[14:15] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[22:23], v[24:25], v[0:1], v[22:23] v_add_f64 v[24:25], v[2:3], -v[10:11] v_add_f64 v[18:19], v[18:19], -v[22:23] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_scale_f64 v[28:29], null, v[26:27], v[26:27], v[24:25] v_rcp_f64_e32 v[30:31], v[28:29] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[24:25], v[26:27], v[24:25] v_mul_f64 v[34:35], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[28:29], -v[28:29], v[34:35], v[32:33] v_div_fmas_f64 v[28:29], v[28:29], v[30:31], v[34:35] s_delay_alu instid0(VALU_DEP_1) v_div_fixup_f64 v[24:25], v[28:29], v[26:27], v[24:25] v_add_f64 v[26:27], v[10:11], -v[20:21] v_add_f64 v[28:29], -v[8:9], 0 v_fma_f64 v[20:21], -v[12:13], s[70:71], v[14:15] v_add_f64 v[14:15], v[0:1], -v[14:15] v_add_f64 v[8:9], v[56:57], -v[8:9] v_fma_f64 v[12:13], -v[12:13], s[70:71], 0 v_add_f64 v[0:1], -v[0:1], 0 v_div_scale_f64 v[30:31], null, v[28:29], v[28:29], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[32:33], v[30:31] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[26:27], v[28:29], v[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[36:37], v[34:35], v[32:33] v_fma_f64 v[30:31], -v[30:31], v[36:37], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[30:31], v[30:31], v[32:33], v[36:37] v_div_fixup_f64 v[26:27], v[30:31], v[28:29], v[26:27] v_div_scale_f64 v[30:31], null, v[20:21], v[20:21], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[32:33], v[30:31] s_waitcnt_depctr 0xfff v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[34:35], -v[30:31], v[32:33], 1.0 v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33] v_div_scale_f64 v[34:35], vcc_lo, v[16:17], v[20:21], v[16:17] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[36:37], v[34:35], v[32:33] v_fma_f64 v[30:31], -v[30:31], v[36:37], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[30:31], v[30:31], v[32:33], v[36:37] v_div_fixup_f64 v[16:17], v[30:31], v[20:21], v[16:17] v_div_scale_f64 v[20:21], null, v[6:7], v[6:7], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[16:17], v[26:27], -v[16:17] v_rcp_f64_e32 v[30:31], v[20:21] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[20:21], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_fma_f64 v[32:33], -v[20:21], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[18:19], v[6:7], v[18:19] v_mul_f64 v[34:35], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[20:21], v[34:35], v[32:33] v_div_fmas_f64 v[20:21], v[20:21], v[30:31], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[6:7], v[20:21], v[6:7], v[18:19] v_add_f64 v[18:19], v[22:23], -v[24:25] v_div_scale_f64 v[20:21], null, v[14:15], v[14:15], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[30:31], v[20:21] s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[20:21], v[30:31], 1.0 v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[32:33], -v[20:21], v[30:31], 1.0 v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[18:19], v[14:15], v[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[34:35], v[32:33], v[30:31] v_fma_f64 v[20:21], -v[20:21], v[34:35], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[20:21], v[20:21], v[30:31], v[34:35] v_div_fixup_f64 v[14:15], v[20:21], v[14:15], v[18:19] v_add_f64 v[18:19], v[24:25], -v[26:27] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_lt_f64_e64 s2, |v[14:15]|, |v[6:7]| v_div_scale_f64 v[20:21], null, v[8:9], v[8:9], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v7, v7, v15, s2 v_rcp_f64_e32 v[30:31], v[20:21] v_cndmask_b32_e64 v6, v6, v14, s2 v_cmp_lt_f64_e64 s2, |v[24:25]|, |v[22:23]| s_waitcnt_depctr 0xfff v_fma_f64 v[32:33], -v[20:21], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_fma_f64 v[32:33], -v[20:21], v[30:31], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31] v_div_scale_f64 v[32:33], vcc_lo, v[18:19], v[8:9], v[18:19] v_mul_f64 v[34:35], v[32:33], v[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], -v[20:21], v[34:35], v[32:33] v_div_fmas_f64 v[20:21], v[20:21], v[30:31], v[34:35] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_div_fixup_f64 v[8:9], v[20:21], v[8:9], v[18:19] v_div_scale_f64 v[18:19], null, v[12:13], v[12:13], v[16:17] v_rcp_f64_e32 v[20:21], v[18:19] s_waitcnt_depctr 0xfff v_fma_f64 v[30:31], -v[18:19], v[20:21], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[20:21], v[30:31], v[20:21] v_fma_f64 v[30:31], -v[18:19], v[20:21], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fma_f64 v[20:21], v[20:21], v[30:31], v[20:21] v_div_scale_f64 v[30:31], vcc_lo, v[16:17], v[12:13], v[16:17] v_mul_f64 v[32:33], v[30:31], v[20:21] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[18:19], -v[18:19], v[32:33], v[30:31] v_div_fmas_f64 v[18:19], v[18:19], v[20:21], v[32:33] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_div_fixup_f64 v[12:13], v[18:19], v[12:13], v[16:17] v_mul_f64 v[16:17], v[4:5], v[28:29] v_cmp_lt_f64_e64 vcc_lo, |v[8:9]|, |v[12:13]| v_dual_cndmask_b32 v13, v13, v9 :: v_dual_cndmask_b32 v12, v12, v8 v_cmp_lt_f64_e64 vcc_lo, |v[8:9]|, |v[14:15]| s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) v_mul_f64 v[12:13], v[16:17], v[12:13] v_add_f64 v[16:17], -v[56:57], 0 v_dual_cndmask_b32 v9, v15, v9 :: v_dual_cndmask_b32 v8, v14, v8 v_cmp_lt_f64_e64 vcc_lo, |v[26:27]|, |v[24:25]| v_mul_f64 v[18:19], v[16:17], v[4:5] v_mul_f64 v[0:1], v[16:17], v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64 v[8:9], v[18:19], v[8:9] v_mul_f64 v[0:1], v[0:1], v[6:7] v_mul_f64 v[6:7], v[24:25], v[26:27] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v13, v9, v13 :: v_dual_cndmask_b32 v12, v8, v12 v_cndmask_b32_e64 v1, v1, v9, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v0, v0, v8, s2 v_dual_cndmask_b32 v8, v24, v26 :: v_dual_cndmask_b32 v9, v25, v27 v_cmp_ngt_f64_e32 vcc_lo, 0, v[6:7] v_dual_cndmask_b32 v7, 0, v9 :: v_dual_cndmask_b32 v6, 0, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fma_f64 v[4:5], v[4:5], v[6:7], v[10:11] v_cndmask_b32_e64 v6, v22, v24, s2 v_cndmask_b32_e64 v7, v23, v25, s2 v_add_f64 v[45:46], v[4:5], v[12:13] v_mul_f64 v[4:5], v[22:23], v[24:25] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_cmp_ngt_f64_e32 vcc_lo, 0, v[4:5] v_dual_cndmask_b32 v5, 0, v7 :: v_dual_cndmask_b32 v4, 0, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[2:3], v[16:17], v[4:5], v[2:3] v_add_f64 v[50:51], v[2:3], v[0:1] .LBB4_27: ; %Flow452 s_or_b32 exec_lo, exec_lo, s6 v_add_nc_u32_e32 v0, 1, v70 s_waitcnt vmcnt(2) v_add_nc_u32_e32 v2, 2, v70 s_waitcnt vmcnt(1) v_add_nc_u32_e32 v4, 3, v70 v_add_nc_u32_e32 v6, -1, v70 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v8, -3, v70 v_cvt_f64_i32_e32 v[0:1], v0 v_cvt_f64_i32_e32 v[2:3], v2 v_cvt_f64_i32_e32 v[4:5], v4 v_add_nc_u32_e32 v10, -2, v70 v_cvt_f64_i32_e32 v[6:7], v6 v_cvt_f64_i32_e32 v[8:9], v8 ; implicit-def: $vgpr52_vgpr53 s_delay_alu instid0(VALU_DEP_3) v_cvt_f64_i32_e32 v[10:11], v10 v_max_f64 v[0:1], v[0:1], 0 v_max_f64 v[2:3], v[2:3], 0 v_max_f64 v[4:5], v[4:5], 0 v_max_f64 v[6:7], v[6:7], 0 v_max_f64 v[8:9], v[8:9], 0 v_max_f64 v[10:11], v[10:11], 0 v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[71:72] v_cmp_gt_f64_e64 s2, v[2:3], v[71:72] v_cmp_gt_f64_e64 s3, v[4:5], v[71:72] v_cmp_gt_f64_e64 s4, v[6:7], v[71:72] v_cmp_gt_f64_e64 s5, v[8:9], v[71:72] v_cmp_gt_f64_e64 s6, v[10:11], v[71:72] v_dual_cndmask_b32 v1, v1, v72 :: v_dual_cndmask_b32 v0, v0, v71 v_cndmask_b32_e64 v3, v3, v72, s2 v_cndmask_b32_e64 v2, v2, v71, s2 v_cndmask_b32_e64 v5, v5, v72, s3 v_cndmask_b32_e64 v4, v4, v71, s3 v_cndmask_b32_e64 v7, v7, v72, s4 v_cndmask_b32_e64 v6, v6, v71, s4 v_cndmask_b32_e64 v9, v9, v72, s5 v_cndmask_b32_e64 v8, v8, v71, s5 v_cvt_i32_f64_e32 v12, v[0:1] v_cvt_i32_f64_e32 v3, v[2:3] v_cndmask_b32_e64 v11, v11, v72, s6 v_cvt_i32_f64_e32 v4, v[4:5] v_cndmask_b32_e64 v10, v10, v71, s6 v_cvt_i32_f64_e32 v5, v[6:7] v_cvt_i32_f64_e32 v6, v[8:9] s_delay_alu instid0(VALU_DEP_3) v_cvt_i32_f64_e32 v7, v[10:11] v_mad_u64_u32 v[0:1], null, v12, s65, v[74:75] v_mad_u64_u32 v[1:2], null, v3, s65, v[74:75] v_mad_u64_u32 v[2:3], null, v4, s65, v[74:75] v_mad_u64_u32 v[3:4], null, v5, s65, v[74:75] v_mad_u64_u32 v[4:5], null, v6, s65, v[74:75] v_mad_u64_u32 v[5:6], null, v7, s65, v[74:75] v_mad_u64_u32 v[6:7], null, v0, s64, v[73:74] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_mad_u64_u32 v[8:9], null, v3, s64, v[73:74] v_mad_u64_u32 v[10:11], null, v4, s64, v[73:74] s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_mad_u64_u32 v[3:4], null, v5, s64, v[73:74] v_mad_u64_u32 v[12:13], null, v1, s64, v[73:74] v_ashrrev_i32_e32 v9, 31, v8 v_mad_u64_u32 v[0:1], null, v2, s64, v[73:74] v_ashrrev_i32_e32 v11, 31, v10 v_ashrrev_i32_e32 v4, 31, v3 v_ashrrev_i32_e32 v7, 31, v6 v_ashrrev_i32_e32 v13, 31, v12 s_load_b64 s[64:65], s[0:1], 0xb0 v_lshlrev_b64 v[10:11], 3, v[10:11] v_lshlrev_b64 v[2:3], 3, v[3:4] v_lshlrev_b64 v[4:5], 3, v[8:9] v_lshlrev_b64 v[6:7], 3, v[6:7] v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[8:9], 3, v[12:13] v_add_co_u32 v10, vcc_lo, s68, v10 v_add_co_ci_u32_e32 v11, vcc_lo, s69, v11, vcc_lo v_add_co_u32 v2, vcc_lo, s68, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s69, v3, vcc_lo v_add_co_u32 v4, vcc_lo, s68, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s69, v5, vcc_lo v_lshlrev_b64 v[0:1], 3, v[0:1] v_add_co_u32 v6, vcc_lo, s68, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s69, v7, vcc_lo v_add_co_u32 v8, vcc_lo, s68, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s69, v9, vcc_lo v_add_co_u32 v0, vcc_lo, s68, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s69, v1, vcc_lo s_clause 0x5 global_load_b64 v[14:15], v[10:11], off global_load_b64 v[18:19], v[2:3], off global_load_b64 v[16:17], v[4:5], off global_load_b64 v[4:5], v[6:7], off global_load_b64 v[12:13], v[8:9], off global_load_b64 v[6:7], v[0:1], off s_waitcnt lgkmcnt(0) v_cmp_ngt_f64_e64 s62, s[64:65], v[60:61] v_cmp_ngt_f64_e64 s33, s[64:65], v[62:63] ; implicit-def: $vgpr0_vgpr1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, s62, s33 s_and_saveexec_b32 s3, s2 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s68, exec_lo, s3 s_cbranch_execz .LBB4_29 ; %bb.28: s_waitcnt vmcnt(4) v_add_f64 v[0:1], v[18:19], -v[14:15] s_waitcnt vmcnt(3) v_add_f64 v[2:3], v[16:17], -v[18:19] v_add_f64 v[8:9], v[68:69], -v[16:17] s_waitcnt vmcnt(2) v_add_f64 v[10:11], v[4:5], -v[68:69] s_waitcnt vmcnt(1) v_add_f64 v[4:5], v[12:13], -v[4:5] s_waitcnt vmcnt(0) v_add_f64 v[6:7], v[6:7], -v[12:13] s_getpc_b64 s[70:71] s_add_u32 s70, s70, _Z24weno_onesided_derivativeddddd@rel32@lo+4 s_addc_u32 s71, s71, _Z24weno_onesided_derivativeddddd@rel32@hi+12 v_div_scale_f64 v[12:13], null, s[64:65], s[64:65], v[0:1] v_div_scale_f64 v[14:15], null, s[64:65], s[64:65], v[2:3] v_div_scale_f64 v[16:17], null, s[64:65], s[64:65], v[8:9] v_div_scale_f64 v[18:19], null, s[64:65], s[64:65], v[10:11] v_div_scale_f64 v[20:21], null, s[64:65], s[64:65], v[4:5] v_div_scale_f64 v[22:23], null, s[64:65], s[64:65], v[6:7] v_div_scale_f64 v[58:59], vcc_lo, v[0:1], s[64:65], v[0:1] v_rcp_f64_e32 v[24:25], v[12:13] v_rcp_f64_e32 v[26:27], v[14:15] v_rcp_f64_e32 v[28:29], v[16:17] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_rcp_f64_e32 v[30:31], v[18:19] v_rcp_f64_e32 v[32:33], v[20:21] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3) v_rcp_f64_e32 v[34:35], v[22:23] v_fma_f64 v[36:37], -v[12:13], v[24:25], 1.0 v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0 v_fma_f64 v[47:48], -v[16:17], v[28:29], 1.0 v_fma_f64 v[52:53], -v[18:19], v[30:31], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[54:55], -v[20:21], v[32:33], 1.0 v_fma_f64 v[56:57], -v[22:23], v[34:35], 1.0 v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25] v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27] v_fma_f64 v[28:29], v[28:29], v[47:48], v[28:29] v_fma_f64 v[30:31], v[30:31], v[52:53], v[30:31] v_fma_f64 v[32:33], v[32:33], v[54:55], v[32:33] v_fma_f64 v[34:35], v[34:35], v[56:57], v[34:35] v_fma_f64 v[36:37], -v[12:13], v[24:25], 1.0 v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0 v_fma_f64 v[47:48], -v[16:17], v[28:29], 1.0 v_fma_f64 v[52:53], -v[18:19], v[30:31], 1.0 v_fma_f64 v[54:55], -v[20:21], v[32:33], 1.0 v_fma_f64 v[56:57], -v[22:23], v[34:35], 1.0 v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25] v_div_scale_f64 v[36:37], s0, v[2:3], s[64:65], v[2:3] v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27] v_div_scale_f64 v[38:39], s1, v[8:9], s[64:65], v[8:9] v_fma_f64 v[28:29], v[28:29], v[47:48], v[28:29] v_div_scale_f64 v[47:48], s2, v[10:11], s[64:65], v[10:11] v_fma_f64 v[30:31], v[30:31], v[52:53], v[30:31] v_div_scale_f64 v[52:53], s3, v[4:5], s[64:65], v[4:5] v_fma_f64 v[32:33], v[32:33], v[54:55], v[32:33] v_fma_f64 v[34:35], v[34:35], v[56:57], v[34:35] v_div_scale_f64 v[54:55], s4, v[6:7], s[64:65], v[6:7] v_mul_f64 v[56:57], v[58:59], v[24:25] v_mul_f64 v[60:61], v[36:37], v[26:27] v_mul_f64 v[62:63], v[38:39], v[28:29] v_mul_f64 v[68:69], v[47:48], v[30:31] v_mul_f64 v[70:71], v[52:53], v[32:33] v_mul_f64 v[72:73], v[54:55], v[34:35] v_fma_f64 v[12:13], -v[12:13], v[56:57], v[58:59] v_fma_f64 v[14:15], -v[14:15], v[60:61], v[36:37] v_fma_f64 v[16:17], -v[16:17], v[62:63], v[38:39] v_fma_f64 v[18:19], -v[18:19], v[68:69], v[47:48] v_fma_f64 v[20:21], -v[20:21], v[70:71], v[52:53] v_fma_f64 v[22:23], -v[22:23], v[72:73], v[54:55] v_div_fmas_f64 v[12:13], v[12:13], v[24:25], v[56:57] s_mov_b32 vcc_lo, s0 v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[60:61] s_mov_b32 vcc_lo, s1 v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[62:63] s_mov_b32 vcc_lo, s2 v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[68:69] s_mov_b32 vcc_lo, s3 v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[70:71] s_mov_b32 vcc_lo, s4 v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[72:73] v_div_fixup_f64 v[0:1], v[12:13], s[64:65], v[0:1] v_div_fixup_f64 v[54:55], v[14:15], s[64:65], v[2:3] v_div_fixup_f64 v[56:57], v[16:17], s[64:65], v[8:9] v_div_fixup_f64 v[58:59], v[18:19], s[64:65], v[10:11] v_div_fixup_f64 v[60:61], v[20:21], s[64:65], v[4:5] v_div_fixup_f64 v[62:63], v[22:23], s[64:65], v[6:7] v_dual_mov_b32 v2, v54 :: v_dual_mov_b32 v3, v55 v_dual_mov_b32 v4, v56 :: v_dual_mov_b32 v5, v57 v_dual_mov_b32 v6, v58 :: v_dual_mov_b32 v7, v59 v_dual_mov_b32 v8, v60 :: v_dual_mov_b32 v9, v61 s_swappc_b64 s[30:31], s[70:71] v_dual_mov_b32 v52, v0 :: v_dual_mov_b32 v53, v1 v_dual_mov_b32 v0, v62 :: v_dual_mov_b32 v1, v63 v_dual_mov_b32 v2, v60 :: v_dual_mov_b32 v3, v61 v_dual_mov_b32 v4, v58 :: v_dual_mov_b32 v5, v59 v_dual_mov_b32 v6, v56 :: v_dual_mov_b32 v7, v57 v_dual_mov_b32 v8, v54 :: v_dual_mov_b32 v9, v55 s_swappc_b64 s[30:31], s[70:71] s_mov_b64 s[0:1], s[66:67] ; implicit-def: $vgpr60_vgpr61 ; implicit-def: $vgpr62_vgpr63 ; implicit-def: $vgpr68_vgpr69 ; implicit-def: $vgpr14_vgpr15 ; implicit-def: $vgpr18_vgpr19 ; implicit-def: $vgpr16_vgpr17 ; implicit-def: $vgpr4_vgpr5 ; implicit-def: $vgpr12_vgpr13 ; implicit-def: $vgpr6_vgpr7 .LBB4_29: ; %Flow445 s_and_not1_saveexec_b32 s7, s68 s_cbranch_execz .LBB4_37 ; %bb.30: s_load_b128 s[8:11], s[0:1], 0x80 v_lshlrev_b64 v[0:1], 3, v[66:67] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s10, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s8, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo global_load_b64 v[22:23], v[2:3], off global_load_b64 v[20:21], v[0:1], off v_add_f64 v[2:3], s[64:65], s[64:65] v_dual_mov_b32 v0, s64 :: v_dual_mov_b32 v1, s65 s_and_saveexec_b32 s2, s62 s_cbranch_execz .LBB4_32 ; %bb.31: v_mul_f64 v[8:9], s[64:65], 0x40080000 v_dual_mov_b32 v60, s64 :: v_dual_mov_b32 v61, s65 s_delay_alu instid0(VALU_DEP_4) v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3 s_waitcnt vmcnt(0) v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v20, v4 v_dual_mov_b32 v4, v12 :: v_dual_mov_b32 v5, v13 v_dual_mov_b32 v13, v7 :: v_dual_mov_b32 v12, v6 v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9 .LBB4_32: s_or_b32 exec_lo, exec_lo, s2 ; implicit-def: $vgpr6_vgpr7 ; implicit-def: $sgpr2_sgpr3 ; implicit-def: $sgpr4_sgpr5 s_and_saveexec_b32 s6, s33 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s6, exec_lo, s6 s_cbranch_execz .LBB4_34 ; %bb.33: s_mov_b32 s4, 0 s_waitcnt vmcnt(2) v_mul_f64 v[6:7], s[64:65], -2.0 s_mov_b32 s5, 0xc0080000 s_xor_b32 s3, s65, 0x80000000 s_mov_b32 s2, s64 ; implicit-def: $vgpr62_vgpr63 ; implicit-def: $vgpr22_vgpr23 .LBB4_34: ; %Flow s_or_saveexec_b32 s6, s6 v_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4 v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2 s_waitcnt vmcnt(5) v_dual_mov_b32 v27, v17 :: v_dual_mov_b32 v26, v16 v_dual_mov_b32 v25, v19 :: v_dual_mov_b32 v24, v18 s_xor_b32 exec_lo, exec_lo, s6 s_cbranch_execz .LBB4_36 ; %bb.35: v_xor_b32_e32 v63, 0x80000000, v63 s_xor_b32 s3, s65, 0x80000000 s_mov_b32 s2, s64 s_waitcnt vmcnt(2) v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v7, s3 v_dual_mov_b32 v9, -2.0 :: v_dual_mov_b32 v6, s2 v_dual_mov_b32 v10, v62 :: v_dual_mov_b32 v11, v63 s_waitcnt vmcnt(1) v_dual_mov_b32 v27, v23 :: v_dual_mov_b32 v26, v22 v_dual_mov_b32 v25, v17 :: v_dual_mov_b32 v24, v16 v_dual_mov_b32 v14, v18 :: v_dual_mov_b32 v15, v19 .LBB4_36: ; %_Z14select_stencilRdS_S_S_S_S_S_S_S_S_S_S_S_S_dddddddddddddddd.exit.i377 s_or_b32 exec_lo, exec_lo, s6 s_waitcnt vmcnt(3) v_add_f64 v[12:13], v[12:13], -v[4:5] v_add_f64 v[16:17], v[2:3], -v[0:1] s_waitcnt vmcnt(0) v_add_f64 v[18:19], v[4:5], -v[20:21] v_add_f64 v[22:23], v[0:1], -v[60:61] v_add_f64 v[20:21], v[20:21], -v[68:69] v_add_f64 v[28:29], v[68:69], -v[26:27] v_add_f64 v[4:5], -v[10:11], 0 v_add_f64 v[26:27], v[26:27], -v[24:25] v_add_f64 v[30:31], v[10:11], -v[6:7] v_add_f64 v[14:15], v[24:25], -v[14:15] v_fma_f64 v[24:25], -v[8:9], s[64:65], v[6:7] v_div_scale_f64 v[32:33], null, v[16:17], v[16:17], v[12:13] v_div_scale_f64 v[34:35], null, v[22:23], v[22:23], v[18:19] v_div_scale_f64 v[36:37], null, v[60:61], v[60:61], v[20:21] v_div_scale_f64 v[38:39], null, v[4:5], v[4:5], v[28:29] v_div_scale_f64 v[47:48], null, v[30:31], v[30:31], v[26:27] v_div_scale_f64 v[52:53], null, v[24:25], v[24:25], v[14:15] v_div_scale_f64 v[84:85], vcc_lo, v[12:13], v[16:17], v[12:13] v_rcp_f64_e32 v[54:55], v[32:33] v_rcp_f64_e32 v[56:57], v[34:35] v_rcp_f64_e32 v[58:59], v[36:37] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_rcp_f64_e32 v[62:63], v[38:39] v_rcp_f64_e32 v[68:69], v[47:48] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3) v_rcp_f64_e32 v[70:71], v[52:53] v_fma_f64 v[72:73], -v[32:33], v[54:55], 1.0 v_fma_f64 v[74:75], -v[34:35], v[56:57], 1.0 v_fma_f64 v[76:77], -v[36:37], v[58:59], 1.0 v_fma_f64 v[78:79], -v[38:39], v[62:63], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[80:81], -v[47:48], v[68:69], 1.0 v_fma_f64 v[82:83], -v[52:53], v[70:71], 1.0 v_fma_f64 v[54:55], v[54:55], v[72:73], v[54:55] v_fma_f64 v[56:57], v[56:57], v[74:75], v[56:57] v_fma_f64 v[58:59], v[58:59], v[76:77], v[58:59] v_fma_f64 v[62:63], v[62:63], v[78:79], v[62:63] v_fma_f64 v[68:69], v[68:69], v[80:81], v[68:69] v_fma_f64 v[70:71], v[70:71], v[82:83], v[70:71] v_fma_f64 v[72:73], -v[32:33], v[54:55], 1.0 v_fma_f64 v[74:75], -v[34:35], v[56:57], 1.0 v_fma_f64 v[76:77], -v[36:37], v[58:59], 1.0 v_fma_f64 v[78:79], -v[38:39], v[62:63], 1.0 v_fma_f64 v[80:81], -v[47:48], v[68:69], 1.0 v_fma_f64 v[82:83], -v[52:53], v[70:71], 1.0 v_fma_f64 v[54:55], v[54:55], v[72:73], v[54:55] v_div_scale_f64 v[72:73], s2, v[18:19], v[22:23], v[18:19] v_fma_f64 v[56:57], v[56:57], v[74:75], v[56:57] v_div_scale_f64 v[74:75], s3, v[20:21], v[60:61], v[20:21] v_fma_f64 v[58:59], v[58:59], v[76:77], v[58:59] v_div_scale_f64 v[76:77], s4, v[28:29], v[4:5], v[28:29] v_fma_f64 v[62:63], v[62:63], v[78:79], v[62:63] v_div_scale_f64 v[78:79], s5, v[26:27], v[30:31], v[26:27] v_fma_f64 v[68:69], v[68:69], v[80:81], v[68:69] v_div_scale_f64 v[80:81], s6, v[14:15], v[24:25], v[14:15] v_fma_f64 v[70:71], v[70:71], v[82:83], v[70:71] v_mul_f64 v[82:83], v[84:85], v[54:55] v_mul_f64 v[86:87], v[72:73], v[56:57] v_mul_f64 v[88:89], v[74:75], v[58:59] v_mul_f64 v[90:91], v[76:77], v[62:63] v_mul_f64 v[92:93], v[78:79], v[68:69] v_mul_f64 v[94:95], v[80:81], v[70:71] v_fma_f64 v[32:33], -v[32:33], v[82:83], v[84:85] v_fma_f64 v[34:35], -v[34:35], v[86:87], v[72:73] v_fma_f64 v[36:37], -v[36:37], v[88:89], v[74:75] v_fma_f64 v[38:39], -v[38:39], v[90:91], v[76:77] v_fma_f64 v[47:48], -v[47:48], v[92:93], v[78:79] v_fma_f64 v[52:53], -v[52:53], v[94:95], v[80:81] v_div_fmas_f64 v[32:33], v[32:33], v[54:55], v[82:83] s_mov_b32 vcc_lo, s2 v_div_fmas_f64 v[34:35], v[34:35], v[56:57], v[86:87] s_mov_b32 vcc_lo, s3 v_div_fmas_f64 v[36:37], v[36:37], v[58:59], v[88:89] s_mov_b32 vcc_lo, s4 v_div_fmas_f64 v[38:39], v[38:39], v[62:63], v[90:91] s_mov_b32 vcc_lo, s5 v_div_fmas_f64 v[47:48], v[47:48], v[68:69], v[92:93] s_mov_b32 vcc_lo, s6 v_div_fmas_f64 v[52:53], v[52:53], v[70:71], v[94:95] v_div_fixup_f64 v[12:13], v[32:33], v[16:17], v[12:13] v_div_fixup_f64 v[16:17], v[34:35], v[22:23], v[18:19] v_fma_f64 v[34:35], -v[8:9], s[64:65], v[10:11] v_fma_f64 v[8:9], -v[8:9], s[64:65], 0 v_div_fixup_f64 v[18:19], v[36:37], v[60:61], v[20:21] v_div_fixup_f64 v[20:21], v[38:39], v[4:5], v[28:29] v_div_fixup_f64 v[22:23], v[47:48], v[30:31], v[26:27] v_add_f64 v[26:27], v[60:61], -v[10:11] v_add_f64 v[30:31], -v[6:7], 0 v_div_fixup_f64 v[14:15], v[52:53], v[24:25], v[14:15] v_add_f64 v[24:25], v[2:3], -v[60:61] v_add_f64 v[10:11], v[0:1], -v[10:11] v_add_f64 v[6:7], v[60:61], -v[6:7] v_add_f64 v[12:13], v[12:13], -v[16:17] v_add_f64 v[16:17], v[16:17], -v[18:19] v_add_f64 v[28:29], v[18:19], -v[20:21] v_add_f64 v[32:33], v[20:21], -v[22:23] v_add_f64 v[14:15], v[22:23], -v[14:15] v_div_scale_f64 v[22:23], null, v[24:25], v[24:25], v[12:13] v_div_scale_f64 v[80:81], vcc_lo, v[12:13], v[24:25], v[12:13] v_div_scale_f64 v[36:37], null, v[0:1], v[0:1], v[16:17] v_div_scale_f64 v[38:39], null, v[26:27], v[26:27], v[28:29] v_div_scale_f64 v[47:48], null, v[30:31], v[30:31], v[32:33] v_div_scale_f64 v[52:53], null, v[34:35], v[34:35], v[14:15] v_rcp_f64_e32 v[54:55], v[22:23] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_rcp_f64_e32 v[56:57], v[36:37] v_rcp_f64_e32 v[58:59], v[38:39] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[62:63], v[47:48] v_rcp_f64_e32 v[68:69], v[52:53] v_fma_f64 v[70:71], -v[22:23], v[54:55], 1.0 v_fma_f64 v[72:73], -v[36:37], v[56:57], 1.0 s_delay_alu instid0(TRANS32_DEP_3) v_fma_f64 v[74:75], -v[38:39], v[58:59], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[76:77], -v[47:48], v[62:63], 1.0 v_fma_f64 v[78:79], -v[52:53], v[68:69], 1.0 v_fma_f64 v[54:55], v[54:55], v[70:71], v[54:55] v_fma_f64 v[56:57], v[56:57], v[72:73], v[56:57] v_fma_f64 v[58:59], v[58:59], v[74:75], v[58:59] v_fma_f64 v[62:63], v[62:63], v[76:77], v[62:63] v_fma_f64 v[68:69], v[68:69], v[78:79], v[68:69] v_fma_f64 v[70:71], -v[22:23], v[54:55], 1.0 v_fma_f64 v[72:73], -v[36:37], v[56:57], 1.0 v_fma_f64 v[74:75], -v[38:39], v[58:59], 1.0 v_fma_f64 v[76:77], -v[47:48], v[62:63], 1.0 v_fma_f64 v[78:79], -v[52:53], v[68:69], 1.0 v_fma_f64 v[54:55], v[54:55], v[70:71], v[54:55] v_div_scale_f64 v[70:71], s2, v[16:17], v[0:1], v[16:17] v_fma_f64 v[56:57], v[56:57], v[72:73], v[56:57] v_div_scale_f64 v[72:73], s3, v[28:29], v[26:27], v[28:29] v_fma_f64 v[58:59], v[58:59], v[74:75], v[58:59] v_div_scale_f64 v[74:75], s4, v[32:33], v[30:31], v[32:33] v_fma_f64 v[62:63], v[62:63], v[76:77], v[62:63] v_div_scale_f64 v[76:77], s5, v[14:15], v[34:35], v[14:15] v_fma_f64 v[68:69], v[68:69], v[78:79], v[68:69] v_mul_f64 v[78:79], v[80:81], v[54:55] v_mul_f64 v[82:83], v[70:71], v[56:57] v_mul_f64 v[84:85], v[72:73], v[58:59] v_mul_f64 v[86:87], v[74:75], v[62:63] v_mul_f64 v[88:89], v[76:77], v[68:69] v_fma_f64 v[22:23], -v[22:23], v[78:79], v[80:81] v_fma_f64 v[36:37], -v[36:37], v[82:83], v[70:71] v_fma_f64 v[38:39], -v[38:39], v[84:85], v[72:73] v_fma_f64 v[47:48], -v[47:48], v[86:87], v[74:75] v_fma_f64 v[52:53], -v[52:53], v[88:89], v[76:77] v_div_fmas_f64 v[22:23], v[22:23], v[54:55], v[78:79] s_mov_b32 vcc_lo, s2 v_div_fmas_f64 v[36:37], v[36:37], v[56:57], v[82:83] s_mov_b32 vcc_lo, s3 v_div_fmas_f64 v[38:39], v[38:39], v[58:59], v[84:85] s_mov_b32 vcc_lo, s4 v_div_fmas_f64 v[47:48], v[47:48], v[62:63], v[86:87] s_mov_b32 vcc_lo, s5 v_div_fmas_f64 v[52:53], v[52:53], v[68:69], v[88:89] v_div_fixup_f64 v[12:13], v[22:23], v[24:25], v[12:13] v_div_fixup_f64 v[16:17], v[36:37], v[0:1], v[16:17] v_add_f64 v[0:1], -v[0:1], 0 v_div_fixup_f64 v[22:23], v[38:39], v[26:27], v[28:29] v_div_fixup_f64 v[24:25], v[47:48], v[30:31], v[32:33] v_div_fixup_f64 v[14:15], v[52:53], v[34:35], v[14:15] v_add_f64 v[12:13], v[12:13], -v[16:17] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[26:27], v[16:17], -v[22:23] v_add_f64 v[28:29], v[22:23], -v[24:25] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64 v[14:15], v[24:25], -v[14:15] v_div_scale_f64 v[32:33], null, v[2:3], v[2:3], v[12:13] v_div_scale_f64 v[72:73], vcc_lo, v[12:13], v[2:3], v[12:13] v_div_scale_f64 v[34:35], null, v[10:11], v[10:11], v[26:27] v_div_scale_f64 v[36:37], null, v[6:7], v[6:7], v[28:29] v_div_scale_f64 v[38:39], null, v[8:9], v[8:9], v[14:15] v_rcp_f64_e32 v[47:48], v[32:33] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_rcp_f64_e32 v[52:53], v[34:35] v_rcp_f64_e32 v[54:55], v[36:37] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3) v_rcp_f64_e32 v[56:57], v[38:39] v_fma_f64 v[58:59], -v[32:33], v[47:48], 1.0 v_fma_f64 v[62:63], -v[34:35], v[52:53], 1.0 s_waitcnt_depctr 0xfff v_fma_f64 v[68:69], -v[36:37], v[54:55], 1.0 v_fma_f64 v[70:71], -v[38:39], v[56:57], 1.0 v_fma_f64 v[47:48], v[47:48], v[58:59], v[47:48] v_fma_f64 v[52:53], v[52:53], v[62:63], v[52:53] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[54:55], v[54:55], v[68:69], v[54:55] v_fma_f64 v[56:57], v[56:57], v[70:71], v[56:57] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[58:59], -v[32:33], v[47:48], 1.0 v_fma_f64 v[62:63], -v[34:35], v[52:53], 1.0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[68:69], -v[36:37], v[54:55], 1.0 v_fma_f64 v[70:71], -v[38:39], v[56:57], 1.0 s_delay_alu instid0(VALU_DEP_4) v_fma_f64 v[47:48], v[47:48], v[58:59], v[47:48] v_div_scale_f64 v[58:59], s2, v[26:27], v[10:11], v[26:27] v_fma_f64 v[52:53], v[52:53], v[62:63], v[52:53] v_div_scale_f64 v[62:63], s3, v[28:29], v[6:7], v[28:29] v_fma_f64 v[54:55], v[54:55], v[68:69], v[54:55] v_div_scale_f64 v[68:69], s4, v[14:15], v[8:9], v[14:15] v_fma_f64 v[56:57], v[56:57], v[70:71], v[56:57] v_mul_f64 v[70:71], v[72:73], v[47:48] v_mul_f64 v[74:75], v[58:59], v[52:53] v_mul_f64 v[76:77], v[62:63], v[54:55] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_mul_f64 v[78:79], v[68:69], v[56:57] v_fma_f64 v[32:33], -v[32:33], v[70:71], v[72:73] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[34:35], -v[34:35], v[74:75], v[58:59] v_fma_f64 v[36:37], -v[36:37], v[76:77], v[62:63] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_fma_f64 v[38:39], -v[38:39], v[78:79], v[68:69] v_div_fmas_f64 v[32:33], v[32:33], v[47:48], v[70:71] s_mov_b32 vcc_lo, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_div_fmas_f64 v[34:35], v[34:35], v[52:53], v[74:75] s_mov_b32 vcc_lo, s3 v_div_fmas_f64 v[36:37], v[36:37], v[54:55], v[76:77] s_mov_b32 vcc_lo, s4 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_div_fmas_f64 v[38:39], v[38:39], v[56:57], v[78:79] v_div_fixup_f64 v[2:3], v[32:33], v[2:3], v[12:13] v_add_f64 v[12:13], -v[60:61], 0 v_div_fixup_f64 v[10:11], v[34:35], v[10:11], v[26:27] v_mul_f64 v[26:27], v[4:5], v[30:31] v_div_fixup_f64 v[6:7], v[36:37], v[6:7], v[28:29] v_div_fixup_f64 v[8:9], v[38:39], v[8:9], v[14:15] v_mul_f64 v[0:1], v[12:13], v[0:1] v_mul_f64 v[14:15], v[12:13], v[4:5] v_cmp_lt_f64_e64 vcc_lo, |v[10:11]|, |v[2:3]| v_cmp_lt_f64_e64 s2, |v[6:7]|, |v[10:11]| v_cmp_lt_f64_e64 s3, |v[6:7]|, |v[8:9]| v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10 v_cmp_lt_f64_e64 vcc_lo, |v[22:23]|, |v[16:17]| s_delay_alu instid0(VALU_DEP_4) v_cndmask_b32_e64 v11, v11, v7, s2 v_cndmask_b32_e64 v10, v10, v6, s2 v_cmp_lt_f64_e64 s2, |v[24:25]|, |v[22:23]| v_cndmask_b32_e64 v7, v9, v7, s3 v_cndmask_b32_e64 v6, v8, v6, s3 v_mul_f64 v[0:1], v[0:1], v[2:3] v_mul_f64 v[2:3], v[14:15], v[10:11] v_mul_f64 v[8:9], v[22:23], v[24:25] v_mul_f64 v[10:11], v[16:17], v[22:23] v_mul_f64 v[6:7], v[26:27], v[6:7] v_dual_cndmask_b32 v14, v17, v23 :: v_dual_cndmask_b32 v15, v16, v22 v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v0, v0, v2 v_cmp_ngt_f64_e64 s3, 0, v[8:9] v_cmp_ngt_f64_e64 s4, 0, v[10:11] v_cndmask_b32_e64 v7, v3, v7, s2 v_cndmask_b32_e64 v3, v23, v25, s2 v_cndmask_b32_e64 v8, v22, v24, s2 v_cndmask_b32_e64 v6, v2, v6, s2 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v11, 0, v3, s3 v_cndmask_b32_e64 v9, 0, v14, s4 v_cndmask_b32_e64 v10, 0, v8, s3 v_cndmask_b32_e64 v8, 0, v15, s4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[3:4], v[4:5], v[10:11], v[20:21] v_fma_f64 v[8:9], v[12:13], v[8:9], v[18:19] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f64 v[52:53], v[3:4], v[6:7] v_add_f64 v[0:1], v[8:9], v[0:1] .LBB4_37: ; %Flow446 s_or_b32 exec_lo, exec_lo, s7 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x18 s_load_b64 s[2:3], s[0:1], 0x28 v_lshlrev_b64 v[2:3], 3, v[66:67] s_waitcnt vmcnt(2) lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v4, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo s_waitcnt vmcnt(0) v_add_co_u32 v6, vcc_lo, s6, v2 v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo global_load_b64 v[4:5], v[4:5], off v_add_co_u32 v8, vcc_lo, s2, v2 global_load_b64 v[6:7], v[6:7], off v_add_co_ci_u32_e32 v9, vcc_lo, s3, v3, vcc_lo s_load_b64 s[2:3], s[0:1], 0x8 global_load_b64 v[8:9], v[8:9], off s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_load_b64 v[2:3], v[2:3], off s_waitcnt vmcnt(3) v_max_f64 v[10:11], v[4:5], v[4:5] v_cmp_nlt_f64_e32 vcc_lo, 0, v[4:5] s_waitcnt vmcnt(2) v_max_f64 v[12:13], v[6:7], v[6:7] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_max_f64 v[10:11], v[10:11], 0 v_dual_cndmask_b32 v5, 0, v5 :: v_dual_cndmask_b32 v4, 0, v4 v_cmp_nlt_f64_e32 vcc_lo, 0, v[6:7] v_mul_f64 v[10:11], v[41:42], v[10:11] v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6 s_waitcnt vmcnt(1) v_cmp_nlt_f64_e32 vcc_lo, 0, v[8:9] s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[4:5], v[43:44], v[4:5], v[10:11] v_max_f64 v[10:11], v[12:13], 0 v_fma_f64 v[4:5], v[50:51], v[6:7], v[4:5] v_max_f64 v[6:7], v[8:9], v[8:9] v_dual_cndmask_b32 v9, 0, v9 :: v_dual_cndmask_b32 v8, 0, v8 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[4:5], v[45:46], v[10:11], v[4:5] v_fma_f64 v[0:1], v[0:1], v[8:9], v[4:5] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_max_f64 v[4:5], v[6:7], 0 v_fma_f64 v[0:1], v[52:53], v[4:5], v[0:1] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[10:11], v[2:3], v[0:1] .LBB4_38: ; %Flow460 s_or_b32 exec_lo, exec_lo, s76 .LBB4_39: ; %Flow462 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s75 .LBB4_40: ; %Flow464 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s74 .LBB4_41: ; %Flow466 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s73 .LBB4_42: ; %Flow468 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s72 .LBB4_43: ; %.sink.split s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s63 s_load_b64 s[0:1], s[0:1], 0x0 s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v64 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v65, vcc_lo global_store_b64 v[0:1], v[10:11], off .LBB4_44: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 8 .amdhsa_kernarg_size 448 .amdhsa_user_sgpr_count 13 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 1 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 1 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 96 .amdhsa_next_free_sgpr 80 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end4: .size _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end4-_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 12260 ; NumSgprs: 82 ; NumVgprs: 96 ; ScratchSize: 8 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 10 ; VGPRBlocks: 11 ; NumSGPRsForWavesPerEU: 82 ; NumVGPRsForWavesPerEU: 96 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1 ; COMPUTE_PGM_RSRC2:USER_SGPR: 13 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .offset: 80 .size: 4 .value_kind: by_value - .offset: 84 .size: 4 .value_kind: by_value - .offset: 88 .size: 4 .value_kind: by_value - .offset: 96 .size: 8 .value_kind: by_value - .offset: 104 .size: 8 .value_kind: by_value - .offset: 112 .size: 8 .value_kind: by_value - .offset: 120 .size: 4 .value_kind: by_value - .offset: 128 .size: 4 .value_kind: hidden_block_count_x - .offset: 132 .size: 4 .value_kind: hidden_block_count_y - .offset: 136 .size: 4 .value_kind: hidden_block_count_z - .offset: 140 .size: 2 .value_kind: hidden_group_size_x - .offset: 142 .size: 2 .value_kind: hidden_group_size_y - .offset: 144 .size: 2 .value_kind: hidden_group_size_z - .offset: 146 .size: 2 .value_kind: hidden_remainder_x - .offset: 148 .size: 2 .value_kind: hidden_remainder_y - .offset: 150 .size: 2 .value_kind: hidden_remainder_z - .offset: 168 .size: 8 .value_kind: hidden_global_offset_x - .offset: 176 .size: 8 .value_kind: hidden_global_offset_y - .offset: 184 .size: 8 .value_kind: hidden_global_offset_z - .offset: 192 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 384 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .private_segment_fixed_size: 8 .sgpr_count: 76 .sgpr_spill_count: 0 .symbol: _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 88 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 88 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 96 .size: 8 .value_kind: global_buffer - .offset: 104 .size: 4 .value_kind: by_value - .offset: 108 .size: 4 .value_kind: by_value - .offset: 112 .size: 4 .value_kind: by_value - .offset: 120 .size: 8 .value_kind: by_value - .offset: 128 .size: 8 .value_kind: by_value - .offset: 136 .size: 8 .value_kind: by_value - .offset: 144 .size: 4 .value_kind: by_value - .offset: 152 .size: 4 .value_kind: hidden_block_count_x - .offset: 156 .size: 4 .value_kind: hidden_block_count_y - .offset: 160 .size: 4 .value_kind: hidden_block_count_z - .offset: 164 .size: 2 .value_kind: hidden_group_size_x - .offset: 166 .size: 2 .value_kind: hidden_group_size_y - .offset: 168 .size: 2 .value_kind: hidden_group_size_z - .offset: 170 .size: 2 .value_kind: hidden_remainder_x - .offset: 172 .size: 2 .value_kind: hidden_remainder_y - .offset: 174 .size: 2 .value_kind: hidden_remainder_z - .offset: 192 .size: 8 .value_kind: hidden_global_offset_x - .offset: 200 .size: 8 .value_kind: hidden_global_offset_y - .offset: 208 .size: 8 .value_kind: hidden_global_offset_z - .offset: 216 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 408 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .private_segment_fixed_size: 8 .sgpr_count: 62 .sgpr_spill_count: 0 .symbol: _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 130 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 80 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 88 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 96 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 104 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 112 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 120 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 128 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 136 .size: 8 .value_kind: global_buffer - .offset: 144 .size: 4 .value_kind: by_value - .offset: 148 .size: 4 .value_kind: by_value - .offset: 152 .size: 4 .value_kind: by_value - .offset: 160 .size: 8 .value_kind: by_value - .offset: 168 .size: 8 .value_kind: by_value - .offset: 176 .size: 8 .value_kind: by_value - .offset: 184 .size: 4 .value_kind: by_value - .offset: 192 .size: 4 .value_kind: hidden_block_count_x - .offset: 196 .size: 4 .value_kind: hidden_block_count_y - .offset: 200 .size: 4 .value_kind: hidden_block_count_z - .offset: 204 .size: 2 .value_kind: hidden_group_size_x - .offset: 206 .size: 2 .value_kind: hidden_group_size_y - .offset: 208 .size: 2 .value_kind: hidden_group_size_z - .offset: 210 .size: 2 .value_kind: hidden_remainder_x - .offset: 212 .size: 2 .value_kind: hidden_remainder_y - .offset: 214 .size: 2 .value_kind: hidden_remainder_z - .offset: 232 .size: 8 .value_kind: hidden_global_offset_x - .offset: 240 .size: 8 .value_kind: hidden_global_offset_y - .offset: 248 .size: 8 .value_kind: hidden_global_offset_z - .offset: 256 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 448 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .private_segment_fixed_size: 8 .sgpr_count: 82 .sgpr_spill_count: 0 .symbol: _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 96 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "a9b385d32004ebe5994000f0a44fc78149530394.hip" .globl _Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi # -- Begin function _Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .p2align 4, 0x90 .type _Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi,@function _Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: # @_Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .cfi_startproc # %bb.0: subq $264, %rsp # imm = 0x108 .cfi_def_cfa_offset 272 movq %rdi, 120(%rsp) movq %rsi, 112(%rsp) movq %rdx, 104(%rsp) movq %rcx, 96(%rsp) movq %r8, 88(%rsp) movq %r9, 80(%rsp) movsd %xmm0, 72(%rsp) movsd %xmm1, 64(%rsp) movsd %xmm2, 56(%rsp) leaq 120(%rsp), %rax movq %rax, 128(%rsp) leaq 112(%rsp), %rax movq %rax, 136(%rsp) leaq 104(%rsp), %rax movq %rax, 144(%rsp) leaq 96(%rsp), %rax movq %rax, 152(%rsp) leaq 88(%rsp), %rax movq %rax, 160(%rsp) leaq 80(%rsp), %rax movq %rax, 168(%rsp) leaq 272(%rsp), %rax movq %rax, 176(%rsp) leaq 280(%rsp), %rax movq %rax, 184(%rsp) leaq 288(%rsp), %rax movq %rax, 192(%rsp) leaq 296(%rsp), %rax movq %rax, 200(%rsp) leaq 304(%rsp), %rax movq %rax, 208(%rsp) leaq 312(%rsp), %rax movq %rax, 216(%rsp) leaq 320(%rsp), %rax movq %rax, 224(%rsp) leaq 72(%rsp), %rax movq %rax, 232(%rsp) leaq 64(%rsp), %rax movq %rax, 240(%rsp) leaq 56(%rsp), %rax movq %rax, 248(%rsp) leaq 328(%rsp), %rax movq %rax, 256(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 128(%rsp), %r9 movl $_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $280, %rsp # imm = 0x118 .cfi_adjust_cfa_offset -280 retq .Lfunc_end0: .size _Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end0-_Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .cfi_endproc # -- End function .globl _Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi # -- Begin function _Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .p2align 4, 0x90 .type _Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi,@function _Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: # @_Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .cfi_startproc # %bb.0: subq $296, %rsp # imm = 0x128 .cfi_def_cfa_offset 304 movq %rdi, 120(%rsp) movq %rsi, 112(%rsp) movq %rdx, 104(%rsp) movq %rcx, 96(%rsp) movq %r8, 88(%rsp) movq %r9, 80(%rsp) movsd %xmm0, 72(%rsp) movsd %xmm1, 64(%rsp) movsd %xmm2, 56(%rsp) leaq 120(%rsp), %rax movq %rax, 128(%rsp) leaq 112(%rsp), %rax movq %rax, 136(%rsp) leaq 104(%rsp), %rax movq %rax, 144(%rsp) leaq 96(%rsp), %rax movq %rax, 152(%rsp) leaq 88(%rsp), %rax movq %rax, 160(%rsp) leaq 80(%rsp), %rax movq %rax, 168(%rsp) leaq 304(%rsp), %rax movq %rax, 176(%rsp) leaq 312(%rsp), %rax movq %rax, 184(%rsp) leaq 320(%rsp), %rax movq %rax, 192(%rsp) leaq 328(%rsp), %rax movq %rax, 200(%rsp) leaq 336(%rsp), %rax movq %rax, 208(%rsp) leaq 344(%rsp), %rax movq %rax, 216(%rsp) leaq 352(%rsp), %rax movq %rax, 224(%rsp) leaq 360(%rsp), %rax movq %rax, 232(%rsp) leaq 368(%rsp), %rax movq %rax, 240(%rsp) leaq 376(%rsp), %rax movq %rax, 248(%rsp) leaq 72(%rsp), %rax movq %rax, 256(%rsp) leaq 64(%rsp), %rax movq %rax, 264(%rsp) leaq 56(%rsp), %rax movq %rax, 272(%rsp) leaq 384(%rsp), %rax movq %rax, 280(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 128(%rsp), %r9 movl $_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $312, %rsp # imm = 0x138 .cfi_adjust_cfa_offset -312 retq .Lfunc_end1: .size _Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end1-_Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .cfi_endproc # -- End function .globl _Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi # -- Begin function _Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .p2align 4, 0x90 .type _Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@function _Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi: # @_Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .cfi_startproc # %bb.0: subq $328, %rsp # imm = 0x148 .cfi_def_cfa_offset 336 movq %rdi, 120(%rsp) movq %rsi, 112(%rsp) movq %rdx, 104(%rsp) movq %rcx, 96(%rsp) movq %r8, 88(%rsp) movq %r9, 80(%rsp) movsd %xmm0, 72(%rsp) movsd %xmm1, 64(%rsp) movsd %xmm2, 56(%rsp) leaq 120(%rsp), %rax movq %rax, 128(%rsp) leaq 112(%rsp), %rax movq %rax, 136(%rsp) leaq 104(%rsp), %rax movq %rax, 144(%rsp) leaq 96(%rsp), %rax movq %rax, 152(%rsp) leaq 88(%rsp), %rax movq %rax, 160(%rsp) leaq 80(%rsp), %rax movq %rax, 168(%rsp) leaq 336(%rsp), %rax movq %rax, 176(%rsp) leaq 344(%rsp), %rax movq %rax, 184(%rsp) leaq 352(%rsp), %rax movq %rax, 192(%rsp) leaq 360(%rsp), %rax movq %rax, 200(%rsp) leaq 368(%rsp), %rax movq %rax, 208(%rsp) leaq 376(%rsp), %rax movq %rax, 216(%rsp) leaq 384(%rsp), %rax movq %rax, 224(%rsp) leaq 392(%rsp), %rax movq %rax, 232(%rsp) leaq 400(%rsp), %rax movq %rax, 240(%rsp) leaq 408(%rsp), %rax movq %rax, 248(%rsp) leaq 416(%rsp), %rax movq %rax, 256(%rsp) leaq 424(%rsp), %rax movq %rax, 264(%rsp) leaq 432(%rsp), %rax movq %rax, 272(%rsp) leaq 440(%rsp), %rax movq %rax, 280(%rsp) leaq 448(%rsp), %rax movq %rax, 288(%rsp) leaq 72(%rsp), %rax movq %rax, 296(%rsp) leaq 64(%rsp), %rax movq %rax, 304(%rsp) leaq 56(%rsp), %rax movq %rax, 312(%rsp) leaq 456(%rsp), %rax movq %rax, 320(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 128(%rsp), %r9 movl $_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $344, %rsp # imm = 0x158 .cfi_adjust_cfa_offset -344 retq .Lfunc_end2: .size _Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end2-_Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi,@object # @_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .section .rodata,"a",@progbits .globl _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .p2align 3, 0x0 _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: .quad _Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .size _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, 8 .type _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi,@object # @_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .globl _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .p2align 3, 0x0 _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: .quad _Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .size _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, 8 .type _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@object # @_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .globl _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .p2align 3, 0x0 _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi: .quad _Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .size _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi" .size .L__unnamed_1, 52 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi" .size .L__unnamed_2, 65 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi" .size .L__unnamed_3, 76 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .addrsig_sym _Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .addrsig_sym _Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .addrsig_sym _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi .addrsig_sym _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
300,789
8,652
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197
code for sm_80 Function : _Z1kPiS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; ISETP.GE.AND P0, PT, R0, 0x1, PT ; @!P0 EXIT ; IADD3 R2, R0.reuse, -0x1, RZ ; UMOV UR4, URZ ; LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; ULDC.64 UR10, c[0x0][0x118] ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; @!P0 BRA 0x8f0 ; IADD3 R6, -R0, c[0x0][0x170], RZ ; UMOV UR4, URZ ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; MOV R5, c[0x0][0x16c] ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; ISETP.GT.AND P0, PT, R6, RZ, PT ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; @!P0 BRA 0x780 ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; @!P1 BRA 0x510 ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; LDG.E R7, [R2.64] ; IMAD.SHL.U32 R7, R7, 0x10, RZ ; STG.E [R4.64], R7 ; LDG.E R8, [R2.64+0x4] ; SHF.L.U32 R9, R8, 0x4, RZ ; STG.E [R4.64+0x4], R9 ; LDG.E R8, [R2.64+0x8] ; IMAD.SHL.U32 R11, R8, 0x10, RZ ; STG.E [R4.64+0x8], R11 ; LDG.E R8, [R2.64+0xc] ; IMAD.SHL.U32 R13, R8, 0x10, RZ ; STG.E [R4.64+0xc], R13 ; LDG.E R8, [R2.64+0x10] ; IMAD.SHL.U32 R7, R8, 0x10, RZ ; STG.E [R4.64+0x10], R7 ; LDG.E R8, [R2.64+0x14] ; SHF.L.U32 R9, R8, 0x4, RZ ; STG.E [R4.64+0x14], R9 ; LDG.E R8, [R2.64+0x18] ; IMAD.SHL.U32 R11, R8, 0x10, RZ ; STG.E [R4.64+0x18], R11 ; LDG.E R8, [R2.64+0x1c] ; IMAD.SHL.U32 R13, R8, 0x10, RZ ; STG.E [R4.64+0x1c], R13 ; LDG.E R8, [R2.64+0x20] ; IMAD.SHL.U32 R7, R8, 0x10, RZ ; STG.E [R4.64+0x20], R7 ; LDG.E R8, [R2.64+0x24] ; SHF.L.U32 R9, R8, 0x4, RZ ; STG.E [R4.64+0x24], R9 ; LDG.E R8, [R2.64+0x28] ; IMAD.SHL.U32 R11, R8, 0x10, RZ ; STG.E [R4.64+0x28], R11 ; LDG.E R8, [R2.64+0x2c] ; IMAD.SHL.U32 R13, R8, 0x10, RZ ; STG.E [R4.64+0x2c], R13 ; LDG.E R8, [R2.64+0x30] ; IMAD.SHL.U32 R7, R8, 0x10, RZ ; STG.E [R4.64+0x30], R7 ; LDG.E R8, [R2.64+0x34] ; SHF.L.U32 R9, R8, 0x4, RZ ; STG.E [R4.64+0x34], R9 ; LDG.E R8, [R2.64+0x38] ; IADD3 R6, R6, -0x10, RZ ; IMAD.SHL.U32 R11, R8, 0x10, RZ ; STG.E [R4.64+0x38], R11 ; LDG.E R8, [R2.64+0x3c] ; ISETP.GT.AND P1, PT, R6, 0xc, PT ; UIADD3 UR4, UR4, 0x10, URZ ; IADD3 R7, P3, R4, 0x40, RZ ; IADD3 R10, P2, R2, 0x40, RZ ; IMAD.X R3, RZ, RZ, R3, P2 ; IMAD.MOV.U32 R2, RZ, RZ, R10 ; IMAD.SHL.U32 R13, R8, 0x10, RZ ; IADD3.X R8, RZ, R5, RZ, P3, !PT ; STG.E [R4.64+0x3c], R13 ; IMAD.MOV.U32 R4, RZ, RZ, R7 ; MOV R5, R8 ; @P1 BRA 0x160 ; ISETP.GT.AND P1, PT, R6, 0x4, PT ; @!P1 BRA 0x760 ; LDG.E R7, [R2.64] ; IMAD.SHL.U32 R7, R7, 0x10, RZ ; STG.E [R4.64], R7 ; LDG.E R8, [R2.64+0x4] ; IMAD.SHL.U32 R9, R8, 0x10, RZ ; STG.E [R4.64+0x4], R9 ; LDG.E R8, [R2.64+0x8] ; SHF.L.U32 R11, R8, 0x4, RZ ; STG.E [R4.64+0x8], R11 ; LDG.E R8, [R2.64+0xc] ; IMAD.SHL.U32 R13, R8, 0x10, RZ ; STG.E [R4.64+0xc], R13 ; LDG.E R8, [R2.64+0x10] ; IMAD.SHL.U32 R7, R8, 0x10, RZ ; STG.E [R4.64+0x10], R7 ; LDG.E R8, [R2.64+0x14] ; SHF.L.U32 R9, R8, 0x4, RZ ; STG.E [R4.64+0x14], R9 ; LDG.E R8, [R2.64+0x18] ; IMAD.SHL.U32 R11, R8, 0x10, RZ ; STG.E [R4.64+0x18], R11 ; LDG.E R8, [R2.64+0x1c] ; IADD3 R7, P2, R4, 0x20, RZ ; UIADD3 UR4, UR4, 0x8, URZ ; IADD3 R10, P1, R2, 0x20, RZ ; PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; IADD3.X R9, RZ, R3, RZ, P1, !PT ; IADD3 R6, R6, -0x8, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R10 ; MOV R3, R9 ; IMAD.SHL.U32 R13, R8, 0x10, RZ ; IMAD.X R8, RZ, RZ, R5, P2 ; STG.E [R4.64+0x1c], R13 ; IMAD.MOV.U32 R4, RZ, RZ, R7 ; IMAD.MOV.U32 R5, RZ, RZ, R8 ; ISETP.NE.OR P0, PT, R6, RZ, P0 ; @!P0 BRA 0x8f0 ; LDG.E R7, [R2.64] ; SHF.L.U32 R7, R7, 0x4, RZ ; STG.E [R4.64], R7 ; LDG.E R8, [R2.64+0x4] ; IMAD.SHL.U32 R9, R8, 0x10, RZ ; STG.E [R4.64+0x4], R9 ; LDG.E R8, [R2.64+0x8] ; IADD3 R6, R6, -0x4, RZ ; IMAD.SHL.U32 R11, R8, 0x10, RZ ; STG.E [R4.64+0x8], R11 ; LDG.E R8, [R2.64+0xc] ; ISETP.NE.AND P0, PT, R6, RZ, PT ; UIADD3 UR4, UR4, 0x4, URZ ; IADD3 R7, P2, R4, 0x10, RZ ; IADD3 R10, P1, R2, 0x10, RZ ; IMAD.X R3, RZ, RZ, R3, P1 ; MOV R2, R10 ; SHF.L.U32 R13, R8, 0x4, RZ ; IMAD.X R8, RZ, RZ, R5, P2 ; STG.E [R4.64+0xc], R13 ; IMAD.MOV.U32 R4, RZ, RZ, R7 ; IMAD.MOV.U32 R5, RZ, RZ, R8 ; @P0 BRA 0x780 ; ISETP.NE.AND P0, PT, R0, RZ, PT ; @!P0 EXIT ; UMOV UR5, 0x4 ; ULDC.64 UR6, c[0x0][0x168] ; ULDC.64 UR8, c[0x0][0x160] ; UIMAD.WIDE UR6, UR4, UR5, UR6 ; UIMAD.WIDE UR4, UR4, UR5, UR8 ; MOV R2, UR4 ; IMAD.U32 R3, RZ, RZ, UR5 ; LDG.E R2, [R2.64] ; IADD3 R0, R0, -0x1, RZ ; IMAD.U32 R4, RZ, RZ, UR6 ; MOV R5, UR7 ; UIADD3 UR6, UP0, UR6, 0x4, URZ ; ISETP.NE.AND P0, PT, R0, RZ, PT ; UIADD3 UR4, UP1, UR4, 0x4, URZ ; UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; UIADD3.X UR5, URZ, UR5, URZ, UP1, !UPT ; IMAD.SHL.U32 R7, R2, 0x10, RZ ; STG.E [R4.64], R7 ; @P0 BRA 0x960 ; EXIT ; BRA 0xa50; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_00046f27_00000000-6_2020a46ed7b802e0c4e9d3dfa1d4027853178931.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z23__device_stub__Z1kPiS_iPiS_i .type _Z23__device_stub__Z1kPiS_iPiS_i, @function _Z23__device_stub__Z1kPiS_iPiS_i: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z1kPiS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z23__device_stub__Z1kPiS_iPiS_i, .-_Z23__device_stub__Z1kPiS_iPiS_i .globl _Z1kPiS_i .type _Z1kPiS_i, @function _Z1kPiS_i: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z23__device_stub__Z1kPiS_iPiS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z1kPiS_i, .-_Z1kPiS_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z1kPiS_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z1kPiS_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z1kPiS_i ; -- Begin function _Z1kPiS_i .globl _Z1kPiS_i .p2align 8 .type _Z1kPiS_i,@function _Z1kPiS_i: ; @_Z1kPiS_i ; %bb.0: s_load_b32 s4, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s4, 1 s_cbranch_scc1 .LBB0_3 ; %bb.1: ; %.lr.ph.preheader s_load_b128 s[0:3], s[0:1], 0x0 v_mov_b32_e32 v0, 0 .LBB0_2: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 s_waitcnt lgkmcnt(0) global_load_b32 v1, v0, s[0:1] s_add_i32 s4, s4, -1 s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_waitcnt vmcnt(0) v_lshlrev_b32_e32 v1, 4, v1 global_store_b32 v0, v1, s[2:3] s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 s_cmp_eq_u32 s4, 0 s_cbranch_scc0 .LBB0_2 .LBB0_3: ; %._crit_edge s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z1kPiS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 20 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 5 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z1kPiS_i, .Lfunc_end0-_Z1kPiS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 100 ; NumSgprs: 5 ; NumVgprs: 2 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 5 ; NumVGPRsForWavesPerEU: 2 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 20 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z1kPiS_i .private_segment_fixed_size: 0 .sgpr_count: 5 .sgpr_spill_count: 0 .symbol: _Z1kPiS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "2020a46ed7b802e0c4e9d3dfa1d4027853178931.hip" .globl _Z16__device_stub__kPiS_i # -- Begin function _Z16__device_stub__kPiS_i .p2align 4, 0x90 .type _Z16__device_stub__kPiS_i,@function _Z16__device_stub__kPiS_i: # @_Z16__device_stub__kPiS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z1kPiS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z16__device_stub__kPiS_i, .Lfunc_end0-_Z16__device_stub__kPiS_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z1kPiS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z1kPiS_i,@object # @_Z1kPiS_i .section .rodata,"a",@progbits .globl _Z1kPiS_i .p2align 3, 0x0 _Z1kPiS_i: .quad _Z16__device_stub__kPiS_i .size _Z1kPiS_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z1kPiS_i" .size .L__unnamed_1, 10 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z16__device_stub__kPiS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z1kPiS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
3,874
1,828
1,901
1,727
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code for sm_80 Function : _Z6solveUPfS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; I2F.U32.RP R4, c[0x0][0x0] ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x0], PT ; ULDC.64 UR6, c[0x0][0x118] ; MUFU.RCP R4, R4 ; IADD3 R2, R4, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.MOV R5, RZ, RZ, -R3 ; IMAD R5, R5, c[0x0][0x0], RZ ; IMAD.HI.U32 R0, R3, R5, R2 ; S2R R5, SR_TID.X ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; IMAD.HI.U32 R0, R0, c[0x0][0x170], RZ ; IMAD.MOV R3, RZ, RZ, -R0 ; IMAD R3, R3, R6, c[0x0][0x170] ; ISETP.GE.U32.AND P2, PT, R3, c[0x0][0x0], PT ; @P2 IADD3 R3, R3, -c[0x0][0x0], RZ ; @P2 IADD3 R0, R0, 0x1, RZ ; ISETP.GE.AND P2, PT, R2, 0x2, PT ; ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x0], PT ; @P1 IADD3 R0, R0, 0x1, RZ ; @!P0 LOP3.LUT R0, RZ, c[0x0][0x0], RZ, 0x33, !PT ; @!P2 BRA 0x9d0 ; IMAD R18, R0.reuse, R5, RZ ; LOP3.LUT R7, R0, 0x3, RZ, 0xc0, !PT ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; ISETP.NE.AND P0, PT, R5, RZ, PT ; IMAD.MOV.U32 R6, RZ, RZ, R4 ; IADD3 R4, R4, -0x1, RZ ; IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; BSSY B0, 0x340 ; IMAD.WIDE R2, R4, R9, c[0x0][0x160] ; @P0 BRA 0x330 ; IMAD R8, R4, c[0x0][0x170], R4 ; LDG.E R13, [R2.64] ; IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; LDG.E R8, [R8.64] ; MUFU.RCP R10, R8 ; FCHK P0, R13, R8 ; FFMA R11, -R8, R10, 1 ; FFMA R11, R10, R11, R10 ; FFMA R10, R13, R11, RZ ; FFMA R12, -R8, R10, R13 ; FFMA R11, R11, R12, R10 ; @!P0 BRA 0x320 ; IMAD.MOV.U32 R12, RZ, RZ, R8 ; MOV R8, 0x320 ; CALL.REL.NOINC 0xb40 ; STG.E [R2.64], R11 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P0, PT, R0, 0x1, PT ; @!P0 BRA 0x9a0 ; IADD3 R8, R0, -0x1, RZ ; UMOV UR4, URZ ; ISETP.NE.AND P2, PT, R7, RZ, PT ; ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; @!P0 BRA 0x6c0 ; IMAD.IADD R10, R0, 0x1, -R7 ; UMOV UR4, URZ ; IADD3 R13, R18, UR4, RZ ; IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; ISETP.GE.AND P1, PT, R13.reuse, R4, PT ; IMAD.WIDE R8, R13, R11, c[0x0][0x160] ; ISETP.LT.OR P1, PT, R13, RZ, P1 ; @!P1 IMAD R14, R13.reuse, c[0x0][0x170], R4 ; @!P1 LDG.E R12, [R8.64] ; @!P1 IMAD.WIDE R14, R14, R11, c[0x0][0x168] ; @!P1 LDG.E R17, [R2.64] ; @!P1 LDG.E R14, [R14.64] ; IADD3 R19, R13, 0x1, RZ ; ISETP.GE.AND P0, PT, R19, R4, PT ; ISETP.LT.OR P0, PT, R19, RZ, P0 ; @!P0 IMAD R16, R19, c[0x0][0x170], R4 ; @!P0 LDG.E R20, [R8.64+0x4] ; @!P1 FFMA R19, R17, -R14, R12 ; @!P0 IMAD.WIDE R16, R16, R11, c[0x0][0x168] ; @!P1 STG.E [R8.64], R19 ; @!P0 LDG.E R17, [R16.64] ; @!P0 LDG.E R12, [R2.64] ; IADD3 R15, R13, 0x2, RZ ; ISETP.GE.AND P1, PT, R15, R4, PT ; ISETP.LT.OR P1, PT, R15, RZ, P1 ; @!P1 IMAD R14, R15, c[0x0][0x170], R4 ; @!P1 IMAD.WIDE R14, R14, R11, c[0x0][0x168] ; @!P0 FFMA R21, R12, -R17, R20 ; @!P1 LDG.E R20, [R8.64+0x8] ; @!P0 STG.E [R8.64+0x4], R21 ; @!P1 LDG.E R15, [R14.64] ; @!P1 LDG.E R12, [R2.64] ; IADD3 R13, R13, 0x3, RZ ; ISETP.GE.AND P0, PT, R13, R4, PT ; ISETP.LT.OR P0, PT, R13, RZ, P0 ; @!P0 IMAD R16, R13, c[0x0][0x170], R4 ; @!P1 FFMA R17, R12, -R15, R20 ; @!P0 IMAD.WIDE R12, R16, R11, c[0x0][0x168] ; @!P0 LDG.E R16, [R8.64+0xc] ; @!P1 STG.E [R8.64+0x8], R17 ; @!P0 LDG.E R12, [R12.64] ; @!P0 LDG.E R11, [R2.64] ; IADD3 R10, R10, -0x4, RZ ; UIADD3 UR4, UR4, 0x4, URZ ; @!P0 FFMA R11, R11, -R12, R16 ; @!P0 STG.E [R8.64+0xc], R11 ; ISETP.NE.AND P0, PT, R10, RZ, PT ; @P0 BRA 0x3e0 ; @!P2 BRA 0x9a0 ; IADD3 R15, R18, UR4, RZ ; IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; BSSY B0, 0x7d0 ; ISETP.NE.AND P1, PT, R7, 0x1, PT ; ISETP.GE.AND P0, PT, R15.reuse, R4, PT ; IMAD.WIDE R8, R15, R17, c[0x0][0x160] ; ISETP.LT.OR P0, PT, R15, RZ, P0 ; @P0 BRA 0x7c0 ; IMAD R10, R15, c[0x0][0x170], R4 ; LDG.E R12, [R8.64] ; IMAD.WIDE R10, R10, R17, c[0x0][0x168] ; LDG.E R13, [R2.64] ; LDG.E R10, [R10.64] ; FFMA R13, R13, -R10, R12 ; STG.E [R8.64], R13 ; BSYNC B0 ; @!P1 BRA 0x9a0 ; IADD3 R11, R15, 0x1, RZ ; BSSY B0, 0x8c0 ; ISETP.NE.AND P1, PT, R7, 0x2, PT ; ISETP.GE.AND P0, PT, R11, R4, PT ; ISETP.LT.OR P0, PT, R11, RZ, P0 ; @P0 BRA 0x8b0 ; IMAD R10, R11, c[0x0][0x170], R4 ; LDG.E R12, [R2.64] ; IMAD.WIDE R10, R10, R17, c[0x0][0x168] ; LDG.E R13, [R8.64+0x4] ; LDG.E R11, [R10.64] ; FFMA R13, R12, -R11, R13 ; STG.E [R8.64+0x4], R13 ; BSYNC B0 ; @!P1 BRA 0x9a0 ; IADD3 R15, R15, 0x2, RZ ; BSSY B0, 0x9a0 ; ISETP.GE.AND P0, PT, R15, R4, PT ; ISETP.LT.OR P0, PT, R15, RZ, P0 ; @P0 BRA 0x990 ; IMAD R10, R15, c[0x0][0x170], R4 ; LDG.E R2, [R2.64] ; IMAD.WIDE R10, R10, R17, c[0x0][0x168] ; LDG.E R12, [R8.64+0x8] ; LDG.E R11, [R10.64] ; FFMA R13, R2, -R11, R12 ; STG.E [R8.64+0x8], R13 ; BSYNC B0 ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GT.AND P0, PT, R6, 0x2, PT ; @P0 BRA 0x1c0 ; ISETP.NE.AND P0, PT, R5, RZ, PT ; @P0 EXIT ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; LDG.E R5, [R4.64] ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; LDG.E R0, [R2.64] ; MUFU.RCP R6, R5 ; FCHK P0, R0, R5 ; FFMA R7, -R5, R6, 1 ; FFMA R7, R6, R7, R6 ; FFMA R6, R0, R7, RZ ; FFMA R8, -R5, R6, R0 ; FFMA R7, R7, R8, R6 ; @!P0 BRA 0xb20 ; IMAD.MOV.U32 R13, RZ, RZ, R0 ; MOV R8, 0xb10 ; IMAD.MOV.U32 R12, RZ, RZ, R5 ; CALL.REL.NOINC 0xb40 ; IMAD.MOV.U32 R7, RZ, RZ, R11 ; STG.E [R2.64], R7 ; EXIT ; SHF.R.U32.HI R11, RZ, 0x17, R12 ; BSSY B1, 0x1190 ; SHF.R.U32.HI R9, RZ, 0x17, R13.reuse ; LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; LOP3.LUT R14, R9, 0xff, RZ, 0xc0, !PT ; IMAD.MOV.U32 R9, RZ, RZ, R13 ; IADD3 R16, R11, -0x1, RZ ; IADD3 R15, R14, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R16, 0xfd, PT ; ISETP.GT.U32.OR P0, PT, R15, 0xfd, P0 ; @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; @!P0 BRA 0xd70 ; FSETP.GTU.FTZ.AND P0, PT, |R13|, +INF , PT ; FSETP.GTU.FTZ.AND P1, PT, |R12|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0x1170 ; LOP3.LUT P0, RZ, R12, 0x7fffffff, R9, 0xc8, !PT ; @!P0 BRA 0x1150 ; FSETP.NEU.FTZ.AND P2, PT, |R13|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P1, PT, |R12|, +INF , PT ; FSETP.NEU.FTZ.AND P0, PT, |R13|, +INF , PT ; @!P1 BRA !P2, 0x1150 ; LOP3.LUT P2, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; @P1 BRA 0x1130 ; LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; @P0 BRA 0x1100 ; ISETP.GE.AND P0, PT, R15, RZ, PT ; ISETP.GE.AND P1, PT, R16, RZ, PT ; @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; @!P0 FFMA R9, R13, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R12, R12, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R10, R10, 0x40, RZ ; LEA R13, R11, 0xc0800000, 0x17 ; BSSY B2, 0x10f0 ; IADD3 R14, R14, -0x7f, RZ ; IMAD.IADD R13, R12, 0x1, -R13 ; IMAD R9, R14.reuse, -0x800000, R9 ; MUFU.RCP R12, R13 ; FADD.FTZ R16, -R13, -RZ ; IADD3 R13, R14, 0x7f, -R11 ; IMAD.IADD R10, R13, 0x1, R10 ; FFMA R15, R12, R16, 1 ; FFMA R12, R12, R15, R12 ; FFMA R15, R9, R12, RZ ; FFMA R17, R16, R15, R9 ; FFMA R17, R12, R17, R15 ; FFMA R16, R16, R17, R9 ; FFMA R9, R12, R16, R17 ; SHF.R.U32.HI R11, RZ, 0x17, R9 ; LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; IMAD.IADD R14, R11, 0x1, R10 ; IADD3 R11, R14, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R11, 0xfe, PT ; @!P0 BRA 0x10d0 ; ISETP.GT.AND P0, PT, R14, 0xfe, PT ; @P0 BRA 0x10a0 ; ISETP.GE.AND P0, PT, R14, 0x1, PT ; @P0 BRA 0x10e0 ; ISETP.GE.AND P0, PT, R14, -0x18, PT ; LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0x10e0 ; FFMA.RZ R10, R12, R16.reuse, R17.reuse ; ISETP.NE.AND P2, PT, R14, RZ, PT ; FFMA.RM R11, R12, R16.reuse, R17.reuse ; ISETP.NE.AND P1, PT, R14, RZ, PT ; LOP3.LUT R13, R10, 0x7fffff, RZ, 0xc0, !PT ; FFMA.RP R10, R12, R16, R17 ; IADD3 R12, R14, 0x20, RZ ; IMAD.MOV R14, RZ, RZ, -R14 ; LOP3.LUT R13, R13, 0x800000, RZ, 0xfc, !PT ; FSETP.NEU.FTZ.AND P0, PT, R10, R11, PT ; SHF.L.U32 R12, R13, R12, RZ ; SEL R10, R14, RZ, P2 ; ISETP.NE.AND P1, PT, R12, RZ, P1 ; SHF.R.U32.HI R10, RZ, R10, R13 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R12, RZ, 0x1, R10 ; SEL R11, RZ, 0x1, !P0 ; LOP3.LUT R11, R11, 0x1, R12, 0xf8, !PT ; LOP3.LUT R11, R11, R10, RZ, 0xc0, !PT ; IMAD.IADD R12, R12, 0x1, R11 ; LOP3.LUT R9, R12, R9, RZ, 0xfc, !PT ; BRA 0x10e0 ; LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x10e0 ; IMAD R9, R10, 0x800000, R9 ; BSYNC B2 ; BRA 0x1180 ; LOP3.LUT R9, R12, 0x80000000, R9, 0x48, !PT ; LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x1180 ; LOP3.LUT R9, R12, 0x80000000, R9, 0x48, !PT ; BRA 0x1180 ; MUFU.RSQ R9, -QNAN ; BRA 0x1180 ; FADD.FTZ R9, R13, R12 ; BSYNC B1 ; IMAD.MOV.U32 R11, RZ, RZ, R9 ; IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; RET.REL.NODEC R8 0x0 ; BRA 0x11c0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z6solveLPfS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; I2F.U32.RP R4, c[0x0][0x0] ; IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; MUFU.RCP R4, R4 ; IADD3 R2, R4, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.MOV R5, RZ, RZ, -R3 ; IMAD R5, R5, c[0x0][0x0], RZ ; IMAD.HI.U32 R0, R3, R5, R2 ; IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; IMAD.HI.U32 R0, R0, c[0x0][0x170], RZ ; ISETP.GE.AND P1, PT, R2, 0x2, PT ; IMAD.MOV R3, RZ, RZ, -R0 ; IMAD R3, R3, R6, c[0x0][0x170] ; ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x0], PT ; @P0 IADD3 R3, R3, -c[0x0][0x0], RZ ; @!P1 EXIT ; S2R R5, SR_TID.X ; ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x0], PT ; IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; ULDC.64 UR6, c[0x0][0x118] ; @P0 IADD3 R0, R0, 0x1, RZ ; @P1 IADD3 R0, R0, 0x1, RZ ; @!P2 LOP3.LUT R0, RZ, c[0x0][0x0], RZ, 0x33, !PT ; LOP3.LUT R7, R0.reuse, 0x3, RZ, 0xc0, !PT ; IMAD R8, R0, R5, RZ ; IMAD.IADD R9, R0, 0x1, -R7 ; ISETP.GE.AND P0, PT, R0, 0x1, PT ; @!P0 BRA 0x840 ; IADD3 R2, R0, -0x1, RZ ; IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; IADD3 R10, R6, -0x1, RZ ; UMOV UR4, URZ ; ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; ISETP.NE.AND P2, PT, R7, RZ, PT ; IMAD.WIDE R2, R10, R11, c[0x0][0x160] ; @!P0 BRA 0x570 ; IMAD.MOV.U32 R12, RZ, RZ, R9 ; UMOV UR4, URZ ; IADD3 R13, R8, UR4, RZ ; IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; ISETP.GE.AND P1, PT, R13.reuse, R6, PT ; IMAD.WIDE R4, R13, R11, c[0x0][0x160] ; ISETP.GE.OR P1, PT, R13, c[0x0][0x170], !P1 ; @!P1 IMAD R14, R13.reuse, c[0x0][0x170], R10 ; @!P1 LDG.E R16, [R2.64] ; @!P1 IMAD.WIDE R14, R14, R11, c[0x0][0x168] ; @!P1 LDG.E R17, [R4.64] ; @!P1 LDG.E R15, [R14.64] ; IADD3 R19, R13, 0x1, RZ ; ISETP.GE.AND P0, PT, R19, R6, PT ; ISETP.GE.OR P0, PT, R19, c[0x0][0x170], !P0 ; @!P0 IMAD R18, R19, c[0x0][0x170], R10 ; @!P0 LDG.E R20, [R4.64+0x4] ; @!P1 FFMA R19, R16, -R15, R17 ; @!P0 IMAD.WIDE R16, R18, R11, c[0x0][0x168] ; @!P1 STG.E [R4.64], R19 ; @!P0 LDG.E R17, [R16.64] ; @!P0 LDG.E R18, [R2.64] ; IADD3 R15, R13, 0x2, RZ ; ISETP.GE.AND P1, PT, R15, R6, PT ; ISETP.GE.OR P1, PT, R15, c[0x0][0x170], !P1 ; @!P1 IMAD R14, R15, c[0x0][0x170], R10 ; @!P1 IMAD.WIDE R14, R14, R11, c[0x0][0x168] ; @!P0 FFMA R21, R18, -R17, R20 ; @!P1 LDG.E R18, [R4.64+0x8] ; @!P0 STG.E [R4.64+0x4], R21 ; @!P1 LDG.E R15, [R14.64] ; @!P1 LDG.E R16, [R2.64] ; IADD3 R13, R13, 0x3, RZ ; ISETP.GE.AND P0, PT, R13, R6, PT ; ISETP.GE.OR P0, PT, R13, c[0x0][0x170], !P0 ; @!P0 IMAD R20, R13, c[0x0][0x170], R10 ; @!P1 FFMA R13, R16, -R15, R18 ; @!P0 IMAD.WIDE R16, R20, R11, c[0x0][0x168] ; @!P0 LDG.E R18, [R4.64+0xc] ; @!P1 STG.E [R4.64+0x8], R13 ; @!P0 LDG.E R17, [R16.64] ; @!P0 LDG.E R14, [R2.64] ; IADD3 R12, R12, -0x4, RZ ; UIADD3 UR4, UR4, 0x4, URZ ; @!P0 FFMA R15, R14, -R17, R18 ; @!P0 STG.E [R4.64+0xc], R15 ; ISETP.NE.AND P0, PT, R12, RZ, PT ; @P0 BRA 0x290 ; @!P2 BRA 0x840 ; IADD3 R17, R8, UR4, RZ ; BSSY B0, 0x670 ; ISETP.NE.AND P1, PT, R7, 0x1, PT ; ISETP.GE.AND P0, PT, R17.reuse, R6, PT ; IMAD.WIDE R4, R17, R11, c[0x0][0x160] ; ISETP.GE.OR P0, PT, R17, c[0x0][0x170], !P0 ; @P0 BRA 0x660 ; IMAD R12, R17, c[0x0][0x170], R10 ; LDG.E R14, [R2.64] ; IMAD.WIDE R12, R12, R11, c[0x0][0x168] ; LDG.E R15, [R4.64] ; LDG.E R13, [R12.64] ; FFMA R15, R14, -R13, R15 ; STG.E [R4.64], R15 ; BSYNC B0 ; @!P1 BRA 0x840 ; IADD3 R13, R17, 0x1, RZ ; BSSY B0, 0x760 ; ISETP.NE.AND P1, PT, R7, 0x2, PT ; ISETP.GE.AND P0, PT, R13, R6, PT ; ISETP.GE.OR P0, PT, R13, c[0x0][0x170], !P0 ; @P0 BRA 0x750 ; IMAD R12, R13, c[0x0][0x170], R10 ; LDG.E R14, [R2.64] ; IMAD.WIDE R12, R12, R11, c[0x0][0x168] ; LDG.E R15, [R4.64+0x4] ; LDG.E R13, [R12.64] ; FFMA R15, R14, -R13, R15 ; STG.E [R4.64+0x4], R15 ; BSYNC B0 ; @!P1 BRA 0x840 ; IADD3 R17, R17, 0x2, RZ ; BSSY B0, 0x840 ; ISETP.GE.AND P0, PT, R17, R6, PT ; ISETP.GE.OR P0, PT, R17, c[0x0][0x170], !P0 ; @P0 BRA 0x830 ; IMAD R10, R17, c[0x0][0x170], R10 ; LDG.E R2, [R2.64] ; IMAD.WIDE R10, R10, R11, c[0x0][0x168] ; LDG.E R12, [R4.64+0x8] ; LDG.E R11, [R10.64] ; FFMA R13, R2, -R11, R12 ; STG.E [R4.64+0x8], R13 ; BSYNC B0 ; IADD3 R6, R6, 0x1, RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; @!P0 BRA 0x1d0 ; EXIT ; BRA 0x890; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z2LUPfii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; I2F.U32.RP R0, c[0x0][0x0] ; HFMA2.MMA R2, -RZ, RZ, 0, 0 ; ULDC UR5, c[0x0][0x168] ; ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; UISETP.GE.AND UP0, UPT, UR5, 0x2, UPT ; PLOP3.LUT P3, PT, PT, PT, UP0, 0x80, 0x0 ; MUFU.RCP R0, R0 ; IADD3 R3, R0, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; IMAD.MOV R5, RZ, RZ, -R3 ; IMAD R5, R5, c[0x0][0x0], RZ ; IMAD.HI.U32 R2, R3, R5, R2 ; IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; IMAD.HI.U32 R2, R2, c[0x0][0x168], RZ ; IADD3 R4, -R2, RZ, RZ ; IMAD R0, R4, R5, c[0x0][0x168] ; ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; @P0 IADD3 R0, R0, -c[0x0][0x0], RZ ; ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x0], PT ; @!P3 EXIT ; S2R R3, SR_TID.X ; @P0 IADD3 R2, R2, 0x1, RZ ; UIADD3 UR5, UR5, -0x1, URZ ; UMOV UR4, URZ ; @P1 IADD3 R2, R2, 0x1, RZ ; ULDC.64 UR16, c[0x0][0x118] ; @!P2 LOP3.LUT R2, RZ, c[0x0][0x0], RZ, 0x33, !PT ; LOP3.LUT R5, R2.reuse, 0x3, RZ, 0xc0, !PT ; IADD3 R4, R2, -0x1, RZ ; IMAD.IADD R6, R2, 0x1, -R5 ; ISETP.GE.AND P0, PT, R2, 0x1, PT ; @!P0 BRA 0x1d60 ; ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; ULDC UR6, c[0x0][0x168] ; HFMA2.MMA R14, -RZ, RZ, 0, 2.384185791015625e-07 ; UIMAD UR6, UR4, UR6, UR4 ; MOV R8, RZ ; IMAD.U32 R15, RZ, RZ, UR6 ; IMAD.WIDE R14, R15, R14, c[0x0][0x160] ; @!P0 BRA 0x930 ; IMAD.MOV.U32 R8, RZ, RZ, RZ ; MOV R7, R6 ; IMAD R20, R8, c[0x0][0x0], R3 ; IADD3 R7, R7, -0x4, RZ ; BSSY B2, 0x460 ; ISETP.GE.AND P0, PT, R20.reuse, c[0x0][0x168], PT ; ISETP.NE.AND P2, PT, R7, RZ, PT ; ISETP.LE.OR P0, PT, R20, UR4, P0 ; @P0 BRA 0x450 ; HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; LDG.E R19, [R14.64] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x168] ; IMAD R16, R20, R9, UR4 ; IMAD.WIDE R16, R16, R17, c[0x0][0x160] ; LDG.E R12, [R16.64] ; BSSY B3, 0x440 ; MUFU.RCP R0, R19 ; FCHK P0, R12, R19 ; FFMA R9, -R19, R0, 1 ; FFMA R9, R0, R9, R0 ; FFMA R0, R12, R9, RZ ; FFMA R10, -R19, R0, R12 ; FFMA R9, R9, R10, R0 ; @!P0 BRA 0x430 ; MOV R0, 0x430 ; CALL.REL.NOINC 0x1dd0 ; BSYNC B3 ; STG.E [R16.64], R9 ; BSYNC B2 ; IADD3 R20, R20, c[0x0][0x0], RZ ; BSSY B2, 0x5f0 ; ISETP.GE.AND P0, PT, R20, c[0x0][0x168], PT ; ISETP.LE.OR P0, PT, R20, UR4, P0 ; @P0 BRA 0x5e0 ; LDG.E R19, [R14.64] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x168] ; MOV R17, 0x4 ; IMAD R16, R20, R9, UR4 ; IMAD.WIDE R16, R16, R17, c[0x0][0x160] ; LDG.E R12, [R16.64] ; BSSY B3, 0x5d0 ; MUFU.RCP R0, R19 ; FCHK P0, R12, R19 ; FFMA R9, -R19, R0, 1 ; FFMA R9, R0, R9, R0 ; FFMA R0, R12, R9, RZ ; FFMA R10, -R19, R0, R12 ; FFMA R9, R9, R10, R0 ; @!P0 BRA 0x5c0 ; MOV R0, 0x5c0 ; CALL.REL.NOINC 0x1dd0 ; BSYNC B3 ; STG.E [R16.64], R9 ; BSYNC B2 ; IADD3 R20, R20, c[0x0][0x0], RZ ; BSSY B2, 0x780 ; ISETP.GE.AND P0, PT, R20, c[0x0][0x168], PT ; ISETP.LE.OR P0, PT, R20, UR4, P0 ; @P0 BRA 0x770 ; HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; LDG.E R19, [R14.64] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x168] ; IMAD R16, R20, R9, UR4 ; IMAD.WIDE R16, R16, R17, c[0x0][0x160] ; LDG.E R12, [R16.64] ; BSSY B3, 0x760 ; MUFU.RCP R0, R19 ; FCHK P0, R12, R19 ; FFMA R9, -R19, R0, 1 ; FFMA R9, R0, R9, R0 ; FFMA R0, R12, R9, RZ ; FFMA R10, -R19, R0, R12 ; FFMA R9, R9, R10, R0 ; @!P0 BRA 0x750 ; MOV R0, 0x750 ; CALL.REL.NOINC 0x1dd0 ; BSYNC B3 ; STG.E [R16.64], R9 ; BSYNC B2 ; IADD3 R16, R20, c[0x0][0x0], RZ ; BSSY B2, 0x910 ; ISETP.GE.AND P0, PT, R16, c[0x0][0x168], PT ; ISETP.LE.OR P0, PT, R16, UR4, P0 ; @P0 BRA 0x900 ; LDG.E R19, [R14.64] ; IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x168] ; MOV R17, 0x4 ; IMAD R16, R16, R9, UR4 ; IMAD.WIDE R16, R16, R17, c[0x0][0x160] ; LDG.E R12, [R16.64] ; BSSY B3, 0x8f0 ; MUFU.RCP R0, R19 ; FCHK P0, R12, R19 ; FFMA R9, -R19, R0, 1 ; FFMA R9, R0, R9, R0 ; FFMA R0, R12, R9, RZ ; FFMA R10, -R19, R0, R12 ; FFMA R9, R9, R10, R0 ; @!P0 BRA 0x8e0 ; MOV R0, 0x8e0 ; CALL.REL.NOINC 0x1dd0 ; BSYNC B3 ; STG.E [R16.64], R9 ; BSYNC B2 ; IADD3 R8, R8, 0x4, RZ ; @P2 BRA 0x2b0 ; ISETP.NE.AND P0, PT, R5, RZ, PT ; @!P0 BRA 0xe40 ; IMAD R7, R8, c[0x0][0x0], R3 ; BSSY B2, 0xae0 ; ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; ISETP.LE.OR P0, PT, R7, UR4, P0 ; @P0 BRA 0xad0 ; HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; LDG.E R19, [R14.64] ; IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x168] ; IMAD R16, R7, R16, UR4 ; IMAD.WIDE R16, R16, R17, c[0x0][0x160] ; LDG.E R12, [R16.64] ; BSSY B3, 0xac0 ; MUFU.RCP R0, R19 ; FCHK P0, R12, R19 ; FFMA R9, -R19, R0, 1 ; FFMA R9, R0, R9, R0 ; FFMA R0, R12, R9, RZ ; FFMA R8, -R19, R0, R12 ; FFMA R9, R9, R8, R0 ; @!P0 BRA 0xab0 ; MOV R0, 0xab0 ; CALL.REL.NOINC 0x1dd0 ; BSYNC B3 ; STG.E [R16.64], R9 ; BSYNC B2 ; ISETP.NE.AND P0, PT, R5, 0x1, PT ; @!P0 BRA 0xe40 ; IADD3 R7, R7, c[0x0][0x0], RZ ; BSSY B2, 0xc90 ; ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; ISETP.LE.OR P0, PT, R7, UR4, P0 ; @P0 BRA 0xc80 ; LDG.E R19, [R14.64] ; IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x168] ; MOV R17, 0x4 ; IMAD R16, R7, R16, UR4 ; IMAD.WIDE R16, R16, R17, c[0x0][0x160] ; LDG.E R12, [R16.64] ; BSSY B3, 0xc70 ; MUFU.RCP R0, R19 ; FCHK P0, R12, R19 ; FFMA R9, -R19, R0, 1 ; FFMA R9, R0, R9, R0 ; FFMA R0, R12, R9, RZ ; FFMA R8, -R19, R0, R12 ; FFMA R9, R9, R8, R0 ; @!P0 BRA 0xc60 ; MOV R0, 0xc60 ; CALL.REL.NOINC 0x1dd0 ; BSYNC B3 ; STG.E [R16.64], R9 ; BSYNC B2 ; ISETP.NE.AND P0, PT, R5, 0x2, PT ; @!P0 BRA 0xe40 ; IADD3 R7, R7, c[0x0][0x0], RZ ; BSSY B2, 0xe40 ; ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; ISETP.LE.OR P0, PT, R7, UR4, P0 ; @P0 BRA 0xe30 ; HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; LDG.E R19, [R14.64] ; IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x168] ; IMAD R16, R7, R16, UR4 ; IMAD.WIDE R16, R16, R17, c[0x0][0x160] ; LDG.E R12, [R16.64] ; BSSY B3, 0xe20 ; MUFU.RCP R0, R19 ; FCHK P0, R12, R19 ; FFMA R7, -R19, R0, 1 ; FFMA R7, R0, R7, R0 ; FFMA R0, R12, R7, RZ ; FFMA R8, -R19, R0, R12 ; FFMA R9, R7, R8, R0 ; @!P0 BRA 0xe10 ; MOV R0, 0xe10 ; CALL.REL.NOINC 0x1dd0 ; BSYNC B3 ; STG.E [R16.64], R9 ; BSYNC B2 ; UIADD3 UR8, UR4, 0x1, URZ ; ULDC UR6, c[0x0][0x168] ; UISETP.GE.AND UP0, UPT, UR8, UR6, UPT ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; @P0 BRA 0x1d60 ; ULOP3.LUT UR6, URZ, UR4, URZ, 0x33, !UPT ; IMAD.MOV.U32 R0, RZ, RZ, RZ ; ULDC UR9, c[0x0][0x168] ; UMOV UR7, 0x2 ; UIADD3 UR6, UR6, UR9, URZ ; UIADD3 UR7, -UR4, UR9, -UR7 ; UIADD3 UR10, UR4, 0x2, URZ ; UIADD3 UR11, UR4, 0x3, URZ ; UIADD3 UR12, UR4, 0x4, URZ ; ULOP3.LUT UR9, UR6, 0x3, URZ, 0xc0, !UPT ; UISETP.GE.U32.AND UP1, UPT, UR7, 0x3, UPT ; IMAD R12, R0.reuse, c[0x0][0x0], R3 ; IADD3 R0, R0, 0x1, RZ ; BSSY B0, 0x1d50 ; ISETP.GE.AND P0, PT, R12, c[0x0][0x168], PT ; ISETP.GE.AND P1, PT, R0, R2, PT ; ISETP.LE.OR P0, PT, R12, UR4, P0 ; @P0 BRA 0x1d40 ; ISETP.NE.AND P0, PT, RZ, UR9, PT ; IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; MOV R7, c[0x0][0x168] ; UMOV UR6, UR8 ; IMAD R8, R12, R7, UR4 ; IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; @!P0 BRA 0x11a0 ; LDG.E R7, [R14.64+0x4] ; LDG.E R10, [R8.64] ; LDG.E R11, [R8.64+0x4] ; UISETP.NE.AND UP0, UPT, UR9, 0x1, UPT ; UMOV UR6, UR10 ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; FFMA R7, R7, -R10, R11 ; STG.E [R8.64+0x4], R7 ; @!P0 BRA 0x11a0 ; LDG.E R7, [R14.64+0x8] ; LDG.E R10, [R8.64] ; LDG.E R11, [R8.64+0x8] ; UISETP.NE.AND UP0, UPT, UR9, 0x2, UPT ; UMOV UR6, UR11 ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; FFMA R7, R7, -R10, R11 ; STG.E [R8.64+0x8], R7 ; @!P0 BRA 0x11a0 ; LDG.E R7, [R14.64+0xc] ; LDG.E R10, [R8.64] ; LDG.E R11, [R8.64+0xc] ; UMOV UR6, UR12 ; FFMA R7, R7, -R10, R11 ; STG.E [R8.64+0xc], R7 ; PLOP3.LUT P0, PT, PT, PT, UP1, 0x80, 0x0 ; @!P0 BRA 0x1d40 ; ULDC UR13, c[0x0][0x168] ; MOV R7, c[0x0][0x168] ; UIADD3 UR7, -UR6, UR13, URZ ; IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x160] ; ULDC UR14, c[0x0][0x168] ; MOV R19, c[0x0][0x164] ; UISETP.GT.AND UP0, UPT, UR7, 0xc, UPT ; IMAD R7, R12, R7, UR6 ; UIMAD UR13, UR4, UR13, UR6 ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; UPLOP3.LUT UP0, UPT, UPT, UPT, UPT, 0x80, 0x0 ; @!P0 BRA 0x1860 ; ULDC UR7, c[0x0][0x168] ; UPLOP3.LUT UP0, UPT, UPT, UPT, UPT, 0x40, 0x0 ; UIADD3 UR7, UR7, -0xc, URZ ; MOV R10, R18 ; IMAD.U32 R17, RZ, RZ, UR13 ; IMAD.MOV.U32 R11, RZ, RZ, R19 ; LDG.E R19, [R8.64] ; IMAD.WIDE R12, R7, 0x4, R10 ; IMAD.WIDE R16, R17, 0x4, R10 ; LDG.E R20, [R12.64] ; LDG.E R18, [R16.64] ; FFMA R19, R18, -R19, R20 ; LDG.E R20, [R12.64+0x4] ; STG.E [R12.64], R19 ; LDG.E R18, [R16.64+0x4] ; LDG.E R21, [R8.64] ; FFMA R21, R18, -R21, R20 ; LDG.E R20, [R12.64+0x8] ; STG.E [R12.64+0x4], R21 ; LDG.E R18, [R16.64+0x8] ; LDG.E R23, [R8.64] ; FFMA R23, R18, -R23, R20 ; LDG.E R20, [R12.64+0xc] ; STG.E [R12.64+0x8], R23 ; LDG.E R18, [R16.64+0xc] ; LDG.E R19, [R8.64] ; FFMA R19, R18, -R19, R20 ; LDG.E R20, [R12.64+0x10] ; STG.E [R12.64+0xc], R19 ; LDG.E R18, [R16.64+0x10] ; LDG.E R21, [R8.64] ; FFMA R21, R18, -R21, R20 ; LDG.E R20, [R12.64+0x14] ; STG.E [R12.64+0x10], R21 ; LDG.E R18, [R16.64+0x14] ; LDG.E R23, [R8.64] ; FFMA R23, R18, -R23, R20 ; LDG.E R20, [R12.64+0x18] ; STG.E [R12.64+0x14], R23 ; LDG.E R18, [R16.64+0x18] ; LDG.E R19, [R8.64] ; FFMA R19, R18, -R19, R20 ; LDG.E R20, [R12.64+0x1c] ; STG.E [R12.64+0x18], R19 ; LDG.E R18, [R16.64+0x1c] ; LDG.E R21, [R8.64] ; FFMA R21, R18, -R21, R20 ; LDG.E R20, [R12.64+0x20] ; STG.E [R12.64+0x1c], R21 ; LDG.E R18, [R16.64+0x20] ; LDG.E R23, [R8.64] ; FFMA R23, R18, -R23, R20 ; LDG.E R20, [R12.64+0x24] ; STG.E [R12.64+0x20], R23 ; LDG.E R18, [R16.64+0x24] ; LDG.E R19, [R8.64] ; FFMA R19, R18, -R19, R20 ; LDG.E R20, [R12.64+0x28] ; STG.E [R12.64+0x24], R19 ; LDG.E R18, [R16.64+0x28] ; LDG.E R21, [R8.64] ; FFMA R21, R18, -R21, R20 ; LDG.E R20, [R12.64+0x2c] ; STG.E [R12.64+0x28], R21 ; LDG.E R18, [R16.64+0x2c] ; LDG.E R23, [R8.64] ; FFMA R23, R18, -R23, R20 ; LDG.E R20, [R12.64+0x30] ; STG.E [R12.64+0x2c], R23 ; LDG.E R18, [R16.64+0x30] ; LDG.E R19, [R8.64] ; FFMA R19, R18, -R19, R20 ; LDG.E R20, [R12.64+0x34] ; STG.E [R12.64+0x30], R19 ; LDG.E R18, [R16.64+0x34] ; LDG.E R21, [R8.64] ; FFMA R21, R18, -R21, R20 ; LDG.E R20, [R12.64+0x38] ; STG.E [R12.64+0x34], R21 ; LDG.E R18, [R16.64+0x38] ; LDG.E R23, [R8.64] ; FFMA R23, R18, -R23, R20 ; LDG.E R20, [R12.64+0x3c] ; STG.E [R12.64+0x38], R23 ; LDG.E R18, [R16.64+0x3c] ; LDG.E R19, [R8.64] ; UIADD3 UR6, UR6, 0x10, URZ ; UISETP.GE.AND UP2, UPT, UR6, UR7, UPT ; PLOP3.LUT P2, PT, PT, PT, UP2, 0x80, 0x0 ; FFMA R25, R18, -R19, R20 ; STG.E [R12.64+0x3c], R25 ; IADD3 R18, P0, R10, 0x40, RZ ; IADD3.X R19, RZ, R11, RZ, P0, !PT ; @!P2 BRA 0x12b0 ; UIADD3 UR7, -UR6, UR14, URZ ; UISETP.GT.AND UP2, UPT, UR7, 0x4, UPT ; ULDC UR7, c[0x0][0x168] ; PLOP3.LUT P0, PT, PT, PT, UP2, 0x80, 0x0 ; @!P0 BRA 0x1ba0 ; IMAD.U32 R11, RZ, RZ, UR13 ; LDG.E R17, [R8.64] ; IMAD.WIDE R12, R7, 0x4, R18 ; IMAD.WIDE R10, R11, 0x4, R18 ; LDG.E R20, [R12.64] ; LDG.E R16, [R10.64] ; FFMA R17, R16, -R17, R20 ; LDG.E R20, [R12.64+0x4] ; STG.E [R12.64], R17 ; LDG.E R16, [R10.64+0x4] ; LDG.E R21, [R8.64] ; FFMA R21, R16, -R21, R20 ; LDG.E R20, [R12.64+0x8] ; STG.E [R12.64+0x4], R21 ; LDG.E R16, [R10.64+0x8] ; LDG.E R23, [R8.64] ; FFMA R23, R16, -R23, R20 ; LDG.E R20, [R12.64+0xc] ; STG.E [R12.64+0x8], R23 ; LDG.E R16, [R10.64+0xc] ; LDG.E R17, [R8.64] ; FFMA R17, R16, -R17, R20 ; LDG.E R20, [R12.64+0x10] ; STG.E [R12.64+0xc], R17 ; LDG.E R16, [R10.64+0x10] ; LDG.E R21, [R8.64] ; FFMA R21, R16, -R21, R20 ; LDG.E R20, [R12.64+0x14] ; STG.E [R12.64+0x10], R21 ; LDG.E R16, [R10.64+0x14] ; LDG.E R23, [R8.64] ; FFMA R23, R16, -R23, R20 ; LDG.E R20, [R12.64+0x18] ; STG.E [R12.64+0x14], R23 ; LDG.E R16, [R10.64+0x18] ; LDG.E R17, [R8.64] ; FFMA R17, R16, -R17, R20 ; LDG.E R20, [R12.64+0x1c] ; STG.E [R12.64+0x18], R17 ; LDG.E R16, [R10.64+0x1c] ; LDG.E R21, [R8.64] ; IADD3 R18, P0, R18, 0x20, RZ ; UPLOP3.LUT UP0, UPT, UPT, UPT, UPT, 0x40, 0x0 ; IADD3.X R19, RZ, R19, RZ, P0, !PT ; UIADD3 UR6, UR6, 0x8, URZ ; FFMA R21, R16, -R21, R20 ; STG.E [R12.64+0x1c], R21 ; UISETP.LT.OR UP0, UPT, UR6, UR7, UP0 ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; @!P0 BRA 0x1d40 ; IMAD.U32 R13, RZ, RZ, UR13 ; LDG.E R16, [R8.64] ; IMAD.WIDE R10, R7, 0x4, R18 ; IMAD.WIDE R12, R13, 0x4, R18 ; LDG.E R17, [R10.64] ; LDG.E R7, [R12.64] ; LDG.E R18, [R10.64+0x4] ; FFMA R7, R7, -R16, R17 ; STG.E [R10.64], R7 ; LDG.E R16, [R12.64+0x4] ; LDG.E R17, [R8.64] ; FFMA R17, R16, -R17, R18 ; LDG.E R18, [R10.64+0x8] ; STG.E [R10.64+0x4], R17 ; LDG.E R16, [R12.64+0x8] ; LDG.E R19, [R8.64] ; FFMA R19, R16, -R19, R18 ; LDG.E R18, [R10.64+0xc] ; STG.E [R10.64+0x8], R19 ; LDG.E R7, [R12.64+0xc] ; LDG.E R16, [R8.64] ; FFMA R7, R7, -R16, R18 ; STG.E [R10.64+0xc], R7 ; BSYNC B0 ; @!P1 BRA 0xf40 ; UIADD3 UR4, UR4, 0x1, URZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; UISETP.GE.AND UP0, UPT, UR4, UR5, UPT ; PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; @P0 CALL.REL.NOINC 0x1dc0 ; BRA 0x1f0 ; EXIT ; SHF.R.U32.HI R9, RZ, 0x17, R19 ; BSSY B0, 0x2410 ; SHF.R.U32.HI R11, RZ, 0x17, R12 ; LOP3.LUT R9, R9, 0xff, RZ, 0xc0, !PT ; LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; IADD3 R13, R9, -0x1, RZ ; IADD3 R18, R11, -0x1, RZ ; ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ; ISETP.GT.U32.OR P0, PT, R18, 0xfd, P0 ; @!P0 MOV R10, RZ ; @!P0 BRA 0x1ff0 ; FSETP.GTU.FTZ.AND P0, PT, |R12|, +INF , PT ; FSETP.GTU.FTZ.AND P1, PT, |R19|, +INF , PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; @P0 BRA 0x23f0 ; LOP3.LUT P0, RZ, R19, 0x7fffffff, R12, 0xc8, !PT ; @!P0 BRA 0x23d0 ; FSETP.NEU.FTZ.AND P3, PT, |R12|.reuse, +INF , PT ; FSETP.NEU.FTZ.AND P1, PT, |R19|, +INF , PT ; FSETP.NEU.FTZ.AND P0, PT, |R12|, +INF , PT ; @!P1 BRA !P3, 0x23d0 ; LOP3.LUT P3, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; @P1 BRA 0x23b0 ; LOP3.LUT P1, RZ, R19, 0x7fffffff, RZ, 0xc0, !PT ; PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; @P0 BRA 0x2380 ; ISETP.GE.AND P0, PT, R18, RZ, PT ; ISETP.GE.AND P1, PT, R13, RZ, PT ; @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; @!P0 MOV R10, 0xffffffc0 ; @!P0 FFMA R12, R12, 1.84467440737095516160e+19, RZ ; @!P1 FFMA R19, R19, 1.84467440737095516160e+19, RZ ; @!P1 IADD3 R10, R10, 0x40, RZ ; LEA R18, R9, 0xc0800000, 0x17 ; BSSY B1, 0x2370 ; IADD3 R11, R11, -0x7f, RZ ; IMAD.IADD R21, R19, 0x1, -R18 ; IMAD R19, R11.reuse, -0x800000, R12 ; IADD3 R11, R11, 0x7f, -R9 ; MUFU.RCP R13, R21 ; FADD.FTZ R18, -R21, -RZ ; IADD3 R11, R11, R10, RZ ; FFMA R22, R13, R18, 1 ; FFMA R22, R13, R22, R13 ; FFMA R13, R19, R22, RZ ; FFMA R12, R18, R13, R19 ; FFMA R13, R22, R12, R13 ; FFMA R18, R18, R13, R19 ; FFMA R12, R22, R18, R13 ; SHF.R.U32.HI R9, RZ, 0x17, R12 ; LOP3.LUT R10, R9, 0xff, RZ, 0xc0, !PT ; IMAD.IADD R9, R10, 0x1, R11 ; IADD3 R10, R9, -0x1, RZ ; ISETP.GE.U32.AND P0, PT, R10, 0xfe, PT ; @!P0 BRA 0x2350 ; ISETP.GT.AND P0, PT, R9, 0xfe, PT ; @P0 BRA 0x2320 ; ISETP.GE.AND P0, PT, R9, 0x1, PT ; @P0 BRA 0x2360 ; ISETP.GE.AND P0, PT, R9, -0x18, PT ; LOP3.LUT R12, R12, 0x80000000, RZ, 0xc0, !PT ; @!P0 BRA 0x2360 ; FFMA.RZ R10, R22.reuse, R18.reuse, R13.reuse ; ISETP.NE.AND P3, PT, R9.reuse, RZ, PT ; FFMA.RP R11, R22.reuse, R18.reuse, R13.reuse ; ISETP.NE.AND P1, PT, R9.reuse, RZ, PT ; FFMA.RM R18, R22, R18, R13 ; LOP3.LUT R10, R10, 0x7fffff, RZ, 0xc0, !PT ; IADD3 R13, R9.reuse, 0x20, RZ ; LOP3.LUT R10, R10, 0x800000, RZ, 0xfc, !PT ; IADD3 R9, -R9, RZ, RZ ; SHF.L.U32 R13, R10, R13, RZ ; FSETP.NEU.FTZ.AND P0, PT, R11, R18, PT ; SEL R9, R9, RZ, P3 ; ISETP.NE.AND P1, PT, R13, RZ, P1 ; SHF.R.U32.HI R18, RZ, R9, R10 ; PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; SHF.R.U32.HI R10, RZ, 0x1, R18 ; SEL R9, RZ, 0x1, !P0 ; LOP3.LUT R9, R9, 0x1, R10, 0xf8, !PT ; LOP3.LUT R9, R9, R18, RZ, 0xc0, !PT ; IMAD.IADD R9, R10, 0x1, R9 ; LOP3.LUT R12, R9, R12, RZ, 0xfc, !PT ; BRA 0x2360 ; LOP3.LUT R12, R12, 0x80000000, RZ, 0xc0, !PT ; LOP3.LUT R12, R12, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x2360 ; LEA R12, R11, R12, 0x17 ; BSYNC B1 ; BRA 0x2400 ; LOP3.LUT R12, R19, 0x80000000, R12, 0x48, !PT ; LOP3.LUT R12, R12, 0x7f800000, RZ, 0xfc, !PT ; BRA 0x2400 ; LOP3.LUT R12, R19, 0x80000000, R12, 0x48, !PT ; BRA 0x2400 ; MUFU.RSQ R12, -QNAN ; BRA 0x2400 ; FADD.FTZ R12, R12, R19 ; BSYNC B0 ; MOV R10, R0 ; IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; IMAD.MOV.U32 R9, RZ, RZ, R12 ; RET.REL.NODEC R10 0x0 ; BRA 0x2450; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z8computeKPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; I2F.U32.RP R0, c[0x0][0x0] ; IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x0], PT ; IMAD.MOV.U32 R27, RZ, RZ, 0x1 ; MUFU.RCP R0, R0 ; IADD3 R2, R0, 0xffffffe, RZ ; F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; IMAD.MOV.U32 R2, RZ, RZ, RZ ; IMAD.MOV R5, RZ, RZ, -R3 ; IMAD R5, R5, c[0x0][0x0], RZ ; IMAD.HI.U32 R3, R3, R5, R2 ; IMAD.HI.U32 R28, R3, c[0x0][0x178], RZ ; IADD3 R3, -R28, RZ, RZ ; IMAD R0, R3, R4, c[0x0][0x178] ; ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; @P0 IADD3 R0, R0, -c[0x0][0x0], RZ ; @P0 IADD3 R28, R28, 0x1, RZ ; ISETP.GE.U32.AND P2, PT, R0, c[0x0][0x0], PT ; ISETP.LE.AND P0, PT, R27, c[0x0][0x178], PT ; @P2 IADD3 R28, R28, 0x1, RZ ; @!P1 LOP3.LUT R28, RZ, c[0x0][0x0], RZ, 0x33, !PT ; ISETP.LT.OR P0, PT, R28, 0x1, !P0 ; @P0 EXIT ; S2R R5, SR_TID.X ; LOP3.LUT R27, R27, c[0x0][0x178], RZ, 0xc0, !PT ; UMOV UR4, URZ ; ULDC.64 UR6, c[0x0][0x118] ; IADD3 R27, -R27, c[0x0][0x178], RZ ; IMAD R5, R28, R5, RZ ; IADD3 R26, R5, UR4, RZ ; UIADD3 UR4, UR4, 0x1, URZ ; ISETP.GE.AND P0, PT, R26, c[0x0][0x178], PT ; @P0 EXIT ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; HFMA2.MMA R3, -RZ, RZ, 0, 0 ; IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; ISETP.LE.AND P0, PT, R28, UR4, PT ; ISETP.NE.AND P1, PT, R0, c[0x0][0x178], PT ; IMAD.WIDE R6, R26, R4, c[0x0][0x160] ; IMAD.WIDE R8, R26, R4, c[0x0][0x168] ; @!P1 BRA 0x9d0 ; IMAD.MOV.U32 R3, RZ, RZ, RZ ; IMAD.MOV.U32 R2, RZ, RZ, R27 ; IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; LDG.E R17, [R8.64] ; IMAD.WIDE R10, R3.reuse, R4.reuse, c[0x0][0x168] ; LDG.E R15, [R6.64] ; IMAD.WIDE R12, R3, R4, c[0x0][0x160] ; LDG.E R14, [R10.64] ; LDG.E R0, [R12.64] ; MOV R16, 0x652b82fe ; BSSY B0, 0x5f0 ; FADD R14, -R14, R17 ; FADD R0, -R0, R15 ; FMUL R15, R14, R14 ; FFMA R0, R0, R0, R15 ; F2F.F64.F32 R14, R0 ; IMAD.MOV.U32 R17, RZ, RZ, 0x3ff71547 ; DFMA R18, -R14, R16, 6.75539944105574400000e+15 ; DADD R20, R18, -6.75539944105574400000e+15 ; DFMA R24, R20, c[0x2][0x0], -R14 ; DFMA R24, R20, c[0x2][0x8], R24 ; IMAD.MOV.U32 R20, RZ, RZ, 0x69ce2bdf ; IMAD.MOV.U32 R21, RZ, RZ, 0x3e5ade15 ; DFMA R22, R24, R20, c[0x2][0x10] ; DFMA R22, R24, R22, c[0x2][0x18] ; DFMA R22, R24, R22, c[0x2][0x20] ; DFMA R22, R24, R22, c[0x2][0x28] ; DFMA R22, R24, R22, c[0x2][0x30] ; DFMA R22, R24, R22, c[0x2][0x38] ; DFMA R22, R24, R22, c[0x2][0x40] ; DFMA R22, R24, R22, c[0x2][0x48] ; DFMA R22, R24, R22, c[0x2][0x50] ; DFMA R22, R24, R22, 1 ; DFMA R22, R24, R22, 1 ; DADD R24, -RZ, -R14 ; MOV R29, R25 ; FSETP.GEU.AND P1, PT, |R29|, 4.1917929649353027344, PT ; IMAD R25, R18, 0x100000, R23 ; IMAD.MOV.U32 R24, RZ, RZ, R22 ; @!P1 BRA 0x5e0 ; FSETP.GEU.AND P2, PT, |R29|, 4.2275390625, PT ; DADD R14, -R14, +INF ; FSETP.GT.AND P1, PT, R0, RZ, PT ; FSEL R24, R14, RZ, !P1 ; @!P2 LEA.HI R0, R18, R18, RZ, 0x1 ; @!P2 IMAD.MOV.U32 R14, RZ, RZ, RZ ; FSEL R25, R15, RZ, !P1 ; @!P2 SHF.R.S32.HI R19, RZ, 0x1, R0 ; @!P2 LEA R23, R19, R23, 0x14 ; @!P2 IMAD.IADD R18, R18, 0x1, -R19 ; @!P2 LEA R15, R18, 0x3ff00000, 0x14 ; @!P2 DMUL R24, R22, R14 ; BSYNC B0 ; F2F.F32.F64 R23, R24 ; ISETP.NE.AND P1, PT, R26, R3, PT ; F2F.F64.F32 R14, R23 ; DADD R18, R14, c[0x2][0x58] ; IMAD R15, R26, c[0x0][0x178], R3 ; @!P1 F2F.F32.F64 R23, R18 ; IMAD.WIDE R14, R15, R4, c[0x0][0x170] ; STG.E [R14.64], R23 ; LDG.E R10, [R10.64+0x4] ; LDG.E R29, [R8.64] ; LDG.E R12, [R12.64+0x4] ; LDG.E R25, [R6.64] ; BSSY B0, 0x920 ; FADD R29, -R10, R29 ; FMUL R0, R29, R29 ; FADD R25, -R12, R25 ; FFMA R0, R25, R25, R0 ; F2F.F64.F32 R18, R0 ; DFMA R16, -R18, R16, 6.75539944105574400000e+15 ; DADD R12, -RZ, -R18 ; DADD R22, R16, -6.75539944105574400000e+15 ; DFMA R10, R22, c[0x2][0x0], -R18 ; FSETP.GEU.AND P1, PT, |R13|, 4.1917929649353027344, PT ; DFMA R10, R22, c[0x2][0x8], R10 ; DFMA R20, R10, R20, c[0x2][0x10] ; DFMA R20, R10, R20, c[0x2][0x18] ; DFMA R20, R10, R20, c[0x2][0x20] ; DFMA R20, R10, R20, c[0x2][0x28] ; DFMA R20, R10, R20, c[0x2][0x30] ; DFMA R20, R10, R20, c[0x2][0x38] ; DFMA R20, R10, R20, c[0x2][0x40] ; DFMA R20, R10, R20, c[0x2][0x48] ; DFMA R20, R10, R20, c[0x2][0x50] ; DFMA R20, R10, R20, 1 ; DFMA R20, R10, R20, 1 ; IMAD R11, R16, 0x100000, R21 ; IMAD.MOV.U32 R10, RZ, RZ, R20 ; @!P1 BRA 0x910 ; FSETP.GEU.AND P2, PT, |R13|, 4.2275390625, PT ; DADD R18, -R18, +INF ; FSETP.GT.AND P1, PT, R0, RZ, PT ; FSEL R11, R19, RZ, !P1 ; @!P2 LEA.HI R10, R16, R16, RZ, 0x1 ; @!P2 SHF.R.S32.HI R13, RZ, 0x1, R10 ; FSEL R10, R18, RZ, !P1 ; @!P2 IADD3 R12, R16, -R13, RZ ; @!P2 IMAD R21, R13, 0x100000, R21 ; @!P2 LEA R13, R12, 0x3ff00000, 0x14 ; @!P2 IMAD.MOV.U32 R12, RZ, RZ, RZ ; @!P2 DMUL R10, R20, R12 ; BSYNC B0 ; F2F.F32.F64 R17, R10 ; IADD3 R19, R3.reuse, 0x1, RZ ; IADD3 R2, R2, -0x2, RZ ; ISETP.NE.AND P1, PT, R26, R19, PT ; IADD3 R3, R3, 0x2, RZ ; F2F.F64.F32 R12, R17 ; DADD R12, R12, c[0x2][0x58] ; @!P1 F2F.F32.F64 R17, R12 ; ISETP.NE.AND P1, PT, R2, RZ, PT ; STG.E [R14.64+0x4], R17 ; @P1 BRA 0x2c0 ; IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; LOP3.LUT P1, RZ, R0, c[0x0][0x178], RZ, 0xc0, !PT ; @!P1 BRA 0xda0 ; IMAD.WIDE R16, R3.reuse, R4.reuse, c[0x0][0x168] ; LDG.E R9, [R8.64] ; IMAD.WIDE R14, R3, R4, c[0x0][0x160] ; LDG.E R7, [R6.64] ; LDG.E R16, [R16.64] ; LDG.E R14, [R14.64] ; MOV R12, 0x652b82fe ; IMAD.MOV.U32 R13, RZ, RZ, 0x3ff71547 ; IMAD.MOV.U32 R18, RZ, RZ, 0x69ce2bdf ; IMAD.MOV.U32 R19, RZ, RZ, 0x3e5ade15 ; BSSY B0, 0xd10 ; FADD R2, -R16, R9 ; FADD R0, -R14, R7 ; FMUL R11, R2, R2 ; FFMA R0, R0, R0, R11 ; F2F.F64.F32 R10, R0 ; DFMA R12, -R10, R12, 6.75539944105574400000e+15 ; DADD R8, R12, -6.75539944105574400000e+15 ; DFMA R16, R8, c[0x2][0x0], -R10 ; DFMA R6, R8, c[0x2][0x8], R16 ; DFMA R8, R6, R18, c[0x2][0x10] ; DFMA R8, R6, R8, c[0x2][0x18] ; DFMA R8, R6, R8, c[0x2][0x20] ; DFMA R8, R6, R8, c[0x2][0x28] ; DFMA R8, R6, R8, c[0x2][0x30] ; DFMA R8, R6, R8, c[0x2][0x38] ; DFMA R8, R6, R8, c[0x2][0x40] ; DFMA R8, R6, R8, c[0x2][0x48] ; DADD R14, -RZ, -R10 ; DFMA R8, R6, R8, c[0x2][0x50] ; DFMA R8, R6, R8, 1 ; FSETP.GEU.AND P1, PT, |R15|, 4.1917929649353027344, PT ; DFMA R6, R6, R8, 1 ; LEA R9, R12, R7, 0x14 ; IMAD.MOV.U32 R8, RZ, RZ, R6 ; @!P1 BRA 0xd00 ; FSETP.GEU.AND P2, PT, |R15|, 4.2275390625, PT ; DADD R10, -R10, +INF ; FSETP.GT.AND P1, PT, R0, RZ, PT ; FSEL R8, R10, RZ, !P1 ; @!P2 LEA.HI R2, R12, R12, RZ, 0x1 ; @!P2 IMAD.MOV.U32 R10, RZ, RZ, RZ ; FSEL R9, R11, RZ, !P1 ; @!P2 SHF.R.S32.HI R13, RZ, 0x1, R2 ; @!P2 LEA R7, R13, R7, 0x14 ; @!P2 IMAD.IADD R12, R12, 0x1, -R13 ; @!P2 LEA R11, R12, 0x3ff00000, 0x14 ; @!P2 DMUL R8, R6, R10 ; BSYNC B0 ; F2F.F32.F64 R9, R8 ; ISETP.NE.AND P1, PT, R26.reuse, R3, PT ; IMAD R3, R26, c[0x0][0x178], R3 ; IMAD.WIDE R2, R3, R4, c[0x0][0x170] ; @!P1 F2F.F64.F32 R6, R9 ; STG.E [R2.64], R9 ; @!P1 DADD R6, R6, c[0x2][0x58] ; @!P1 F2F.F32.F64 R7, R6 ; @!P1 STG.E [R2.64], R7 ; @!P0 BRA 0x1e0 ; EXIT ; BRA 0xdc0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; .......... Function : _Z9computeKTPfS_S_iff .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R0, SR_CTAID.X ; IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; ULDC.64 UR4, c[0x0][0x118] ; IMAD.WIDE R10, R0, R9, c[0x0][0x168] ; IMAD.WIDE R8, R0, R9, c[0x0][0x160] ; LDG.E R10, [R10.64] ; LDG.E R8, [R8.64] ; HFMA2.MMA R4, -RZ, RZ, 1323, -4.565715789794921875e-05 ; IMAD.MOV.U32 R5, RZ, RZ, 0x3ff71547 ; MOV R11, 0x3e5ade15 ; FADD R2, -R10, c[0x0][0x180] ; IMAD.MOV.U32 R10, RZ, RZ, 0x69ce2bdf ; FADD R6, -R8, c[0x0][0x17c] ; FMUL R3, R2, R2 ; FFMA R6, R6, R6, R3 ; F2F.F64.F32 R2, R6 ; DFMA R4, -R2, R4, 6.75539944105574400000e+15 ; DADD R12, R4, -6.75539944105574400000e+15 ; DFMA R14, R12, c[0x2][0x0], -R2 ; DFMA R8, R12, c[0x2][0x8], R14 ; DADD R12, -RZ, -R2 ; DFMA R10, R8, R10, c[0x2][0x10] ; DFMA R10, R8, R10, c[0x2][0x18] ; FSETP.GEU.AND P0, PT, |R13|, 4.1917929649353027344, PT ; DFMA R10, R8, R10, c[0x2][0x20] ; DFMA R10, R8, R10, c[0x2][0x28] ; DFMA R10, R8, R10, c[0x2][0x30] ; DFMA R10, R8, R10, c[0x2][0x38] ; DFMA R10, R8, R10, c[0x2][0x40] ; DFMA R10, R8, R10, c[0x2][0x48] ; DFMA R10, R8, R10, c[0x2][0x50] ; DFMA R10, R8, R10, 1 ; DFMA R10, R8, R10, 1 ; IMAD R9, R4, 0x100000, R11 ; IMAD.MOV.U32 R8, RZ, RZ, R10 ; @!P0 BRA 0x320 ; FSETP.GEU.AND P1, PT, |R13|, 4.2275390625, PT ; DADD R2, -R2, +INF ; FSETP.GT.AND P0, PT, R6, RZ, PT ; FSEL R8, R2, RZ, !P0 ; FSEL R9, R3, RZ, !P0 ; @P1 BRA 0x320 ; LEA.HI R2, R4, R4, RZ, 0x1 ; MOV R8, RZ ; SHF.R.S32.HI R3, RZ, 0x1, R2 ; IADD3 R4, R4, -R3, RZ ; IMAD R11, R3, 0x100000, R11 ; LEA R9, R4, 0x3ff00000, 0x14 ; DMUL R8, R10, R8 ; F2F.F32.F64 R9, R8 ; SHF.R.S32.HI R3, RZ, 0x1f, R0 ; LEA R2, P0, R0, c[0x0][0x170], 0x2 ; LEA.HI.X R3, R0, c[0x0][0x174], R3, 0x2, P0 ; STG.E [R2.64], R9 ; EXIT ; BRA 0x380; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000cef76_00000000-6_5aec82e8b871266bf98edd01b278c533e4a3ee01.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2065: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2065: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%8.10f " .LC1: .string "\n" .text .globl _Z9printVectPfi .type _Z9printVectPfi, @function _Z9printVectPfi: .LFB2057: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 testl %esi, %esi jle .L4 movq %rdi, %rbx movslq %esi, %rsi leaq (%rdi,%rsi,4), %r12 leaq .LC0(%rip), %rbp .L5: pxor %xmm0, %xmm0 cvtss2sd (%rbx), %xmm0 movq %rbp, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $4, %rbx cmpq %r12, %rbx jne .L5 .L4: leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z9printVectPfi, .-_Z9printVectPfi .globl _Z8printMatPfi .type _Z8printMatPfi, @function _Z8printMatPfi: .LFB2058: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $24, %rsp .cfi_def_cfa_offset 80 movl %esi, 12(%rsp) testl %esi, %esi jle .L8 movslq %esi, %r14 leaq 0(,%r14,4), %r15 leaq (%rdi,%r15), %rbp negq %r14 salq $2, %r14 movl $0, %r13d leaq .LC0(%rip), %r12 .L10: leaq 0(%rbp,%r14), %rbx .L11: pxor %xmm0, %xmm0 cvtss2sd (%rbx), %xmm0 movq %r12, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L11 leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addl $1, %r13d addq %r15, %rbp cmpl %r13d, 12(%rsp) jne .L10 .L8: addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z8printMatPfi, .-_Z8printMatPfi .globl _Z13computePointsPfS_fi .type _Z13computePointsPfS_fi, @function _Z13computePointsPfS_fi: .LFB2059: .cfi_startproc endbr64 testl %edx, %edx jle .L20 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movl %edx, %r11d leal 1(%rdx), %ebp movl $0, %r10d movl $0, %r9d movl $1, %r8d movl %edx, %ebx .L16: pxor %xmm2, %xmm2 cvtsi2ssl %r8d, %xmm2 mulss %xmm0, %xmm2 movslq %r9d, %rax leaq (%rbx,%rax), %r12 leal 1(%r10), %ecx .L17: movss %xmm2, (%rdi,%rax,4) leal (%rcx,%rax), %edx pxor %xmm1, %xmm1 cvtsi2ssl %edx, %xmm1 mulss %xmm0, %xmm1 movss %xmm1, (%rsi,%rax,4) addq $1, %rax cmpq %r12, %rax jne .L17 addl %r11d, %r9d addl $1, %r8d subl %r11d, %r10d cmpl %ebp, %r8d jne .L16 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L20: .cfi_restore 3 .cfi_restore 6 .cfi_restore 12 ret .cfi_endproc .LFE2059: .size _Z13computePointsPfS_fi, .-_Z13computePointsPfS_fi .globl _Z10computeResPfS_i .type _Z10computeResPfS_i, @function _Z10computeResPfS_i: .LFB2060: .cfi_startproc endbr64 testl %edx, %edx jle .L26 movslq %edx, %rdx salq $2, %rdx movl $0, %eax pxor %xmm1, %xmm1 .L25: movss (%rdi,%rax), %xmm0 mulss (%rsi,%rax), %xmm0 addss %xmm0, %xmm1 addq $4, %rax cmpq %rdx, %rax jne .L25 .L23: movaps %xmm1, %xmm0 ret .L26: pxor %xmm1, %xmm1 jmp .L23 .cfi_endproc .LFE2060: .size _Z10computeResPfS_i, .-_Z10computeResPfS_i .globl _Z8computeFPfS_S_i .type _Z8computeFPfS_S_i, @function _Z8computeFPfS_S_i: .LFB2061: .cfi_startproc endbr64 testl %ecx, %ecx jle .L33 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 movq %rdi, %r12 movq %rsi, %r13 movq %rdx, %r14 movslq %ecx, %rcx leaq 0(,%rcx,4), %rbp movl $0, %ebx .L30: call rand@PLT pxor %xmm0, %xmm0 cvtss2sd (%r12,%rbx), %xmm0 subsd .LC3(%rip), %xmm0 pxor %xmm1, %xmm1 cvtss2sd 0(%r13,%rbx), %xmm1 subsd .LC3(%rip), %xmm1 mulsd %xmm0, %xmm0 mulsd %xmm1, %xmm1 addsd %xmm1, %xmm0 movsd .LC4(%rip), %xmm1 subsd %xmm0, %xmm1 pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 mulss .LC5(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 subsd .LC3(%rip), %xmm0 mulsd .LC6(%rip), %xmm0 cvtsd2ss %xmm0, %xmm0 cvtss2sd %xmm0, %xmm0 addsd %xmm1, %xmm0 cvtsd2ss %xmm0, %xmm0 movss %xmm0, (%r14,%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L30 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L33: .cfi_restore 3 .cfi_restore 6 .cfi_restore 12 .cfi_restore 13 .cfi_restore 14 ret .cfi_endproc .LFE2061: .size _Z8computeFPfS_S_i, .-_Z8computeFPfS_S_i .globl _Z35__device_stub__Z9computeKTPfS_S_iffPfS_S_iff .type _Z35__device_stub__Z9computeKTPfS_S_iffPfS_S_iff, @function _Z35__device_stub__Z9computeKTPfS_S_iffPfS_S_iff: .LFB2087: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movl %ecx, 20(%rsp) movss %xmm0, 16(%rsp) movss %xmm1, 12(%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 20(%rsp), %rax movq %rax, 136(%rsp) leaq 16(%rsp), %rax movq %rax, 144(%rsp) leaq 12(%rsp), %rax movq %rax, 152(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L40 .L36: movq 168(%rsp), %rax subq %fs:40, %rax jne .L41 addq $184, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L40: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 200 pushq 56(%rsp) .cfi_def_cfa_offset 208 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z9computeKTPfS_S_iff(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L36 .L41: call __stack_chk_fail@PLT .cfi_endproc .LFE2087: .size _Z35__device_stub__Z9computeKTPfS_S_iffPfS_S_iff, .-_Z35__device_stub__Z9computeKTPfS_S_iffPfS_S_iff .globl _Z9computeKTPfS_S_iff .type _Z9computeKTPfS_S_iff, @function _Z9computeKTPfS_S_iff: .LFB2088: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z9computeKTPfS_S_iffPfS_S_iff addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2088: .size _Z9computeKTPfS_S_iff, .-_Z9computeKTPfS_S_iff .globl _Z32__device_stub__Z8computeKPfS_S_iPfS_S_i .type _Z32__device_stub__Z8computeKPfS_S_iPfS_S_i, @function _Z32__device_stub__Z8computeKPfS_S_iPfS_S_i: .LFB2089: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L48 .L44: movq 136(%rsp), %rax subq %fs:40, %rax jne .L49 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L48: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z8computeKPfS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L44 .L49: call __stack_chk_fail@PLT .cfi_endproc .LFE2089: .size _Z32__device_stub__Z8computeKPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8computeKPfS_S_iPfS_S_i .globl _Z8computeKPfS_S_i .type _Z8computeKPfS_S_i, @function _Z8computeKPfS_S_i: .LFB2090: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z32__device_stub__Z8computeKPfS_S_iPfS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2090: .size _Z8computeKPfS_S_i, .-_Z8computeKPfS_S_i .globl _Z23__device_stub__Z2LUPfiiPfii .type _Z23__device_stub__Z2LUPfiiPfii, @function _Z23__device_stub__Z2LUPfiiPfii: .LFB2091: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L56 .L52: movq 104(%rsp), %rax subq %fs:40, %rax jne .L57 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L56: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z2LUPfii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L52 .L57: call __stack_chk_fail@PLT .cfi_endproc .LFE2091: .size _Z23__device_stub__Z2LUPfiiPfii, .-_Z23__device_stub__Z2LUPfiiPfii .globl _Z2LUPfii .type _Z2LUPfii, @function _Z2LUPfii: .LFB2092: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z23__device_stub__Z2LUPfiiPfii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2092: .size _Z2LUPfii, .-_Z2LUPfii .globl _Z28__device_stub__Z6solveLPfS_iPfS_i .type _Z28__device_stub__Z6solveLPfS_iPfS_i, @function _Z28__device_stub__Z6solveLPfS_iPfS_i: .LFB2093: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L64 .L60: movq 120(%rsp), %rax subq %fs:40, %rax jne .L65 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L64: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6solveLPfS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L60 .L65: call __stack_chk_fail@PLT .cfi_endproc .LFE2093: .size _Z28__device_stub__Z6solveLPfS_iPfS_i, .-_Z28__device_stub__Z6solveLPfS_iPfS_i .globl _Z6solveLPfS_i .type _Z6solveLPfS_i, @function _Z6solveLPfS_i: .LFB2094: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z28__device_stub__Z6solveLPfS_iPfS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2094: .size _Z6solveLPfS_i, .-_Z6solveLPfS_i .globl _Z28__device_stub__Z6solveUPfS_iPfS_i .type _Z28__device_stub__Z6solveUPfS_iPfS_i, @function _Z28__device_stub__Z6solveUPfS_iPfS_i: .LFB2095: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L72 .L68: movq 120(%rsp), %rax subq %fs:40, %rax jne .L73 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L72: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6solveUPfS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L68 .L73: call __stack_chk_fail@PLT .cfi_endproc .LFE2095: .size _Z28__device_stub__Z6solveUPfS_iPfS_i, .-_Z28__device_stub__Z6solveUPfS_iPfS_i .globl _Z6solveUPfS_i .type _Z6solveUPfS_i, @function _Z6solveUPfS_i: .LFB2096: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z28__device_stub__Z6solveUPfS_iPfS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2096: .size _Z6solveUPfS_i, .-_Z6solveUPfS_i .section .rodata.str1.1 .LC8: .string "Start computing LU\n" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC10: .string "Time for LU factors routines: %4.10f s \n" .align 8 .LC11: .string "Time for solver routine is: %4.10f s \n" .section .rodata.str1.1 .LC12: .string " result is: %8.10f\n" .text .globl main .type main, @function main: .LFB2062: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $152, %rsp .cfi_def_cfa_offset 208 movq %rsi, %rbx movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax movq 8(%rsi), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %rbp movl %eax, 12(%rsp) movq 16(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 24(%rsp) movq 24(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 16(%rsp) movq 32(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %r13 movl %ebp, %r12d imull %ebp, %r12d leal 0(,%r12,4), %ebx movslq %ebx, %rbx movq %rbx, %rdi call malloc@PLT movq %rax, %r15 movq %rbx, %rdi call malloc@PLT movq %rax, %r14 movq %rbx, %rdi call malloc@PLT movq %rax, (%rsp) addl $1, %ebp pxor %xmm1, %xmm1 cvtsi2ssl %ebp, %xmm1 movss .LC7(%rip), %xmm0 divss %xmm1, %xmm0 movl 12(%rsp), %edx movq %r14, %rsi movq %r15, %rdi call _Z13computePointsPfS_fi movl %r12d, %ecx movq (%rsp), %rbp movq %rbp, %rdx movq %r14, %rsi movq %r15, %rdi call _Z8computeFPfS_S_i movl $0, %edi call cudaSetDevice@PLT leaq 40(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 48(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movl %r12d, %esi imull %r12d, %esi sall $2, %esi movslq %esi, %rsi leaq 56(%rsp), %rdi call cudaMalloc@PLT leaq 64(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movl $1, %ecx movq %rbx, %rdx movq %rbp, %rsi movq 64(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq %r15, %rsi movq 40(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq %r14, %rsi movq 48(%rsp), %rdi call cudaMemcpy@PLT movl %r13d, 124(%rsp) movl $1, 128(%rsp) movl $1, 132(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) movl $1, 120(%rsp) movl $0, %r9d movl $0, %r8d movq 124(%rsp), %rdx movl $1, %ecx movq 112(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L84 .L77: leaq .LC8(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 72(%rsp), %rdi call cudaEventCreate@PLT leaq 80(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 72(%rsp), %rdi call cudaEventRecord@PLT movl %r13d, 124(%rsp) movl $1, 128(%rsp) movl $1, 132(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) movl $1, 120(%rsp) movl $0, %r9d movl $0, %r8d movq 124(%rsp), %rdx movl $1, %ecx movq 112(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L85 .L78: movl $0, %esi movq 80(%rsp), %rdi call cudaEventRecord@PLT movq 80(%rsp), %rdi call cudaEventSynchronize@PLT leaq 32(%rsp), %rdi movq 80(%rsp), %rdx movq 72(%rsp), %rsi call cudaEventElapsedTime@PLT movq 72(%rsp), %rdi call cudaEventDestroy@PLT movq 80(%rsp), %rdi call cudaEventDestroy@PLT movss 32(%rsp), %xmm0 divss .LC9(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 leaq .LC10(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT leaq 88(%rsp), %rdi call cudaEventCreate@PLT leaq 96(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 72(%rsp), %rdi call cudaEventRecord@PLT movl %r13d, 124(%rsp) movl $1, 128(%rsp) movl $1, 132(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) movl $1, 120(%rsp) movl $0, %r9d movl $0, %r8d movq 124(%rsp), %rdx movl $1, %ecx movq 112(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L86 .L79: movl %r13d, 124(%rsp) movl $1, 128(%rsp) movl $1, 132(%rsp) movl $1, 112(%rsp) movl $1, 116(%rsp) movl $1, 120(%rsp) movl $0, %r9d movl $0, %r8d movq 124(%rsp), %rdx movl $1, %ecx movq 112(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L87 .L80: movl $0, %esi movq 96(%rsp), %rdi call cudaEventRecord@PLT movq 80(%rsp), %rdi call cudaEventSynchronize@PLT leaq 36(%rsp), %rdi movq 96(%rsp), %rdx movq 88(%rsp), %rsi call cudaEventElapsedTime@PLT movq 88(%rsp), %rdi call cudaEventDestroy@PLT movq 96(%rsp), %rdi call cudaEventDestroy@PLT movss 36(%rsp), %xmm0 divss .LC9(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 leaq .LC11(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq %rbx, %rdi call malloc@PLT movq %rax, %rbp movl $2, %ecx movq %rbx, %rdx movq 64(%rsp), %rsi movq %rax, %rdi call cudaMemcpy@PLT leaq 104(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movl $1, 124(%rsp) movl $1, 128(%rsp) movl $1, 132(%rsp) movl %r12d, 112(%rsp) movl $1, 116(%rsp) movl $1, 120(%rsp) movl $0, %r9d movl $0, %r8d movq 124(%rsp), %rdx movl $1, %ecx movq 112(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L88 .L81: movq %rbx, %rdi call malloc@PLT movq %rax, %r13 movl $2, %ecx movq %rbx, %rdx movq 104(%rsp), %rsi movq %rax, %rdi call cudaMemcpy@PLT movl %r12d, %edx movq %rbp, %rsi movq %r13, %rdi call _Z10computeResPfS_i cvtss2sd %xmm0, %xmm0 leaq .LC12(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq %r15, %rdi call free@PLT movq %r14, %rdi call free@PLT movq (%rsp), %rdi call free@PLT movq %rbp, %rdi call free@PLT movq %r13, %rdi call free@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq 48(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rdi call cudaFree@PLT movq 64(%rsp), %rdi call cudaFree@PLT movq 104(%rsp), %rdi call cudaFree@PLT movq 136(%rsp), %rax subq %fs:40, %rax jne .L89 movl $0, %eax addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L84: .cfi_restore_state movl %r12d, %ecx movq 56(%rsp), %rdx movq 48(%rsp), %rsi movq 40(%rsp), %rdi call _Z32__device_stub__Z8computeKPfS_S_iPfS_S_i jmp .L77 .L85: movl %r13d, %edx movl %r12d, %esi movq 56(%rsp), %rdi call _Z23__device_stub__Z2LUPfiiPfii jmp .L78 .L86: movl %r12d, %edx movq 56(%rsp), %rsi movq 64(%rsp), %rdi call _Z28__device_stub__Z6solveLPfS_iPfS_i jmp .L79 .L87: movl %r12d, %edx movq 56(%rsp), %rsi movq 64(%rsp), %rdi call _Z28__device_stub__Z6solveUPfS_iPfS_i jmp .L80 .L88: pxor %xmm0, %xmm0 cvtsd2ss 24(%rsp), %xmm0 pxor %xmm1, %xmm1 cvtsd2ss 16(%rsp), %xmm1 movl %r12d, %ecx movq 104(%rsp), %rdx movq 48(%rsp), %rsi movq 40(%rsp), %rdi call _Z35__device_stub__Z9computeKTPfS_S_iffPfS_S_iff jmp .L81 .L89: call __stack_chk_fail@PLT .cfi_endproc .LFE2062: .size main, .-main .section .rodata.str1.1 .LC13: .string "_Z6solveUPfS_i" .LC14: .string "_Z6solveLPfS_i" .LC15: .string "_Z2LUPfii" .LC16: .string "_Z8computeKPfS_S_i" .LC17: .string "_Z9computeKTPfS_S_iff" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2098: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC13(%rip), %rdx movq %rdx, %rcx leaq _Z6solveUPfS_i(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC14(%rip), %rdx movq %rdx, %rcx leaq _Z6solveLPfS_i(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC15(%rip), %rdx movq %rdx, %rcx leaq _Z2LUPfii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC16(%rip), %rdx movq %rdx, %rcx leaq _Z8computeKPfS_S_i(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC17(%rip), %rdx movq %rdx, %rcx leaq _Z9computeKTPfS_S_iff(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2098: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC3: .long 0 .long 1071644672 .align 8 .LC4: .long 0 .long 1072693248 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC5: .long 805306368 .section .rodata.cst8 .align 8 .LC6: .long -1610612736 .long 1069128089 .section .rodata.cst4 .align 4 .LC7: .long 1065353216 .align 4 .LC9: .long 1148846080 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9computeKTPfS_S_iff ; -- Begin function _Z9computeKTPfS_S_iff .globl _Z9computeKTPfS_S_iff .p2align 8 .type _Z9computeKTPfS_S_iff,@function _Z9computeKTPfS_S_iff: ; @_Z9computeKTPfS_S_iff ; %bb.0: s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[8:9], s[0:1], 0x10 s_mov_b32 s2, s15 s_ashr_i32 s3, s15, 31 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b64 s[2:3], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s4, s4, s2 s_addc_u32 s5, s5, s3 s_add_u32 s6, s6, s2 s_addc_u32 s7, s7, s3 s_load_b64 s[0:1], s[0:1], 0x1c s_load_b32 s6, s[6:7], 0x0 s_load_b32 s4, s[4:5], 0x0 s_mov_b32 s5, 0x3e5ade15 s_waitcnt lgkmcnt(0) v_sub_f32_e64 v0, s1, s6 v_sub_f32_e64 v1, s0, s4 s_mov_b32 s1, 0xbff71547 s_mov_b32 s0, 0x652b82fe s_mov_b32 s4, 0x6a5dcb37 v_mul_f32_e32 v6, v0, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v6, v1, v1 v_cvt_f64_f32_e32 v[0:1], v6 v_cmp_nlt_f32_e32 vcc_lo, 0x44866000, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mul_f64 v[2:3], v[0:1], s[0:1] s_mov_b32 s1, 0xbfe62e42 s_mov_b32 s0, 0xfefa39ef v_rndne_f64_e32 v[2:3], v[2:3] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[0:1], v[2:3], s[0:1], -v[0:1] s_mov_b32 s1, 0xbc7abc9e s_mov_b32 s0, 0x3b39803f s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[0:1], v[2:3], s[0:1], v[0:1] s_mov_b32 s1, 0x3e928af3 s_mov_b32 s0, 0xfca7ab0c v_cvt_i32_f64_e32 v2, v[2:3] s_delay_alu instid0(VALU_DEP_2) v_fma_f64 v[4:5], v[0:1], s[4:5], s[0:1] s_mov_b32 s1, 0x3ec71dee s_mov_b32 s0, 0x623fde64 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[4:5], v[0:1], v[4:5], s[0:1] s_mov_b32 s1, 0x3efa0199 s_mov_b32 s0, 0x7c89e6b0 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[4:5], v[0:1], v[4:5], s[0:1] s_mov_b32 s1, 0x3f2a01a0 s_mov_b32 s0, 0x14761f6e s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[4:5], v[0:1], v[4:5], s[0:1] s_mov_b32 s1, 0x3f56c16c s_mov_b32 s0, 0x1852b7b0 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[4:5], v[0:1], v[4:5], s[0:1] s_mov_b32 s1, 0x3f811111 s_mov_b32 s0, 0x11122322 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[4:5], v[0:1], v[4:5], s[0:1] s_mov_b32 s1, 0x3fa55555 s_mov_b32 s0, 0x555502a1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[4:5], v[0:1], v[4:5], s[0:1] s_mov_b32 s1, 0x3fc55555 s_mov_b32 s0, 0x55555511 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[4:5], v[0:1], v[4:5], s[0:1] s_mov_b32 s1, 0x3fe00000 s_mov_b32 s0, 11 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_fma_f64 v[4:5], v[0:1], v[4:5], s[0:1] s_add_u32 s0, s8, s2 s_addc_u32 s1, s9, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[4:5], v[0:1], v[4:5], 1.0 v_fma_f64 v[0:1], v[0:1], v[4:5], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[0:1], v[0:1], v2 v_cvt_f32_f64_e32 v0, v[0:1] s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v1, 0 :: v_dual_cndmask_b32 v0, 0, v0 global_store_b32 v1, v0, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9computeKTPfS_S_iff .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 36 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9computeKTPfS_S_iff, .Lfunc_end0-_Z9computeKTPfS_S_iff ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 556 ; NumSgprs: 18 ; NumVgprs: 7 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 0 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 7 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z8computeKPfS_S_i ; -- Begin function _Z8computeKPfS_S_i .globl _Z8computeKPfS_S_i .p2align 8 .type _Z8computeKPfS_S_i,@function _Z8computeKPfS_S_i: ; @_Z8computeKPfS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s33, s[0:1], 0x18 s_mov_b32 s41, 0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cvt_f32_u32_e32 v1, s2 s_sub_i32 s4, 0, s2 v_rcp_iflag_f32_e32 v1, v1 s_waitcnt_depctr 0xfff v_mul_f32_e32 v1, 0x4f7ffffe, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v1, v1 v_readfirstlane_b32 s3, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s4, s4, s3 s_mul_hi_u32 s4, s3, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s3, s3, s4 s_mul_hi_u32 s3, s33, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_mul_i32 s4, s3, s2 s_add_i32 s5, s3, 1 s_sub_i32 s4, s33, s4 s_sub_i32 s6, s4, s2 s_cmp_ge_u32 s4, s2 s_cselect_b32 s3, s5, s3 s_cselect_b32 s4, s6, s4 s_add_i32 s5, s3, 1 s_cmp_ge_u32 s4, s2 s_cselect_b32 s40, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lt_i32 s40, 1 s_cbranch_scc1 .LBB1_10 ; %bb.1: ; %.lr.ph49 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 v_mul_lo_u32 v6, s40, v0 v_mov_b32_e32 v7, 0 s_cmp_gt_i32 s33, 0 s_mov_b32 s3, 0xbff71547 s_cselect_b32 s42, -1, 0 s_mov_b32 s2, 0x652b82fe s_mov_b32 s9, 0xbfe62e42 s_mov_b32 s8, 0xfefa39ef v_mul_lo_u32 v8, v6, s33 v_mov_b32_e32 v9, v6 s_mov_b32 s11, 0xbc7abc9e s_mov_b32 s10, 0x3b39803f s_mov_b32 s13, 0x3e928af3 s_mov_b32 s12, 0xfca7ab0c s_mov_b32 s15, 0x3e5ade15 s_mov_b32 s14, 0x6a5dcb37 s_mov_b32 s17, 0x3ec71dee s_mov_b32 s16, 0x623fde64 s_mov_b32 s19, 0x3efa0199 s_mov_b32 s18, 0x7c89e6b0 s_mov_b32 s21, 0x3f2a01a0 s_mov_b32 s20, 0x14761f6e s_mov_b32 s23, 0x3f56c16c s_mov_b32 s22, 0x1852b7b0 s_mov_b32 s25, 0x3f811111 s_mov_b32 s24, 0x11122322 s_mov_b32 s27, 0x3fa55555 s_mov_b32 s26, 0x555502a1 s_mov_b32 s29, 0x3fc55555 s_mov_b32 s28, 0x55555511 s_mov_b32 s31, 0x3fe00000 s_mov_b32 s30, 11 s_mov_b32 s35, 0x3f847ae1 s_mov_b32 s34, 0x47ae147b s_mov_b32 s43, 0 ; implicit-def: $sgpr44 s_branch .LBB1_4 .LBB1_2: ; %._crit_edge ; in Loop: Header=BB1_4 Depth=1 s_add_i32 s43, s43, 1 v_add_nc_u32_e32 v9, 1, v9 s_cmp_ge_i32 s43, s40 v_add_nc_u32_e32 v8, s33, v8 s_cselect_b32 s36, -1, 0 s_and_not1_b32 s37, s44, exec_lo s_and_b32 s36, s36, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s44, s37, s36 .LBB1_3: ; %Flow71 ; in Loop: Header=BB1_4 Depth=1 s_or_b32 exec_lo, exec_lo, s45 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s36, exec_lo, s44 s_or_b32 s41, s36, s41 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s41 s_cbranch_execz .LBB1_10 .LBB1_4: ; =>This Loop Header: Depth=1 ; Child Loop BB1_8 Depth 2 v_add_nc_u32_e32 v0, s43, v6 s_or_b32 s44, s44, exec_lo s_mov_b32 s45, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s33, v0 s_cbranch_execz .LBB1_3 ; %bb.5: ; %.preheader ; in Loop: Header=BB1_4 Depth=1 s_and_not1_b32 vcc_lo, exec_lo, s42 s_cbranch_vccnz .LBB1_2 ; %bb.6: ; %.lr.ph ; in Loop: Header=BB1_4 Depth=1 v_ashrrev_i32_e32 v1, 31, v0 v_mov_b32_e32 v10, v9 s_waitcnt lgkmcnt(0) s_mov_b64 s[36:37], s[6:7] s_mov_b64 s[38:39], s[4:5] s_mov_b32 s46, s33 v_lshlrev_b64 v[4:5], 2, v[0:1] v_mov_b32_e32 v0, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v2, vcc_lo, s4, v4 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo s_branch .LBB1_8 .LBB1_7: ; in Loop: Header=BB1_8 Depth=2 s_or_b32 exec_lo, exec_lo, s47 v_ashrrev_i32_e32 v1, 31, v0 s_add_i32 s46, s46, -1 s_add_u32 s38, s38, 4 v_add_nc_u32_e32 v10, -1, v10 s_addc_u32 s39, s39, 0 v_lshlrev_b64 v[12:13], 2, v[0:1] v_add_nc_u32_e32 v0, 1, v0 s_add_u32 s36, s36, 4 s_addc_u32 s37, s37, 0 s_cmp_lg_u32 s46, 0 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v12, vcc_lo, s0, v12 v_add_co_ci_u32_e32 v13, vcc_lo, s1, v13, vcc_lo global_store_b32 v[12:13], v11, off s_cbranch_scc0 .LBB1_2 .LBB1_8: ; Parent Loop BB1_4 Depth=1 ; => This Inner Loop Header: Depth=2 global_load_b32 v1, v[4:5], off s_clause 0x1 global_load_b32 v11, v7, s[36:37] global_load_b32 v12, v7, s[38:39] global_load_b32 v13, v[2:3], off s_mov_b32 s47, exec_lo s_waitcnt vmcnt(2) v_sub_f32_e32 v1, v1, v11 s_waitcnt vmcnt(0) v_sub_f32_e32 v11, v13, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v1, v1, v1 v_fmac_f32_e32 v1, v11, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cvt_f64_f32_e32 v[11:12], v1 v_cmp_nlt_f32_e32 vcc_lo, 0x44866000, v1 v_mul_f64 v[13:14], v[11:12], s[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_rndne_f64_e32 v[13:14], v[13:14] v_fma_f64 v[11:12], v[13:14], s[8:9], -v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[11:12], v[13:14], s[10:11], v[11:12] v_cvt_i32_f64_e32 v13, v[13:14] v_fma_f64 v[15:16], v[11:12], s[14:15], s[12:13] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[15:16], v[11:12], v[15:16], s[16:17] v_fma_f64 v[15:16], v[11:12], v[15:16], s[18:19] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[15:16], v[11:12], v[15:16], s[20:21] v_fma_f64 v[15:16], v[11:12], v[15:16], s[22:23] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[15:16], v[11:12], v[15:16], s[24:25] v_fma_f64 v[15:16], v[11:12], v[15:16], s[26:27] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[15:16], v[11:12], v[15:16], s[28:29] v_fma_f64 v[15:16], v[11:12], v[15:16], s[30:31] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[15:16], v[11:12], v[15:16], 1.0 v_fma_f64 v[11:12], v[11:12], v[15:16], 1.0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[11:12], v[11:12], v13 v_cvt_f32_f64_e32 v11, v[11:12] s_delay_alu instid0(VALU_DEP_1) v_cndmask_b32_e32 v11, 0, v11, vcc_lo v_cmpx_eq_u32_e32 0, v10 s_cbranch_execz .LBB1_7 ; %bb.9: ; in Loop: Header=BB1_8 Depth=2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_f64_f32_e32 v[11:12], v11 v_add_f64 v[11:12], v[11:12], s[34:35] s_delay_alu instid0(VALU_DEP_1) v_cvt_f32_f64_e32 v11, v[11:12] s_branch .LBB1_7 .LBB1_10: ; %.critedge s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z8computeKPfS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 17 .amdhsa_next_free_sgpr 48 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z8computeKPfS_S_i, .Lfunc_end1-_Z8computeKPfS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 984 ; NumSgprs: 50 ; NumVgprs: 17 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 6 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 50 ; NumVGPRsForWavesPerEU: 17 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z2LUPfii ; -- Begin function _Z2LUPfii .globl _Z2LUPfii .p2align 8 .type _Z2LUPfii,@function _Z2LUPfii: ; @_Z2LUPfii ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b32 s10, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s7, s2, 0xffff s_cmp_lt_i32 s10, 2 v_cvt_f32_u32_e32 v1, s7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v1, v1 s_waitcnt_depctr 0xfff v_mul_f32_e32 v1, 0x4f7ffffe, v1 v_cvt_u32_f32_e32 v1, v1 s_delay_alu instid0(VALU_DEP_1) v_readfirstlane_b32 s2, v1 s_cbranch_scc1 .LBB2_14 ; %bb.1: ; %.preheader65.lr.ph s_sub_i32 s3, 0, s7 s_load_b64 s[4:5], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) s_mul_i32 s3, s3, s2 v_mul_lo_u32 v6, v0, s10 s_mul_hi_u32 s3, s2, s3 s_mul_i32 s15, s10, s7 s_add_i32 s2, s2, s3 s_mov_b32 s3, 0 s_mul_hi_u32 s2, s10, s2 v_mov_b32_e32 v8, 0 s_mul_i32 s6, s2, s7 s_add_i32 s1, s2, 1 s_sub_i32 s0, s10, s6 v_add_nc_u32_e32 v7, 1, v6 s_sub_i32 s6, s0, s7 s_cmp_ge_u32 s0, s7 s_cselect_b32 s1, s1, s2 s_cselect_b32 s0, s6, s0 s_add_i32 s6, s1, 1 s_cmp_ge_u32 s0, s7 s_mov_b32 s2, 1 s_cselect_b32 s11, s6, s1 s_add_i32 s12, s10, 1 s_cmp_gt_i32 s11, 0 s_mov_b32 s6, s3 s_cselect_b32 s13, -1, 0 s_add_i32 s14, s10, -2 s_branch .LBB2_3 .LBB2_2: ; %._crit_edge ; in Loop: Header=BB2_3 Depth=1 s_set_inst_prefetch_distance 0x2 v_add_nc_u32_e32 v6, 1, v6 v_add_nc_u32_e32 v7, 1, v7 s_add_i32 s0, s6, 1 s_add_i32 s2, s2, s12 s_cmp_lg_u32 s6, s14 s_mov_b32 s6, s0 s_waitcnt lgkmcnt(0) s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB2_14 .LBB2_3: ; %.preheader65 ; =>This Loop Header: Depth=1 ; Child Loop BB2_6 Depth 2 ; Child Loop BB2_11 Depth 2 ; Child Loop BB2_13 Depth 3 s_and_not1_b32 vcc_lo, exec_lo, s13 s_cbranch_vccnz .LBB2_8 ; %bb.4: ; %.lr.ph ; in Loop: Header=BB2_3 Depth=1 s_mul_i32 s0, s6, s12 v_mov_b32_e32 v1, v6 s_ashr_i32 s1, s0, 31 v_mov_b32_e32 v3, v0 s_lshl_b64 s[0:1], s[0:1], 2 s_waitcnt lgkmcnt(0) s_add_u32 s8, s4, s0 s_addc_u32 s9, s5, s1 s_mov_b32 s1, 0 s_set_inst_prefetch_distance 0x1 s_branch .LBB2_6 .p2align 6 .LBB2_5: ; in Loop: Header=BB2_6 Depth=2 s_or_b32 exec_lo, exec_lo, s0 v_add_nc_u32_e32 v3, s7, v3 v_add_nc_u32_e32 v1, s15, v1 s_add_i32 s1, s1, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_ge_i32 s1, s11 s_cbranch_scc1 .LBB2_8 .LBB2_6: ; Parent Loop BB2_3 Depth=1 ; => This Inner Loop Header: Depth=2 v_cmp_lt_i32_e32 vcc_lo, s6, v3 v_cmp_gt_i32_e64 s0, s10, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s16, vcc_lo, s0 s_and_saveexec_b32 s0, s16 s_cbranch_execz .LBB2_5 ; %bb.7: ; in Loop: Header=BB2_6 Depth=2 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[4:5], 2, v[1:2] v_add_co_u32 v4, vcc_lo, s4, v4 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo s_clause 0x1 global_load_b32 v2, v[4:5], off global_load_b32 v9, v8, s[8:9] s_waitcnt vmcnt(0) v_div_scale_f32 v10, null, v9, v9, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f32_e32 v11, v10 s_waitcnt_depctr 0xfff v_fma_f32 v12, -v10, v11, 1.0 v_fmac_f32_e32 v11, v12, v11 v_div_scale_f32 v12, vcc_lo, v2, v9, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v13, v12, v11 v_fma_f32 v14, -v10, v13, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v13, v14, v11 v_fma_f32 v10, -v10, v13, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f32 v10, v10, v11, v13 v_div_fixup_f32 v2, v10, v9, v2 global_store_b32 v[4:5], v2, off s_branch .LBB2_5 .LBB2_8: ; %.preheader64 ; in Loop: Header=BB2_3 Depth=1 s_set_inst_prefetch_distance 0x2 s_and_not1_b32 vcc_lo, exec_lo, s13 s_cbranch_vccnz .LBB2_2 ; %bb.9: ; %.lr.ph71 ; in Loop: Header=BB2_3 Depth=1 s_lshl_b64 s[0:1], s[2:3], 2 v_mov_b32_e32 v1, v7 s_waitcnt lgkmcnt(0) s_add_u32 s8, s4, s0 s_addc_u32 s9, s5, s1 s_add_i32 s16, s6, 1 s_mov_b32 s17, 0 s_set_inst_prefetch_distance 0x1 s_branch .LBB2_11 .p2align 6 .LBB2_10: ; %Flow95 ; in Loop: Header=BB2_11 Depth=2 s_or_b32 exec_lo, exec_lo, s18 v_add_nc_u32_e32 v1, s15, v1 s_add_i32 s17, s17, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lt_i32 s17, s11 s_cbranch_scc0 .LBB2_2 .LBB2_11: ; Parent Loop BB2_3 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB2_13 Depth 3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, s17, s7, v[0:1] v_cmp_lt_i32_e32 vcc_lo, s6, v2 v_cmp_gt_i32_e64 s0, s10, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s0, vcc_lo, s0 s_and_saveexec_b32 s18, s0 s_cbranch_execz .LBB2_10 ; %bb.12: ; %.lr.ph69 ; in Loop: Header=BB2_11 Depth=2 v_mad_u64_u32 v[3:4], null, v2, s10, s[6:7] v_ashrrev_i32_e32 v2, 31, v1 s_mov_b64 s[0:1], s[8:9] s_mov_b32 s19, s16 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[9:10], 2, v[1:2] v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v9 v_lshlrev_b64 v[4:5], 2, v[3:4] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v10, vcc_lo v_add_co_u32 v4, vcc_lo, s4, v4 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo .p2align 6 .LBB2_13: ; Parent Loop BB2_3 Depth=1 ; Parent Loop BB2_11 Depth=2 ; => This Inner Loop Header: Depth=3 global_load_b32 v9, v[2:3], off global_load_b32 v10, v[4:5], off global_load_b32 v11, v8, s[0:1] s_add_i32 s19, s19, 1 s_add_u32 s0, s0, 4 s_addc_u32 s1, s1, 0 s_cmp_lt_i32 s19, s10 s_waitcnt vmcnt(0) v_fma_f32 v9, -v10, v11, v9 global_store_b32 v[2:3], v9, off v_add_co_u32 v2, vcc_lo, v2, 4 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo s_cbranch_scc1 .LBB2_13 s_branch .LBB2_10 .LBB2_14: ; %._crit_edge73 s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z2LUPfii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 15 .amdhsa_next_free_sgpr 20 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z2LUPfii, .Lfunc_end2-_Z2LUPfii ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 796 ; NumSgprs: 22 ; NumVgprs: 15 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 22 ; NumVGPRsForWavesPerEU: 15 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z6solveLPfS_i ; -- Begin function _Z6solveLPfS_i .globl _Z6solveLPfS_i .p2align 8 .type _Z6solveLPfS_i,@function _Z6solveLPfS_i: ; @_Z6solveLPfS_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b32 s8, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_cmp_lt_i32 s8, 2 v_cvt_f32_u32_e32 v1, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v1, v1 s_waitcnt_depctr 0xfff v_mul_f32_e32 v1, 0x4f7ffffe, v1 v_cvt_u32_f32_e32 v1, v1 s_delay_alu instid0(VALU_DEP_1) v_readfirstlane_b32 s3, v1 s_cbranch_scc1 .LBB3_8 ; %bb.1: ; %.preheader.lr.ph s_sub_i32 s4, 0, s2 v_mov_b32_e32 v6, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s4, s4, s3 s_mul_hi_u32 s4, s3, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_add_i32 s3, s3, s4 s_load_b128 s[4:7], s[0:1], 0x0 s_mul_hi_u32 s0, s8, s3 s_mul_i32 s1, s0, s2 s_add_i32 s3, s0, 1 s_sub_i32 s1, s8, s1 s_delay_alu instid0(SALU_CYCLE_1) s_sub_i32 s9, s1, s2 s_cmp_ge_u32 s1, s2 s_cselect_b32 s0, s3, s0 s_cselect_b32 s1, s9, s1 s_add_i32 s3, s0, 1 s_cmp_ge_u32 s1, s2 s_mov_b32 s2, 1 s_cselect_b32 s1, s3, s0 s_mov_b32 s3, 0 v_mul_lo_u32 v5, s1, v0 s_waitcnt lgkmcnt(0) s_add_u32 s9, s6, -4 s_addc_u32 s10, s7, -1 s_add_u32 s11, s4, -4 s_addc_u32 s12, s5, -1 s_cmp_gt_i32 s1, 0 s_delay_alu instid0(VALU_DEP_1) v_mad_u64_u32 v[0:1], null, v5, s8, 1 s_cselect_b32 s13, -1, 0 s_set_inst_prefetch_distance 0x1 s_branch .LBB3_3 .p2align 6 .LBB3_2: ; %._crit_edge ; in Loop: Header=BB3_3 Depth=1 s_delay_alu instid0(VALU_DEP_1) v_add_nc_u32_e32 v0, 1, v0 s_add_i32 s2, s2, 1 s_waitcnt_vscnt null, 0x0 s_cmp_lg_u32 s2, s8 s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB3_8 .LBB3_3: ; %.preheader ; =>This Loop Header: Depth=1 ; Child Loop BB3_6 Depth 2 s_and_not1_b32 vcc_lo, exec_lo, s13 s_cbranch_vccnz .LBB3_2 ; %bb.4: ; %.lr.ph ; in Loop: Header=BB3_3 Depth=1 s_lshl_b64 s[6:7], s[2:3], 2 s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v1, v0 s_add_u32 s6, s11, s6 s_addc_u32 s7, s12, s7 s_mov_b32 s14, 0 s_branch .LBB3_6 .p2align 6 .LBB3_5: ; in Loop: Header=BB3_6 Depth=2 s_or_b32 exec_lo, exec_lo, s0 v_add_nc_u32_e32 v1, s8, v1 s_add_i32 s14, s14, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lt_i32 s14, s1 s_cbranch_scc0 .LBB3_2 .LBB3_6: ; Parent Loop BB3_3 Depth=1 ; => This Inner Loop Header: Depth=2 v_add_nc_u32_e32 v3, s14, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_le_i32_e32 vcc_lo, s2, v3 v_cmp_gt_i32_e64 s0, s8, v3 s_and_b32 s15, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s0, s15 s_cbranch_execz .LBB3_5 ; %bb.7: ; in Loop: Header=BB3_6 Depth=2 v_ashrrev_i32_e32 v4, 31, v3 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[3:4], 2, v[3:4] v_lshlrev_b64 v[7:8], 2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v2, vcc_lo, s4, v3 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v7, vcc_lo, s9, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s10, v8, vcc_lo global_load_b32 v4, v[2:3], off global_load_b32 v7, v[7:8], off global_load_b32 v8, v6, s[6:7] s_waitcnt vmcnt(0) v_fma_f32 v4, -v7, v8, v4 global_store_b32 v[2:3], v4, off s_branch .LBB3_5 .LBB3_8: ; %._crit_edge33 s_set_inst_prefetch_distance 0x2 s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6solveLPfS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end3: .size _Z6solveLPfS_i, .Lfunc_end3-_Z6solveLPfS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 472 ; NumSgprs: 18 ; NumVgprs: 9 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 9 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .protected _Z6solveUPfS_i ; -- Begin function _Z6solveUPfS_i .globl _Z6solveUPfS_i .p2align 8 .type _Z6solveUPfS_i,@function _Z6solveUPfS_i: ; @_Z6solveUPfS_i ; %bb.0: s_clause 0x2 s_load_b32 s2, s[0:1], 0x24 s_load_b32 s10, s[0:1], 0x10 s_load_b128 s[4:7], s[0:1], 0x0 s_mov_b32 s3, 0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_cmp_lt_i32 s10, 2 v_cvt_f32_u32_e32 v1, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v1, v1 s_waitcnt_depctr 0xfff v_mul_f32_e32 v1, 0x4f7ffffe, v1 v_cvt_u32_f32_e32 v1, v1 s_delay_alu instid0(VALU_DEP_1) v_readfirstlane_b32 s0, v1 s_cbranch_scc1 .LBB4_10 ; %bb.1: ; %.lr.ph43 s_sub_i32 s1, 0, s2 v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_mul_i32 s1, s1, s0 s_mov_b32 s14, s10 s_mul_hi_u32 s1, s0, s1 s_add_i32 s0, s0, s1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_hi_u32 s0, s10, s0 s_mul_i32 s1, s0, s2 s_add_i32 s8, s0, 1 s_sub_i32 s1, s10, s1 s_delay_alu instid0(SALU_CYCLE_1) s_sub_i32 s9, s1, s2 s_cmp_ge_u32 s1, s2 s_cselect_b32 s0, s8, s0 s_cselect_b32 s1, s9, s1 s_add_i32 s8, s0, 1 s_cmp_ge_u32 s1, s2 s_cselect_b32 s11, s8, s0 v_cmp_eq_u32_e64 s0, 0, v0 v_mul_lo_u32 v5, s11, v0 s_add_i32 s12, s10, 1 s_cmp_gt_i32 s11, 0 s_cselect_b32 s13, -1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v1, s10, v5 v_add3_u32 v6, v1, s10, -1 s_branch .LBB4_3 .LBB4_2: ; %._crit_edge ; in Loop: Header=BB4_3 Depth=1 s_set_inst_prefetch_distance 0x2 v_add_nc_u32_e32 v6, -1, v6 s_cmp_gt_i32 s14, 2 s_mov_b32 s14, s2 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB4_10 .LBB4_3: ; =>This Loop Header: Depth=1 ; Child Loop BB4_8 Depth 2 s_add_i32 s2, s14, -1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB4_5 ; %bb.4: ; in Loop: Header=BB4_3 Depth=1 s_lshl_b64 s[8:9], s[2:3], 2 s_mul_i32 s16, s2, s12 s_add_u32 s8, s4, s8 s_addc_u32 s9, s5, s9 s_ashr_i32 s17, s16, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_lshl_b64 s[16:17], s[16:17], 2 s_add_u32 s16, s6, s16 s_addc_u32 s17, s7, s17 s_clause 0x1 global_load_b32 v1, v2, s[8:9] global_load_b32 v3, v2, s[16:17] s_waitcnt vmcnt(0) v_div_scale_f32 v4, null, v3, v3, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f32_e32 v7, v4 s_waitcnt_depctr 0xfff v_fma_f32 v8, -v4, v7, 1.0 v_fmac_f32_e32 v7, v8, v7 v_div_scale_f32 v8, vcc_lo, v1, v3, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v9, v8, v7 v_fma_f32 v10, -v4, v9, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v9, v10, v7 v_fma_f32 v4, -v4, v9, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f32 v4, v4, v7, v9 v_div_fixup_f32 v1, v4, v3, v1 global_store_b32 v2, v1, s[8:9] .LBB4_5: ; in Loop: Header=BB4_3 Depth=1 s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 vcc_lo, exec_lo, s13 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_cbranch_vccnz .LBB4_2 ; %bb.6: ; %.lr.ph ; in Loop: Header=BB4_3 Depth=1 s_lshl_b64 s[8:9], s[2:3], 2 v_mov_b32_e32 v3, v6 s_add_u32 s8, s4, s8 s_addc_u32 s9, s5, s9 s_mov_b32 s15, 0 s_set_inst_prefetch_distance 0x1 s_branch .LBB4_8 .p2align 6 .LBB4_7: ; in Loop: Header=BB4_8 Depth=2 s_or_b32 exec_lo, exec_lo, s1 v_add_nc_u32_e32 v3, s10, v3 s_add_i32 s15, s15, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lt_i32 s15, s11 s_cbranch_scc0 .LBB4_2 .LBB4_8: ; Parent Loop BB4_3 Depth=1 ; => This Inner Loop Header: Depth=2 v_add_nc_u32_e32 v1, s15, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_lt_i32_e32 vcc_lo, -1, v1 v_cmp_gt_i32_e64 s1, s2, v1 s_and_b32 s16, vcc_lo, s1 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s1, s16 s_cbranch_execz .LBB4_7 ; %bb.9: ; in Loop: Header=BB4_8 Depth=2 v_ashrrev_i32_e32 v4, 31, v3 v_lshlrev_b64 v[7:8], 2, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshlrev_b64 v[9:10], 2, v[3:4] v_add_co_u32 v7, vcc_lo, s4, v7 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo v_add_co_u32 v9, vcc_lo, s6, v9 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo global_load_b32 v1, v[7:8], off global_load_b32 v4, v[9:10], off global_load_b32 v9, v2, s[8:9] s_waitcnt vmcnt(0) v_fma_f32 v1, -v4, v9, v1 global_store_b32 v[7:8], v1, off s_branch .LBB4_7 .LBB4_10: ; %._crit_edge44 s_mov_b32 s0, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB4_12 ; %bb.11: v_mov_b32_e32 v0, 0 s_clause 0x1 global_load_b32 v1, v0, s[4:5] global_load_b32 v2, v0, s[6:7] s_waitcnt vmcnt(0) v_div_scale_f32 v3, null, v2, v2, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f32_e32 v4, v3 s_waitcnt_depctr 0xfff v_fma_f32 v5, -v3, v4, 1.0 v_fmac_f32_e32 v4, v5, v4 v_div_scale_f32 v5, vcc_lo, v1, v2, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v6, v5, v4 v_fma_f32 v7, -v3, v6, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v6, v7, v4 v_fma_f32 v3, -v3, v6, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f32 v3, v3, v4, v6 v_div_fixup_f32 v1, v3, v2, v1 global_store_b32 v0, v1, s[4:5] .LBB4_12: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6solveUPfS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 18 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end4: .size _Z6solveUPfS_i, .Lfunc_end4-_Z6solveUPfS_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 804 ; NumSgprs: 20 ; NumVgprs: 11 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 20 ; NumVGPRsForWavesPerEU: 11 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object ; @__hip_cuid_ .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 36 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9computeKTPfS_S_iff .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z9computeKTPfS_S_iff.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z8computeKPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 50 .sgpr_spill_count: 0 .symbol: _Z8computeKPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 17 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z2LUPfii .private_segment_fixed_size: 0 .sgpr_count: 22 .sgpr_spill_count: 0 .symbol: _Z2LUPfii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 15 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6solveLPfS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6solveLPfS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6solveUPfS_i .private_segment_fixed_size: 0 .sgpr_count: 20 .sgpr_spill_count: 0 .symbol: _Z6solveUPfS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "5aec82e8b871266bf98edd01b278c533e4a3ee01.hip" .globl _Z9printVectPfi # -- Begin function _Z9printVectPfi .p2align 4, 0x90 .type _Z9printVectPfi,@function _Z9printVectPfi: # @_Z9printVectPfi .cfi_startproc # %bb.0: testl %esi, %esi jle .LBB0_4 # %bb.1: # %.lr.ph.preheader pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx movl %esi, %r14d xorl %r15d, %r15d .p2align 4, 0x90 .LBB0_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str, %edi movb $1, %al callq printf incq %r15 cmpq %r15, %r14 jne .LBB0_2 # %bb.3: popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 .cfi_restore %rbx .cfi_restore %r14 .cfi_restore %r15 .LBB0_4: # %._crit_edge movl $10, %edi jmp putchar@PLT # TAILCALL .Lfunc_end0: .size _Z9printVectPfi, .Lfunc_end0-_Z9printVectPfi .cfi_endproc # -- End function .globl _Z8printMatPfi # -- Begin function _Z8printMatPfi .p2align 4, 0x90 .type _Z8printMatPfi,@function _Z8printMatPfi: # @_Z8printMatPfi .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 pushq %rax .cfi_def_cfa_offset 64 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdi, (%rsp) # 8-byte Spill testl %esi, %esi jle .LBB1_5 # %bb.1: # %.preheader.lr.ph movl %esi, %ebx movl %esi, %r15d xorl %r12d, %r12d xorl %r13d, %r13d .p2align 4, 0x90 .LBB1_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_3 Depth 2 movl %r12d, %eax movq (%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %rbp xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_3: # Parent Loop BB1_2 Depth=1 # => This Inner Loop Header: Depth=2 movss (%rbp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str, %edi movb $1, %al callq printf incq %r14 cmpq %r14, %r15 jne .LBB1_3 # %bb.4: # %._crit_edge # in Loop: Header=BB1_2 Depth=1 movl $10, %edi callq putchar@PLT incq %r13 addl %ebx, %r12d cmpq %r15, %r13 jne .LBB1_2 .LBB1_5: # %._crit_edge13 addq $8, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z8printMatPfi, .Lfunc_end1-_Z8printMatPfi .cfi_endproc # -- End function .globl _Z13computePointsPfS_fi # -- Begin function _Z13computePointsPfS_fi .p2align 4, 0x90 .type _Z13computePointsPfS_fi,@function _Z13computePointsPfS_fi: # @_Z13computePointsPfS_fi .cfi_startproc # %bb.0: testl %edx, %edx jle .LBB2_5 # %bb.1: # %.preheader.preheader movl %edx, %eax negl %eax movl $1, %r8d xorl %ecx, %ecx .p2align 4, 0x90 .LBB2_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB2_3 Depth 2 xorps %xmm1, %xmm1 cvtsi2ss %r8d, %xmm1 mulss %xmm0, %xmm1 movslq %ecx, %rcx movl $1, %r9d .p2align 4, 0x90 .LBB2_3: # Parent Loop BB2_2 Depth=1 # => This Inner Loop Header: Depth=2 movss %xmm1, (%rdi,%rcx,4) xorps %xmm2, %xmm2 cvtsi2ss %r9d, %xmm2 mulss %xmm0, %xmm2 movss %xmm2, (%rsi,%rcx,4) incq %rcx leal (%rax,%r9), %r10d incl %r10d # kill: def $r9d killed $r9d killed $r9 incl %r9d # kill: def $r9d killed $r9d def $r9 cmpl $1, %r10d jne .LBB2_3 # %bb.4: # %._crit_edge # in Loop: Header=BB2_2 Depth=1 leal 1(%r8), %r9d cmpl %edx, %r8d movl %r9d, %r8d jne .LBB2_2 .LBB2_5: # %._crit_edge24 retq .Lfunc_end2: .size _Z13computePointsPfS_fi, .Lfunc_end2-_Z13computePointsPfS_fi .cfi_endproc # -- End function .globl _Z10computeResPfS_i # -- Begin function _Z10computeResPfS_i .p2align 4, 0x90 .type _Z10computeResPfS_i,@function _Z10computeResPfS_i: # @_Z10computeResPfS_i .cfi_startproc # %bb.0: testl %edx, %edx jle .LBB3_1 # %bb.2: # %.lr.ph.preheader movl %edx, %eax xorps %xmm0, %xmm0 xorl %ecx, %ecx .p2align 4, 0x90 .LBB3_3: # %.lr.ph # =>This Inner Loop Header: Depth=1 movss (%rdi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero mulss (%rsi,%rcx,4), %xmm1 addss %xmm1, %xmm0 incq %rcx cmpq %rcx, %rax jne .LBB3_3 # %bb.4: # %._crit_edge retq .LBB3_1: xorps %xmm0, %xmm0 retq .Lfunc_end3: .size _Z10computeResPfS_i, .Lfunc_end3-_Z10computeResPfS_i .cfi_endproc # -- End function .globl _Z24__device_stub__computeKTPfS_S_iff # -- Begin function _Z24__device_stub__computeKTPfS_S_iff .p2align 4, 0x90 .type _Z24__device_stub__computeKTPfS_S_iff,@function _Z24__device_stub__computeKTPfS_S_iff: # @_Z24__device_stub__computeKTPfS_S_iff .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movl %ecx, 20(%rsp) movss %xmm0, 16(%rsp) movss %xmm1, 12(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 20(%rsp), %rax movq %rax, 120(%rsp) leaq 16(%rsp), %rax movq %rax, 128(%rsp) leaq 12(%rsp), %rax movq %rax, 136(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z9computeKTPfS_S_iff, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end4: .size _Z24__device_stub__computeKTPfS_S_iff, .Lfunc_end4-_Z24__device_stub__computeKTPfS_S_iff .cfi_endproc # -- End function .globl _Z23__device_stub__computeKPfS_S_i # -- Begin function _Z23__device_stub__computeKPfS_S_i .p2align 4, 0x90 .type _Z23__device_stub__computeKPfS_S_i,@function _Z23__device_stub__computeKPfS_S_i: # @_Z23__device_stub__computeKPfS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z8computeKPfS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end5: .size _Z23__device_stub__computeKPfS_S_i, .Lfunc_end5-_Z23__device_stub__computeKPfS_S_i .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function _Z8computeFPfS_S_i .LCPI6_0: .long 0x30000000 # float 4.65661287E-10 .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI6_1: .quad 0xbfe0000000000000 # double -0.5 .LCPI6_2: .quad 0x3fb99999a0000000 # double 0.10000000149011612 .LCPI6_3: .quad 0x3ff0000000000000 # double 1 .text .globl _Z8computeFPfS_S_i .p2align 4, 0x90 .type _Z8computeFPfS_S_i,@function _Z8computeFPfS_S_i: # @_Z8computeFPfS_S_i .cfi_startproc # %bb.0: testl %ecx, %ecx jle .LBB6_4 # %bb.1: # %.lr.ph.preheader pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdx, %rbx movq %rsi, %r14 movq %rdi, %r15 movl %ecx, %r12d xorl %r13d, %r13d .p2align 4, 0x90 .LBB6_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI6_0(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movsd .LCPI6_1(%rip), %xmm3 # xmm3 = mem[0],zero addsd %xmm3, %xmm0 mulsd .LCPI6_2(%rip), %xmm0 cvtsd2ss %xmm0, %xmm0 movss (%r15,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero cvtss2sd %xmm1, %xmm1 addsd %xmm3, %xmm1 mulsd %xmm1, %xmm1 movss (%r14,%r13,4), %xmm2 # xmm2 = mem[0],zero,zero,zero cvtss2sd %xmm2, %xmm2 addsd %xmm3, %xmm2 mulsd %xmm2, %xmm2 addsd %xmm1, %xmm2 movsd .LCPI6_3(%rip), %xmm1 # xmm1 = mem[0],zero subsd %xmm2, %xmm1 cvtss2sd %xmm0, %xmm0 addsd %xmm1, %xmm0 cvtsd2ss %xmm0, %xmm0 movss %xmm0, (%rbx,%r13,4) incq %r13 cmpq %r13, %r12 jne .LBB6_2 # %bb.3: popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 .cfi_restore %rbx .cfi_restore %r12 .cfi_restore %r13 .cfi_restore %r14 .cfi_restore %r15 .LBB6_4: # %._crit_edge retq .Lfunc_end6: .size _Z8computeFPfS_S_i, .Lfunc_end6-_Z8computeFPfS_S_i .cfi_endproc # -- End function .globl _Z17__device_stub__LUPfii # -- Begin function _Z17__device_stub__LUPfii .p2align 4, 0x90 .type _Z17__device_stub__LUPfii,@function _Z17__device_stub__LUPfii: # @_Z17__device_stub__LUPfii .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) movq %rsp, %rax movq %rax, 80(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z2LUPfii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end7: .size _Z17__device_stub__LUPfii, .Lfunc_end7-_Z17__device_stub__LUPfii .cfi_endproc # -- End function .globl _Z21__device_stub__solveLPfS_i # -- Begin function _Z21__device_stub__solveLPfS_i .p2align 4, 0x90 .type _Z21__device_stub__solveLPfS_i,@function _Z21__device_stub__solveLPfS_i: # @_Z21__device_stub__solveLPfS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6solveLPfS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end8: .size _Z21__device_stub__solveLPfS_i, .Lfunc_end8-_Z21__device_stub__solveLPfS_i .cfi_endproc # -- End function .globl _Z21__device_stub__solveUPfS_i # -- Begin function _Z21__device_stub__solveUPfS_i .p2align 4, 0x90 .type _Z21__device_stub__solveUPfS_i,@function _Z21__device_stub__solveUPfS_i: # @_Z21__device_stub__solveUPfS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6solveUPfS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end9: .size _Z21__device_stub__solveUPfS_i, .Lfunc_end9-_Z21__device_stub__solveUPfS_i .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI10_0: .long 0x3f800000 # float 1 .LCPI10_1: .long 0x30000000 # float 4.65661287E-10 .LCPI10_5: .long 0x447a0000 # float 1000 .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI10_2: .quad 0xbfe0000000000000 # double -0.5 .LCPI10_3: .quad 0x3fb99999a0000000 # double 0.10000000149011612 .LCPI10_4: .quad 0x3ff0000000000000 # double 1 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $280, %rsp # imm = 0x118 .cfi_def_cfa_offset 336 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %rbx movq 8(%rsi), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r12 movq 16(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 264(%rsp) # 8-byte Spill movq 24(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 256(%rsp) # 8-byte Spill movq 32(%rbx), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r13 movl %r12d, %eax imull %eax, %eax movq %rax, 80(%rsp) # 8-byte Spill leal (,%rax,4), %eax movl %eax, 96(%rsp) # 4-byte Spill movslq %eax, %r15 movq %r15, %rdi callq malloc movq %rax, %rbx movq %r15, %rdi callq malloc movq %rax, %r14 movq %r15, %rdi callq malloc movq %rax, %rbp testl %r12d, %r12d jle .LBB10_5 # %bb.1: # %.preheader.i.preheader leal 1(%r12), %eax cvtsi2ss %eax, %xmm1 movss .LCPI10_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero divss %xmm1, %xmm0 movl %r12d, %eax negl %eax movl $1, %edx xorl %ecx, %ecx .p2align 4, 0x90 .LBB10_2: # %.preheader.i # =>This Loop Header: Depth=1 # Child Loop BB10_3 Depth 2 xorps %xmm1, %xmm1 cvtsi2ss %edx, %xmm1 mulss %xmm0, %xmm1 movslq %ecx, %rcx movl $1, %esi .p2align 4, 0x90 .LBB10_3: # Parent Loop BB10_2 Depth=1 # => This Inner Loop Header: Depth=2 movss %xmm1, (%rbx,%rcx,4) xorps %xmm2, %xmm2 cvtsi2ss %esi, %xmm2 mulss %xmm0, %xmm2 movss %xmm2, (%r14,%rcx,4) incq %rcx leal (%rax,%rsi), %edi incl %edi # kill: def $esi killed $esi killed $rsi incl %esi # kill: def $esi killed $esi def $rsi cmpl $1, %edi jne .LBB10_3 # %bb.4: # %._crit_edge.i # in Loop: Header=BB10_2 Depth=1 leal 1(%rdx), %esi cmpl %r12d, %edx movl %esi, %edx jne .LBB10_2 .LBB10_5: # %_Z13computePointsPfS_fi.exit movq %r13, 272(%rsp) # 8-byte Spill movq %r15, 240(%rsp) # 8-byte Spill movq 80(%rsp), %rax # 8-byte Reload movl 96(%rsp), %ecx # 4-byte Reload imull %eax, %ecx movl %ecx, 96(%rsp) # 4-byte Spill movl %eax, %r15d testl %r12d, %r12d je .LBB10_8 # %bb.6: # %.lr.ph.preheader.i xorl %r13d, %r13d .p2align 4, 0x90 .LBB10_7: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI10_1(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movsd .LCPI10_2(%rip), %xmm3 # xmm3 = mem[0],zero addsd %xmm3, %xmm0 mulsd .LCPI10_3(%rip), %xmm0 cvtsd2ss %xmm0, %xmm0 movss (%rbx,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero cvtss2sd %xmm1, %xmm1 addsd %xmm3, %xmm1 mulsd %xmm1, %xmm1 movss (%r14,%r13,4), %xmm2 # xmm2 = mem[0],zero,zero,zero cvtss2sd %xmm2, %xmm2 addsd %xmm3, %xmm2 mulsd %xmm2, %xmm2 addsd %xmm1, %xmm2 movsd .LCPI10_4(%rip), %xmm1 # xmm1 = mem[0],zero subsd %xmm2, %xmm1 cvtss2sd %xmm0, %xmm0 addsd %xmm1, %xmm0 cvtsd2ss %xmm0, %xmm0 movss %xmm0, (%rbp,%r13,4) incq %r13 cmpq %r13, %r15 jne .LBB10_7 .LBB10_8: # %_Z8computeFPfS_S_i.exit xorl %edi, %edi callq hipSetDevice leaq 136(%rsp), %rdi movq 240(%rsp), %r13 # 8-byte Reload movq %r13, %rsi callq hipMalloc leaq 128(%rsp), %rdi movq %r13, %rsi callq hipMalloc movslq 96(%rsp), %rsi # 4-byte Folded Reload leaq 120(%rsp), %rdi callq hipMalloc leaq 112(%rsp), %rdi movq %r13, %rsi callq hipMalloc movq 112(%rsp), %rdi movq %rbp, 96(%rsp) # 8-byte Spill movq %rbp, %rsi movq %r13, %rdx movl $1, %ecx callq hipMemcpy movq 136(%rsp), %rdi movq %rbx, %rsi movq %r13, %rdx movl $1, %ecx callq hipMemcpy movq 128(%rsp), %rdi movq %r14, %rsi movq %r13, %rdx movl $1, %ecx callq hipMemcpy movq 272(%rsp), %r13 # 8-byte Reload movl %r13d, %eax movabsq $4294967297, %rdi # imm = 0x100000001 leaq (%rax,%rdi), %rbp decq %rbp movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_10 # %bb.9: movq 136(%rsp), %rax movq 128(%rsp), %rcx movq 120(%rsp), %rdx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) movq %rdx, 56(%rsp) movq 80(%rsp), %rax # 8-byte Reload movl %eax, 88(%rsp) leaq 72(%rsp), %rax movq %rax, 144(%rsp) leaq 64(%rsp), %rax movq %rax, 152(%rsp) leaq 56(%rsp), %rax movq %rax, 160(%rsp) leaq 88(%rsp), %rax movq %rax, 168(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z8computeKPfS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_10: movl $.Lstr, %edi callq puts@PLT leaq 88(%rsp), %rdi callq hipEventCreate leaq 104(%rsp), %rdi callq hipEventCreate movq 88(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_12 # %bb.11: movq 120(%rsp), %rax movq %rax, 72(%rsp) movq 80(%rsp), %rax # 8-byte Reload movl %eax, 16(%rsp) movl %r13d, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 144(%rsp) leaq 16(%rsp), %rax movq %rax, 152(%rsp) leaq 8(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z2LUPfii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_12: movq 104(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 104(%rsp), %rdi callq hipEventSynchronize movq 88(%rsp), %rsi movq 104(%rsp), %rdx leaq 224(%rsp), %rdi callq hipEventElapsedTime movq 88(%rsp), %rdi callq hipEventDestroy movq 104(%rsp), %rdi callq hipEventDestroy movss 224(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero divss .LCPI10_5(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movl $.L.str.3, %edi movb $1, %al callq printf leaq 248(%rsp), %rdi callq hipEventCreate leaq 208(%rsp), %rdi callq hipEventCreate movq 88(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax movq 240(%rsp), %r13 # 8-byte Reload jne .LBB10_14 # %bb.13: movq 112(%rsp), %rax movq 120(%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) movq 80(%rsp), %rax # 8-byte Reload movl %eax, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 144(%rsp) leaq 64(%rsp), %rax movq %rax, 152(%rsp) leaq 8(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 56(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z6solveLPfS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_14: movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rbp, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_16 # %bb.15: movq 112(%rsp), %rax movq 120(%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) movq 80(%rsp), %rax # 8-byte Reload movl %eax, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 144(%rsp) leaq 64(%rsp), %rax movq %rax, 152(%rsp) leaq 8(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 56(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z6solveUPfS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_16: movq 208(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 104(%rsp), %rdi callq hipEventSynchronize movq 248(%rsp), %rsi movq 208(%rsp), %rdx leaq 220(%rsp), %rdi callq hipEventElapsedTime movq 248(%rsp), %rdi callq hipEventDestroy movq 208(%rsp), %rdi callq hipEventDestroy movss 220(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero divss .LCPI10_5(%rip), %xmm0 cvtss2sd %xmm0, %xmm0 movl $.L.str.4, %edi movb $1, %al callq printf movq %r13, %rdi callq malloc movq %rax, %rbp movq 112(%rsp), %rsi movq %rax, %rdi movq %r13, %rdx movl $2, %ecx callq hipMemcpy leaq 200(%rsp), %rdi movq %r13, %rsi callq hipMalloc movabsq $4294967297, %rdx # imm = 0x100000001 leaq (%rdx,%r15), %rdi decq %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB10_18 # %bb.17: movsd 264(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movsd 256(%rsp), %xmm1 # 8-byte Reload # xmm1 = mem[0],zero cvtsd2ss %xmm1, %xmm1 movq 136(%rsp), %rax movq 128(%rsp), %rcx movq 200(%rsp), %rdx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) movq %rdx, 56(%rsp) movq 80(%rsp), %rax # 8-byte Reload movl %eax, 236(%rsp) movss %xmm0, 232(%rsp) movss %xmm1, 228(%rsp) leaq 72(%rsp), %rax movq %rax, 144(%rsp) leaq 64(%rsp), %rax movq %rax, 152(%rsp) leaq 56(%rsp), %rax movq %rax, 160(%rsp) leaq 236(%rsp), %rax movq %rax, 168(%rsp) leaq 232(%rsp), %rax movq %rax, 176(%rsp) leaq 228(%rsp), %rax movq %rax, 184(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 144(%rsp), %r9 movl $_Z9computeKTPfS_S_iff, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB10_18: movq %r13, %rdi callq malloc movq %r13, %rdx movq %rax, %r13 movq 200(%rsp), %rsi movq %rax, %rdi movl $2, %ecx callq hipMemcpy testl %r12d, %r12d je .LBB10_19 # %bb.20: # %.lr.ph.i113.preheader xorps %xmm0, %xmm0 xorl %eax, %eax .p2align 4, 0x90 .LBB10_21: # %.lr.ph.i113 # =>This Inner Loop Header: Depth=1 movss (%r13,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero mulss (%rbp,%rax,4), %xmm1 addss %xmm1, %xmm0 incq %rax cmpq %rax, %r15 jne .LBB10_21 # %bb.22: # %_Z10computeResPfS_i.exit.loopexit cvtss2sd %xmm0, %xmm0 jmp .LBB10_23 .LBB10_19: xorps %xmm0, %xmm0 .LBB10_23: # %_Z10computeResPfS_i.exit movl $.L.str.5, %edi movb $1, %al callq printf movq %rbx, %rdi callq free movq %r14, %rdi callq free movq 96(%rsp), %rdi # 8-byte Reload callq free movq %rbp, %rdi callq free movq %r13, %rdi callq free movq 136(%rsp), %rdi callq hipFree movq 128(%rsp), %rdi callq hipFree movq 120(%rsp), %rdi callq hipFree movq 112(%rsp), %rdi callq hipFree movq 200(%rsp), %rdi callq hipFree xorl %eax, %eax addq $280, %rsp # imm = 0x118 .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end10: .size main, .Lfunc_end10-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB11_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB11_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9computeKTPfS_S_iff, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z8computeKPfS_S_i, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z2LUPfii, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6solveLPfS_i, %esi movl $.L__unnamed_4, %edx movl $.L__unnamed_4, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6solveUPfS_i, %esi movl $.L__unnamed_5, %edx movl $.L__unnamed_5, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end11: .size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB12_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB12_2: retq .Lfunc_end12: .size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%8.10f " .size .L.str, 8 .type _Z9computeKTPfS_S_iff,@object # @_Z9computeKTPfS_S_iff .section .rodata,"a",@progbits .globl _Z9computeKTPfS_S_iff .p2align 3, 0x0 _Z9computeKTPfS_S_iff: .quad _Z24__device_stub__computeKTPfS_S_iff .size _Z9computeKTPfS_S_iff, 8 .type _Z8computeKPfS_S_i,@object # @_Z8computeKPfS_S_i .globl _Z8computeKPfS_S_i .p2align 3, 0x0 _Z8computeKPfS_S_i: .quad _Z23__device_stub__computeKPfS_S_i .size _Z8computeKPfS_S_i, 8 .type _Z2LUPfii,@object # @_Z2LUPfii .globl _Z2LUPfii .p2align 3, 0x0 _Z2LUPfii: .quad _Z17__device_stub__LUPfii .size _Z2LUPfii, 8 .type _Z6solveLPfS_i,@object # @_Z6solveLPfS_i .globl _Z6solveLPfS_i .p2align 3, 0x0 _Z6solveLPfS_i: .quad _Z21__device_stub__solveLPfS_i .size _Z6solveLPfS_i, 8 .type _Z6solveUPfS_i,@object # @_Z6solveUPfS_i .globl _Z6solveUPfS_i .p2align 3, 0x0 _Z6solveUPfS_i: .quad _Z21__device_stub__solveUPfS_i .size _Z6solveUPfS_i, 8 .type .L.str.3,@object # @.str.3 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.3: .asciz "Time for LU factors routines: %4.10f s \n" .size .L.str.3, 42 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Time for solver routine is: %4.10f s \n" .size .L.str.4, 40 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz " result is: %8.10f\n" .size .L.str.5, 20 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9computeKTPfS_S_iff" .size .L__unnamed_1, 22 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z8computeKPfS_S_i" .size .L__unnamed_2, 19 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z2LUPfii" .size .L__unnamed_3, 10 .type .L__unnamed_4,@object # @3 .L__unnamed_4: .asciz "_Z6solveLPfS_i" .size .L__unnamed_4, 15 .type .L__unnamed_5,@object # @4 .L__unnamed_5: .asciz "_Z6solveUPfS_i" .size .L__unnamed_5, 15 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Start computing LU" .size .Lstr, 19 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__computeKTPfS_S_iff .addrsig_sym _Z23__device_stub__computeKPfS_S_i .addrsig_sym _Z17__device_stub__LUPfii .addrsig_sym _Z21__device_stub__solveLPfS_i .addrsig_sym _Z21__device_stub__solveUPfS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9computeKTPfS_S_iff .addrsig_sym _Z8computeKPfS_S_i .addrsig_sym _Z2LUPfii .addrsig_sym _Z6solveLPfS_i .addrsig_sym _Z6solveUPfS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
31,544
13,239
22,228
15,830
199
code for sm_80 Function : _Z9partitionPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; S2R R10, SR_CTAID.X ; IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x0] ; ULDC.64 UR4, c[0x0][0x118] ; S2R R3, SR_TID.X ; IMAD R10, R10, c[0x0][0x0], R3 ; IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x4] ; ISETP.GE.AND P0, PT, R10, c[0x0][0x178], PT ; STG.E [R2.64], RZ ; BAR.SYNC.DEFER_BLOCKING 0x0 ; @P0 EXIT ; HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; IMAD.WIDE R8, R10, R13, c[0x0][0x170] ; IMAD.WIDE R10, R10, R13.reuse, c[0x0][0x168] ; LDG.E R0, [R8.64] ; LDG.E R7, [R10.64] ; BSSY B0, 0x610 ; IMAD.WIDE R4, R0.reuse, R13, c[0x0][0x160] ; ISETP.GT.AND P0, PT, R0, R7, PT ; IADD3 R6, R7, -0x1, RZ ; @!P0 BRA 0x600 ; LDG.E R8, [R4.64] ; IMAD.IADD R9, R0.reuse, 0x1, -R7 ; LOP3.LUT R11, RZ, R7, RZ, 0x33, !PT ; BSSY B1, 0x340 ; LOP3.LUT P1, R12, R9, 0x3, RZ, 0xc0, !PT ; IMAD.IADD R11, R0, 0x1, R11 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; ISETP.GE.U32.AND P0, PT, R11, 0x3, PT ; @!P1 BRA 0x330 ; IMAD.WIDE R10, R7, R13, c[0x0][0x160] ; MOV R14, R12 ; IMAD.MOV.U32 R16, RZ, RZ, R10 ; IMAD.MOV.U32 R17, RZ, RZ, R11 ; IMAD.MOV.U32 R9, RZ, RZ, R7 ; MOV R12, R16 ; IMAD.MOV.U32 R13, RZ, RZ, R17 ; LDG.E R19, [R12.64] ; ISETP.GT.AND P1, PT, R19, R8, PT ; @!P1 IADD3 R6, R6, 0x1, RZ ; @!P1 IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; @!P1 IMAD.WIDE R10, R6, R11, c[0x0][0x160] ; @!P1 LDG.E R15, [R10.64] ; IADD3 R14, R14, -0x1, RZ ; IADD3 R9, R9, 0x1, RZ ; @!P1 STG.E [R10.64], R19 ; ISETP.NE.AND P2, PT, R14, RZ, PT ; @!P1 STG.E [R12.64], R15 ; IADD3 R16, P1, R12, 0x4, RZ ; IADD3.X R17, RZ, R13, RZ, P1, !PT ; @P2 BRA 0x230 ; BSYNC B1 ; @!P0 BRA 0x600 ; IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; IMAD.WIDE R10, R9, R10, c[0x0][0x160] ; IMAD.MOV.U32 R12, RZ, RZ, R10 ; MOV R13, R11 ; IMAD.MOV.U32 R10, RZ, RZ, R12 ; IMAD.MOV.U32 R11, RZ, RZ, R13 ; LDG.E R21, [R10.64] ; ISETP.GT.AND P0, PT, R21, R8, PT ; @!P0 IADD3 R6, R6, 0x1, RZ ; @!P0 MOV R13, 0x4 ; @!P0 IMAD.WIDE R12, R6, R13, c[0x0][0x160] ; @!P0 LDG.E R17, [R12.64] ; @!P0 STG.E [R12.64], R21 ; LDG.E R23, [R10.64+0x4] ; @!P0 STG.E [R10.64], R17 ; ISETP.GT.AND P1, PT, R23, R8, PT ; @!P1 IADD3 R6, R6, 0x1, RZ ; @!P1 IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; @!P1 IMAD.WIDE R14, R6, R15, c[0x0][0x160] ; @!P1 LDG.E R19, [R14.64] ; @!P1 STG.E [R14.64], R23 ; LDG.E R25, [R10.64+0x8] ; @!P1 STG.E [R10.64+0x4], R19 ; ISETP.GT.AND P0, PT, R25, R8, PT ; @!P0 IADD3 R6, R6, 0x1, RZ ; @!P0 IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; @!P0 IMAD.WIDE R12, R6, R13, c[0x0][0x160] ; @!P0 LDG.E R21, [R12.64] ; @!P0 STG.E [R12.64], R25 ; LDG.E R27, [R10.64+0xc] ; IADD3 R9, R9, 0x4, RZ ; @!P0 STG.E [R10.64+0x8], R21 ; ISETP.GT.AND P1, PT, R27, R8, PT ; @!P1 IADD3 R6, R6, 0x1, RZ ; @!P1 MOV R15, 0x4 ; @!P1 IMAD.WIDE R14, R6, R15, c[0x0][0x160] ; @!P1 LDG.E R17, [R14.64] ; ISETP.GE.AND P0, PT, R9, R0, PT ; @!P1 STG.E [R14.64], R27 ; @!P1 STG.E [R10.64+0xc], R17 ; IADD3 R12, P1, R10, 0x10, RZ ; IMAD.X R13, RZ, RZ, R11, P1 ; @!P0 BRA 0x390 ; BSYNC B0 ; IADD3 R11, R6, 0x1, RZ ; IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; LDG.E R15, [R4.64] ; IMAD.WIDE R10, R11, R8, c[0x0][0x160] ; LDG.E R13, [R10.64] ; ISETP.GT.AND P0, PT, R6.reuse, R7, PT ; BSSY B0, 0x7d0 ; IADD3 R9, R6, 0x2, RZ ; ISETP.GE.AND P1, PT, R9, R0, PT ; STG.E [R10.64], R15 ; STG.E [R4.64], R13 ; @!P0 BRA 0x7c0 ; S2R R5, SR_LANEID ; VOTEU.ANY UR6, UPT, PT ; FLO.U32 R12, UR6 ; POPC R13, UR6 ; ISETP.EQ.U32.AND P0, PT, R12, R5, PT ; @P0 ATOMG.E.ADD.STRONG.GPU PT, R13, [R2.64], R13 ; S2R R4, SR_LTMASK ; LOP3.LUT R14, R4, UR6, RZ, 0xc0, !PT ; POPC R14, R14 ; SHFL.IDX PT, R11, R13, R12, 0x1f ; IADD3 R11, R11, R14, RZ ; IMAD.WIDE R4, R11, R8, c[0x0][0x168] ; IMAD.WIDE R10, R11, R8, c[0x0][0x170] ; STG.E [R4.64], R7 ; STG.E [R10.64], R6 ; BSYNC B0 ; @P1 EXIT ; S2R R5, SR_LANEID ; VOTEU.ANY UR6, UPT, PT ; FLO.U32 R10, UR6 ; POPC R11, UR6 ; ISETP.EQ.U32.AND P0, PT, R10, R5, PT ; @P0 ATOMG.E.ADD.STRONG.GPU PT, R11, [R2.64], R11 ; S2R R12, SR_LTMASK ; LOP3.LUT R12, R12, UR6, RZ, 0xc0, !PT ; POPC R12, R12 ; SHFL.IDX PT, R7, R11, R10, 0x1f ; IMAD.IADD R7, R7, 0x1, R12 ; IMAD.WIDE R4, R7, R8, c[0x0][0x168] ; IMAD.WIDE R6, R7, R8, c[0x0][0x170] ; STG.E [R4.64], R9 ; STG.E [R6.64], R0 ; EXIT ; BRA 0x8e0; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; ..........
.file "tmpxft_000e198e_00000000-6_d6acea145810588f6f9b0fb1e58f9a1fdf48a1c4.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%d " .text .globl _Z8printArrPii .type _Z8printArrPii, @function _Z8printArrPii: .LFB2057: .cfi_startproc endbr64 testl %esi, %esi jle .L8 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %rbx movslq %esi, %rsi leaq (%rdi,%rsi,4), %r12 leaq .LC0(%rip), %rbp .L5: movl (%rbx), %edx movq %rbp, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %r12, %rbx jne .L5 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L8: .cfi_restore 3 .cfi_restore 6 .cfi_restore 12 ret .cfi_endproc .LFE2057: .size _Z8printArrPii, .-_Z8printArrPii .globl _Z33__device_stub__Z9partitionPiS_S_iPiS_S_i .type _Z33__device_stub__Z9partitionPiS_S_iPiS_S_i, @function _Z33__device_stub__Z9partitionPiS_S_iPiS_S_i: .LFB2084: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 136(%rsp), %rax subq %fs:40, %rax jne .L16 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z9partitionPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z33__device_stub__Z9partitionPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9partitionPiS_S_iPiS_S_i .globl _Z9partitionPiS_S_i .type _Z9partitionPiS_S_i, @function _Z9partitionPiS_S_i: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z33__device_stub__Z9partitionPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z9partitionPiS_S_i, .-_Z9partitionPiS_S_i .globl _Z18quickSortIterativePiii .type _Z18quickSortIterativePiii, @function _Z18quickSortIterativePiii: .LFB2058: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsp, %rbp .cfi_def_cfa_register 6 pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $72, %rsp .cfi_offset 15, -24 .cfi_offset 14, -32 .cfi_offset 13, -40 .cfi_offset 12, -48 .cfi_offset 3, -56 movq %rdi, %r13 movq %fs:40, %rax movq %rax, -56(%rbp) xorl %eax, %eax movl %edx, %r12d subl %esi, %r12d addl $1, %r12d movslq %r12d, %r12 salq $2, %r12 leaq 15(%r12), %rax movq %rax, %rdi andq $-16, %rdi andq $-4096, %rax movq %rsp, %rcx subq %rax, %rcx .L20: cmpq %rcx, %rsp je .L21 subq $4096, %rsp orq $0, 4088(%rsp) jmp .L20 .L21: movq %rdi, %rax andl $4095, %eax subq %rax, %rsp testq %rax, %rax je .L22 orq $0, -8(%rsp,%rax) .L22: leaq 3(%rsp), %rbx movq %rbx, %r8 shrq $2, %r8 andq $-4, %rbx leaq 15(%r12), %rax movq %rax, %rdi andq $-16, %rdi andq $-4096, %rax movq %rsp, %rcx subq %rax, %rcx .L23: cmpq %rcx, %rsp je .L24 subq $4096, %rsp orq $0, 4088(%rsp) jmp .L23 .L24: movq %rdi, %rax andl $4095, %eax subq %rax, %rsp testq %rax, %rax je .L25 orq $0, -8(%rsp,%rax) .L25: leaq 3(%rsp), %r14 movq %r14, %rax shrq $2, %rax andq $-4, %r14 movl %esi, 0(,%r8,4) movl %edx, 0(,%rax,4) leaq -104(%rbp), %rdi movq %r12, %rsi call cudaMalloc@PLT movl $1, %ecx movq %r12, %rdx movq %r13, %rsi movq -104(%rbp), %rdi call cudaMemcpy@PLT leaq -96(%rbp), %rdi movq %r12, %rsi call cudaMalloc@PLT movl $1, %ecx movq %r12, %rdx movq %rbx, %rsi movq -96(%rbp), %rdi call cudaMemcpy@PLT leaq -88(%rbp), %rdi movq %r12, %rsi call cudaMalloc@PLT movl $1, %ecx movq %r12, %rdx movq %r14, %rsi movq -88(%rbp), %rdi call cudaMemcpy@PLT movl $1, %ebx movl $1, %r15d movl $1, %eax leaq _ZL6d_size(%rip), %r14 jmp .L30 .L33: movl %ebx, %ecx movq -88(%rbp), %rdx movq -96(%rbp), %rsi movq -104(%rbp), %rdi call _Z33__device_stub__Z9partitionPiS_S_iPiS_S_i jmp .L26 .L27: movl $2, %ecx movq %r12, %rdx movq -104(%rbp), %rsi movq %r13, %rdi call cudaMemcpy@PLT testl %ebx, %ebx jle .L19 movl %ebx, %eax .L30: movl %eax, -68(%rbp) movl $1, -64(%rbp) movl $1, -60(%rbp) movl %r15d, -80(%rbp) movl $1, -76(%rbp) movl $0, %r9d movl $0, %r8d movq -68(%rbp), %rdx movl $1, %ecx movq -80(%rbp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L33 .L26: leaq -68(%rbp), %rdi movl $2, %r8d movl $0, %ecx movl $4, %edx movq %r14, %rsi call cudaMemcpyFromSymbol@PLT movl -68(%rbp), %ebx cmpl $1023, %ebx jle .L27 testl $1023, %ebx setne %r15b movzbl %r15b, %r15d leal 1023(%rbx), %eax testl %ebx, %ebx cmovns %ebx, %eax sarl $10, %eax addl %eax, %r15d movl $2, %ecx movq %r12, %rdx movq -104(%rbp), %rsi movq %r13, %rdi call cudaMemcpy@PLT movl $1024, %eax jmp .L30 .L19: movq -56(%rbp), %rax subq %fs:40, %rax jne .L34 leaq -40(%rbp), %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 popq %rbp .cfi_remember_state .cfi_def_cfa 7, 8 ret .L34: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size _Z18quickSortIterativePiii, .-_Z18quickSortIterativePiii .section .rodata.str1.1 .LC1: .string "r" .LC2: .string "%d" .LC3: .string "\nInput length = %d\n" .LC4: .string "\n" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC5: .string "\nSolution wrong Expecting : %d but got : %d\n" .section .rodata.str1.1 .LC6: .string "\nSolution is Correct !!!\n" .LC8: .string "\nTime : %f s \n" .text .globl main .type main, @function main: .LFB2059: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $40, %rsp .cfi_def_cfa_offset 96 movq %rsi, %rbp movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax movq 8(%rsi), %rdi leaq .LC1(%rip), %rsi call fopen@PLT movq %rax, %r13 leaq 20(%rsp), %rdx leaq .LC2(%rip), %rsi movq %rax, %rdi movl $0, %eax call __isoc23_fscanf@PLT movl 20(%rsp), %edx leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movslq 20(%rsp), %rdi movabsq $2305843009213693950, %rax cmpq %rdi, %rax jb .L36 salq $2, %rdi call _Znam@PLT movq %rax, %r12 movq %rax, %r14 movl $0, %ebx leaq .LC2(%rip), %r15 cmpl $0, 20(%rsp) jle .L38 .L40: movq %r14, %rdx movq %r15, %rsi movq %r13, %rdi movl $0, %eax call __isoc23_fscanf@PLT addl $1, %ebx addq $4, %r14 cmpl %ebx, 20(%rsp) jg .L40 .L38: call clock@PLT movq %rax, (%rsp) movl 20(%rsp), %edx movl $0, %esi movq %r12, %rdi call _Z18quickSortIterativePiii call clock@PLT movq %rax, 8(%rsp) movq 16(%rbp), %rdi leaq .LC1(%rip), %rsi call fopen@PLT movq %rax, %r14 leaq 20(%rsp), %rdx leaq .LC2(%rip), %rsi movq %rax, %rdi movl $0, %eax call __isoc23_fscanf@PLT movslq 20(%rsp), %rdi movabsq $2305843009213693950, %rax cmpq %rdi, %rax jb .L41 salq $2, %rdi call _Znam@PLT movq %rax, %r15 movq %rax, %rbp movl $0, %ebx cmpl $0, 20(%rsp) jle .L43 .L45: movq %rbp, %rdx leaq .LC2(%rip), %rsi movq %r14, %rdi movl $0, %eax call __isoc23_fscanf@PLT addl $1, %ebx addq $4, %rbp cmpl %ebx, 20(%rsp) jg .L45 .L43: leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT cmpl $0, 20(%rsp) jle .L46 movl $0, %ebx movl $0, %eax leaq .LC5(%rip), %rbp jmp .L48 .L36: movq 24(%rsp), %rax subq %fs:40, %rax je .L39 call __stack_chk_fail@PLT .L39: call __cxa_throw_bad_array_new_length@PLT .L41: movq 24(%rsp), %rax subq %fs:40, %rax je .L44 call __stack_chk_fail@PLT .L44: call __cxa_throw_bad_array_new_length@PLT .L47: addq $1, %rbx cmpl %ebx, 20(%rsp) jle .L57 .L48: movl (%r15,%rbx,4), %edx cmpl 4(%r12,%rbx,4), %edx je .L47 movl (%r12,%rbx,4), %ecx movq %rbp, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %eax jmp .L47 .L57: testl %eax, %eax je .L46 .L49: movq %r14, %rdi call fclose@PLT movq %r13, %rdi call fclose@PLT movq 24(%rsp), %rax subq %fs:40, %rax jne .L58 movl $0, %eax addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L46: .cfi_restore_state leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl 8(%rsp), %eax movl (%rsp), %ecx subl %ecx, %eax pxor %xmm0, %xmm0 cvtsi2sdl %eax, %xmm0 divsd .LC7(%rip), %xmm0 leaq .LC8(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT jmp .L49 .L58: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size main, .-main .section .rodata.str1.1 .LC9: .string "_Z9partitionPiS_S_i" .LC10: .string "d_size" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC9(%rip), %rdx movq %rdx, %rcx leaq _Z9partitionPiS_S_i(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC10(%rip), %rdx movq %rdx, %rcx leaq _ZL6d_size(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL6d_size .comm _ZL6d_size,4,4 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC7: .long 0 .long 1093567616 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9partitionPiS_S_i ; -- Begin function _Z9partitionPiS_S_i .globl _Z9partitionPiS_S_i .p2align 8 .type _Z9partitionPiS_S_i,@function _Z9partitionPiS_S_i: ; @_Z9partitionPiS_S_i ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s4, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] v_mov_b32_e32 v0, 0 s_getpc_b64 s[2:3] s_add_u32 s2, s2, d_size@rel32@lo+4 s_addc_u32 s3, s3, d_size@rel32@hi+12 global_store_b32 v0, v0, s[2:3] s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s4, v1 s_cbranch_execz .LBB0_15 ; %bb.1: s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x10 s_load_b128 s[4:7], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s1, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v3, vcc_lo, s2, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo v_add_co_u32 v1, vcc_lo, s6, v1 v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo global_load_b32 v0, v[3:4], off global_load_b32 v2, v[1:2], off s_waitcnt vmcnt(1) v_ashrrev_i32_e32 v1, 31, v0 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v4, -1, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 2, v[0:1] v_add_co_u32 v6, vcc_lo, s4, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo v_cmpx_lt_i32_e64 v2, v0 s_cbranch_execz .LBB0_7 ; %bb.2: ; %.lr.ph.preheader global_load_b32 v1, v[6:7], off v_ashrrev_i32_e32 v3, 31, v2 s_mov_b32 s8, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b64 v[8:9], 2, v[2:3] v_mov_b32_e32 v3, v2 v_add_co_u32 v8, vcc_lo, s4, v8 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo s_set_inst_prefetch_distance 0x1 s_branch .LBB0_4 .p2align 6 .LBB0_3: ; in Loop: Header=BB0_4 Depth=1 s_or_b32 exec_lo, exec_lo, s0 v_add_nc_u32_e32 v3, 1, v3 v_add_co_u32 v8, s0, v8, 4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v9, s0, 0, v9, s0 v_cmp_ge_i32_e32 vcc_lo, v3, v0 s_or_b32 s8, vcc_lo, s8 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s8 s_cbranch_execz .LBB0_6 .LBB0_4: ; %.lr.ph ; =>This Inner Loop Header: Depth=1 global_load_b32 v10, v[8:9], off s_mov_b32 s0, exec_lo s_waitcnt vmcnt(0) v_cmpx_le_i32_e64 v10, v1 s_cbranch_execz .LBB0_3 ; %bb.5: ; in Loop: Header=BB0_4 Depth=1 v_add_nc_u32_e32 v4, 1, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v5, 31, v4 v_lshlrev_b64 v[11:12], 2, v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v11, vcc_lo, s4, v11 v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo global_load_b32 v5, v[11:12], off global_store_b32 v[11:12], v10, off s_waitcnt vmcnt(0) global_store_b32 v[8:9], v5, off s_branch .LBB0_3 .LBB0_6: ; %Flow72 s_set_inst_prefetch_distance 0x2 s_or_b32 exec_lo, exec_lo, s8 .LBB0_7: ; %Flow73 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s1 v_ashrrev_i32_e32 v5, 31, v4 s_mov_b32 s0, exec_lo v_lshlrev_b64 v[8:9], 2, v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v8, vcc_lo, s4, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo s_clause 0x1 global_load_b32 v1, v[6:7], off global_load_b32 v3, v[8:9], off offset:4 s_waitcnt vmcnt(1) global_store_b32 v[8:9], v1, off offset:4 s_waitcnt vmcnt(0) global_store_b32 v[6:7], v3, off v_cmpx_gt_i32_e64 v4, v2 s_cbranch_execz .LBB0_11 ; %bb.8: s_mov_b32 s4, exec_lo s_mov_b32 s1, exec_lo v_mbcnt_lo_u32_b32 v1, s4, 0 ; implicit-def: $vgpr3 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v1 s_cbranch_execz .LBB0_10 ; %bb.9: s_bcnt1_i32_b32 s8, s4 v_mov_b32_e32 v3, 0 v_mov_b32_e32 v5, s8 s_getpc_b64 s[4:5] s_add_u32 s4, s4, d_size@rel32@lo+4 s_addc_u32 s5, s5, d_size@rel32@hi+12 global_atomic_add_u32 v3, v3, v5, s[4:5] glc .LBB0_10: s_or_b32 exec_lo, exec_lo, s1 s_waitcnt vmcnt(0) v_readfirstlane_b32 s1, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v5, s1, v1 v_ashrrev_i32_e32 v6, 31, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[5:6], 2, v[5:6] v_add_co_u32 v7, vcc_lo, s6, v5 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo v_add_co_u32 v5, vcc_lo, s2, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo global_store_b32 v[7:8], v2, off global_store_b32 v[5:6], v4, off .LBB0_11: ; %Flow71 s_or_b32 exec_lo, exec_lo, s0 v_add_nc_u32_e32 v1, 2, v4 s_delay_alu instid0(VALU_DEP_1) v_cmp_lt_i32_e32 vcc_lo, v1, v0 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_15 ; %bb.12: s_mov_b32 s1, exec_lo s_mov_b32 s0, exec_lo v_mbcnt_lo_u32_b32 v2, s1, 0 ; implicit-def: $vgpr3 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB0_14 ; %bb.13: s_bcnt1_i32_b32 s1, s1 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s1 s_getpc_b64 s[4:5] s_add_u32 s4, s4, d_size@rel32@lo+4 s_addc_u32 s5, s5, d_size@rel32@hi+12 global_atomic_add_u32 v3, v3, v4, s[4:5] glc .LBB0_14: s_or_b32 exec_lo, exec_lo, s0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s0, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v2, s0, v2 v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[2:3] v_add_co_u32 v4, vcc_lo, s6, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_store_b32 v[4:5], v1, off global_store_b32 v[2:3], v0, off .LBB0_15: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9partitionPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 13 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9partitionPiS_S_i, .Lfunc_end0-_Z9partitionPiS_S_i ; -- End function .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 892 ; NumSgprs: 18 ; NumVgprs: 13 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 2 ; VGPRBlocks: 1 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 13 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .protected d_size ; @d_size .type d_size,@object .section .bss,"aw",@nobits .globl d_size .p2align 2, 0x0 d_size: .long 0 ; 0x0 .size d_size, 4 .type __hip_cuid_,@object ; @__hip_cuid_ .globl __hip_cuid_ __hip_cuid_: .byte 0 ; 0x0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym d_size .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9partitionPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z9partitionPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 13 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
.text .file "d6acea145810588f6f9b0fb1e58f9a1fdf48a1c4.hip" .globl _Z8printArrPii # -- Begin function _Z8printArrPii .p2align 4, 0x90 .type _Z8printArrPii,@function _Z8printArrPii: # @_Z8printArrPii .cfi_startproc # %bb.0: testl %esi, %esi jle .LBB0_4 # %bb.1: # %.lr.ph.preheader pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rdi, %rbx movl %esi, %r14d xorl %r15d, %r15d .p2align 4, 0x90 .LBB0_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movl (%rbx,%r15,4), %esi movl $.L.str, %edi xorl %eax, %eax callq printf incq %r15 cmpq %r15, %r14 jne .LBB0_2 # %bb.3: popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 .cfi_restore %rbx .cfi_restore %r14 .cfi_restore %r15 .LBB0_4: # %._crit_edge retq .Lfunc_end0: .size _Z8printArrPii, .Lfunc_end0-_Z8printArrPii .cfi_endproc # -- End function .globl _Z24__device_stub__partitionPiS_S_i # -- Begin function _Z24__device_stub__partitionPiS_S_i .p2align 4, 0x90 .type _Z24__device_stub__partitionPiS_S_i,@function _Z24__device_stub__partitionPiS_S_i: # @_Z24__device_stub__partitionPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9partitionPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end1: .size _Z24__device_stub__partitionPiS_S_i, .Lfunc_end1-_Z24__device_stub__partitionPiS_S_i .cfi_endproc # -- End function .globl _Z18quickSortIterativePiii # -- Begin function _Z18quickSortIterativePiii .p2align 4, 0x90 .type _Z18quickSortIterativePiii,@function _Z18quickSortIterativePiii: # @_Z18quickSortIterativePiii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset %rbp, -16 movq %rsp, %rbp .cfi_def_cfa_register %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $136, %rsp .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 movq %rdi, %r12 movl %edx, %eax subl %esi, %eax leal 1(%rax), %ecx leaq 15(,%rcx,4), %rcx andq $-16, %rcx movq %rsp, %r13 subq %rcx, %r13 movq %r13, %rsp movq %rsp, %r15 subq %rcx, %r15 movq %r15, %rsp movl %esi, (%r13) movl %edx, (%r15) cltq leaq 4(,%rax,4), %r14 leaq -48(%rbp), %rdi movq %r14, %rsi callq hipMalloc movq -48(%rbp), %rdi movl $1, %ebx movq %r12, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq -72(%rbp), %rdi movq %r14, %rsi callq hipMalloc movq -72(%rbp), %rdi movq %r13, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy leaq -64(%rbp), %rdi movq %r14, %rsi callq hipMalloc movq -64(%rbp), %rdi movq %r15, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movl $1, %r15d movl $1, %r13d jmp .LBB2_1 .p2align 4, 0x90 .LBB2_5: # in Loop: Header=BB2_1 Depth=1 movq -48(%rbp), %rsi movq %r12, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy testl %r13d, %r13d jle .LBB2_6 .LBB2_1: # =>This Inner Loop Header: Depth=1 movl %r15d, %edi movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi movl %ebx, %edx orq %rax, %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_3 # %bb.2: # in Loop: Header=BB2_1 Depth=1 movq -48(%rbp), %rax movq -72(%rbp), %rcx movq -64(%rbp), %rdx movq %rax, -144(%rbp) movq %rcx, -136(%rbp) movq %rdx, -128(%rbp) movl %r13d, -52(%rbp) leaq -144(%rbp), %rax movq %rax, -176(%rbp) leaq -136(%rbp), %rax movq %rax, -168(%rbp) leaq -128(%rbp), %rax movq %rax, -160(%rbp) leaq -52(%rbp), %rax movq %rax, -152(%rbp) leaq -120(%rbp), %rdi leaq -104(%rbp), %rsi leaq -88(%rbp), %rdx leaq -80(%rbp), %rcx callq __hipPopCallConfiguration movq -120(%rbp), %rsi movl -112(%rbp), %edx movq -104(%rbp), %rcx movl -96(%rbp), %r8d movl $_Z9partitionPiS_S_i, %edi leaq -176(%rbp), %r9 pushq -80(%rbp) pushq -88(%rbp) callq hipLaunchKernel addq $16, %rsp .LBB2_3: # in Loop: Header=BB2_1 Depth=1 movl $d_size, %esi movl $4, %edx leaq -176(%rbp), %rdi xorl %ecx, %ecx movl $2, %r8d callq hipMemcpyFromSymbol movl -176(%rbp), %r13d movl %r13d, %ebx cmpl $1024, %r13d # imm = 0x400 jl .LBB2_5 # %bb.4: # in Loop: Header=BB2_1 Depth=1 movl %r13d, %r15d shrl $10, %r15d movl %r13d, %eax andl $1023, %eax # imm = 0x3FF cmpl $1, %eax sbbl $-1, %r15d movl $1024, %ebx # imm = 0x400 jmp .LBB2_5 .LBB2_6: leaq -40(%rbp), %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 popq %rbp .cfi_def_cfa %rsp, 8 retq .Lfunc_end2: .size _Z18quickSortIterativePiii, .Lfunc_end2-_Z18quickSortIterativePiii .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI3_0: .quad 0x412e848000000000 # double 1.0E+6 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %r12 movq 8(%rsi), %rdi movl $.L.str.1, %esi callq fopen movq %rax, %rbx leaq 4(%rsp), %rdx movl $.L.str.2, %esi movq %rax, %rdi xorl %eax, %eax callq __isoc23_fscanf movl 4(%rsp), %esi movl $.L.str.3, %edi xorl %eax, %eax callq printf movslq 4(%rsp), %r15 leaq (,%r15,4), %rdi testq %r15, %r15 movq $-1, %rbp cmovsq %rbp, %rdi callq _Znam movq %rax, %r14 testq %r15, %r15 jle .LBB3_3 # %bb.1: # %.lr.ph.preheader movq %r14, %r15 xorl %r13d, %r13d .p2align 4, 0x90 .LBB3_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movl $.L.str.2, %esi movq %rbx, %rdi movq %r15, %rdx xorl %eax, %eax callq __isoc23_fscanf incq %r13 movslq 4(%rsp), %rax addq $4, %r15 cmpq %rax, %r13 jl .LBB3_2 .LBB3_3: # %._crit_edge callq clock movq %rax, 16(%rsp) # 8-byte Spill movl 4(%rsp), %edx movq %r14, %rdi xorl %esi, %esi callq _Z18quickSortIterativePiii callq clock movq %rax, 8(%rsp) # 8-byte Spill movq 16(%r12), %rdi movl $.L.str.1, %esi callq fopen movq %rax, %r12 leaq 4(%rsp), %rdx movl $.L.str.2, %esi movq %rax, %rdi xorl %eax, %eax callq __isoc23_fscanf movslq 4(%rsp), %r13 leaq (,%r13,4), %rdi testq %r13, %r13 cmovsq %rbp, %rdi callq _Znam movq %rax, %r15 testq %r13, %r13 jle .LBB3_6 # %bb.4: # %.lr.ph36.preheader movq %r15, %rbp xorl %r13d, %r13d .p2align 4, 0x90 .LBB3_5: # %.lr.ph36 # =>This Inner Loop Header: Depth=1 movl $.L.str.2, %esi movq %r12, %rdi movq %rbp, %rdx xorl %eax, %eax callq __isoc23_fscanf incq %r13 movslq 4(%rsp), %rax addq $4, %rbp cmpq %rax, %r13 jl .LBB3_5 .LBB3_6: # %._crit_edge37 movl $10, %edi callq putchar@PLT cmpl $0, 4(%rsp) jle .LBB3_12 # %bb.7: # %.lr.ph41.preheader xorl %ebp, %ebp xorl %eax, %eax jmp .LBB3_8 .p2align 4, 0x90 .LBB3_10: # in Loop: Header=BB3_8 Depth=1 incq %rbp movslq 4(%rsp), %rcx cmpq %rcx, %rbp jge .LBB3_11 .LBB3_8: # %.lr.ph41 # =>This Inner Loop Header: Depth=1 movl (%r15,%rbp,4), %esi cmpl 4(%r14,%rbp,4), %esi je .LBB3_10 # %bb.9: # in Loop: Header=BB3_8 Depth=1 movl (%r14,%rbp,4), %edx movl $.L.str.5, %edi xorl %eax, %eax callq printf movl $1, %eax jmp .LBB3_10 .LBB3_11: # %._crit_edge42.loopexit testl %eax, %eax jne .LBB3_13 .LBB3_12: # %.critedge movl $.Lstr, %edi callq puts@PLT movq 8(%rsp), %rax # 8-byte Reload subl 16(%rsp), %eax # 4-byte Folded Reload cvtsi2sd %eax, %xmm0 divsd .LCPI3_0(%rip), %xmm0 movl $.L.str.7, %edi movb $1, %al callq printf .LBB3_13: movq %r12, %rdi callq fclose movq %rbx, %rdi callq fclose xorl %eax, %eax addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9partitionPiS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $0, 8(%rsp) movl $0, (%rsp) movl $d_size, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movl $4, %r9d movq %rbx, %rdi xorl %r8d, %r8d callq __hipRegisterVar movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%d " .size .L.str, 4 .type d_size,@object # @d_size .local d_size .comm d_size,4,4 .type _Z9partitionPiS_S_i,@object # @_Z9partitionPiS_S_i .section .rodata,"a",@progbits .globl _Z9partitionPiS_S_i .p2align 3, 0x0 _Z9partitionPiS_S_i: .quad _Z24__device_stub__partitionPiS_S_i .size _Z9partitionPiS_S_i, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "r" .size .L.str.1, 2 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "%d" .size .L.str.2, 3 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "\nInput length = %d\n" .size .L.str.3, 20 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "\nSolution wrong Expecting : %d but got : %d\n" .size .L.str.5, 45 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "\nTime : %f s \n" .size .L.str.7, 16 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9partitionPiS_S_i" .size .L__unnamed_1, 20 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "d_size" .size .L__unnamed_2, 7 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "\nSolution is Correct !!!" .size .Lstr, 25 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__partitionPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym d_size .addrsig_sym _Z9partitionPiS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
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